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0 20 8 2 6 ? by semikron b 14 C 42
0 20 8 2 6 ? by semikron b 14 C 43 fig.2 dimensions (in mm) and connections of the skhi 23 input connector = 14 pin flat cable according to din 41651 output connector = molex 41791 series (mates with 41695 crimp terminals 7258)
0 20 82 6 ? by semikron b 14 C 44 semidriver ? skhi 23/12 semidriver ? skhi 23/17 medium power double igbt driver overview the new intelligent double igbt driver, skhi 23 respecti- vely skhi 23/17 is a standard driver for all power igbts in the market. skhi 23/12 drives all igbts with v ce up to 1200 v. skhi 23/17 drives all igbts with v ce up to 1700 v. to protect the driver against moisture and dust it is coated with var- nish. the adaption of the drivers to the application has been improved by using pins to changing several parameters and functions. the connections to the igbts can be made by using only one molex connector with 12 pins or by using 2 separate connectors with 5 pins for each igbt. the high power outputs capability was designed to switch high current double or single modules (or paralleled igbts). the output buffers have been improved to make it possible to switch up to 200 a igbt modules at frequencies up to 20 khz. a new function has been added to the short circuit protecti- on circuitry (soft turn off), this automatically increases the igbt turn off time and hence reduces the dc voltage overshoot enabling the use of higher dc-bus voltages. this means an increase in the final output power. integrated dc/dc converters with high galvanic isolation (4 kv) ensures that the user is protected from the high voltage (secondary side). the power supply for the driver may be the same as used in the control board (0/+15 v) without the requirement of isolation. all information that is transmitted between input and output uses ferrite transformers, resulting in high dv/dt immunity (75 kv/ m s). the driver input stages are connected directly to the control board output and due to different control board operating voltages, the input circuit includes a user voltage level selector (+15 v or +5 v). in the following only the designa- tion skhi 23 is used. this is valid for both driver versions. any unique features will be marked as skhi 23/12 (v ce = 1200 v) or skhi 23/17 (v ce = 1700 v) respectively. a. features and configuration of the driver a) a short description is given below. for detailed informa- tion, please refer to section b. the following is valid for both channels (top and bottom) unless specified. b) the skhi 23 has an input level selector circuit for two different levels. it is preset for cmos (15 v) level, but can be changed by the user to hcmos (5 v) level by solder bridging between pins j1 and k1. for long input cables, we do not recommend the 5 v level due to possible disturbances emitted by the power side. c) an interlock circuit prevents the two igbts of the half bridge to switch-on at the same time, and a ,,dead- time can be adjusted by putting additional resistors between pins j3 and k3 (r td1 ) and pins j4 and k4 (r td2 ). therefore it will be possible to reduce the dead- time t td (see also table 3). the interlocking may also be inhibit by solder bridging between pins j5 and k5 to obtain two independent drivers. d) the error memory blocks the transmission of all turn-on signals to the igbt if either a short circuit or malfunction of v s is detected, a signal is sent to the external control board through an open collector transi- stor. it is preset to ,,high-logic but can be set to ,,low-lo- gic (error). e) the v s monitor ensures that v s actual is not below 13 v. f) with a ferrite transformer the information be- tween primary and secondary may flow in both directi- ons and high levels of dv/dt and isolation are obtained. g) a high frequency dc/dc converter avoids the requirement of external isolated power supplies to ob- tain the necessary gate voltage. an isolated ferrite transformer in half-bridge configuration supplies the necessary power to the gate of the igbt. with this feature, we can use the same power supply used in the external control circuit, even if we are using more than one skhi 23, e.g. in three-phase configurations. h) short circuit protection is provided by measuring the collector-emitter voltage with a v ce monitoring circuit. an additional circuit detects the short circuit after a delay (adjusted with r ce (this value can only be reduced) and c ce (this value can only be increased) and decreases the turn off speed (adjusted by r goff-sc ) of the igbt. soft turn-off under fault conditions is necessary as it reduces the voltage overshoot and allows for a faster turn off during normal operation. i) the output buffer is responsible for providing the correct current to the gate of the igbt. if these signals do not have sufficient power, the igbt will not switch properly, and additional losses or even the destruction of the igbt may occur. according to the application (switching frequency and gate charge of the igbt) the equivalent value of r gon and the r goff must be matched to the optimum value. this can be done by putting additional parallel resistors r gon , r goff with those alrea- dy on the board. if only one igbt is to be used, (instead of paralleled igbts) only one cable could be connected between driver and gate by solder bridging between the pins j12 and k12 (top) as well as between j19 and k19 (bottom). j) fig. 1 shows a simplified block diagram of the skhi 23 driver. some preliminary remarks will help the under- standing: stabilised +15 v must be present between pins x1.8,9 (v s ) and x1.10,11 ( ^ ); an input signal (on or off command to the igbts) from the control system is
0 2 0 8 2 6 ? by semikron b 14 C 45
02 08 2 6 ? by semikron b 14 C 46 table 1 pins; factory adjustment and possibilities of adjustments function pin description adjustment by factory possibilities of functions input level selector j1 / k1 not bridged t 15v cmos soldering bridged t 5v hcmos error - logic j2 / k2 not bridged t high-aktiv soldering bridged t low-aktiv interlock time j3 / k3 (top r td1 ) j4 / k4 (bot r td2 ) not equiped t max. t td = 10 m s adjustment according table 3 interlock of top and bottom j5 / k5 not bridged t interlock activ soldering bridged t no interlock r ce top j6 / k6 skhi 23/12 not equiped t r ce = 18 k w skhi 23/17 not equiped t r ce = 36 k w adjustment according tab. 4a/b c ce top j7 / k7 skhi 23/12 not equiped t c ce = 330 pf skhi 23/17 not equiped t c ce = 470 pf adjustment according tab. 4a/b r gon top j8 / k8 skhi 23/12 not equiped t r gon = 22 w skhi 23/17 not equiped t r gon = 22 w adjustment according tab. 4a/b r goff top j9 / k9 skhi 23/12 not equiped t r goff = 22 w skhi 23/17 not equiped t r goff = 22 w adjustment according tab. 4a/b ir goff top j10 / k10 equiped with ir goff = 0 w adjustment according tab. 4a/b r goffsc top j11 / k11 equiped with t r goffsc = 22 w top: one igbt/ paralleled igbts j12 / k12 not bridged t 2 cables to gates soldering bridged t 1 cable to gate r ce bot j13 / k13 skhi 23/12 not equiped t r ce = 18 k w skhi 23/17 not equiped t r ce = 36 k w adjustment according tab. 4a/b c ce bot j14 / k14 skhi 23/12 not equiped t c ce = 330 pf skhi 23/17 not equiped t c ce = 470 pf adjustment according tab. 4a/b r gon bot j15 / k15 skhi 23/12 not equiped t r gon = 22 w skhi 23/17 not equiped t r gon = 22 w adjustment according tab. 4a/b r goff bot j16 / k16 skhi 23/12 not equiped t r goff = 22 w skhi 23/17 not equiped t r goff = 22 w adjustment according tab. 4a/b ir goff bot j17 / k17 equiped with ir goff = 0 w adjustment according tab. 4a/b r goffsc bot j18 / k18 equiped with t r goffsc = 22 w bot: one igbt/ paralleled igbts j19 / k19 not bridged t 2 cables to gates soldering bridged t 1 cable to gate shield j20 / k20 not bridged t no screening soldering bridged t screening to gnd
0 20 8 2 6 ? by semikron b 14 C 47
0 20 8 2 6 ? by semikron b 14 C 48 the v cestat must be adjusted to remain above v cesat in normal operation (igbt in full saturation). to avoid a false failure indication when the igbt just starts to conduct (v cesat value is still too high) some decay time must be provided for the v ceref . as the v ce signal is inter- nally limited at 10 v, the decay time of v ceref must reach this level after v ce or a failure indication will occur (see fig.6, curve 1). a t min is defined as function of v cestat and t to find out the best choice for r ce and v ce (see fig.6, curve 2). the time the igbt reaches to the 10 v (represented by a " o in fig. 6) depends on the igbt itself and r gon used. the r ce and c ce values can be found from fig. 7a and 7b for skhi 23/12 and from fig. 7c and 7d for skhi 23/17 by taking the v cestat and t min as input values with following remarks: r ce > 10 k w c ce < 2,7 nf attention!: if this function is not used, for example during the experimental phase, the v ce monitoring must be con- nected with the emitter output to avoid possible fault indication and consequent gate signal blocking. 10. r gon , r goff these two resistors are responsible for the switching speed of each igbt. as an igbt has input capacitance (varying during the switching time) which must be charged and discharged, both resistors will dictate what time must be taken to do this. the final value of resistance is difficult to predict, because it depends on many parameters, as fol- lows: dc-link voltage stray inductance of the circuit switching frequency type of igbt the driver is delivered with two r g resistors (22 w ) on the board. this value can be reduced to use the driver with bigger modules or higher frequencies, by putting additional resistors in parallel. the outputs g on and g off were previewed to connect the driver with more than one igbt (paralleling). in that case adjustments for skhi 23/12 1 10 024681012141618 fig.7a v cestat as function of r ce fig.7b t min as function of r ce and c ce fig.7c v cestat as function of r ce fig.7d t min as function of r ce and c ce 1 10 0 4 8 12 16 20 24 28 32 36 0,1 1 10 100 0 4 8 12 16 20 24 28 32 36 adjustments for skhi 23/17 v cestat [v] r ce [k w ] v cestat [v] t min [ m s] c ce 1 nf 470 pf 330 pf 0,1 1 10 024681012141618 r ce [k w ] r ce [k w ] t min [ m s] c ce 1 nf 470 pf 330 pf r ce [k w ]
0 2 0 8 2 6 ? by semikron b 14 C 49
0 20 8 2 6 ? by semikron b 14 C 50
0 20 8 2 6 ? by semikron b 14 C 51

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