GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg1 of 7 normally ? off silicon carbide junction transistor features package ? 250 c maximum operating temperature ? gate oxide free sic switch ? exceptional safe operating area ? excellent gain linearity ? temperature independent switching performance ? low output capacitance ? positive temperature coefficient of r ds,on ? suitable for connecting an anti-parallel diode advantages applications ? compatible with si mosfet/igbt gate drive ics ? > 20 s short-circuit withstand capability ? lowest-in-class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? ? hybrid electric vehicles (hev) ? solar inverters ? switched-mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives table of contents section i: absolute maximum ratings ........................................................................................... ............... 1 ? section ii: static elect rical characteristics ................................................................................. .................. 2 ? section iii: dynamic elect rical charac teristics ............................................................................... ............. 2 ? section iv: figures ........................................................................................................... ............................... 3 ? section v: GA10JT12-CAL gate drive theory of operation ....................................................................... 5 ? section vi: mechani cal parameters ............................................................................................. .................. 6 ? section vii: chip dimensions .................................................................................................. ....................... 6 ? section viii: spice model para meters .......................................................................................... ................ 8 ? section i: absolute maximum ratings parameter symbol conditions value unit notes drain ? source voltage v ds v gs = 0 v 1200 v continuous drain current i d t c = 25c 25 a continuous drain current i d t c = 155c 10 a continuous gate current i g 1.3 a turn-off safe operating area rbsoa t vj = 250 o c, clamped inductive load i d,max = 10 @ v ds v dsmax a short circuit safe operating area scsoa t vj = 250 o c, i g = 1 a, v ds = 800 v, non repetitive >20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v power dissipation p tot t c = 25 c / 155 c, t p > 100 ms 170 / 22 w storage temperature t stg -55 to 250 c s d g v ds = 1200 v r ds(on) = 120 m i d (tc = 25c) = 25 a h fe (tc = 25c) = 80
GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg2 of 7 section ii: static electrical characteristics a: on state b: off state section iii: dynamic electrical characteristics parameter symbol conditions value unit notes min. typical max. drain ? source on resistance r ds(on) i d = 10 a, t j = 25 c i d = 10 a, t j = 125 c i d = 10 a, t j = 175 c 120 164 208 m ? fig. 5 gate on voltage v gs,on i d = 10 a, v ds = 30 v, t j = 25 c i d = 10 a, v ds = 30 v, t j = 175 c 3.5 3.2 v fig. 4 dc current gain h fe v ds = 5 v, i d = 10 a, t j = 25 c v ds = 5 v, i d = 10 a, t j = 125 c v ds = 5 v, i d = 10 a, t j = 175 c 80 56 50 ? fig. 5 drain leakage current i dss v ds = 1200 v, v gs = 0 v, t j = 25 c v ds = 1200 v, v gs = 0 v, t j = 125 c v ds = 1200 v, v gs = 0 v, t j = 175 c 1 1 10 a fig. 6 gate leakage current i sg v sg = 20 v, t j = 25 c 20 na parameter symbol conditions value unit notes min. typical max. input capacitance c iss v gs = 0 v, v ds = 800 v, f = 1 mhz 1403 pf fig. 9 reverse transfer/output capacitance c rss /c oss v ds = 800 v, f = 1 mhz 30 pf fig. 9 output capacitance stored energy e oss v gs = 0 v, v ds = 800 v, f = 1 mhz 9 j fig. 10 effective output capacitance, time related c oss,tr i d = constant, v gs = 0 v, v ds = 0?800 v 55 pf effective output capacitance, energy related c oss,er v gs = 0 v, v ds = 0?800 v 40 pf gate-source charge q gs v gs = -5?3 v 11 nc gate-drain charge q gd v gs = 0 v, v ds = 0?800 v 44 nc gate charge - total q g 55 nc internal gate resistance ? zero bias r g(int-zero) f = 1 mhz, v ac = 50 mv, v ds = 0 v, v gs = 0 v, t j = 175 oc 2.6 ? internal gate resistance ? on r g ( int-on ) v gs > 2.5 v, v ds = 0 v, t j = 175 oc 0.19 ?
GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg3 of 7 section iv: figures figure 1: typical output characteristics at 25 c figure 2: typical output characteristics at 125 c figure 3: typical output characteristics at 175 c figure 4: drain-source voltage vs. gate current figure 5: dc current gain and normalized on-resistance vs. temperature figure 6: dc current gain vs. drain current
GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg4 of 7 figure 7: typical transfer characteristics figure 8: typical blocking characteristics figure 9: input, output, and reverse transfer capacitance figure 10: output capacitance stored energy
GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg5 of 7 section v: GA10JT12-CAL gate drive theory of operation the sjt transistor is a current controlled transistor which requires a positive gate curr ent for turn-on as well as to remain i n on-state. an ideal gate current waveform for ultra-fast switching of the sjt, while maintaining low gate drive losses, is shown in figure 11. figure 11: idealized gate current waveform a: gate currents, i g,pk /-i g,pk and voltages during turn-on and turn-off an sjt is rapidly switched from its blocking state to on-state, when the necessary gate charge, q g , for turn-on is supplied by a burst of high gate current, i g,on , until the gate-source capacitance, c gs , and gate-drain capacitance, c gd , are fully charged. , as an example, an i g,pon 2.5 a is required to achieve a 18 ns v ds fall time for a 800 v switching transition, due to the gate-drain charge, q gd of 44 nc for the GA10JT12-CAL. the i g,pon pulse should ideally terminate, when the drain volt age falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-stat e. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the to-247 package and drive circuit. a voltage developed ac ross the parasitic inductance in the source path, l s , can de-bias the gate-source junction, when high drain currents begin to flow through the device. the applied gate voltage should be maintained high enough, above the v gs,on (see figure 7) level to counter these effects. a high negative peak current, -i g,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. while sati sfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn-off transition. b: steady on-state after the device is turned on, i g may be advantageously lowered to i g,steady for reducing unnecessary gate drive losses. the i g,steady is determined by noting the dc current gain, h fe , of the device from figures 5 and 6. the desired i g,steady is determined by the peak device junction temperature t j during operation, drain current i d , dc current gain h fe , and a 50 % safety margin to ensure operating the device in the satu ration region with low on-state voltage drop by the equation: , , 1.5
GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg6 of 7 section vi: mechanical parameters raster size 2.10 x 2.10 mm 2 83 x 83 mil 2 a rea total / active 4.41/3.31 mm 2 6836/5134 mil 2 thickness 360 m 14 mil wafer size 100 mm 3937 mil flat position 0 deg 0 deg passivation frontside polyimide pad metal (anode) 4000 nm al backside metal (cathode) 400 nm ni + 200 nm au -system die bond electrically conductive glue or solder wire bond al 10 mil (source) al 3 mil (gate) reject ink dot size 0.3 mm recommended storage environment store in original container, in dry nitrogen, < 6 months at an ambient temperature of 23 c section vii: chip dimensions mm mil die a 2.10 83 b 2.10 83 source wirebondable c 1.47 58 d 1.52 60 e 0.17 7 f 0.40 16 gate wirebondable g 0.30 12 h 0.30 12 note 1. controlled dimension is inch. di mension in bracket is millimeter. 2. dimensions do not include end fl ash, mold flash, material protrusions
GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg7 of 7 revision history date revision comments supersedes 2014/09/12 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specificat ions and data in this document without noti ce. genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or i mplied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic cont rol and weapons systems, nor in applications where their failure may result in death , personal injury and/or property damage.
GA10JT12-CAL sept 2014 http://www.genesicsemi.com/high-temperatur e-sic/high-temperature-sic-bare-die/ pg1 of 1 section viii: spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website (http://www.genesicsemi.com/images/products_sic/s jt/GA10JT12-CAL_spice.pdf) into ltspice (version 4) software for simulation of the GA10JT12-CAL. * model of genesic semiconductor inc. * * $revision: 2.0 $ * $date: 12-sep-2014 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2014 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * .model ga10jt12 npn + is 5.00e-47 + ise 1.26e-28 + eg 3.23 + bf 85 + br 0.55 + ikf 5000 + nf 1 + ne 2 + rb 4.67 + irb 0.001 + rbm 0.16 + re 0.005 + rc 0.099 + cjc 427.39e-12 + vjc 3.1004 + mjc 0.4752 + cje 1373e-12 + vje 10.6442 + mje 0.21376 + xti 3 + xtb -1.27 + trc1 6.8e-3 + vceo 1200 + icrating 10 + mfg genesic_semiconductor * * end of ga10jt12 spice model
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