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r01ds0241ej0100 rev. 1.00 page 1 of 67 jul 31, 2014 rl78/g1g renesas mcu datasheet 1. outline 1.1 features ultra-low power consumption technology ?v dd = single power supply voltage of 2.7 to 5.5 v ? halt mode ?stop mode ? snooze mode rl78 cpu core ? cisc architecture with 3-stage pipeline ? minimum instruction execution time: can be changed from high-speed (0.04167 s: @ 24 mhz operation with high-speed on-chip oscillator) to low-speed (1.0 s: @1 mhz operation with high-s peed on-chip oscillator) ? multiply/divide/multiply & accumulate instructions are supported. ? address space: 1 mb ? general-purpose registers: (8-bit register 8) 4 banks ? on-chip ram: 1.5 kb code flash memory ? code flash memory: 8 to 16 kb ? block size: 1 kb ? prohibition of block erase and rewriting (security function) ? on-chip debug function ? self-programming (flash shield window function) high-speed on-chip oscillator ? select from 48 mhz, 24 mhz, 16 mhz, 12 mhz, 8 mhz, 4 mhz, and 1 mhz ? high accuracy: 2.0% (v dd = 2.7 to 5.5 v, t a = -20 to +85 c) operating ambient temperature ?t a = -40 to +85 c power management and reset function ? on-chip power-on-reset (por) circuit ? on-chip voltage detector (lvd) (select interrupt and reset from 6 levels) event link controller (elc) ? event signals of 18 to 19 types can be linked to the specified peripheral function. serial interfaces ? csi: 1 channel ? uart: 2 channels ? simplified i 2 c: 1 channel timer ? 16-bit timer: 7 channels (timer array unit (tau): 4 channels, timer rj: 1 channel, timer rd: 2 channels) ? 12-bit interval timer: 1 channel ? watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) a/d converter ? 8/10-bit resolution a/d converter (v dd = 2.7 to 5.5 v) ? analog input: 8 to 12 channels ? internal reference voltage (1.45 v) and temperature sensor comparator ? 2 channels programmable gain amplifier i/o port ? i/o port: 26 to 40 ? can be set to n-ch open drain, ttl input buffer, and on- chip pull-up resistor ? different potential interface: can connect to a 2.5/3 v device ? on-chip key interrupt function ? on-chip clock output/ buzzer output controller others ? on-chip bcd (binary-coded decimal) correction circuit remark: the function mounted depend on the product. see 1.6 outline of functions. r01ds0241ej0100 rev. 1.00 jul 31, 2014
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 2 of 67 jul 31, 2014 rom, ram capacities note this is 630 bytes when the self-programming function is used. flash rom ram 30 pins 32 pins 44 pins 16 kb 1.5 kb note r5f11eaaasp r5f11ebaafp r5f11efaafp 8 kb r5f11ea8asp r5f11eb8afp r5f11ef8afp
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 3 of 67 jul 31, 2014 1.2 list of part numbers figure 1 - 1 part number, memory size, and package of rl78/g1g table 1 - 1 orderable part numbers pin count package part number 44 pins 44-pin plastic lqfp (10 10 mm) r5f11efaafp#30, r5f11efaafp#50 r5f11ef8afp#30, r5f11ef8afp#50 32 pins 32-pin plastic lqfp (7 7 mm) r5f11ebaafp#30, r5f11ebaafp#50 r5f11eb8afp#30, r5f11eb8afp#50 30 pins 30-pin plastic lssop (7.62 mm (300)) r5f11eaaasp#v0, r5f11eaaasp#x0 r5f11ea8asp#v0, r5f11ea8asp#x0 r5 f11e aaxxxsp type of packing #v0: tray (lssop) #x0: embossed tape (lssop) #30: tray (lqfp) #50: embossed tape (lqfp) package type sp: 0.65-mm pitch lssop fp: 0.80-mm pitch lqfp rom code number if the product has been pre-programmed before shipment (omitted for blank products) field of application a: consumer applications, operating ambient temperature: -40 c to +85 c memory type: f: flash memory renesas mcu renesas semiconductor product #v0 number of pins: a: 30-pin b: 32-pin f: 44-pin a rom capacity 8: 8 kb a: 16 kb rl78/g1g group part no.
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 4 of 67 jul 31, 2014 1.3 pin configuration (top view) 1.3.1 30-pin products ? 30-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. the functions in parentheses shown in the above figure can be assigned by setting peripheral i/o redirection register 1 (pior1). 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p21/ani1/av refm p22/ani2 p23/ani3 p147/ani18 p10/trdiod1 p11/trdioc1 p12/trdiob1 p13/trdioa1 p14/trdiod0 p15/pclbuz1/trdiob0 p16/ti01/to01/intp5/trdioc0 p17/ti02/to02/trdioa0/trdclk p51/intp2/so00/txd0/tooltxd p50/intp1/si00/rxd0/toolrxd/sda00/(trjo0) p30/intp3/sck00/scl00/trjo0 p01/ani16/to00/rxd1/pgai/(trjio0) p00/ani17/ti00/txd1/cmp0p/(trjo0) p120/ani19/cmp1p p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p60 p61 p31/ti03/to03/intp4/pclbuz0/ssi00 /(trjio0) p20/ani0/av refp
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 5 of 67 jul 31, 2014 1.3.2 32-pin products ? 32-pin plastic lqfp (7 7 mm, 0.8 mm pitch) caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. the functions in parentheses shown in the above figure can be assigned by setting peripheral i/o redirection register 1 (pior1). p51/intp2/so00/txd0/tooltxd p50/intp1/si00/rxd0/toolrxd/sda00/(trjo0) p30/intp3/sck00/scl00/trjo0 p70 p31/ti03/to03/intp4/pclbuz0/(trjio0) p62/ssi00 p61 p60 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 1 p147/ani18 p23/ani3 p22/ani2 p20/ani0/av refp p01/ani16/to00/rxd1/pgai/trjio0 p00/ani17/ti00/txd1/cmp0p/(trjo0) 2345678 24 23 22 21 20 19 18 17 p40/tool0 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd reset p17/ti02/to02/trdioa0/trdclk p16/ti01/to01/intp5/trdioc0 p15/pclbuz1/trdiob0 p14/trdiod0 p13/trdioa1 p12/trdiob1 p11/trdioc1 p10/trdiod1 p120/ani19/cmp1p p21/ani1/av refm
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 6 of 67 jul 31, 2014 1.3.3 44-pin products ? 44-pin plastic lqfp (10 10 mm, 0.8 mm pitch) caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. the functions in parentheses shown in the above figure can be assigned by setting peripheral i/o redirection register 1 (pior1). 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/to00/rxd1/pgai/ani16/trjio0 p00/ti00/txd1/cmp0p/ani17/(trjo0) p120/ani19/cmp1p p50/intp1/si00/rxd0/toolrxd/sda00/(trjo0) p30/intp3/sck00/scl00/trjo0 p70/kr0 p71/kr1 p72/kr2 p73/kr3 p31/ti03/to03/intp4/pclbuz0/(trjio0) p63 p62/ssi00 p61 p60 33 3231 30 29 28 27 26 25 24 1234567891011 23 p41/(trjio0) p40/tool0 reset p124 p123 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p17/ti02/to02/trdioa0/trdclk p16/ti01/to01/intp5/trdioc0 p15/pclbuz1/trdiob0 p14/trdiod0 p13/trdioa1 p12/trdiob1 p11/trdioc1 p10/trdiod1 p146 p147/ani18 p51/intp2/so00/txd0/tooltxd
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 7 of 67 jul 31, 2014 1.4 pin identification ani0 to ani7, ani16 to ani19:analog input av refm : a/d converter reference potential (- side) input av refp : a/d converter reference potential (+ side) input exclk: external clock input (main system clock) intp0 to intp5: external interrupt input kr0 to kr3: key return p00, p01: port 0 p10 to p17: port 1 p20 to p27: port 2 p30, p31: port 3 p40, p41: port 4 p50, p51: port 5 p60 to p63: port 6 p70 to p73: port 7 p120 to p124: port 12 p137: port 13 p146, p147: port 14 pclbuz0, pclbuz1: programmable clock output/buzzer output regc: regulator capacitance reset : reset rxd0, rxd1: receive data sck00: serial clock input/output scl00: serial clock output sda00: serial data input/output si00: serial data input so00: serial data output ssi00 : serial interface chip select input ti00 to ti03: timer input to00 to to03, trjo0: timer output tool0: data input/output for tool toolrxd, tooltxd: data input/output for external device trdclk: timer external input clock trdioa0, trdiob0, trdioc0, trdiod0,:timer input/output trdioa1, trdiob1, trdioc1, trdiod1, trjio0 txd0, txd1: transmit data cmp0p, cmp1p: comparator input pgai: pga input v dd : power supply v ss : ground x1, x2: crystal oscillator (main system clock)
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 8 of 67 jul 31, 2014 1.5 block diagram 1.5.1 30-pin products voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd intp5/p16 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p31 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 iic00 to00/p01 rxd0/p50 port 1 p10 to p17 8 port 2 p20 to p23 4 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p120 port 12 p121, p122 p137 port 13 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug 2 2 cmp (2ch) cmp0 cmp0p/p00 cmp1 cmp1p/p120 2 port 4 p40 p60, p61 2 4 ani0/p20 to ani3/p23 10-bit a/d converter ani16/p01, ani17/p00, ani18/p147, ani19/p120 4 av refp /p20 av refm /p21 x1/p121 reset x2/exclk/p122 p147 multiplier & divider, mulitiply- accumulator rl78 cpu core code flash memory buzzer output pclbuz0/p31, pclbuz1/p15 clock output control 2 bcd adjustment event link controller pga pwm option unit pgai/p01 window watchdog timer 12- bit interval timer low-speed on-chip oscillator
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 9 of 67 jul 31, 2014 1.5.2 32-pin products voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd intp5/p16 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 iic00 to00/p01 rxd0/p50 port 1 p10 to p17 8 port 2 p20 to p23 4 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p120 port 12 p121, p122 p137 port 13 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug 2 2 cmp (2ch) cmp0 cmp0p/p00 cmp1 cmp1p/p120 2 port 4 p40 port 7 p70 p60 to p62 3 4 ani0/p20 to ani3/p23 10-bit a/d converter ani16/p01, ani17/p00, ani18/p147, ani19/p120 4 av refp /p20 av refm /p21 x1/p121 reset x2/exclk/p122 p147 multiplier & divider, mulitiply- accumulator rl78 cpu core code flash memory buzzer output pclbuz0/p31, pclbuz1/p15 clock output control 2 bcd adjustment event link controller pga pwm option unit pgai/p01 window watchdog timer 12- bit interval timer low-speed on-chip oscillator
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 10 of 67 jul 31, 2014 1.5.3 44-pin products voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd intp5/p16 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 iic00 to00/p01 rxd0/p50 port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p120 port 12 p121 to p124 p137 port 13 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug 2 2 cmp (2ch) cmp0 cmp0p/p00 cmp1 cmp1p/p120 4 port 4 p40, p41 port 7 p70 to p73 p60 to p63 4 4 8 ani0/p20 to ani7/p27 10-bit a/d converter ani16/p01, ani17/p00, ani18/p147, ani19/p120 4 av refp /p20 av refm /p21 key return kr0/p70 to kr3/p73 4 x1/p121 reset x2/exclk/p122 2 p146, p147 2 multiplier & divider, mulitiply- accumulator rl78 cpu core code flash memory buzzer output pclbuz0/p31, pclbuz1/p15 clock output control 2 bcd adjustment event link controller pga pwm option unit pgai/p01 window watchdog timer 12- bit interval timer low-speed on-chip oscillator
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 11 of 67 jul 31, 2014 1.6 outline of functions [30-pin, 32-pin, 44-pin products (code flash memory 8 kb to 16 kb)] caution the above outline of the functions applies when peripheral i/o redirection register 1 (pior1) is set to 00h. (1/2) caution since a library is used when rewriting the flash memory using the user program, flash rom and ram areas are used. refer to the rl78 family flash self-progra mming library type01 user?s manual before using these products. item 30-pin 32-pin 44-pin r5f11ea8asp, r5f11eaaasp r5f11eb8afp, r5f11ebaafp r5f11ef8afp, r5f11efaafp code flash memory (kb) 8 to 16 ram (kb) 1.5 address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 5.5 v high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 24 mhz (v dd = 2.7 to 5.5 v) low-speed on-chip oscillator clock 15 khz (typ.): v dd = 2.7 to 5.5 v general-purpose register 8 bits 32 regi sters (8 bits 8 registers 4 banks) minimum instruction execution time 0.04167 s (high-speed on-chip oscillator clock: f ih = 24 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits ), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and ac cumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 26 28 40 cmos i/o 23 25 35 cmos input 3 3 5 cmos output ? n-ch open-drain i/o (6 v tolerance) ? timer 16-bit timer 7 channels (tau: 4 channels, timer rj: 1 channel, timer rd: 2 channels) watchdog timer 1 channel 12-bit interval timer 1 channel timer output timer outputs: 14 channels pwm outputs: 9 channels
rl78/g1g 1. outline r01ds0241ej0100 rev. 1.00 page 12 of 67 jul 31, 2014 (2/2) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction execution is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. item 30-pin 32-pin 44-pin r5f11ea8asp, r5f11eaaasp r5f11eb8afp, r5f11ebaafp r5f11ef8afp, r5f11efaafp clock output/buzzer output 2 ? 2.44 khz, 4.88 khz, 9.77 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) 8/10-bit resolution a/d converter 8 channels 12 channels comparator 2 channels pga 1 channel serial interface ? csi: 1 channel/uart0: 1 channel/simplified i 2 c: 1 channel ? uart1: 1 channel event link controller (elc) event input: 18 event trigger output: 6 event input: 19 event trigger output: 6 vectored interrupt sources internal 20 external 67 key interrupt ? 4 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.03 v ? power-down-reset: 1.50 0.03 v voltage detector 2.75 v to 4.06 v (6 stages) on-chip debug function provided power supply voltage v dd = 2.7 to 5.5 v operating ambient temperature t a = -40 to +85c
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 13 of 67 jul 31, 2014 2. electrical specifications caution 1. the rl78 microcontroller has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. caution 2. the pins mounted are as follows according to product. 2.1 pins mounted according to product 2.1.1 port functions refer to 2.1.1 30-pin products , 2.1.2 32-pin products , and 2.1.3 44-pin products in the rl78/g1g user?s manual. 2.1.2 non-port functions refer to 2.2.1 with functions for each product in the rl78/g1g user?s manual.
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 14 of 67 jul 31, 2014 2.2 absolute maximum ratings note 1. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. note 2. must be 6.5 v or lower. note 3. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark 1. unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. remark 2. av ref (+): + side reference voltage of the a/d converter. remark 3. v ss : reference voltage absolute maximum ratings (1/2) parameter symbol conditions ratings unit supply voltage v dd -0.5 to +6.5 v regc pin input voltage v iregc regc -0.3 to +2.8 and -0.3 to v dd +0.3 note 1 v input voltage v i1 p00, p01, p10 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p121 to p124, p137, p146, p147, exclk, reset -0.3 to v dd +0.3 note 2 v output voltage v o1 p00, p01, p10 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 -0.3 to v dd +0.3 note 2 v analog input voltage v ai1 ani0 to ani7, ani16 to ani19 -0.3 to v dd +0.3 notes 2, 3 and -0.3 to av ref (+) +0.3 v
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 15 of 67 jul 31, 2014 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. absolute maximum ratings (2/2) parameter symbol conditions ratings unit output current, high i oh1 per pin p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 -40 ma total of all pins -170 ma p00, p01, p40, p41, p120 -70 ma p10 to p17, p30, p31, p50, p51, p60 to p63, p70 to p73, p146, p147 -100 ma i oh2 per pin p20 to p27 -0.5 ma total of all pins -2 ma output current, low i ol1 per pin p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 40 ma total of all pins 170 ma p00, p01, p40, p41, p120 70 ma p10 to p17, p30, p31, p50, p51, p60 to p63, p70 to p73, p146, p147 100 ma i ol2 per pin p20 to p27 1 ma total of all pins 5m a operating ambient temperature t a in normal operation mode -40 to +85 c in flash memory programming mode storage temperature t stg -65 to +150 c
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 16 of 67 jul 31, 2014 2.3 oscillator characteristics 2.3.1 x1 oscillator characteristics note indicates only permissible oscillat or frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator, refer to 5.4 system clock oscillator in the rl78/g1g user?s manual. 2.3.2 on-chip oscillator characteristics note 1. high-speed on-chip oscillator fr equency is selected with bits 0 to 4 of the option byte (000c2h) and bits 0 to 2 of the hocodiv register. note 2. this only indicates the oscillator characteristics. refer to ac characteristics for instruction execution time. (t a = -40 to +85c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 2.7 v v dd 5.5 v 1.0 20.0 mhz (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 12 4m h z f hoco 14 8 high-speed on-chip oscillator clock frequency accuracy -2 +2 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy -15 +15 %
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 17 of 67 jul 31, 2014 2.4 dc characteristics 2.4.1 pin characteristics note 1. value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. note 2. do not exceed the total current value. note 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = -10.0 ma total output current of pins = (-10.0 0.7)/(80 0.01) -8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p00, p10, p15, p17, p30, p50, p51 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 2.7 v v dd 5.5 v -10.0 note 2 ma total of p00, p01, p40, p41, p120 (when duty 70% note 3 ) 4.0 v v dd 5.5 v -55.0 ma 2.7 v v dd < 4.0 v -10.0 ma total of p10 to p17, p30, p31, p50, p51, p60 to p63, p70 to p73, p146, p147 (when duty 70% note 3 ) 4.0 v v dd 5.5 v -80.0 ma 2.7 v v dd < 4.0 v -19.0 ma total of all pins (when duty 70% note 3 ) 2.7 v v dd 5.5 v -135.0 ma i oh2 per pin for p20 to p27 2.7 v v dd 5.5 v -0.1 note 2 ma total of all pins (when duty 70% note 3 ) 2.7 v v dd 5.5 v -1.5 ma
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 18 of 67 jul 31, 2014 note 1. value of current at which the device operation is guaranteed even if the current flows from an output pin to the v ss pin. note 2. however, do not exceed the total current value. note 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = 10.0 ma total output current of pins = (10.0 0.7)/(80 0.01) 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, low note 1 i ol1 per pin for p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 20.0 note 2 ma total of p00, p01, p40, p41, p120 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 70.0 ma 2.7 v v dd < 4.0 v 15.0 ma total of p10 to p17, p30, p31, p50, p51, p60 to p63, p70 to p73, p146, p147 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 80.0 ma 2.7 v v dd < 4.0 v 35.0 ma total of all pins (when duty 70% note 3 ) 150.0 ma i ol2 per pin for p20 to p27 0.4 note 2 ma total of all pins (when duty 70% note 3 ) 2.7 v v dd 5.5 v 5.0 ma
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 19 of 67 jul 31, 2014 caution the maximum value of v ih of pins p00, p10, p15, p17, p30, p50, and p51 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit input voltage, high v ih1 p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120 to p124, p146, p147 normal input buffer 0.8 v dd v dd v v ih2 p01, p10, p15 to p17, p30, p31, p50 ttl input buffer 4.0 v v dd 5.5 v 2.2 v dd v ttl input buffer 3.3 v v dd < 4.0 v 2.0 v dd v ttl input buffer 2.7 v v dd < 3.3 v 1.50 v dd v v ih3 p20 to p27 0.7 v dd v dd v v ih4 exclk, reset 0.8 v dd v dd v input voltage, low v il1 p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120 to p124, p146, p147 normal input buffer 0 0.2 v dd v v il2 p01, p10, p15 to p17, p30, p31, p50 ttl input buffer 4.0 v v dd 5.5 v 00.8v ttl input buffer 3.3 v v dd < 4.0 v 00.5v ttl input buffer 2.7 v v dd < 3.3 v 00.32v v il3 p20 to p27 0 0.3 v dd v v il4 exclk, reset 0 0.2 v dd v
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 20 of 67 jul 31, 2014 caution p00, p10, p15, p17, p30, p50, and p51 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output voltage, high v oh1 p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 4.0 v v dd 5.5 v, i oh1 = -10.0 ma v dd - 1.5 v 4.0 v v dd 5.5 v, i oh1 = -3.0 ma v dd - 0.7 v 2.7 v v dd 5.5 v, i oh1 = -2.0 ma v dd - 0.6 v 2.7 v v dd 5.5 v, i oh1 = -1.0 ma v dd - 0.5 v v oh2 p20 to p27 2.7 v v dd 5.5 v, i oh2 = -100 a v dd - 0.5 v output voltage, low v ol1 p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 4.0 v v dd 5.5 v, i ol1 = 20.0 ma 1.3 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 0.3 ma 0.4 v v ol2 p20 to p27 2.7 v v dd 5.5 v, i ol2 = 400 a 0.4 v
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 21 of 67 jul 31, 2014 remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit input leakage current, high i lih1 p00, p01, p10 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p123, p124, p137, p146, p147, reset v i = v dd 1 a i lih2 p121, p122 (x1, x2, exclk) v i = v dd in input port or external clock input 1 a in resonator connection 10 a input leakage current, low i lil1 p00, p01, p10 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p123, p124, p137, p146, p147, reset v i = v ss -1 a i lil2 p121, p122 (x1, x2, exclk) v i = v ss in input port or external clock input -1 a in resonator connection -10 a on-chip pull-up resistance r u p00, p01, p10 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p73, p120, p146, p147 v i = v ss , in input port 10 20 100 k
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 22 of 67 jul 31, 2014 2.4.2 supply current characteristics note 1. total current flowing into v dd , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripher al operation current. however, not including the current flowing into the a/d converter, comparator, programmable ga in amplifier, watchdog timer, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors. note 2. when high-speed on-chip oscillator is stopped. note 3. when high-speed system clock is stopped. note 4. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high speed main) mode: v dd = 2.7 v to 5.5 v@1 mhz to 24 mhz ls (low speed main) mode: v dd = 2.7 v to 5.5 v@1 mhz to 8 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillati on frequency or external ma in system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (48 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (24 mhz max.) remark 4. temperature condition of the typ. value is t a = 25c (1) flash rom: 16 kb of 30- pin to 44-pin products (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) mode notes 3, 4 f hoco = 48 mhz, f ih = 24 mhz basic operation v dd = 5.0 v 1.8 ma v dd = 3.0 v 1.8 hs (high-speed main) mode notes 3, 4 f hoco = 48 mhz, f ih = 24 mhz normal operation v dd = 5.0 v 3.9 6.9 ma v dd = 3.0 v 3.9 6.9 f hoco = 24 mhz, f ih = 24 mhz normal operation v dd = 5.0 v 3.7 6.3 v dd = 3.0 v 3.7 6.3 f hoco = 16 mhz, f ih = 16 mhz normal operation v dd = 5.0 v 2.8 4.6 v dd = 3.0 v 2.8 4.6 ls (low-speed main) mode notes 3, 4 f ih = 8 mhz normal operation v dd = 3.0 v 1.2 2.0 ma hs (high-speed main) mode notes 2, 4 f mx = 20 mhz, v dd = 5.0 v normal operation square wave input 3.1 5.3 ma resonator connection 3.3 5.5 f mx = 20 mhz, v dd = 3.0 v normal operation square wave input 3.1 5.3 resonator connection 3.3 5.5 f mx = 10 mhz, v dd = 5.0 v normal operation square wave input 2.0 3.1 resonator connection 2.0 3.2 f mx = 10 mhz, v dd = 3.0 v normal operation square wave input 2.0 3.1 resonator connection 2.0 3.2 ls (low-speed main) mode notes 2, 4 f mx = 8 mhz, v dd = 3.0 v normal operation square wave input 1.2 1.9 ma resonator connection 1.2 2.0
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 23 of 67 jul 31, 2014 note 1. total current flowing into v dd , including the input leakage current flowing wh en the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripher al operation current. however, not including the current flowing into the a/d converter, comparator, programmable ga in amplifier, watchdog timer, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors. note 2. during halt instruction execution by flash memory. note 3. when high-speed on-chip oscillator is stopped. note 4. when high-speed system clock is stopped. note 5. when high-speed on-chip oscillator and high-speed system clock are stopped. when watchdog timer is stopped. the values below the max. column include the leakage current. note 6. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high speed main) mode: v dd = 2.7 v to 5.5 v@1 mhz to 24 mhz ls (low speed main) mode: v dd = 2.7 v to 5.5 v@1 mhz to 8 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillati on frequency or external ma in system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (48 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (24 mhz max.) remark 4. temperature condition of the typ. value is t a = 25c (1) flash rom: 16 kb of 30-pin to 44-pin products (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode notes 4, 6 f hoco = 48 mhz, f ih = 24 mhz v dd = 5.0 v 0.60 2.40 ma v dd = 3.0 v 0.60 2.40 f hoco = 24 mhz, f ih = 24 mhz v dd = 5.0 v 0.40 1.83 v dd = 3.0 v 0.40 1.83 f hoco = 16 mhz, f ih = 16 mhz v dd = 5.0 v 0.38 1.38 v dd = 3.0 v 0.38 1.38 ls (low-speed main) mode notes 4, 6 f ih = 8 mhz v dd = 3.0 v 260 710 a hs (high-speed main) mode notes 3, 6 f mx = 20 mhz, v dd = 5.0 v square wave input 0.28 1.55 ma resonator connection 0.42 1.74 f mx = 20 mhz, v dd = 3.0 v square wave input 0.28 1.55 resonator connection 0.42 1.74 f mx = 10 mhz, v dd = 5.0 v square wave input 0.19 0.86 resonator connection 0.27 0.93 f mx = 10 mhz, v dd = 3.0 v square wave input 0.19 0.86 resonator connection 0.27 0.93 ls (low-speed main) mode notes 3, 6 f mx = 8 mhz, v dd = 3.0 v square wave input 95 550 a resonator connection 145 590 i dd3 stop mode note 5 t a = -40 c 0.18 0.51 a t a = +25 c 0.24 0.51 t a = +50 c 0.29 1.10 t a = +70 c 0.41 1.90 t a = +85 c 0.90 3.30
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 24 of 67 jul 31, 2014 note 1. when high speed on-chip oscillator and high-speed system clock are stopped. note 2. current flowing only to the watchdog timer (including th e operating current of the low-speed on-chip oscillator). the current value of the rl78 microcontroller is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates in stop mode. note 3. current flowing only to the a/d converter. the current value of the rl78 microcontroller is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. note 4. current flowing only to the comparator. the current value of the rl78 microcontroller is the sum of i dd1 or i dd2 and i cmp when the comparator operates in operating mode or halt mode. note 5. current flowing only to the programmable gain amplifier. t he current value of the rl78 microcontroller is the sum of i dd1 or i dd2 and i pga when the programmable gain amplifier operates in operating mode or halt mode. note 6. current flowing only to the lvd circuit. the current value of the rl78 microcontroller is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvd circuit operates in the operating, halt or stop mode. note 7. for details on the transition time to snooze mode, refer to 18.3.3 snooze mode in the rl78/g1g user?s manual. note 8. current flowing only to the 12-bit interval timer (excluding t he operating current of the low-speed on-chip oscillator). the supply current of the rl78 microcontroller is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. w hen the low-speed on-chip oscillator is selected, i fil should be added. remark 1. f il : low-speed on-chip oscillator clock frequency remark 2. f clk : cpu/peripheral hardware clock frequency remark 3. temperature condition of the typ. value is t a = 25c (2) peripheral functions (common to all products) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit 12-bit interval timer operating current i it notes 1, 8 0.02 a watchdog timer operating current i wdt notes 1, 2 f il = 15 khz 0.22 a a/d converter operating current i adc note 3 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma low voltage mode, av refp = v dd = 3.0 v 0.5 0.7 ma a/d converter reference voltage current i adref 75 a temperature sensor operating current i tmps 75 a comparator operating current i cmp note 4 per channel of comparator 1 when the comparator is operating 45.0 65.0 a when the comparator is stopped 0.0 0.1 programmable gain amplifier operating current i pga note 5 when the programmable gain amplifier is operating 240.0 340.0 a when the programmable gain amplifier is stopped 0.0 0.1 lvd operating current i lvi note 6 0.08 a snooze operating current i snoz adc operation the mode is performed note 7 0.50 0.60 ma the a/d conversion operations are performed low voltage mode av refp = v dd = 3.0 v 1.20 1.44 ma csi/uart operation 0.70 0.84 ma
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 25 of 67 jul 31, 2014 2.5 ac characteristics 2.5.1 basic operation remark f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn bit of timer mode register mn (tmrmn). m: unit number (m = 0), n: channel number (n = 0 to 3)) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation hs (high-speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s ls (low-speed main) mode 2.7 v v dd 5.5 v 0.125 1 s in the self programming mode hs (high-speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s ls (low-speed main) mode 2.7 v v dd 5.5 v 0.125 1 s external main system clock frequency f ex 2.7 v v dd 5.5 v 1.0 20.0 mhz external main system clock input high-level width, low-level width t exh , t exl 2.7 v v dd 5.5 v 24 ns ti00 to ti03 input high-level width, low-level width t tih , t til 1/f mck + 10 ns timer rj input cycle f c trjio 2.7 v v dd 5.5 v 100 ns timer rj input high-level width, low-level width f wh , f wl trjio 2.7 v v dd 5.5 v 40 ns to00 to to03, trjio0,trjo, trdioa0/1, trdiob0/1, trdioc0/1,trdiod0/1 output frequency f to hs (high-speed main) mode 4.0 v v dd 5.5 v 12 mhz 2.7 v v dd < 4.0 v 8 mhz ls (low-speed main) mode 2.7 v v dd 5.5 v 4 mhz pclbuz0, pclbuz1 output frequency f pcl hs (high-speed main) mode 4.0 v v dd 5.5 v 16 mhz 2.7 v v dd < 4.0 v 8 mhz ls (low-speed main) mode 2.7 v v dd 5.5 v 4 mhz interrupt input high-level width, low-level width t inth , t intl intp0 to intp5 2.7 v v dd 5.5 v 1 s key interrupt input low-level width t kr kr0-kr3 2.7 v v dd 5.5 v 250 ns reset low-level width t rsl 10 s
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 26 of 67 jul 31, 2014 minimum instruction execution time during main system clock operation tcy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 0.04167 0.05 cycle time t cy [s] supply voltage v dd [v] during self-programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 27 of 67 jul 31, 2014 tcy vs v dd (ls (low-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 5.5 0.01 cycle time t cy [s] supply voltage v dd [v] 6.0 0.125 during self-programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected 2.7
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 28 of 67 jul 31, 2014 ac timing test points external system clock timing ti/to timing v ih /v oh v il /v ol v ih /v oh test points v il /v ol exclk 1/f ex t exl t exh t til t tih 1/f to ti00 to ti03 to00 to to03 trjio0, trjo0, trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 29 of 67 jul 31, 2014 t tjil trjio t tjih t tdil trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 t tdih t tdsil intp0
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 30 of 67 jul 31, 2014 interrupt reques t input timing key interrupt input timing reset input timing intp0 to intp5 t intl t inth t kr kr0 to kr3 t rsl reset
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 31 of 67 jul 31, 2014 2.6 peripheral functions characteristics ac timing test points 2.6.1 serial array unit uart mode connection diagram (durin g communication at same potential) uart mode bit width (durin g communication at same potential) (reference) note 1. transfer rate in the snooze mode is 4800 bps only. however, the snooze mode cannot be used when frqsel4 = 1. note 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (2.7 v v dd 5.5 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 5) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03)) (1) during communication at same potential (uart mode) (t a = -40 to +85 c, 2.7 v 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. transfer rate note 1 2.7 v v dd 5.5 v f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 2 4.0 1.3 mbps v ih /v oh v il /v ol v ih /v oh test points v il /v ol txdq rxdq user?s device rx tx rl78 microcontroller baud rate error tolerance txdq rxdq high-/low-bit width 1/transfer rate
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 32 of 67 jul 31, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. this value is valid only when csi00?s peripheral i/o redi rect function is not used. remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom numbers (g = 1) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) (2) during communication at same potential (csi mo de) (master mode, sckp... internal clock output, corresponding csi00 only) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time t kcy1 t kcy1 2/f clk 2.7 v v dd 5.5 v 83.3 250 ns sckp high-/low-level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 - 7 t kcy1 /2 - 50 ns 2.7 v v dd 5.5 v t kcy1 /2 - 10 t kcy1 /2 - 50 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v 23 110 ns 2.7 v v dd 5.5 v 33 110 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v v dd 5.5 v 10 10 ns delay time from sckp to sop output note 3 t kso1 c = 20 pf note 4 10 10 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 33 of 67 jul 31, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim number (g = 3, 5) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) (3) during communication at same potential (csi mo de) (master mode, sckp... internal clock output) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd 5.5 v 167 500 ns sckp high-/low-level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 - 12 t kcy1 /2 - 50 ns 2.7 v v dd 5.5 v t kcy1 /2 - 18 t kcy1 /2 - 50 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v 44 110 ns 2.7 v v dd 5.5 v 44 110 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v v dd 5.5 v 19 19 ns delay time from sckp to sop output note 3 t kso1 2.7 v v dd 5.5 v c = 30 pf note 4 25 25 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 34 of 67 jul 31, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sop output lines. note 5. the maximum transfer rate when using the snooze mode is 1 mbps. caution select the normal input buffer for the sip pin and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim number (g = 3, 5) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) (4) during communication at same potential (csi mode) (slave mode , sckp... external clock input) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time note 5 t kcy2 4.0 v v dd 5.5 v 20 mhz < f mck 8/f mck ?n s f mck 20 mhz 6/f mck 6/f mck ns 2.7 v v dd 5.5 v 16 mhz < f mck 8/f mck ?n s f mck 16 mhz 6/f mck 6/f mck ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v t kcy2 /2 - 7 t kcy2 /2 - 7 ns 2.7 v v dd 5.5 v t kcy2 /2 - 8 t kcy2 /2 - 8 ns sip setup time (to sckp ) note 1 t sik2 2.7 v v dd 5.5 v 1/f mck + 20 1/f mck + 30 ns sip hold time (from sckp ) note 2 t ksi2 2.7 v v dd 5.5 v 1/f mck + 31 1/f mck + 31 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.7 v v dd 5.5 v 2/f mck + 44 2/f mck + 110 ns ssi00 setup time t ssik dapmn = 0 2.7 v v dd 5.5 v 120 120 ns dapmn = 1 2.7 v v dd 5.5 v 1/f mck + 120 1/f mck + 120 ns ssi00 hold time t kssi dapmn = 0 2.7 v v dd 5.5 v 1/f mck + 120 1/f mck + 120 ns dapmn = 1 2.7 v v dd 5.5 v 120 120 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 35 of 67 jul 31, 2014 csi mode connection diagram (during communication at same potential) csi mode connection diagram (during communication at same potential) (slave transmission of slave se lect input function (csi00)) remark 1. p: csi number (p = 00) remark 2. m: unit number, n: channel number (mn = 00) sckp sop user's device sck si sip so rl78 microcontroller sck00 so00 user's device sck si si00 so ssi00 ss0 rl78 microcontroller
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 36 of 67 jul 31, 2014 csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00) remark 2. m: unit number, n: channel number (mn = 00) sip sop t kcy1, 2 input data output data sckp t kl1, 2 t kh1, 2 ssi00 (csi00 only) t sik1, 2 t ksi1, 2 t kso1, 2 t ssik t kssi input data output data t kcy1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 t ssik t kssi sip sop sckp ssi00 (csi00 only) t kl1, 2
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 37 of 67 jul 31, 2014 note 1. the value must also be equal to or less than f mck /4. note 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. (remaks are listed on the next page.) (5) during communication at sa me potential (simplified i 2 c mode) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sclr clock frequency f scl 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 1000 note 1 400 note 1 khz 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 400 note 1 400 note 1 khz hold time when sclr = ?l? t low 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 475 1150 ns 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 1150 ns hold time when sclr = ?h? t high 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 475 1150 ns 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 1150 ns data setup time (reception) t su: dat 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 1/f mck + 85 note 2 1/f mck + 145 note 2 ns 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 145 note 2 1/f mck + 145 note 2 ns data hold time (transmission) t hd: dat 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 0 305 0 305 ns 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 0 355 0 355 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 38 of 67 jul 31, 2014 simplified i 2 c mode connection diagram (during communication at same potential) simplified i 2 c mode serial transfer timing (d uring communication at same potential) caution select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). remark 1. r b [ ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance remark 2. r: iic number (r = 00), g: pim number (g = 3, 5), h: pom number (h = 3, 5) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0), n: channel number (n = 0), mn = 00) sdar sclr user?s device sda scl v dd r b rl78 microcontroller sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 39 of 67 jul 31, 2014 note 1. transfer rate in the snooze mode is 4800 bps only. however, the snooze mode cannot be used when frqsel4 = 1. note 2. use it with v dd v b . note 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (2.7 v v dd 5.5 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. v b [v]: communication line voltage remark 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 5) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03) remark 4. v ih and v il below are observation points for the ac characteri stics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v: v ih = 1.50 v, v il = 0.32 v (6) communication at di fferent potential (2.5 v, 3 v) (uart mode) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. transfer rate reception 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck /6 note 1 f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 3 4.0 1.3 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck /6 note 1 f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 3 4.0 1.3 mbps 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v f mck /6 notes 1, 2 f mck /6 notes 1, 2 bps theoretical value of the maximum transfer rate f mck = f clk note 3 4.0 1.3 mbps
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 40 of 67 jul 31, 2014 note 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd 5.5 v and 2.7 v v b 4.0 v note 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum transfer rate under conditions of the customer. note 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 4.0 v and 2.3 v v b 2.7 v note 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum transfer rate under conditions of the customer. note 5. use it with v dd v b . (6) communication at different pote ntial (2.5 v, 3 v) (uart mode) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. transfer rate transmission 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v note 1 note 1 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 2.8 note 2 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v note 3 note 3 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 1.2 note 4 mbps 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v note 5, 6 note 5, 6 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 7 0.43 note 7 mbps maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 2.2 v b {-c b r b in (1 - )} 2.2 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 2.0 v b {-c b r b in (1 - )} 2.0 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides .
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 41 of 67 jul 31, 2014 note 6. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 3.3 v and 1.6 v v b 2.0 v note 7. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 6 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage remark 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 5) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03)) remark 4. v ih and v il below are observation points for the ac characteri stics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v: v ih = 1.50 v, v il = 0.32 v uart mode connection diagram (during communication at different potential) maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 1.5 v b {-c b r b in (1 - )} 1.5 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . txdq rxdq user?s device rx tx v b r b rl78 microcontroller
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 42 of 67 jul 31, 2014 uart mode bit width (during communicatio n at different potential) (reference) remark 1. r b [ ]: communication line (txdq) pull-up resistance, v b [v]: communication line voltage remark 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 5) baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate txdq rxdq
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 43 of 67 jul 31, 2014 ( notes , caution and remarks are listed on the next page.) (7) communication at different potential (2.5 v, 3 v) (csi mode) (mas ter mode, sckp... inte rnal clock output, corresponding csi00 only) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time t kcy1 t kcy1 2/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 200 1150 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 300 1150 ns sckp high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 - 120 t kcy1 /2 - 120 ns sckp low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 - 7 t kcy1 /2 - 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 - 10 t kcy1 /2 - 50 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 58 479 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 121 479 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 ns delay time from sckp to sop output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 60 60 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 130 130 ns sip setup time (to sckp ) note 2 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 23 110 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 33 110 ns sip hold time (from sckp ) note 2 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 ns delay time from sckp to sop output note 2 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 44 of 67 jul 31, 2014 csi mode connection diagram (during communication at different potential) note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. note 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) remark 3. v ih and v il below are observation points for the ac characteri stics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v remark 4. this value is valid only w hen csi00?s peripheral i/o redirect function is not used. sckp sop user?s device sck si sip so v b r b v b r b rl78 microcontroller
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 45 of 67 jul 31, 2014 caution 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. caution 2. use it with v dd v b . remark 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) remark 3. v ih and v il below are observation points for the ac characteri stics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v (8) communication at different potential (2.5 v, 3 v) (f mck /4) (csi mode) (master mode, sckp ... internal clock output) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v)(1/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time t kcy1 t kcy1 4/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 300 1150 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 500 1150 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 1150 1150 ns sckp high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 - 75 t kcy1 /2 - 75 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 - 170 t kcy1 /2 - 170 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 - 458 t kcy1 /2 - 458 ns sckp low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 - 12 t kcy1 /2 - 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 - 18 t kcy1 /2 - 50 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 - 50 t kcy1 /2 - 50 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 46 of 67 jul 31, 2014 ( notes , caution and remarks are listed on the next page.) (8) communication at different potential (2.5 v, 3 v) (f mck /4) (csi mode) (master mode , sckp... internal clock output) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 81 479 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 479 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 479 479 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 19 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 19 19 ns delay time from sckp to sop output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 100 100 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 195 195 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 483 483 ns sip setup time (to sckp ) note 2 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 44 110 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 110 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 110 110 ns sip hold time (from sckp ) note 2 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 19 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 19 19 ns delay time from sckp to sop output note 2 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 25 25 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 25 25 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 25 25 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 47 of 67 jul 31, 2014 csi mode connection diagram (during communication at different potential note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. note 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. caution 2. use it with v dd v b . remark 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) remark 3. v ih and v il below are observation points for the ac characteri stics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v sckp sop user?s device sck si sip so v b r b v b r b rl78 microcontroller
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 48 of 67 jul 31, 2014 csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) input data sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 output data sckp input data output data sip sop sckp t kcy1 t kh1 t kl1 t sik1 t ksi1 t kso1
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 49 of 67 jul 31, 2014 ( notes , caution and remarks are listed on the next page.) (9) communication at different potential (2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter sym bol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time note 1 t kcy2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v 20 mhz < f mck 24 mhz 12/f mck ?n s 8 mhz < f mck 20 mhz 10/f mck ?n s 4 mhz < f mck 8 mhz 8/f mck 16/f mck ns f mck 4 mhz 6/f mck 10/f mck ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 20 mhz < f mck 24 mhz 16/f mck ?n s 16 mhz < f mck 20 mhz 14/f mck ?n s 8 mhz < f mck 16 mhz 12/f mck ?n s 4 mhz < f mck 8 mhz 8/f mck 16/f mck ns f mck 4 mhz 6/f mck 10/f mck ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v 20 mhz < f mck 24 mhz 36/f mck ?n s 16 mhz < f mck 20 mhz 32/f mck ?n s 8 mhz < f mck 16 mhz 26/f mck ?n s 4 mhz < f mck 8 mhz 16/f mck 16/f mck ns f mck 4 mhz 10/f mck 10/f mck ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v t kcy2 /2 - 12 t kcy2 /2 - 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v t kcy2 /2 - 18 t kcy2 /2 - 50 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v t kcy2 /2 - 50 t kcy2 /2 - 50 ns sip setup time (to sckp ) note 2 t sik2 2.7 v v dd 5.5 v 1/f mck + 20 1/f mck + 30 ns sip hold time (from sckp ) note 3 t ksi2 1/f mck + 31 1/f mck + 31 ns delay time from sckp to sop output note 4 t kso2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 120 2/f mck + 573 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 214 2/f mck + 573 ns 2.7 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r v = 5.5 k 2/f mck + 573 2/f mck + 573 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 50 of 67 jul 31, 2014 csi mode connection diagram (during communication at different potential) note 1. transfer rate in the snooze mode: max. 1 mbps note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and sckp pin, and the n-ch open drain output (v dd tolerance) mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. r b [ ]: communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) remark 4. v ih and v il below are observation points for the ac characteri stics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v remark 5. communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. sckp sop user?s device sck si sip so v b r b rl78 microcontroller
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 51 of 67 jul 31, 2014 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) remark 2. communication at different potential cannot be performed dur ing clock synchronous serial communication with the slave select function. sip sop sckp input data output data t kcy2 t kh2 t kl2 t sik2 t ksi2 t kso2 input data output data sip sop sckp t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 52 of 67 jul 31, 2014 ( notes , caution and remarks are listed on the next page.) (10) communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sclr clock frequency f scl 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1000 note 1 300 note 1 khz 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1000 note 1 300 note 1 khz 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 400 note 1 300 note 1 khz 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 400 note 1 300 note 1 khz 2.7 v v dd < 3.3 v, 1.6 v v b < 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 300 note 1 300 note 1 khz hold time when sclr = ?l? t low 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 475 1550 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 475 1550 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1150 1550 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 1150 1550 ns 2.7 v v dd < 3.3 v, 1.6 v v b < 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 1550 1550 ns hold time when sclr = ?h? t high 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 245 610 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 200 610 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 675 610 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 600 610 ns 2.7 v v dd < 3.3 v, 1.6 v v b < 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 610 610 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 53 of 67 jul 31, 2014 note 1. the value must also be equal to or less than f mck /4. note 2. use it with v dd v b . note 3. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) (10) communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. data setup time (reception) t su:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 3 1/f mck + 190 note 3 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 3 1/f mck + 190 note 3 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 2.7 v v dd < 3.3 v, 1.6 v v b < 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 1/f mck + 190 note 3 1/f mck + 190 note 3 ns data hold time (transmission) t hd:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 0 305 0 305 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 0 305 0 305 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 0 355 0 355 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 0 355 0 355 ns 2.7 v v dd < 3.3 v, 1.6 v v b < 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 0 405 0 405 ns
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 54 of 67 jul 31, 2014 simplified i 2 c mode connection diagram (during communication at different potential) simplified i 2 c mode serial transfer timing (durin g communication at different potential) remark 1. r b [ ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage remark 2. r: iic number (r = 00), g: pim, pom number (g = 3, 5) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mo de register mn (smrmn). m: unit number (m = 0), n: channel number (n = 0), mn = 00) remark 4. v ih and v il below are observation points for the ac characteri stics of the serial array unit when communicating at different potentials in simplified i 2 c mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v sdar sclr user?s device sda scl v b r b v b r b rl78 microcontroller sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 55 of 67 jul 31, 2014 2.7 analog characteristics 2.7.1 a/d converte r characteristics note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage (-) = av refm reference voltage (+) = v dd reference voltage (-) = v ss reference voltage (+) = v bgr reference voltage (-) = av refm ani0 to ani7 refer to 2.7.1 (1) .r e f e r t o 2.7.1 (3) . refer to 2.7.1 (4) . ani16 to ani19 refer to 2.7.1 (2) . internal reference voltage temperature sensor output voltage refer to 2.7.1 (1) .? (1) when av ref (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), av ref (-) = av refm /ani1 (adrefm = 1), target ani pin: ani2 to ani7 (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp, reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 81 0 b i t overall error note 1 ainl 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 1.2 3.5 lsb conversion time t conv 10-bit resolution av refp = v dd 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 0.25 % fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 0.25 % fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 1.5 lsb reference voltage (+) av refp 2.7 v dd v analog input voltage v ain 0a v refp v v bgr select internal reference voltage output, 2.7 v v dd 5.5 v, hs (high-speed main) mode 1.38 1.45 1.5 v
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 56 of 67 jul 31, 2014 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. (2) when av ref (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), av ref (-) = av refm /ani1 (adrefm = 1), target ani pin: ani16 to ani19 (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp, reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 81 0 b i t overall error note 1 ainl 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 1.2 5.0 lsb conversion time t conv 10-bit resolution av refp = v dd 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 0.35 % fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 0.35 % fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 3.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd 2.7 v v dd 5.5 v 2.0 lsb reference voltage (+) av refp 2.7 v dd v analog input voltage v ain 0a v refp v v bgr select internal reference voltage output, 2.7 v v dd 5.5 v, hs (high-speed main) mode 1.38 1.45 1.5 v
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 57 of 67 jul 31, 2014 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. (3) when av ref (+) = v dd (adrefp1 = 0, adrefp0 = 0), av ref (-) = v ss (adrefm = 0), target ani pin: ani0 to ani7, ani16 to ani19 (t a = -40 to +85c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v dd , reference voltage (-) = v ss) parameter symbol conditions min. typ. max. unit resolution r es 81 0 b i t overall error note 1 ainl 10-bit resolution 2.7 v v dd 5.5 v 1.2 7.0 lsb conversion time t conv 10-bit resolution 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s zero-scale error notes 1, 2 ezs 10-bit resolution 2.7 v v dd 5.5 v 0.60 % fsr full-scale error notes 1, 2 efs 10-bit resolution 2.7 v v dd 5.5 v 0.60 % fsr integral linearity error note 1 ile 10-bit resolution 2.7 v v dd 5.5 v 4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.7 v v dd 5.5 v 2.0 lsb analog input voltage v ain ani0 to ani7 0 v dd v ani16 to ani19 0 v dd v v bgr select internal reference voltage output, 2.7 v v dd 5.5 v, hs (high-speed main) mode 1.38 1.45 1.5 v
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 58 of 67 jul 31, 2014 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. (4) when av ref (+) = internal reference voltage (adrefp1 = 1, adrefp0 = 0), av ref (-) = av refm /ani1 (adrefm = 1), target ani pin: ani0 to ani7, ani16 to ani19 (t a = -40 to +85c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v bgr , reference voltage (-) = av refm = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8b i t conversion time t conv 8-bit resolution 2.7 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 8-bit resolution 2.7 v v dd 5.5 v 0.60 % fsr integral linearity error note 1 ile 8-bit resolution 2.7 v v dd 5.5 v 2.0 lsb differential linearity error note 1 dle 8-bit resolution 2.7 v v dd 5.5 v 1.0 lsb reference voltage (+) v bgr 1.38 1.45 1.5 v analog input voltage v ain 0v bgr v
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 59 of 67 jul 31, 2014 2.7.2 temperature sensor characteristics 2.7.3 comparator note 1. time required after the operation enable signal of the comparator has been changed (cmpnen = 0 1) until a state satisfying the dc and ac characteristics of the comparator is entered. note 2. enable operation of internal reference voltage generation (cvrem bit = 1; m = 0, 1) and wait for the operation stabilization wait time before enabling the co mparator output (cnoe bit = 1; n = 0, 1). (t a = -40 to +85c, 2.7 v v dd 5.5 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c1 . 0 5 v reference output voltage v const setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature -3.6 mv/ c operation stabilization wait time t amp 5 s (t a = -40 to +85c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage v iocmp 5 40 mv input voltage range v icmp 0v dd v internal reference voltage deviation ?v iref cmrvm register value: 7fh to 80h (m = 0, 1) 2 lsb other than above 1 lsb response time t cr , t cf input amplitude = 100 mv 70 150 ns operation stabilization time note 1 t cmp cmpnen = 0 1 pvddad = 3.3 to 5.5 v 1 s pvddad = 2.7 to 3.3 v 3 reference voltage stabilization wait time t vr cvre: 0 1 note 2 20 s input voltage v in output voltage v o +100 mv -100 mv comparator reference voltage t cr t cf
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 60 of 67 jul 31, 2014 2.7.4 programmable gain amplifier note time required after the pga operation has been enabled (pgaen = 1) until a state satisfying the dc and ac specifications of the pga is entered. 2.7.5 por circui t characteristics note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through setting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). (t a = -40 to +85c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage v iopga 5 10 mv input voltage range v ipga 0 0.9 v dd /gain v response time v ohpga 0.9 v dd v v olpga 0.1 v dd gain error ? 4, 8 times 1 % 16 times 1.5 32 times 2 slew rate sr rpga rising edge 4.0 v v dd 5.5 v 1.4 v/ s 2.7 v v dd 4.0 v 0.5 sr fpga falling edge 4.0 v v dd 5.5 v 1.4 2.7 v v dd 4.0 v 0.5 operation stabilization wait time note t pga 4, 8 times 5 s 16, 32 times 10 (t a = -40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v por power supply rise time 1.47 1.51 1.55 v v pdr power supply fall time 1.46 1.50 1.54 v minimum pulse width note t pw 300 s t pw v por v pdr or 0.7 v supply voltage (v dd )
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 61 of 67 jul 31, 2014 2.7.6 lvd circui t characteristics remark v lvd (n - 1) > v lvdn : n = 1 to 5 (t a = -40 to +85 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage supply voltage level v lvd0 power supply rise time 3.98 4.06 4.14 v power supply fall time 3.90 3.98 4.06 v v lvd1 power supply rise time 3.68 3.75 3.82 v power supply fall time 3.60 3.67 3.74 v v lvd2 power supply rise time 3.07 3.13 3.19 v power supply fall time 3.00 3.06 3.12 v v lvd3 power supply rise time 2.96 3.02 3.08 v power supply fall time 2.90 2.96 3.02 v v lvd4 power supply rise time 2.86 2.92 2.97 v power supply fall time 2.80 2.86 2.91 v v lvd5 power supply rise time 2.76 2.81 2.87 v power supply fall time 2.70 2.75 2.81 v minimum pulse width t lw 300 s detection delay time t ld 300 s
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 62 of 67 jul 31, 2014 2.7.7 power supply voltage ri sing slope characteristics caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 2.5 ac characteristics. lvd detection voltage of interrupt & reset mode (t a = -40 to +85 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit interrupt and reset mode v lvd5 v poc2 , v poc1 , v poc0 = 0, 1, 1, falling reset voltage: 2.7 v 2.70 2.75 2.81 v v lvd4 lvis1, lvis0 = 1, 0 (+0.1 v) rising release reset voltage 2.86 2.92 2.97 v falling interrupt voltage 2.80 2.86 2.91 v v lvd3 lvis1, lvis0 = 0, 1 (+0.2 v) rising release reset voltage 2.96 3.02 3.08 v falling interrupt voltage 2.90 2.96 3.02 v v lvd0 lvis1, lvis0 = 0, 0 (+1.2 v) rising release reset voltage 3.98 4.06 4.14 v falling interrupt voltage 3.90 3.98 4.06 v (t a = -40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 63 of 67 jul 31, 2014 2.8 ram data retention characteristics note this depends on the por detection voltage. for a falling voltage, data in ram are retained until the voltage reaches the level that triggers a por reset but not once it reac hes the level at which a por reset is generated. 2.9 flash memory programming characteristics note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. note 2. when using flash memory programmer and renes as electronics self programming library. note 3. these specifications show t he characteristics of the flash memory and the results obtained from renesas electronics reliability testing. remark when updating data multiple times, use t he flash memory as one for updating data. 2.10 dedicated flash memory programmer communication (uart) (t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.46 note 5.5 v (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.7 v v dd 5.5 v 1 24 mhz number of code flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85c note 3 1,000 times (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115.2 k 1 m bps v dd stop instruction execution standby release signal (interrupt request) stop mode ram date retention mode operation mode v dddr
rl78/g1g 2. electr ical specifications r01ds0241ej0100 rev. 1.00 page 64 of 67 jul 31, 2014 2.11 timing for switching flas h memory programming modes <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial comm unication settings within 100 ms from when the external resets end. t su : how long from when the tool0 pin is placed at the low level until a pin reset ends t hd: how long to keep the tool0 pin at the low level from when the external resets end (the flash firmware proc essing time is excluded) (t a = -40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must end before the external reset ends. 1ms reset tool0 <1> <2> <3> t su <4> t suinit 723 s + t hd processing time 00h reception (toolrxd, tooltxd mode)
rl78/g1g 3. package drawings r01ds0241ej0100 rev. 1.00 page 65 of 67 jul 31, 2014 3. package drawings 3.1 30-pin products r5f11ea8asp, r5f11eaaasp jeita package code renesas code previous code mass (typ.) [g] p-lssop30-0300-0.65 plsp0030jb-b s30mc-65-5a4-3 0.18 s s h j t i g d e f c b k p l u n item b c i l m n a k d e f g h j p 30 16 11 5 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1p 0.2 0.10 9.85p 0.15 0.17p 0.03 0.1p 0.05 0.24 1.3p 0.1 8.1p 0.2 1.2 0.08 0.07 1.0p 0.2 3 o 5 o 3 o 0.25 0.6p 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition.
rl78/g1g 3. package drawings r01ds0241ej0100 rev. 1.00 page 66 of 67 jul 31, 2014 3.2 32-pin products r5f11eb8afp, r5f11ebaafp 0.145 0.055 (unit:mm) item dimensions d e hd he a a1 a2 7.00 0.10 7.00 0.10 9.00 0.20 9.00 0.20 1.70 max. 0.10 0.10 1.40 c e x y 0.80 0.20 0.10 l 0.50 0.20 0 to 8 0.37 0.05 b note 1.dimensions 1 and 2 do not include mold flash. 2.dimension 3 does not include trim offset. y e xb m l c hd he a1 a2 a d e detail of lead end 8 16 1 32 9 17 25 24 2 1 3 jeita package code renesas code previous code mass (typ.) [g] p-lqfp32-7x7-0.80 plqp0032gb-a p32ga-80-gbt-1 0.2
rl78/g1g 3. package drawings r01ds0241ej0100 rev. 1.00 page 67 of 67 jul 31, 2014 3.3 44-pin products r5f11ef8afp, r5f11efaafp jeita package code renesas code previous code mass (typ.) [g] p-lqfp44-10x10-0.80 plqp0044gc-a p44gb-80-ues-2 0.36 s y e sxb m q l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 0.055 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00p 0.20 10.00p 0.20 12.00p 0.20 12.00p 0.20 1.60 max. 0.10p 0.05 1.40p 0.05 0.25 c q e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.50 0.60p 0.15 1.00p 0.20 3 o 5 o 3 o note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 0.37 0.08 0.07 b 11 22 1 44 12 23 34 33
c - 1 rl78/g1g datasheet rev. date description page summary 1.00 jul 31, 2014 ? first edition issued all trademarks and registered trademarks are the property of their respective owners. revision history
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the corre ct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device.
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