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- 1 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers ACT8865 features ? three step-down dc/dc converters ? four low-dropout linear regulators ? i 2 c tm serial interface ? advanced enable/disable sequencing controller ? minimal external components ? tiny 44mm tqfn44-32 package ? 0.75mm package height ? pb-free and rohs compliant general description the ACT8865 is a complete, cost effective, highly- efficient activepmu tm power management solution, optimized for the unique power, voltage- sequencing, and control r equirements of the atmel sama5d3 series: sama5d[31/33/34/35/36] and sam9 series:sam9g[15/25/35/45/46];sam9x[25/35], sam9m[10/11], sam9n[11/12] processors. it is ideal for a wide range of high performance portable handheld applications such as human-machine interfaces, control panels, smart grid infrastructures, network gateways, m2m systems, 2d barcode scanners, barcode printers, machine vision equipment, as well as home and commercial building automations, pos terminals, medical devices and white goods. this device features three step-down dc/dc converters and four low-noise, low-dropout linear regulators. the three dc/dc converters utilize a high- efficiency, fixed-frequency (2mhz), current-mode pwm control architecture that requires a minimum number of external components. two dc/dcs are capable of supplying up to 1150ma of output current, while the third supports up to 1300ma. all four low-dropout linear regulators are high- performance, low-noise, regulators that supply up to 320ma. the ACT8865 is available in a compact, pb-free and rohs-compliant tqfn44-32 package. typical application diagram rev 2, 11-feb-14 advanced pmu for atmel sama5d3 series & sam9 series processors ACT8865 npbin reg1 reg2 reg3 reg4 reg5 reg6 reg7 sda nrsto nirq npbstat 1.2v 3.3v vddioddr etc. vddiop etc. vddfuse vddana auxiliary 1 auxiliary 1 twd twck gpio fiq/irq nrst 1.8v 1150ma 1150ma 1300ma 320ma 320ma 320ma 320ma push button scl atmel sama5dx vddcore_gbit enet etc.
ACT8865 rev 2, 11-feb-14 - 2 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers table of contents general info rmation ........................................................................................................... .......................... p. 01 functional block diagram ...................................................................................................... ...................... p. 03 ordering in formation .......................................................................................................... .......................... p. 04 pin config uration ............................................................................................................. ............................ p. 04 pin descrip tions .............................................................................................................. ............................. p. 05 absolute maxi mum ratings ...................................................................................................... ................... p. 07 i 2 c interface electrical characteristics ........................................................................................ ................ p. 08 global regist er map ........................................................................................................... ......................... p. 09 register and bit descriptions ................................................................................................. ..................... p. 10 system control electric al characteristics ..................................................................................... ............... p. 14 step-down dc/dc electric al characteristics .................................................................................... .......... p. 15 low-noise ldo electric al characteristics ...................................................................................... ............. p. 16 typical performance characteristics ........................................................................................... ................ p. 17 system control information .................................................................................................... ...................... p. 21 control si gnals ............................................................................................................... .................. p. 21 push-button control ........................................................................................................... .............. p. 22 control sequ ences(1) .......................................................................................................... ............ p. 23 functional de scription ........................................................................................................ ......................... p. 24 i 2 c interf ace ................................................................................................................... .................. p. 24 voltage monitor and interrupt ........................................................................................................... p. 24 thermal s hutdown .............................................................................................................. ............. p. 24 step-down dc/d c regulators .................................................................................................... ................ p. 25 general description .......................................................................................................................... p. 2 5 100% duty cycl e operat ion ..................................................................................................... ........ p. 25 synchronous re ctification ..................................................................................................... ........... p. 25 soft-start .................................................................................................................... ...................... p. 25 compensation .................................................................................................................. ................ p. 25 configuration options ....................................................................................................................... p. 25 ok[ ] and output f ault interrupt .............................................................................................. ......... p. 25 pcb layout considerations .......................................................................................... ................... p. 26 low-noise, low-dropout linear regulators ................................................................................................ p. 27 general description .......................................................................................................................... p. 2 7 output curr ent limit .......................................................................................................... ............... p. 27 compensation .................................................................................................................. ................ p. 27 configuration options ....................................................................................................................... p. 27 ok[ ] and output f ault interrupt .............................................................................................. ......... p. 27 pcb layout considerations .......................................................................................... ................... p. 28 tqfn44-32 package out line and dime nsions ...................................................................................... ..... p. 29 revision hi story .............................................................................................................. ............................. p. 30
ACT8865 rev 2, 11-feb-14 - 3 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers reg2 reg1 reg3 functional block diagram
ACT8865 rev 2, 11-feb-14 - 4 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers refbp npbin pwrhld vp3 sw3 gp3 npbstat nirq nrsto vp2 sw2 gp2 sw1 vp1 nc2 gp1 pin configuration thin - qfn (tqfn44-32) ordering information : all active-semi components are rohs compliant and with pb-free plating unless specified differently. the term pb-free means semiconductor products that are in compliance with current rohs (restriction of haza rdous substances) standards. : standard product options are identified in this table. contac t factory for custom options, minimum order quantity is 12,000 u nits. : to select v stbyx as a output regulation voltage of regx , drive vsel to a logic high. the v stbyx can be set by software via i 2 c interface, refer to appropriate sections of this datasheet for v stbyx setting. : v out2 = 1.2v @vsel=0 and v out2 = 1.0v @vsel=vin part number v out1 v out2 v out3 v out4 v out5 v out6 v out7 package pins temperature range ACT8865qi303-t 1.8v 1.2v 3.3v 0.6v 0.6v 0.6v 0.6v tqfn44-32 32 -40c to +85c top view
ACT8865 rev 2, 11-feb-14 - 5 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers pin descriptions pin name description 1 out1 output feedback sense for reg1. connect this pi n directly to the output node to connect the internal feedback network to the output voltage. 2 ga analog ground. connect ga directly to a quiet ground node. connect ga, gp1,gp2 and gp3 together at a single point as close to the ic as possible. 3 out4 output voltage for reg4. capable of delivering up to 320ma of output current. connect a 3.3f ceramic capacitor from out4 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 4 out5 output voltage for reg5. capable of delivering up to 320ma of output current. connect a 3.3f ceramic capacitor from out5 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 5 inl45 power input for reg4 and reg5. bypass to ga wi th a high quality ceramic capacitor placed as close to the ic as possible. 6 inl67 power input for reg6 and reg7. bypass to ga wi th a high quality ceramic capacitor placed as close to the ic as possible. 7 out6 output voltage for reg6. capable of delivering up to 320ma of output current. connect a 3.3f ceramic capacitor from out6 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 8 out7 output voltage for reg7. capable of delivering up to 320ma of output current. connect a 3.3f ceramic capacitor from out7 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 9 npbin master enable input. drive npbin to ga through a 50k ? resistor to enable the ic, drive npbin directly to ga to a ssert a manual reset condition. refer to the npbin multi-function input section for more information. npbin is internally pulled up to v vddref through a 35k ? resistor. 10 pwrhld power hold input. refer to the control sequences section for more information. 11 nrsto active low reset output. see the nrsto output section for more information. 12 nirq open-drain interrupt output. nirq asserts any time an unmasked fault condition exists or an interrupt occurs. see the nirq output section for more information. 13 npbstat active-low open-drain push-button status ou tput. npbstat is asse rted low whenever the npbin is pushed, and is high-z otherwise. see the npbstat output section for more information. 14 gp3 power ground for reg3. connect ga, gp1, gp2, and gp3 together at a single point as close to the ic as possible. 15 sw3 switching node output for reg3. connect th is pin to the switching end of the inductor. 16 vp3 power input for reg3. bypass to gp 3 with a high quality ceramic capacitor placed as close to the ic as possible. 17 pwren power enable input. refer to the control sequences section for more information. 18 nc1 not connected. not internally connected. 19 out3 output feedback sense for reg3. connect this pi n directly to the output node to connect the internal feedback network to the output voltage. 20 vsel step-down dc/dcs output voltage selection. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. see the output voltage programming section for more information. 21 scl clock input for i 2 c serial interface. 22 sda data input for i 2 c serial interface. data is read on the rising edge of scl.
ACT8865 rev 2, 11-feb-14 - 6 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers pin descriptions cont?d pin name description 25 nc2 not connected. not internally connected. 26 vp2 power input for reg2 and system control. bypass to gp2 with a high quality ceramic capacitor placed as close to the ic as possible. 27 sw2 switching node output for reg2. connect th is pin to the switching end of the inductor. 28 gp2 power ground for reg2. connect ga, gp1,gp2 and gp3 together at a single point as close to the ic as possible. 29 gp1 power ground for reg1. connect ga, gp1,gp2 and gp3 together at a single point as close to the ic as possible. 30 sw1 switching node output for reg1. connect th is pin to the switching end of the inductor. 31 vp1 power input for reg1. bypass to gp1 with a high quality ceramic capacitor placed as close to the ic as possible. 32 refbp reference bypass. connect a 0.047 f ceramic capacitor from refbp to ga. this pin is discharged to ga in shutdown. ep ep exposed pad. must be soldered to ground on pcb. 24 out2 output feedback sense for reg2. connect this pi n directly to the output node to connect the internal feedback network to the output voltage. 23 vddref power supply for the internal reference. connect this pin directly to the system power supply. bypass vddref to ga with a 100nf capacitor placed as close to the ic as possible. star connection with vp1, vp2 and vp3 preferred.
ACT8865 rev 2, 11-feb-14 - 7 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers absolute maximum ratings : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rati ng conditions for long periods m ay affect device reliability. parameter value unit vp1 to gp1, vp2 to gp2, vp3 to gp3 -0.3 to + 6 v inl, vddref to ga -0.3 to + 6 v npbin, scl, sda, refbp, pwrhld, pwren, vsel to ga -0.3 to (v vddref + 0.3) v nrsto, nirq, npbstat to ga -0.3 to + 6 v sw1, out1 to gp1 -0.3 to (v vp1 + 0.3) v sw2, out2 to gp2 -0.3 to (v vp2 + 0.3) v sw3, out3 to gp3 -0.3 to (v vp3 + 0.3) v out4, out5, out6, out7 to ga -0.3 to (v inl + 0.3) v gp1, gp2, gp3 to ga -0.3 to + 0.3 v junction to ambient thermal resistance ( ja ) 27.5 c/w operating ambient temper ature -40 to 85 c maximum junction temperature 125 c storage temperature -65 to 150 c lead temperature (soldering, 10 sec) 300 c
ACT8865 rev 2, 11-feb-14 - 8 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers figure 1: i 2 c compatible serial bus timing (v vp1 = v vp2 = v vp3 = 3.6v, t a = 25c, unless otherwise specified.) i 2 c interface electrical characteristics sda scl t st t su t hd t sp t scl start condition stop condition parameter test conditions min typ max unit scl, sda input low v vddref = 3.1v to 5.5v, t a = -40oc to 85oc 0.35 v scl, sda input high v vddref = 3.1v to 5.5v, t a = -40oc to 85oc 1.55 v sda leakage current 1 a sda output low i ol = 5ma 0.35 v scl clock period, t scl 1.5 s sda data setup time, t su 100 ns sda data hold time, t hd 300 ns start setup time, t st for start condition 100 ns stop setup time, t sp for stop condition 100 ns scl leakage current 1 2 a
ACT8865 rev 2, 11-feb-14 - 9 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers global register map output address bits d7 d6 d5 d4 d3 d2 d1 d0 sys 0x00 name trst nsysmode nsyslevmsk nsysstat syslev[3] syslev[2] syslev[1] syslev[0] default 1 1 0 r 0 1 1 1 sys 0x01 name reserved reserved mstroff reserved scratch scratch reserved scratch default 0 0 0 0 0 0 0 0 reg1 0x20 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default 0 0 1 0 0 1 0 0 reg1 0x21 name reserved reserved vset2[5] vset2[4] vset2[3] vset2[2] vset2[1] vset2[0] default 0 0 1 0 0 1 0 0 reg1 0x22 name on phase mode delay[2] delay[1] delay[0] nfltmsk ok default 0 0 1 0 0 1 0 r reg2 0x30 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default 0 0 0 1 1 0 0 0 reg2 0x31 name reserved reserved vset2[5] vset2[4] vset2[3] vset2[2] vset2[1] vset2[0] default 0 0 0 1 0 0 0 0 reg2 0x32 name on phase mode delay[2] delay[1] delay[0] nfltmsk ok default 0 0 1 0 1 0 0 r reg3 0x40 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default 0 0 1 1 1 0 0 1 reg3 0x41 name reserved reserved vset2[5] vset2[4] vset2[3] vset2[2] vset2[1] vset2[0] default 0 0 1 1 1 0 0 1 reg3 0x42 name on pwrstat mode delay[2] delay[1] delay[0] nfltmsk ok default 0 0 1 0 0 0 0 r reg4 0x50 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 0 0 0 0 0 0 reg4 0x51 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 0 0 0 r reg5 0x54 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 0 0 0 0 0 0 reg5 0x55 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 0 0 0 r reg6 0x60 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 0 0 0 0 0 0 reg6 0x61 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 0 0 0 r reg7 0x64 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 0 0 0 0 0 0 reg7 0x65 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 0 0 0 r : default values of ACT8865qi303-t. 2 : all bits are automatically cleared to default values when t he input power is removed or falls below the system uvlo.
ACT8865 rev 2, 11-feb-14 - 10 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions table 1: global register map output address bit name access description sys 0x00 [7] trst r/w reset timer setting. defines the reset timeout threshold. see nrsto output section for more information. sys 0x00 [6] nsysmode r/w syslev mode select. defines the response to the syslev voltage detector, 1: g enerate an interrupt when v vddref falls below the programmed syslev th reshold, 0: automatic shutdown when v vddref falls below the programmed syslev threshold. sys 0x00 [5] nsyslevmsk r/w system voltage level interrupt mask. disabled interrupt by default, set to 1 to enable this interrupt. see the programmable system voltage monitor section for more information sys 0x00 [4] nsysstat r system voltage status. value is 1 when v vddref is lower than the syslev voltage threshold, value is 0 when v vddref is higher than the system voltage detection threshold. sys 0x00 [3:0] syslev r/w system voltage detect thres hold. defines the syslev voltage threshold. see the programmable system voltage monitor section for more information. sys 0x01 [7:6] - r reserved. sys 0x01 [5] mstroff r/w master off control. set bit to 1 to turn off all regulators. the bit will be automatically cleared to 0 when npbin is asserted. sys 0x01 [4] - r reserved. sys 0x01 [3:1] scratch r/w scratchpad bits. non-functional bits, maybe be used by user to store system status information. volatile bits, which are cleared upon system shutdown. sys 0x01 [0] scratch r/w scratchpad bits. non-functional bits, maybe be used by user to store system status information. volatile bits, which are cleared upon system shutdown. reg1 0x20 [7:6] - r reserved. reg1 0x20 [5:0] vset1 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information. reg1 0x21 [7:6] - r reserved. reg1 0x21 [5:0] vset2 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg1 0x22 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg1 0x22 [6] phase r/w regulator phase control. set bit to 1 for regulator to operate 180 out of phase with the oscillator, clear bit to 0 for regulator to operate in phase with the oscillator. reg1 0x22 [5] mode r/w regulator mode select. set bi t to 1 for fixed-frequency pwm under all load conditions, clear bit to 0 to transit to power-savings mode under light-load conditions. reg1 0x22 [4:2] delay r/w regulator turn-on delay control. see the reg1, reg2, reg3 turn-on delay section for more information. reg1 0x22 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts.
ACT8865 rev 2, 11-feb-14 - 11 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions cont?d output address bit name access description reg1 0x22 [0] ok r/w regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg2 0x30 [7:6] - r reserved. reg2 0x30 [5:0] vset1 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information. reg2 0x31 [7:6] - r reserved. reg2 0x31 [5:0] vset2 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg2 0x32 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg2 0x32 [6] phase r/w regulator phase control. set bit to 1 for regulator to operate 180 out of phase with the oscillator, clear bit to 0 for regulator to operate in phase with the oscillator. reg2 0x32 [5] mode r/w regulator mode select. set bi t to 1 for fixed-frequency pwm under all load conditions, clear bit to 0 to transit to power- savings mode under light-load conditions. reg2 0x32 [4:2] delay r/w regulator turn-on delay control. see the reg1, reg2, reg3 turn-on delay section for more information. reg2 0x32 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts. reg2 0x32 [0] ok r/w regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg3 0x40 [7:6] - r reserved. reg3 0x40 [5:0] vset1 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information. reg3 0x41 [7:6] - r reserved. reg3 0x41 [5:0] vset2 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg3 0x42 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg3 0x42 [6] pwrstat r/w configures regulator behavior with respect to the npbin input. set bit to 0 to enable regulator when npbin is asserted. reg3 0x42 [5] mode r/w regulator mode select. set bi t to 1 for fixed-frequency pwm under all load conditions, clear bit to 0 to transition to power- savings mode under light-load conditions. reg3 0x42 [4:2] delay r/w regulator turn-on delay control. see the reg1, reg2, reg3 turn-on delay section for more information. reg3 0x42 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts. reg3 0x42 [0] ok r/w regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg4 0x50 [7:6] - r reserved. reg4 0x50 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg4 0x51 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator.
ACT8865 rev 2, 11-feb-14 - 12 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions cont?d output address bit name access description reg4 0x51 [6] dis r/w output discharge control. when activated, discharges ldo output to ga through 1.5k ? when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg4 0x51 [5] lowiq r/w ldo low-iq mode control. set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. reg4 0x51 [4:2] delay r/w regulator turn-on delay control. see the reg4, reg5, reg6, reg7 turn-on delay section for more information. reg4 0x51 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts. reg4 0x51 [0] ok r/w regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg5 0x54 [7:6] - r reserved. reg5 0x54 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg5 0x55 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg5 0x55 [6] dis r/w output discharge control. when activated, discharges ldo output to ga through 1.5k ? when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg5 0x55 [5] lowiq r/w ldo low-iq mode control. set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. reg5 0x55 [4:2] delay r/w regulator turn-on delay control. see the reg4, reg5, reg6, reg7 turn-on delay section for more information. reg5 0x55 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts. reg5 0x55 [0] ok r/w regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg6 0x60 [7:6] - r reserved. reg6 0x60 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg6 0x61 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg6 0x61 [6] dis r/w output discharge control. when activated, discharges ldo output to ga through 1.5k ? when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg6 0x61 [5] lowiq r/w ldo low-iq mode control. set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. reg6 0x61 [4:2] delay r/w regulator turn-on delay control. see the reg4, reg5, reg6, reg7 turn-on delay section for more information. reg6 0x61 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts. reg6 0x61 [0] ok r/w regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg7 0x64 [7:6] - r reserved. reg7 0x64 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg7 0x65 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator.
ACT8865 rev 2, 11-feb-14 - 13 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions cont?d output address bit name access description reg7 0x65 [5] lowiq r/w ldo low-iq mode control. set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. reg7 0x65 [4:2] delay r/w regulator turn-on delay control. see the reg4, reg5, reg6, reg7 turn-on delay section for more information. reg7 0x65 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable to fault- interrupts, clear bit to 0 to disable fault-interrupts. reg7 0x65 [0] ok r/w regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg7 0x65 [6] dis r/w output discharge control. when activated, discharges ldo output to ga through 1.5k ? when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function.
ACT8865 rev 2, 11-feb-14 - 14 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers system control electr ical characteristics (v vp1 = v vp2 = v vp3 = 3.6v, t a = 25c, unless otherwise specified.) : pwrhld, pwren, vsel are logic inputs. 2 : npbstat, nirq, nrsto are open drain outputs. 3 : typical value shown. actual value may vary from 56.3ms to 72.8ms. parameter test conditions min typ max unit input voltage range 2.7 5.5 v uvlo threshold voltage v vddref rising 2.2 2.45 2.65 v uvlo hysteresis v vddref falling 200 mv reg1, reg2, reg3 enabled. reg4 reg5, reg6 and reg7 disabled. 13.85 ma reg1, reg2, reg3, reg4, reg5, reg6 and reg7 enabled. (pwm mode) 14 reg1, reg2, reg3, reg4, reg5, reg6 and reg7 enabled. (pfm mode, v in = 3.6v) 420 a shutdown supply current all regulators disabled 1.5 3.0 a oscillator frequency 1.8 2 2.2 mhz logic high input voltage 1 1.4 v logic low input voltage 0.4 v leakage current v nirq = v nrsto = 4.2v 1 a low level output voltage 2 i sink = 5ma 0.35 v nrsto delay 64 ms thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis 20 c supply current
ACT8865 rev 2, 11-feb-14 - 15 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers step-down dc/dc electrical characteristics (v vp1 = v vp2 = v vp3 = 3.6v, t a = 25c, unless otherwise specified.) : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. 2 : imax maximum output current. parameter conditions min typ max unit operating voltage range 2.7 5.5 v uvlo threshold input volt age rising 2.5 2.6 2.7 v uvlo hysteresis input voltage falling 100 mv regulator enabled (pwm mode) 4.5 7.0 ma regulator enabled (pfm mode) 65 a shutdown current v vp = 5.5v, regulator disabled 0 1 a output voltage accuracy v out 1.2v, i out = 10ma -1% v nom 1% v v out < 1.2v, i out = 10ma -2% v nom 2% line regulation v vp = max(v nom 1 +1, 3.2v) to 5.5v 0.15 %/v load regulation i out = 10ma to imax 2 0.0017 %/ma power good threshold v out rising 93 %v nom power good hysteresis v out falling 2 %v nom oscillator frequency v out 20% of v nom 1.8 2 2.2 mhz v out = 0v 500 khz soft-start period 400 s minimum on-time 75 ns reg1 maximum output current 1.15 a current limit 1.5 1.8 2.1 a pmos on-resistance i sw1 = -100ma 0.16 ? nmos on-resistance i sw1 = 100ma 0.16 ? sw1 leakage current v vp1 = 5.5v, v sw1 = 0 or 5.5v 1 a reg2 maximum output current 1.15 a current limit 1.5 1.8 2.1 a pmos on-resistance i sw2 = -100ma 0.16 ? nmos on-resistance i sw2 = 100ma 0.16 ? sw2 leakage current v vp2 = 5.5v, v sw2 = 0 or 5.5v 1 a reg3 maximum output current 1.30 a current limit 1.7 2.1 2.5 a pmos on-resistance i sw3 = -100ma 0.16 ? nmos on-resistance i sw3 = 100ma 0.16 ? sw3 leakage current v vp3 = 5.5v, v sw3 = 0 or 5.5v 0 1 a quiescent supply current
ACT8865 rev 2, 11-feb-14 - 16 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers low-noise ldo electri cal characteristics (v inl = 3.6v, c out4 = c out5 = 1.5f, c out6 = c out7 = 3.3f, lowiq[ ] = [0], t a = 25c, unless otherwise specified.) : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. 2 : imax maximum output current. 3 : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage (for 3.1v output voltage or higher) : ldo current limit is defined as the output current at which th e output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 30% (typ) parameter test conditions min typ max unit operating voltage range 2.5 5.5 v output voltage accuracy v out 1.2v, t a = 25c, i out = 10ma -1% v nom 2% v v out < 1.2v, t a = 25c, i out = 10ma -2% v nom 4% line regulation v inl = max (v out + 0.5v, 3.6v) to 5.5v 0.05 v inl = max (v out + 0.5v, 3.6v) to 5.5v lowiq[ ] = [1] 0.5 load regulation i out = 1ma to imax 2 0.08 v/a power supply rejection ratio f = 1khz, i out = 20ma, v out =1.2v 75 db f = 10khz, i out = 20ma, v out =1.2v 65 supply current per output regulator enabled, low iq[ ] = [0] 37 60 a regulator enabled, low iq[ ] = [1] 31 52 regulator disabled 0 1 soft-start period v out = 2.9v 140 s power good threshold v out rising 89 % power good hysteresis v out falling 3 % output noise i out = 20ma, f = 10hz to 100khz, v out = 1.2v 50 v rms discharge resistance ldo disabled, dis[ ] = 1 1.5 k ? reg4 dropout voltage i out = 160ma, v out > 3.1v 90 180 mv maximum output current 320 ma current limit v out = 95% of regulation voltage 400 ma stable c out4 range 3.3 20 f reg5 dropout voltage i out = 160ma, v out > 3.1v 140 280 mv maximum output current 320 ma current limit v out = 95% of regulation voltage 400 ma stable c out5 range 3.3 20 f reg6 dropout voltage i out = 160ma, v out > 3.1v 90 180 mv maximum output current 320 ma current limit v out = 95% of regulation voltage 400 ma stable c out6 range 3.3 20 f reg7 dropout voltage i out = 160ma, v out > 3.1v 140 280 mv maximum output current 320 ma current limit v out = 95% of regulation voltage 400 ma stable c out7 range 3.3 20 f mv/v
ACT8865 rev 2, 11-feb-14 - 17 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers typical performanc e characteristics (v vp1 = v vp2 = v vp3 = 3.6v, t a = 25c, unless otherwise specified.) temperature (c) -40 -20 0 20 40 60 80 100 120 ACT8865-001 v ref vs. temperature v ref (%) ACT8865-002 frequency vs. temperature frequency (%) temperature (c) -40 -20 0 20 40 60 80 85 typical oscillator frequency=2mhz typical v ref =1.2v 0.84 0.42 0 -0.42 -0.84 2.5 2 1.5 1 0.5 0 -0.5 -1 npbin startup sequence ACT8865-003 ch1: v npbin , 2v/div ch2: v out3 , 2v/div ch3: v out1 , 1v/div ch4: v out2 , 1v/div time: 1ms/div ch1 ch2 ch3 ch4 pwrhld startup sequence ACT8865-004 ch1 ch2 ch3 ch4 ch1: v pwrhld , 2v/div ch2: v out3 , 2v/div ch3: v out1 , 1v/div ch4: v out2 , 1v/div time: 1ms/div pwren startup sequence ACT8865-005 ch1 ch2 ch3 ch4 ch1: v pwren , 2v/div ch2: v out4 , 500mv/div ch3: v out5 , 500mv/div ch4: v out6 , 500mv/div ch5: v out7 , 500mv/div time: 1ms/div ch5
ACT8865 rev 2, 11-feb-14 - 18 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers ACT8865-006 push-button response (first power-up) (t a = 25c, unless otherwise specified.) typical performance ch aracteristics cont?d ch1 ch2 ch3 manual reset response ch1 ch2 ch3 ACT8865-007 ch1: v npbin , 2v/div ch2: v npbstat , 2v/div ch3: v nrsto , 2v/div time: 20ms/div npbin resistor = 50k ? ch1: v npbin , 2v/div ch2: v npbstat , 2v/div ch3:v nrsto , 2v/div time: 30ms/div npbin resistor = 0 ? ACT8865-009 reg2 efficiency vs. output current efficiency (%) output current (ma) 1 10 100 1000 100 80 60 40 20 0 v out = 1.2v v in = 3.6v v in = 4.2v v in = 5.0v ACT8865-008 reg1 efficiency vs. output current 100 80 60 40 20 0 efficiency (%) output current (ma) 1 10 100 1000 v out = 1.8v v in = 3.6v v in = 4.2v v in = 5.0v ACT8865-010 reg3 efficiency vs. output current 100 80 60 40 20 0 efficiency (%) output current (ma) 1 10 100 1000 v out = 3.3v v in = 3.6v v in =5.0v v in = 4.2v
ACT8865 rev 2, 11-feb-14 - 19 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers (t a = 25c, unless otherwise specified.) typical performance ch aracteristics cont?d temperature (c) -40 -20 0 20 40 60 80 100 120 ACT8865-011 reg1 output voltage vs. temperature output voltage (v) 1.815 1.809 1.803 1.797 1.791 1.785 v out3 = 1.8v i load = 100ma temperature (c) -40 -20 0 20 40 60 80 100 120 ACT8865-012 reg2 output voltage vs. temperature output voltage (v) 3.310 3.306 3.302 3.298 3.294 3.290 v out2 = 3.3v i load = 100ma 1.210 1.206 1.202 1.198 1.194 1.190 temperature (c) -40 -20 0 20 40 60 80 100 120 ACT8865-013 reg3 output voltage vs. temperature output voltage (v) v out1 = 1.2v i load = 100ma ACT8865-014 reg1, 2, 3 mosfet resistance r dson (m ? ) input voltage (v) 3.0 3.5 4.0 4.5 5.0 5.5 300 250 200 150 100 50 0 350 i load = 100ma pmos nmos
ACT8865 rev 2, 11-feb-14 - 20 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers (t a = 25c, unless otherwise specified.) typical performance ch aracteristics cont?d ACT8865-016 reg4, 6 dropout voltage vs. output current dropout voltage (mv) 200 150 100 50 0 output current (ma) 0 50 100 150 200 250 300 350 ACT8865-017 reg5, 7 dropout voltage vs. output current dropout voltage (mv) 200 150 100 50 0 250 300 output current (ma) 0 50 100 150 200 250 300 350 ACT8865-015 4% 2% 0% -2% -4% -6% error percent (%) reg4, 5, 6, 7 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 400 v out 1.2v v out > 1.2v temperature (c) -40 -20 0 20 40 60 80 ACT8865-018 reg4, 5, 6, 7 output voltage vs. temperature 4% 2% 0% -2% -4% error percent (%) v out > 1.2v v out 1.2v esr ( ? ) act8945a-019 region of stable c out esr vs. output current 1 0.1 0.01 output current (ma) 0 50 100 250 200 150 stable esr act8945a-020 ldo output voltage noise ch1 ch1: v outx , 200v/div (ac coupled) time: 200ms/div
ACT8865 rev 2, 11-feb-14 - 21 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers system control information interfacing with the atmel sama5d 3 series & sam9 series processors the ACT8865 is optimized for use in applications using the following atmel platforms: sama5d3 series and sam9 series processors, supporting the power domains as shown in the following table: table 2: ACT8865 and atmel sama5d3 series & sam9 series power domains power domain ACT8865 channel type default voltage current capability vddioddr/vddcore_lpddr re g1 dc/dc 1.8v 1100ma vddcore_gbit enet, vddio_lpddr reg2 dc/dc 1.2v 1100ma vddiop, vddosc, vddutmii, vddiom,10/100 enet reg3 dc/dc 3.3v 1200ma vddfuse reg4 ldo 0.6v 320ma auxiliary 1 reg6 ldo 0.6v 320ma auxiliary 2 reg7 ldo 0.6v 320ma vddana reg5 ldo 0.6v 320ma : v out2 = 1.2v @ vsel=0 (sama5 series) and v out2 = 1.0v @ vsel=vin (sam9 series)
ACT8865 rev 2, 11-feb-14 - 22 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers system control information control signals enable inputs the ACT8865 features a variety of control inputs, which are used to enable and disable outputs depending upon the desired mode of operation. pwren, pwrhld are logic inputs, while npbin is a unique, multi-function input. refer to the processor specification fo r a description of which channels are controlled by each input. npbin multi-function input ACT8865 features the npbin multi-function pin, which combines system enable/disable control with a hardware reset function. select either of the two pin functions by asserting this pin, either through a direct connection to ga, or through a 50k ? resistor to ga, as shown in figure 2. figure 2: npbin input manual reset function the second major function of the npbin input is to provide a manual-reset input for the processor. to manually-reset the processor, drive npbin directly to ga through a low impedance (less than 2.5k ? ). when this occurs, nrsto immediately asserts low, then remains asserted low until the npbin input is de-asserted and the reset time-out period expires. npbstat output npbstat is an open-drain output that reflects the state of the npbin input; npbstat is asserted low whenever npbin is asserted, and is high-z otherwise. this output is typically used as an interrupt signal to the processor, to initiate a software-programmable routine such as operating mode selection or to open a menu. connect npbstat to an appropriate supply voltage (typically out3) through a 10k ? or greater resistor. nrsto output nrsto is an open-drain output which asserts low upon startup or when manual reset is asserted via the npbin input. when asserted on startup, nrsto remains low until reset time-out period expires after out3 reaches its power-ok threshold. when asserted due to manual-reset, nrsto immediately asserts low, then remains asserted low until the npbin input is de-asserted and the reset time-out period expires. connect a 10k ? or greater pull-up resistor from nrsto to an appropriate voltage supply (typically out3). nirq output nirq is an open-drain out put that asserts low any time an interrupt is generated. connect a 10k ? or greater pull-up resistor from nirq to an appropriate voltage supply. nirq is typi cally used to drive the interrupt input of the system processor. many of the ACT8865's f unctions support interrupt- generation as a result of various conditions. these are typically masked by default, but may be unmasked via the i 2 c interface. for more information about the available fault conditions, refer to the appropriate sections of this datasheet. note that under some conditions a false interrupt may be generated upon initial startup. for this reason, it is recommended that the interrupt service routine check and validate n syslevmsk[ - ] and nfltmsk[ - ] bits before processing an interrupt generated by these bits. these interrupts may be validated by nsysstat[ - ], ok[ - ] bits. push-button control the ACT8865 is designed to initiate a system enable sequence when the npbin multi-function input is asserted. once this occurs, a power-on sequence commences, as described below. the power-on sequence must complete and the microprocessor must take control (by asserting pwren or pwrhld) before npbin is de-asserted. if the microprocessor is unable to complete its power-up routine successf ully before the user releases the push-button, the ACT8865 automatically shuts the syst em down. this provides protection against accidental or momentary assertions of the push-button. if desired, longer ?push-and-hold? times can be implemented by simply adding an additional time delay before asserting pwren or pwrhld.
ACT8865 rev 2, 11-feb-14 - 23 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers control sequences the ACT8865 features a variety of control sequences that are optimiz ed for supporting system enable and disable sequences of atmel sama5d3 series: sama5d[31/33/34/35/36] and sam9 series: sam9g[15/25/35/45/46], sam9x[25/35], sam9m[10/11], sam9n[11/12] application processor. enabling/disabling sequence a typical enable sequence is initiated whenever npbin is asserted low via 50k ? resistance. the enable sequence begins by enabling reg3. when reg3 reaches its power-ok threshold, nrsto is asserted low, resetting t he microprocessor. when reg3 reaches its power-ok threshold for 2ms , reg1 is enabled. when reg3 reaches its power- ok threshold for 4ms , reg2 is enabled. when reg3 is above its power-ok threshold when the reset timer expires, nrsto is de-asserted, allowing the microprocessor to begin its boot sequence. reg4, reg5, reg6 and reg7 can be enabled or disabled by pwren after system powers up. during the boot sequence, the microprocessor must assert pwrhld, holding the regulators to ensure that the system remains powered after npbin is released. as with the enable sequence, a typical disable sequence is initiated when the user presses the push-button, which interrupts the processor via the npbstat output. the actual disable sequence is completely software-controlled, but typically involved initiating various ?clean-up? processes before finally set mstroff[] bit to 1 to shut the system down. : typical value shown, actual delay time may vary from (t-1ms ) x 88% to t x 112%, where t is the typical delay time setting. figure 3: ACT8865qi303-t enable/disable sequence
ACT8865 rev 2, 11-feb-14 - 24 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers i 2 c interface the ACT8865 features an i 2 c interface that allows advanced programming capability to enhance overall system performance. to ensure compatibility with a wide range of system processors, the i 2 c interface supports clock speeds of up to 400khz (?fast-mode? operation) and uses standard i 2 c commands. i 2 c write-byte commands are used to program the ACT8865, and i 2 c read-byte commands are used to read the ACT8865?s internal registers. the ACT8865 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read- operation or a write-operation, [1011011x]. sda is a bi-directional data line and scl is a clock input. the master device initiates a transaction by issuing a start condition, defined by sda transitioning from high to low while scl is high. data is transferred in 8-bit packets, beginning with the msb, and is clocked-in on the rising edge of scl. each packet of data is followed by an ?acknowledge? (ack) bit, used to confirm that the data was transmitted successfully. for more information regarding the i 2 c 2-wire serial interface, go to the nxp website: http://www.nxp.com. voltage monitor and interrupt programmable system voltage monitor the ACT8865 features a programmable system- voltage monitor, which monitors the voltage at vddref and compares it to a programmable threshold voltage. the programmable voltage threshold is programmed by syslev[3:0], as shown in table 3. syslev[ ] is set to 3.0v by default. there is a 200mv rising hysteresis on syslev[ ] threshold such that v vddref needs to be 3.2v(typ) or higher in order to power up the ic. the nsysstat[ - ] bit reflects the output of an internal voltage comparator that monitors vddref relative to the syslev[ - ] voltage threshold, the value of nsystat[ - ] = 1 when v vddref is lower than the syslev[ - ] voltage threshold, and nsystat[ - ] = 0 when v vddref is higher than the syslev[ - ] voltage threshold. note that the syslev[ - ] voltage threshold is defined for falling voltages, and that the comparator produces about 200mv of hysteresis at vddref. as a result, once v vddref falls below the syslev threshold, its voltage must increase by more than about 200mv to clear that condition. after the ic is powered up, the ACT8865 responds in one of two ways when the voltage at vddref falls below the syslev[ - ] voltage threshold: 1) if nsysmode[ - ] = 1 (default case), when system v o l t a g e l e v e l i n t e r r u p t i s u n m a s k e d (nsyslevmsk[ ]=1) and v vddref falls below the programmable threshold, the ACT8865 asserts nirq, providing a software ?under-voltage alarm?. the response to this interrupt is controlled by the cpu, but will typically initiate a controlled shutdown sequence either or alert the user that the battery is low. in this case the interrupt is cleared when v vddref rises up again above the syslev rising threshold and nsysstat[ - ] is read via i 2 c. 2) if nsysmode[ - ] = 0, when v vddref falls below the programmable threshold the ACT8865 shuts down, immediately disabling all regulators. this option is useful for implementing a programmable ?under- voltage lockout? function that forces the system off when the battery voltage falls below the syslev threshold voltage. since this option does not support a controlled shutdown sequence, it is generally used as a "fail-safe" to shut the system down when the battery voltage is too low. table 3: syslev falling threshold thermal shutdown the ACT8865 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. this circuitry disables all regulators if the ACT8865 die temperature exceeds 160c, and prevents the regulators from being enabled until the ic temperature drops by 20c (typ). syslev[3:0] syslev falling threshold (hysteresis = 200mv) 0000 2.3 0001 2.4 0010 2.5 0011 2.6 0100 2.7 0101 2.8 0110 2.9 0111 3.0 1000 3.1 1001 3.2 1010 3.3 1011 3.4 1100 3.5 1101 3.6 1110 3.7 1111 3.8 functional description
ACT8865 rev 2, 11-feb-14 - 25 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers general description the ACT8865 features three synchronous, fixed- frequency, current-mode pwm step down converters that achieve peak efficiencies of up to 97%. reg1 and reg2 are capable of supplying up to 1150ma of output current, while reg3 supports up to 1300ma. these regulators operate with a fixed frequency of 2mhz, minimizing noise in sensitive applications and allowing the use of small external components. 100% duty cycle operation each regulator is capable of operating at up to 100% duty cycle. during 100% duty-cycle operation, the high-side power mosfet is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. synchronous rectification reg1, reg2, and reg3 each feature integrated n- channel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the need for external rectifiers. soft-start when enabled, each output voltages tracks an internal 400 s soft-start ramp , minimizing input current during startup and allowing each regulator to power up in a smooth, monotonic manner that is independent of output load conditions. compensation each buck regulator utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. no compensation design is required; simply follow a few simple guidelines described below when choosing external components. input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 4.7 f ceramic capacitor is recommended for each regulator in most applications. output capacitor selection for most applications, 22 f ceramic output capacitors are recommended for reg1/reg2/ reg3. despite the advantages of ceramic capacitors, care must be taken during the design process to ensure stable operation over the full operating voltage and temperature range. ceramic capacitors are available in a variety of dielectrics, each of which exhibits different characteristics that can greatly affect performance over their temperature and voltage ranges. two of the most common dielectrics are y5v and x5r. whereas y5v dielectrics are inexpensive and can provide high capacitance in small packages, their capacitance varies greatly over their voltage and temperature ranges and are not recommended for dc/dc applications. x5r and x7r dielectrics are more suitable for output capacitor applications, as their characteristics are more stable over their operating ranges, and are highly recommended. inductor selection reg1, reg2, and reg3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. these devices were optimized for operation with 2.2 h inductors, although inductors in the 1.5 h to 3.3 h range can be used. choose an inductor with a low dc-resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current by at least 30%. enable / disable control during normal operation, each buck may be enabled or disabled via the i 2 c interface by writing to that regulator's on[ ] bit. to en able the regulator set on[ ] to 1, to disable the regulator clear on[ ] to 0. reg1, reg2, reg3 turn-on delay each of reg1/reg2/reg3 features a programmable turn-on delay which help ensure a reliable qualification. this delay is programmed by delay[2:0], as shown in table 5. operating mode reg1, reg2, and reg3 each operate in fixed- frequency pwm mode at medium to heavy loads when mode[ ] bit is set to 0, and transition to a proprietary power-saving mode at light loads in order to maximize standby battery life. in applications where low noise is critical, force fixed- frequency pwm operation across the entire load current range, at the expense of light-load efficiency, by setting the mode[ ] bit to 1. ok[ ] and output fault interrupt each dc/dc features a power-ok status bit that step-down dc/dc regulators
ACT8865 rev 2, 11-feb-14 - 26 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers can be read by the system microprocessor via the i 2 c interface. if an output voltage is lower than the power-ok threshold, typically 7% below the programmed regulation voltage, that regulator's ok[ ] bit will be 0. if a dc/dc's nfltmsk[ - ] bit is set to 1, the ACT8865 will interrupt the pr ocessor if that dc/dc's output voltage falls below the power-ok threshold. in this case, nirq will assert low and remain asserted until the ok[ ] bit has been read via i 2 c. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step- down dc/dc converter design. step-down dc/dcs exhibi t discontinuous input current, so the input capacitors should be placed as close as possible to the ic, and avoiding the use of via if possible. the inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator's power loop should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple via. the output node for each regulator should be connected to its corresponding outx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside ground plane using multiple via to achieve low electrical and thermal resistance. regx/vset[2:0] 000 001 010 011 100 101 110 111 000 0.600 0.800 1.000 1.200 1.600 2.000 2.400 3.200 001 0.625 0.825 1.025 1.250 1.650 2.050 2.500 3.300 010 0.650 0.850 1.050 1.300 1.700 2.100 2.600 3.400 011 0.675 0.875 1.075 1.350 1.750 2.150 2.700 3.500 100 0.700 0.900 1.100 1.400 1.800 2.200 2.800 3.600 101 0.725 0.925 1.125 1.450 1.850 2.250 2.900 3.700 110 0.750 0.950 1.150 1.500 1.900 2.300 3.000 3.800 111 0.775 0.975 1.175 1.550 1.950 2.350 3.100 3.900 regx/vset[5:3] table 4: regx/vset[ ] output voltage setting
ACT8865 rev 2, 11-feb-14 - 27 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers general description reg4, reg5, reg6 and reg7 are low-noise, low- dropout linear regulators (ldos) that supply up to 320ma. each ldo has been optimized to achieve low noise and high-psrr, achieving more than 65db psrr at frequencies up to 10khz. output current limit each ldo contains current-limit circuitry featuring a current-limit fold-back function. during normal and moderate overload conditions, the regulators can support more than their rated output currents. during extreme overload conditions, however, the current limit is reduced by approximately 30%, reducing power dissipation within the ic. compensation the ldos are internally compensated and require very little design effort, simply select input and output capacitors according to the guidelines below. input capacitor selection each ldo requires a small 1 f ceramic output capacitor for stability. fo r best performance, each output capacitor should be connected directly between the output and ga pins, as close to the output as possible, and with a short, direct connection. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. output capacitor selection each ldo requires a small 3.3 f ceramic output capacitor for stability. fo r best performance, each output capacitor should be connected directly between the output and ga pins, as close to the output as possible, and with a short, direct connection. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. configuration options output voltage programming by default, each ldo powers up and regulates to its default output voltage. once the system is enabled, each output voltage may be independently programmed to a different value by writing to the regulator's vset[ - ] register via the i 2 c serial interface as shown in table 4. enable / disable control during normal operation, each ldo may be enabled or disabled via the i 2 c interface by writing to that ldo's on[ ] bit. to enable the ldo set on[ ] to 1, to disable the ldo clear on[ ] to 0. reg4, reg5, reg6, reg7 turn-on delay each of reg4, reg5, reg6 and reg7 features a programmable turn-on delay which help ensure a reliable qualification. this delay is programmed by delay[2:0], as shown in table 5. table 5: regx/delay[ ] turn-on delay output discharge each of the ACT8865?s ldos features an optional output discharge function, which discharges the output to ground through a 1.5k ? resistance when the ldo is disabled. this feature may be enabled or disabled by setting dis[ - ] via; set dis[ - ] to 1 to enable this function, clear dis[ - ] to 0 to disable it. low-power mode each of ACT8865's ldos features a lowiq[ - ] bit which, when set to 1, reduces the ldo's quiescent current by about 16%, saving power and extending battery lifetime. ok[ ] and output fault interrupt each ldo features a power-ok status bit that can be read by the system mi croprocessor via the interface. if an output voltage is lower than the power-ok threshold, typically 11% below the programmed regulation voltage, the value of that regulator's ok[ - ] bit will be 0. if a ldo's nfltmsk[ - ] bit is set to 1, the ACT8865 will interrupt the processor if that ldo's output voltage falls below the power-ok threshold. in this case, nirq will assert low and remain asserted until the ok[ - ] bit has been read via i 2 c. low-noise, low-dropou t linear regulators delay[2] delay[1] delay[0] turn-on delay 0 0 0 0 ms 0 0 1 2 ms 0 1 0 4 ms 0 1 1 8 ms 1 0 0 16 ms 1 0 1 32 ms 1 1 0 64 ms 1 1 1 128 ms
ACT8865 rev 2, 11-feb-14 - 28 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers pcb layout considerations pcb layout considerations the ACT8865?s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. output traces should be routed to avoid close proximity to noisy nodes, particularly the sw nodes of the dc/dcs. refbp is a filtered reference noise, and internally has a direct connection to the linear regulator controller. any noise injected onto refbp will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via refbp. as with the ld o output capacitors, the refbp bypass capacitor should be placed as close to the ic as possible, with short, direct connections to the star-ground. avoid the use of via whenever possible. noisy nodes, such as from the dc/dcs, should be routed as far away from refbp as possible.
ACT8865 rev 2, 11-feb-14 - 29 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers tqfn44-32 package outline and dimensions symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.200 0.008 b 0.150 0.250 0.006 0.010 d 4.000 typ 0.158 typ e 4.000 typ d2 2.550 2.800 0.100 0.110 e2 2.550 2.800 0.100 0.110 e 0.400 typ 0.016 typ l 0.250 0.450 0.010 0.018 r 0.250 0.010 0.158 typ a3 d e e b l e/2 d2 e2 d/2 a a1 r
ACT8865 rev 2, 11-feb-14 - 30 - www.active-semi.com activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2014 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers active-semi, inc. reserves the right to modify the circuitry or specifications without notice. user s should evaluate each product to make sure that it is suitable for their applicat ions. active-semi products are not intended or authorized for use as critical components in life-support dev ices or systems. active-semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com . is a registered trademark of active-semi. revision history revision date description rev prb 20 jun 2013 initial release. rev 0 18 jul 2013 updated table 2. rev 1 01 aug 2013 updated general description and typical application diagram. rev 2 11 feb 2014 added the power consumption information of pfm mode in ec table.

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