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data sheet ics831742agi july 10, 2012 1 ?2012 integrated device technology, inc. 4:2 differential clock/data multiplexer ICS831742I general description the ICS831742I is a high-performance, differential hcsl clock/data multiplexer and fanout buffer. the device is designed for the multiplexing and fanout of high-frequency clock and data signals. the device has four differential, selectable clock/data inputs. the selected input signal is distributed to two low-skew differential hcsl outputs. each input pair accepts hcsl, lvds and lvpecl levels. the ICS831742I is characterized to operate from a 3.3v power supply. guaranteed input, output-to-ou tput and part-to-part skew characteristics make the ICS831742I ideal for those clock and data distribution applications demandin g well-defined performance and repeatability. the ICS831742I supports the clock multiplexing and distribution of pci express (2.5 gb/s), gen 2 (5 gb/s) and gen 3 (8 gb/s) clock signals. features ? 4:2 differential clock/data multiplexer with fanout ? four selectable, differential input pairs ? each differential input pair can accept the following levels: hcsl, lvds and lvpecl ? two differential hcsl output pairs ? maximum input/output clock frequency: 700mhz ? maximum input/output data rate: 1400mb/s (nrz) ? lvcmos interface levels for all control inputs ? pci express (2.5gb/s), gen 2 (5 gb/s) and gen 3 (8 gb/s) clock jitter compliant ? input skew: 110ps max ? part-to-part skew: 225ps max ? full 3.3v supply voltage ? available in lead-free (rohs 6) ? -40c to 85c ambient operating temperature 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd clk0 nclk0 v dd clk1 nclk1 clk2 nclk2 gnd clk3 nclk3 v dd sel1 iref v dd sel0 qb nqb nqa qa v dd gnd noeb noea block diagram qa nqa qb nqb iref clk0 nclk0 clk1 nclk1 clk2 nclk2 clk3 nclk3 sel1 sel0 noea noeb pullup/down pulldown pulldown pulldown pullup pullup pullup/down pulldown pullup/down pulldown pullup/down pulldown 0 0 0 1 1 0 1 1 pin assignment ics831742agi 24-lead tssop 4.4mm x 7.8mm x 0.925mm package body g package top view
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 2 ?2012 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 9, 15 gnd power power supply ground. 2 clk0 input pulldown non-inverting clock/data input. 3 nclk0 input pulldown/pullup inverting differential clock/data input. v dd /2 default when left floating. 4, 12, 16, 21 v dd power positive power supply. 5 clk1 input pulldown non-inverting clock/data input. 6 nclk1 input pulldown/pullup inverting differential clock/data input. v dd /2 default when left floating. 7 clk2 input pulldown non-inverting clock/data input. 8 nclk2 input pulldown/pullup inverting differential clock/data input. v dd /2 default when left floating. 10 clk3 input pulldown non-inverting clock/data input. 11 nclk3 input pulldown/pullup inverting differential clock/data input. v dd /2 default when left floating. 13 noea input pullup output enable for the qa output. see table 3a for function. lvcmos/lvttl interface levels. 14 noeb input pullup output enable for the qb output. see table 3b for function. lvcmos/lvttl interface levels. 17, 18 qa, nqa output differential output pair. hcsl interface levels. 19, 20 qb, nqb output differential output pair. hcsl interface levels. 22, 24 sel0, sel1 input pulldown differential clock/data input select. see table 3c for function. lvcmos/lvttl interface levels. 23 iref input an external fixed precision resistor (475 ? ) from this pin to ground provides a reference current used for the differential current-mode qx, nqx outputs. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 3 ?2012 integrated device technology, inc. function tables table 3a. noea configuration table note: noea is an asynchronous control. table 3b. noeb configuration table note: noeb is an asynchronous control. table 3c. selx configuration table note: sel1 and sel0 are asynchronous controls input operation noea 0 output qa, nqa is enabled. 1 (default) output qa, nqa is in a high-impedance state. input operation noeb 0 output qb, nqb is enabled. 1 (default) output qb, nqb is in a high-impedance state. input selected sel1 sel0 0 (default) 0 (default) clk0, nclk0 01clk1, nclk1 10clk2, nclk2 11clk3, nclk3
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 4 ?2012 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating co nditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c table 4b. lvcmos/lvttl input dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 87.8c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.0 3.3 3.6 v i dd power supply current outputs unloaded 26 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current noea, noeb v dd = v in = 3.6v 5 a sel0, sel1 v dd = v in = 3.6v 150 a i il input low current noea, noeb v dd = 3.6v, v in = 0v -150 a sel0, sel1 v dd = 3.6v, v in = 0v -5 a symbol parameter test conditio ns minimum typical maximum units i ih input high current clk0, nclk0; clk1, nclk1; clk2, nclk2; clk3, nclk3 v dd = v in = 3.6v 150 a i il input low current clk[0:3] v dd = 3.6v, v in = 0v -5 a nclk[0:3] v dd = 3.6v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 0.5 v dd ? 0.85 v
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 5 ?2012 integrated device technology, inc. ac electrical characteristics table 5a. pci express jitter specifications, v dd = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. measurements performed wit h a pci express compliant input source. for additional infor mation, refer to the pci express application note section in the datasheet. note 1: peak-to-peak jitter after applying system transfer func tion for the common clock architecture. maximum limit for pci ex press gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. note 2: rms jitter after applying the tw o evaluation bands to the two transfer func tions defined in the common clock architectu re and reporting the worst case results for each evaluation band. ma ximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). note 3: rms jitter after applying system tr ansfer function for the common clock archit ecture. this specification is based on th e pci express base specification revision 0.7, october 2009 and is subject to change pending the fi nal release version of the specification. note 4: this parameter is guaranteed by characterization. not tested in production. symbol parameter test condit ions minimum typical maximum pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak; note 1, 4 ? = 100mhz, 100mhz input evaluation band: 0hz - nyquist (clock frequency/2) 10 21 86 ps t refclk_hf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, 100mhz input high band: 1.5mhz - nyquist (clock frequency/2) 12.5 3.1ps t refclk_lf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, 100mhz input low band: 10khz - 1.5mhz 0.05 0.2 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms; note 3, 4 ? = 100mhz, 100mhz input evaluation band: 0hz - nyquist (clock frequency/2) 0.2 0.8 0.8 ps
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 6 ?2012 integrated device technology, inc. table 5b. hcsl ac characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input cro ss point to the differential output crossing point. note 2: measurement taken from differential waveform. note 3: measurement from -150mv to +150mv on the differential waveform (derived from qx minus nqx). the signal must be monotoni c through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossi ng. note 4: t stable is the time the differential clock must maintain a minimum 150mv differential vo ltage after rising/falling edges before it is allowed to drop back into the v rb = 100 differential range. see parameter measurement information section. note 5: measurement taken from single-ended waveform. note 6: defined as the maximum instantaneous voltage includ ing overshoot. see parameter measurement information section. note 7: defined as the minimum instantaneous voltage includi ng undershoot. see parameter measurement information section. note 8: measured at crossing point wher e the instantaneous voltage value of the risi ng edge of qx equals the falling edge of nq x. see parameter measurement information section note 9: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refe rs to all crossing points for this measurement. see parameter measurement information section. note 10: defined as the total variation of all crossing voltage of rising qx and falling nqx. this is the maximum allowed varia nce in the v cross for any particular system. see parameter measurement information section. note 11: input duty cycle must be 50%. note 12: matching applies to rising edge rate for qx and falling edge rate for nqx. it is measur ed using a 75mv window centere d on the median crosspoint where qx meets nqx falling. the median crosspoint is used to calculate the voltage thresholds the oscilloscop e is to use for the edge rate calculations. the rise edge rate of qx should be compared to the fall edge rate of nqx, the maximum allowed d ifference should not exceed 20% of the slowest edge rate. note 13: defined as skew between input paths on the same device , using the same input signal leve ls, measured at one specific o utput at the differential cross points. note 14: this parameter is defined in accordance with jedec standard 65. note 15: defined as skew between outputs on different devices ope rating at the same supply voltage and with equal load conditio ns. using the same type of inputs on each device, the outputs ar e measured at the differential cross points. note 16: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differentia l cross points. symbol parameter test conditio ns minimum typical maximum units f out output frequency 700 mhz t pd propagation delay; note 1 1.5 2 2.5 ns t sk(o) output skew; note 16 across all outputs 3 15 ps tsk(i) input skew; note 13 any input to q/nq 30 110 ps tsk(pp) part-to-part skew; note 14, 15 225 ps mux isol mux isolation f = 100mhz 40 db rising edge rate rising edge rate; note 2, 3 f = 100mhz 0.6 4 v/ns falling edge rate falling edge rate; note 2, 3 f = 100mhz 0.6 4 v/ns v rb ringback voltage; note 2, 4 f = 100mhz -100 100 mv v max absolute max output voltage; note 5, 6 f = 100mhz 1150 mv v min absolute min output voltage; note 5, 7 f = 100mhz -300 mv v cross absolute crossing voltage; note 5, 8, 9 f = 100mhz 250 550 mv ? v cross total variation of v cross over all edges; note 5, 8, 10 f = 100mhz 140 mv odc output duty cycle; note 11 f ? 200mhz 48 50 52 %
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 7 ?2012 integrated device technology, inc. parameter measurement information 3.3v hcsl output load ac test circuit differential input level output skew 3.3v hcsl output load ac test circuit part-to-part skew propagation delay 475 33 50 50 33 49.9 49.9 hcsl gnd 2pf 2pf qx nqx 0v iref v dd 3.3v0.3v this load condition is used for v rb , v max , v min , v cross , and ? v cross measurements. v cmr cross points v pp v dd gnd nclk[0:3] clk[0:3] t sk(o) qx nqx qy nqy 475 50 50 hcsl gnd 0v scope iref v dd this load condition is used for t sk(o), t sk(pp), t sk(i), t pd and tjit measurements. 3.3v0.3v qx nqx t sk(pp) part 1 part 2 qy nqy t pd nclk[0:3] clk[0:3] nqa, nqb qa, qb
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 8 ?2012 integrated device technology, inc. parameter measurement in formation, continued input skew differential measurement points for duty cycle/period single-ended measurement points for delta cross point differential measurement points for rise/fall edge rate differential measurement points for ringback single-ended measurement points for absolute cross point/swing t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) nclky clky nq[a, b] q[a, b] nclkx clkx q - nq 0.0v clock period (differential) positive duty cycle (differential) negative duty cycle (differential) ? v cross nq q q - nq -150mv +150mv 0.0v fall edge rate rise edge rate t stable v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v v rb t stable v cross_max v cross_min v max v min nq q
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 9 ?2012 integrated device technology, inc. parameter measurement in formation, continued mux isolation amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1 l or h sel q
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 10 ?2012 integrated device technology, inc. applications information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullup or pulldown; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk/nclk inputs for applications not requiring the use of the all differential inputs, any clk/nclk input can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: differential output s the unused differential output can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. wiring the differential input to accept singl e-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is reco mmended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specific ations are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 11 ?2012 integrated device technology, inc. differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input hc s l *r 333 *r4 33 clk nclk 2.5v 3 . 3 v zo = 50 zo = 50 differenti a l inp u t r1 50 r2 50 *option a l ? r 3 a nd r4 c a n b e 0 zo = 50 3.3v r1 50 r2 50 r2 50 lvds clk nclk 3.3v receiver zo = 50 zo = 50
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 12 ?2012 integrated device technology, inc. recommended termination figure 3a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3a. recommended source termination (where the driver and receiver will be on separate pcbs) figure 3b is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 13 ?2012 integrated device technology, inc. pci express a pplication note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase interpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s) * h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist ( high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 14 ?2012 integrated device technology, inc. power considerations this section provides information on power dissi pation and junction temperature for the ICS831742I. equations and example calculations are also provided. 1.power dissipation. the total power dissipation for the ICS831742I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 0.3v = 3.6v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.6v * 26ma = 93.6mw ? power (outputs) max = 46.8mw/loaded output pair if all outputs are loaded, the total power is 2 * 46.8mw = 93.6mw total power_ max = 93.6mw + 93.6mw = 187.2mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bon d pad and directly affects the reliability of the device. the maximum recommended junction temperature for devices is 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 87.8c/w per table 6 below. therefore, tj for an ambient temperatur e of 85c with all outputs switching is: 85c + 0.187w * 87.8c/w = 101.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depend ing on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ? ja for 24 lead tssop, forced convection ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 87.8c/w 83.5c/w 81.3c/w
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 15 ?2012 integrated device technology, inc. 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 4. figure 4. hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17m a of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out , since v out = i out * r l = (v dd_max ? i out * r l ) * i out = (3.6v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 46.8mw v dd v out r l 50 ic ? i out = 17ma r ref = 475 1%
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 16 ?2012 integrated device technology, inc. reliability information table 7. ? ja vs. air flow table for a 24 lead tssop transistor count the transistor count for the ICS831742I is: 765 package outline and package dimensions package outline - g suffix for 24 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 87.8c/w 83.5c/w 81.3c/w all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ICS831742I data sheet 4:2 differential clock/data multiplexer ics831742agi july 10, 2012 17 ?2012 integrated device technology, inc. table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-f ree configuration and are rohs compliant. part/order number marking package shipping packaging temperature 831742agilf ics831742agil ?lead-free? 24 lead tssop tube -40 ? c to 85 ? c 831742agilft ics831742agil ?lead-free? 24 lead tssop tape & reel -40 ? c to 85 ? c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applicat ions, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ICS831742I data sheet 4:2 differential clock/data multiplexer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of any kind, whether e xpress or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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