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(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 1 /24 product specifications 17.0? sxga color tft - lcd module model name: l170e3/m170en04 ec: 7 / v.7 ( ) preliminary specifications ( u ) final specifications note: this specification is subj ect to change without notice.
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 2 /24 i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 display characteristics 2.2 functional block diagram 2.3 optical characteristics 2.4 pixel format image 3.0 electrical characteristics 3.1 absolute maximum ratings 3.2 connectors 3.3 signal pin 3.4 signal description 3.5 signal electrical characteristics 3.6 interface timing 3.6.1 timing characteristics 3.6.2 timing definition 3.7 power consumption 3.8 powe r on/off sequence 4.0 backlight characteristics 4.1 signal for lamp connector 4.2 parameter guide line for ccfl inverter 5.0 vibration, shock and drop 5.1 vibration and shock 5.2 drop test 6.0 environment 6.1 temperature and humidity 6.1.1 op erating conditions 6.1.2 shipping conditions 6.2 atmospheric pressure 6.3 thermal shock 7.0 reliability 7.1 failure criteria 7.2 failure rate 7.2.1 usage 7.2.2 components de - rating 7.3 ccfl life 7.4 on/off cycle 8.0 safety 8.1 sharp edge requi rement 8.2 material 8.2.1 toxicity 8.2.2 flammability 8.3 capacitors 8.4 hazardous voltage 9.0 other requirements 9.1 smoke free design 9.2 national test lab requirement 10.0 mechanical characteristics
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 3 /24 ii record of revision version and date pa ge old description new description remark 0.1. 200 2 /0 2 / 19 all first edition for customer all 1.0 handling precautions 1) since front polarizer is easily damaged, pay attention not to scratch it. 2) be sure to turn off power supply when inserting or disconnectin g from input connector. 3) wipe off water drop immediately. long contact with water may cause discoloration or spots. 4) when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. 5) since the panel is made of glass, it may break or cra ck if dropped or bumped on hard surface. 6) since cmos lsi is used in this module, take care of static electricity and insure human earth when handling. 7) do not open nor modify the module assembly. 8) do not press the reflector sheet at the back of the module to any directions. 9) at the insertion or removal of the signal interface connector, be sure not to rotate nor tilt the interface connector of the tft - lcd module. 10) after installation of the tft - lcd module into an enclosure (lcd monitor housing, for examp le), do not twist nor bend the tft - lcd module even momentary. at designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the tft - lcd module from outside. otherwise the tft - lcd module may be damaged.
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 4 /24 2.0 general description this specification applies to the 17.0 inc h color tft - lcd module l170e3 the display supports the sxga (1280(h) x 1024(v)) screen format and 16.7m colors (rgb 8 - bits data). all input signals are 2 channel lvds interface compatible. this module does not contain an inverter card for backlight. 2.1 display characteristics the following items are characteristics summary on the table under 25 j condition: items unit specifications screen diagonal [mm] 432(17.0") active area [mm] 337. 920 (h) x 270.336(v) pixels h x v 1280(x3) x 1024 pixel pitch [mm] 0.264 (per one triad) x 0.264 pixel arrangement r.g.b. vertical stripe display mode normally white white luminance [cd/m 2 ] 250 (typ) contrast ratio 400 : 1 (typ) optical response time [msec] 40 (typ) nominal input voltage vdd [volt] +5.0 v power consumption (vdd line + ccfl line) [watt] 25w(max) (w/o inverter, all black pattern) weight [grams] 2000 (typ) physical size [mm] 383.5(w) x 306(h) x 20.0(d) (typ) electrical interf ace even/odd r/g/b data(8bits),3 sync signal, clock support color 16.7m colors ( rgb 8 - bit data ) temperature range operating storage (shipping) [ o c] [ o c] 0 to +50 - 20 to +60
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 5 /24 2.2 functional block diagram the following diagram shows the function al block of the 17.0 inches color tft - lcd module: lvds + 5v jae fi - x30s - hf jst bhr - 04vs - 1 mating type jae fi - x30s - h mating type sm04(4.0)b - bhs - 1 - tb connector dc/dc converter lvds receiver timing controller gamma correction tft - lcd 1280*(3)*1024 pixels x - driver ic y - driver ic g1 g1024 d1 d3840 inverter dc power 4 ccfl i/f + x pcb y pcb asic(leo 3)
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 6 /24 2.3 optical characteristics the optical characteristics are me asured under stable conditions at 25 j (room temperature) : item unit conditions min. typ. max. viewing angle [degree] [degre e] horizontal (right) cr = 10 (left) 60/60 - 70/70 - - [degree] [degree] vertical (up) cr = 10 (down) 50 55 60 65 - - contrast ratio normal direction 250 400 - response time(note 1) [msec] raising time - 25 35 - [msec] falling time - 15 25 - [msec] raising + falling - 40 - color / chromaticity red x 0.59 0.62 0.65 coordinates (cie) red y 0.3 0.33 0.36 green x 0.27 0.3 0 0.33 green y 0.57 0. 60 0.63 blue x 0.12 0.15 0.18 blue y 0.07 0.10 0.13 color coordinates (cie) white wh ite x 0.28 0.31 0.34 white y 0.3 0.3 3 0.36 luminance uniformity (note 2) [%] 80 85 - white luminance at ccfl 6.0ma(center point) [cd/m 2 ] 200 250 - crosstalk ( in 75hz) [%] 1.5 note 1: definition of response time: the output signals of photod etector are measured when the input signals are changed from ? black? to ? white? (falling time), and from ?white? to ? black? (rising time), respectively. the response time interval between the 10% and 90% of amplitudes. refer to figure as below. tr r tr d 100 90 10 0 % optical response white black white
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 7 /24 note 2 measure points & diagram display length distance x = ?????????????? ???????????? 10 display width distance y = ?????????? ???? ???????????? 10 minimum luminance in 5 points ( 1 - 5) uniformity = ??????????????????? ???????????? ???????????? maximum luminance in 5 points ( 1 - 5) this panel is compatible with tco99 approbation in luminance uniformity <1.7, luminance contrast >0.5 lcd display area = 337.9 x 270.4 mm w/10 1 2 5 3 l/10 l /10 w/10 w/10 w/10 4
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 8 /24 2.4 pixel format image following figure shows th e relationship of the input signals and lcd pixel format. r g b r g b r g b r g b r g b r g b r g b r g b 1 2 1279 1280 1st line 1024th
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 9 /24 3.0 electrical characteristics 3.1 absolute maximum ratings absolute maximum ratings of the module is as following: item symbol min max unit conditions logic/lcd driv e voltage vin - 0.3 +5.5 [volt] select lvds data order sellvds nc nc [volt] ccfl inrush current icfll - 38 [ma] note 1 ccfl current icfl - 7.6 [ma] rms operating temperature top 0 +50 [ o c] note 2 operating humidity hop 8 95 [%rh] note 2 storage tem perature tst - 20 +60 [ o c] note 2 storage humidity hst 8 95 [%rh] note 2 note 1 : duration=50 msec. note 2 : maximum wet - bulb should be 39 j and no condensation. 3.2 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. connector name / designation interface connector / interface card manufacturer jae or compatible type part number fi - x30s - hf mating housing part number fi - x30s - h connector name / designation lamp connector / backlight lamp manufacturer jst type part number bhr - 04vs - 1 mating type part number s m04(4.0)b - bhs - 1 - tb
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 10 /24 3.3 signal pin pin# signal name pin# signal name 1 rxo0 - 2 rxo0+ 3 rxo1 - 4 rxo1+ 5 rxo2 - 6 rxo2+ 7 gnd 8 rxoc - 9 rxoc+ 10 rxo3 - 11 rxo3+ 12 rxe0 - 13 rxe0+ 14 gnd 15 rxe1 - 16 rxe1+ 17 gnd 18 rxe2 - 19 rxe2+ 20 rxec - 21 r xec+ 22 rxe3 - 23 rxe3+ 24 gnd 25 nc 26 nc 27 nc 28 power 29 power 30 power
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 11 /24 3.4 signal description the module using a pair of lvds receiver sn75lvds82(texas instruments) or compatible. lvds is a differential signal technology for lcd interface and high speed data transfer device. transmitter shall be sn75lvds83(negative edge sampling) or compatible . the first lvds port(rxoxxx) transmits odd pixels while the second lvds port(rxexxx) transmits even pixels. pin # signal name description 1 rxo0 - nega tive lvds differential data input (odd data) 2 rxo0+ positive lvds differential data input (odd data) 3 rxo1 - negative lvds differential data input (odd data) 4 rxo1+ positive lvds differential data input (odd data) 5 rxo2 - negative lvds differential d ata input (odd data, h - sync,v - sync,dsptmg) 6 rxo2+ positive lvds differential data input (odd data, h - sync,v - sync,dsptmg) 7 gnd power ground 8 rxoc - negative lvds differential clock input (odd clock) 9 rxoc+ positive lvds differential clock input (odd clock) 10 rxo3 - negative lvds differential data input (odd data) 11 rxo3+ positive lvds differential data input (odd data) 12 rxe0 - negative lvds differential data input (even clock) 13 rxe0+ positive lvds differential data input (even data) 14 gnd po wer ground 15 rxe1 - positive lvds differential data input (even data) 16 rxe1+ negative lvds differential data input (even data) 17 gnd power ground 18 rxe2 - negative lvds differential data input (even data) 19 rxe2+ positive lvds differential data in put (even data) 20 rxec - negative lvds differential clock input (even clock) 21 rxec+ positive lvds differential clock input (even clock) 22 rxe3 - negative lvds differential data input (even data) 23 rxe3+ positive lvds differential data input (even da ta) 24 gnd power ground 25 nc - 26 nc - 27 nc - 28 power power 29 power power 30 power power note: input signals of odd and even clock shall be the same timing.
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 12 /24 lvds data name description dsp display timing :when the signal is high, the pixel data shall be valid to be displayed v - s vertical sync :both positive and negative polarity are acceptable h - s horizontal sync :both positive and negative polarity are acceptable ti lvds x?mitter sn75lvds83 module lvds signal (interface con nector pin7) signal name low(open) d0 red0 d1 red1 d2 red2 d3 red3 d4 red4 d5 red7 d6 red5 d7 green0 d8 green1 d9 green2 d10 green6 d11 green7 d12 green3 d13 green4 d14 green5 d15 blue0 d16 blue6 d17 blue7 d18 blue1 d19 blue2 d20 blue 3 d21 blue4 d22 blue5 d23 na d24 h sync d25 v sync d26 display timing d27 red6
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 13 /24 note: r/g/b data 7:msb, r/g/b data 0:lsb o = ?first pixel data? e = ?second pixel data? rxeclkin+ rxeclkin- rxeclkin+ rxeclkin- rxein0+ rxein0- rxein1+ rxein1- rxein2+ rxein2- rxein3+ rxein3- rxoin0+ rxoin0- rxoin1+ rxoin1- rxoin2+ rxoin2- rxoin3+ rxoin3- er1 er0 er5 eg0 er4 er3 er2 er1 er0 eg0 eg2 eg2 eb1 eb0 eg5 eg4 eg3 eg2 eg1 eb1 eb3 eb2 na na na eb5 eb4 eb3 eb2 dsp er7 er6 na eb7 eb6 eg7 eg6 er7 er6 na or1 or0 og0 or5 or4 or3 or2 or1 or0 og0 og2 og1 ob1 ob0 og5 og4 og3 og2 og1 ob1 ob3 ob2 dsp v-s h-s ob5 ob4 ob3 ob2 na or7 or6 na ob7 ob6 og7 og6 or7 or6 na 1 cycle 1 cycle
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 14 /24 3.5 signal electrical characteristics input signals shall be low or hi - z state when vin is off it is recommended to refer the specifications of sn75lvds82dgg(texas instruments) in detail. each signal characteristics are as follows; parameter condition min max unit vth differential input high voltage(v cm=+1.2v) 100 [mv] vtl differential input low voltage(vcm=+1.2v) - 100 [mv] thd tsu input clock input data t
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 15 /24 3.6 interface timings basically, interface timings described here is not actual input timing of lcd module but output timing of sn75lvds82dgg (texas instruments) or equivalent. 3.6.1 timing characteristics signal item symbol min typ max unit dtclk freq. fdck 50 67.5 70 mhz dtclk cycle tck 14.2 14.8 20 ns +v - sync frame rate 1/tv 56.25 75 77 hz +v - sync cycle tv 13 13.33 17.78 ms + v - sync cycle tv 1035 1066 2047 lines +v - sync active level tva 3 3 lines +v - sync v - back porch tvb 7 38 63 lines +v - sync v - front porch tvf 1 1 lines +dsptmg v - line m - 1024 - lines +h - sync scan rate 1/th - 80.06 - khz +h - sync cycle th 800 844 1023 tck +h - sync active level tha(*1) 4 56 tck +h - sync back porch thb(*1) 4 124 tck +h - sync front porch thf 4 24 tck +dsptmg display pixels n - 640 - tck note: typical value is refer to vesa standard , (*1) tha+thb should be less than 1024 tck. 3.6.2 timing definition 1688dot 112dot 248dot 48dot 1280dot h-sync dsptmg 42h 1h 38h 3h 1024h v-sync dsptmg note :1280x1024 at 75 hz (vesa standard), horizontal line rate : 13.02us, dot clock :135mhz.
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 16 /24 3.7 power consumption input power specifications are as fo llows; symbol parameter min typ max units condition vdd logic/lcd drive voltage 4.5 5 5.5 [volt] idd vdd current 850 1100 [ma] iidd inrush vdd current 6.5 [a] t < 80us pdd vdd power 4.25 5.5 [watt] vin=5v ,all black pattern vddrp allowab le logic/lcd drive ripple voltage 100 [mv] p - p vddns allowable logic/lcd drive ripple noise 100 [mv] p - p 3.8 power on/off sequence vin power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi - z state or low level when vin is off. 10% 10% 10% 10% 10% 10% 10% 90% 90% 0 min. 0 min. 0 min. 170ms min. 10ms min. 30 max, 1ms min. vin lamp on signal
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 17 /24 4.0 backlight characteristics 4.1 signal for lamp connector pin # signal name 1 lamp high voltage 2 lamp high voltage 3 no connection 4 ground 4.2 parameter guide line f or cfl inverter symbol parameter min typ max units condition (l255) white luminance 200 250 - [cd/m 2 ] (ta=25 o c) iscfl ccfl standard current 5.5 6.0 6.5 [ma] rms (ta=25 o c) ircfl ccfl operation range 3.0 6.0 7.0 [ma] rms (ta=25 o c) icfl ccfl inrush current - 26 34 [ma] note 1 fcfl ccfl frequency 40 50 80 [khz] (ta=25 o c) note 2 vicfl (0 o c) ccfl ignition voltage 1700 [volt] rms (ta=0 o c) note 4 vicfl (25 o c) ccfl ignition voltage 1200 [volt] rms (ta=25 o c) note 4 vcfl ccfl discharge voltage (ref erence) 720 863 [volt] rms (ta=25 o c) note 3 pcfl ccfl power consumption 17.3 19.0 [watt] (ta=25 o c) note 3 note 1: duration=50 [msec] note 2: ccfl frequency should be carefully determined to avoid interference between inverter and tft lcd note 3: calc ulator value for reference (icflvcfl=pcfl) note 4: ccfl inverter should be able to give out a power that has a generating capacity of over 1700 voltage. lamp units need 1700 voltage minimum for ignition
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 18 /24 5.0 vibration, shock, and drop 5.1 vibration & sho ck frequency: 10 - 200hz sweep: 30 minutes each axis (x, y, z) acceleration: 1.5g(10~200hz p - p) test method: acceleration (g) 1.5 frequency (hz) 10~200~10 active time(min) 30 5.2 shock test spec: acceleration (g) ? a 50 active time - b 20 wave form half - sin times 1 direction: ? x , ? y, ? z 5.3 drop test package test: the drop height is 60 cm.
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 19 /24 6.0 environment the display module will meet the provision of this specification during operating condition or after storage or shipm ent condition specified below. operation at 10% beyond the specified range will not cause physical damage to the unit. 6.1 temperature and humidity 6.1.1 operating conditions the display module operates error free, when operated under the following condit ions; temperature 0 0 c to 50 0 c relative humidity 8% to 95% wet bulb temperature 39.0 0 c 6.1.2 shipping conditions the display module operates error free, after the following conditions; temperature - 20 0 c to 60 0 c relative humidity 8% to 95 % wet bulb temperature 39.0 0 c 6.2 atmospheric pressure the display assembly is capable of being operated without affecting its operations over the pressure range as following specified; pressure note maximum pressure 1040hpa 0m = sea level minimum pressure 674hpa 3048m = 10.000 feet note : non - operation attitude limit of this display module = 30,000 feet. = 9145 m. 6.3 thermal shock the display module will not sustain damage after being subjected to 100 cycles of rapid temperature change . a cycle of rapid temperature change consists of varying the temperature from - 20 0 c to 60 0 c, and back again. thermal shock cycle - 20 0 c for 30min 60 0 c for 30min power is not applied during the test. after temperature cycling, the unit is placed in normal room ambient for at least 4 hours before powering on.
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 20 /24 7.0 reliability this display module and the packaging of that will comply following standards. 7.1 failure criteria the display assembly will be considered as failing unit when it no long er meets any of the requirements stated in this specification. only as for maximum white luminance, following criteria is applicable. note : maximum white luminance shall be 125 cd/m 2 or more. 7.2 failure rate the average failure rate of the display modul e (from first power - on cycle till 1,000 hours later) will not exceed 1.0%. the average failure rate of the display module from 1,000 hours until 16,000 hours will not exceed 0.7% per 1000 hours. 7.2.1 usage the assumed usage for the above criteria is: 220 po wer - on hours per month 500 power on/off cycles per month maximum brightness setting operation to be within office environment (25 0 c typical) 7.2.2 component de - rating all the components used in this device will be checked the load condition to meet the fa ilure rate criteria. 7.3 ccfl life the assumed ccfl life will be longer than 30,000 hours, typical value is 50,000 hours under stable condition at 25 5 o c; standard current at 6.0 0.5ma. definition of life: brightness becomes 50% or less than the min imum luminance value of ccfl. 7.4 on/off cycle the display module will be capable of being operated over the following on/off cycles. on/off value cycles +vin and ccfl power 30,000 10 seconds on / 10 seconds off
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 21 /24 8.0 safety 8.1 sharp edge requirem ents there will be no sharp edges or comers on the display assembly that could cause injury. 8.2 materials 8.2.1 toxicity there will be no carcinogenic materials used anywhere in the display module. if toxic materials are used, they will be reviewed and a pproved by the responsible adt toxicologist. 8.2.2 flammability all components including electrical components that do not meet the flammability grade ul94 - v1 in the module will complete the flammability rating exception approval process. the printed circ uit board will be made from material rated 94 - v1 or better. the actual ul flammability rating will be printed on the printed circuit board. 8.3 capacitors if any polarized capacitors are used in the display assembly, provisions will be made to keep the m from being inserted backwards. 8.4 hazardous voltages any point exceeding 42.4 volts meets the requirement of the limited current circuit. the current through a 2k [ resistance is less than 0.7 x f (khz) ma.
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 22 /24 9.0 other requirements 9 .1 national test lab requirement the display module will satisfy all requirements for compliance to ul 1950, first edition u.s.a. information technology equipment csa c22.2 no.950 - m89 canada, information technology equipment eec 950 international, information technology equipment en 60 950 international, information processing equipment (european norm for iec950) 9.2 label 9.2.1 product label
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 23 /24 10.0 mechanical characteristics
(c) copyright au optronics, inc. january, 2001 all rights reserved. l170e3 - 7 ver0. 1 no reproduction and redistribution allowed. 24 /24

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