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data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 2gb ddr2 C sdram registered dimm 240 pin rdimm sep02g72e2bf2sa - 3 0 r 2gb pc2 - 53 00 in fbga techn ology rohs compliant options: ? data rate / latency marking ddr2 533 mts / cl4 - 37 ddr2 667 mt/s / cl5 - 30 ? module density 2048mb with 18 dies and 2 ranks ? standard grade (t a ) 0c to 70c (t c ) 0c to 85c environmental requirements: ? operating temperature (t ambient ) standard grade 0c to 70c ? operating humidity 10% to 90% relative humidity, noncondensing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, noncondensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c figure: mechanical dimensions 1 1 if no tolerances specified 0.15mm features: ? 240 - pin 72 - bit ddr2 registered dual - in - line double data rate s ynchronous dram module for server applications ? module organization: dual rank 256 m x 72 ? v dd = 1.8v 0.1 v, v ddq 1.8v 0.1 v ? 1.8v i/o ( sstl_18 compati ble) ? serial presence detect with eeprom ? supports ecc error detection and correction ? jedec compatible ddr2 pll/register component with parity bit support for address and control bus ? gold - contact pad ? this module family is fully pin and functional compatible to jedec. (see www.jedec.org ) ? the pcb and all components are manufactured according to the rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ? ddr2 sdram component samsun g k4t1g084qf ? 128mx8 ddr 2 sdram in fbga - 60 package ? four bit prefetch architecture ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency C 1 t ck ? programmable burst length: 4 or 8 ? adjustable data - output drive strength ? on - die termination (odt) ? dll to align dq and dqs transitions with ck
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 this swissbit module is an industry standard 240 - pin 8 - byte ddr2 registered sdram dual - in - line me mory module ( r dimm) which is organized as x72 high speed cmos memory arrays. all control and address signals are re - driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. de - coupling capacitors, stub resistors, calibration resistors and termination resistors are mounted on the pcb board. the module uses double data rate architecture to achieve high - speed operation. ddr2 sdram modules operate f rom a differential clock (ck and ck#). read and write accesses to a ddr2 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst length is either four or ei ght locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr2 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_18 compatible. the ddr2 sdram module uses the serial presence detect (spd) function implemented via serial e eprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr2 sdrams used row addr. device bank select column addr. refresh module bank select 256m x 72bit 18 x 128m x 8bit (1 024m bit) 14 ba0, ba1, ba2 10 8k s0#, s1# module dimension s in mm 133.33 (long) x 30(high) x 4 [max] (thickness) timing parameters part number module density transfer rate clock cycle/ data bit rate latency sep02g72e2bf2sa - 37 r 2048 mb 4.2 gb/s 3.7ns/533mt/s 4 - 4 - 4 sep02g72e2bf2sa - 30r 2048 mb 5.3 gb/s 3.0ns/667 mt/s 5 - 5 - 5 pin name a0 C a13 address inputs ba0 C ba2 bank address inputs dq0 C dq63 data input / output cb0 C cb7 data check bits input / output dm0 C dm8 input data mask dqs0 C dqs8 data strobe, positive line dqs0# - dqs8# data strobe, negative l ine (only used when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 clock enable ck0 C ck1 clock input, positive line ck0# - ck1# clock input, negative line s0#, s1# chip sele ct reset# asynchronously forces all registered outputs low when reset# is low. this signal can be used during power - up to ensure that cke is low and dqs are high - z. figure 1: mechanical dimensions
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 p ar _in parity bit for the address and control bus. e rr _out parity error found on the add ress and control bus. v dd / v ddq supply voltage (1.8v 0.1v) v ref input / output reference v ss ground v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa 2 presence detect a ddress inputs odt0, odt1 on - die termination nc no connection pin configuration pin # front side pin # back side pin # front side pin # back side 1 v ref 121 v ss 61 a4 181 v dd q 2 v ss 122 dq4 62 v dd q 182 a3 3 dq0 123 dq5 63 a2 183 a1 4 dq1 124 v ss 64 v dd 184 v dd 5 v ss 125 dm0 (dqs9) 65 v ss 185 ck0 6 dqs0# 126 nc (dqs9#) 66 v ss 186 ck0# 7 dqs0 127 v ss 67 v dd 187 v dd 8 v ss 128 dq6 68 par_in 188 a0 9 dq2 129 dq7 69 v dd 189 v dd 10 dq3 130 v ss 70 a10/ap 190 ba1 11 v ss 131 dq12 71 ba0 191 v dd q 12 dq8 132 dq13 72 v dd q 192 ras# 13 dq9 133 v ss 73 we# 193 s0# 14 v ss 134 dm1 (dqs10) 74 cas# 194 v dd q 15 dqs1# 135 nc (dqs10#) 75 v dd q 195 odt0 16 dqs1 136 v ss 76 nc (s1#) 196 a13 17 v ss 137 nc (ck1) 77 nc (odt1) 197 v dd 18 reset 138 nc (ck1#) 78 v dd q 198 v ss 19 nc 139 v ss 79 v ss 199 dq36 20 v ss 140 dq14 80 dq32 200 dq37 21 dq10 141 dq15 81 dq33 201 v ss 22 dq11 142 v ss 82 v ss 202 dm4 (dqs13) 23 v ss 143 dq20 83 dqs4# 203 nc (dqs13#) 24 dq16 144 dq21 84 dqs4 204 v ss 25 dq17 145 v ss 85 v ss 205 dq38 26 v ss 146 dm2 (dqs11) 86 dq34 206 dq39 27 dqs2# 147 nc (dqs11#) 87 dq35 207 v ss 28 dqs2 148 v ss 88 v ss 208 dq44 29 v ss 149 dq22 89 dq40 209 dq45 30 dq18 150 dq23 90 dq41 210 v ss 31 dq19 151 v ss 91 v ss 211 dm5 (dqs14)
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 pin # front side pin # back sid e pin # front side pin # back side 32 v ss 152 dq28 92 dqs5# 212 nc (dqs14#) 33 dq24 153 dq29 93 dqs5 213 v ss 34 dq25 154 v ss 94 v ss 214 dq46 35 v ss 155 dm3 (dqs12) 95 dq42 215 dq47 36 dqs3# 156 nc (dqs12#) 96 dq43 216 v ss 37 dqs3 157 v ss 97 v ss 217 d q52 38 v ss 158 dq30 98 dq48 218 dq53 39 dq26 159 dq31 99 dq49 219 v ss 40 dq27 160 v ss 100 v ss 220 nc (ck2) 41 v ss 161 cb4 101 sa2 221 nc (ck2#/) 42 cb0 162 cb5 102 nc (test) 222 v ss 43 cb1 163 v ss 103 v ss 223 dm6 (dqs15) 44 v ss 164 dm8 (dqs17) 104 d qs6# 224 nc (dqs15#) 45 dqs8# 165 nc (dqs17#) 105 dqs6 225 v ss 46 dqs8 166 v ss 106 v ss 226 dq54 47 v ss 167 cb6 107 dq50 227 dq55 48 cb2 168 cb7 108 dq51 228 v ss 49 cb3 169 v ss 109 v ss 229 dq60 50 v ss 170 v dd q 110 dq56 230 dq61 51 v dd 171 nc (cke1) 1 11 dq57 231 v ss 52 cke0 172 v dd 112 v ss 232 dm7 (dqs16) 53 v dd 173 nc (a15) 113 dqs7# 233 nc (dqs16#) 54 ba2 174 nc (a14) 114 dqs7 234 v ss 55 par_out 175 v dd q 115 v ss 235 dq62 56 v dd q 176 a12 116 dq58 236 dq63 57 a11 177 a9 117 dq59 237 v ss 58 a7 17 8 v dd 118 v ss 238 v dd spd 59 v dd 179 a8 119 sda 239 sa0 60 a5 180 a6 120 scl 240 sa1 (sig): signal in brackets may be routed to the socket connector, but is not used on the module
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 functional block diagramm 2048mb ddr2 ecc registered dimm, 2 ranks and 18 components
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 1.0 2.3 v i/o supply voltage v dd q - 0.5 2.3 v v dd l supply voltage v dd l - 0.5 2.3 v voltage on any pin relative to v ss v in , v out - 0.5 2.3 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 40 40 ck, ck# - 20 20 dm - 5 5 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 16 16 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.7 1.8 1.9 v i/o supply voltag e v dd q 1.7 1.8 1.9 v v dd l supply voltage v dd l 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C ref v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.125 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.25 - v input low (logic 0) voltage v il (ac) - v ref - 0.25 v c apacitance at ddr2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and real istic than a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 i dd specifications and conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) parameter & test condition symbol max. unit 5300 - 555 4200 - 444 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between vali d commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 495 450 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 549 522 ma precharge power - down current: all device banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref i dd2p 180 180 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 360 360 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every tw o clock cycles; dq inputs changing once per clock cycle i dd2n 450 432 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast pdn exit mr[12] = 0 i dd3p 414 396 ma slow pdn exit mr[12] = 1 270 270 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs a re changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 576 540 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 810 720 ma
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 parameter & test condition symbol ma x. unit 5300 - 555 4200 - 444 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between vali d commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 693 630 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 1890 1800 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are float ing at v ref ; dqs are floating at v ref i dd6 180 180 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1530 1395 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 5300 - 555 4200 - 444 unit cl (i dd ) 5 4 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 60 ns t rrd (i dd ) 7.5 7.5 ns t ck (i dd ) 3.0 3.7 5 ns t ras min (i dd ) 45 45 ns t ras max (i dd ) 70000 70 000 ns t rp (i dd ) 15 15 ns t rfc (i dd ) 127.5 1 27 .5 ns
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 4200 - 444 unit parameter symbol min max min max clock cycle time cl = 6 t ck (6) - - - - n s cl = 5 t ck (5) 3.0 8.0 3.75 8.0 n s cl = 4 t ck (4) 3.75 8.0 3.75 8.0 n s cl = 3 t ck (3) 5.0 8.0 5.0 8.0 n s ck high - level width t ch 0.48 0.52 0.45 0.55 t ck ck low - level width t cl 0.48 0.52 0.45 0.55 t ck half clock period t hp min (t ch, t cl ) min (t ch, t cl ) ps access window (output) of dq s from ck/ck# t ac - 0 .45 +0.45 - 0.50 +0.50 ns data - out high - impedance window from ck/ck# t hz +0.45 (= t ac max) +0.50 (= t ac max) ns data - out low - impedance window from ck/ck# t lz - 0.45 (= t ac min) +0.45 (= t ac max) - 0.50 (= t ac min) +0.50 (= t ac max) ns dq and dm input set up time relative to dqs t ds 0.10 0.10 ns dq and dm input hold time relative to dqs t dh 0.175 0.35 ns dq and dm input pulse width ( for each input ) t dipw 0.35 0.35 t ck data hold skew factor t qhs 0.34 0.4 ns dq - dqs hold, dqs to first dq to go non - v alid, per access t qh t hp - t qhs t hp - t qhs ns data valid output window t dvw t qh - t dqsq t qh - t dqsq ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck dqs C t dqsq 0.24 0.30 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dq s write preamble t wpre 0.35 0.25 t ck dqs write preamble setup time t wpres 0 0 ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 +0.25 - 0.25 + 0.25 t ck write command to first dqs latchi ng transition wl - t dqss wl+ t dqss wl - t dqss wl+ t dqss t ck address and control input pulse width ( for each input ) t ipw 0.6 0.6 t ck address and control input setup time t isa 0.2 0.5 ns
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 ddr2 sdram component electrical characteristics and recommende d ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 4200 - 444 unit parameter symbol min max min max address and control input hold time t ih 0.275 0.5 ns cas# to cas# command delay t ccd 2 2 t ck active to act ive (same bank) command period t rc 60 55 ns active bank a to active bank b command t rrd 7.5 7.5 ns active to read or write delay t rcd 15 15 ns four bank activate period t faw 37.5 37.5 ns active to precharge command t ras 45 70000 t rtp 7.5 7.5 ns write recovery time t wr 15 15 ns auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns internal write to read command delay t wtr 7.5 7.5 ns precharge command perio d t rp 15 15 ns precharge all command period t rpa t rp + t ck t rp + t ck ns load mode command cycle time t mrd 2 2 t ck cke low to ck, ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t ck refresh to active or refresh to refresh command interval t rfc 127.5 127 .5 ns average periodic refresh interval (0c<= t case <= 85 c) t refi 7.8 7.8 s (85c<= t case <= 95 c) t refi 3.9 3.9 s exit self refresh to non - read command t xsnr t rfc (min) + 10 t rfc (min) + 10 ns exit self r efresh to read command t xsrd 200 200 t ck exit self refresh timing reference t isxr t is t is ps odt turn - on delay t aond 2 2 2 2 t ck odt turn - on t aon t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1,000 ps odt turn - off delay t aofd 2.5 2.5 t ck odt tur n - off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn - on (power - down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn - off (power - down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power - down entry latency t anpd 3 t ck
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8 v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 4200 - 444 unit parameter symbol min max min max odt power - down exit latency t axpd 8 8 t ck odt enable from mrs command t mod 0 12 0 12 ns exit active power - down to read command, mr [bit 12 = 0 ] t xard 2 2 t ck exit active power - down to read command, mr [bit 12 = 1] t xards 7 C C ck exit precharge power - down to any non - read command t xp 2 2 t ck cke minimum high/low time t cke 3 3 t ck register specifications parameter symbol pin s conditions min max units dc high - level input voltage v ih(dc) address, control, command sstl_18 v ref(dc) + 125 v ddq + 250 mv dc low - level input voltage v il(dc) address, control, command sstl_18 0 v ref(dc) - 125 mv ac high - level input voltage v ih(ac) ad dress, control, command sstl_18 v ref ( dc ) + 250 v dd mv ac low - level input voltage v il(ac) address, control, command sstl_18 0 v ref(dc) - 250 mv output high voltage v oh parity output lvcmos 1.2 - v output low voltage v ol parity output lvcmos - 0.5 v inpu t current i i all pins v i = v ddq or v ssq - 5 +5 a static standby i dd all pins reset# = v ssq (i o = 0) - 100 a static operating i dd all pins reset# = v ssq ; v i = v ih(ac) or v il(dc) i o = 0 - 40 ma dynamic operating (clock tree) i ddd n/a reset# = v dd , v i = v ih(ac) or v il(ac) , i o = 0; ck and ck# switching 50% duty cycle - varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2 , 5 0% duty cycle - varies by manufacturer a input capacitance (per device, per pin) c i data v i = v ref 250mv; v ddq = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c i reset# v i = v ddq or v ssq - varies by manufacturer pf notes: 1. timing and swit ching specifications for the register listed above are critical for proper operation of the ddr2 sdram registered dimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this register is available in jedec standard jesd82.
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 serial presence - detect matrix byte description 5300 - 555 4200 - 444 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x 08 2 fundamental memory type 0x 08 3 number of row addresses on assembly 0 x 0e 4 number of column addresses on assembly 0x 0a 5 dimm hight and module ranks 0x61 6 module data width 0x 48 7 module data width (continued) 0x 00 8 module voltage interface levels (v dd q ) 0x 05 9 sdram cycle time, (t ck ) [max cl] cas latency = 5 ( 4200 + 5300) 0x30 0x3d 10 sdram access from clock, (t ac ) [max cl] cas latency = 5 (4200 + 5300) 0x45 0x50 11 module configuration type 0x 06 12 refresh rate / type 0x 82 13 sdram device width (primary sdram) 0x 08 14 error - checking sdram data width 0x 08 1 5 minimum clock delay, back - to - back random column access 0x 00 16 burst lengths supported 0x 0c 17 number of banks on sdram device 0x 08 18 cas latencies supported 0x 38 19 module thickness 0x 01 20 ddr2 dimm type 0x 01 21 sdram module attributes 0x 05 22 sdram device attributes: weak driver and 50 odt 0x 07 23 sdram cycle time, (t ck ) [max cl C 1] cas latency = 4 (4200 + 5300) 0x 3d 24 sdram access from ck, (t ac ) [max cl C 1] cas latency = 4 (4200 + 5300) 0x50 25 sdram cycle time, (t ck ) [max cl C 2] cas l atency = 3 (4200 + 5300) 0x 50 26 sdram access from ck, (t ac ) [max cl C 2] cas latency = 3 (4200 + 5300) 0x 60 27 minimum row precharge time, (t rp ) 0x 3c 28 minimum row active to row active, (t rrd ) 0x 1e 29 minimum ras# to cas# delay, (t rcd ) 0x 3c 30 minim um ras# pulse width, (t ras ) 0x 2d 31 module bank density 0x01
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 serial presence - dtect matrix (continued) byte description 5300 - 555 4200 - 444 32 address and command setup time, (t isb ) 0x20 0x25 33 address and command hold time, (t ihb ) 0x27 0x37 34 data / data mask input setup time, (t dsb ) 0x10 0x 10 35 data / data mask input hold time, (t dhb ) 0x17 0x22 36 write recovery time, (t wr ) 0x 3c 37 write to read command delay, (t wtr ) 0x 1e 38 read to precharge command delay, (t rtp ) 0x 1e 39 mem analysis probe 0 x 00 40 extension for bytes 41 and 42 0x 06 41 min active auto refresh time, (t rc ) 0x 3c 42 minimum auto refresh to active / auto refresh command period, (t rfc) 0x7f 43 sdram device max cycle time, (t ckmax ) 0x 80 44 sdram device max dqs - dq skew time, (t d qsq ) 0x18 0x1e 45 sdram device max read data hold skew factor, (t qhs ) 0x22 0x28 46 pll relock time 0x 0f 47 - 61 optional features, not supported 0x 00 62 spd revision 0x 13 63 checksum for bytes 0 - 62 0x41 0x85 64 - 67 manufacturer`s jedec id code 0x 7f7f7fd a 68 - 71 manufacturer`s jedec id code (continued) 0x 00 72 manufacturing location xx 73 - 90 module part number (ascii) sep02g72e2bf2sa - xx 91 pcb identification code x 92 identification code (continued) x 93 year of manufacture in bcd x 94 week of ma nufacture in bcd x 95 - 98 module serial number x 99 - 127 manufacturer - specific data (rsvd) 0x00 128 - 255 open for customer use 0xff part number code s e p 02g 72 e2 b f 2 sa - 3 0 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr2 - 667mt/s sdram d dr 2 2 40 pin registered 1.8v chip vendor (samsung) depth (2gb) 2 module ranks width chip rev. f pcb - type ( b62rrcg 1.0 1 ) chip organisation x8 * optional / additi onal information
data sheet rev.1. 0 23.11.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@sw issbit.com of 14 locations swissbit ag industriestrasse 4 C 8 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berli n germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 14 willett avenue, suite 301a port chester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swi ssbit na, inc. 3913 todd lane, suite C 307 austin, tx 78744 usa phone: +1 512 302 9001 fax: +1 512 302 4808 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512

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