View SEP02G72D1BH2MT-25R_8053560.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 1 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 2 gb ddr2 C sdram registered dimm 240 pin rdimm sep02g72d1bh2mt - 25r 2 gb pc2 - 6 4 00 in fbga techn ology rohs compliant options: ? data rate / latency marking ddr2 800mt/s cl6 - 25 ddr2 667mt/s cl5 - 30 ? module density 2048mb with 18 dies and 2 ranks ? standard grade (t a ) 0c to 70c (t c ) 0c to 85c environmental requirements: ? operating temperature (t ambient ) standard gra de 0c to 70c ? operating humidity 10% to 90% relative humidity, noncondensing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, noncondensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c mechanical dimensions 1 1 if no tolerances specified 0.15mm features: ? 240 - pin 72 - bit ddr2 registered dual - in - line double data rate s ynchronous dram module for server applications ? module organization: dual rank 256 m x 72 ? v dd = 1.8v 0.1 v, v ddq 1.8 v 0.1 v ? 1.8v i/o ( sstl_18 compatible) ? serial presence detect with eeprom ? supports ecc error detection and correction ? jedec compatible ddr2 pll/register component with parity bit support for address and control bus ? gold - contact pad ? this module family is fu lly pin and functional compatible to jedec. (see www.jedec.org ) ? the pcb and all components are manufactured according to the rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (r ohs)] ? ddr2 sdram component micron mt47h128m8cf - 25 die - rev. h ? 128mx8 ddr 2 sdram in fbga - 60 package ? four bit prefetch architecture ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency C 1 t ck ? programmable burst le ngth: 4 or 8 ? adjustable data - output drive strength ? on - die termination (odt) ? dll to align dq and dqs transitions with ck 133 . 35 70 . 68 1 8 . 3 0 1 6 . 3 0 4 . 00 8 . 00 2 . 49 2 . 31 2 . 20
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 2 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 this swissbit module is an industry standard 240 - pin 8 - byte ddr2 registered sdram dual - in - line mem ory module ( r dimm) which is organized as x72 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr2 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr2 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr2 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr2 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high eff ective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_18 compatible. the ddr2 sdram module uses the serial presence detect (spd) function implemented via serial eepro m using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr2 sdrams used row addr. device bank select column addr. refresh module bank select 256 m x 72bit 18 x 128m x 8bit ( 1024m bit) 14 ba0, ba1 , ba2 10 8k s0#, s1# module dimensions in mm 133.33 (long) x 18.3 (high) x 4 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency sep02g72d1bh2mt - 25r 2048 mb 6.4 gb/s 2.5ns/800mt/s 6 - 6 - 6 sep02g72d1bh2mt - 30r 2048 mb 5.3 gb/s 3.0ns/667mt/ s 5 - 5 - 5 pin name a0 - a13 address inputs ba0, ba1 bank address inputs dq0 C dq63 data input / output cb0 C cb7 check bits dm0 - dm8 input data mask ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 clock enable ck0 cl ock input, positive line ck0# clock input, negative line dqs0 C dqs17 data strobe, positive line dqs0# - dqs17# data strobe, negative line (only used when differential data strobe mode is enabled) cs0#, cs1# chip select reset# asynchronously forces al l registered outputs low when reset# is low. this signal can be used during power - up to ensure that cke is low and dqs are high - z. figure 1: mechanical dimensions
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 3 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 p ar _in parity bit for the address and control bus. e rr _out parity error found on the address and control bus. v dd / v ddq s upply voltage (1.8v 0.1v) v ref input / output reference v ss ground v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0, odt1 on - die te rmination nc no connection pin configuration pin # front side pin # front side pin # back side pin # back side 1 v ref 61 a4 121 v ss 181 v ddq 2 v ss 62 v ddq 122 dq4 182 a3 3 dq0 63 a2 123 dq5 183 a1 4 dq1 64 v dd 124 v ss 184 v dd 5 v ss 65 v ss 125 d m0 ( dqs9 ) 185 ck0 6 dqs0# 66 v ss 126 nc ( dqs9# ) 186 ck0# 7 dqs0 67 v dd 127 v ss 187 v dd 8 v ss 68 p ar_ in 128 dq6 188 a0 9 dq2 69 v dd 129 dq7 189 v dd 10 dq3 70 a10 130 v ss 190 ba1 11 v ss 71 ba0 131 dq12 191 v ddq 12 dq8 72 v ddq 132 dq13 192 ras# 13 dq9 73 we# 133 v ss 193 cs0# 14 vss 74 cas# 134 dm1 ( dqs10 ) 194 v ddq 15 dqs1# 75 v ddq 135 nc ( dqs10# ) 195 odt0 16 dqs1 76 cs1# 136 v ss 196 a13 17 v ss 77 odt1 137 cke1 197 v dd 18 reset# 78 v ddq 138 cke1# 198 v ss 19 nc 79 v ss 139 v ss 199 dq36 20 v ss 80 dq 32 140 dq14 200 dq37 21 dq10 81 dq33 141 dq15 201 vss 22 dq11 82 v ss 142 v ss 202 dm4 ( dqs13 ) 23 v ss 83 dqs4# 143 dq20 203 nc ( dqs13# ) 24 dq16 84 dqs4 144 dq21 204 v ss 25 dq17 85 v ss 145 v ss 205 dq38 26 v ss 86 dq34 146 dm2 ( dqs11 ) 206 dq39 27 dqs2# 8 7 dq35 147 nc ( dqs11 ) 207 v ss 28 dqs2 88 v ss 148 v ss 208 dq44 29 v ss 89 dq40 149 dq22 209 dq45 30 dq18 90 dq41 150 dq23 210 v ss
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 4 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 pin # front side pin # front side pin # back side pin # back side 31 dq19 91 v ss 151 v ss 211 dm5 ( dqs14 ) 32 v ss 92 dqs5# 1 52 dq28 212 nc ( dqs14# ) 33 dq24 93 dqs5 153 dq29 213 v ss 34 dq25 94 v ss 154 v ss 214 dq46 35 v ss 95 dq42 155 dm3 ( dqs12 ) 215 dq47 36 dqs3# 96 dq43 156 nc ( dqs12# ) 216 v ss 37 dqs3 97 v ss 157 v ss 217 dq52 38 v ss 98 dq48 158 dq30 218 dq53 39 dq26 99 dq4 9 159 dq31 219 v ss 40 dq27 100 v ss 160 v ss 220 nc (ck2) 41 v ss 101 sa2 161 cb4 221 nc (ck2#) 42 cb0 102 nc (test) 162 cb5 222 v ss 43 cb1 103 v ss 163 v ss 223 dm6 ( dqs15 ) 44 v ss 104 dqs6# 164 dm8 ( dqs17 ) 224 nc ( dqs15# ) 45 dqs8# 105 dqs6 165 nc ( dqs17# ) 225 v ss 46 dqs8 106 v ss 166 v ss 226 dq54 47 v ss 107 dq50 167 cb6 227 dq55 48 cb2 108 dq51 168 cb7 228 v ss 49 cb3 109 v ss 169 v ss 229 dq60 50 v ss 110 dq56 170 v dd 230 dq61 51 v dd 111 dq57 171 cke1 231 v ss 52 cke0 112 v ss 172 v dd 232 dm7 ( dqs16 ) 53 v dd 113 dqs7# 173 nc (a15) 233 nc ( dqs16# ) 54 ba2 114 dqs7 174 nc (a14) 234 v ss 55 e rr _out 115 v ss 175 v dd 235 dq62 56 v ddq 116 dq58 176 a12 236 dq63 57 a11 117 dq59 177 a9 237 v ss 58 a7 118 v ss 178 v dd 238 v ddspd 59 v dd 119 sda 179 a8 239 sa0 60 a 5 120 scl 180 a6 240 sa1 (sig): signal in brackets may be routed to the socket connector, but is not used on the module
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 5 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 functional block diagramm 2048 mb ddr2 ecc registered dimm, 2 ranks and 18 components
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 6 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 maximum electrical dc characteristics param eter/ condition symbol min max units supply voltage v dd - 1.0 2.3 v i/o supply voltage v dd q - 0.5 2.3 v v dd l supply voltage v dd l - 0.5 2.3 v voltage on any pin relative to v ss v in , v out - 0.5 2.3 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 40 40 ck, ck# - 20 20 dm - 5 5 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 16 16 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v dd q 1.7 1.8 1.9 v v dd l supply voltage v dd l 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C ref v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.125 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.25 - v input low (logic 0) voltage v il (ac) - v ref - 0.25 v capacitance at ddr2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. simulati ons can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 7 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 i dd specifications and conditions (0c t case + 85c v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) parameter & test con dition symbol max. unit 6400 - 666 5300 - 555 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 873 828 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# i s high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 1053 963 ma precharge power - down current: all device banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref i dd2p 126 126 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd 2q 900 720 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 900 720 ma acti ve power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast pdn exit mr[12] = 0 i dd3p 720 540 ma slow pdn exit mr[12] = 1 180 180 active standby curre nt: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cyc le i dd3n 1080 990 ma operating read current *) : all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between va lid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 1503 1278 ma
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 8 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 parameter & test condition symbol max. unit 6400 - 666 5300 - 555 operating write current *) : all device banks open, c ontinuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq input s changing once per clock cycle i dd4w 1503 1278 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 4230 3870 ma self refresh current: ck and ck# at 0v; cke 0.2v ; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 126 126 ma operating current *) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 3078 2583 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 6400 - 666 5300 - 555 unit cl (i dd ) 6 5 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 60 ns t rrd (i dd ) 7.5 7.5 ns t ck (i dd ) 2.5 3.0 ns t ras min (i dd ) 45 45 ns t ras max (i dd ) 70 000 70 000 ns t rp (i dd ) 15 15 ns t rfc (i dd ) 105 105 ns
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 9 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 6400 - 666 5300 - 555 parameter symbol min max min max unit clock cycle time cl = 6 t ck (6) 2.5 8.0 - - ns cl = 5 t ck (5) 3.0 8.0 3.0 8.0 ns cl = 4 t ck (4) 3.75 8.0 3.75 8.0 ns cl = 3 t ck (3) - - 5.0 8.0 ns ck high - level width t ch 0.48 0.52 0.48 0.52 t ck ck low - level width t cl 0.48 0.52 0.48 0.52 t ck half clock period t hp min (t ch, t cl ) min (t ch, t cl ) ps access window (output) of dq s from ck/ck# t ac - 0.40 +0.40 - 0.45 +0.45 ns data - ou t high - impedance window from ck/ck# t hz t ac max +0.45 (= t ac max) ns data - out low - impedance window from ck/ck# t lz t ac min t ac max - 0.45 (= t ac min) +0.45 (= t ac max) ns dq and dm input setup time relative to dqs t ds 0.05 0.10 ns dq and dm input hol d time relative to dqs t dh 0.125 0.175 ns dq and dm input pulse width ( for each input ) t dipw 0.35 0.35 t ck data hold skew factor t qhs 0.3 0.34 ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh t hp - t qhs t hp - t qhs ns data va lid output window t dvw t qh - t dqsq t qh - t dqsq ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck dqs C t dqsq 0.2 0.24 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dqs write preamble t wpre 0.35 0.35 t ck dqs write preamble setup time t wpres 0 0 ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 - 0.25 + 0.25 t ck write command to first dqs latching transition wl - t dqss wl+ t dqss wl - t dqss wl+ t dqss t c k address and control input pulse width ( for each input ) t ipw 0.6 0.6 t ck address and control input setup time t is 0.175 0.2 ns
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 10 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 6400 - 666 5300 - 555 parameter symbol min max min max unit address and control input hold time t ih 0.25 0.275 ns cas# to cas# command delay t ccd 2 2 t ck active to act ive (same bank) command period t rc 60 60 ns active bank a to active bank b command t rrd 7.5 7.5 ns active to read or write delay t rcd 15 15 ns four bank activate period t faw 37.5 37.5 ns active to precharge command t ras 45 70,000 45 70,000 ns internal read to precharge command delay t rtp 7.5 7.5 ns write recovery time t wr 15 15 ns auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns internal write to read command delay t wtr 7.5 7.5 ns precharge command perio d t rp 15 15 ns precharge all command period t rpa t rp + t ck t rp + t ck ns load mode command cycle time t mrd 2 2 t ck cke low to ck, ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t ck refresh to active or refresh to refresh command interval t rfc 105 70 70 (0c<= t case <= 85 c) t refi 7.8 7.8 s (85c<= t case <= 95 c) t refi (it) 3.9 3.9 exit self refresh to non - read command t xsnr t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 t ck exit self refresh timing reference t isxr t is t is ps odt turn - on delay t aond 2 2 2 2 t ck odt turn - on t aon t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1,000 ps odt turn - off delay t aofd 2.5 2.5 2. 5 2.5 t ck odt turn - off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn - on (power - down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn - off (power - down mode) t aofpd t ac (mi n) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power - down entry latency t anpd 3 3 t ck
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 11 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 6400 - 666 5300 - 555 parameter symbol min max min max unit odt power - down exit latency t axpd 8 8 t ck odt enable from mrs command t mod 12 12 ns exit active power - down to read command , mr [bit 12 = 0] t xard 2 2 t ck exit active power - down to read command, mr [bit 12 = 1] t xards 8 C ck exit precharge power - down to any non - read command t xp 2 2 t ck cke minimum high/low time t cke 3 3 t ck register specifications pa rameter symbol pins conditions min max units dc high - level input voltage v ih(dc) address, control, command sstl_18 v ref(dc) + 125 v ddq + 250 mv dc low - level input voltage v il(dc) address, control, command sstl_18 0 v ref(dc) - 125 mv ac high - level input voltage v ih(ac) address, control, command sstl_18 v ref(dc) + 250 v dd mv ac low - level input voltage v il(ac) address, control, command sstl_18 0 v ref(dc) - 250 mv output high voltage v oh parity output lvcmos 1.2 - v output low voltage v ol parity output lv cmos - 0.5 v input current i i all pins v i = v ddq or v ssq - 5 +5 a static standby i dd all pins reset# = v ssq (i o = 0) - 100 a static operating i dd all pins reset# = v ssq ; v i = v ih(ac) or v il(dc) i o = 0 - 40 ma dynamic operating (clock tree) i ddd n/a re set# = v dd , v i = v ih(ac) or v il(ac), i o = 0; ck and ck# switching 50% duty cycle - varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i = v ih(ac) or v il(ac), i o = 0; ck and ck# switching 50% duty cycle; one data input swi tching at t ck/2 , 50% duty cycle - varies by manufacturer a input capacitance (per device, per pin) c i data v i = v ref 250mv; v ddq = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c i reset# v i = v ddq or v ssq - varies by manufacturer pf notes: 1. timing and switching specifications for the register listed above are critical for proper operation of the ddr2 sdram registered dimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this register is available in jedec standard jesd82.
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 12 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 serial presence - detect matrix byte description 6400 - 666 5300 - 555 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x 08 2 fundamental memory type 0x 08 3 number of row addre sses on assembly 0x 0e 4 number of column addresses on assembly 0x 0a 5 dimm hight and module ranks 0x61 6 module data width 0x 48 7 module data width (continued) 0x 00 8 module voltage interface levels (v dd q ) 0x 05 9 sdram cycle time, (t ck ) [max cl] cas latency = 6 (6400); cl = 5 (5300) 0x25 0x 30 10 sdram access from clock, (t ac ) [max cl] cas latency = 6 (6400); cl = 5 (53 00) 0x40 0x 45 11 module error correction configuration type 0x 06 12 refresh rate / type 0x 82 13 sdram device width (primary sdra m) 0x 08 14 error - checking sdram data width 0x 08 15 minimum clock delay, back - to - back random column access 0x 00 16 burst lengths supported 0x 0c 17 number of banks on sdram device 0x 08 18 cas latencies supported 0x70 0x 38 19 module thickness 0x 01 20 ddr2 dimm type 0x 01 21 sdram module attributes 0x 05 22 sdram device attributes: weak driver and 50 odt 0x 03 23 sdram cycle time, (t ck ) [max cl C 1] cas latency = 4 (6400); cl = 3 (5300) 0x30 0x 3d 24 sdram access from ck, (t ac ) [max cl C 1] cas latenc y = 4 (6400); cl = 3 (5300) 0x40 0x45 25 sdram cycle time, (t ck ) [max cl C 2] cas latency = 3 (6400); cl = 2 (5300) 0x 3d 0x 50 26 sdram access from ck, (t ac ) [max cl C 2] cas latency = 3 (6400); cl = 2 (5300) 0x 40 0x 45 27 minimum row precharge time, ( t rp ) 0x 3c 28 minimum row active to row active, (t rrd ) 0x 1e 29 minimum ras# to cas# delay, (t rcd ) 0x 3c 30 minimum ras# pulse width, (t ras ) 0x 2d 31 module bank density 0x01
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 13 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 serial presence - dtect matrix (continued) byte description 6400 - 666 5300 - 555 32 address and command setup time, (t isb ) 0x17 0x 20 33 address and command hold time, (t ihb ) 0x25 0x 27 34 data / data mask input setup time, (t dsb ) 0x 05 0x 10 35 data / data mask input hold time, (t dhb ) 0x12 0x17 36 write recovery time, (t wr ) 0x 3c 37 w rite to read command delay, (t wtr ) 0x 1e 38 read to precharge command delay, (t rtp ) 0x 1e 39 mem analysis probe 0x 00 40 extension for bytes 41 and 42 0x06 41 min active auto refresh time, (t rc ) 0x 3c 42 minimum auto refresh to active / auto refresh comma nd period, (t rfc) 0x7f 43 sdram device max cycle time, (t ckmax ) 0x 80 44 sdram device max dqs - dq skew time, (t dqsq ) 0x14 0x 18 45 sdram device max read data hold skew factor, (t qhs ) 0x1e 0x 22 46 pll relock time 0x 0f 47 - 61 optional features, not support ed 0x 00 62 spd revision 0x 13 63 checksum for bytes 0 - 62 0xf2 0x17 64 - 6 7 manufacturer`s jedec id code 0x 7f 7f7fda 68 - 71 manufacturer`s jedec id code (continued) 0x 00 72 manufacturing location x 73 - 90 module part number (ascii) sep02g72d1bh2mt - xx 91 pcb identification code x 92 identification code (continued) x 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95 - 98 module serial number x 99 - 127 manufacturer - specific data (rsvd) 0x00 128 - 255 open for customer use 0xff part numbe r code s e p 0 2 g 72 d 1 b h 2 mt - 25 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr2 - 800 m t/s sdram d dr 2 2 4 0 pin registered 1.8v chip vendor ( micron ) depth ( 2 gb ) 2 module ranks width chip rev. h pcb - type ( b 8 2 v rrc t 3 . 98 ) chip organisation x8 * optional / additional information
data sheet rev.1. 2 25 . 11 .2010 swissbit ag industriestrasse 4 fon: +4 1 (0) 71 913 03 03 www. swissbit.com page 14 ch - 9552 bronschhofen fax: +4 1 (0) 71 913 03 15 email: info@swissbit.com of 14 locations swissbit ag industriestrasse 4 C 8 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fa x: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 14 willett avenue, suite 301a port chester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swissbit na, inc. 3913 todd lane, suite C 307 austin, tx 78744 usa phone: +1 512 302 9001 fax: +1 512 302 4808 _____________________________ swi ssbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512

▲Up To Search▲

Price & Availability of SEP02G72D1BH2MT-25R

	To Download SEP02G72D1BH2MT-25R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .