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data sheet, rev. 1.31, dec. 2005 communications samurai 6 port 10/100 mbit/s single chip ethernet switch controller (adm6996lcx - green package version; adm6996lhx - heat sink and green package) version ac
edition 2005-12-05 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. template: template_a4_3.1.fm / 3.1 / 2005-11-01 trademarks abm ? , aop ? , bluemoon ? , convergate ? , c166 ? , duslic ? , falc ? , geminax ? , inca ? , iom ? , ipvd ? , isac ? , iwe ? , iworx ? , muslic ? , octalfalc ? , octat ? , quadfalc ? , scout ? , serocco ? , s-gold ? , sicofi ? , sieget ? , smarti ? , socrates ? , vinetic ? , wdtc ? , 10bases ? are registered trademarks of infineon technologies ag. ace?, arcofi?, asm?, asp?, bluenix?, digitape?, dualfalc?, easyport?, e-gold?, e-goldlite?, epic?, ipat-2?, elic?, idec?, itac?, m-gold?, sct?, s-gold2?, s-gold3?, musac?, potswire?, quat?, s-goldlite?, sicat?, sidec?, slicofi?, vdslite?, 10basev?, 10basevx? are trademarks of infineon technologies ag. microsoft ? and visio ? are registered trademarks of microsoft corporation. linux ? is a registered trademark of linus torvalds. framemaker ? is a registered trademark of adobe systems incorporated. apoxi ? is a registered trademark of comneon gmbh & co. ohg. primecell ? , realview ? , arm ? are registered trademarks of arm limited. oakdspcore ? , teaklite ? dsp core, ocem ? are registered trademarks of parthusceva inc. indoorgps?, gl-20000?, gl-ln-22? are trademarks of global locate. arm926ej-s?, ads?, multi-ice? are trademarks of arm limited. samurai 6 port 10/100 mbit/s single chip ethernet switch controller (adm6996lcx - green package version) revision history: 2005-12-05, rev. 1.31 previous version: 2005-04-28, rev.1.1 page/ date subjects (major changes since last revision) page19 modify lnkfp5 pin description page 71~156 add 16bits mode registers description 2005-08-30 changed to the new infineon format 2005-08-30 rev. 1.1 changed to rev. 1.3 update in content 2005-11-07 revision 1.3 changed to revision 1.31minor change. included green package information and heat sind information data sheet 4 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 pin description by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 10/100m phy block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 100base-x module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 100base-x receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.1 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.2 adaptive equalizer and timing recovery module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.3 nrzi/nrz and serial/parallel decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.4 data de-scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.5 symbol alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.6 symbol decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.7 valid data signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.8 receive errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.9 100base-x link monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.10 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.11 bad ssd detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.12 far-end fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 100base-tx transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.1 transmit drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.2 twisted-pair receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 10base-t module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.1 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.2 manchester encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.3 transmit driver and receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.4 smart squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.8 jabber function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.9 link test function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10 automatic link polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.12 auto negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.13 memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14 switch functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15.1 address learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents data sheet 5 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx table of contents 3.15.2 address recognition and packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.3 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.4 back off algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.5 inter-packet gap (ipg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.6 illegal frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.7 half duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.8 full duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.9 old broadcast storm filter (0x0b[0]=0 and 0x11[6]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.10 new broadcast/multicast storm (0x0b[0]=1 and 0x11[6]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16 auto tp mdix function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.17 port locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.18 vlan setting & tag/untag & port-base vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.19 old fixed ingress bandwidth control (0x0b[0]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20 new scalable egress/ingress bandwidth control (0x0b[0]=1 and 0x33[12]=1) . . . . . . . . . . . . . . . . . 33 3.21 mac table accessible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.22 priority setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.23 led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23.1 single color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23.2 dual color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.3 circuit for single led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.23.4 circuit for dual led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.24 mac clone and port5 mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.25 the hardware difference between adm6996lc/lcx/i and adm6996l . . . . . . . . . . . . . . . . . . . . . . 40 4 32 bits mode registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 eeprom registers (0x0b[0]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.1 eeprom register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 serial registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2.1 serial register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3 packet with priority: normal packet content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4 vlan packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 tos ip packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6 eeprom access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.7 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5 16 bits mode registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 eeprom basic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 eeprom extended registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3 counter and switch status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.4 phy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6 hardware, eeprom and smi interface for configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.1 hardware setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.2 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3 smi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1 tx/fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1.1 tp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1.2 fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7.2 dc characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7.3 ac characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.3.1 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.3.2 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 samurai adm6996lc/lcx/lhx table of contents data sheet 6 rev. 1.31, 2005-12-05 7.3.3 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.3.4 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.3.5 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.3.6 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.3.7 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.3.8 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.3.9 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.3.10 reduce mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.3.11 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.3.12 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.3.13 sdc/sdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 77 8.1 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 data sheet 7 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx list of figures figure 1 adm6996lc/lcx/lhx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2 5 tp/fx port + 1 mii port 128 pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 3 circuit for single color led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 4 circuit for dual color led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 5 adm6996lc/lcx to cpu with single mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6 mac clone enable and vlan setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 7 100m full duplex mac to mac mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 8 old router architecture example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 9 new router architecture using adm6996lc/lcx/lhx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10 cpu generated reset signal requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 11 cpu write eeprom command requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 12 serial interface read command timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 13 serial interface reset command timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 14 interconnection between adm6996lc/lcx/lhx, eeprom and cpu . . . . . . . . . . . . . . . . . . . . 159 figure 15 tp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 16 fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 17 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 18 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 19 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 20 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 21 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 22 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 23 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 24 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 25 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 26 reduce mii timing (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 27 reduce mii timing (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 28 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 29 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 30 sdc/sdio timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 31 p-pqfp-128 outside dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 list of figures data sheet 8 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx list of tables table 1 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3 io signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6 fixed ingress bandwidth control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7 single color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8 dual color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 9 pin description(qfp128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 10 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 12 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 13 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 14 basic control registers 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 15 reserved register 1 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 16 reserved register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 17 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19 drop scheme for each queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20 vlan mapping table registers 1 to 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 21 reserved register 8 to 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 22 note: reference table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 26 per port counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 27 ethernet packet from layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 28 vlan packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 29 ip packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 30 resetl & eeprom content relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 31 broadcast storming threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 32 priority queue weight ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 33 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 34 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 35 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 36 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 37 basic control registers 1 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 38 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 39 pxso registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 40 vfxl registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 41 vfxh registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 42 tfx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 43 pfx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 44 tufx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 45 clx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 46 chx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 47 phy_cx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 48 phy_sx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 49 phy_ix_a registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 list of tables data sheet 9 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx list of tables table 50 phy_ix_b registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 51 anapx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 52 anlpax registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 53 anex registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 54 nptx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 55 lpnpx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 56 hardware setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 57 (d) the pin type of eecs, eesk, edi and edo during the operation . . . . . . . . . . . . . . . . . . . 162 table 58 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 59 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 60 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 61 dc electrical characteristics for 3.3 v operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 62 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 63 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 64 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 65 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 66 10-base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 67 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 68 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 69 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 70 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 71 reduce mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 72 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 73 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 74 sdc/sdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 samurai adm6996lc/lcx/lhx product overview data sheet 10 rev. 1.31, 2005-12-05 1 product overview 1.1 overview the samurai (adm6996lc/lcx/lhx) is a high performance, low cost, highly integrated (controller, phy and memory) five-port 10/100 mbit/s tx/fx plus one 10/100 mac port ethernet switch controller with all ports supporting 10/100 mb/s full/half duplex. the adm6996lc/lcx/lhx is intended for applications for stand alone bridges for low cost soho markets such as wire/adsl/wireless router, ip set top box, vdsl2, gateway and homepna/homeplug applications. the adm6996lcx is the environmentally friendly ?green? package version. the lh solution contains a heat sink which can be used in special circumstances but is not recommended for all projects. adm6996lc/lcx/lhx provides advanced functions such as: 802.1p(q.o.s.), port-based/tag-based vlan, port mac address locking, management, port status, mac address access and bandwidth control . the adm6996lc/lcx/lhx also supports back pressure in half-duplex mode and 802.3x flow control pause packet in full-duplex mode to prevent packet loss when buffer is full. when back pressure is enabled, and there is no receive buffer available for the incoming packet, the adm6996lc/lcx/lhx will issue a jam pattern on the receiving port in half duplex mode and transmit the 802.3x pause packet back to receiving end in full duplex mode. the built-in sram used for packet buffering is divided into 256 bytes/block to achieve the optimized memory utilization through complicated link lists on packets with various lengths. adm6996lc/lcx/lhx also supports priority features by port-base, vlan, ip tos, tcp/udp layer4 destination port number, mac destination address field checking. users can be easily set different priority modes in individual ports, through a small low-cost micro controller to initialize or on-the-fly to configure. each output port supports four queues in the way of fixed n:1 or programmable fairness queuing to fit the bandwidth demand on various types of packets such as voice, video and data. tag/untag, and up to 16 groups of vlan also is supported. an intelligent address recognition algorithm makes adm6996lc/lcx/lhx to recognize up to 2k different mac addresses and enables filtering and forwarding at full wire speed. port mac address locking function is also supported by adm6996lc/lcx/lhx to use on building internet access to prevent multiple users sharing one port traffic. 1.2 features ? supports five 10m/100m auto-detect half/full duplex switch ports with tx/fx interfaces and one mii/gpsi port. ? supports 2k mac addresses table with 4-ways associative hash algorithm. ? supports four queue for qos ? supports priority features by port-based, 802.1p, ip tos of packets, layer4 tcp/udp destination port number and mac address da. ? supports mac dress accessible such as search, add and delete. ? supports engress/ingress 64k scalable bandwidth control. ? supports store & forward architecture and performs forwarding and filtering at non-blocking full wire speed. ? supports buffer allocation with 256 bytes per block ? supports aging function enable/disable. ? supports per port single/dual color mode with power on auto diagnostic. ? supports 802.3x flow control pause packet for full duplex in case buffer is full. ? supports back pressure function for half duplex operation in case buffer is full. ? supports packet length up to 1518/1522 (default)/1536/1784 bytes in maximum. ? broadcast/multicast storm suppression. data sheet 11 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx product overview ? supports tag-based vlan. up to 16 vlan groups is implemented by the last four bits of vlan id. ? 2bit mac clone to support multiple wan application ? supports tp interface auto mdix function for auto tx/rx swap by strapping-pin. ? easy management 32bits smart counter for per port rx/tx byte/packet count, 16-bit smart counter for per port error count and collision count through serial 32/16 bits mode access. 16 bits mode is mdc/mdio timing compatible. ? supports phy status output for management system. ? 25m crystal only for the whole system. ? 128 qfp package with 0.18um technology. 1.8 v/3.3 v power supply. ? 1.0 w low power consumption. 1.3 applications adm6996lc/lcx/lhx in 128-pin pqfp: ? wire/adsl/wireless/vdsl2 router ? ip setop box, homepna, homeplug application. samurai adm6996lc/lcx/lhx product overview data sheet 12 rev. 1.31, 2005-12-05 1.4 block diagram figure 1 below shows a simple block diagram of the adm6996lc/lcx/lhx internal blocks. figure 1 adm6996lc/lcx/lhx block diagram po rt 0 po rt 1 po rt 2 ... po rt 4 mlt3 nrz nrzi digital equalizer nrz to 5b 5b to nrz txn7 txp7 driver a/d con v ert er rx n 7 rx p7 base line correction clock generator bias 10/100m mac descrambler data handler jabber detector carrier integrity monitor fifo partition handler scramble r transmit state machine led display control twisted pai r interface led interface ... 10/100m mac 10/100m mac 10/100m mac switching fabric embedded memory mii interface memory bist eeprom handler eeprom interface data sheet 13 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 2 interface description this chapter describes the interface descriptions for the adm6996lc/lcx/lhx ?pin diagram ? abbreviations ? pin description by function 2.1 pin diagram figure 2 shows the pin diagram for the adm6996lc/lcx/lhx. figure 2 5 tp/fx port + 1 mii port 128 pin diagram dupcol4 gndo vcc3o dupcol3 dupcol2 (bpen) dupcol1 (phyas1) dupcol0 (recanen) vccik gndik rc xi xo vccpll gndpll control vref gndbias rtx vccbias vcca2 txp0 txn0 gnda rxp0 rxn0 vccad gndik (gfcen)txd0 p4fx (p5_busmd0)txd1 (p5_busmd1)txd2 (sdio_md)txd3 ldspd4 gndo vcc3o ldspd3 ldspd2 vccik gndik ldspd1 ldspd0 test vccik gndik gndo vcca2 txp4 txn4 gnda rxp4 rxn4 vccad vc ci k txen (phyas0) txclk/refclk_out rx er gndo gndo vc c3 o rx clk /r efc lk_i n rx dv rx d0 vc ci k gndik cr s col edi (ledmode) eecs eesk (xoven) vc ci k gndik edo cko25m cf g0 gndo vc c3 o spdtnp5 lnkfp5 dp hal fp 5 lnkact4 gndik vc ci k lnkact3 lnkact2 lnkact1 lnkact0 gndo rx d1 rx d2 rx d3 samurai-lc adm6996lc rx n3 rx p3 gnda txn3 txp3 vcca2 nc nc nc nc nc nc vccad rx n2 rx p2 gnda txn2 txp2 vcca2 nc nc nc nc nc nc vccad rx n1 rx p1 gnda txn1 txp1 vcca2 nc nc nc nc nc nc 104 103 105 112 111 110 109 108 107 106 113 114 116 115 117 124 123 122 121 120 119 118 125 126 128 127 68 69 70 71 72 73 74 75 76 77 67 66 65 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 10 1 10 2 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 40 41 39 63 64 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 1 31 32 33 34 35 36 37 38 samurai adm6996lc/lcx/lhx interface description data sheet 14 rev. 1.31, 2005-12-05 2.2 abbreviations standard abbreviations for i/o tables: 2.3 pin description by function adm6996lc/lcx/lhx pins are categorized into one of the following groups: ? network media connection ? port 5 mii interface ? led interface ? eeprom interface ? power/ground, 48 pins ? miscellaneous table 1 abbreviations for pin type abbreviations description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. ao output. analog levels. ai/o input or output. analog levels. pwr power gnd ground mcl must be connected to low (jedec standard) mch must be connected to high (jedec standard) nu not usable (jedec standard) nc not connected (jedec standard) table 2 abbreviations for buffer type abbreviations description z high impedance pu pull up, 10 k ? pd pull down, 10 k ? ts tristate capability: the corresponding pin has 3 operational states: low, high and high- impedance. od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. an external pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. oc open collector pp push-pull. the corresponding pin has 2 operational states: active-low and active-high (identical to output with no type attribute). od/pp open-drain or push-pull. the corresponding pin can be configured either as an output with the od attribute or as an output with the pp attribute. st schmitt-trigger characteristics ttl ttl characteristics data sheet 15 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description note: table 1 can be used for reference. table 3 io signals ball no. name pin type buffer type function network media connection 41 rxp_4 ai/o ana receive pair differential data is received on this pin. 37 rxp_3 24 rxp_2 11 rxp_1 126 rxp_0 40 rxn_4 ai/o ana 38 rxn_3 25 rxn_2 12 rxn_1 127 rxn_0 44 txp_4 ai/o ana transmit pair differential data is transmitted on this pin. 34 txp_3 21 txp_2 8 txp_1 123 txp_0 43 txn_4 ai/o ana 35 txn_3 22 txn_2 9txn_1 124 txn_0 port 5 mii interface 63 gfcen i pu, lvttl global flow control enable value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl( rc ) as flow control enable. note: power on setting 0 b flow control capability is depended upon the register setting in corresponding eeprom register 1 b all ports flow control capability is enabled mii_txd0 o 4 ma, pu, lvttl port 5 transmit data bit 0 in mii mode the bit[0] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. gpsi_txd o 4 ma, pu, lvttl port 5 transmit data in gpsi mode when port 5 is operating in gpsi mode, this pin acts as gpsi transmit data. synchronous to the rising edge of gpsi_txclk. rmii_txd0 o 4 ma, pu, lvttl port 5 transmit data bit 0 in rmii mode when port 5 is operating in rmii mode, this pin acts as rmii transmit data bit [0]. synchronous to the rising edge of refclk_in. samurai adm6996lc/lcx/lhx interface description data sheet 16 rev. 1.31, 2005-12-05 61 p5_busmd0 i pd, lvttl port 5 bus mode selection bit 0 value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as port 5 bus mode selection bit 0. combined with p5_busmd1 , adm6996lc/lcx/lhx provides 3 bus type for port 5. p5_busmd[1:0], interface note: power on setting 00 b mii 01 b gpsi 10 b rmii 11 b reserved and not allowed mii_txd1 o 4 ma, pd, lvttl port 5 transmit data bit 1 in mii mode the bit[1] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. rmii_txd1 o 4 ma, pd, lvttl port 5 transmit data bit 1 in rmii mode the bit[1] of rmii transmit data of port 5. synchronous to the rising edge of refclk_in. 60 p5_busmd1 i pd, lvttl port 5 bus mode selection bit 1 value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as port 5 bus mode selection bit 1. combined with p5_busmd0 , adm6996lc/lcx/lhx provides 3 bus type for port 5. note: power on setting mii_txd2 o 4 ma, pd, lvttl port 5 transmit data bit 2 in mii mode the bit[2] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. 59 sdio_md i pd, lvttl sdc/sdio mode selection value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl for sdio 32/16 bits selection. 0 b 32 bits mode 1 b 16 bits mode. same timing as mdc/mdio. mii_txd3 o 4 ma, pd, lvttl port 5 transmit data bit 3 in mii mode the bit[3] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. table 3 io signals (cont?d) ball no. name pin type buffer type function data sheet 17 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 66 phyas0 i pd, lvttl phy address msb bit 0 during power on reset, value will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as phy start address select. phyas[1:0] = 00 b and phy address starts from 01000 b . note: power on setting mii_txen o 8 ma, pd, lvttl port 5 transmit enable txen in mii mode active high to indicate that the data on mii_txd[3:0] is valid. synchronous to the rising edge of mii_txclk. gpsi_txen o 8 ma, pd, lvttl port 5 transmit enable txen in gpsi mode active high to indicate that the data on gpsi_txd is valid. synchronous to the rising edge of gpsi_txclk. rmii_txen o 8 ma, pd, lvttl port 5 r transmit enable txen in rmii mode active high to indicate that the data on rmii_txd[1:0] is valid. synchronous to the rising edge of refclk_in. 74 mii_rxd0 i pd, lvttl port 5 receive data bit 0 in mii mode the bit[0] of mii receive data, synchronous to the rising edge of mii_rxclk. gpsi_rxd i pd, lvttl port 5 receive data in gpsi mode in gpsi mode, this acts as receive data input, synchronous to the rising edge of gpsi_rxclk. rmii_rxd0 i pd, lvttl port 5 receive data bit 0 in rmii mode the bit[0] of rmii receive data, synchronous to the rising edge of refclk_in. 100 mii_rxd1 i pd, lvttl port 5 receive data bit 1in mii mode the bit[1] of mii receive data, synchronous to the rising edge of mii_rxclk. rmii_rxd1 i pd, lvttl port 5 receive data bit 1in rmii mode bit[1] of rmii receive data, synchronous to the rising edge of refclk_in. 101 mii_rxd2 i pd, lvttl port 5 receive data bit 2 in mii mode the bit[2] of mii receive data. synchronous to the rising edge of mii_rxclk. 102 mii_rxd3 i pd, lvttl port 5 receive data bit 3 in mii mode the bit[3] of mii receive data. synchronous to the rising edge of mii_rxclk. 73 mii_rxdv i pd, lvttl port 5 receive data valid in mii mode active high to indicate that the data on mii_rxd[3:0] is valid. synchronous to the rising edge of mii_rxclk. rmii_crsdv i pd, lvttl port 5 carrier sense and receive data valid in rmii mode active high to indicate that the data on rmii_rxd[1:0] is valid. synchronous to the rising edge of refclk _in. table 3 io signals (cont?d) ball no. name pin type buffer type function samurai adm6996lc/lcx/lhx interface description data sheet 18 rev. 1.31, 2005-12-05 68 mii_rxer i pd, lvttl port 5 receive error in mii mode active high to indicate that there is error on the mii_rxd [3:0]. upon receiving this signal, adm6996lc/lcx/lhx will send error symbol onto the medium. only valid in 100m operation. rmii_rxer i pd, lvttl port 5 receive error in rmii mode active high to indicate that there is error on the rmii_ rxd[1:0]. upon receiving this signal, adm6996lc/lcx/lhx will send error symbol onto the medium. only valid in 100m operation. 77 mii_crs i pd, lvttl port 5 carrier sense in mii mode in full duplex mode, mii_p5crs reflects the receive carrier sense situation on medium only; in half duplex, mii_crs will be high both in receive and transmit condition. gpsi_crs i pd, lvttl port 5 carrier sense in gpsi mode in full duplex mode, gpsi_crs reflects the receive carrier sense situation on medium only; in half duplex, gpsi_crs will be high both in receive and transmit condition. 78 mii_col i pd, lvttl port 5 collision input in mii mode active high to indicate that there is collision on the medium. stay low in full duplex operation. gpsi_col i pd, lvttl port 5 collision input in gpsi mode active high to indicate that there is collision on the medium. stay low in full duplex operation. 72 mii_rxclk i pd, lvttl port 5 receive clock inputin mii mode mii_rxdv and mii_rxd[3:0] are synchronous to the rising edge of this clock. it is free running 25 mhz clock in 100m mode and 2.5 mhz clock in 10m mode. gpsi_ rxclk i pd, lvttl port 5 receive clock input in gpsi mode gpsi_rxd are synchronous to the rising edge of this clock. it is non-continuous 10 mhz clock input. refclk_in i pd, lvttl 50mhz reference clock input in rmii mode rmii_rxd[1:0], rmii_txd[1:0], rmii_txen and rmii_crsdv are synchronous to the rising edge of this clock. 67 mii_txclk i pd, lvttl port 5 transmit clock input in mii mode mii_txen and mii_txd[3:0] are output at the rising edge of this clock. it is free running 25 mhz clock in 100m mode and 2.5 mhz clock in 10m mode. gpsi_txclk i pd, lvttl port 5 transmit clock input in gpsi mode gpsi_txen and gpsi_txd are synchronous to the rising edge of this clock. it is continuous 10 mhz clock input. refclk _ out o 8 ma, pd, lvttl 50mhz reference clock output in rmii mode this pin is used as 50 mhz reference clock signal output pin when port 5 operates in rmii mode. table 3 io signals (cont?d) ball no. name pin type buffer type function data sheet 19 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 89 spdtnp5 i pd, lvttl port 5 speed input 0 b 100m 1 b 10m 90 lnkfp5 i pd, lvttl port 5 link fail status input 0 b link up 1 b link failed 91 dphalfp5 i pd, lvttl port 5 duplex status input 0 b full duplex 1 b half duplex led interface 103 dupcol4 o 8 ma, pd, lvttl port 4 duplex /collision led in full duplex mode, this pin acts as duplex led for port 4, respectively; in half duplex mode, it is collision led for each port. see chapter 3.23 led display for more detail. 106 dupcol3 o 8 ma, pd, lvttl port 3 duplex /collision led in full duplex mode, this pin acts as duplex led for port 3, respectively; in half duplex mode, it is collision led for each port. see chapter 3.23 led display for more detail. 107 bpen i pu, lvttl recommend back-pressure in half-duplex the value on this pin will be latched by adm6996lc/lcx/lhx during power on reset as the beck- pressure enable in half-duplex mode. note: power on setting 0 b disable back-pressure 1 b enable back-pressure dupcol2 o 8 ma, pu, lvttl port 2 duplex-collision led in full duplex mode, this pin acts as port 2 duplex led; in half duplex mode, it is collision led for port 2. see chapter 3.23 led display for more detail. 108 phyas1 i pd, lvttl recommend phy address bit 1 value on this pin will be latched by adm6996lc/lcx/lhx during power on reset as the phy address recommend value bit 1. see phyas0 description for more detail. note: power on setting dupcol1 o 8 ma, pd, lvttl port 1 duplex-collision led in full duplex mode, this pin acts as port 1 duplex led; in half duplex mode, it is collision led for port 1. see chapter 3.23 led display for more detail. table 3 io signals (cont?d) ball no. name pin type buffer type function samurai adm6996lc/lcx/lhx interface description data sheet 20 rev. 1.31, 2005-12-05 109 recanen i pu, lvttl recommend auto negotiation enable only valid for twisted pair interface. programming this bit to 1 has no effect on the fiber port. note: power on setting. 0 b disable all tp port auto negotiation capability 1 b enable all tp port auto negotiation capability dupcol0 o 8 ma, pu, lvttl port 0 duplex-collision led in full duplex mode, this pin acts as port 0 duplex led; in half duplex mode, it is the collision led for port 0. see chapter 3.23 led display for more detail. 92 lnkact_4 o 8 ma, pd, lvttl link/activity led of port 4 to 0 used to indicate corresponding port? s link/activity status, see chapter 3.23 led display for more detail. 95 lnkact_3 96 lnkact_2 97 lnkact_1 98 lnkact_0 58 ldspd_4 o 8 ma, pd, lvttl port 4 to port 0 speed led used to indicate corresponding port? s speed status, see chapter 3.23 led display for more detail. 55 ldspd_3 54 ldspd_2 51 ldspd_1 50 ldspd_0 eeprom interface 84 edo i pu, lvttl eeprom data output this pin is used to input eeprom data when reading eeprom. during adm6996lc/lcx/lhx initialization, adm6996lc/lcx/lhx will drive eeprom interface signal to read settings from eeprom. any other devices attach to eeprom interface should driv e hi-z or keep tristate during this period. see chapter 4.6 eeprom access for more detail. 80 ifsel i pd, lvttl interface selection after adm6996lc/lcx/lhx initialization, this pin is used to select using eeprom interface or sdc/sdio interface. eecs/ifsel interface 0 b sdc/sdio interface 1 b eeprom interface eecs o 4 ma, pd, lvttl eeprom chip select during adm6996lc/lcx/lhx initialization, this pin is used as the eeprom chip select signal. during adm6996lc/lcx/lhx initialization, adm6996lc/lcx/lhx will drive eeprom interface signal to read settings from the eeprom. any other devices attached to the eeprom interface should drive hi-z or keep tristate during this period. see chapter 4.6 eeprom access for more detail. table 3 io signals (cont?d) ball no. name pin type buffer type function data sheet 21 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 81 xoven i pd, lvttl cross over enable value on this pin (active low) will be latched by adm6996lc/lcx/lhx at the rising edge of resetl for port 4~0 crossover auto detect (only available in tp interface). note: power on setting. 0 b disable 1 b enable eesk i/o 4 ma, pd, lvttl eeprom serial clock during adm6996lc/lcx/lhx initialization, this pin is used to output clock to eeprom. after adm6996lc/lcx/lhx initialization process is done, this pin is used as eeprom interface clock input if ifsel = 1. sdc i pd, lvttl serial management interface clock input if ifsel = 0, this pin is used as a serial management interface clock input. 79 led_mode i pd, lvttl enable mac to choose led display mode value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as dsingle/dual color led mode control signal. see chapter 3.23 led display for more detail. note: power on setting. edi i/o 8 ma, pd, lvttl eeprom serial data input during adm6996lc/lcx/lhx initialization, this pin is used to output address and command to access eeprom. after the initialization process is done, this pin becomes an input pin to monitor eeprom data if ifsel = 1. sdio i/o 8 ma, pd, lvttl serial management interface data input/output if ifsel = 0, this pin is used as data input/output pin of serial management interface. power/ground, 48 pins 10, 23, 36, 42, 125 gnda gnd ? ground used by ad block 7, 20, 33, 45, 122 vcca2 pwr ? 1.8 v, power used by tx line driver 13, 26, 39, 128 vccad pwr ? 3.3 v, power used by ad block 119 gndbias gnd ? ground used by bias block 121 vccbias pwr ? 3.3 v, power used by bias block. 116 gndpll gnd ? ground used by pll table 3 io signals (cont?d) ball no. name pin type buffer type function samurai adm6996lc/lcx/lhx interface description data sheet 22 rev. 1.31, 2005-12-05 115 vccpll pwr ? 1.8 v, power used by pll 47, 52, 64, 76, 83, 93 gndik gnd ? ground used by digital core 48, 53, 75, 82, 94, 110 vccik pwr ? 1.8 v, power used by digital core 46, 57, 70, 87, 99, 104 gndo gnd ? ground used by digital pad 56, 71, 88, 105 vcc3o pwr ? 3.3 v, power used by digital pad miscellaneous 62 p4fx i pd, lvttl port 4 fiber selection during power on reset, value will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as port 4 fiber select. 0 b twisted pair mode 1 b fiber mode 65 int_n o od,8 ma interrupt active low interrupt signal to indicate the status change in the interrupt status register. interrupt signal will keep active low until host read the status of isr register. 0 b interrupt 1 b not interrupt 69 wait_init i pd, lvttl wait initialization this pin will be used to pause all activities after power up until eeprom is loaded successfully or cpu initialization is done. 0 b pause until loading eeprom is done. 1 b pause until eeprom successfully loaded or cpu initialization is done. 1, 2, 3, 4, 5, 6, 14, 15, 16, 17, 18, 19, 27, 28, 29, 30, 31, 32 nc - - not connected 49 test i pd, lvttl test mode reserved and should be kept 0 when under normal operation. 86 cfg0 i pu, lvttl configuration 0 reserved and should be kept 0 when under normal operation. 85 cko25m o 8 ma, pd, lvttl 25mhz clock output free running 25 mhz clock output (even during power on reset) table 3 io signals (cont?d) ball no. name pin type buffer type function data sheet 23 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 112 rc i st rc input for power on reset this pin is sampled by using the 25 mhz free running clock signal which inputs from xi to generate the low-active reset signal, resetl. see chapter 7.3.2 power on reset for the timing requirement. 113 xi ai ana 25mhz crystal /oscillator input 25mhz crystal or oscillator input. variation is limited to +/- 50ppm. 114 xo ao ana 25m crystal output when connected to oscillator, this pin should be left unconnected. 120 rtx ai ana constant voltage reference external 1.0 k ? 1% resistor connection to ground. 118 vref ai ana analog reference voltage used by internal bias circuit for voltage reference. external 0.1uf capacitor connection to ground for noise filter. 117 control ai/o ana fet control signal the pin is used to control fet for 3.3 v to 1.8 v regulator. external 0.1uf capacitor connection to ground for noise filter, even the pin is un-connected. table 3 io signals (cont?d) ball no. name pin type buffer type function samurai adm6996lc/lcx/lhx function description data sheet 24 rev. 1.31, 2005-12-05 3 function description 3.1 functional descriptions the adm6996lc/lcx/lhx integrates five 100base-x physical sub-layer (phy), 100base-tx physical medium dependent (pmd) transceivers, five complete 10base-t modules, a 6 port 10/100 switch controller and one 10/100 mii/gpsi mac and memory into a single chip for both 10mbit/s, 100mbit/s ethernet switch operation. it also supports 100base-fx operation through external fiber-optic transceivers. the device is capable of operating in either full duplex mode or half-duplex mode in 10mbit/s and 100mbit/s. operational modes can be selected by hardware configuration pins, software settings of management registers, or determined by the on-chip auto negotiation logic. the adm6996lc/lcx/lhx consists of three major blocks: ? 10/100m phy block ? switch controller block ?built-in ssram the interfaces used for communication between the phy block and switch core is an mii interface. an auto mdix function is supported in this block. this function can be enabled and disabled by the hardware pin. 3.2 10/100m phy block the 100base-x section of the device implements the following functional blocks: ? 100base-x physical coding sub-layer (pcs) ? 100base-x physical medium attachment (pma) ? twisted-pair transceiver (pmd) the 100base-x and 10base-t sections share the following functional blocks: ? clock synthesizer module ? mii registers ? ieee 802.3u auto negotiation 3.3 100base-x module the adm6996lc/lcx/lhx implements a 100base-x compliant pcs and pma and 100base-tx compliant tp- pmd as illustrated in figure 2. bypass options for each of the major functional blocks within the 100base-x pcs provides flexibility for various applications. 100mbit/s phy loop back is included for diagnostic purpose. 3.4 100base-x receiver the 100base-x receiver consists of functional blocks required to recover and condition the 125mbit/s receive data stream. the adm6996lc/lcx/lhx implements the 100base-x receiving state machine diagram as given in the ansi/ieee standard 802.3u, clause 24. the 125mbit/s receive data stream may originate from the on-chip twisted-pair transceiver in a 100base-tx application. alternatively, the receive data stream may be generated by an external optical receiver as in a 100base-fx application. the receiver block consists of the following functional sub-blocks: ? a/d converter ? adaptive equalizer and timing recovery module ? nrzi/nrz and serial/parallel decoder ?de-scrambler ? symbol alignment block ? symbol decoder data sheet 25 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description ? collision detect block ? carrier sense block ? stream decoder block 3.4.1 a/d converter a high performance a/d converter with a 125 mhz sampling rate converts signals received on the rxp/rxn pins to 6 bits data streams. it possess an auto-gain-control capability that will further improve receive performance especially under long cabling or harsh detrimental signal integrity. due to high pass characteristic on a transformer, a built in base-line-wander correcting circuit will be cancelled out and its dc level restored. 3.4.2 adaptive equalizer and timing recovery module all digital design is especially immune to noise environments and achieves better correlation between production and system testing. baud rate adaptive equalizer/timing recovery compensates for line loss induced from twisted pairs and tracks a far end clock at 125m samples per second. adaptive equalizer?s implemented with feed forward and decision feedback techniques meet the requirement of ber with less than 10-12 for transmission on a cat5 twisted pair cable ranging from 0 to 120 meters. 3.4.3 nrzi/nrz and serial/parallel decoder the recovered data is converted from nrzi to nrz. the data is not necessarily aligned to the 4b/5b code group?s boundary. 3.4.4 data de-scrambling the de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering linear feedback shift register (lfsr) to the state of the scrambling lfsr. upon achieving synchronization, the incoming data is xored by the deciphering lfsr and de-scrambled. in order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data that it generates. to ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status. upon synchronization of the de-scrambler the hold timer starts a 722 micro second countdown. upon detection of sufficient idle symbols within the 722 micro sec. period, the hold timer will reset and begin a new countdown. this monitoring operation will continue indefinitely given an operating network connection operating with good signal integrity. if the link state monitor does not recognize sufficient unscrambled idle symbols within the 722 micro second period, the de-scrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. 3.4.5 symbol alignment the symbol alignment circuit in the adm6996lc/lcx/lhx determines code word alignment by recognizing the /j/k delimiter pair. this circuit operates on unaligned data from the de-scrambler. once the /j/k symbol pair (11000 10001 b ) is detected, subsequent data is aligned on a fixed boundary. 3.4.6 symbol decoding the symbol decoder functions is a look-up table that translates incoming 5b symbols into 4b nibbles as shown in table 1. the symbol decoder first detects the /j/k symbol pair preceded by idle symbols and replaces the symbol with a mac preamble. all subsequent 5b symbols are converted to the corresponding 4b nibbles for the duration of the entire packet. this conversion ceases upon the detection of the /t/r symbol pair denoting the end of stream delimiter (esd). the translated data is presented on the internal rxd[3:0] signal lines where rxd[0] represents the least significant bit of the translated nibble. samurai adm6996lc/lcx/lhx function description data sheet 26 rev. 1.31, 2005-12-05 3.4.7 valid data signal the valid data signal (rxdv) indicates that recovered and decoded nibbles are being presented on the internal rxd[3:0] synchronous receive clock, rxclk. rxdv is asserted when the first nibble of a translated /j/k is ready for transfer over the internal mii. it remains active until either the /t/r delimiter is recognized, link test indicates failure, or no signal is detected. on any of these conditions, rxdv is de-asserted. 3.4.8 receive errors the rxer signal is used to communicate receiver error conditions. while the receiver is in a state of holding rxdv asserted, the rxer will be asserted for each code word that does not map to a valid code-group. 3.4.9 100base-x link monitor the 100base-x link monitor function allows the receiver to ensure that reliable data is being received. without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected. the adm6996lc/lcx/lhx performs the link integrity test as outlined in ieee 100base-x (clause 24) link monitor state diagram. the link status is multiplexed with 10mbit/s link status to form the reportable link status bit in the serial management register 1h, and driven to the lnkact pin. when persistent signal energy is detected on the network, the logic moves into a link-ready state after approximately 500 micro secs, and waits for an enable from the auto negotiation module. when received, the link- up state is entered, and the transmission and reception logic blocks become active. should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. 3.4.10 carrier sense carrier sense (crs) for 100mbit/s operation is asserted upon the detection of two non contiguous zeros occurring within any 10-bit boundary of the received data stream. the carrier sense function is independent of symbol alignment. in switch mode, crs is asserted during either packet transmission or reception. for repeater mode, crs is asserted only during packet reception. when the idle symbol pair is detected in the received data stream, crs is de-asserted. in repeater mode, crs is only asserted due to receive activity. crs is intended to encapsulate rxdv. 3.4.11 bad ssd detection a bad start of stream delimiter (bad ssd) is an error condition that occurs in the 100base-x receiver if a carrier is detected (crs asserted) and a valid /j/k set of code-group (ssd) is not received. if this condition is detected, then the adm6996lc/lcx/lhx will assert rxer and present rxd[3:0] = 1110 b to the internal mii for the cycles that correspond to received 5b code-groups until at least two idle code-groups are detected. once at least two idle code groups are detected, rxer and crs become de-asserted. 3.4.12 far-end fault auto negotiation provides a mechanism for transferring information from the local station to the link partner that a remote fault has occurred for 100base-tx. as auto negotiation is not currently specified for operation over fiber, the far end fault indication function (fefi) provides this capability for 100base-fx applications. a remote fault is an error in the link that one station can detect while the other cannot. an example of this is a disconnected wire at a station?s transmitter. this station will be receiving valid data and detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other station. a 100base-fx station that detects such a remote fault may modify its transmitted idle stream from all 1 b ?s to a group of 84 1 b ?s followed by a single 0 b . this is referred to as the fefi idle pattern. data sheet 27 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.5 100base-tx transceiver the adm6996lc/lcx/lhx implements a tp-pmd compliant transceiver for 100base-tx operation. the differential transmit driver is shared by the 10base-t and 100base-tx subsystems. this arrangement results in one device that uses the same external magnetic for both the 10base-t and the 100base-tx transmissions with a simple rc component connection. the individually wave-shaped 10base-t and 100base-tx transmit signals are multiplexed in the transmission output driver selection. 3.5.1 transmit drivers the adm6996lc/lcx/lhx 100base-tx transmission driver implements mlt-3 translation and wave-shaping functions. the rise/fall time of the output signal is closely controlled to conform to the target range as specified in the ansi tp-pmd standard. 3.5.2 twisted-pair receiver for 100base-tx operation, the incoming signal is detected by the on-chip twisted-pair receiver that consists of a differential line receiver, an adaptive equalizer and a base-line wander compensation circuits. the adm6996lc/lcx/lhx uses an adaptive equalizer that changes filter frequency response in accordance with cable length. the cable length is estimated based on the incoming signal strength. the equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable. 3.6 10base-t module the 10base-t transceiver module is ieee 802.3 compliant. it includes the receiver, transmitter, collision, heartbeat, loop back, jabber, wave shaper, and link integrity functions, as defined in the standard. figure 3 provides an overview for the 10base-t module. the adm6996lc/lcx/lhx 10base-t module is comprised of the following functional blocks: ? manchester encoder and decoder ? collision detector ? link test function ? transmit driver and receiver ? serial and parallel interface ? jabber and sqe test functions ? polarity detection and correction 3.6.1 operation modes the adm6996lc/lcx/lhx 10base-t module is capable of operating in either half-duplex mode or full-duplex mode. in half-duplex mode, the adm6996lc/lcx/lhx functions as an ieee 802.3 compliant transceiver with fully integrated filtering. the col signal is asserted during collisions or jabber events, and the crs signal is asserted during transmit and receive. in full duplex mode the adm6996lc/lcx/lhx can simultaneously transmit and receive data. 3.6.2 manchester encoder/decoder data encoding and transmission begins when the transmission enable input (txen) goes high and continues as long as the transceiver is in a good link state. transmission ends when the transmission enable input goes low. the last transition occurs at the center of the bit cell if the last bit is a 1 b , or at the boundary of the bit cell if the last bit is 0 b . decoding is accomplished using a differential input receiver circuit and a phase-locked loop that separate the manchester-encoded data stream into clock signals and nrz data. the decoder detects the end of a frame when samurai adm6996lc/lcx/lhx function description data sheet 28 rev. 1.31, 2005-12-05 no more mid bit transitions are detected. within one and a half bit times after the last bit, carrier sense is de- asserted. 3.6.3 transmit driver and receiver the adm6996lc/lcx/lhx integrates all the required signal conditioning functions in its 10base-t block such that external filters are not required. only one isolation transformer and impedance matching resistors are needed for the 10base-t transmit and receive interface. the internal transmit filtering ensures that all the harmonics in the transmission signal are attenuated properly. 3.6.4 smart squelch the smart squelch circuit is responsible for determining when valid data is present on the differential receive. the adm6996lc/lcx/lhx implements an intelligent receive squelch on the rxp/rxn differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. the squelch circuitry employs a combination of amplitude and timing measurements (as specified in the ieee 802.3 10base-t standard) to determine the validity of data on the twisted-pair inputs. the signal at the start of the packet is checked by the analog squelch circuit and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150ns. finally, the signal must exceed the original squelch level within an additional 150ns to ensure that the input waveform will not be rejected. only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating the end of a packet. once good data has been detected, the squelch levels are reduced to minimize the effect of noise, causing premature end-of-packet detection. the receive squelch threshold level can be lowered for use in longer cable applications. this is achieved by setting bit 10 of register address 11 h . 3.7 carrier sense carrier sense (crs) is asserted due to receive activity once valid data is detected via the smart squelch function. for 10 mbit/s half duplex operation, crs is asserted during either packet transmission or reception. for 10 mbit/s full duplex and repeater mode operations, the crs is asserted only due to receive activity. 3.8 jabber function the jabber function monitors the adm6996lc/lcx/lhx output and disables the transmitter if it attempts to transmit a longer than legal sized packet. if txen is high for greater than 24ms, the 10base-t transmitter will be disabled. once disabled by the jabber function, the transmitter stays disabled for the entire time that the txen signal is asserted. this signal has to be de-asserted for approximately 256 ms (the un-jab time) before the jabber function re-enables the transmit outputs. the jabber function can be disabled by programming bit 4 of register address 10 h to high. 3.9 link test function a link pulse is used to check he integrity of the connection with the remote end. if valid link pulses are not received, the link detector disables the 10base-t twisted-pair transmitter, receiver, and collision detection functions. the link pulse generator produces pulses as defined in ieee 802.3 10base-t standard. each link pulse is nominally 100ns in duration and is transmitted every 16 ms, in the absence of transmit data. data sheet 29 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.10 automatic link polarity detection the adm6996lc/lcx/lhx?s 10base-t transceiver module incorporates an ?automatic link polarity detection circuit?. the inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive packets are received with inverted end-of-packet pulses. if the input polarity is reversed, the error condition will be automatically corrected and reported in bit 5 of register 10 h . 3.11 clock synthesizer the adm6996lc/lcx/lhx implements a clock synthesizer that generates all the reference clocks needed from a single external frequency source. the clock source must be a ttl level signal at 25 mhz +/- 50ppm 3.12 auto negotiation the auto negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signaling used to communicate auto negotiation abilities between two devices at each end of a link segment. for further detail regarding auto negotiation, refer to clause 28 of the ieee 802.3u specification. the adm6996lc/lcx/lhx supports four different ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner. highest priority is relative to the following list: ? 100base-tx full duplex (highest priority) ? 100base-tx half duplex ? 10base-t full duplex ? 10base-t half duplex (lowest priority) 3.13 memory block the adm6996lc/lcx/lhx?s built in memory is divided into two blocks. one is a mac addressing table and the other one is a data buffer. the mac address learning table size is 2k entries with each entry occupying eight bytes length. these eight bytes of data include a 6 byte source address, vlan information, port information and an aging counter. a data buffer is divided into 256 bytes/block. the adm6996lc/lcx/lhx buffer management is per port fixed block number and all ports share one global buffer. this architecture can get better memory utilization and network balance at different speeds and duplex test conditions. received packets will separate into several 256 bytes/block and chain together. if a packet size is more than 256 bytes then the adm6996lc/lcx/lhx will chain two or more blocks to store receiving packets. 3.14 switch functional description the adm6996lc/lcx/lhx uses a ?store & forward? switching approach for the following reason: ? store & forward switches allow switching between different speed media (e.g. 10basex and 100basex). such switches require large elastic buffers especially when bridging between a server on a 100 mbit/s network and clients on a 10 mbit/s segment. ? store & forward switches improve overall network performance by acting as a ?network cache? ? store & forward switches prevent the forwarding of corrupted packets by the frame check sequence (fcs) before forwarding to the destination port. 3.15 basic operation the adm6996lc/lcx/lhx receives incoming packets from one of its ports, searches in the address table for the destination mac address and then forwards the packet to the other port within the same vlan group, where samurai adm6996lc/lcx/lhx function description data sheet 30 rev. 1.31, 2005-12-05 appropriate. if the destination address is not found in the address table, the adm6996lc/lcx/lhx treats the packet as a broadcast packet and forwards the packet to the other ports within the same vlan group. the adm6996lc/lcx/lhx automatically learns the port number of attached network devices by examining the source mac address of all incoming packets at wire speed. if the source address is not found in the address table, the device adds it to the table. 3.15.1 address learning a four-way hash algorithm is implemented to allow the maximum of 4 different addresses with the same hash key to be stored at the same time. up to 2k entries can be created and all entries are stored in the internal ssram. an address is stored in the address table. the adm6996lc/lcx/lhx searches for the source address (sa) of an incoming packet in the address table and acts as below: 1. if the sa was not found in the address table (a new address), the adm6996lc/lcx/lhx waits until the end of the packet (non-error packet) and updates the address table. if the sa was found in the address table, then the aging value of each corresponding entry will be reset to 0 b . 2. when the da is pause command, then the learning process will be disabled automatically by adm6996lc/lcx/lhx. 3.15.2 address recognition and packet forwarding the adm6996lc/lcx/lhx forwards the incoming packets between bridged ports according to the destination address (da) as below. all the packet forwarded will check the vlan first. a forwarding port must be the within the same vlan as the source port. if the da is a unicast address and the address was found in the address table, the adm6996lc/lcx/lhx will check the port number and act as follows: ? if the port number is equal to the port on which the packet was received, the packet is discarded. ? if the port number is different, the packet is forwarded across the bridge. ? if the da is a unicast address and the address was not found, the adm6996lc/lcx/lhx treats it as a multicast packet and forwards it across the bridge. ? if the da is a multicast address, the packet is forwarded across the bridge. ? if the da is a pause command (01 80 c2 00 00 01 h ), then this packet will be dropped by the adm6996lc/lcx/lhx. the adm6996lc/lcx/lhx can issue and learn pause commands. ? the adm6996lc/lcx/lhx will forward the packet with a da of (01 80 c2 00 00 00 h ), filter out the packet with a da of (01 80 c2 00 00 01 h ), and forward a packet with a da of (01-80-c2-00-00-02 h to 01 80 c2 00 00 0f h ) 3.15.3 address aging address aging is supported for topology changes such as an address moving from one port to another. when this happens, the adm6996lc/lcx/lhx internally has a 300 second timer which will ?age-out? (remove) the address from the address table. the aging function can be enabled/disabled by the user. normally, disabling an aging function is for security purposes. 3.15.4 back off algorithm the adm6996lc/lcx/lhx implements the truncated exponential back off algorithm compliant to the 802.3 csma-cd standard. the adm6996lc/lcx/lhx will restart the back off algorithm by choosing 0-9 collision counts. the adm6996lc/lcx/lhx resets the collision counter after 16 consecutive retransmit trials. 3.15.5 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the typical number is 96 bits at a time. the value is 9.6 micro secs for 10 mbit/s ethernet, 960ns for 100 mbit/s fast ethernet and 96ns for 1000m. data sheet 31 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description the adm6996lc/lcx/lhx provides an option of 92 bit gap in an eeprom to prevent packet loss when flow control is turned off and clock p.p.m. values differ. 3.15.6 illegal frames the adm6996lc/lcx/lhx will discard all illegal frames such as runt packets (less than 64 bytes), oversized packets (greater than 1518 or 1522 bytes) and bad crc. dribbling packing with good crc value will be accepted by the adm6996lc/lcx/lhx. in case of bypass mode enable, the adm6996lc/lcx/lhx will support tag and untagged packets with sizes up to 1522 bytes. in case of non-bypass mode, the adm6996lc/lcx/lhx will support tag packets up to 1526bytes and untagged packets up to 1522bytes. 3.15.7 half duplex flow control a back pressure function is supported for half-duplex operations. when the adm6996lc/lcx/lhx cannot allocate a receive buffer for an incoming packet (buffer full), the device will transmit a jam pattern on the port, thus forcing a collision. back pressure is enabled by the bpen set during reset assertion. an infineon proprietary algorithm is implemented inside the adm6996lc/lcx/lhx to prevent the back pressure function causing hub partitioned under heavy traffic environment and reducing the packet loss rate to increase the whole system performance. 3.15.8 full duplex flow control when full duplex port run out of its receive buffer, a pause packet command will be issued by adm6996lc/lcx/lhx to notice the packet sender to pause transmission. this frame based flow control is totally compliant to ieee 802.3x. adm6996lc/lcx/lhx can issue or receive pause packet. 3.15.9 old broadcast storm filter (0x0b[0]=0 and 0x11[6]=0) if the broadcast storm filter is enabled, the broadcast packets over 50 ms of the threshold will be discarded by the threshold setting. see eeprom reg.10 h . broadcast storm mode: time interval: 50ms max. packet number = 7490 in 100base, 749 in 10base 3.15.10 new broadcast/multicast storm (0x0b[0]=1 and 0x11[6]=1) adm6996lc/lcx allows users to limit the traffic of the broadcast address (da = ffffffffffff h ) to prevent them from blocking the switch bandwidth. if users also want to limit the multicast packets(da[40] = 1 b ), they can table 4 the max. packet number = 7490 in 100base, 749 in 10base per port falling threshold 00 b 01 b 10 b 11 b all 100tx disable 7440fps 14880fps 29760fps not all 100tx disable 744fps 1488fps 2976fps table 5 the max. packet number = 7490 in 100base, 749 in 10base per port rising threshold 00 b 01 b 10 b 11 b all 100tx disable 14880fps 29760fps 59520fps not all 100tx disable 1488fps 2976fps 5952fps samurai adm6996lc/lcx/lhx function description data sheet 32 rev. 1.31, 2005-12-05 set the multicast packet counted into storming counter (see 0010 h [5]) function. two thresholds and storm enable bits (see 003b h and 003c h ) are used to control the broadcast storm. 1. time scale. adm6996lc/lcx uses 50ms as a scale to meter the storm packets. 2. storm keeps on at least 1.6 seconds if any of the ports meets the rising threshold in the 4 consecutive 50 ms intervals. in these 1.6 seconds, the ports meeting the rising threshold will start to discard the broadcast or multicast packets until the 50 ms interval expires. users could also disable input filter (see 000b h [14]) function to forward above packets to the un-congested port instead of discarding directly. 3. storm finishes. after the 1.6-second storm period, adm6996lc/lcx will check the port that makes the storm on. if all of these ports meet the falling threshold in the 2 consecutive 50 ms intervals and no other ports satisfy the rising threshold at the same time, the storm will finish. 3.16 auto tp mdix function at normal application which switch connect to nic card is by one by one tp cable. if switch connect other device such as another switch must by two way. first one is cross over tp cable. second way is use extra rj45 which crossover internal tx+- and rx+- signal. by second way customer can use one by one cable to connect two switch devices. all these effort need extra cost and not good solution. adm6996lc/lcx/lhx provide auto mdix function which can adjust tx+- and rx+- at correct pin. user can use one by one cable between adm6996lc/lcx/lhx and other device. this function can be enable/disable by hardware pin and eeprom configuration register 01 h ~ 09 h bit 15. if hardware pin set all port at auto mdix mode then eeprom setting is useless. if hardware pin set all port at non auto mdix mode then eeprom can set each port this function enable or disable. 3.17 port locking port locking function will provide customer simple way to limit per port user number to one. if this function is turn on then adm6996lc/lcx/lhx will lock first mac address in learning table. after this mac address locking will never age out except reset signal. another mac address which not same as locking one will be dropped. adm6996lc/lcx/lhx provide one mac address per port. this function is per port setting. when turn on port locking function, recommend customer turn off aging function. see eeprom register 12 h bit 0~8. 3.18 vlan setting & tag/untag & port-base vlan adm6996lc/lcx/lhx supports bypass mode and untagged port as default setting while the chip is power-on. thus, every packet with or without tag will be forwarded to the destination port without any modification by adm6996lc/lcx/lhx. meanwhile port-base vlan could be enabled according to the pvid value (user define 4bits to map 16 groups written at register 13 h to register 22 h ) of the configuration content of each port. adm6996lc/lcx/lhx also supports 16 802.1q vlan groups. in vlan four bytes tag include twelve vlan id. adm6996lc/lcx/lhx learn user define four bits of vid. if user need to use this function, two eeprom registers are needed to be programmed first: * port vid number at eeprom register 01 h ~ 09 h bit 13~10, register 28 h ~ 2b h and register 2c h bit 7~0: adm6996lc/lcx/lhx will check coming packet. if coming packet is non vlan packet then adm6996lc/lcx/lhx will use pvid as vlan group reference. adm6996lc/lcx/lhx will use packet?s vlan value when receive tagged packet. * vlan group mapping register. eeprom register 13 h ~ 22 h define vlan grouping value. user use these register to define vlan group. parameter rising threshold falling threshold all link ports are 100m 100m threshold (see 003b h [12:0]) 1/2 100m threshold all link ports are not all 100m 10m threshold (see 003c h [12:0]) 1/2 10m threshold data sheet 33 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description user can define each port as tag port or untag port by configuration register bit 4. the operation of packet between tag port and untag port can explain by follow example: example1: port receives untag packet and send to untag port. adm6996lc/lcx/lhx will check the port user define four bits of vlan id first then check vlan group resister. if destination port same vlan as receiving port then this packet will forward to destination port without any change. if destination port not same vlan as receiving port then this packet will be dropped. example2: port receives untag packet and send to tag port. adm6996lc/lcx/lhx will check the port user define fours bits of vlan id first then check vlan group resister. if destination port same vlan as receiving port than this packet will forward to destination port with four byte vlan tag and new crc. if destination port not same vlan as receiving port then this packet will be dropped. example3: port receives tag packet and send to untag port. adm6996lc/lcx/lhx will check the packet vlan id first then check vlan group resister. if destination port same vlan as receiving port than this packet will forward to destination port after remove four bytes with new crc error. if destination port not same vlan as receiving port then this packet will be dropped. example4: port receives tag packet and send to tag port. adm6996lc/lcx/lhx will check the user define packet vlan id first then check vlan group resister. if destination port same vlan as receiving port than this packet will forward to destination port without any change. if destination port not same vlan as receiving port then this packet will be dropped. 3.19 old fixed ingress bandwidth control (0x0b[0]=0) adm6996lc/lcx/lhx also supports adm6996l compatible bandwidth control with fixed rate. 3.20 new scalable egress/ingress bandwidth control (0x0b[0]=1 and 0x33[12]=1) bandwidth control function is useful on community networks for different levels of service. adm6996lc/lcx/lhx provides scalable egress/ingress bandwidth control. users can set any value that is based on a 64k unit. 3.21 mac table accessible cpu accesses switch internal mac table is provided by adm6996lc/lcx/lhx. cpu can search, add, delete and set adm6996lc/lcx/lhx internal mac table through a serial interface. search: cpu can search target mac address switch port number. add: cpu can add mac address to learning table. delete: cpu can delete mac address from learning table. set mac address: cpu can set mac address as static or no static address. static means not aging out. 3.22 priority setting it is a trend that data, voice and video will be put on networking, switch not only deal data packet but also provide service of multimedia data. adm6996lc/lcx/lhx provides two priority queues on each port with n:1 rate. see eeprom reg.10 h . this priority function can set three ways as below: * by port base: set specific port at specific queue. adm6996lc/lcx/lhx only check the port priority and not check packet?s content vlan and tos. table 6 fixed ingress bandwidth control 000 001 010 011 100 101 110 111 256k 512k 1m 2m 5m 10m 20m 50m samurai adm6996lc/lcx/lhx function description data sheet 34 rev. 1.31, 2005-12-05 * by vlan first: adm6996lc/lcx/lhx check vlan three priority bit first then ip tos priority bits. * by ip tos first: adm6996lc/lcx/lhx check ip tos three priority bit first then vlan three priority bits. if port set at vlan/tos priority but receiving packet without vlan or tos information then port base priority will be used. * by tcp/udp destination port number: adm6996lc/lcx/lhx check layer4 tcp/udp destination port number to map the priority queue. * by mac destination address: user can set mac address to map priority queue. 3.23 led display three leds per port are provided by adm6996lc/lcx/lhx. link/act, duplex/col. & speed are three led display of adm6996lc/lcx/lhx. dual color led mode also supported by adm6996lc/lcx/lhx. for easy production purpose adm6996lc/lcx/lhx will send test signal to each led at power on reset stage. eeprom register 12 h define led configuration table. 1. led_mode : it is the value latched on the edi pin during the power on reset. it?s also used to control the dual or single color mode and is useless when the value wait_init is high. 2. dcs (see 0012 h ): dupcol leds indicate the duplex status only. 3. dhcol (see 0030 h ): when enabled, pin dupcol0 shows col_10m status and pin dupcol1 shows col_100m status. these two leds are necessary in the dual-speed hub. adm6996lc/lcx/lhx led is active low signal. dupcol0 & dupcol1 will check external signal at reset time. if external signal add pull high then led will active low. if external signal add pull down resister then led will drive high. 3.23.1 single color led display table 7 single color led display pin name status lnkact4/lnkact3/ lnkact2/lnkact1/ lnkact0 these pins have no power on reset values on them, and adm6996lc/lcx/lhx uses active low value to drive the led. so the output values of these pins after the power on reset are shown as follows: 1. first period: this period lasts 1.28 s for led on test. adm6996lc/lcx/lhx drives value 0 to open the led. 2. second period: this period lasts 0.48 s for led off test. adm6996lc/lcx/lhx drives value 1 to close the led. 3. normal period: tis period indicates the link status. 0 b port links up and led is on. 1 b port links down and led is off. 0/1 b port links up and is transmitting or receiving. the led flashes at 10 hz. ldspd4/ldspd3/ ldspd2/ldspd1/ ldspd0 the behavior of these pins is the same as the lnkact, except the normal period. normal period: this period indicates the speed status. 0 b port links up and its speed is 100m. led is on. 1 b port links down or its speed is 10m. led is off. data sheet 35 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.23.2 dual color led display users should be careful that dupcol led only supports the single color mode. the only difference between single and dual color for dupcol led is the self-test time. dupcol2/ dupcol1/ dupcol0 these 3 pins have power on reset values on them. adm6996lc/lcx/lhx needs to consider these values to drive the correct value. if the power on reset value is value_power_on, then the display is as follows: 1. first period: this period lasts 1.28 s for led on test. adm6996lc/lcx/lhx drives ~value_power_on to open the led. 2. second period: this period lasts 0.48 s for led off test. adm6996lc/lcx/lhx drives value_power_on to close the led. 3. normal period: tis period indicates the duplex/collision status. ~value_power_on = port links up in the full-duplex mode. led is on. value_power_on = port links down. led flashes at 10 hz. 0/1 b port links up and collision is detected. the led flashes at 10 hz. if dcs is enabled, the normal period changes its way to display. ~value_power_on = port links up in the duplex mode. led is on. value_power_on = port links down or links up in the half-duplex mode. led is off. 0/1 b this value is cancelled. led doesn?t blink. if dhcol is enabled, the display in the normal period is as follows: dupcol0: 10m collision indicator. 0/1 b one of the ports links up in 10m half-duplex mode and detects a collision event. the led flashes at 20 hz. value_power_on = when the above event is not satisfied, the led is off. dupcol1: 100 m collision indicator. 0/1 b one of the ports links up in 100m half-duplex mode and detects a collision event. the led flashes at 20 hz. value_power_on = the above event is not satisfied. led is off. dupcol4/ dupcol3 the behavior of these pins is the same as the lnkact, except for the normal period. normal period: this period indicates the duplex/collision status. ~value_power_on = port links up in the full-duplex mode. led is on. value_power_on = port links down. led is off. 0/1 b port links up and collision is detected. the led flashes at 10 hz. if dcs is enabled, the normal period changes its way to display. ~value_power_on = port links up in the duplex mode. led is on. value_power_on = port links down or links up in the half-duplex mode. led is off. 0/1 b this value is cancelled. led doesn?t blink. table 7 single color led display (cont?d) pin name status samurai adm6996lc/lcx/lhx function description data sheet 36 rev. 1.31, 2005-12-05 3.23.3 circuit for single led mode figure 3 circuit for single color led mode 3.23.4 circuit for dual led mode figure 4 circuit for dual color led mode table 8 dual color led display pin name status (lnkact4, ldspd4)/ (lnkact3, ldspd3) (lnkact2, ldspd2) (lnkact1, ldspd1) (lnkact0, ldspd0) first period: test led on with green color. it lasts 1.28 s. 01 b led is on with green color. second period: test led on with yellow color. it lasts 1.28 s. 10 b led is on with yellow color. third period: test led off. 00 b led is off. normal period: this period shows the status of the link and speed at the same time. 00 b port links down.led is off. 11 b port links down. led is off. 01 b port links up in 100m. led glows green. 10 b port links up in 10m. led glows yellow. 0/1,1 b port links up in 100m and is receiving or transmitting. led blinks with green color at 10 hz. 0/1,0 b port links up in 10m and is receiving or transmitting. led blinks with yellow color at 10 hz. dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0 the behavior of these pins is the same as the single mode, except the self-test period. the led on test period is 2.56 s instead of 1.28 s. dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0/ lnkact4/lnkact3 lnkact2/lnkact1 lnkact0/ l d spd 4/ l d spd 3 l d spd 2/ l d spd 1 ldspd0/ dupcol2/dupcol1/ dupcol0 3.3v 0v l d spd 4/ l d spd 3/ l d spd 2/ l d spd 1/ ldspd0 lnkact4/lnkact3/ lnkact2/lnkact1/ lnkact0 3.3v 0v dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0 dupcol2/dupcol1/ dupcol0 data sheet 37 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.24 mac clone and port5 mii connection in adm6996lc/lcx, there are three different configurations (mac type mii mode, gpsi mode and rmii, p5_busmd0 ) for port5 to connect the cpu?s mii/gpsi or rmii interface. here we dipicted a general router applications of adm6996lc/lcx, connected to cpu with single mii. in figure 5 , we can see either lan to wan or wan to lan, the packets will go through the same mii port. because the cpu need to send out the packets with the registered mac id to the wan port, and this mac id may also come in from the lan ports. we know the switch learning scheme can?t permit the packets with same mac id input from different port. in the adm6996lc/lcx design, we use the mac clone and vlan group to solve this problem. from figure 6 , users can have more details for this implementation. figure 5 adm6996lc/lcx to cpu with single mii connection 6 port switch core cpu with single mii mii p0 phy p0 mac p1 phy p1 mac p2 phy p2 mac p3 phy p3 mac p4 phy p4 mac p5 mac lan ports wan port mac mii samurai adm6996lc/lcx/lhx function description data sheet 38 rev. 1.31, 2005-12-05 here we use an example to describe how to enable the mac clone and set the vlan group to reach this lan/wan routing activity. figure 6 mac clone enable and vlan setting step1: set adm6996lc/lcx to tag-based vlan mode -- set eeprom 0x11 h to 0xff20 h step2: set per port pvid and tag/untag output port -- port0, untag, pvid=1, set eeprom 0x01 h to 0x840f h port1, untag, pvid=1, set eeprom 0x03 h to 0x840f h port2, untag, pvid=1, set eeprom 0x05 h to 0x840f h port3, untag, pvid=1, set eeprom 0x07 h to 0x840f h port4, untag, pvid=2, set eeprom 0x08 h to 0x880f h port5, tag, pvid=2, set eeprom 0x09 h to 0x881f h step3: set wan/lan group group1: port 0/1/2/3/5, set eeprom 0x14 h to 0x0155 h group2: port 4/5, set eeprom 0x15 h to 0x0180 h if untag packet received from lan port and forwards to cpu port, adm6996lc/lcx will use ingress port pvid as the egress tag vid. cpu can recognize the source group of the packet by vid. if vid=1, it means the packet is received from the lan port. otherwise, if vid=2, it means the packet is received from the wan port. cpu has to change the tag vid to determine the destination group. the tag packet received from cpu port will follow tag-based vlan to determine the broadcast domain. if the tag packet with vid=1 will follow vlan group 1 (lan group) and the tag packet with vid=2 will follow the vlan group 2 (wan group). cpu port 5 mii, tag, pvid=2 port 0 untag pvid=1 port 1 untag pvid=1 port 2 untag pvid=1 port 3 untag pvid=1 port 4 untag pvid=2 mii lan port wan port 1) untag packet 2) tag packet with vid=1 3) cpu changes vid=1 to 2 4) tag packet with vid=2 5) untag packet data sheet 39 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description normally, the mac mode mii should be connected to the pcs mode mii. but in some applications, we need to connect both mac mode mii to each other as shown in above figures. in figure 7 , due to most cpu?s mii being mac mode, so port5 is mac to mac connected. through the hardware setting, it is easy to set adm6996lc/lcx port5 mii to operate in 100m full duplex mode. this mode (100m full) is normally the operation mode to be with cpu, the interface connection is described in the following diagram. (1) cko25m is the 25m clock driven out by adm6996lc/lcx to fit 100m mii operation. this clock output provides 8ma driving capability and it can directly connected to txclk/rxclk. (2) due to it is operated in full duplex mode, so col is tied to gnd. figure 7 100m full duplex mac to mac mii connection note: 1. pin 60 and pin 61 should be pull low to let p5_busmd be latched as ?00? and make port5 be operating in mii mode ( p5_busmd0 ). 2. pin 89 (spdtnp5) should be pull low or floating to set port5 be operating in 100mbit/s. 3. pin 91 (dphalfp5) should be pull low or floating to set port5 be operating in full duplex mode. 4. pin 90 (lnkfp5) should be pull low or floating to set port5 link up. (85) cko25m (67) txclk (72) rxclk (77) crs (73) rxdv (66) txen (102,101,100,74)rxd[3:0] (59,60,61,63)txd[3:0] (78) col (68) rxer adm6996lc/i p5 mac mode mii txclk rxclk txen crs rxdv txd[3:0] rxd[3:0] col rxer cpu mac mode mii p5_busmd0 (61) spdtnp5 (89) dphalfp5 (91) lnkfp5 (90) note p5_busmd1 (60) samurai adm6996lc/lcx/lhx function description data sheet 40 rev. 1.31, 2005-12-05 3.25 the hardware difference between adm6996lc/lcx/i and adm6996l adm6996lc/lcx is power-down version to replace adm6996l and adm6996i is advanced function version to new application. pin description(qfp128) table 9 pin description(qfp128) pin no. adm6996lc/lcx adm6996l notes 47 gndik(gnd digital) nc gndik in adm6996l datasheetask the customer to double-check 48 vccik(1.8v digital) nc vccik in adm6996l datasheetask the customer to double-check 59 p5txd3(sdio_md) p5txd3(vol23) for adm6996lc/lcx, sdio_md=0 default 32bit modefor adm6996i, sdio_md=0 default 16bit modeadd pull-up/down resistor for adm6996l/lc/i compatible design to avoid wrong power-on-latch. 60 p5txd2(rmiisel) p5txd2(romcode25 ) add pull down resistor for adm6996l/lc/i p5 mii mode to avoid wrong power-on-latch. 61 p5txd1(7wire) p5txd1(p5gpsi) add pull down resistor for adm6996l/lc/i p5 mii mode to avoid wrong power-on-latch. 65 int_n vccik(1.8v digital) interrupt for learning table access/port security/counter overflow/port statusadd a option design to cpu int_n pin data sheet 41 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description 4 32 bits mode registers description 4.1 eeprom registers (0x0b[0]=0) table 10 registers address space module base address end address note eeprom 00 h 33 h independent address space table 11 registers overview register short name register long name offset address page number sigreg signature register 00 h 43 ctrlreg_0 basic control register 0 01 h 44 resreg_0 reserved register 0 02 h 45 ctrlreg_p1 basic control register 1 03 h 45 resreg_1 reserved register 1 04 h 45 ctrlreg_p2 basic control register 2 05 h 45 resreg_2 reserved register 2 06 h 45 ctrlreg_p3 basic control register 3 07 h 45 ctrlreg_p4 basic control register 4 08 h 45 resreg_3 reserved register 3 09 h 45 resreg_4 reserved register 4 0a h 46 configreg_1 configuration register 1 0b h 46 resreg_5 reserved register 5 0c h 46 resreg_6 reserved register 6 0d h 47 vlan_map_p vlan priority map register 0e h 47 tos_priority tos priority map register 0f h 48 configreg_2 configuration register 2 10 h 48 vlan_mode vlan mode select register 11 h 49 configreg_3 miscellaneous configuration register 3 12 h 52 vlan_map_0 vlan mapping table registers 0 13 h 53 vlan_map_1 vlan mapping table registers 1 14 h 54 vlan_map_2 vlan mapping table registers 2 15 h 54 vlan_map_3 vlan mapping table registers 3 16 h 54 vlan_map_4 vlan mapping table registers 4 17 h 54 vlan_map_5 vlan mapping table registers 5 18 h 54 vlan_map_6 vlan mapping table registers 6 19 h 54 vlan_map_7 vlan mapping table registers 7 1a h 54 vlan_map_8 vlan mapping table registers 8 1b h 54 vlan_map_9 vlan mapping table registers 9 1c h 54 vlan_map_10 vlan mapping table registers 10 1d h 54 samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 42 rev. 1.31, 2005-12-05 the register is addressed wordwise. vlan_map_11 vlan mapping table registers 11 1e h 54 vlan_map_12 vlan mapping table registers 12 1f h 54 vlan_map_13 vlan mapping table registers 13 20 h 54 vlan_map_14 vlan mapping table registers 14 21 h 54 vlan_map_15 vlan mapping table registers 15 22 h 54 resreg_7 reserved register 7 23 h 54 resreg_8 reserved register 8 24 h 55 resreg_9 reserved register 9 25 h 55 resreg_10 reserved register 10 26 h 55 resreg_11 reserved register 11 27 h 55 configreg_4 configuration register 4 28 h 55 configreg_5 configuration register 5 29 h 55 configreg_6 configuration register 6 2a h 56 configreg_7 configuration register 7 2b h 56 configreg_8 configuration register 2c h 56 resreg_12 reserved register 12 2d h 57 resreg_13 reserved register 13 2e h 58 ph_restart phy restart 2f h 58 configreg_ miscellaneous configuration register 9 30 h 59 bwcon_0 bandwidth control register 0 31 h 59 bwcon_1 bandwidth control register 1 32 h 60 bwconen bandwidth control enable register 33 h 61 table 12 register access types mode symbol description hw description sw read/write rw register is used as input for the hw register is read and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latch high signal at high level, clear on read sw can read the register latch low, self clearing llsc latch high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latch high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) table 11 registers overview (cont?d) register short name register long name offset address page number data sheet 43 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description 4.1.1 eeprom register descriptions signature register description latch low, mask clearing llmk latch high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) interrupt high, self clearing ihsc differentiate the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiate the input signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiate the input signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiate the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interrupt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is read and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be cleared due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is read and writable by sw. table 13 registers clock domains clock short name description ?? sigreg offset reset value signature register 00 h 4154 h field bits type description signature 15:0 ro signature 4154 h sigreg obligatory value (at) table 12 register access types (cont?d) mode symbol description hw description sw u r 6 l j q d w x u h samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 44 rev. 1.31, 2005-12-05 note: adm6996lc/lcx/lhx will check register 0 value before read all eeprom content. if this value not match with 0x4154h then other values in eeprom will be useless. adm6996lc/lcx/lhx will use internal default value. user cannot write signature register when programming adm6996lc/lcx/lhx internal register. basic control register 0 used to configure chip settings ctrlreg_0 offset reset value basic control register 0 01 h 040f h field bits type description cam 15 rw crossover auto mdix 0 b d disable note: hardware reset latch value eesk can be set globally using the auto mdix function. 1 b e enable fse 14 rw fx select enable 0 b tp tp mode note: if this bit has been set to fx in hardware then the bit does not have the power to change from fx to tp 1 b fx fx mode pv 13 :10 rw port vlan id pp 9:8 rw port based priority ppe 7 rw port based priority enable 0 b vte vlan or tos priority enable note: this bit is default 0 b to enable vlan or tos priority check. if user would like to check the vlan priority, tag mode should be enabled. 1 b pbe port based priority enable note: if this bit is set to 1 b , only port based priority will be checked. tv 6 rw tos over vlan priority 0 b v vlan enable 1 b t tos enable pd 5 rw port disable 0 b e enable 1 b d disable ot 4 rw output packet tagging 0 b u un-tag 1 b t tag u z & |