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| - 1 - m378t2863fbs m378t5663fb3 rev. 1.0, jul. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. m391t2863fb3 datasheet m391t5663fb3 240pin unbuffered dimm based on 1gb f-die 60 & 84 fbga with lead-free & halogen-free (rohs compliant)
- 2 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm revision history revision no. history draft date remark editor 1.0 - first release. jul. 2010 - s.h.kim - 3 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm table of contents 240pin unbuffered dimm based on 1gb f-die 1. ddr2 unbuffered dimm ordering info rmation ........ .............. .............. .............. ........... ........... ........... .......................... 4 2. key features................................................................................................................ ................................................. 4 3. address configuration ....................................................................................................... ........................................... 4 4. pin configurations (front side/back side)....... ............................................................................ .................................. 5 5. x72 dimm pin configurations (front side/back side) .......................................................................... ......................... 6 6. pin description ............................................................................................................. ................................................. 6 7. input/output function description ..................... ...................................................................... ..................................... 7 8. functional block diagram : .................................................................................................. ......................................... 8 8.1 1gb, 128mx64 module - m378t2863f bs ................. .............. .............. ........... ........... ............ .......... ..................... 8 8.2 1gb, 128mx72 ecc module - m391t 2863fb3 ............... .............. .............. .............. .............. .............. ................. 9 8.3 2gb, 256mx64 module - m378t5663f b3 ............... .............. .............. .............. ........... ............ ......... ...................... 10 8.4 2gb, 256mx72 ecc module - m391t 5663fb3 ............... .............. .............. .............. .............. .............. ................. 11 9. absolute maximum dc ratings ... .............................................................................................. ................................... 12 10. ac & dc operating conditions.... .............. .............. .............. .............. .............. ............ ......... .................................... 12 10.1 recommended dc operating conditions (sstl - 1.8).... .............. .............. .............. .............. .............. ............... 12 10.2 operating temperature condition ........................................................................................... .............................. 13 10.3 input dc logic level .............. .............. .............. .............. .............. ............ ........... ......... ....................................... 13 10.4 input ac logic level ...................................................................................................... ....................................... 13 10.5 ac input test conditions........ .............. .............. .............. .............. ............ ........... ........... ..................................... 13 11. idd specification parameters definition ............. ....................................................................... ................................. 14 12. operating current table : .................................................................................................. ......................................... 15 12.1 m378t2863fbs : 1gb(128mx8 *8) module................ .............. .............. .............. .............. .............. .................... 15 12.2 m378t5663fb3 : 2gb(128mx8 *16) module ........... .............. .............. .............. ........... ........... .......... ................... 15 12.3 m391t2863fb3 : 1gb(128mx8 *9) ecc module........... .............. .............. ........... ........... ........... .......... ................ 16 12.4 m391t5663fb3 : 2gb(128mx8 *18) ecc module......... .............. .............. ........... ........... ........... ........... ............... 16 13. input/output capacitance ................................................................................................... ........................................ 17 14. electrical characteristics & ac timing for ddr2-800/ 667 ............. .............. .............. .............. ............. ..................... 17 14.1 refresh parameters by device density...................................................................................... ........................... 17 14.2 speed bins and cl, trcd, trp, trc and tras for corre sponding bin ....... .............. .............. ............ ........... ...... 17 14.3 timing parameters by speed grade ......................................................................................... ........................... 18 15. physical dimensions : ................................... ................................................................... ........................................... 20 15.1 128mbx8 based 128mx64 module (1 rank)............. ........................................................................ ..................... 20 15.2 128mbx8 based 128mx72 module (1 rank)............. ........................................................................ ..................... 21 - 4 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 1. ddr2 unbuffered dimm ordering information note : 1. ?b? of part number(11th digit) stands for lead-free, halogen-free, and rohs compliant products. 2. ?3? of part number(12th digit) stands for dummy pad pcb products. 3. ?s? of part number(12th digit) stands for reduced layer pcb products. 2. key features ? performance range e7 (ddr2-800) f7 (ddr2-800) e6 (ddr2-667) unit ? jedec standard v dd = 1.8v 0.1v power supply ?v ddq = 1.8v 0.1v ? 333mhz f ck for 667mb/sec/pin, 400mhz f ck for 800mb/sec/pin ? 8 banks ? posted cas ? programmable cas latency: 3, 4, 5, 6 ? programmable additive latency: 0, 1, 2, 3, 4, 5 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (s ingle-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination with selectabl e values(50/75 /150 ohms or disable) ? average refresh period 7.8us at lower than a t case 85 part number density organization component composition number of rank height x64 non ecc m378t2863fbs-ce7/f7/e6 1gb 128mx64 128mx8(k4t1g084qf)*8 1 30mm m378t5663fb3-ce7/f7/e6 2gb 256mx64 128mx8(k4t1g084qf)*16 2 30mm x72 ecc m391t2863fb3-ce7/f7/e6 1gb 128mx72 128mx8(k4t1g084qf)*9 1 30mm M391T5663FB3-CE7/f7/e6 2gb 256mx72 128mx8(k4t1g084qf)*18 2 30mm cas latency 5 65 tck trcd(min) 12.5 15 15 ns trp(min) 12.5 15 15 ns trc(min) 57.5 60 60 ns organization row address column address bank address auto precharge 128mx8(1gb) based module a0-a13 a0-a9 ba0-ba2 a10 - 5 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 4. pin configurations (front side/back side) note : nc = no connect, rfu = reserved for future use 1. pin196(a13) is used for x4/x8 base unbuffered dimm. 2. the test pin is reserved for bus analysis tools and is not connected on standard me mory module products (dimms.) pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5 2 v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4 dq1 124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5 v ss 125 dm0 35 v ss 155 dm3 key 95 dq42 215 dq47 6dqs 0 126 nc 36 dqs 3156 nc 65 v ss 185 ck0 96 dq43 216 v ss 7 dqs0 127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8 v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 ck2 11 v ss 131 dq12 41 v ss 161 nc 70 a10/ap 190 ba1 101 sa2 221 ck 2 12 dq8 132 dq13 42 nc 162 nc 71 ba0 191 v ddq 102 nc, test 2 222 v ss 13 dq9 133 v ss 43 nc 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6 14 v ss 134 dm1 44 v ss 164 nc 73 we 193 s 0104dqs 6 224 nc 15 dqs 1 135 nc 45 nc 165 nc 74 cas 194 v ddq 105dqs6225 v ss 16 dqs1 136 v ss 46 nc 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 ck1 47 v ss 167 nc 76 s 1 196 a13 1 107 dq50 227 dq55 18 nc 138 ck 1 48 nc 168 nc 77 odt1 197 v dd 108dq51228 v ss 19 nc 139 v ss 49 nc 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4 113 dqs 7 233 nc 24 dq16 144 dq21 54 ba2 174 nc 83 dqs 4 203 nc 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 v ddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss - 6 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 5. x72 dimm pin configuratio ns (front side/back side) note : nc = no connect, rfu = reserved for future use 1. pin196(a13) is used for x4/x8 base unbuffered dimm. 2. the test pin is reserved for bus analysis tools and is not connected on standard memory module products (dimms.) 6. pin description note : *the v dd and v ddq pins are tied to the single power-plane on pcb. pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5 2 v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4 dq1 124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5 v ss 125 dm0 35 v ss 155 dm3 key 95 dq42 215 dq47 6dqs 0 126 nc 36 dqs 3156 nc 65 v ss 185 ck0 96 dq43 216 v ss 7 dqs0 127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8 v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 ck2 11 v ss 131 dq12 41 v ss 161 cb4 70 a10/ap 190 ba1 101 sa2 221 ck 2 12 dq8 132 dq13 42 cb0 162 cb5 71 ba0 191 v ddq 102 nc, test 2 222 v ss 13 dq9 133 v ss 43 cb1 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6 14 v ss 134 dm1 44 v ss 164 dm8 73 we 193 s 0104dqs 6 224 nc 15 dqs 1 135 nc 45 dqs 8 165 nc 74 cas 194 v ddq 105dqs6225 v ss 16 dqs1 136 v ss 46 dqs8 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 ck1 47 v ss 167 cb6 76 s 1 196 a13 107 dq50 227 dq55 18 nc 138 ck 148cb2168cb777odt1197 v dd 108dq51228 v ss 19 nc 139 v ss 49 cb3 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4 113 dqs 7 233 nc 24 dq16 144 dq21 54 ba2 174 nc 83 dqs 4 203 nc 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 v ddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss pin name description pin name description a0-a13 ddr2 sdram address bus ck0, ck1, ck2 ddr2 sdra m clocks (positive line of differential pair) ba0-ba2 ddr2 sdram bank select ck 0, ck 1, ck 2 ddr2 sdram clocks (negative line of differential pair) ras ddr2 sdram row address strobe scl i 2 c serial bus clock for eeprom cas ddr2 sdram column address strobe sda i 2 c serial bus data line for eeprom we ddr2 sdram wirte enable sa0-sa2 i 2 c serial address select for eeprom s 0, s 1 dimm rank select lines v dd * ddr2 sdram core power supply cke0,cke1 ddr2 sdram clock enable lines v ddq * ddr2 sdram i/o driver power supply odt0, odt1 on-die termination control lines v ref ddr2 sdram i/o reference supply dq0 - dq63 dimm memory data bus v ss power supply return (ground) cb0 - cb7 dimm ecc check bits v ddspd serial eeprom positive power supply dqs0 - dqs8 ddr2 sdram data strobes nc spare pins(no connect) dm(0-8) ddr2 sdram data masks reset not used on udimm dqs 0-dqs 8 ddr2 sdram differential data strobes test used by memory bus analysis tools (unused on memory dimms) - 7 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 7. input/output function description ck0-ck2 0- 2 input ck and ck are differential clock inputs. all the sdram ad dr/cntl inputs are sampled on the crossing of pos - itive edge of ck and negative edge of ck . output (read) data is reference to the crossing of ck and ck (both directions of crossing) cke0-cke1 input activates the sdram ck signal when high and deactiva tes the ck signal when low. by deactivating the clocks, cke low initiates the powe down mode, or the self-refresh mode 0- 1 input enables the associated sdram command decoder when low and disables the command decoder when h igh. when the command decoder is disbled, new co mmand are ignored but previous operations continue. this signal provides for ex ternal rank selection on systems with multiple ranks , , we input , , and we (along with cs) define the command being entered. odt0-odt1 input when high, termination resi sta nce is enabled for all dq, dq and dm pins, assuming the function is enabled in the extended mode register set (emrs). v ref supply reference voltage for sstl 18 inputs. v ddq supply power supply for the ddr ii sdram output buffers to provid e improved noise i mmunity. for all current ddr2 unbuffered dimm designs, v ddq shares the same power plane as v dd pins. ba0-ba2 input selects which sdram bank of four is activated. a0-a13 input during a bank activate command cycle, addre ss input defines the row address (ra0-ra13) during a read or write command cycle, address input def ines the colum address, in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ba2 defines the bank to be precharged. if ap is low, autopre - charge is disbled. during a precharge command cycle, ap is used in conjunction with ba0-ba2 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0-ba2. if ap is low, ba0, ba1, ba2 are used to define which bank to precharge. dq0-dq63 cb0-cb7 in/out data and check bit input/output pins. dm0-dm8 input v dd ,v ss supply power and ground for ddr2 sdram input buffers, and core logic. v dd and v ddq pins are tied to v dd / v ddq planes on these modules. dqs0-dqs8 0- 8 in/out data strobe for input and output data. for rawcards using x16 o rginized dra ms dq0-7 connect to the ldqs pin of the drams and dq8-17 connect to the udqs pin of the dram sa0-sa2 input these signals and tied at the system planar to either v ss or v dd to configure the serial spd eerpom address range. sda in/out this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pullup on the system board. symbol type description ck ck s s ras cas ras cas dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is samp led on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. dqs dqs - 8 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 8. functional block diagram : 8.1 1gb, 128mx64 module - m378t2863fbs (populated as 1 rank of x8 ddr2 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm nu/ cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 note : 1. dq,dm, dqs/dqs resistors : 22 ohms r 5%. 2. bax, ax, ras , cas , we resistors : 10 ohms r 5%. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 2 ddr2 sdrams 3 ddr2 sdrams 3 ddr2 sdrams v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 v ref v ddspd serial pd a0 - a13 a0-a13 : ddr2 sdrams d0 - d7 ras ras : ddr2 sdrams d0 - d7 cas cas : ddr2 sdrams d0 - d7 we we : ddr2 sdrams d0 - d7 cke0 cke : ddr2 sdrams d0 - d7 ba0 - ba2 ba0-ba2 : ddr2 sdrams d0 - d7 odt0 odt : ddr2 sdrams d0 - d7 - 9 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 8.2 1gb, 128mx72 ecc module - m391t2863fb3 (populated as 1 rank of x8 ddr2 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 note : 1. dq,dm, dqs/dqs resistors : 22 ohms r 5%. 2. bax, ax, ras , cas , we resistors : 10 ohms r 5%. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 3 ddr2 sdrams 3 ddr2 sdrams 3 ddr2 sdrams v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v ref v ddspd serial pd dqs 8 dqs8 dm8 dm cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 a0 - a13 a0-a13 : ddr2 sdrams d0 - d8 ras ras : ddr2 sdrams d0 - d8 cas cas : ddr2 sdrams d0 - d8 we we : ddr2 sdrams d0 - d8 cke0 cke : ddr2 sdrams d0 - d8 ba0 - ba2 ba0-ba2 : ddr2 sdrams d0 - d8 odt0 odt : ddr2 sdrams d0 - d8 - 10 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 8.3 2gb, 256mx64 module - m378t5663fb3 (populated as 2 ranks of x8 ddr2 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 note : 1. dq,dm, dqs/dqs resistors : 22 ohms r 5%. 2. bax, ax, ras , cas , we resistors : 7.5 ohms r 5%. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 4 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 v ref v ddspd serial pd a0 - a13 a0-a13 : ddr2 sdrams d0 - d15 we we : ddr2 sdrams d0 - d15 cke1 cke : ddr2 sdrams d8 - d15 ba0 - ba2 ba0-ba2 : ddr2 sdrams d0 - d15 odt0 odt : ddr2 sdrams d0 - d7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 s 1 cke0 cke : ddr2 sdrams d0 - d7 ras ras : ddr2 sdrams d0 - d15 cas cas : ddr2 sdrams d0 - d15 odt1 odt : ddr2 sdrams d8 - d15 - 11 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 8.4 2gb, 256mx72 ecc module - m391t5663fb3 (populated as 2 ranks of x8 ddr2 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 note : 1. dq,dm, dqs/dqs resistors : 22 ohms r 5%. 2. bax, ax, ras , cas , we resistors : 7.5 ohms r 5%. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 6 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref v ddspd serial pd a0 - a13 a0-a13 : ddr2 sdrams d0 - d17 we we : ddr2 sdrams d0 - d17 cke1 cke : ddr2 sdrams d9 - d17 ba0 - ba2 ba0-ba2 : ddr2 sdrams d0 - d17 odt0 odt : ddr2 sdrams d0 - d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 s 1 cke0 cke : ddr2 sdrams d0 - d8 ras ras : ddr2 sdrams d0 - d17 cas cas : ddr2 sdrams d0 - d17 odt1 odt : ddr2 sdrams d9 - d17 dqs 8 dqs8 dm8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 - 12 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 9. absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions a bove those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the ce nter/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 10. ac & dc operating conditions 10.1 recommended dc operating conditions (sstl - 1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 compliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. 5. sodimms that include an optional temperature sensor may require a restricted v ddspd operating voltage range for proper operation of the temperature sensor. refer to the thermal sensor specification fo r details regarding the supported voltage range. all other functions of the sodimm spd are suppo rted across the full v ddspd range. symbol parameter rating units note v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 q c 1, 2 symbol parameter rating units note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3 - 13 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 10.2 operating temperature condition note : 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ea se refer to jesd51.2 standard. 2. at 85 - 95 note : 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. figure 1. ac input test signal waveform 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units note t oper operating temperature 0 to 95 symbol parameter min. max. units note v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter ddr2-667, ddr2-800 units min. max. v ih (ac) ac input logic high v ref + 0.200 v v il (ac) ac input logic low v ref - 0.200 v symbol condition value units note v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr - 14 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 11. idd specification parameters definition (idd values are for full operating range of voltage and temperature) symbol proposed conditions units note idd0 operating one bank active-precharge current ; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc (idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; tck = tck(idd); cke is low; other cont rol and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; other control and address bus inputs ar e switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl (idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; addr ess bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = tras- max(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current ; tck = tck(idd); refresh command at every trfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke d 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl (idd), al = trcd(idd)-1*tck(idd); tck = tck(idd), trc = trc(idd), trrd = trrd(idd), tfaw = tfaw(idd), trcd = 1*tck(idd); cke is high, cs is high between valid com- mands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the following page for detailed timing conditions ma - 15 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 12. operating current table : 12.1 m378t2863fbs : 1gb(128mx8 *8) module (t a =0 o c, v dd = 1.9v) note : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. 12.2 m378t5663fb3 : 2gb(128mx8 *16) module (t a =0 o c, v dd = 1.9v) ntoe : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol 800@cl=5 800@cl6 667@cl=5 units note ce7 cf7 ce6 idd0 360 360 344 ma idd1 408 408 384 ma idd2p 80 80 80 ma idd2q 160 160 160 ma idd2n 200 200 192 ma idd3p-f 184 184 176 ma idd3p-s 160 160 160 ma idd3n 296 296 280 ma idd4w 576 576 520 ma idd4r 640 640 560 ma idd5 840 840 800 ma idd6 80 80 80 ma idd7 1,280 1,280 1,160 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 560 560 536 ma idd1 608 608 576 ma idd2p 160 160 160 ma idd2q 320 320 320 ma idd2n 400 400 384 ma idd3p-f 368 368 352 ma idd3p-s 320 320 320 ma idd3n 496 496 472 ma idd4w 776 776 712 ma idd4r 840 840 752 ma idd5 1,040 1,040 992 ma idd6 160 160 160 ma idd7 1,480 1,480 1,352 ma - 16 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 12.3 m391t2863fb3 : 1gb(128mx8 *9) ecc module (t a =0 o c, v dd = 1.9v) ntoe : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. 12.4 m391t5663fb3 : 2gb(128mx8 *18) ecc module (t a =0 o c, v dd = 1.9v) ntoe : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 405 405 387 ma idd1 459 459 432 ma idd2p909090ma idd2q 180 180 180 ma idd2n 225 225 216 ma idd3p-f 207 207 198 ma idd3p-s 180 180 180 ma idd3n 333 333 315 ma idd4w 648 648 585 ma idd4r 720 720 630 ma idd5 945 945 900 ma idd6 90 90 90 ma idd7 1,440 1,440 1,305 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 630 630 603 ma idd1 684 684 648 ma idd2p 180 180 180 ma idd2q 360 360 360 ma idd2n 450 450 432 ma idd3p-f 414 414 396 ma idd3p-s 360 360 360 ma idd3n 558 558 531 ma idd4w 873 873 801 ma idd4r 945 945 846 ma idd5 1,170 1,170 1,116 ma idd6 180 180 180 ma idd7 1,665 1,665 1,521 ma - 17 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 13. input/output capacitance (v dd =1.8v, v ddq =1.8v, ta=25 o c ) note : dm is internally loaded to match dq and dqs identically. 14. electrical characteristics & ac timing for ddr2-800/667 (0 speed ddr2-800(e7) ddr2-800(f7) ddr2-667(e6) units bin (cl - trcd - trp) 5 - 5 - 5 6 - 6- 6 5 - 5 - 5 parameter min max min max min max tck, cl=3 5 8 - - 5 8 ns tck, cl=4 3.75 8 3.75 8 3.75 8 ns tck, cl=5 2.5 8 3 8 3 8 ns tck, cl=6 - - 2.5 8 - - ns trcd 12.5 - 15 - 15 - ns trp 12.5 - 15 - 15 - ns trc 57.5 - 60 - 60 - ns tras 45 70000 45 70000 45 70000 ns parameter symbol min max min max units non-ecc m378t2863fbs m378t5663fb3 input capacitance, ck and ck cck0 - 24 - 26 pf cck1 - 25 - 28 cck2 - 25 - 28 input capacitance, cke and cs ci1 - 42 - 42 input capacitance, addr, ras , cas , we ci2 - 42 - 42 input/output capacitance, dq, dm, dqs, dqs cio - 6 - 10 ecc m391t2863fb3 m391t5663fb3 units input capacitance, ck and ck cck0 - 25 - 28 pf cck1 - 25 - 28 cck2 - 25 - 28 input capacitance, cke and cs ci 1 - 44 - 44 input capacitance, addr, ras , cas , we ci 2 - 44 - 44 input/output capacitance, dq, dm, dqs, dqs cio - 6 - 10 parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 ? < ? - 18 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 14.3 timing parameters by speed grade (refer to notes for informations related to this table at the component datasheet) parameter symbol ddr2-800 ddr2-667 units note min max min max dq output access time from ck/ck tac -400 400 - 450 450 ps 40 dqs output access time from ck/ck tdqsck -350 350 - 400 400 ps 40 average clock high pulse width tch(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 average clock low pulse width tcl(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck half pulse period thp min(tcl(abs), tch(abs)) x min(tcl(abs), tch(abs)) x ps 37 average clock period tck(avg) 2500 8000 3000 8000 ps 35,36 dq and dm input hold time tdh(base) 125 x 175 x ps 6,7,8,21,28,31 dq and dm input setup time tds(base) 50 x 100 x ps 6,7,8,20,28,31 control & address input pulse width for each input tipw 0.6 x 0.6 x tck(avg) dq and dm input pulse width for each input tdipw 0.35 x 0.35 x tck(avg) data-out high-impedance time from ck/ck thz x tac(max) x tac(max) ps 18,40 dqs/dqs low-impedance time from ck/ck tlz(dqs) tac(min) tac(max) tac(min) tac(max) ps 18,40 dq low-impedance time from ck/ck tlz(dq) 2* tac(min) tac(max) 2* tac(min) tac(max) ps 18,40 dqs-dq skew for dqs and associated dq signals tdqsq x 200 x 240 ps 13 dq hold skew factor tqhs x 300 x 340 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x ps 39 dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 -0.25 0.25 tck(avg) 30 dqs input high pulse width tdqsh 0.35 x 0.35 x tck(avg) dqs input low pulse width tdqsl 0.35 x 0.35 x tck(avg) dqs falling edge to ck setup time tdss 0.2 x 0.2 x tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 x 0.2 x tck(avg) 30 mode register set command cycle time tmrd 2 x 2 x nck mrs command to odt update delay tmod 0 12 0 12 ns 32 write postamble twpst 0.4 0.6 0.4 0.6 tck(avg) 10 write preamble twpre 0.35 x 0.35 x tck(avg) address and control input hold time tih(base) 250 x 275 x ps 5,7,9,23,29 address and control input setup time tis(base) 175 x 200 x ps 5,7,9,22,29 read preamble trpre 0.9 1.1 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 0.4 0.6 tck(avg) 19,42 activate to activate command period for 1kb page size products trrd 7.5 x 7.5 x ns 4,32 activate to activate command period for 2kb page size products trrd 10 x 10 x ns 4,32 - 19 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm parameter symbol ddr2-800 ddr2-667 units note min max min max four activate window for 1kb page size products tfaw 35 x 37.5 x ns 32 four activate window for 2kb page size products tfaw 45 x 50 x ns 32 cas to cas command delay tccd 2 x 2 x nck write recovery time twr 15 x 15 x ns 32 auto precharge write recovery + precharge time tdal wr + tnrp x wr + tnrp x nck 33 internal write to read command delay twtr 7.5 x7.5 x ns 24,32 internal read to precharge command delay trtp 7.5 x 7.5 x ns 3,32 exit self refresh to a non-read command txsnr trfc + 10 xtrfc + 10 x ns 32 exit self refresh to a read command txsrd 200 x200 x nck exit precharge power down to any command txp 2 x 2 x nck exit active power down to read command txard 2 x 2 x nck 1 exit active power down to read command (slow exit, lower power) txards 8 - al x 7 - al x nck 1,2 cke minimum pulse width (high and low pulse width) tcke 3 x 3 x nck 27 odt turn-on delay taond 2 2 2 2 nck 16 odt turn-on taon tac(min) tac(max)+0.7 tac(min) tac(max)+0.7 ns 6,16,40 odt turn-on (power-down mode) taonpd tac(min)+2 2*tck(avg) +tac(max)+1 tac(min)+2 2*tck(avg) +tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 nck 17,45 odt turn-off taof tac(min) tac(max)+0.6 tac(min) tac(max)+0.6 ns 17,43,45 odt turn-off (power-down mode) taofpd tac(min)+2 2.5*tck(avg)+ tac(max)+1 tac(min)+2 2.5*tck(avg)+ tac(max)+1 ns odt to power down entry latency tanpd 3 x3 x nck odt power down exit latency taxpd 8 x8 x nck ocd drive mode output delay toit 0 12 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck(avg) +tih x tis+tck(avg) +tih xns15 - 20 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 15. physical dimensions : 15.1 128mbx8 based 128mx64 module (1 rank) - m378t2863fbs/m391t2863fb3 units : millimeters the used device is 128m x8 ddr2 sdram, flip-chip. ddr2 sdram part no : k4t1g084qf 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 131.35 133.35 10.00 1.270 0.10 2.7 128.95 (2) 2.50 (2x)4.00 30.00 2.30 17.80 a b 63.00 55.00 spd n/a (for x72) (for x64) ecc - 21 - datasheet ddr2 sdram rev. 1.0 unbuffered dimm 15.2 128mbx8 based 128m x72 module (1 rank) - m378t5663fb3/m391t5663fb3 units : millimeters the used device is 128m x8 ddr2 sdram, flip-chip. ddr2 sdram part no : k4t1g084qf 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 131.35 133.35 10.00 128.95 (2) 2.50 (2x)4.00 30.00 2.30 17.80 a b 63.00 55.00 spd n/a (for x72) (for x64) ecc spd n/a (for x72) (for x64) ecc |
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