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RT8108 1 ds8108-03 september 2011 www.richtek.com ordering information 5v to 12v single synchronous buck pwm controller general description the RT8108 series are single-phase synchronous buck pwm dc/dc controllers designed to drive two n-mosfets. they provide a highly accurate, programmable output voltage precisely regulated to low voltage requirement with an internal 0.6v or 0.8v reference. the RT8108 series use a single feedback loop voltage mode pwm control for fast transient response. the high driving capability makes it suitable for large output current applications. an oscillator with fixed frequency 200khz / 300khz / 500khz reduces the component size of the external inductor and capacitor for saving pcb board area and cost. the RT8108 series integrate complete protection functions such as ocp, ovp and otp uvp into sop-8 and sop-8 (exposed pad) surface mount packages. features z z z z z single ic supply voltage ( 5v to 12v) z z z z z drive two n-mosfets z z z z z fixed operating frequency at 200khz, 300khz and 500khz z z z z z voltage mode pwm control with external feedback loop compensation z z z z z over current protection by sensing mosfet r ds(on) z z z z z hardware pin for on/off control z z z z z full 0 to 90% duty cycle z z z z z fast transient response z z z z z rohs compliant and halogen free applications z mother boards and desktop servers z graphic cards z switching power supply z generic dc/dc power regulator pin configurations (top view) sop-8 boot ugate gnd lgate/ocset phase comp/sd vcc fb 2 3 4 5 6 7 8 sop-8 (exposed pad) gnd 2 3 4 5 6 7 8 9 boot ugate gnd lgate/ocset phase comp/sd vcc fb note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. RT8108 package type s : sop-8 sp : sop-8 (exposed pad-option 1) lead plating system g : green (halogen free and pb free) frequency / v ref options a : 300k / 0.6v b : 300k / 0.8v c : 200k / 0.6v d : 200k / 0.8v e : 500k / 0.6v f : 500k / 0.8v
RT8108 2 ds8108-03 september 2011 www.richtek.com pin no. pin nam e pi n function sop-8 sop-8 (exposed pad) 1 1 boot bootstrap supply pin for the upper gate driver. connect the bootstrap capacitor between boot and phase pins. 2 2 ugate upper gate driver output. connect this pin to gate of the high side power n-mosfet. 3 3, 9 (exposed pad) gnd both signal and power ground for the ic. tie this pin directly to the low-side mosfet source and ground plane with the lowest impedance. the exposed pad must be soldered to a large pcb and connected to gnd for maximum pow er dissipation. 4 4 lgate/ocset low-side gate drive. it also acts as over current setup pin by adjusting the resistor connecting to gnd. 5 5 vcc connect this pin to a well-decoupled 5v or 12v bias supply. it is also the positive supply for the lower gate driver. 6 6 fb feedback of the output voltage. 7 7 comp/sd feedback compensation and enable/shutdown control pin. 8 8 phase connect this pin to the source of the upper mosfet and the drain of the lower mosfet. functional pin description typical application circuit v o u t 2 8 4 6 v c c c o m p / s d u g a t e r t 8 1 0 8 x l g a t e / o c s e t f b 5 7 1 b o o t p h a s e l o u t v i n r s c o u t c b o o t c h f c b u l k 3 . 3 v t o 1 2 v c d c p l v c c 5 v o r 1 2 v c 1 c f r f r o f f s e t e n 3 g n d r ocset r b o o t r u g a t e r c
RT8108 3 ds8108-03 september 2011 www.richtek.com function block diagram internal regulator por and soft-start gate control logic vcc + - + - oscillator + - 0.2v 5v int. + - sample and hold ea dis dis pwm inhibit pwm comparator oc comparator i ocset d boot fixed 200khz / 300khz / 500khz boot ugate gnd lgate/ocset phase comp/sd vcc fb -1 v ref (0.6v / 0.8v) delay 5v
RT8108 4 ds8108-03 september 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max unit supply input supply input voltage v cc 4.75 -- 13.2 v supply current i cc ug at e, l g at e o p en - - 2. 5 1 0 m a shutdown current i shdn ug at e, l g at e o p en - - 2 - - m a power-on reset por threshold v cc_rth v cc rising 3.8 4 4.3 v power on reset hysteresis v cc_hys -- 0.4 -- v to be continued recommended operating conditions (note 4) z supply input voltage, v cc ------------------------------------------------------------------------------ 5v 5%, 12v 10% z junction temperature range --------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, v cc ------------------------------------------------------------------------------ 16v z boot to phase ----------------------------------------------------------------------------------------- 15v z boot to gnd dc ------------------------------------------------------------------------------------------------------------ ? 0.3v to v cc + 15v <200ns ------------------------------------------------------------------------------------------------------ ? 0.3v to 42v z phase to gnd dc ------------------------------------------------------------------------------------------------------------ ? 0.5v to 15v <200ns ------------------------------------------------------------------------------------------------------ ? 5v to 30v z ugate v oltage ------------------------------------------------------------------------------------------- v phase ? 0.3v to v boot + 0.3v <200ns ------------------------------------------------------------------------------------------------------ v phase ? 5v to v boot + 5v z lgate v oltage -------------------------------------------------------------------------------------------- gnd ? 0.3v to v cc + 0.3v <200ns ------------------------------------------------------------------------------------------------------ gnd ? 5v to v cc + 5v z other input or output voltages ------------------------------- ----------------------------------------- gnd ? 0.3v to 7v z power dissipation, p d @ t a = 25 c sop-8 ------------------------------------------------------------------------------------------------------- 0.909w sop-8 (exposed pad) ---------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) sop-8, ja ------------------------------------------------------------------------------------------------- 110 c/w sop-8 (exposed pad), ja ----------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc ---------------------------------------------------------------------------- 28 c/w z junction temperature ------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------- 200v (v cc = 12v, t a = 25 c, unless otherwise specified)
RT8108 5 ds8108-03 september 2011 www.richtek.com note 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board (4 layers, 2s2p) of jedec 51-7 thermal measurement standard. the case point of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. . parameter symbol test conditions min typ max unit oscillator RT8108a/b 250 300 350 RT8108c/d 170 200 230 pwm frequency RT8108e/f f sw 425 500 575 khz ramp amplitude v osc -- 1.5 -- v p-p reference RT8108a/c/e 0.594 0.6 0.606 reference vo lta g e RT8108b/d/f v ref 0.792 0.8 0.808 v pwm controller open loop dc gain a o -- 88 -- db gain bandwidth gbw -- 15 -- mhz f os c = 200khz / 300khz -- 92 -- % maximum duty d max f os c = 500khz -- 85 -- % pwm controller gate driver upper gate s ource i ugatesr v boot ? v ph ase = 12v 1 1.2 -- a upper gate sink r ugatesk v ugate ? v ph ase = 0.1v, i = 50ma -- 2.25 4 lower gate source i lgatesr v cc = 12v 1 1.2 -- a lower gate sink r lgatesk v lgate = 0.1v, i = 50ma -- 1 2 protection under voltage protection (uvp) v fb_uvp sweep v fb 68 75 82 % over voltage protection v fb_ovp sweep v fb (after por) 115 125 130 % over voltage protection v pre_ovp sweep v fb (before por) -- 130 -- % lgate oc setting current i ocset 22 25 28 a over temperature protect ion t otp -- 165 -- c RT8108a/b 1 3 5 RT8108c/d 1 4 7 soft-start interval RT8108e/f t ss measure fb from 10% to 90% 0.7 2.5 4 ms comp/sd shutdown threshold v sd -- -- 0.2 v
RT8108 6 ds8108-03 september 2011 www.richtek.com typical operating characteristics efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 load current (a) efficiency (%) v in = v cc = 12v reference voltage vs. temperature 0.597 0.598 0.599 0.600 0.601 0.602 0.603 0.604 0.605 -50 -25 0 25 50 75 100 125 temperature ( c) reference voltage (v) v in = v cc = 12v, no load output voltage vs. load current 1.190 1.194 1.198 1.202 1.206 1.210 0 5 10 15 20 25 load current (a) output voltage (v) v in = v cc = 12v frequency vs. temperature 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 temperature ( c) frequency (khz) 11 v in = v cc = 12v, no load power on from v in time (4ms/div) v in (10v/div) v in = v cc = 12v, no load v out (1v/div) ugate (20v/div) v cc (10v/div) power off from v in time (100ms/div) v in (10v/div) v in = v cc = 12v, no load v out (1v/div) ugate (20v/div) v cc (10v/div)
RT8108 7 ds8108-03 september 2011 www.richtek.com power on from comp/sd time (1ms/div) v out (1v/div) ugate (20v/div) v in = v cc = 12v, no load v comp (1v/div) lgate (10v/div) power off from comp/sd time (20ms/div) v in = v cc = 12v, no load v out (1v/div) ugate (20v/div) v comp (1v/div) lgate (10v/div) load transient response time (10 s/div) i load (10a/div) v out_ac (50mv/div) v in = v cc = 12v, i load = 15a to 0a l = 1uh, c out = 1640uf ugate (20v/div) load transient response time (10 s/div) i load (10a/div) v out_ac (50mv/div) v in = v cc = 12v, i load = 0a to 15a l = 1uh, c out = 1640uf ugate (20v/div) time (10ms/div) v cc = 12v, i ocset = 15a v out (1v/div) ugate (20v/div) i l (10a/div) lgate (10v/div) over current protection over voltage protection time (20ms/div) v in = v cc = 12v, no load v out (1v/div) ugate (20v/div) v fb (1v/div) lgate (10v/div)
RT8108 8 ds8108-03 september 2011 www.richtek.com application information function description the RT8108 series are single-phase synchronous buck pwm controllers with embedded mosfet drivers. the mosfet drivers are designed with high-current driving capability to support up to 12v+12v bootstrapped voltage for high efficiency power conversion. the RT8108 series utilize voltage-mode control scheme, which is implemented with a voltage error amplifier to provide a simple control loop. a fixed frequency oscillator (200khz/300khz/500khz, typical) is integrated to eliminate external component count. the soft-start function is also integrated to eliminate the external timing capacitor. the RT8108 series provide full protection functions to protect the load. the feedback voltage at the fb pin is monitored for over-voltage protection and under-voltage protection. an internal 0.6v/0.8v reference allows the output voltage to be precisely regulated for low output voltage applications. an elaborately designed control circuit allows the converter to power up with pre- biased output voltage to avoid negative voltage damage to the load. the RT8108 series use r ds(on) current-sensing technique, which is lossless and cost-effective. inductor current information is monitored by the voltage across r ds(on) of the low-side mosfet for over current protection. power-up the power on reset (por) circuit monitors the supply voltage of the controller (vcc). if vcc exceeds the por rising threshold voltage, the controller is initiated. the controller sets the over current protection threshold prior to the beginning of soft start. if vcc falls below the por falling threshold during normal operation, all mosfets stop switching and the controller is reset. the por rising and falling threshold has a hysteresis to prevent noise- caused reset. soft-start the RT8108 series provide soft-start function internally. the soft-start function is used to prevent the large inrush current while the converter is powered-up. an internal current source charges the internal soft-start capacitor such that the internal soft-start voltage ramps up in a monotone. the fb voltage will track the internal soft-start voltage during the soft-start interval. after the internal soft- start voltage exceeds the reference voltage, the fb voltage no longer tracks the soft-start voltage but follows the reference voltage. therefore, the duty cycle of thr ugate signal at power up is limited and so does the input current. power-up with pre-biased voltage generally, if the output voltage is not initially zero at power- up, or the output capacitor is pre-charged, the voltage at fb pin is not equal to zero. the controller will turn on the low-side mosfet to discharge the output capacitor, forcing the feedback voltage to follow the reference voltage. large current is then drawn from the output capacitor while discharging. the discharge current depends on the inductance and the output capacitance. output voltage may oscillate and be negative. the negative output voltage could damage the load. the RT8108 series implement elaborate control circuits to prevent the negative voltage when the converter is powered- up with pre-biased voltage on the output capacitor. figure 1 shows the waveform that converter is powered-up at no load with pre-biased output voltage. the output voltage rises from its pre-charged initial value during soft-start without being pulled down. figure 1. power up with pre-biased output voltage comp/sd enable/disable the comp/sd pin can also be used to enable or to disable the controller. pull down comp/sd pin below the shutdown level v shdn can disable the controller. when the controller is disabled, ugate signal goes low first and then lgate time (1ms/div) ugate (20v/div) v out (1v/div) lgate (10v/div) v comp (2v/div)
RT8108 9 ds8108-03 september 2011 www.richtek.com signal also goes low after a short delay time. in practical applications, connect a small signal mofset to comp/sd pin to pull down the comp/sd voltage to implement the enable/disable function. over voltage protection (ovp) the output voltage is scaled by the divider resistors and fed back to the fb pin. the voltage on the fb pin will be compared to the internal reference voltage v ref for voltage- related protection functions, including over voltage protection and under voltage protection. if the fb voltage is higher than the ovp threshold during operation, ovp will be triggered. when ovp is triggered, ugate will go low and lgate will go high to discharge the output capacitor. once ovp is triggered, controller will be latched unless vcc por is detected again. besides, the RT8108 series also provide ovp even if vcc is below the por threshold. this can protect the load even if the high-side mosfet is shorted before the power- on-reset. if the fb voltage is higher than the ovp threshold while vcc rises but not exceeds the por threshold, ovp will be triggered. the lgate signal will go high to discharge the output capacitor. under voltage protection (uvp) the voltage on the fb pin is also monitored for under voltage protection. if the fb voltage is lower than the uvp threshold during normal operation, uvp will be triggered. when uvp is triggered, both ugate and lgate go low. unlike ovp, uvp is not a latched protection. the controller will begin soft start again after a specific period of time (~40ms). furthermore, the controller will enter the hiccup mode and always try to restart if uvp situation is not removed. the uvp is reset by detecting vcc por again. unlike ovp, the output voltage is monitored for uvp only after soft- start completes. over current protection (ocp) the RT8108 series sense output current through low-side mosfet r ds(on) for over current protection. when the lgate is turned on, the controller monitors voltage across the low-side mosfet. the lossless r ds(on) current sensing technique is cost-effective, because no external component is required. the RT8108 series utilize cycle-by-cycle peak current sensing, the voltage across the low-side mosfet is sampled and held after low-side mosfet is turned on. this sampled and held voltage represents the inductor peak current and is compared to the user-programmed protection level. once the inductor current exceeds the protection level, ocp will be triggered. when the ocp is triggered, both ugate and lgate go low to stop the energy transferring to the load. like uvp, the ocp is a continuing hiccupped protection. the soft start will be initiated again after a specific period of time (4*tss, typical). if ocp situation is not removed, controller will always try to restart. ocp setting the RT8108 series employ an elaborate topology for ocp setting, which eliminates controller pin count. connect a resistor from lgate to gnd to set the ocp level as shown in figure 2. figure 2. ocp setting when the v cc exceeds the por threshold at power up, lgate is internally floating and enters tri-state. an internal current source i ocset then flows through r ocset to determine the ocp threshold voltage. the voltage across the r ocset is stored as the over current level for ocp. after that, the current source is switched off, and lgate leaves the tri-state and prepared for the soft-start. therefore, no extra pin is required to set the ocp threshold. the internal current source i oc is only active for a short period of time after v cc por. the r ocset can be determined using the following equation. ds(on) max ocset ocset ri r = 2 x i where i ocset is 25ua (typical), i max represents the allowed maximum inductor peak current. -1 sample & hold phase lgate i ocset oc r ocset 5v + - delay por
RT8108 10 ds8108-03 september 2011 www.richtek.com mosfet drivers the RT8108 series integrate high-current gate drivers for mosfets to obtain high-efficiency power conversion in synchronous buck topology. a dead time is used to prevent the crossover conduction for the high-side and low-side mosfets. because both the two gate signals are off during the dead time, the inductor current freewheels through the body diode of the low-side mosfet. the freewheeling current and the forward voltage of the body diode contribute to the power loss. the RT8108 series employ a constant dead time control scheme to ensure safe operation without sacrificing efficiency. furthermore, an elaborate logic circuit is implemented to prevent the cross-conduction between mosfets. for high output current applications, two or more power mosfets are paralleled to have reduced r ds(on) . the gate driver needs to provide more current to switch on/off these paralleled mosfets. gate driver with lower source/sink current capability results in longer rising/ falling time in gate signals, and therefore the higher switching loss. the RT8108 series employ embedded high-current gate drivers to obtain high-efficiency power conversion. the embedded drivers contribute to the majority of the controller power dissipation. if no gate resistor is used, the power dissipation of the controller can be approximately calculated using the following equation. p sw = f sw x (q g_high-side x v boot + q g_low-side x v drive_low-side ) where v boot represents the voltage across the bootstrap capacitor. it is important to ensure the package can dissipate the switching loss and have enough room for safe operation. inductor selection inductor plays an importance role in the buck converter because the energy from the input power rail is stored in it and then released to the load. from the viewpoint of efficiency, the dc resistance (dcr) of inductor should be as small as possible because inductor carries current all the time. using inductor that has lower dcr can obtain higher efficiency. in addition, because inductor cost most of the board space, its size is also important. low profile inductors can save board space especially when the height has limitation. additionally, larger inductance results in lower ripple current, and therefore the lower power loss. however, the inductor current rising time increases with inductance value. this means the inductor will have a longer charging time before its current reaches the required output current. since the response time is increased, the transient response performance will be decreased. therefore, the inductor design is a trade-off between performance, size and cost. in general, inductance is designed such that the ripple current ranges between 20% to 30% of full load current. the inductance can be calculated using the following equation. in out out min sw out_full load in vv v l = fki v ? where k is 0.2 to 0.3. input capacitor selection voltage rating and current rating are the key parameters in selecting input capacitor. the voltage rating must be 1.25 times greater than the maximum input voltage to ensure enough room for safe operation. generally, input capacitor has a voltage rating of 1.5 times greater than the maximum input voltage is a conservatively safe design. the input capacitor is used to supply the input rms current, which can be approximately calculated using the following equation. out out rms out in in vv i = i 1 vv ?? ? ?? ?? refer to the manufacturer's databook for rms current rating to select proper capacitor. use more than one capacitor with low equivalent series resistance (esr) in parallel to form a capacitor bank is popular. besides, placing ceramic capacitor close to the drain of the high-side mosfet is helpful in reducing the input voltage ripple at heavy load. output capacitor selection the output capacitor and the inductor form a low-pass filter in the buck topology. the electrolytic capacitor is usually used because it can provide large capacitance value. in steady state condition, the output capacitor supplies only ac ripple current to the load. the ripple current flows into/
RT8108 11 ds8108-03 september 2011 www.richtek.com out of the capacitor results in ripple voltage, which can be determined using the following equation. v out_esr = i l x esr in addition, the output voltage ripple is also influenced by the switching frequency and the capacitance value. out_c l out sw 1 v = i 8c f ?? the total output voltage ripple is the sum of v out_esr and v out_c . if the specification for steady-state output voltage ripple is known, the esr can be determined using the above equations. another parameter that has influence on the output voltage undershoot is the equivalent series inductance (esl). the rapid change in load current results in di/dt during transient. therefore, esl contributes to part of the voltage undershoot. use capacitor that has low esl to obtain better transient performance. generally, use several capacitors connected in parallel can have better transient performance than use single capacitor for the same total esr. unlike the electrolytic capacitor, the ceramic capacitor has relatively low esr and can reduce the voltage deviation during load transient. however, the ceramic capacitor can only provide low capacitance value. therefore, use a mixed combination of electrolytic capacitor and ceramic capacitor can also have better transient performance. feedback loop compensation figure 3 shows the voltage mode control loop for a buck converter. the control loop consists of the modulator, output lc filter and the compensator. the modulator is composed of the pwm comparator and power mosfets. the pwm comparator compares the error amplifier ea output (comp) with the oscillator (osc) sawtooth wave to generate a pwm signal. the mosfets is then switched on and off according to the duty cycle of the pwm signal. the voltage presented at phase node is a square wave of 0v to vin. the phase voltage is filtered by the output filter l out and c out to produce output voltage v out , which is fedback to the inverting input of the error amplifier. the output voltage is then regulated according to the reference voltage v ref . in order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. the goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0db crossing frequency. it is also recommended to manipulate loop frequency response that its gain crosses over 0db at a slope of ? 20db/dec. figure 3. co ntrol loop for voltage mode buck converter - + + - osc v osc z fb z in v in driver driver ref pwm comparator comp ea + - ref ea z fb z in v out fb comp c1 c2 c3 r1 r2 r3 esr phase c out v out l out 1) modulator and output lc filter referring to figure 3, the modulator gain is the input voltage v in divided by the peak to peak oscillator voltage v osc as shown as following equation : in gain osc v modulator = v where v osc = 1.5v (typ.) the output lc filter introduces a double pole to the transfer function, creating ? 40db/decade gain slope above its corner frequency, with a phase lag of 180 degrees. the frequency at the double-pole of lc filter is expressed as follows. 1 lc out out f 2l c =
RT8108 12 ds8108-03 september 2011 www.richtek.com 2) compensator fugire 4 illustrates the type ii compensator, which consists of the error amplifier and the impedance z c and z f . + - fb v ref comp ea z c z f c1 c2 r2 r1 v out r f figure 4. type ii compensator type ii compensator provides two poles and one zero to the system. the first pole is located at low frequency to increase the dc gain for regulation accuracy. the location of the other pole and the zero is expressed as follows. figure 5 shows the bode plot for the gain of system. the compensation gain determined by z c and z f should be designed to have high crossover frequency (bandwidth) with sufficient phase margin. in order to make the gain crosses over 0db at a slope of ? 20db/dec, place the zero before the lc double-pole frequency. empirically, f z1 is placed at 75% of the lc double-pole frequency. furthermore, the bandwidth of the system is the factor that affects the converter's transient performance. high bandwidth results in fast transient response, but it often jeopardizes the system stability. the bandwidth should be designed to be less than 1/5 of the switching frequency. properly adjust r1 and r2 to change the mid-frequency gain to obtain the required bandwidth. the pole at f p1 is usually placed at half of the switching frequency to have sufficient phase margin and attenuation at high frequency. z1 1 f 2r2c2 = p1 1 f c1 c2 2r2 c1 c2 = + figure 5. system gain bode plot f r e q u e n c y 1 0 h z 1 0 0 h z 1 . 0 k h z 1 0 k h z 1 0 0 k h z 1 . 0 m h z v d b ( v o ) v d b ( c o m p 2 ) v d b ( l o ) - 4 0 0 4 0 8 0 - 6 0 10 10 0 1k 10k 100k 1m 80 40 0 20 60 -20 -40 -60 loop gain compensation gain modulator gain frequency (hz) gain (db) layout considerations pcb layout is critical to high-current high-frequency switching converter designs. a good layout can help the controller to function properly and achieve expected performance. on the other hand, pcb without a carefully layout can radiate excessive noise, having more power loss and even malfunction in the controller. in order to avoid the above condition, the following general guidelines must be followed in pcb layout. ` power stage components should be placed first. place the input bulk capacitors close to the high-side power mosfets, and then locate the output inductor and finally the output capacitors. ` place the ceramic capacitor physically close to the drain of the high-side mosfet. this can reduce the input voltage drop when high-side mosfet is turned on. if more than one mosfet is paralleled, each should have its own individual ceramic capacitor. ` keep the high-current loops as short as possible. during high speed switching, the current transition between mosfets usually causes di/dt voltage spike due to the parasitic components on pcb trace. therefore, making the trace length between power mosfets and inductors wide and short can reduce the voltage spike and emi. ` make mosfet gate driver path as short as possible. since the gate driver uses narrow-width high-current pulses to switch on/off the power mosfet, the driver path must be short to reduce the trace inductance. this is especially important for low-side mosfet, because this can reduce the possibility of shoot-through. in addition, the esr of the output capacitor introduces a zero to the transfer function, creating a +20db/dec gain slope with a phase shift of 90 degree. the frequency of the esr zero is expressed as follows. 1 esr out f 2esrc =
RT8108 13 ds8108-03 september 2011 www.richtek.com ` providing enough copper area around the power mosfets to help heat dissipation. using thick copper also reduces the trace resistance and inductance to have better performance. ` the output capacitors should be placed physically close to the load. this can minimize the trace parasitic components and improve transient response. ` all small signal components should be located close to the controller. the small signal components include the feedback voltage divider resistors, compensator, function setting components and high-frequency bypass capacitors. the feedback voltage divider resistor and the compensator must be placed close to fb pin and comp pin, because these pins are inherently noise-sensitive. ` voltage feedback path must be kept away from the switching nodes. the noisy switching node is, for example, the interconnection between high-side mosfet, low-side mosfet and inductor. the feedback path must be kept away from this kind of noisy node to avoid noise pick-up. ` a multi-layer pcb design is recommended. make use of one single layer as the ground and have separate layers for power rail or signal that is suitable for pcb design. figure 6. pcb layout
RT8108 14 ds8108-03 september 2011 www.richtek.com outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050
RT8108 15 ds8108-03 september 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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