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TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 1/76 rev 0.1 tentative toshiba mos digital integr ated circuit silicon monolithic overview the rambus xdr tm dram device is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any ot her application where high bandwidth and low latency are required. the 512mb rambus xdr dram device is a cmos dram organized as 32m words by 16 bits. the use of differential rambus signaling level (drsl) technology permits 4000/3200/2400 mb/s transfer rates while using conventional system and board design technologies. xdr d ram devices are capable of su stained data transfers of 8000/6400/4800 mb/s. xdr dram device architecture allows the highest su stained bandwidth for multiple, interleaved randomly addressed memory transactions. the high ly efficient protocol yields over 95% utilization while allowing fine access granularity. the device's 8 banks support up to four interleaved transactions. features ? highest pin bandwidth available ? 4000/3200/2400 mb/s octal data rate (odr) signaling ? bi-directional differential rsl (drsl) flexible read/write bandwidth allocation minimum pin count ? programmable on-chip termination adaptive impedance matching reduced system cost and routing complexity ? highest sustained bandwidth per dram device ? 8000/6400/4800 mb/s sustained data rate ? 8 banks: bank-interleaved transactions at full bandwidth ? dynamic request scheduling ? early-read-after-write support for maximum efficiency ? zero overhead refresh ? low latency ? 2.0/2.5/3.33 ns request packets ? point-to-point data interconnect for fastest possible flight time ? support for low-latency, fast-cycle cores ? low power ? 1.8v v dd ? programmable small-swin g i/o signaling (drsl) ? low power pll/dll design ? power down self refresh support ? per pin i/o power down for narrow-width operation ? programmable i/o width ? 4 / 8 / 16 programmable device i/o width ? lead free note: xdr is a trademark or a registered trademark in japan and/or other countries. lead free
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 2/76 rev 0.1 pin assignment (top view) xdr dram csp x16 note: ? : optional ball / depopulated ? : depopulated ? rsrv: reserved pin ? dq8?dq15, dqn8?dqn15 are rsrv?s for 8 ? dq4?dq15, dqn4?dqn15 are rsrv?s for 4 key timing parameters/part numbers organization a bandwidth (1/t bit ) b latency (t rac ) c bin d part number 8 4k 1k 16 2400 36 a TC59YM916BKG24A 8 4k 1k 16 3200 27 a tc59ym916bkg32a 8 4k 1k 16 3200 35 b tc59ym916bkg32b 8 4k 1k 16 3200 35 c tc59ym916bkg32c 8 4k 1k 16 4000 28 b tc59ym916bkg40b 8 4k 1k 16 4000 28 c tc59ym916bkg40c a. bank row column width b. data rate measured in mbit/s per dq differential pair. see ?timing conditions? on page 60 and ?timing characteristics? on pa ge 62. note that t bit = t cycle / 8. c. read access time t rac ( = t rcd ? r + t cac ) measured in ns. see ?timing parameters? on page 63. d. timing parameter bin. see ?timing parameters? on page 63. this is a measure of the number of interleaved read transactions needed for maximum efficiency (the value ceiling (t rc-r /t rr-d ). for bin a, t rc ? a / t rr ? d = 4, and for bin b, t rc ? r / t rr ? d = 5 a b c d e f g h j k l 5 1 3 6 4 2 11 7 9 12 10 8 dqn3 dq3 dqn15 dq15 v dd gnd gnd v dd dqn7 dq7 dqn11 dq11 dqn9 dq9 dqn5 dq5 v dd gnd vterm gnd dqn13 dq13 dqn1 dq1 v dd v dd v dd gnd vterm gnd gnd v dd cmd sck gnd rq10 rq11 v dd gnd gnd rq9 rq8 rq4 rq3 vterm gnd v dd gnd rq1 gnd rst sdi gnd rq0 gnd v dd v dd v dd dqn0 sdo dqn8 dq8 dqn4 dq4 gnd dq12 dq6 dqn10 dq0 dqn2 dq2 dqn14 dq14 v dd gnd dqn6 dq10 vterm gnd gnd v dd 15 13 16 14 cfm rsrv cfmn rsrv v dd v dd gnd gnd v dd rq7 vref rq6 rq5 rq2 v dd gnd v dd gnd dqn12 vterm vterm gnd gnd gnd v dd v dd v dd
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 3/76 rev 0.1 general description the timing diagrams in figure 1 illust rate xdr dram device write and read transactions. there are three sets of pins used for normal memory access transactio ns: cfm/cfmn clock pins, rq11?rq0 request pins, and dq15?dq0/dqn15...dqn0 data pins. the ?n? a ppended to a signal name denotes the complementary signal of a differential pair. a transaction is a collection of packets needed to complete a memory access. a packet is a set of bit windows on the signals of a bus. there are two bu ses that carry packets: the rq bus and dq bus. each packet on the rq bus uses a set of 2 bit-windows on each signal, while the dq bus uses a set of 16 bit-windows on each signal. in the write transaction shown in figure 1, a request packet (on the rq bus) at clock edge t 0 contains an activate (act) command. this causes row ra of bank ba in the me mory component to be loaded into the sense amp array for the bank. a second request packet at clock edge t 1 contains a write (wr) command. this causes the data packet d (a1) at edge t 4 to be written to column ca1 of the sense amp array for bank ba. a third request packet at clock edge t 3 contains another write (wr) command. this causes the data packet d (a2) at edge t 6 to be also be written to column ca2. a final request packet at clock edge t 13 contains a precharge (pre) command. the spacing between the request packet s are constrained by the following timing parameters in the diagram: t rcd-w , t cc , and t wrp . in addition, the spacing betw een the request packets and data packets are constrained by the t cwrd parameter. the spacing of the cfm/cfmn clock edges is constrained by t cycle . figure 1. xdr dram device write and read transactions the read transaction shows a re quest packet at clock edge t 0 containing an act command. this causes row ra of bank ba of the memory component to load into the sense amp array for the bank. a second request packet at clock edge t 5 contains a read (rd) command. this caus es the data packet q (a1) at edge t 11 to be read from column ca1 of the sense amp array for bank ba. a third request packet at clock edge t 7 contains another rd command. this causes the data packet q (a2) at edge t 13 to also be read from column ca2. a final request packet at clock edge t 10 contains a pre command. the spacing between the request packet s are constrained by the following timing parameters in the diagram: t rcd-r , t cc , and t rdp . in addition, the spacing between the reques t and data packets is constrained by the t cac parameter. transaction a: rd a2 = = {ba, ra} a1 = = {ba} read transaction rd a1 rd a2 act a0 t rcd-r q(a1) q(a2) transaction a: wr a2 = = {ba, ra} a1 = = {ba} write transaction wr a1 wr a2 act a0 t rcd-w
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 4/76 rev 0.1 table of contents overview----------------------------------------------------------------------------------------------------------------------- -------- 1 features----------------------------------------------------------------------------------------------------------------------- --------- 1 xdr dram csp 16 pin out-------------------------------------------------------------------------------------------------- 1 key timing parameters / part numbers------------------------------------------------------------------------------------- 1 pin assignment (top view) ----------------------------------------------------------------------------------------------------- - 2 key timing parameters/part numbers----------------------------- --------------------------------------------------------- 2 related documentation---------------------------------------------------------------------------------------------------------- - 2 general description------------------------------------------------------------------------------------------------------------ ---- 3 table of contents-------------------------------------------------------------------------------------------------------------- ----- 4 lift of tables----------------------------------------------------------------------------------------------------------------- --------- 5 lift of figures---------------------------------------------------------------------------------------------------------------- --------- 6 pin description--------- ------------ ------------ ------------ ------------ ------------ ------------ ------------ ---------- --------- ------- 7 block diagram------------------------------------------------------------------------------------------------------------------ ------ 8 request packets---------------------------------------------------------------------------------------------------------------- --- 10 request packet formats------------------------------------------------------------------------------------------------------- 1 0 request field encoding-------------------------------------------------------------------------------------------------------- 12 request field interactions----------------------------------------------------------------------------------------------------- 14 request interactions cases----------------- ---------------------------------------------------------------------------------- 1 5 dynamic request scheduling------------------------------------------------------------------------------------------------ 20 memory operations-------------------------------------------------------------------------------------------------------------- 22 write transactions --------------------------------------------------------------------------------------------------------------- 22 read transactions --------------------------------------------------------------------------------------------------------------- 24 interleaved transactions------------------------------------------------------------------------------------------------------- 26 read/write interaction--------------------------------------------------------------------------------------------------------- - 28 propagation delay----------- ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ------- 30, 31 register operations------------------------------------------------------------------------------------------------------------ -- 33 serial transactions -------------------------------------------------------------------------------------------------------------- 33 serial write transaction -------------------------------------------------------------------------------------------------------- 33 serial read transaction -------------------------------------------------------------------------------------------------------- 33 register summary--------------------------------------------------------------------------------------------------------------- 35 maintenance operations---------- ---------------------------------------------------------------------------------------------- 42 refresh transactions ----------------------------------------------------------------------------------------------------------- 42 interleaved refresh transactions -------------------------------------------------------------------------------------------- 42 calibration transactions------------------------------------------------------------------------------------------------------- - 44 power state management----------------------------------------------------------------------------------------------------- 45 initialization----------------------------------------------------------------------------------------------------------------- ------- 47 xdr dram initialization overview ------------------------------------------------------------------------------------------ 49 xdr dram pattern load with wdsl register -------------------------------------------------------------------------- 50 special feature description--------------------------------------------------------------------------------------------------- 52 dynamic width control --------------------------------------------------------------------------------------------------------- 52 write masking------------------------------------------------------------------------------------------------------------------ --- 54 multiple bank sets and the eraw feature- ------------ ------------ ------------ ------------ ------------ ------------ ------ 56 simultaneous precharge------------------------------------------------------------------------------------------------------- 5 8 operating conditions-------- ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- --------- - 59 electrical conditions ------------------------------------------------------------------------------------------------------------- 59 timing conditions-------- ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- -- 60 operating characteristics------------------------------------------------------------------------------------------------------ 61 electrical characteristics ------------------------------------------------------------------------------------------------------- 61 supply current profile------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- --------- - 62 timing characteristics--------------------------------------------------------------------------------------------------------- - 62 timing parameters-------------------------------------------------------------------------------------------------------------- 63 receive/transmit timing------------------------------------------------------------------------------------------------------- 65 clocking ---------------------------------------------------------------------------------------------------------------------------- 65 rsl rq receive timing------------------------------------------------------------------------------------------------------- 66 drsl dq receive timing----------------------------------------------------------------------------------------------------- 67 drsl dq transmit timing----------------------------------------------------------------------------------------------------- 69 serial interface receive timing---------------------------------------------------------------------------------------------- 7 1 serial interface transmit timing--------------------------------- ------------------------------------------------------------ 7 2 package description---------------- ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- - 73 package parasitic summary -------------------------------------------------------------------------------------------------- 73 package mechanical drawing------- ------------ ------------ ------------ ------------ ------------ ------------ ---------- ------- 75 package pin numbering--------------------------------------------------------------------------------------------------------76
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 5/76 rev 0.1 table of tables table 1. pin descriptions----------------------------------------------------------------------------------------------------- - 7 table 2. request field description--------------------------- ------------------------------------------------------------- 10 table 3. op field encoding summary---------------------------- -------------------------------------------------------- 12 table 4. rop field encoding summary------- --------------------------------------------------------------------------- 12 table 5. pop field encoding summary------- --------------------------------------------------------------------------- 13 table 6. xop field encoding summary------- --------------------------------------------------------------------------- 13 table 7. packet interaction summary---------------------------- -------------------------------------------------------- 14 table 8. scmd field encoding summary------------------------- ------------------------------------------------------ 33 table 9. initialization timing parameters-------------------- ------------------------------------------------------------ 48 table 10. wdsl-to-core/dq/sc map (first generation 16/ 8/ 4 xdr dram, bl = 16)---------------- 50 table 11. core data word-to wdsl format ------------------------------------------------------------------------ 51 table 12. electrical conditions--------------------------------------------------------------------------------------------- 5 9 table 13. timing conditions------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------- 6 0 table 14. electrical characteristics--------------------------------------------------------------------------------------- 61 table 15. supply current profile ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------- 62 table 16. timing characteristics------------------------------------------------------------------------------------------- 62 table 17. timing parameters-------------------------------------------------------------------------------------------- 63,64 table 18. package rsl parasitic summary---------------------------------------------------------------------------- 73 table 19. csp x16 package mechanical parameters---------- ------------ ------------ ------------ ---------- -------- 75
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 6/76 rev 0.1 table of figures figure 1. xdr dram device write and read transactions-------------------------------------------------------- 3 figure 2. 512mb (8x4mx16) xdr dram bloc k diagram--------- ------------ ------------ ---------- ---------- --------- 9 figure 3. request packet formats----------------------------------------------------------------------------------------- 11 figure 4. act-, rd-, wr-, pre-to-act packet interactions------------------------------------------------------- 16 figure 5. act-, rd-, wr-, pre-to-rd packet interactions--------------------------------------------------------- 17 figure 6. act-, rd-, wr-, pre-to-wr packet interactions-------------------------------------------------------- 18 figure 7. act-, rd-, wr-, pre-to-pre packet interactions ------------- ------------ ------------ ---------- -------- 19 figure 8. request scheduling examples-------------------------------------------------------------------------------- 21 figure 9. write transactions------------------------------------------------------------------------------------------------- 23 figure 10. read transactions------------------------------------------------------------------------------------------------ 25 figure 11. interleaved transactions---------------------------- ----------------------------------------------------------- 27 figure 12. write/read interaction------------------------------------------------------------------------------------------ 29 figure 13. propagation delay------------------------------------------------------------------------------------------------ 3 2 figure 14. serial write transaction--------------------------- ------------------------------------------------------------- 34 figure 15. serial read transaction ? selected dram------ --------------------------------------------------------- 34 figure 16. serial read transaction ? non-selected dram -------------------------------------------------------- 34 figure 17. serial identification (sid) re gister-------------------------------------------------------------------------- 36 figure 18. configuration (cfg) register---------------------- ----------------------------------------------------------- 36 figure 19. power management (pm) register-------------------------------------------------------------------------- 36 figure 20. write data serial load (wdsl) control register------------------------------------------------------ 36 figure 21. rq scan high (rqh) register---------------------- ---------------------------------------------------------- 37 figure 22. rq scan low (rql) register--------------------------------------------------------------------------------- 37 figure 23. refresh bank (refb) control register-------------------------------------------------------------------- 37 figure 24. refresh high (refh) row register------------------------------------------------------------------------- 37 figure 25. refresh middle (refm) row register--------------------------------------------------------------------- 37 figure 26. refresh low (refl) row register-------------------------------------------------------------------------- 38 figure 27. io configuration (refl) register----------------- --------------------------------------------------------- 38 figure 28. current calibration 0 (cc0) register-------------- --------------------------------------------------------- 38 figure 29. current calibration 1 (cc1) register-------------- --------------------------------------------------------- 38 figure 30. impedance calibration 0 (zc0) register------------------------------------------------------------------ 38 figure 31. impedance calibration 1 (zc1) register------------------------------------------------------------------ 39 figure 32. current fuse setting 0 (fzc0) register------------------------------------------------------------------ 39 figure 33. current fuse setting 1 (fzc1) register------------------------------------------------------------------ 39 figure 34. read only memory 0 (rom0) register-------------------------------------------------------------------- 39 figure 35. read only memory 1 (rom1) register-------------------------------------------------------------------- 39 figure 36. test register------------------------------------------------------------------------------------------------------ - 40 figure 37. dll register------------------------------------------------------------------------------------------------------- - 40 figure 38. pll0 register------------------------------------------------------------------------------------------------------ 40 figure 39. pll1 register------------------------------------------------------------------------------------------------------ 40 figure 40. ift register------------------------------------------------------------------------------------------------------- -- 40 figure 41. da register-------------------------------------------------------------------------------------------------------- - 40 figure 42. partner-definable (part) register---------------- ---------------------------------------------------------- 41 figure 43. delay (dly) control register--------------------------------------------------------------------------------- 41 figure 44. refresh transactions-------------------------------------------------------------------------------------------- 43 figure 45. calibration transactions--------------------------------------------------------------------------------------- 44 figure 46. power state management-------------------------------------------------------------------------------------- 46 figure 47. serial interface systems t opology------------ ------------ ------------ ---------- ---------- ---------- ------- 47 figure 48. initialization timing for xdr dram [ k ] device-------------------------------------------------------- 47 figure 49. multiplexes for dynamic width control--------- ------------ ---------- ---------- ---------- ---------- ------ 52 figure 50. d-to-s and s-to-q mapping for dynamic width control--------------------------------------------- 53 figure 51. byte mask logic----- ------------ ------------ ------------ ------------ ------------ ------------ ------------ ---------- 54 figure 52. write-masked (wrm) transaction example-------------------------------------------------------------- 55 figure 53. write/read interaction ? no eraw feature-------------------------------------------------------------- 56 figure 54. write/read interaction ? eraw feature------------------------------------------------------------------ 56 figure 55. xdr dram block diagram with bank sets-------------------------------------------------------------- 57 figure 56. simultaneous precharge ? tpp-d cases------------------------------------------------------------------ 58 figure 57. clocking waveforms--------------------------------------------------------------------------------------------- 65 figure 58. rsl rq receive waveform------------------------------------------------------------------------------------ 66 figure 59. drsl dq receive waveform------------------------ --------------------------------------------------------- 68 figure 60. rsl dq transmit waveforms--------------------------------------------------------------------------------- 70 figure 61. serial interface receive waveforms------------------------------------------------------------------------ 71 figure 62. serial interface transmit waveforms---------------------------------------------------------------------- 72 figure 63. equivalent circuits for pa ckage parasitic------- ---------------- ------------ ------------ ---------- ------- 74 figure 64. csp x16 package mechanical drawing------------- ------------ ------------ ------------ ---------- --------- 75 figure 65. csp x16 package - pin numbering (top view) ---------------------------------------------------------- 76
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 7/76 rev 0.1 pin description table 1 summarizes the pin functionalit y of the xdr dram device. the first group of pins provide the necessary supply voltages. these include vdd and gnd for the core and interface logic, vref fo r receiving input signals, and vterm for driving output signals. the next group of pins is used for high bandw idth memory accesses. these include dq15?dq0 and dqn15...dqn0 for carrying read and writ e data signals, rq11...rq0 for carr ying request signals, and cfm and cfmn for carrying timing information used by the dq, dqn, and rq signals. the final set of pins comprises the serial interface that is used for control register ac cesses. these include rst for initializing the state of the device, cmd for carrying command signals, sdi and sdo for carrying register read data, and sck for carrying the timing information used by the rst, sdi, sdo, and cmd signals. table 1. pin descriptions signal i/o type no. of pins description v dd ? ? 22 c supply voltage for the core and interface of the device. gnd ? ? 26 a,c ground reference for the core and interface logic of the device. v ref ? ? 1 logic threshold reference voltage for rsl signals. v term ? ? 6 a termination voltage for drsl signals. dq15?dq0 i/o drsl b 16 positive data signals that carry write or read data to and from the device. dqn15?dqn0 i/o drsl b 16 negative data signals that carry write or read data to and from the device. rq11?rq0 i rsl b 12 request signals that carry control and address information to the device. cfm i diffclk b 1 clock from master ? positive interfac e clock used for receiving rsl signals, and receiving and transmitting dr sl signals from the channel. cfmn i diffclk b 1 clock from master ? negative interface clock used for receiving rsl signals, and receiving and transmitting dr sl signals from the channel. rst i rsl b 1 reset input ? this pin is used to initialize the device. cmd i rsl b 1 command input ? this pin carries co mmand, address, and control register write data into the device. sck i rsl b 1 serial clock input ? clock source us ed for reading from and writing to the control registers. sdi i rsl b 1 serial data input ? this pin carries control register read data through the device. this pin is also us ed to initialize the device. sdo o cmos b 1 serial data output ? this pin carries control register read data from the device. this pin also used to initialize the device. rsrv ? ? 2 reserved pins ? follow rambus x dr system design guidelines for connecting rsrv pins. total pin count per package 100/(108) a. j6 / j11 / c6 / c11 are optional balls. this table repres ent a superset across all the generations and densities pf xdr dram . b. all dq and cfm signals are high-true; low vo ltage is logic 0 and high voltage is logic 1. all dqn, cfmn, rq, rsl and cmos signals are low-true; high voltage is logic 0 and low voltage is logic 1. c. h1 / h16 / d1 / d16 are depopulated balls.
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 8/76 rev 0.1 block diagram a block diagram of the xdr dram device is shown in figure 2. it shows all interface pins and major internal blocks. the cfm and cfmn clock signals are received and used by the clock generation logi c to produce three virtual clock signals: 1/t cycle , 2/t cycle , and 16/t cc . the frequency of these signals ar e 1x, 2x, and 8x that of the cfm and cfmn signals. these virtual signals show the effective data rate of the lo gic blocks to which they connect; they are not necessarily present in the actual memory component. the rq11...rq0 pins receive the request packet. two 12-bit words are received in one t cycle interval. this is indicated by the 2/t cycle clocking signal connected to the 1: 2 demux block that assembles the 24-bit request packet. these 24 bits are loaded into a register (clocked by the 1/t cycle clocking signal) and decoded by the decode block. the vref pin supplies a referenc e voltage used by the rq receivers. three sets of control signals are pr oduced by the decode block. these include the bank (ba) and row (r) addresses for an activate (act) command, the bank (br) and row (refr) addresses for a precharge (pre) command, the bank (bp) address for a precharge (pre) command, the bank (br) address for a refresh precharge (refp) command, and the bank (bc) and column (c and sc) addresses for a read (rd) or write (wr or wrm) command. in addition, a mask (m) is used for a masked write (wrm) command. these commands can all be optiona lly delayed in increments of t cycle under control of delay fields in the request. the control signals of the co mmands are loaded into registers and presented to the memory core. these registers are clocked at maximum rates determined by core timing parameters, in this case 1/t rr , 1/t pp , and 1/t cc (1/4, 1/4, and 1/2 the frequency of cfm). these registers may be loaded at any t cycle rising edge. once loaded, they should not be changed until a t rr , t pp , or t cc time later because timing paths of the memory core need time to settle. a bank address is decoded for an act co mmand. the indicated row of the select ed bank is sensed and placed into the associated sense amp array for the bank. sensing a row is also referred to as ?opening a page? for the bank. another bank address is decoded for a pre command. the indicated bank and associated sense amp array are precharged to a state in which a subsequent act command can be applied. precharging a bank is also called ?closing the page? for the bank. after a bank is given an act command and before it is given a pre command, it may receive read (rd) and write (wr) column commands. these commands permit the data in the bank?s associated sense amp array to be accessed. for a wr command, the bank address is decoded. the indi cated column of the associated sense amp array of the selected bank is written with the da ta received from the dq15?dq0 pins. the bank address is decoded for a rd command. the indi cated column of the selected bank?s associated sense amp array is read. the data is tr ansmitted onto the dq15...dq0 pins. the dq15...dq0 pins receive the write da ta packet (d) for a write transaction. 16 sixteen-bit words are received in one t cc interval. this is indicated by the 16/t cc clocking signal connected to the 1:16 demux block that assembles the 16x16-bit write data packet . the write data is then driven to the selected sense amp array bank. 16 sixteen-bit words are accessed in the selected sense amp array bank for a read transaction. the dq15?0 pins transmit this read data packet (q) in one t cc interval. this is indicated by the 16/t cc clocking signal connected to the 16:1 mux block. the vterm pin supplies a termination voltage for the dq pins. the rst, sck, and cmd pins connect to the control regi ster block. these pins su pply the data, address and control needed to write the control registers. the read data for these registers is accessed through the sdo/sdi pins. these pins are also used to initialize the device. the controls registers are used to tr ansition between power modes, and are also used for calibrating the high speed transmit and receive circuits of the device. the control registers also supply bank (refb) and row (refr) addresses for refresh operations.
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 9/76 rev 0.1 figure 2. 256mb (8x2mx16) xdr dram block diagram 1:2 demux col logic refb,refr 12 reg control registers power mode logic calibration logic refresh logic initialization logic 2/t cycle 12 byte mask (wr) reg 12 1 4 rq11...rq0 vref cfmn cfm decode 12 12 act logic pre logic 7 6+4 3 rd,wr delay (0..1) * t cycle 3 pre delay (0..3) * t cycle 11 3 act delay (0..1) * t cycle 1/t cycle 1/t cycle 2/t cycle 16/t cc 1 sdo ba,br,refb r,ref r 12 decode 3 1 bank array 16x16 * 2 6 * 2 12 a ct row a ct row reg ba,br,refb 3 decode 1 pre pre 1 bank 0 bank (2 3 -1) 16x16 * 2 6 1 16x16 * 2 6 sense amp array 16x16 * 2 6 2 3 2 3 1/t rr 1/t pp decode 1 r/w r/w 1 2 3 6 col col 3 reg 1/t cc bc reg 8 4 c sc m sense amp 0 sense amp (2 3 -1) 16x16 16x16 16x16 dynamic width demux (wr) 16x16 16x16 q[15:0] [15:0] s[15:0] [15:0] width 16:1 mux 16/t cc 16 1:16 demux 16 16 16 16/t cc 16 16 2 16x16 d[15:0] [15:0] vterm dq15?dq0 dqn15?dqn0 width termination rst,sck,cmd,sdi dynamic width demux (rd)
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 10/76 rev 0.1 request packets a request packet carries address and control information to the memory device. this section contains tables and diagrams for packet formats, field encoding and packet interactions. request packet formats there are five types of request packets: 1. rowa - specifies an act command 2. col - specifies rd and wr commands 3. colm - specifies a wrm command 4. rowp - specifies pre and ref commands 5. colx - specifies the remaining commands table 2 describes fields within different request packet types. various request packet type formats are illustrated in figure 3. each packet type consists of 24 bits sampled on the rq11..rq0 pins on two successive edges of the cfm/cfmn clock. the request packet formats are distinguished by th e op3..op0 field. this field also specifies the operation code of the desired command. in the rowa packet, a bank address (ba), row address (r), and command delay (dela) are specified for the activate (act) command. in the col packet, a bank address (bc) , column address (c), sub-column address (sc), command delay (delc), and sub-opcode (wrx) are specified for th e read (rd) and write (wr) commands. in the colm packet, a bank address ( bc), column address (c), sub-column address (sc), command delay (delc), and mask field (m) are specified fo r the masked write (wrm) command. in the rowp packet, two independent commands may be specified. a bank address (b p) and sub-opcode (pop) are specified for the precharge (pre) co mmands. an address field (ra) and su b-opcode (rop) are specified for the refresh (ref) commands. in the colx packet, a sub-operation code field (xop) is specified for the remaining commands. table 2. request field description field packet types description op3..op0 rowa/rowp/co l/colm/colx 4-bit operation code that specifies packet format. (encoded commands are in a table 3 on page 12.) dela rowa delay the associated row activate command by 0 or 1 t cycle . ba2..ba0 rowa 3-bit bank address for row activate command. r10..r0 rowa 11-bit row address for row activate command. wrx col specifies rd ( = 0) or wr ( = 1) command. delc col delay the column read or write command by 0 or 1 t cycle . bc2..bc0 col/colm 3-bit bank address for column read or write command. c9..c4 col/colm 6-bit column address for column read or write command. sc3..sc0 col/colm 4-bit sub-column address for dyna mic width (see ?dynamic width control? on page 49). m7..m0 colm 8-bit mask for masked-write command wrm. pop2..pop0 rowp 3-bit operation code that specifies row precharge command with a delay of 0 to 3 t cycle . (encoded commands are in table 5 on page 13). bp2..bp0 rowp 3-bit bank address for row precharge command. rop2..rop0 rowp 3-bit operation code that specifies refresh commands. (encoded commands are in table 4 on page 12). ra7..ra0 rowp 8-bit refresh address field (specifie s br bank address, delay value, and refr load value) xop3..xop0 colx 4-bit extended operation code that specifie s column preload, calibration and power down commands. (encoded commands are in table 6 on page13).
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 11/76 rev 0.1 figure 3. request packet formats rq11 cfm cfmn t cycle op 3 del a rq10 op 2 r 8 rq9 r 9 r 7 rq8 r 10 r 6 rq7 r 11 r 5 rq6 rsrv r 4 rq5 rsrv r 3 rq4 rsrv r 2 rq3 rsrv r 1 rq2 ba 2 r 0 rq1 ba 1 rsrv rq0 ba 0 rsrv t cycle op 3 del c op 2 rsrv op 1 rsrv op 0 rsrv wr x c 7 c 8 c 6 c 9 c 5 rsrv c 4 rsrv sc 3 bc 2 sc 2 bc 1 sc 1 bc 0 sc 0 t cycle op 3 m 7 m 3 m 6 m 2 m 5 m 1 m 4 m 0 c 7 c 8 c 6 c 9 c 5 rsrv c 4 rsrv sc 3 bc 2 sc 2 bc 1 sc 1 bc 0 sc 0 t cycle op 3 pop 2 op 2 rop 2 op 1 rop 1 op 0 rop 0 pop 1 ra 7 pop 0 ra 6 rsrv ra 5 rsrv ra 4 rsrv ra 3 bp 2 ra 2 bp 1 ra 1 bp 0 ra 0 t cycle op 3 rsrv op 2 rsrv op 1 rsrv op 0 rsrv rsrv rsrv rsrv rsrv rsrv rsrv rsrv rsrv xop 3 rsrv xop 2 rsrv xop 1 rsrv xop 0 rsrv rowa packet rowp packet col packet colm packet cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 colx packet t cycle wrm a2 rd a1 act a0 pre a3 pdn
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 12/76 rev 0.1 request field encoding operation-code fields are encoded within different packet types to specify commands. table 3 through table 6 provides packet type and encoding summaries. table 3 shows the op field encoding for the five pack et types. the colm and ro wa packets each specify a single command: act and wrm. the co l, colx, and rowp packets each us e additional fields to specify multiple commands: wrx, xop, and pop/rop, respecti vely. the colm packet specifies the masked write command wrm. this is like the wr unmasked write co mmand, except that a mask field m7...m0 indicates whether each byte of the write data pa cket is written or not written. the ro wa packet specifies the row activate command act. the col packet uses the wrx field to sp ecify the column read and column write (unmasked) commands table 3. op field encoding summary op [3:0] packet command description 0000 ? nop no operation rd column read (wrx = 0). column c9?c4 of sense amp in bank bc2?bc0 is read to dq bus after delc * t cycle . 0001 col wr column write (wrx = 1). write dq bus to column c9?c4 of sense amp in bank bc2?bc0 after delc * t cycle . 0010 colx caly xop3?xop0 specifies a calibrate or power down command ? see table 6 on page 13. prex pop2?pop0 specifies a row precharge command ? see table 5 on page 13. 0011 rowp refy, lrrr rop2?rop0 specifies a row refresh command or load refr register command ? see table 4 on page 12. 01xx rowa act row activate command. row r11?r0 of bank ba2 ?ba0 is placed into the sense amp of the bank after dela * t cycle . 1xxx colm wrm column write command (masked) ? mask m7?m0 specifies which bytes are written. encoding of the rop field in the rowp packet is show n in table 4. the first encoding specifies a nopr (no operation) command. the refp command uses the ra field to select a bank to be precharged. the refa and refi commands use the ra field and refh/m/l registers to select a bank and row to be activated for refresh. the refi command also increments the refh/m/l register. the re fp, refa, and refi commands may also be delayed by up to 3*t cycle using the ra [7:6] field. the lrr0, lrr1, and lrr2 commands load the refh/m/l registers from the ra [7:0] field. table 4. rop field encoding summary rop [2:0] command description 000 nopr no operation 001 refp refresh precharge command. bank ra2?ra0 is precharged. this command is delayed by {0, 1, 2, 3} * t cycle (the value is given by the expression (2 * ra [7] + ra [6]). 010 refa refresh activate command. row r [11:0] (from refh/m /l register) of bank ra2? ra0 is placed into sense amp. this command is delayed by {0, 1, 2, 3} * t cycle (the value is given by the expression (2 * ra [7] + ra [6]). 011 refi refresh activate command. row r [11:0] (from refh/m /l register) of bank ra2? ra0 is placed into sense amp. this command is delayed by {0, 1, 2, 3} * t cycle (the value is given by the expression (2 * ra [7] + ra [6]). r[11 : 0] field of refh/m/l register is incr emented after the activate command has completed. 100 lrr0 load refresh low row register (refl). ra [7:0] is stored in r [7:0] field. 101 lrr1 load refresh middle row register (refm) . ra [3:0] is stored in r [11:8] field. 110 lrr2 load refresh high row regist er ? not used with this device 111 ? reserved
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 13/76 rev 0.1 the refh/m/l registers are also referred to as the refr regi sters. note that only the bits that are needed for specifying the refresh row (12 bits in all) are implemented in the refr register s - the rest are reserved. note also that the ra2?ra0 field that specifie s the refresh bank address is also re ferred to as br2?br0. see ?refresh transactions? on page 40. table 5 shows the pop field encoding in the rowp pack et. the first encoding specifies a nopp (no operation) command. there are four variations of pre (precharge) comma nd. each uses the bp field to specify the bank to be precharged. each also specifies a different delay of up to 3 * t cycle using the pop [1:0] fiel d. a precharge command may be specified in addition to a refresh command using the rop field. table 5. pop field encoding summary pop [2:0] command description 000 nopp no operation 001 ? reserved. 010 ? reserved. 011 ? reserved. 100 pre0 row precharge command ? bank bp2? bp0 is precharged. this command is delayed by 0*t cycle . 101 pre1 row precharge command ? bank bp2? bp0 is precharged. this command is delayed by 1*t cycle . 110 pre2 row precharge command ? bank bp2? bp0 is precharged. this command is delayed by 2*t cycle . 111 pre3 row precharge command ? bank bp2? bp0 is precharged. this command is delayed by 3*t cycle . table 6 shows the xop field encoding in the colx packet. this fiel d encodes the remaining commands. the calc and cale commands perform calib ration operations to ensure sign al integrity on the channel. see ?calibration transactions? on page 42. the pdn command causes the device to enter a power-do wn state. see ?power stat e management? on page 43. table 6. xop field encoding summary xop [3:0] command command and description xop [3:0] command command and description 0000 ? reserved 1000 calc current calibration command. 0001 ? reserved. 1001 calz impedance calibration command. 0010 ? reserved. 1010 cale end calibration command (calc). 0011 ? reserved. 1011 ? reserved. 0100 ? reserved. 1100 pdn enter power down power state. 0101 ? reserved. 1101 ? reserved 0110 ? reserved 1110 ? reserved 0111 ? reserved 1111 ? reserved.
TC59YM916BKG24A,32a,32b,40b,32c,40c 2004-12-15 14/76 rev 0.1 request field interactions a summary of request packet interactions is shown in table 7. each case is limited to request packets with commands that perform memory operations (including re fresh commands). this includ es all commands in rowa, rowp, col, and colm packets. the commands in colx packets are described in later sections. see ?maintenance operations? on page 40. request packet/command ?a? is followed by request pack et/command ?b?. the minimum possible spacing between these two packet/commands is 0 * t cycle . however, a larger time interval may be needed because of a resource interaction between the two packet/commands. if the minimum possible spacing is 0 * t cycle , then an entry of ?no limit? is shown in the table. note that the spacing values shown in the table are relative to the effective beginning of a packet/command. the use of the delay field with a command will delay the position of the effective packet/command from the position of the actual packet/command. see ?dynam ic request scheduling? on page 20. any of the packet/command encoding under one of the four operation types is equivalent in terms of the resource constraints. therefore, both the horizo ntal columns (packet ?a?) and vertical rows (packet ?b?) of the interaction table are divided into four major groups. the four possible operation types fo r request packets a and b include: : [a] activate row ? rowa/act ? rowp/refa ? rowp/refi ; [r] read column ? col/rd ; [w] write column ? col/wr ? colm/wrm ; [p] precharge row ? rowp/pre ? rowp/refp table 7. packet interaction summary second packet/command to bank bb first packet command to bank ba activate row [a] rowa ? act bb rowp ? refa bb rowp ? refi ba read column [r] col ? rd bb write column [w] col ? wr bb colm ? wrm bb precharge row[p] rowp ? pre bb rowp ? refp bb ba,bb different case aad: t rr case ard: no limit case awd: no limit case apd: no limit activate row [a] rowa ? act ba rowp ? refa ba rowp ? refi ba ba,bb same case aas: t rc case ars: t rcd-r case aws: t rcd-w case aps: t ras ba,bb different case rad: no limit case rrd: t cc case rwd a : t ? rw case rpd: no limit read column [r] col ? rd ba ba,bb same case ras b : t rdp +t rp case rrs: t cc case rws a : t ? rw case rrs: t rdp ba,bb different case wad: no limit case wrd c : t ? wr case wwd: t cc case wpd: no limit write column [w] col ? wr ba colm ? wrm ba ba,bb same case was b : t wrp +t rp case wrs c : t ? wr case wws: t cc case wps: t wrp ba,bb different case pad: no limit case prd: no limit case pwd: no limit case ppd: t pp precharge row [p] rowp ? pre ba rowp ? refp ba ba,bb same case pas: t rp case prs d : t rp +t rcd-r case pws d : t rp +t rcd-w case pps: t rc see examples: figure 4 fi gure 5 figure 6 figure 7 a. t ? rw is equal to t cc + t rw ? bub,xdr dram + t cac ? t cwd and is defined in table 17. this also depends upon propagation delay ? see ?propagation delay? on page 30. b. a pre command is needed between the rd and act/refa commands or the wr/wrm and act/refa commands. c. t ? wr is defined in table 17. d. an act command is needed between the pre/refp and rd commands or the pre/refp and wr/wrm commands.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 15/76 rev 0.1 the first request is shown along the vert ical axis on the left of the table. the second request is shown along the horizontal axis at the top of the table. each request includes a bank specification ?ba? and ?bb?. the first and second banks may be the same, or they may be different. these two sub cases for each interaction are shown along the vertical axis on the left. there are 32 possible interaction cases al together. the table gives each case a label of the form ?xyz?, where ?x? and ?y? are one of the four operation ty pes (?a? for activate, ?r? for read, ?w? for write, or ?p? for precharge) for the first and second request, respectively, and ?z? in dicates the same bank (?s? ) or different bank (?d?). along the horizontal axis at the bottom of the table are cr oss-references to four figures (figure 4 through figure 7). each figure illustrates the eight ca ses in the corresponding vertical co lumn. thus, figure 4 shows the eight cases when the second request is an acti vate operation (?a?). in the following di scussion of the cases, only those in which the interaction interval is greater than t cycle will be described. request interactions cases in figure 4, the interaction interval for the aad case is t rr . this parameter is the row-to-row time and is the minimum interval between activate comma nds to different banks of a device. the interaction interval for the aas case is t rc . this is the row cycle time parameter and is the minimum interval between activate commands to same banks of a de vice. a precharge operation must be inserted between the two activate operations. the interaction interval for the ras case is t wrp + t rp . a precharge operation must be inserted between the read and activate operation. the minimum interval between a read and a precharge operation to a bank is t rdp . the minimum interval between a precharge and an activate operation to a bank is t rp . the interaction interval for the was case is t wrp + t rp . a precharge operation must be inserted between the read and the activate operation. the minimum interval between a write and a precharge operation to a bank is t wrp . the minimum interval between a precharge and an activate operation to a bank is t rp . the interaction interval for the pas case is t rp . the minimum interval between a precharge and an activate operation to a bank is t rp . in figure 5, the interaction interval for the ars case is t rcd-r . this is the row-to-column-read time parameter and represents the minimum interval between an activate operation and a read operation to a bank. the interaction interval for the rrd and rrs cases is t cc . this is the column-to-co lumn time parameter and represents the minimum interval between two read operations. the interaction interval for the wrd and wrs cases is t ? wr . this is the write-to-read time parameter and represents the minimum interval between a write and a read operation to any banks. see ?read/write interaction? on page 28. the interaction interval for the prs case is t rp + t rcd-r . an activate operation must be inserted between the precharge and the read operation. the minimum interval between a precharge and an activate operation to a bank is t rp . the minimum interval between an activate and read operation to a bank is t rcd-r . in figure 6, the interaction interval for the aws case is t rcd-w . this is the row-to-column-write timing parameter and represents the minimum interval between an activate operation and a write operation to a bank. the interaction interval for the rwd and rws cases is t ? rw . this is the read-to-write time parameter and represents the minimum interval between a read and a write operation to any banks. see ?read/write interaction? on page 28. the interaction interval for the wwd and wws cases is t cc . this is the column-to-column time parameter and represents the minimum interval between two write operations. the interaction interval for the pws case is t rp + t rcd-w . an activate operation must be inserted between the precharge and the write operation. the minimum interval between a precharge and an activate operation to a bank is t rp . the minimum interval between an activate and a write operation to a bank is t rcd-w . in figure 7, the interaction interval for the aps case is t ras . this parameter is the minimum activate ? to - precharge time to a bank. the interaction intervals for the rps and wps cases are t rdp and t wrd , respectively. these are the read- or write-to-precharge time parameters to a bank. the interaction interval for the ppd case is t pp . this parameter is the precharge-to-precharge time and the minimum interval between precharge commands to different banks of a device. the interaction interval for the pps case is t rc . this is the row cycle time parameter and the minimum interval between precharge commands to same banks of a device. an activate operation must be inserted between the two activate operations. this activate operation must be placed a time t rp after the first, and a time t ras before the second precharge.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 16/76 rev 0.1 figure 4. act-, rd-, wr-, pr e-to-act packet interactions a: rowa packet with act,ba,ra ba bb aad case (activate-activate-different bank) b: rowa packet with act,bb,rb a: rowa packet with act,ba,ra ba = bb a as case (activate-activate-same bank) b: rowa packet with act,bb,rb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rp t ras t rc act b act b act a act a t rr pre a a: col packet with rd, ba,ra ba bb rad case (read-activate-different bank) b: rowa packet with act,bb,rb a: col packet with rd,ba,ra ba = bb ras case (read-activate-same bank) b: rowa packet with act,bb,rb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rp t rdp t rdp + t rp act b act b rd a rd a no limit pre a a: rowp packet with pre, ba ba bb pad case (precharge-activate-different bank) b: rowa packet with act,bb,rb a: rowp packet with pre,ba ba = bb pas case (precharge-activate-same bank) b: rowa packet with act,bb,rb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rp act b act b pre a no limit pre a t 5 a: col packet with wr, ba,ra ba bb wad case (write-activate-different bank) b: rowa packet with act,bb,rb a: col packet with wr,ba,ra ba = bb was case (write-activate-same bank) b: rowa packet with act,bb,rb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rp t wrp t wrp + t rp act b act b wr a wr a no limit pre a t 5
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 17/76 rev 0.1 figure 5. act-, rd-, wr-, pre-to-rd packet interactions a: rowa packet with act,ba,ra ba bb ard case (activate-read different bank) b: col packet with rd,bb,cb a: rowa packet with act,ba,ra ba = bb a rs case (activate-read same bank) b: col packet with rd,bb,cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rcd-r rd b rd b act a no limit act a a: col packet with rd, ba, ca ba bb rrd case (read-read different bank) b: col packet with rd, bb, cb a: col packet with rd, ba, ca ba = bb rrs case (read-read same bank) b: col packet with rd, bb, cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cc rd b rd b rd a rd a t cc a: col packet with wr, ba, ca ba bb wrd case (write-read different bank) b: col packet with rd, bb, cb a: col packet with wr, ba, ca ba = bb wrs case (write-read same bank) b: col packet with rd, bb, cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t ? wr rd b rd b wr a t ? wr t 5 wr a a: rowp packet with pre, ba ba bb prd case (precharge-read dif f erent bank) b: col packet with rd, bb, cb a: rowp packet with pre, ba ba = bb prs case (precharge-read same bank) b: col packet with rd, bb, cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rp + t rcd-r rd b pre a no limit t 5 pre a rd b act b t rp t rcd-r
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 18/76 rev 0.1 figure 6. act-, rd-, wr-, pre-to-wr packet interactions a: rowa packet with act, ba, ra ba bb awd case (activate-write different bank) b: col packet with wr, bb,cb a: rowa packet with act, ba, ra ba = bb a ws case (activate-write same bank) b: col packet with wr, bb, cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 wr b wr b act a act a no limit t rcd-w a: col packet with wr, ba, ca ba bb wwd case (write-write different bank) b: col packet with wr,bb,cb a: cop packet with wr,ba, ca ba = bb wws case (write-write same bank) b: col packet with wr, bb, cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cc wr b wr a t cc wr a t 5 wr b a: rowp packet with prr, ba ba bb pwd case (precharge-write different bank) b: col packet with wr, bb,cb a: rowp packet with pre, ba ba = bb pws case (precharge-write same bank) b: cop packet with wr, bb, cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rp + t rcd-w pre a no limit t 5 wr b pre a t rp t rcd-w wr b act b a: col packet with rd, ba,ra ba bb rwd case (read-write different bank) b: col packet with wr, bb, cb a: col packet with rd, ba, ca ba = bb rws case (read-activate same bank) b: col packet with wr, bb, cb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t ? ? rw rd a t cwd t cycle t cac q (a) d (b) t cac t cwd t cycle q (a) d (b)
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 19/76 rev 0.1 figure 7. act-, rd-, wr-, pre-to-pre packet interactions a: rowa packet with act, ba, ra ba bb apd case (activate-precharge different bank) b: rowp packet with pre, bb a: rowa packet with act, ba, ra ba = bb a ps case (activate-precharge same bank) b: rowp packet with prr, bb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t ras pre b pre b act a no limit act a a: col packet with rd, ba, ca ba bb rpd case (read-precharge different bank) b: rowp packet with pre, bb a: col packet with rd, ba, ca ba = bb rps case (read-precharge same bank) b: rowp packet with prr, bb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rdp pre b pre b rd a rd a no limit a: rowp packet with pre, ba ba bb ppd case (precharge-precharge different bank) b: rowp packet with pre, bb a: rowp packet with pre, ba ba = bb pps case (precharge-precharge same bank) b: rowp packet with pre, bb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rc pre b pre a t pp t 5 pre a pre b t rp t ras act b a: col packet with wr, ba, ca ba bb wpd case (write-precharge different bank) b: rowp packet with pre, bb a: col packet with wr, ba, ca ba = bb wps case (write-precharge same bank) b: rowp packet with pre, bb cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t wrp pre b wr a no limit t 5 wr a pre b
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 20/76 rev 0.1 dynamic request scheduling delay fields are present in the ro wa, col, and rowp packets. they permit the associated command to optionally wait for a time of one (or more) t cycle before taking effect. this allows a memory controller more scheduling flexibility when issuing request packets. figure 8 illustra tes the use of the delay fields. in the first timing diagram, a rowa packet with an act command is present at cycle t 0 . the dela field is set to ?1?. this request packet will be equivalent to a rowa packet with an act command at cycle t 1 with the dela field is set to ?0?. this equivalence should be used when analyzing requ est packet interactions. in the second timing diagram, a col packet with a rd command is present at cycle t 0 . the delc field is set to ?1?. this request packet will be equivalent to a col packet with an rd command at cycle t 1 with the delc field is set to ?0?. this equivalence should be used when analyzing request packet interactions. in a similar fashion, a col packet with a wr command is present at cycle t 12 . the delc field is set to ?1?. this request packet will be equivalent to a co l packet with a wr command at cycle t 13 with the delc field is set to ?0?. this equivalence should be used wh en analyzing request packet interactions. in the col packet with a rd command example, the read data delay. t cac is measured between the q read data packet and the virtual col packet at cycle t 1 . likewise, for the example with the col packet with a wr command, the write data delay. t cwd is measured between the d write data packet and the virtual col packet at cycle t 13 . in the third timing diagram, a rowp packet with a pre command is present at cycle t 0 . the del field (pop [1:0]) is set to ?11?. this request pa cket will be equivalent to a rowp pa cket with a pre command at cycle t 1 with the del field is set to ?10?, it will be equivalent to a rowp packet with a pre command at cycle t 2 with the del field is set to ?01?, and it will be equivalent to a rowp packet with a pre command at cycle t 3 with the del field is set to ?00?. this equivalence should be us ed when analyzing reques t packet interactions. in the fourth timing diagram, a rowp packet with a refp command is present at cycle t 0 . the del field (ra [7:6]) is set to ?11?. this request pa cket will be equivalent to a rowp pa cket with a refp command at cycle t 1 with the del field is set to ?10?, it will be equivale nt to a rowp packet with a refp command at cycle t 2 with the del field is set to ?01?, and it will be equivalent to a rowp packet with a refp command at cycle t 3 with the del field is set to ?00?. this equi valence should be used when anal yzing request packet interactions. the two examples for the refa and refi commands are id entical to the example just described for the refp command. the rowp packet allows two independent operations to be specified. a pre precharge command uses the pop and bp fields, and the refp, refa, or refi commands us es the rop and ra fields. both operations have an optional delay field (the pop field for the pre co mmand and the ra field with the refp, refa, or refi commands). the two delay mechanisms are independent of one another. the pop field does not affect the timing of the refp, refa, or refi commands, and the ra field does not affect the timing of the pre command. when the interactions of a rowp packet are analyzed, it must be remembered that there are two independent commands specified, both of which may affect how soon the next request packet can be issued. the constraints from both commands in a rowp packet must be considered, and the one that requires the lo nger time interval to the next request packet must be used by the memory co ntroller. furthermore, the two commands within a rowp packet may not reference the same bank in the bp and ra fields.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 21/76 rev 0.1 figure 8. request scheduling examples rowa/act c omman d cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle act del0 act del1 note: del value is specified by dela field. a ct w/del=1 at t 0 is equivalent to act w/del=0 at t 1 . col/rd an d col/wract c omman d s cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle rd del1 note: del value is specified by del a field. wr del1 wr del1 rd del0 rd w/del=1 at t 0 is equivalent to rd w/del=0 at t 1 . q d t cac t cwd wrm w/del=1 at t 12 is equivalent to wrm w/del=0 at t 13 . note: del value is specified by {pop1, pop0} field. rowp/p re c omman d cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle pre del3 pre del2 pre w/del=3 at t 0 is equivalent to pre w/del=2 a t t 1 or pre w/del=1 at t 2 or refp w/del=0 at t 3 . pre del1 pre del0 cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 refp del3 note: del value is specified by {ra7, ra6} field. rowp/refp , refa , refi c omman d s t 5 t cycle refp del2 refp del1 refp del0 refa del3 refa del2 refa del1 refa del0 refi del3 refi del2 refi del1 refi del0 t cycle refp w/del=3 at t 0 is equivalent to refp w/del=2 at t 1 or refp w/del=1 at t 2 or refp w/del=0 at t 3 . refi w/del=3 at t 13 is equivalent to refi w/del=2 a t t 14 or refi w/del=1 at t 15 or refi w/del=0 at t 16 . refa w/del=3 at t 6 is equivalent to refi w/del=2 at t 7 or refi w/del=1 at t 8 or pre w/del=0 at t 9 .
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 22/76 rev 0.1 memory operations write transactions figure 9 shows four examples of memo ry write transactions. a transaction is one or more request packets (and the associated data packets) needed to perform a memory access. the state of the memory core and the address of the memory access determine how many request packets are needed to perform the access. the first timing diagram shows a page-hit write transactio n. in this case, the selected bank is already open (a row is already present in the sense amp array for the bank). in addition, the selected row for the memory access matches the address of the row already sensed (a page hit). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba. in this case, write data may be directly written into the sense amp array for the bank, and row operations (activate or precharge) are not needed . a col packet with wr command to co lumn ca1 of bank ba is presented on edge t 0 , and a second col packet with wr command to column ca2 of bank ba is presented on edge t 2 . two write data packets d (a1) and d (a2) follow thes e col packets after the write data delay t cwd . the two col packets are separated by the column-cycle time t cc . this is also the length of each write data packet. the second timing diagram shows an ex ample of a page-miss write transaction. in this case, the selected bank is already open (a row is already present in the sense am p array for the bank). however, the selected row for the memory access does not match the address of the row alread y sensed (a page miss). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba, and the bank contains a row other than ra. in this case, write data may not be directly written into the sense amp array for the bank. it is necessary to close the present row (precharge) and access the requested ro w (activate). a precharge command (pre to bank ba) is presented on edge t 0 . an activate command (act to row ra of bank ba) is presented on edge t 6 a time t rp later. a col packet with wr command to column ca1 of bank ba is presented on edge t 7 a time t rcd-w later. a second col packet with wr command to column ca2 of bank ba is presented on edge t 9 . two write data packets d (a1) and d (a2) follow these col packets after the write data delay t cwd . the two col packets are separated by the column-cycle time t cc . this is also the length of each write data packet. the third timing diagram shows an example of a page-empty write transaction. in this case, the selected bank is already closed (no row is present in the sense amp array for the bank). no row comparison is necessary for this case; however, the memory controller must still remember th at bank ba has been left cl osed. in this example, the access is made to row ra of bank ba. in this case, write data may not be directly written in to the sense amp array for the bank. it is necessary to access the requested row (activate). an activate command (act to row ra of bank ba) is presented on edge t 0 . a col packet with wr command to column ca1 of bank ba is presented on edge t 1 a time t rcd ? w later. a second col packet with wr command to column ca2 of bank ba is presented on edge t 3 . two write data packets d (a1) and d (a2) follow these col packets after the write data delay t cwd . the two col packets are separated by the column-cycle time t cc . this is also the length of each write data packet . after the final write command, it may be necessary to close the present row (precharge). a prec harge command (pre to bank ba) is presented on edge t 14 a time t wrp after the last col packet with a wr command. the de cision whether to close the bank or leave it open is made by the memory controller and its page policy. the fourth timing diagram sh ows another example of a page ? empty write transaction. this is similar to the previous example except that only a single write command is presented, ra ther than two write commands. this example shows that even with a mini mum length write transaction, the t ras parameter will not be a constraint. the t ras measures the minimum time between an activate command and a precharge command to a bank. this time interval is also constrained by the sum t rcd ? w + t wrp which will be larger for a write transaction. these two constraints (t ras and t rcd ? w + t wrp ) will be a function of the memory devi ce?s speed bin and the data transfer length (the number of write commands issued betw een the activate and prec harge commands), and the t ras parameter could become a constraint for write transactions for future speed bins. in this example, the sum t rcd ? w + t wrps is greater than t ras by the amount ? t ras .
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 23/76 rev 0.1 figure 9. write transactions cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle wr a2 t cwd t cc page-hit write example wr a1 d(a1) d(a2) transaction a: wr a2 = {ba, ca2} a0 = {ba, ra} a1 = {ba, ca1} a3 = {ba} cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle act a0 t cwd page-miss write example pre a3 d(a1) d(a2) wr a1 t rcd-w t cc wr a2 t rp transaction a: wr a2 = {ba, ca2} a0 = {ba, ra} a1 = {ba, ca1} a3 = {ba} page-empty write example cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle wr a1 t cwd act a0 d(a1) d(a2) wr a2 t rcd-w t wrp pre a3 t cc t dp transaction a: wr a2 = {ba, ca2} a0 = {ba, ra} a1 = {ba, ca1} a3 = {ba} page-empty write example ? core limited transaction b: wr b2 = {bb, cb2} b0 = {bb, rb} b1 = {bb, cb1} b3 = {bb} bb=ba cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle wr a1 t cwd act a0 d(a1) t rcd-w t wrp t ras ?
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 24/76 rev 0.1 read transactions figure 10 shows four examples of memory read transactions. a transaction is one or more request packets (and the associated data packets) needed to perform a memory access. the state of the memory core and the address of the memory access determine how many request packets are needed to perform the access. the first timing diagram shows a page-hit read transaction. in this case, the selected bank is already open (a row is already present in the sense amp array for the bank) . in addition, the selected row for the memory access matches the address of the row already sensed (a page hit). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba. in this case, read data may be directly read from the sense amp array for the bank, and no row operations (activate or precharge) are needed. a col packet with rd command to column ca1 of bank ba is presented on edge t 0 , and a second col packet with rd command to column ca2 of bank ba is presented on edge t 2 . two read data packets q (a1) and q (a2) follow thes e col packets after the read data delay t cac . the two col packets are separated by the column-cycle time t cc . this is also the length of each read data packet. the second timing diagram shows an example of a page-miss read transaction. in this case, the selected bank is already open (a row is already present in the sense am p array for the bank). however, the selected row for the memory access does not match the address of the row alread y sensed (a page miss). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba, and the bank contains a row other than ra. in this case, read data may not be directly read from the sense amp array for the bank. it is necessary to close the present row (precharge) and access the requested row (activate). a precharge command (pre to bank ba) is presented on edge t 0 . an activate command (act to row ra of bank ba) is presented on edge t 6 a time t rp later. a col packet with rd command to column ca1 of bank ba is presented on edge t 11 a time t rcd-r later. a second col packet with rd command to column ca2 of bank ba is presented on edge t 13 . two read data packets q(a1) and q(a2) follow these col packets after the read data delay t cac . the two col packets are separated by the column-cycle time t cc . this is also the length of each read data packet. the third timing diagram shows an example of a page-empty write transaction. in this case, the selected bank is already closed (no row is present in the sense amp array for the bank). no row comparison is necessary for this case; however, the memory controller must still remember th at bank ba has been left cl osed. in this example, the access is made to row ra of bank ba. in this case, read data may not be directly read from the sense amp array for the bank. it is necessary to access the requested row (activate). an activate command (act to row ra of bank ba) is presented on edge t 0 . a col packet with rd command to column ca1 of bank ba is presented on edge t 5 a time t rcd-r later. a second col packet with rd command to column ca2 of bank ba is presented on edge t 7 . two read data packets q (a1) and q (a2) follow these col packets after the read data delay t cac . the two col packets are separated by the column-cycle time t cc . this is also the length of each read data packet. after the final read command, it may be necessary to close the present row (precharge). a precha rge command ? pre to bank ba ? is presented on edge t 10 a time t rdp after the last col packet with a rd command. whet her the bank is closed or left open depends on the memory controller and its page policy. the fourth timing diagram shows anot her example of a page-empty read transaction. this is similar to the previous example except that it uses one read command instead of two read commands. in this case, the core parameter t ras may also be a constraint upon when the precharge command may be issued. the t ras measures the minimum time between an activate command and a precharge command to a bank. this time interval is also constrained by the sum t rcd ? r + t rdp and must be set to whichever is larger. these two constraints (t ras and t rcd-r + t rdp ) will be a function of the memory devi ce?s speed bin and the data transfer length (the number of read commands issued between the activate and precharge comman ds). in this example, the t ras is greater than the sum t rcd-r + t rdp by the amount ? t rdp .
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 25/76 rev 0.1 figure 10. read transactions cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle rd a2 t cac t cc page-hit read example rd a1 q(a1) q(a2) transaction a: rd a2 = {ba, ca2} a0 = {ba, ra} a1 = {ba, ca1} a3 = {ba} transaction a: rd a2 = {ba, ca2} a0 = {ba, ra} a1 = {ba, ca1} a3 = {ba} cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle act a0 t cac page-miss read example pre a3 q(a2) rd a1 t rcd-r t cc rd a2 t rp q(a1) cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle t cac act a0 q(a1) q(a2) rd a2 t rcd-r t rdp pre a3 t cc rd a1 transaction a: rd a2 = {ba, ca2} a0 = {ba, ra} a1 = {ba, ca1} a3 = {ba} page-empty read example transaction a: rd a2 = {ba, ca2} a0 = {ba, ra} a1 = {ba, ca1} a3 = {ba} page-empty read example ? core limited transaction b: rd b2 = {bb, cb2} b0 = {bb, rb} b1 = {bb, cb1} b3 = {bb} bb=ba cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle t cac act a0 q(a1) rd a1 t rcd-r ? t rdp pre a3 t ras act b0 t rp t rdp
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 26/76 rev 0.1 interleaved transactions figure 11 shows two examples of inte rleaved transactions. interleaved tr ansactions are overlapped with one another; a transaction is started be fore an earlier one is completed. the timing diagram at the top of th e figure shows interleaved write transactions. each transaction assumes a page-empty access; that is, a bank is in a closed state prior to an access, and is precharged after the access. with this assumption, each transaction requires the same number of request packets at the same relative positions. if banks were allowed to be in an open state, then each transaction would require a different number of request packets depending upon whether the transaction was page-e mpty, page-hit, or page-miss. this situation is more complicated for the memory controller, and will not be analyzed in this document. in the interleaved page ? empty write example, there are four sets of request pins rq11?rq0 shown along the left side of the timing diagram. the fi rst three show the timing slots used by each of the three requests packet types (act, col and pre), and the fourth set (all) shows the previous three merged together. this allows the pattern used for allocating request slots for the different packets to be seen more clearly. the slots at {t 0 , t 4 , t 8 , t 12 , ...} are used for rowa packets with act commands. this spacing is determined by the t rr parameter. there should not be interference between the interleaved transactions due to resource conflicts because each bank address ? ba, bb, bc, bd, and be ? is as sumed to be different from another. if two of the bank addresses are the same, the later transaction would need to wait until the earlier transaction had completed its precharge operation. five different ban ks are needed because the effective t rc (t rc + ? t rc ) is 20 t cycle . the slots at {t 1 , t 3 , t 5 , t 7 , t 9 , t 11 , ...} are used for col packets with wr commands. this frequency of the col packet spacing is determined by the t cc parameter and by the fact that th ere are two column accesses per row access. the phasing of the col packet spacing is determined by the t rcd-w parameter. if the value of t rcd-w required the col packets to occupy the same request sl ots as the rowa packets (this case is not shown), the delc field in the col packet could be used to place the col packet one t cycle earlier. the dq bus slots at {t 7 , t 9 , t 11 , t 13 , ...} carry the write data packets { d (a1), d (a2), d (b1), d (b2), .... }. two write data packets are written to a ban k in each transaction. the dq bus is completely filled with write data; no idle cycles need to be introduced because ther e are no resource conflicts in this example. the slots at {t 14 , t 18 , t 22 , ...} are used for rowp packets with pre commands. this frequency of rowp packet spacing is determined by the t pp parameter. the phasing of the rowp pa cket spacing is determined by the t wrp parameter. if the value of t wrp required the rowp packets to occupy th e same request slots as the rowa or col packets already assigned (this case is not shown), the dela y field in the rowp packet could be used to place the rowp packet one or more t cycle earlier. there is an example of an interleaved page-empty read at the bottom of the figure. as before, there are four sets of request pins rq11?rq0 shown along the left side of the timing diagram, allowing the pattern used for allocating request slots for the different packets to be seen more clearly. the slots at {t 0 , t 4 , t 8 , t 12 , ...} are used for rowa packets with act commands. this spacing is determined by the t rr parameter. there should not be interference between the interleaved transactions due to resource conflicts because each bank address ? ba, bb, bc, and bd ? is assumed to be different from another. four different banks are needed because the effective t rc is 16 t cycle . the slots at {t 5 , t 7 , t 9 , t 11 , ...} are used for col packets with rd co mmands. this frequency of the col packet spacing is determined by the t cc parameter and by the fact that there are two column accesses per row access. the phasing of the col packet spac ing is determined by the t rcd ? r parameter. if the value of t rcd ? r required the col packets to occupy the same request slots as the rowa packets (this case is not shown), the delc field in the col packet could be used to place the packet one t cycle earlier. the dq bus slots at {t 11 , t 13 , t 15 , t 17 , ...} carry the read data packets { q (a1), q (a2), q (b1), q (b2), ...}. two read data packets are read from a bank in each transaction. the dq bus is comp letely filled with read data ? that is, no idle cycles need to be in troduced because there are no reso urce conflicts in this example. the slots at {t 10 , t 14 , t 18 , t 22 , ...} are used for rowp packets with pre commands. this frequency of the rowp packet spacing is determined by the t pp parameter. the phasing of the ro wp packet spacing is determined by the t rdp parameter. if the value of t rdp required the rowp packets to occu py the same request slots as the rowa or col packets already assigned (this case is not sh own), the delay field in the rowp packet could be used to place the rowp packet one or more t cycle earlier.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 27/76 rev 0.1 figure 11. interleaved transactions cfm cfmn rq11?rq0 (act) t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rr interleaved page-empty read example transaction d: rd d2 = = {bd, rd} d1 = = {bd} t rc dq15?0 dqn15?0 rq11?rq0 (col) rd b1 rd c1 rd c2 rd d1 rd d2 t cc rq11?rq0 (pre) pre b3 pre d3 rq11?rq0 (all) pre b3 pre c3 pre d3 act a0 act b0 rd a1 rd a2 act c0 rd b1 rd b2 act d0 rd c1 rd c2 act e0 rd d1 rd d2 act f0 rd e1 rd e2 transaction a: rd a2 = = {ba, ra} a1 = = {ba} transaction b: rd b2 = = {bb, rb} b1 = = {bb} transaction c: rd c2 = = {bc, rc} c1 = = {bc} transaction e: rd e2 = = {be, re} e1 = = {be} ba,bb,bc,bd are different banks. be = ba act c0 act d0 act f0 act e0 act a0 t cycle act b0 t rcd-r rd a1 rd e1 rd e2 t rp q(c1) q(c2) t rdp q(b2) q(a1) t cac rd a2 rd b2 pre a3 q(a2) pre a3 pre c3 q(b1) cfm cfmn rq11?rq0 (act) t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t rr interleaved page-empty write example transaction d: wr d2 = = {bd, rd} d1 = = {bd} t rc t ? rc dq15?0 dqn15?0 rq11?rq0 (col) wr b2 wr c1 wr c2 wr d1 wr d2 wr e1 wr e2 t wrp rq11?rq0 (pre) pre b3 pre c3 rq11?rq0 (all) pre a3 pre b3 pre c3 act a0 act b0 wr b1 wr b2 act c0 wr c1 wr c2 act d0 wr d1 wr d2 act c0 wr e1 wr e2 act f0 wr f1 wr f2 transaction a: wr a2 = = {ba, ra} a1 = = {ba} transaction b: wr b2 = = {bb, rb} b1 = = {bb} transaction c: wr c2 = = {bc, rc} c1 = = {bc} transaction e: wr e2 = = {be, re} e1 = = {be} transaction f: wr f2 = = {bf, rf} f1 = = {bf} ba,bb,bc,bd,be are different banks. bf = ba act c0 act d0 act f0 act e0 act a0 the effective t rc time is increased by 4 t cycle . t cycle act b0 t rcd-w t cc wr a1 wr a2 wr b1 wr f1 wr f2 t cwd d(a1) d(a2) d(b1) d(c2) d(e1) t rp d(d1) d(b2) wr a1 wr a2 t ? wrp d(d2) pre a3 d(c1) d(e1)
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 28/76 rev 0.1 read/write interaction the previous section described overlapped read transactions and overlapped write transact ions in isolation. this section will describe the interaction of read and write tr ansactions and the spacing re quired to avoid channel and core resource conflicts. figure 12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. two col packets with wr commands are presented on cycles t 0 and t 2 . the write data packets are presented a time t cwd later on cycles t 4 and t 6 . the device requires a time t ? wr after the second col packet with a wr command before a col packet with a rd command may be presen ted. two col packets with rd commands are presented on cycles t 11 and t 13 . the read data packets are returned a time t cac later on cycles t 17 and t 19 . the time t ? wr is required for turning around intern al bi-directional interconnections (ins ide the device). this time must be observed regardless of whether the write and read command s are directed to the same bank or different banks. a gap t wr ? bub, xdr dram will appear on the dq bus between the end of the d (a2) packet and the beginning of the q (b1) packet (measured at the approp riate packet reference points). the si ze of this gap can be evaluated by calculating the difference between cycles t 2 and t 17 using the two timing paths: t wr ? bub,xdrdram = t ? wr + t cac ? t cwd ? t cc in this example, the value of t wr-bub, xdr dram is greater than its minimum value of t wr ? bub, xdr dram, min . the values of t ? wr and t cac are equal to their minimum values. in the second case, the timing diagram displayed at the bottom of figure 12 illustrates a read transaction followed by a write transaction. two col packets with rd commands are presented on cycles t 0 and t 2 . the read data packets are returned a time t cac later on cycles t 6 and t 8 . the device requires a time t ? rw after the second col packet with a rd command before a col packet with a wr command may be presented. two col packets with wr commands are presented on cycles t 10 and t 12 . the write data packets are presented a time t cwd later on cycles t 13 and t 15 . the time t ? rw is required for turning around the ex ternal dq bi-directional interconnections (outside the device). this time must be observed rega rdless whether the read and write commands are directed to the same bank or different banks. the time t ? rw depends upon four timing parameters, and may be evaluated by calculating the difference between cycles t 2 and t 13 using the two timing paths: t ? rw + t cwd = t cac + t cc + t rw ? bub,xdrdram or t ? rw = (t cac ? t cwd ) + t cc + t rw ? bub,xdrdram in this example, the values of t ? rw , t cac , t cwd , t cc , and t rw ? bub,xdr dram are equal to their minimum values.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 29/76 rev 0.1 figure 12. write/read interaction dq15?0 dqn15?0 transaction a: wr a1 = {ba, ca1} rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle wr a1 t ? wr t cac t cwd a2 = {ba, ca2} write/read turnaround example cfm cfmn wr a2 rd b1 rd b2 transaction b: rd b1 = {bb, cb1} b2 = {bb, cb2} d(a1) d(a2) q(b1) q(b2) t cc t wr-bub, xdr dram t dr dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle rd a1 t ? rw t cwd t cac read/write turnaround example cfm cfmn rd a2 wr b1 wr b2 q(a1) q(a2) d(b1) d(b2) t cc t rw-bub,xdr dram transaction a: wr a1 = {ba, ca1} a2 = {ba, ca2} transaction b: rd b1 = {bb, cb1} b2 = {bb, cb2}
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 30/76 rev 0.1 propagation delay figure 13 shows two timing diagrams that display the system-level timing relati onships between the memory component and the memory controller. the timing diagram at the top of th e figure shows the case of a write- read-write command and data at the memory component. in this case, the timing will be identical to what has already been shown in the previous sections; i.e. with all timing measured at the pins of th e memory component. this timing diagram was produced by merging portions of the top and bottom timing diagrams in figure 12. the example shown is that of a single col packet with a write command, follo wed by a single col packet with a read command, followed by a second col packet with a wr ite command. these accesses all assume a page-hit to an open bank. a timing interval t ? wr is required between the first wr command and the rd command, an d a timing interval t ? rw is required between the rd command and the se cond wr command. there is a write data delay t cwd between each wr command and the associated writ e data packet d. there is a read data delay t cac between the rd command and the associated read da ta packet q. in this example, all ti ming parameters have assumed their minimum values except t wr ? bub,xdr dram . the lower timing diagram in the figu re shows the case where timing sk ew is present between the memory controller and the memory component. this skew is the result of the propagatio n delay of signal wavefronts on the wires carrying the signals. the example in the lower di agram assumes that there is a propagation delay of t pd ? rq along both the rq wires and the cfm/cfmn clock wires between the memory controller and the memory component (the value of t pd ? rq used here is 1*t cycle ). note that in an actual system the t pd ? rq value will be different for each memory component connected to the rq wires. in addition, it is assumed that there is a propagation delay t pd ? d along the dq/dqn wires between the memory controller and the memory component (the direction in which write data travels, and it is assumed that there is the same propagation delay t pd ? q along the dq/dqn wires between the memory component and the memory controller (the direction in which read data travels). the su m of these two propagation delays is also denoted by the timing parameter t pd,cyc = t pd ? d + t pd ? q . as a result of these propagation delays, the position of packets will have timing skews that depend upon whether they are measured at the pins of the memory controller or the pins of the memory component. for example, the cfm/cfmn signals at the pins of the memory component are t pd ? rq later than at the pins of the memory controller. this is shown by the cycl e numbering of the cfm/cfmn signals at the two locations ? in this example cycle t 1 at the memory controller aligns with cycle t 0 at the memory component. all the request packets on the rq wires will have a t pd ? rq skew at the memory component relative to the memory controller in this example. because the t pd ? d propagation delay of wr ite data matches the t pd ? rq propagation delay of the write command, the controller may issue the write data packet d(a0) relative to the col packet with the first write command ?wr a0? with the normal write data delay t cwd . if the propagation delays between the memory controller and memo ry component were different for the rq and dq buses (not shown in this example), the write data delay at the memo ry controller would need to be adjusted. a propagation delay is seen by the read command ? that is, the read command will be delayed by a t pd ? rq skew at the memory component relative to the memory contro ller. the memory component will return the read data packet q(b0) relative to this read comma nd with the normal read data delay t cac (at the pins of the memory component). the read data packet will be skewed by an additional propagation delay of t pd ? q as it travels from the memory component back to the memory controller. the effective re ad data delay measured between the read command and the read data at the memory controller will be t cac + t pd ? rq + t pd ? q . the t pd ? rq factor is caused by the propag ation delay of the request packet s as they travel from memory controller to memory component. the t pd ? q factor is caused by the propagatio n delay of the read data packets as they travel from memory component to memory controller.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 31/76 rev 0.1 propagation delay (continue) all timing parameters will be equal to their minimum values except t wr ? bub,xdr dram (as in the top diagram), and the timing parameters t rw ? bub,xdr dram and t ? rw . these will be larger than their minimum values by the amount (t pd,cyc ? t pd,cyc,min ), where t pd,cyc = t pd ? d + t pd ? q . this may be seen by evaluating the two timing paths between cycle t 9 at the controller and cycle t 21 at the xdr dram: t ? rw + t pd ? rq + t cwd = t pd ? rq + t cac + t cc + t rw ? bub,xdr dram or t ? rw = (t cac ? t cwd ) + t cc + t rw ? bub,xdr dram the following relationship was shown for figure 12. t ? rw,min = (t cac ? t cwd )+ t cc + t rw ? bub,xdrdram,min or (t ? rw ? t ? rw,min ) = (t rw ? bub,xdr dram ? t rw ? bub,xdrdram,min ) in other words, the two timing parameters t rw ? bub,xdr dram and t ? rw will change together. the relationship of this change to the propagation delay t pd,cyc ( = t pd ? d + t pd ? q ) can be derived by looking at the two timing paths from t 15 to t 21 at the xdr dram: t pd ? q + t cc + t rw ? bub, 10 + t pd ? d = t cc + t rw ? bub,xdr dram or t rw ? bub,xdr dram = t rw ? bub, 10 + t pd ? d + t pd ? q or t rw ? bub, xdr dram = t rw ? bub, 10 + t pd,cyc in a system with minimum propagation delays: t rw ? bub,xdrdram,min = t rw ? bub, 10 + t pd,cyc,min and since t rw ? bub, 10 is equal to t rw ? bub,yrac,min in both cases, the following is true: (t pd,cyc ? t pd,cyc,min ) = (t rw ? bub,xdr dram ? t rw ? bub,xdrdram,min ) = (t ? rw ? t ? rw,min ) in other words, the values of the t rw ? bub,xdr dram,min and t ? rw,min timing parameters correspond to the value of t pd,cyc,min for the system (this is equal to one t cycle ). as t pd,cyc is increased from this minimum value, t rw ? bub,xdr dram and t ? rw increase from their minimum valu es by an equivalent amount.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 32/76 rev 0.1 figure 13. propagation delay transaction a: wr a0 = ? rw t cwd write-read-write at xdr dram (portions of top and bottom timing diagrams of figure 12 merged) rd b0 wr a0 t ? x dr dra m wr c0 t wr-bub,xdr dram q(b1) t cc transaction b: rd b0 = = controller rq dq t pd-rq t pd-d t pd-q rq dq xdr dram transaction a: wr a0 = {ba, ca0} dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle t ? wr write-read-write at controller and xdr dram w/t pd-rq = t pd-q = t pd-d = 1*t cycle cfm cfmn controller t pd-q transaction b: rd b0 = {bb, cb0} transaction c: wr c0 = {bc, cc0} dq15?0 dqn15?0 rq11 ?rq0 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t -1 t 19 t 20 t 21 t 22 t cwd t cwd cfm cfmn t cac t pd-d rd b0 wr a0 rd b0 t pd-rq t pd-rq t pd-rq t pd-d t cc d(a0) t rw-bub, x10 d(c0) d(a0) q(b0) d(c0) wr a0 t ? rw wr c0 q(b0) t cycle t cc wr c0 t rw-bub,xdr dram x dr dra m
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 33/76 rev 0.1 register operations serial transactions the serial interface consists of five pins. this includes rst, sck, cmd, sdi, and sdo. sdo uses cmos signaling levels. the other four pins use rsl signaling levels. rst, cmd, sdi, and sdo use a timing window, which surrounds the falling ed ge of sck). the rst pin is used for initialization. figure 14 and figure 15 show examples of a serial write transaction and a serial read transaction. each transaction starts on cycle s 4 and requires 32 sck edges. the next serial transaction can begin on cycle s 36 . sck does not need to be asserted if there is no transaction. serial write transaction the serial device write transaction in figure 14 begins with the start [3:0] field. this consists of bits ?1100? on the cmd pin. this indicates to the xdr dram that th e remaining 28 bits constitute a serial transaction. the next two bits are the scmd [1:0] fi eld. this field contains the serial command, the bits 00 in the case of a serial device write transaction. the next eight bits are ?00? and the sid [5:0] field. this field contains the seri al identification of the device being accessed. the next eight bits are the sadr [7:0] field. this field contains the serial address of the control register being accessed. a single bit ?0? follows next. this bit allows one cycle for the access time to the control register. the next eight bits on the cmd pin is th e swd [7:0] field. this is the write da ta that is placed into the selected control register. a final bit ?0? is driven on the cmd pin to finish the serial write transaction. a serial broadcast write is identical ex cept that the contents of the sid [5:0 ] field in the transaction is ignored and all devices perform the register write. the sdi and sdo pins are not used during either serial write transaction. serial read transaction the serial device read transaction in figure 15 begins with the start [3:0] field. this consists of bits ?1100? on the cmd pin. this indicates that the remaining 28 bits constitute a serial transaction. the next two bits are the scmd [1:0] fiel d. this field contains the serial comma nd, and the bits ?10? in the case of a serial device read transaction. the next eight bits are ?00? and the sid [5:0] field. this field contains the seri al identification of the device being accessed. the next eight bits are the sadr [7:0] field and contain the serial address of the control register being accessed. a single bit ?0? follows next. this bit allows one cycle for the access time to the control register and time to turn on the sdo output driver. the next eight bits on the cmd pin are the sequence ?00000000?. at the same time, the eight bits on the sdo pin are the srd [7:0] field. this is the read data that is a ccessed from the selected control register. note the output timing convention here: bit srd [7] is driven from a time t q, si, max after edge s 26 to a time t q, si, min after edge s 27 . the bit is sampled in the controller by the edge s 27 . a final bit ?0? is driven on the cmd pin to finish the serial read transaction. a serial forced read is identical except that the contents of the sid [5:0] field in the transaction is ignored and all devices perform the register read. this is used for device testing. figure 16 shows the response of a dram to a serial device read transaction when its internal sid [5:0] register field doesn?t match the sid [5:0] field of the transaction. in stead of driving read data fr om an internal register for cycle edges s 27 through s 34 on the sdo output pin, it passes the inpu t data from the sdi input pin to the sdo output pin during this same period. table 8. scmd field encoding summary scmd [1:0] command description 00 sdw serial device write-one device is written, the one whose sid[5:0] register matches the sid [5:0] filed of the transaction. 01 sbw serial broadcast write ? all devices ar e written, regardless of the contents of the sid [5:0] register and the sid [5:0] transaction field. 10 sdr serial device read ? one device is read, the one whose sid[5:0] register matches the sid [5:0] field of the transaction. 11 sfr serial forced read ? all devices are read, regardless of the contents of the sid [5:0] register and the sid [5:0] transaction field.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 34/76 rev 0.1 figure 14. serial write transaction figure 15. serial read transaction ? selected dram figure 16. serial read tr ansaction ? non-selected dram sc k s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s 40 s 42 s 44 s 46 s 48 s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 16 s 18 t cyc,sck transaction rst cmd sdi (input) sdo (output) scmd ?0? ?0? ?0? 2?h0, sid[5:0] ?0? 5 4 3 2 1 0 7 sadr [7:0] 6543210 ?0' 7 swd [7:0] 6543210 start ?1? ?1? ?0? ?0? ?0' sc k rst cmd sdi (input) sdo (output) s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s 40 s 42 s 44 s 46 s 48 s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 16 s 18 t cyc,sck scmd ?1? ?0? ?0? 2?h0, sid[5:0] ?0? 5 4 3 2 1 0 7 sadr [7:0] 6543210 ?0? 8?h00 ?0? ?0? ?0? ?0? ?0? ?0? ?0? start ?1? ?1? ?0? ?0? ?0' ?0' 7 srd [7:0] 6543210 transaction sc k rst cmd sdi (input) sdo (output) s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s 40 s 42 s 44 s 46 s 48 s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 16 s 18 t cyc,sck transaction scmd ?0? ?0? ?0? 2?h0, sid[5:0] ?0? 5 4 3 2 1 0 7 sadr [7:0] 6543210?0' ?0? 8?h00 ?0? ?0? ?0? ?0? ?0? ?0? ?0? 7 srd [7:0] 6543210 7 srd [7:0] 6543210 sdi t p, s i sdo s 28 combinational propagation from sdi to sdo start ?1? ?1? ?0? ?0? ?0'
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 35/76 rev 0.1 register summary figure 17 through figure 40 show the control registers in the memory component. the control registers are responsible for configuring the component?s operating mode , for managing power state transitions, for managing refresh, and for managing calibration operations. a control register may contain up to eight bits. each figure shows defined bits in white and reserved bits in gray. reserved bits must be written as 0 and must be ignored when read. write-only fields must be ignored when read each figure displays the foll owing register information: 1. register name 2. register mnemonic 3. register address (sadr [7:0 ] value needed to access it) 4. read-only, write-only or read-write 5. initialization state 6. description of each defined register field figure 17 shows the serial identification register. this regi ster contains the sid [5:0] (s erial identification field). this field contains the serial identifi cation value for the device. the value is compared to the sid [5:0] field of a serial transaction to determine if the serial transaction is directed to this device. the serial identification value is set during the initialization sequence. figure 18 shows the configuration register. it contains three fields. the first is the width field. this field allows the number of dq/dqn pins used for memory read and write accesses to be adjusted. the sle field enables data to be written into the memory through the serial interface using the wdsl register. figure 19 shows the power management register. it contains two fields. the first is the px field. when this field is written with a 1, the memory compon ent transitions from power down to active state. it is usually unnecessary to write a 0 into this field; this is done automatica lly by the pdn command in a colx packet. the pst field indicates the current power state of the memory component. figure 20 shows the write data serial load register. it permits data to be written into memory via the serial interface. figure 23 shows the refresh bank control register. it contains two fields: bank and mbr. the bank field is read-write and contains the bank address used by self-ref resh during the powerdown state. the mbr field controls how many banks are refreshed during each refresh operation. figure 24, figure 25 and figure 26 show different fields of the refresh row register (hig h, middle, and low). this read-write fi eld contains the row address used by self- and auto-refresh. see ?refresh transactions? on page 40 for more details. figure 27 and figure 28 show the current calibration 0 and 1 registers. they contain the ccvalue0 and ccvalue1 fields, respectively. these are read-write fields which control the amount of iol current driven by the dq and dqn pins during a read transaction. the current calibration 0 register controls the even-numbered dq and dqn pins, and the current calibration 1 controls the odd-numbered dq and dqn pins. figure 29 and figure 30 shows the impedance calibration 0 and 1 registers. they contain the zcvalue0 and zcvalue1 fields, respectively. these ar e read-write fields that control the impedance of the on-chip termination components in the dq and dqn pins. the impedance calibration 0 register controls the even-numbered dq and dqn pins, and the impedance calibration 1 controls the odd-numbered dq and dqn pins. figure 33 through figure 39 shows the test registers. this includes th e test, dll, pll0, pll1, ift, da, and part registers. these are used during de vice testing. they are not to be read or written during normal operation. figure 40 shows the dly register. this is used to set the value of t cac and t cwd used by the component. see ?timing parameters? on page 60.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 36/76 rev 0.1 figure 17. serial iden tification (sid) register figure 18. configuration (cfg) register figure 19. power management (pm) register figure 20. write data serial load (wdsl) control register 7 6 5 4 3 2 1 0 pst [1:0] reserved power management register read/write register sadr [7:0]: 00000011 2 pm [7:0] resets to 00000000 2 px ? power down exit field. (write-one-only read = zero) 0 2 ? power down entry do not write zero ? use pdn command. 1 2 ? power down exit ? write one to exit pst [1:0] ? power state field (read-only). 00 2 ? power down (with self-refresh). 01 2 ? active/active-idle 10 2 ? reserved 11 2 ? reserved px 7 6 5 4 3 2 1 0 serial identification register read-only register sadr [7:0]: 00000001 2 sid [7:0] resets to 00000000 2 sid [5:0] ? serial identification field. this field contains the serial i dentification value for the device. the value is compared to the sid [5 :0] field of a serial transaction to determine if the serial transacti on is directed to this device. the serial identification value is se t during the initialization sequence. reserved sid [5:0] configuration register read/write register sadr [7:0]: 00000010 2 cfg [7:0] resets to 00000100 2 width [2:0] ? device interface width field. 000 2 ? reserved 001 2 ? reserved 010 2 ? 4 device width 011 2 ? 8 device width 100 2 ? 16 device width 101 2 , 110 2 , 111 2 ? reserved sle - serial load enable field. 0 2 ? wdsl-path-to-memory disabled 1 2 ? wdsl-path-to-memory enabled rsrv width [2:0] rsrv sle rsrv 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 wdsl [7:0] write data serial load control register read/write register sadr [7:0]: 00000100 2 wdsl [7:0] resets to 00000000 2 wdsl [7:0] ? writing to this register pl aces eight bits of data into the serial-to-parallel conversion lo gic (the ?demux? block of figure 2). writing to this register ?2 x16? times accumulates a full ?t cc ? worth of write data. a subsequent wr command (with sle = 1 in cfg register in figure 18) will write this data (rather than dq data) to the sense amps of a memory bank. the shifting order of the write data is shown in table 10.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 37/76 rev 0.1 figure 21. rq scan high (rqh) register figure 22. rq scan low (rql) register figure 23. refresh bank (refb) control register figure 24. refresh high (refh) row register figure 25. refresh middle (refm) row register 7 6 5 4 3 2 1 0 mbr [1:0] reserved refresh bank control register read/write register sadr [7:0]: 00001000 2 refb [7:0] resets to 00000000 2 bank [2:0] ? refresh bank field. this field returns the bank address for the next self-refresh operation when in powerdown power state. mbr [1:0] ? multiple-bank and multi-row refresh control field. 00 2 ? single-bank refresh 10 2 ? reserved 01 2 ? reserved 11 2 ? reserved bank [2:0] 7 6 5 4 3 2 1 0 rql [7:0] rq scan low register read/write register sadr [7:0]: 00000111 2 rql [7:0] resets to 00000000 2 rqh [7:0] ? latched value of rq [7:0] in rq wire test mode. 7 6 5 4 3 2 1 0 reserved rq scan high register read/write register sadr [7:0]: 00000110 2 rqh [7:0] resets to 00000000 2 rqh [3:0] ? latched value of rq [11:8] in rq wire test mode. rqh [3:0] 7 6 5 4 3 2 1 0 refresh high row register read/write register sadr [7:0]: 00001001 2 refh [7:0] resets to 00000000 2 reserved ? refresh row field. this field contains the high-order bits of the row address that will be refreshed during the next refresh interval. this row address will be incremented after a refi command for auto-refresh, or when the bank [2:0] field for the refb register equals the maximum bank address for self-refresh. reserved 7 6 5 4 3 2 1 0 reserved refresh middle row register read/write register sadr [7:0]: 00001010 2 refm [7:0] resets to 00000000 2 r [10:8] ? refresh row field. this field contains the middle-or der bits of the row address that will be refreshed during the next refr esh interval. this row address will be incremented after a refi command for auto-refresh, or when the bank [2:0] field for the refb register equals the maximum bank address for self-refresh. r [10:8]
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 38/76 rev 0.1 figure 26. refresh lo w (refl) row register figure 27. io configuration (iocfg) register figure 28. current calib ration 0 (cc0) register figure 29. current calib ration 1 (cc1) register figure 30. impedance calibration 0 (zc0) register 7 6 5 4 3 2 1 0 reserved current calibration 1 register read/write register sadr [7:0]: 00010001 2 cc1 [7:0] resets to 00001111 2 ccvalue1 [5:0] ? current calibration value field. this field controls the amount of current drive for the odd-numbered dq and dqn pins. ccvalue1 [5:0] 7 6 5 4 3 2 1 0 reserved current calibration 0 register read/write register sadr [7:0]: 00010000 2 cc0 [7:0] resets to 00001111 2 ccvalue0 [5:0] ? current calibration value field. this field controls the amount of current drive for the even-numbered dq and dqn pins. ccvalue0 [5:0] 7 6 5 4 3 2 1 0 refresh low row register read/write register sadr [7:0]: 00001011 2 refl [7:0] resets to 00000000 2 r [7:0] ? refresh row field. this field contains the low-order bits of the row address that will be refreshed during the next refresh interval. this row address will be incremented after a refi command for auto-refresh, or when the bank [2:0] field for the refb register equals the maximum bank address for self-refresh. r [7:0] 7 6 5 4 3 2 1 0 reserved impedance calibration 0 register read/write register sadr [7:0]: 00010010 2 zc0 [7:0] resets to 00000000 2 reserved 7 6 5 4 3 2 1 0 reserved current calibration 0 register read/write register sadr [7:0]: 00010000 2 cc0 [7:0] resets to 00001111 2 odf [1:0] ? overdrive function field. 00 ? nominal vosw,dq range 01 ? reserved 10 ? reserved 11 ? reserved odf [1:0]
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 39/76 rev 0.1 figure 31. impedance calibration 1 (zc1) register figure 32. current fuse setting 0 (fzc0) register figure 33. current fuse setting 1 (fzc1) register figure 34. read only memory 0 (rom0) register figure 35. read only memory 1 (rom1) register 7 6 5 4 3 2 1 0 vendor [3:0] read only memory 0 register read-only register sadr [7:0]: 00010110 2 rom0 [7:0] resets to vvvvmmmm mask [3:0] ? version number of mask (0001 2 is first version). vendor [3:0] ? vendor number for component: 0000 ? reserved 0100 ? 1111 ? reserved 0001 ? toshiba 0010 ? elpida 0011 ? sec mask [3:0] 7 6 5 4 3 2 1 0 reserved impedance calibration 1 register read/write register sadr [7:0]: 00010011 2 zc1 [7:0] resets to 00000000 2 resereved. 7 6 5 4 3 2 1 0 reserved current fuse setting register read-only register sadr [7:0]: 00010100 2 fzc0 [7:0] resets to vvvvvvvv (vendor-dependent reset value) reserved 7 6 5 4 3 2 1 0 reserved current fuse setting register read-only register sadr [7:0]: 00010101 2 fzc1 [7:0] resets to vvvvvvvv (vendor-dependent reset value) reserved 7 6 5 4 3 2 1 0 bb [1:0] read only memory 1 register read-only register sadr [7:0]: 00010111 2 rom0 [7:0] resets to bbrrrccc cb [2:0] ? column address bits: #bits = 6 + cb [2:0] rb [2:0] ? row address bits: #bits = 10 + rb [2:0] bb [2:0] ? bank address bits: #bits = 2 + bb [2:0] there three fields indicate how many column, row, and bank address bits are present. an offset of {6,10,2} is added to the field value to give the number of address bits. cb [2:0] rb [2:0]
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 40/76 rev 0.1 figure 36. test register figure 37. dll register figure 38. pll0 register figure 39. pll1 register figure 40. ift register figure 41. da register 7 6 5 4 3 2 1 0 reserved da register read/write register sadr [7:0]: 00011101 2 da [7:0] resets to 00000000 2 tbd 7 6 5 4 3 2 1 0 reserved ift register read/write register sadr [7:0]: 00011100 2 ift [7:0] resets to 00000000 2 tbd 7 6 5 4 3 2 1 0 wtl reserved test register read/write register sadr [7:0]: 00011000 2 test [7:0] resets to 00000000 2 wte ? wire test enable wtl ? wire test latch wte 7 6 5 4 3 2 1 0 reserved dll register read/write register sadr [7:0]: 00011001 2 dll [7:0] resets to 00000000 2 tbd 7 6 5 4 3 2 1 0 reserved pll0 register read/write register sadr [7:0]: 00011010 2 pll0 [7:0] resets to 00000000 2 tbd 7 6 5 4 3 2 1 0 reserved pll1 register read/write register sadr [7:0]: 00011011 2 pll1 [7:0] resets to 00000000 2 tbd
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 41/76 rev 0.1 figure 42. delay (dly) control register figure 43. partner-definabl e (part0-partf) registers 7 6 5 4 3 2 1 0 cwd [3:0] dly register read/write register sadr [7:0]: 00011111 2 dly [7:0] resets to 01000110 2 cac [3:0] - programmed value of t cac timing parameter: 0110 2 ? t cac = 6 * t cycle 1000 2 ? t cac = 8 * t cycle 0111 2 ? t cac = 7 * t cycle others ? reserved cwd [3:0] ? programmed value of t cwd timing parameter: 0011 2 ? t cwd = 3 * t cycle 0100 2 ? t cwd = 4 * t cycle others ? reserved cac [3:0] 7 6 5 4 3 2 1 0 reserved part0 register read/write register sadr [7:0]: 10000000 2 part0 [7:0] resets to 00000000 2 part1 register read/write register sadr [7:0]: 10000001 2 part1 [7:0] resets to 00000000 2 partf register read/write register sadr [7:0]: 10001111 2 partf [7:0] resets to 00000000 2 7 6 5 4 3 2 1 0 reserved 7 6 5 4 3 2 1 0 reserved note: the partner-definable registers should not be wri tten or read; doing so will produce undefined results.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 42/76 rev 0.1 maintenance operations refresh transactions figure 44 contains two timing diagrams showing examples of refresh transactions. the top timing diagram shows a single refresh operation. bank ba is assumed to be closed (in a precharged state) when a refa command is received in a rowp packet on clock edge t 0 . the refa command causes the row addressed by the refr register (refh/refm/refl) to be opened (sensed) and placed in the sense amp array for the bank. note that the refa and refi commands are similar to the act command functionally; both specify a bank address and delay value, and both cause the selected bank to open (to become sensed.) the difference is that the act command is accompanied by a row address in th e rowa packet, while the refa and refi commands use a row address in the refr register (refh/refm/refl). after a time t ras , a rowp packet with refp command to bank ba is presented. this causes the bank to be closed (precharged), leaving the bank in the same state as when the refresh transaction began. note that the refp command is equivalent to the pre command functionally; both specify a bank address and delay value, and both cause the selected bank to close (to become precharged). after a time t rp , another rowp packet with refa command to ban k bb is presented (banks ba and bb are the same in this example). this starts a second refresh cycle. each refresh transaction requires a total time t rc = t ras + t rp , but refresh transactions to different banks may be interleaved like normal read and write transactions. each row of each bank must be refreshed once in every t ref interval. this is shown with the fourth rowp packet with a refa command in the top timing diagram. interleaved refresh transactions the lower timing diagram in figure 44 represents one way a memory controller might handle refresh maintenance in a real system. a series of eight rowp packets with refa commands (except for the last which is a refi command) are presented starting at edge t 0 . the packets are spaced with intervals of t rr . each refa or refi command is addressed to a different bank (ba through bh) but uses the same row address from the refr (refh/refm/refl) register. the eighth refi command uses this address and then increments it so the next set of eight refa/refi commands will refresh the next set of rows in each bank. a series of eight rowp packets with refp co mmands are presented effectively at edge t 10 (a time t ras after the first rowp packet with a refa command). the packets are spaced with intervals of t pp . like the refa/refi commands, each refp command is addressed to a different bank (ba through bh). this burst of eight refresh transactio ns fully utilizes the memory componen t. however, other read and writes transactions may be interleaved with the refresh transactio ns before and after the burst to prevent any loss of bus efficiency. in other words, a rowa packet with act comma nd for a read or write could have been presented at edge t? 4 (a time t rr before the first refresh transaction starts at edge t 0 ). also, a rowa packet with act command for a read or write could have been presented at edge t 36 (a time t rr after the last refresh transaction starts at edge t 32 ). in both cases, the other request packets fo r the interleaved read or write accesses (the precharge commands and the read or write commands) could be slotted in among the request packets for the refresh transactions.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 43/76 rev 0.1 figure 44. refresh transactions cfm cfmn rq11 ?rq0 t cycle t rc refresh transaction refa a0 t ras t rp refa b0 refa c0 dq15?0 dqn15?0 transaction a: ref a0 = {ba, refr} a1 = = {bb, refr} b1 = = {bc, refr} c1 = interleaved refresh example cfm cfmn rq11?rq0 (act) refi h0 refa g0 refa i0 dq15?0 dqn15?0 rq11?rq0 (pre) refp e1 refp f1 refp g1 rq11?rq0 (all) refp g1 refp e1 refp f1 refa i0 refa h0 refa g0 refp h1 refp h1 transaction d: ref d0 = {bd, refr} d1 = = {ba, refr} a1 = = {bb, refr} b1 = = {bc, refr} c1 = = {be, refr} e1 = = {bc, refr} f1 = = ba transaction g: ref g0 = {bg, refr} g1 = = {bh, refr} h1 = = {bi, refr + =
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 44/76 rev 0.1 calibration transactions figure 45 shows the calibration transaction diagrams for the xdr dram device. there is one calibration operation supported: calibration of the output current level i ol each dqi and dqni pin. the output current calibration sequen ce is shown in the upper diagram. it begins when a period of t cmd ? calc is observed after the last rq packet (with command ?cmd a? in this example). no request pa ckets should be issued in this period. a colx packet with a ?calc b? command is then issued to start the current calibration sequence. a period of t calce is observed after this packet. no request pa ckets should be issued during this period. a colx packet with a ?cale c? command is then issued to end the current calibrati on sequence. a period of t cale ? cmd is observed after this packet. no request packets sh ould be issued during this period. the first request packet may then be issued (with co mmand ?cmd d? in this example). a second current calibration sequence must be started within an interval of t calc . in this example, the next colx packet with a ?calc e? command starts a subsequent sequence. note that the labels for the cfm clock edges (of the form ti ) are not to scale, and are us ed to identify events in the diagram. the dynamic termination calibration sequ ence is shown in the lower diagram. note that this memory component does not use this sequence; terminatio n calibration is performed during the manufacturing process. however, the termination sequence shown will be issu ed by the controller for those memory components which do use a periodic calibration mechanism. it begins when a period of t cmd-calzc is observed after the packet at edge t 0 (with command cmda in the example). no request packets should be issued during this period. a colx packet with a calz command is then issued at edge t 3 to start the current calibration sequence. a second period of t calze is observed after this packet. no request pa ckets should be issued during this period. a colx packet with a cale command is then issued at edge t 6 to end the current calibration sequence. a third period of t cale-cmd is observed after this packet. no request packet s should be issued during this period. the first request packet may be issued at edge t 12 (with command cmdd in this example). a second current calibration sequence must be started within an interval of t calz . in this example, the next colx packet with a calz command occurs at edge t 20 . note that the labels for the cfm clock edges (of the form ti ) are not to scale, and are us ed to identify events in the diagrams. figure 45. calibration transactions cfm cfmn rq11 ?rq0 t cycle current calibration transaction cmd a calc e dq15?0 dqn15?0 packet a: any cmd packet b: calc packet c: cale cmd d calc b cale c packet d: any cmd packet e: calc t calce t cmd-calc t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 cfm cfmn rq11 ?rq0 t cycle cmd a calc e dq15?0 dqn15?0 cmd d calc b cale c t calce t cale-cmd t cycle termination calibration transaction cmd a calz e t calz cmd d calz b cale c packet e: calz packet a: any cmd packet b: calz packet c: cale packet d: any cmd t calze t cale-cmd t cale-cmd t calc t cmd-calz
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 45/76 rev 0.1 power state management figure 46 shows power state transition diagrams for th e xdr dram device. there are two power states in the xdr dram: powerdown and active. powerdown state is to be us ed in applications in whic h it is necessary to shut down the cfm/cfmn clock signals. in this state, the contents of the st orage cells of the xdr dram will be retained by an internal state machine which performs periodic refresh operations using the refb and refr control registers. the upper diagram shows the sequence needed for powerdow n entry. prior to starting the sequence, all banks of the xdr dram must be precharged so they are left in a closed state. also, all 2 3 banks must be refreshed using the current value of the refr registers, and the refr registers must not be incremented with the refi command at the end of this special set of refresh transactions . this ensures that no matter wh at value has been left in the refb register, no row of any bank will be skipped when au tomatic refresh is first started in powerdown. there may be some banks at the current row value in the refr registers that are refreshed twice during the powerdown entry process. after the last request packet (with the command cmda in the upper diagram of the figure), an interval of t cmd-pdn is observed. no request packets shou ld be issued during this period. a colx packet with the pdn command is issued af ter this interval, causing the xdr dram to enter powerdown state after an interval of t pdn-entry has elapsed (this is the parameter that should be used for calculating the power dissipation of the xdr dram). the cfm/cfmn cloc k signals may be removed a time t pdn-cfm after the colx packet with the pdn command. al so, the termination voltage supply may be removed (set to the ground reference) from the vterm pins a time t pdn-cfm after the colx packet with the pdn command. the voltage on the dq/dqn pins will follow the voltage on the vterm pins during power down entry. when the xdr dram is in powerdow n, an internal frequency source and state machine will automatically generate internal refresh transact ions. it will cycle through all 2 3 state combinations of the refb register. when the largest value is reached and the ref b value wraps around, the refr register is incremented to the next value. the refb and refr values select which bank and which row are refreshed during the next automatic refresh transaction. the lower diagram shows the sequence needed for powe rdown exit. the sequence is started with a serial broadcast write (sbw command) tranasaction using the serial bus of the xdr dram. this transaction writes the value ?00000001? to the power management (pm) register (sadr = ?00000011?) of all xdr drams connected to the serial bus. this sets the px bit of the pm register, causing the xdr d rams to return to active power state. the cfm/cfmn clock signals must be stable a time t cfm-pdn before the end of the sbw transaction. also, the termination voltage supply must be rest ored to its normal operating point (v term, drsl ) on the vterm pins a time tcfm-pdn before the end of the sbw transaction. th e voltage on the dq/dqn pins will follow the voltage on the vterm pins during power down exit. the xdr dram will enter active state after an interval of t pdn-exit has elapsed from the end of the sbw transaction (this is the parameter that should be used for calculating the power di ssipation of the xdr dram). the first request packet may be issued after an interval of t pdn ? cmd has elapsed from the end of the sbw transaction, and must contain a ?refa? command in a rowp packet . in this example, this packet is denoted with the command ?refa 1?. no other request pa ckets should be issued during this t pdn-cmd interval. all ?n? banks (in the example, n = 2 3 ) must be refreshed using the current value of the refr registers. the ?nth? refresh transaction will use a ?refi? command to increme nt the refr register (instead of a ?refr? command). this ensures that no matter what value has been left in the refb register, no row of any bank will be skipped when normal refresh is restarted in active state. there may be some bank s at the current ro w value in the refr registers that are refreshed twice during the powerdown exit process. note that during the powerdown state an internal time source keeps the device refreshed. however, during the t pdn-cmd interval, no internal refresh operations are perfor med. as a result, an additional burst of refresh transactions must be issued after the burst of ?n? transactions described above . this second burst consists of ?m? refresh transactions: m = ceiling [2 3 * 2 11 * t pdn-cmd /t ref ] where ?2 11 ? is the number of rows per bank, and ?2 3 ? is the number of banks. ever y ?nth? refresh transaction (where n = 2 3 ) will use a ?refi? command (to increment the refr register) instead of a ?refa? command.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 46/76 rev 0.1 figure 46. power state management dq15?0 dqn15?0 sc k s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 16 s 18 t cyc,sck power-up transaction rst cmd sdi (input) sdo (output) scmd ?0? ?1? ?0? 2?h0, sid[5:0] ?0? 5 4 3 2 1 0 7 sadr [7:0] 6 543210 ?0' 7 swd [7:0] 6543210 start ?1? ?1? ?0? ?0? cfm cfmn rq11 ?rq0 ?0? ...power down state no signal t cycle t cfm-pdn t pdn-exit t pdn-cmd cfm cfmn rq11 ?rq0 t cycle power down entry cmd a t pdn-cfm dq15?0 dqn15?0 transaction a: last precharge command transaction b: pdn pdn b no signal power down state? t pdn-entry t cmd-pdn cfm cfmn rq11 ?rq0 t cycle refa 1 dq15?0 dqn15?0 refp n refp n-2 refp n-1 refi n transaction n: refi transaction 1: refa transaction 2: refa transaction n-1: refa power down exit t pdn-cmd the final refa/refi command increments the refr register. refa 2
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 47/76 rev 0.1 initialization figure 47 shows the topology of the serial interface signals of a xdr dram system. the three signals rst, cmd, and sck are transmitted by the controller and are received by each xdr dram device along the bus. the signals are terminated to the vterm supply through termination co mponents at the end farthest from the controller. the sdi input of the xdr dram device furt hest from the controller is also term inated to vterm. the sdo output of each xdr dram device is transmitted to the sdi input of the next xdr dram device (in the direction of the controller). this sdo/sdi daisy-chain to pology continues to the controller, where it ends at the srd input of the controller. all the serial interface signals are low-true. all the signals use rsl signaling circuits, except for the sdo output which uses cmos signaling circuits. figure 47. serial interface systems topology figure 48 shows the initialization timing of the serial interface for the xdr dram [k] device in the system shown above. prior to initialization, the rst is held at zero. the cmd input is not used here, and should also be held at zero. note that the inputs are all sampled by the negative edge of the sck clock input. the sdi input for the xdr dram [0] device is zero, and is unknown for the remaining devices. on negative sck edge s 8 the rst input is sampled one. it is sampled one on the next four edges, and is sampled zero on edge s 12 a time t rst-10 after it was first sampled one. the state of the control registers in the xdr dram device are set to their reset values after the first edge (s 8 ) in which rst is sampled one. figure 48. initialization timi ng for xdr dram [ k ] device the sdi inputs will be samp led one within a time t rst-sdo, 11 after rst is first sampled one in all the xdr drams except for xdr dram [0 ]. xdr dram [0]?s sdi input will always be sampled zero. rst srd cmd controlle r sck rst sdi cmd xdr dram sck sdo rst sdi cmd xdr dram sck sdo rst sdi cmd xdr dram sck sdo vterm sc k t cyc,sck rst cmd t rst-10 ?0' ?0' ?0' ?0' ?1' ?1' ?1' ?1' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' sdi (input) t rst-sdo,11 sdo (output) t sdi-sdo,00 s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 16 s 18 t rst,sdi,00 = k * t cyc,sck ?x' ?x' ?x' ?x' ?x' ?1' ?1' ?1' ?1' ?1' ?1' ?1' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?x' ?x' ?x' ?x' ?x' ?1' ?1' ?1' ?1' ?1' ?1' ?1' ?1' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' ?0' power on t coreinit 0 1 0 1 0 1 0 1 0 1
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 48/76 rev 0.1 xdr dram [k] will see its rs t input sampled zero at s 12 , and will then see its sdi input sampled zero at s 16 (after sdi had previously been sample d one). this interval (measured in t cyc, sck units) will be equal to the index [k] of the xdr dram device along the serial inte rface bus. in this exam ple, k is equal to 4. this is because each xdr dram de vice will drive its sdo output zero around the sck edge a time t sdi-sdo,00 after its sdi input is sampled zero. in other words, the xdr dram [0] device will see rs t and sdi both sampled zero on the same edge s 12 (t rst-sdi, 00 will be 0 t cyc, sck units), and will drive its sdo to ze ro around the subsequent edge (s 13 ). the xdr dram [1] device will see sdi sampled zero on edge s 13 (t rst-sdi, 00 will be 1 t cyc, sck units), and will drive its sdo to zero around the subsequent edge (s 14 ). the xdr dram [2] device will see sdi sampled zero on edge s 14 (t rst-sdi, 00 will be 2 t cyc, sck units), and will drive its sdo to zero around the subsequent edge (s 15 ). this continues until the last xdr dram device drives th e srd input of the controller. each xdr dram device contains a state machine whic h measures the interval t rst ? sdi, 00 between the edges in which rst and sdi are both sampled zero, and uses this value to set the sid [5:0 ] field of the sid (serial id entification) register. this value allows directed read and wr ite transactions to be made to the individual xdr dram devices. table 9 summarizes the range of the timing parameters used for initialization by the serial interface bus. table 9. initialization timing parameters symbol parameter min max unit figure (s) t rst, 10 number of cycles between rst being sampled one and rst being sampled zero. 2 ? t cyc,sck ? t rst-sdo, 11 number of cycles between rst being sampled one and sdo being driven to one. 1 1 t cyc,sck ? t rst, sdi, 00 number of cycles between rst being sampled zero (after being sampled one for t rst, 10, min or more cycles) and sdi being sampled zero. this will be equal to the index [k] of the xdr dram device along the serial interface bus. 0 63 t cyc,sck ? t sdi-sdo, 00 number of cycles between sdi being sampled one (after rst has been sampled one for t rst, 10, min or more cycles and is then sampled zero) and sdo being driven to zero. 1 1 t cyc,sck ? t rst-sck the number of sck falling edges after the first sck falling edge in which rst is sampled one. 20 ? t cyc,sck ?
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 49/76 rev 0.1 xdr dram initialization overview [1] apply voltage to vdd, vterm and vref pins. vterm and vref coltages must be less or equal to vdd voltage at all times. wait a time interval t coreinit . power-on reset circuit in xdr dram places xdr dram into low-power state. [2] assert rst, sck, sdi and cmd to logical zero. then: - pulse sck to logical one, then to logical zero four times. - assert rst to logical one. reset circuit places xdr d ram into low-power state (identical to power-on reset). - perform remaining initializati on sequence in figure 48. [3] xdr dram has valid serial id and all registers have default values that are defined in figure 17 through figure 42. [4] perform broadcast or directed regist er writes to adjust registers which n eed a value different from their default value. [5] perform powerdown exit sequence shown in figure 46. this includes the activity from sck cycle s 0 through the final refp command. [6] perform termination current calibration. the calz/cale sequence shown in figure 45 is issued 128 times, then the calc/cale sequence is issued 128 times. after this, each sequence is issued once every t calz or t calc interval. [7] condition the xdr dram banks by performing a ref a/refi activate and refp prec harge operation to each bank eight times. this can be interleaved to save time . the row address for the activate operation will step through eight successive values of the refr registers. the sequence between cycles t 0 and t 32 in the interleaved refresh example in figure 44 could be performed eight times to satisfy this conditioning requirement.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 50/76 rev 0.1 xdr dram pattern load with wdsl register the xdr memory system requires a method of determin istically loading pattern data to xdr drams before beginning receive timing calibration (rx tcal). the me thod employed by the xdr drams to achieve this is called write data serial load (wdsl). a wdsl packet sends one-byte of serial data which is serially shifted into a holding register within the xdr dram. initialization software sends a sequen ce of wdsl packets, each of which shifts the new byte in and advances the shifter by 8 posi tions. in this way, xdr drams of varying widths can be loaded with a single command type. each sequence of wdsl packets will load one full column of data to the inte rnal holding register of the target xdr dram. depending upon the ratio of native device wi dth to programmed width, there may be more than one sub-column per column. after loading a full column, a se ries of wr commands will be issued to sequentially transfer each sub-column of the column to the xdr dram core (s), based upon the sc [3:0] bits. table 10. wdsl-to-core/dq/sc map (first generation 16/ 8/ 4 xdr dram, bl = 16) logical view of xdr dram word written (1 = written, 0 = not written) dq pin used wdsl core word load order 16 8 4 4 8 16 core word wd [n] [15:0] sc[3:2] = xx sc[3:2] = 0x sc[3:2] = 1x sc[3:2] = 00 sc[3:2] = 01 sc[3:2] = 10 sc[3:2] = 11 dq0 dq0 dq0 wd [0] [15:0] wdsl word 8 1 1 0 1 0 0 0 dq1 dq1 dq1 wd [1] [15:0] wdsl word 7 1 1 0 1 0 0 0 dq2 dq2 dq2 wd [2] [15:0] wdsl word 12 1 1 0 1 0 0 0 dq3 dq3 dq3 wd [3] [15:0] wdsl word 3 1 1 0 1 0 0 0 dq0 dq4 dq4 wd [4] [15:0] wdsl word 10 1 1 0 0 1 0 0 dq1 dq5 dq5 wd [5] [15:0] wdsl word 5 1 1 0 0 1 0 0 dq2 dq6 dq6 wd [6] [15:0] wdsl word 14 1 1 0 0 1 0 0 dq3 dq7 dq7 wd [7] [15:0] wdsl word 1 1 1 0 0 1 0 0 dq0 dq0 dq8 wd [8] [15:0] wdsl word 9 1 0 1 0 0 1 0 dq1 dq1 dq9 wd [9] [15:0] wdsl word 6 1 0 1 0 0 1 0 dq2 dq2 dq10 wd [10] [15:0] wdsl word 13 1 0 1 0 0 1 0 dq3 dq3 dq11 wd [11] [15:0] wdsl word 2 1 0 1 0 0 1 0 dq0 dq4 dq12 wd [12] [15:0] wdsl word 11 1 0 1 0 0 0 1 dq1 dq5 dq13 wd [13] [15:0] wdsl word 4 1 0 1 0 0 0 1 dq2 dq6 dq14 wd [14] [15:0] wdsl word 15 1 0 1 0 0 0 1 dq3 dq7 dq15 wd [15] [15:0] wdsl word 0 1 0 1 0 0 0 1 physical view of xdr dram word written (1 = written, 0 = not written) dq14 wd [14] [15:0] wdsl word 15 1 0 1 0 0 0 1 dq6 dq6 wd [6] [15:0] wdsl word 14 1 1 0 0 1 0 0 dq10 wd [10] [15:0] wdsl word 13 1 0 1 0 0 1 0 dq2 dq2 dq2 wd [2] [15:0] wdsl word 12 1 1 0 1 0 0 0 dq12 wd [12] [15:0] wdsl word 11 1 0 1 0 0 0 1 dq4 dq4 wd [4] [15:0] wdsl word 10 1 1 0 0 1 0 0 dq8 wd [8] [15:0] wdsl word 9 1 0 1 0 0 1 0 dq0 dq0 dq0 wd [0] [15:0] wdsl word 8 1 1 0 1 0 0 0 dq3 wd [1] [15:0] wdsl word 7 1 1 0 1 0 0 0 dq3 dq11 wd [9] [15:0] wdsl word 6 1 0 1 0 0 1 0 dq7 wd [5] [15:0] wdsl word 5 1 1 0 0 1 0 0 dq1 dq7 dq15 wd [13] [15:0] wdsl word 4 1 0 1 0 0 0 1 dq3 wd [3] [15:0] wdsl word 3 1 1 0 1 0 0 0 dq3 dq11 wd [11] [15:0] wdsl word 2 1 0 1 0 0 1 0 dq7 wd [7] [15:0] wdsl word 1 1 1 0 0 1 0 0 dq3 dq7 dq15 wd [15] [15:0] wdsl word 0 1 0 1 0 0 0 1
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 51/76 rev 0.1 table 11. core data word-to wdsl format a dq serialization order cfm/pclk cycle cycle 0 cycle 1 symbol (bit) time t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 bit transmitted on dq pins d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 wdsl byte/bit transfer order core word core word wd [n] [15:0] wdsl word wdsl word n wdsl byte order wdsl byte 0 wdsl byte 1 swd field of serial packet 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 bit transmitted on cmd pin d15 d11 d7 d3 d14 d10 d6 d2 d13 d9 d5 d1 d12 d8 d4 d0
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 52/76 rev 0.1 special feature description dynamic width control this xdr dram device includes a feature called dynamic width control. this permits the device to be configured so that read and write data can be accessed through diff ering widths of dq pins. figure 46 shows a diagram of the logic in the path of the read data (q) and write data (d) that accomplishes this. the read path is on the right of the figure. there are 16 sets of s signals (the internal data bus connecting to the sense amps of the memory core), with 16 signals in ea ch set. when the xdr dram device is configured for maximum width operation (using the width [2:0] field in the cfg register), each set of 16 s signals goes to one of the 16 dq pins (via the q [15:0] [15:0] read bus) and are driven out in the 16 time slots for a read data packet. when the xdr dram device is configured for a width that is less than the maximum, some of the dq pins are used and the rest are not used. the sc [3:0] field of the col request packets selects which s [15:0] [15:0] signals are passed to the q [15:0] [15:0] read bus and driven as read data. figure 50 shows the mapping from the s bus to the q bus as a function of the width [2:0] register field and the sc [3:0] field of the col request packet . there is a separate table for each valid value of width [2:0]. in each table, there is an entry in the left co lumn for each valid value of sc [3:0]. this field should be treated as an extension of the c [9:4] column address field. the right hand column shows which sets of s [15:0] [15:0] signals are mapped to the q read data bus for a particular value of sc [3:0]. for example, assume that the width [2:0] value is ?010?, indicating a device width of x4. looking at the appropriate table in figure 47, it may be seen that in th e sc [3:0] field, the sc [1:0 ] sub-column address bits are not used. the remaining sc [3:0] address bit(s) selects one of the 64-bit blocks of s bus signals, causing them to be driven onto the q [3:0] [15:0] read data bus, which in turn is driven to the dq3?dq0/dqn3?dqn0 data pins. the q [15:4] [15:0] signals and dq15?dq4/dqn15...dqn4 da ta pins are not used for a device width of x4. the write path is shown on the left side of figure 46. as before, there are 16 sets of s signals (the internal data bus connecting to the sense amps of the memory core), with 16 signals in each set. when the xdr dram device is configured for maximum width operation (using the width [2 :0] field in the cfg register), each set of 16 s signals is driven from one of the 16 dq pins (v ia the d [15:0] [15:0] write bus) from each of the 16 time slots for a write data packet. figure 50 also shows the mapping from the d bus to the s bus as a function of the width [2:0] register field and the sc [3:0] field of the col request packet. there is a sepa rate table for each valid valu e of width [2:0]. in each table, there is an entry in the left co lumn for each valid value of sc [3:0]. this field should be treated as an extension of the c [9:4] column address field. the right hand column shows which set of s [15:0] [15:0] signals are mapped from the d read data bus for a particular value of sc [3:0]. for example, assume that the width [2:0] value is ?001?, indicating a device width of x2. looking at the appropriate table in figure 47, it may be seen that in th e sc [3:0] field, the sc [0] sub-column address bit is not used. the remaining sc [3:0] address bit(s) selects one of the 32-bit blocks of s bus signals, causing them to be driven from the d [1:0] [15:0] write data bus, which in turn is driven from the dq1?dq0/dqn1 ...dqn0 data pins. the d [15:2] [15:0] signals and dq15?dq2/dqn15?dqn2 da ta pins are not used for a device width of x2. figure 49. multiplexes for dynamic width control m [ 7 : 0 ] 8 byte mask (wr) width [2 : 0] sc [3 : 0] 4+3 dynamic width demux (wr) 16x16 16x16 d1 [ 15:0 ] [ 15:0 ] 16x16 d [ 15:0 ] [ 15:0 ] dynamic width mux (rd) 16x16 q [ 15:0 ] [ 15:0 ] 16x16 width [2 : 0] sc [3 : 0] s [ 15:0 ] [ 15:0 ] 4+3
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 53/76 rev 0.1 the block diagram in figure 49 indicates that the dynamic width logic is positioned after the serial-to-parallel conversion (demux block) in the data receiver block and before the parallel-to -serial conversion (mux block) in the data transmitter block (see the block diagram in figure 2 also). the block diagram is shown in this manner so the functionality of the logic can be made as clear as possibl e. some implementations may place this logic in the data receiver and transmitter blocks, performing the mapping in figure 50 on the serial data rather than the parallel data. however, this design choice will not affect the func tionality of the dynamic width logic; it is strictly an implementation decision. figure 50. d-to-s and s-to-q mapping for dynamic width control width [2:0] = 000 ( 1 device width) width [2:0] = 001 ( 2 device width) width [2:0] = 011 ( 8 device width) s [0] [15:0] 0000 s [1] [15:0] 0001 s [2] [15:0] 0010 s [3] [15:0] 0011 s [4] [15:0] 0100 s [5] [15:0] 0101 s [6] [15:0] 0110 s [7] [15:0] 0111 s [8] [15:0] 1000 s [9] [15:0] 1001 s [10] [15:0] 1010 s [11] [15:0] 1011 s [12] [15:0] 1100 s [13] [15:0] 1101 s [14] [15:0] 1110 s [15] [15:0] 1111 d [0] [15:0] q [0] [15:0] sc [3:0] width [2:0] = 010 ( 4 device width) width [2:0] = 100 ( 16 device width) s [7:0] [15:0] 0xxx s [15:8] [15:0] 1xxx d [7:0] [15:0] q [7:0] [15:0] sc [3:0] s [3:0] [15:0] 00xx s [7:4] [15:0] 01xx s [11:8] [15:0] 10xx s [15:12] [15:0] 11xx d [3:0] [15:0] q [3:0] [15:0] sc [3:0] s [15:0] [15:0] xxxx d [15:0] [15:0] q [15:0] [15:0] sc [3:0] s [1:0] [15:0] s [3:2] [15:0] s [5:4] [15:0] s [7:6] [15:0] s [9:8] [15:0] s [11:10] [15:0] s [13:12] [15:0] s [15:14] [15:0] d [1:0] [15:0] q [1:0] [15:0] 000x 001x 010x 011x 100x 101x 110x 111x sc [3:0]
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 54/76 rev 0.1 write masking figure 51 shows the logic used by the xdr dram device when a write-masked comman d (wrm) is specified in a colm packet. this masking logic permit s individual bytes of a write data packet to be written or not written according to the value of an eight bit write mask m [7:0]. in figure 51, there are 16 sets of 16 bit signals forming th e d1 [15:0] [15:0] input bus for the byte mask block. these are treated as 2x16 8-bit bytes: d1 [15] [15:8] d1 [15] [7:0] ... d1 [1] [15:8] d1 [1] [7:0] d1 [0] [15:8] d1 [0] [7:0] the eight bits of each byte is compared to the value in the byte mask field (m [7:0]). if they are not equal (ne), then the corresponding write enable signal (we) is asserted and the byte is written into the sense amplifier. if they are equal, then the corresponding write enable signal (we) is deserted and the byte is not written into the sense amplifier. in the example of figure 52, a wrm command performs a masked write of a 64-byte data packet to all the memory devices connected to the rq bus (and receiving th e command). it is the job of the memory controller to search the 64-bytes to find an eight bi t data value that is not used and plac e it into the m [7:0] field. this will always be possible because there are 256 possible 8-bit values and there are only 64 possible values used in the bytes in the data packet. figure 51. byte mask logic m [7:0] 8 byte mask (wr) 16x16 16x16 d1 [15:0] [15:0] dynamic width demux (wr) 16x16 d [15:0] [15:0] dynamic width mux (rd) 16x16 q [15:0] [15:0] 16x16 s [15:0] [15:0] 4+3 width [2:0] sc [3:0] width [2:0] sc [3:0] 4+3 ne compare s [15] [15:8] [15] d1 [15] [15:8] 8 m [7:0] 8 d1 [15] [15:8] 8 1 8 ne compare s [15] [7:0] 8 8 8 1 d1 [15] [7:0] 8 8 8 d1 [15] [7:0] ne compare s [0] [15:8] d1 [0] [15:8] 8 8 d1 [0] [15:8] 8 1 8 ne compare s [0] [7:0] 8 8 8 1 d1 [0] [7:0] 8 8 8 d1 [0] [7:0] we-msb [15] we-lsb [0] we-msb [0] we-lsb
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 55/76 rev 0.1 note that other systems might use a data transfer size that is different than the 64 bytes per t cc interval per rq bus that is used in the example in figure 51. figure 52 shows the timing of two successive wrm commands in colm packets. the timing is identical to that of two successive wr commands in col packets. the one differe nce is that the colm packet includes a m [7:0] field that indicates the reserved bit pattern (for the eight bits of each byte) that indicates that the byte is not to be written. this requires that the alignment of bytes with in the data packet be defined, and also that the bit numbering within each byte be defined (note that this was not necessary for the unmasked wr command). in the figure, bytes are contained within a single dq/dqn pin pair - this is necessary so the dynamic width feature can be supported. thus, each pin pair carries two bytes of each data packet. byte [0] is transferred earlier than byte [1], and bit [0] of each byte (corresponding to m [0]) is transferred first, followe d by the remaining bits in succession). figure 52. write-masked (wrm) transaction example t cwd cfm cfmn rq11 ?rq0 t cycle wrm a2 wrm a1 t cc t cac rd a1 dq15?0 dqn15?0 bit-and byte-numbering convention for write and read data p ackets. dq0 dqn0 dq1 dqn1 [1] [2] [3] [4] [5] [6] [7] [8] [9 ] [10] [11] [12] [ 13] [14] [15] [0] byte [0] byte [16+0] [1] [2] [3] [4] [5] [6] [7] [8] [9 ] [10] [11] [12] [ 13] [14] [15] [0] byte [1] byte [16+1] dq15 dqn15 [1] [2] [3] [4] [5] [6] [7] [8] [9 ] [10] [11] [12] [ 13] [14] [15] [0] byte [15] byte [16+15] t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 d(a1) d(a2) q(a1)
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 56/76 rev 0.1 multiple bank sets and the eraw feature figure 55 shows a block diagram of a xdr dram in which the banks are divided into two sets (called the even bank set and the odd bank set) according to the least sign ificant bit of the bank address field. this xdr dram supports a feature called ?early read af ter write? (hereafter called ?eraw?). the logic that accepts commands on the rq11?rq0 sign als is capable of operating these two bank sets independently. in addition, each bank set connects to its ow n internal ?s? data bus (called s0 and s1). the receive interface is able to drive write data on to either of these internal data buses, and the transmit interface is able to sample read data from either of these internal data bu ses. these capabilities will perm it the delay between a write column operation and a read column operation to be reduced, thereby improving performance. figure 50 shows the timing previously presented in figure 12, but with the activity on the internal s data bus included. the write-to-read parameter t ? wr ensures that there is adequate tu rnaround time on the s bus between d (a2) and q (c1). when eraw is supported with odd and even bank sets, the t ? wr, min parameter must be obeyed when the write and read column operations are to the same bank set, but a second parameter t ? wr-d permits earlier column operations to the opposite bank set. figure 51 shows how this is possible because there are two internal data buses s0 and s1. in this example, the four columns read operations are made to the same bank bb, but they could use different banks as long as they all belonged to the bank set that was different from the bank set containing ba (for the column write operations). figure 53. write/read interaction ? no eraw feature figure 54. write/read interaction ? eraw feature cfm cfmn dq15?0 dqn15?0 rq11 ?rq0 transaction a: wr a1 = = ? wr rd c1 rd c2 t cac q(c1) q(c2) t cc q(c2) q(c1) turnaround d(a2) d(a1) t cwd d(a1) d(a2) t cc dq gap transaction c: rd c1 = = = = ? wr-d rd b4 rd c1 t cac q(b3) q(b4) t cc q(c1) turnaround d(a2) d(a1) t cwd t cc transaction b: rd b1 = = = {bb, cb3} transaction c: rd c1 = = bank restrictions bb is in different bank set than ba be is in same bank set as ba wr a2 dq gap d(a2) d(a1) q(b4)
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 57/76 rev 0.1 figure 55. xdr dram block diagram with bank sets 1:2 demux col decode reg byte mask (wr) 12 rq11...rq0 act decode pre decode 6 3 3 12 3 1 ba,br,refb bank (2 3 -1) 16x16*2 6 16x16*2 6 16x16 16x16 dynamic width demux (wr) 16x16 q[15:0] [15:0] s0[15:0] [15:0] 16:1 mux 16/t cc 16 1:16 demux 16 16 16 16/t cc 16 16 16x16 d[15:0] [15:0] dq15?dq0 dqn15?dqn0 even bank array 16x16*2 6 *2 12 bank 0 a ct row pre a ct row 1 12 12 pre sense amp array 16x16*2 6 sense amp 0 r/w col r/w col sense amp (2 3 -2) 1 1 6 6 act row pre odd bank array 16x16*2 6 *2 12 act row pre act logic pre logic 1 1 12 12 1 1 sense amp array 16x16*2 6 r/w col r/w col 1 1 6 6 col logic 16x16*2 6 16x16*2 6 sense amp (2 3 -1) sense amp 1 16x16 16x16 s1[15:0] [15:0] wr even wr odd rd even rd odd 16x16 16x16 dynamic width mux (rd) bank 1 bank (2 3 -2) bank (2 3 -1)
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 58/76 rev 0.1 simultaneous precharge when the xdr dram supports multiple bank sets as in figure 55, another feature may be supported, in addition to eraw. this feature is simu ltaneous precharge, and the timing of several cases is shown in figure 56. the t pp parameter specifies the minimum spacing between packets with precharge commands in xdr drams with a single bank set, or between packets to the same bank set in a xdr dram with multiple bank sets. the t pp-d parameter specifies the minimum spacing between pack ets with precharge commands to different bank sets in a xdr dram with multiple bank sets. in figure 56, case 4 shows an example when both t pp and t pp-d must be at least 4 t cycle . in such a case, precharge commands to different bank sets satisfy the sa me constraint as precharge commands to the same bank set. in figure 56, case 2 shows an example when t pp must be at least 4 t cycle and t pp-d must be at least 2 t cycle . in such a case, a precharge command to one bank set may be inserted between two precharge commands to a different bank set. in figure 56, case 1 shows an example when t pp must be at least 4 t cycle and t pp-d must be at least 1 t cycle . as in the previous case, a precharge command to one bank set may be insert ed between two precharge commands to a different bank set. in this case, the mi ddle precharge command will no t be symmetrically placed relative to the two outer precharge commands. in figure 56, case 0 shows an example when t pp must be at least 4 t cycle and t pp-d must be at least 0 t cycle . this means that two precharge commands may be i ssued on the same cfm clock edge. this is only possible by using the delay mechanism in one of the two commands. see ?dynam ic request scheduling? on page 20. it is also possible by taking advantage of the fact that two independent precharg e commands may be encoded within a single rowp packet. in the example shown, the rowp packet contains both a refp command and a pre command. both precharge commands will be issued inte rnally to different bank sets on the same cfm clock edge. figure 56. simultaneous precharge ? t pp-d cases dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle t pp-d t pp-d cfm cfmn pre pre case 4: t pp-d = 4*t cycle refp & pre have same t rr. pre refp t pp-d pre refp t pp case 2: t pp-d = 2*t cycle refp fits between two pre note ? refp is directed to ban k set different from two pre dq15?0 dqn15?0 rq11 ?rq0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 0 t 20 t 21 t 22 t 23 t cycle t pp-d cfm cfmn case 1: t pp-d = 1*t cycle refp fits between two pre pre refp t pp pre refp t pp case 0: t pp-d = 0*t cycle refp simultaneous with pre note ? refp is directed to ban k set different from pre at t 12 t pp-d pre pre note ? refp is directed to ban k set different from two pre
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 59/76 rev 0.1 operating conditions electrical conditions table 12 summarizes all electrical conditions (temperatu re and voltage conditions) that may be applied to the memory component. the first section of parameters is concerned with absolute volt ages, storage and operating temperatures, and the power supply, reference, and termination voltages. the second section of parameters determines the input vo ltage levels for the rsl rq signals. the high and low voltages must satisfy a symmetry parameter with respect to the v ref, rsl . the third section of parameters determin es the input voltage levels for the rs l si (serial interface) signals. the high and low voltages must satisfy a sy mmetry parameter with respect to the v ref, rsl . the fourth section of parameters determines the input vo ltage levels for the cfm clock signals. the high and low voltages are specified by a common-mode value and a swing value. the fifth section of parameters determines the input vo ltage levels for the write data signals on the drsl dq pins. the high and low voltages are specified by a common-mode value and a swing value. table 12. electrical conditions symbol parameter min max unit v in, abs voltage applied to any pin (except v dd ) with respect to gnd ? 0.300 1.500 v v dd , abs voltage on v dd with respect to gnd ? 0.500 2.300 v t store storage temperature ? 50 100 c t j junction temperature under bias during normal operation manufacturer-specific values c v dd supply voltage applied to v dd pins during normal operation 1.80 ? 0.060 1.80 + 0.060 v v ref,rsl rsl ? reference voltage applied to v ref pin a v term,rsl ? 0.450 ? 0.025 v term,rsl ? 0.450 + 0.025 v v term,drsl rsl ? termination voltage applied to v term pins 1.200 ? 0.060 1.200 + 0.060 v v il,rq rsl rq inputs ? low voltage v ref,rsl ? 0.450 v ref,rsl ? 0.150 ? high voltage v ref,rsl + 0.150 v ref,rsl + 0.450 ? data asymmetry: r a,rq = (v ih,rq ? v ref,rsl ) / (v ref,rsl ? v il,rq ) tbd tbd v v il,si rsl serial interface inputs ? low voltage v ref,rsl ? 0.450 v ref,rsl ? 0.200 v v ih,si b rsl serial interface inputs ? high voltage v ref,rsl + 0.200 v ref,rsl + 0.450 v r a,si rsl rq inputs ? data asymmetry: r a, si = (v ih,rq ? v ref,rsl ) / (v ref,rsl ? v il,rq ) tbd tbd v v icm,cfm cfm/cfmn input ? common mode: v icm, cfm = (v ih,cfm b + v il,cfm )/2 v term,drsl ? 0.150 v term,drsl ? 0.075 v v isw,cfm cfm/cfmn input ? high-low swing: v isw, cfm = (v ih,cfm b ? v il,cfm ) 0.150 0.300 v v icm,dq drsl dq inputs ? common mode: v icm, dq = (v ih,dq b + v il,dq )/2 v term,drsl ? 0.150 v term,drsl ? 0.025 v v isw,dq drsl dq inputs ? high-low swing: v isw, dq = (v ih,dq b ? v il,dq ) 0.050 0.300 v a v term,drsl is typically 1.2000 v 0.060 v. it connects to the rsl termination components, not to this dram component. b v ih is typically equal to v term,rsl or v term,drsl (whichever is appropriate) und er dc conditions in an system.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 60/76 rev 0.1 timing conditions table 13 summarizes all timing conditions that may be applied to the memory component. the first section of parameters is concerned with parameters for the clock sign als. the second section of parameters is concerned with parameters for the request signals. the third section of pa rameters is concerned with parameters for the write data signals. the fourth section of parameters is concerned with parameters for the serial interface signals. the fifth section is concerned with all other parameters, including those for refresh, calibration, power state transitions, and initialization table 13. timing conditions symbol parameter min max units figure (s) ? 4000 2.000 3.830 ? 3200 2.500 3.830 t cycle or t cyc,cfm cfm rsl clock - cycle time ? 2400 3.333 3.830 ns figure 58 t r, cfm , t f, cfm cfm/cfmn input - rise and fall time - use minimum for test. 0.080 0.200 t cycle figure 58 t h, cfm , t l, cfm cfm/cfmn input ? high and low times 40% 60% t cycle figure 58 t r, rq , t f, rq rsl rq input - rise/fall times (20% - 80%) - use minimum for test. 0.080 0.260 t cycle figure 59 @ 2.500 ns > t cycle 2.000 ns tbd ? @ 3.333 ns > t cycle 2.500 ns 0.200 ? t s, rq , t h, rq rsl rq input to sample points (set/hold) @ 3.830 ns t cycle 3.333 ns tbd ? ns figure 59 t ir, dq , t if, dq drsl dq input - rise/fall times (20% - 80%) - use minimum for test. 0.020 0.074 t cycle figure 60 @ 2.500 ns > t cycle 2.000 ns tbd ? @ 3.333 ns > t cycle 2.500 ns 0.0625 ? t s, dq , t h, dq drsl dq input to sample points (set/hold) @ 3.830 ns t cycle 3.333 ns tbd ? ns figure 60 t doff, dq drsl dq input delay offset (fixed) to sample points ? 0.080 0.080 t cycle figure 60 t cyc, sck serial interface sck input - cycle time 20 ? ns figure 62 t r, sck , t f, sck serial interface sck input - rise and fall times ? 5.0 ns figure 62 t h, sck , t l, sck serial interface sck input - high and low times 40% 60% t cycle figure 62 t ir, si, t if, si serial interface cmd, rst, sdi input - rise and fall times ? 5.0 ns figure 62 t s, si , t h, si serial interface cmd, sdi input to sck clock edge - set/hold time 5 ? ns figure 62 t dly, si-rq delay from last sck clock edge for register write to first cfm edge with rq packet. also, delay from first cfm edge with rq packet to the first sck clock edge for register operation. 10 ? t cycle ? t ref refresh interval. every row of every bank must be accessed at least once in this interval with a row-act, rowp-ref or rowp-refi command. ? 16 ms figure 44 t refa-refa,avg average refresh command interval. rowp-refa or rowp-refi commands must be issued at this average rate. this depends upon t ref and the number of banks and the number of rows: t refi = t ref /(n b *n r ) = t ref /(2 3 *2 12 ). t refa-refa,avg =488 ns ? n refa, burst refresh burst limit. the number of rowp-refa or rowp-refi commands which can be issued c onsecutively at the minimum command spacing. ? 128 commands ? t burst-refa refresh burst interval. the interval between a burst of n refa,burst,max rowp-refa or rowp-refi commands and the next rowp-refa or rowp-refi command. ? tbd t cycle ? t coreinit interval needed for one initialization after power is applied. ? 1.500 ms ? t calc current calibration interval ? 100 ms figure 45 w/ pre or refp command 4 ? t cmd-calc t cmd-calz delay between packet with any command and calc packet w/ any other command 16 ? t cycle figure 45 t calce , t calze delay between calc/calz packet and cale packet 12 ? t cycle figure 45 t cale-cmd delay between cale packet and packet with any command 24 ? t cycle figure 45 t cmd-pdn last command before pdn entry 16 ? t cycle figure 46 t pdn-cfm rsl cfm/cfmn stable after pdn entry 16 ? t cycle figure 46 t cfm-pdn rsl cfm/cfmn stable before pdn exit 16 ? t cycle figure 46 t pdn-cmd first command after pdn exit (includes lock time for cfm/cfmn) 4096 ? t cycle figure 46
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 61/76 rev 0.1 operating characteristics electrical characteristics table 14 summarizes all electrical parameters (temperature, current and voltage) that characterize this memory component. the only exception is the supply current values (i dd ) under different operating conditions covered in the supply current profile section. the first section of parameters is concerned with th e thermal characteristics of the memory component. the second section of parameters is concerned with the current need ed by the rq pins and vref pin. the third section of parameters is concerned with the curr ent needed by the dq pins and voltage levels produced by the dq pins when driving read data. this section is also concerned with the current needed by the vterm pin, and with the resistance levels produc ed for the internal termination compon ents that attach to the dq pins. the fourth section of parameters determines the output voltage levels and the current needed for the serial interface signals table 14. electrical characteristics symbol parameter min max unit jc junction-to-case thermal resistance m anufacturer-specific values c/watt i i, rsl rsl rq or serial interface input current @ (0 v in v dd ) ? 10 10 a i ref, rsl v ref, rsl current @ v ref, rsl, max flowing into vref pin ? 10 10 a odf = 00 0.225 0.350 odf = 01 tbd tbd odf = 10 tbd tbd v osw,dq drsl dq outputs ? high-low swing; v osw,dq = (v ih,dq ? v il,dqn ) or (v ih,dqn ? v il,dq ) (see figure 27) odf = 11 tbd tbd v r term,dq drsl dq outputs ? termination resistance 40.0 60.0 ? v ol, si rsl serial interface sdo output ? low voltage 0.0 v ref, rsl ? tbd v v oh, si rsl serial interface sdo output ? high voltage v ref, rsl + tbd v term, rsl v
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 62/76 rev 0.1 supply current profile in this section, table 15 summarizes the supply current (i dd ) that characterizes this memory component. this parameter is shown under different operating conditions. table 15. supply current profile symbol parameter min @t cycle = 2.00ns max @t cycle = 2.50ns max @t cycle = 3.33ns unit i dd, pdn device in pdn, self refresh enabled tbd tbd tbd a i dd, stby device in stby. this is for a device in stby with no packets on the channel. tbd tbd tbd ma i dd, ref device in stby and refreshing rows at the t ref,max period. tbd tbd tbd ma i dd, wr act command every t rr , pre command every t pp , wr command every t cc . tbd tbd tbd ma i dd, rd act command every t rr , pre command every t pp , rd command every t cc a . tbd tbd tbd ma i term,drsl,none no rd nor wr commands issued. c tbd tbd tbd ma i term,drsl,rd rd command every t cc c tbd tbd tbd ma i term,drsl,wr wr command every t cc c tbd tbd tbd ma a. i dd current @ v dd,max flowing into vdd pins. b. this does not include the i ol,dq sink current. the device dissipates i ol,dq *v term,dq in each dq/dqn pair when driving data. c. i term,drsl current @ v term,dq,max flowing into vterm pins. timing characteristics table 16 summarizes all timing parameters that characte rize this memory component. the only exceptions are the core timing parameters that ar e speed-bin dependent. refer to the timing parameters section for more information. the first section of parameters pertains to the timing of the dq pins when driving read data. the second section of parameters is concerned with th e timing for the serial inte rface signals when driving register read data. the third section of parameters is concerned with the time intervals needed by the inte rface to transition between power states. table 16. timing characteristics symbol parameter and other conditions min max unit figure (s) @ 2.500 ns > t cycle 2.000 ns tbd tbd @ 3.333 ns > t cycle 2.500 ns ? 0.0625 + 0.0625 t q, dq drsl dq output delay (variation across 16 q bits on each dq pin) from drive points ? output delay @ 3.830 ns t cycle 3.333 ns tbd tbd ns figure 61 t qoff, dq drsl dq output delay offset (a fixed value for all 16 q bits on each dq pin) from drive points ? output delay ? 0.080 + 0.080 t cycle figure 61 t or, dq , t of, dq drsl dq output ? rise and fall times (20 % ? 80 % ) 0.020 0.040 t cycle figure 61 t q, si serial sck-to-sdo output delay @ c load, max = 20 pf 2 12 ns figure 63 t p, si serial sdi-to-sdo propagation delay @ c load, max = 20 pf ? 15 ns figure 63 t or, si , t of, si serial sdo output rise/fall (20 % ? 80 % ) @ c load, max = 20 pf ? 5 ns figure 63 t pdn-entry time for power state to change after pdn entry ? 16 t cycle figure 46 t pdn-exit time for power state to change after pdn exit 0 ? t cycle figure 46
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 63/76 rev 0.1 timing parameters table 17 summarizes the timing parameters that characte rize the core logic of this memory component. these timing parameters will vary as a functi on of the component?s speed bin. the four sections deal with the timing intervals between packets with, respectively, row-row commands, row-column commands, column-column commands, and column-row commands. table 17. timing parameters symbol parameter and other conditions min (a) min (b) min (c) unit figure(s) t rc 16 20 24 t rc-r,2tcc = t rcd-r + t cc + t rdp + t rp a 16 20 24 t rc-r,2tcc,noeraw = t rcd-w + t cc + t wrp + t rp a 19 24 24 t rc row-cycle time: interval between successive rowa-act or rowp-refa or rowp-refi activate commands to the same bank. t rc-w,2tcc, eraw = t rcd-w + t cc + t wrp + t rp a 23 28 28 t cycle 4, 7 t ras row-asserted time: interval between a rowa-act or rowp-refa or rowp-refi activate command and a rowp-pre or rowp-refp precharge command to the same bank. 10 13 17 t cycle 4, 7 t rp row-precharge time: interval between a rowp-pre or rowp-refp precharge command and a rowa-act or rowp-refa or rowp-refi activate command to the same bank. 6 7 7 t cycle 4, 7 t pp 4 4 4 t cycle t pp precharge-to-precharge time: interval between successive rowp-pre or rowp-refp precharge commands to different banks. t pp-d b 1 1 1 t cycle 4, 7 t rr 4 4 4 t cycle t rr row-to-row time: interval between rowa-act or rowp-refa or rowp-refi activate commands to different banks. t rr-d c 4 4 4 t cycle 4, 7 t rcd-r row-to-column-read delay: interval between a rowa-act activate command and a col-rd read command to the same bank. 5 7 7 t cycle 4, 7 t rcd-w row-to-column-write delay: interval between a rowa-act activate command and a col-wr or col-wrm write command to the same bank. 1 3 3 t cycle 4, 7 t cac column access delay: interval from col-rd read command to q read data 6 7 7 t cycle 10 t cwd column write delay: interval from a col-wr or colm-wrm write command to d write data. 3 3 3 t cycle 9 t cc column-to-column time: interval between successive col-rd commands, or between successive col-wr or colm-wrm commands. 2 2 2 t cycle 4, 7 t rw-bub, xdrdram read-to-write bubble time: interval between the end of a q read data packet and the start of d write data packet (the end of a data packet is the time interval t cc after its start). 3 3 3 t cycle 13 t wr-bub, xdrdram write-to-read bubble time: interval between the end of a d write data packet and the start of q read data packet (the end of a data packet is the time interval t cc after its start). 3 3 3 t cycle 13 t ? rw read-to-write time: interval between a col-rd read command and a col-wr or colm-wrm write command. d 8 9 9 t cycle 12 t ? wr 9 10 10 t cycle t ? wr write-to-read time: interval between a col-wr or colm-wrm write command and a col-rd read command. t ? wr?d e 2 2 2 t cycle 12
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 64/76 rev 0.1 table 17. timing parameters (continued) symbol parameter and other conditions min (a) min (b) min (c) unit figure(s) t rdp read-to-precharge time: interval between a col-rd read command and a rowp-pre precharge command to the same bank. 3 4 4 t cycle 4, 7 t wrp write-to-precharge time: interval between a col-wr or colm-wrm write command and a rowp-pre precharge command to the same bank. 10 12 12 t cycle 4, 7 t dr data-to-read time : interval between a d write data and a col-rd read command to the same bank. 6 7 7 t cycle 12, 13 t dp data-to-precharge time : interval between a d write data and a rowp-pre precharge command to the same bank. 7 9 9 t cycle 9 t lrrn-lrrn interval between rowp-lrrn command and a subsequent rowp-lrrn command. f 16 20 24 t cycle table 4 t refx-lrrn interval between rowp-refx command and a subsequent rowp-lrrn command. 16 20 24 t cycle table 4 t refx-lrrx interval between rowp-lrrn command and a subsequent rowp-refx command. 16 20 24 t cycle table 4 a. the t rc,min parameter is applicable to all transaction types (read, wr ite, refresh, etc). read and write transactions may have an additional limitation, depending upon how many column accesses (each requiring t cc ) are performed in each row access (t rc ). the table lists the special cases (t rc-r, 2tcc , t rc-w, 2tcc, noeraw , t rc-w, 2tcc, eraw ) in which two column accesses are performed in each row access. note that t rc-w, 2tcc, eraw uses a relaxed value of t rcd-w that is equal to t rcd-r,min . all other parameters are minimum. b. t pp-d is the t pp parameter for precharges to different bank sets. see ?simultaneous precharge? on page 55. c. t rr-d is the t rr parameter for aceivates to different bank sets. see ?simultaneous precharge? on page 56. d. see ?propagation delay? on page 30. e. t ? wr-d is the t ? wr parameter for write-read accesses to different bank se ts. see ?multiple bank sets and the eraw feature? on page 53. also, note that the value of t ? wr-d may not take on the values {3,5,7} within the range{t ? wr-d,min , ... t ? wr,min-1 }. t ? wr-d may assume any value t ? wr,min . f. rowp-lrrn includes the commands {rowp-lrr0, rowp-lrr1, rowp-lrr2} rowp-refx inclues the commands {row p-refa, rowp-ref1, rowp-refp}.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 65/76 rev 0.1 receive/transmit timing clocking figure 57 shows a timing diagram for the cfm/cfmn cl ock pins of the memory component. this diagram represents a magnified view of these pins. this diagram shows on ly one clock cycle. cfm and cfmn are differential signals: one signal is th e complement of the other. they are also high-true signals ? a low voltage represents a logical zero and a high voltage represents a logica l one. there are two crossing points in each clock cycle. the prim ary crossing point includes the high ? voltage ? to ? low ? voltage transition of cfm (indicated with the arrowhead in the diagram) . the secondary crossing point includes the low ? voltage ? to ? high ? voltage transition of cfm. all timing events on the rsl signals are referenced to the first set of edges. timing events are measured to and from the crossing poin t of the cfm and cfmn signal s. in the timing diagram, this is how the clock-cycle time (t cycle or t cyc,cfm ), clock-low time (t l,cfm ) and clock-high time (t h,cfm ) are measured. because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise (t r,cfm ) and fall time (t f,cfm ) of the signals are measured from th e 20% and 80% points of the full-swing levels. 20% = v il,cfm + 0.2 * (v ih,cfm ? v il,cfm ) 80% = v il,cfm + 0.8 * (v ih, cfm ? v il,cfm ) figure 57. clocking waveforms cfm cfmn t cycle or t cyc , cfm logic 1 v ih,cfm 80% 20% v il,cfm logic 0 t l , cfm t h , cfm t r , cfm t f , cfm
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 66/76 rev 0.1 rsl rq receive timing figure 58 shows a timing diagram for the rq11?rq0 requ est pins of the memory component. this diagram represents a magnified view of the pins and only a few cl ock cycles (cfm and cfmn ar e the clock signals). timing events are measured to and fr om the primary cfm/cfmn crossing point in which cfm makes its high-voltage-to-low-voltage transition. the rq11?rq0 signals are low true: a high voltage represents a logical zero and a low voltage represents a lo gical one. timing events on the rq11? rq0 pins are measured to and from the point that the signal reaches th e level of the reference voltage v ref, rsl . because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise (t r,rq ) and fall time (t f,rq ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v il,rq + 0.2*(v ih,rq ? v il,rq ) 80% = v il,rq + 0.8*(v ih,rq ? v il,rq ) there are two data receiving windows de fined for each rq11?rq0 signal. the first of these (labeled ?0?) has a set time, t s,rq , and a hold time, t h,rq , measured around the primary cfm/cfmn crossing point. the second (labeled ?1?) has a set time (t s,rq ) and a hold time (t h,rq ) measured around a point 0.5 t cycle after the primary cfm/cfmn crossing point. figure 58. rsl rq receive waveform cfm cfmn logic 0 v ih,rq 80% 20% v il,rq logic 1 t s , rq [1/2]*t cycle rq0 t cycle t h , rq t f , rq t r , rq t s , rq t h , rq 0 1 logic 0 v ih,rq 80% 20% v il,rq logic 1 t s , rq [1/2]*t cycle rq11 t h , rq t f , rq t r , rq t s , rq t h , rq 0 1 v ref , rsl v ref , rsl
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 67/76 rev 0.1 drsl dq receive timing figure 59 shows a timing diagram for receiving write data on the dq/dqn data pins of the memory component. this diagram represents a magnified view of the pins and shows only a few clock cycles are shown (cfm and cfmn are the clock signals). timing ev ents are measured to and from the primary cfm/cfmn crossing point in which cfm makes its high ? voltage ? to ? low ? voltage transition. the dq15?dq0/dqn15?dqn0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. they are also differential?timing events on the dq15?dq0/dqn15...dqn0 pins are measured to and from the point that each differential pair crosses. because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise time (t ir,dq ) and fall time (t if,dq ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v il,dq + 0.2 (v ih,dq ? v il,dq ) 80% = v il,dq + 0.8 (v ih,dq ? v il,dq ) there are 16 data receiving windows defined fo r each dq15?dq0/dqn15?dqn0 pi n pair. the receiving windows for a particular dqi/dqni pin pair is referenced to an offset parameter t doff,dqi (the index ?i? may take on the values {0, 1, ..15} and refers to each of the dq15?dq0/dqn15?dqn0 pin pairs). the t doff,dqi parameter determines the time between the pr imary cfm/cfmn crossing point and the offset point for the dqi/dqni pin pair. the 16 re ceiving windows are placed at times t doff,dqi + (j/8) t cycle (the index ?j? may take on the values {1, 2, ..16} and refers to each of the receiving windows for the dqi/dqni pin pair). the offset values t doff,dqi for each of the 16 dqi/dqni pin pairs can be different. however, each is constrained to lie inside the range {t doff,min , t doff,max }. furthermore, each offset value t doff,dqi is static and will not change during system operation. its valu e can be determined at initialization. the 16 receiving windows (j = 1?16) for the first pair dq0/dqn0 are labe led ?1? through ?16?. each window has a set time (t s,dq ) and a hold time (t h,dq ) measured around a point t doff,dq0 + (j/8) t cycle after the primary cfm/cfmn crossing point. the 16 receiving windows (j = 1?16) for the each of the other pairs dqi/dqni are also labeled ?1? through ?16?. each window has a set time (t s,dq ) and a hold time (t h,dq ) measured around a point t doff,dqi + (j/8) t cycle after the primary cfm/cfmn crossing point.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 68/76 rev 0.1 figure 59. drsl dq receive waveforms cfm cfmn logic 1 v ih,dq 80% 20% v il,dq logic 0 t doff , max i = {0,1,2,3,4,5,?15} j = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16} t cycle [( j )/8]*t cycle t ri , dq t h , dq t doff , min t doff,dq0 1 2 3 4 5 6 7 t fi , dq j t s , dq 15 16 dq0 dqn0 logic 1 v ih,dq 80% 20% v il,dq logic 0 [( j )/8]*t cycle t ri , dq t h , dq t doff,dqi 1 2 3 4 5 6 7 t fi , dq j t s , dq 15 16 dqi dqni logic 1 v ih,dq 80% 20% v il,dq logic 0 [( j )/8]*t cycle t ri , dq t h , dq t doff,dq15 1 2 3 4 5 6 7 t fi , dq j t s , dq 15 16 dq15 dqn15
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 69/76 rev 0.1 drsl dq transmit timing figure 60 shows a timing diagram for transmitting re ad data on the dq15?dq0/dqn 15?dqn0 data pins of the memory component. this diagram represents a magnified vi ew of these pins and only a few clock cycles are shown (cfm and cfmn are the clock signals) . timing events are measured to an d from the primary cfm/cfmn crossing point in which cfm makes its high ? voltage ? to ? low ? voltage transition. the dq15?dq0/dqn15?dqn0 signals are high-true: a low voltage re presents a logical zero and a high voltage represents a logical one. they are also differential ? timing events on the dq15?dq0/dqn15?dqn0 pi ns are measured to and fr om the point that each differential pair crosses. because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise (t or,dq ) and fall time (t of,dq ) of the signals are measured from th e 20% and 80% points of the full-swing levels. 20% = v ol,dq + 0.2 (v oh,dq ? v ol,dq ) 80% = v ol,dq + 0.8 (v oh,dq ? v ol,dq ) there are 16 data transmit windows defined for each dq15?dq0/dqn15?dqn0 pin pair. the transmitting windows for a particular dqi/dqni pin pair is referenced to an offset parameter t qoff,dqi (the index ?i? may take on the values {0, 1, ..15} and refers to each of the dq15?dq0/dqn15?dqn0 pin pairs). the t qoff,dqi + t q,dq, max expression determines the time between the primary cfm/cfmn crossing point and the offset point for the dqi/dqni pin pair. th e 16 receiving windows are placed at times t qoff,dqi + t q,dq, max + (j / 8) t cycle (the index ?j? may take on the values {1, 2, ..16} and refers to each of the transmit windows for the dqi/dqni pin pair). the offset values t qoff,dqi for each of the 15 dqi/dqni pin pairs can be different. however, each is constrained to lie inside the range {t qoff,min, t qoff,max }. furthermore, each offset value t qoff,dqi is static; its value will not change during system operation. its valu e can be determined at initialization time. the 16 transmit windows (j = 1?16) for the first pair dq0/dqn0 are l abeled ?1? through ?16?. each window begins at the time (t qoff,dq0 + t q,dq, max + (j ? 1 / 8) t cycle ) and ends at the time (t qoff,dq0 + t q,dq,min + (( j ) / 8) t cycle ) measured after the primary cfm/cfmn crossing point. the 16 transmit windows (j=1?16) for the other pairs dqi/dqni are also labeled ?1? through ?16?. each window begins at the time (t qoff,dqi + t q,dq,max + (j/8) t cycle ) and ends at the time (t qoff,dqi + t q,dq, min + ((j + 1) / 8) t cycle ) measured after the primary cfm/cfmn crossing point.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 70/76 rev 0.1 figure 60. rsl dq transmit waveforms cfm cfmn logic 1 v oh,dq 80% 20% v ol,dq logic 0 t qoff , max i = {0,1,2,3,4,5,?15} j = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16} t cycle [ ( j )/8 ]*t cycle t ro , dq t q , dq , min t qoff , min t qoff,dq0 2 3 4 5 6 7 8 t fo , dq j t q , dq , max 15 16 dq0 dqn0 1 [ (j-1)/8 ]*t cycle logic 1 v oh,dq 80% 20% v ol,dq logic 0 [ ( j )/8 ]*t cycle t ro , dq t q , dq , min t qoff,dqi 2 3 4 5 6 7 8 t fo , dq j t q , dq , max 15 16 dqi dqni 1 [ (j-1)/8 ]*t cycle logic 1 v oh,dq 80% 20% v ol,dq logic 0 [ ( j )/8 ]*t cycle t ro , dq t q , dq , min t qoff,dq7 2 3 4 5 6 7 8 t fo , dq j t q , dq , max 15 16 dq15 dqn15 1 [ (j-1)/8 ]*t cycle
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 71/76 rev 0.1 serial interface receive timing figure 61 shows a timing diagram for the serial interface pins of the memory componen t. this diagram represents a magnified view of the pins only a few clock cycles. the serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. timing even ts are measured to and from the v ref, rsl level. because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise time (t r,sck and t ri,si ) and fall time (t f,sck and t if,si ) of the signals are measured from the 20 % and 80% points of the full-swing levels. 20% = v il, si + 0.2 (v ih,si ? v il,si ) 50% = v il, si + 0.5 (v ih,si ? v il,si ) 80% = v il, si + 0.8 (v ih,si ? v il,si ) there is one receiving window defined for each serial in terface signal (rst, cmd and sdi pins). this window has a set time (t s,rq ) and a hold time (t h,rq ) measured around the falling ed ge of the sck clock signal. figure 61. serial interface receive waveforms sc k logic 0 v ih,si 80% v ref,rsl 20% v il,si logic 1 t s , si rst smd sdi t h , sck t h , si t fi , si t ri , si t l , sck t cyc , sck logic 0 v ih,si 80% v ref,rsl 20% v il,si logic 1 t f , sck t r , sck
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 72/76 rev 0.1 serial interface transmit timing figure 62 shows a timing diagram for the serial interface pins of the memory componen t. this diagram represents a magnified view of the pins and on ly a few clock cycles are shown. the serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. timing even ts are measured to and from the v ref, rsl level. because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise time (t or,si ) and fall time (t of,si ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v ol,si + 0.2 (v oh,si ? v ol,si ) 50% = v ol,si + 0.5 (v oh,si ? v ol,si ) 80% = v ol,si + 0.8 (v oh,si ? v ol,si ) there is one transmit window defined for the serial interface data signal (sdo pins). this window has a maximum delay time (t q,si,max ) from the falling edge of the sck cl ock signal and a minimum delay time (t q,si,min ) from the next falling edge of the sck clock signal. when the memory component is not selected during a se rial device read transaction, it will simply pass the information on the sdi input to the sdo output. th is combinational propagation delay parameter is t p,si . the t cyc,sck will need to be increased during a seri al read transaction (relative to the t cyc,sck value for a serial write transaction) because of the a ccumulated propagation delay through a ll of the xdr dram devices on the serial interface. during initialization, when the serial identification is determined, the sdi ? to ? sdo path is registered, so the t cyc,sck value can be set to the same value as for serial write transactions. see ?ini tialization? on page 45. figure 62. serial inte rface transmit waveforms sdo sc k logic 0 v ih,si 80% v ref,rsl 20% v il,si logic 1 t q , si , max t h , sck t q , si , min t fo , si t ro t l , sck t cyc , sck logic 0 v oh,si 80% v ref,rsl 20% v ol,si logic 1 t f , sck t r , sck t p , si combinational propagation from sdi to sdo when the device is not selected during a serial device read transaction. logic 0 v ih,si 80% v ref,rsl 20% v il,si logic 1 sdi
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 73/76 rev 0.1 package description package parasitic summary table 18 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory component. most of the parameters have maxi mum values only, however some have both maximum and minimum values. the first group of parameters are for the cfm/cfmn cloc k pair pins. they include inductance, capacitance, and resistance values. the second group of parameters are for the rq request pins. they include inductance, mutual inductance, capacitance, and resistance values. th ere are also limits on the spread in inductance and capacitance values allowed in any one memory component. the third group of parameters are sp ecific to the dq data pins and in clude inductance, mutual inductance, capacitance, and resistance values. th ere are also limits on the spread in inductance and capacitance values allowed in any one memory component. the fourth group of parameters are for the serial interface pins. they include inductance and capacitance values. table 18. package rsl parasitic summary symbol parameter and other conditions min max units l vterm v term pin ? effective input inductance per for bits ? 1.2 nh ? 2400 ? tbd ? 3200 ? 4.0 l i, cfm cfm/cfmn pins ? effective input inductance b ? 4000 ? tbd nh ? 2400 ? tbd ? 3200 1.8 2.4 c i, cfm cfm/cfmn pins ? effective input capacitance b ? 4000 ? tbd pf r i, cfm cfm/cfmn pins ? effective input resistance 4 15 ? ? 2400 ? tbd ? 3200 ? 4.0 l i, rq rsl rq pins ? effective input inductance b ? 4000 ? tbd nh ? 2400 tbd tbd ? 3200 1.8 2.4 c i, rq rsl rq pins ? effective input capacitance b ? 4000 tbd tbd pf r i, rq rsl rq pins ? effective input resistance 4 15 ? l 12, rq mutual inductance between adjacent rsl rq signals ? 0.6 nh ? l i, rq difference in l i, rq between any rsl rq pins of a single device ? 1.8 nh ? c i, rq difference in c i between cfm/cfmn average and rsl rq pins of single device ? 0.06 + 0.06 pf ? 2400 tbd tbd ? 3200 70 130 z pkg, dq drsl dq pins ? package differential impedance note ? package trace length should be less than 10mm long ? 4000 tbd tbd ? ? 2400 ? tbd ? 3200 ? 2.0 c i, dq drsl dq pins ? effective input capacitance a ? 4000 ? tbd pf ? 2400 ? tbd ? 3200 ? 0.06 ? c i, dq difference in c i between dqi and dqni of each drsl pair a ? 4000 ? tbd pf r i, rq drsl dq pins ? effective input resistance 4 25 ? l i, si serial interface effective input inductance b ? 8.0 nh (rst, sck, cmd) 1.7 3.0 c i, si serial interface effective input capacitance b (sdi, sdo) ? 7.0 pf a. this is the effective die input capaci tance, and does not include package capacitance. b. cfm/rq/si should include package capacitance / inductance, only dq does not include package capacitance. this value is a combination of the device io circuitr y and package capacitance and inductance.
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 74/76 rev 0.1 figure 63. equivalent circuits for package parasitic r i,rq rq pin pad c i,rq l i,rq gnd pin dq pin pad gnd pin cfmn pin gnd pin sck, cmd, rst pin gnd pin l 12,rq rq pin l 12,rq rq pin r i,dq c i,dq r i,dq c i,dq dqn pin z pkg,dq /2 z pkg,dq /2 pad pad r i,cfm c i,cfm r i,cfm c i,cfm z pkg,cfm /2 z pkg,cfm /2 pad cfm pin pad c i,si l i,si
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 75/76 rev 0.1 package dimensions 0.2min 1.2max index a l k j h g f e d c b a index 0.80 2.00 0.30 1.28 1.28 1.24 1.27 1.24 0.70 0.5 0.05 0.08 m s ab b s 0.1 s 0.1 s 0.15 4 0.2 s b 15.18 14.56 0.2 s a 0.38 0.05 p-tfbga100-1415az(a) unit: mm 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 weight: g (typ.)
TC59YM916BKG24A,32a ,32b,40b,32c,40c 2004-12-15 76/76 rev 0.1 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshi ba products specifications. also, pl ease keep in mind the precautions and conditions set forth in the ?handling guide for semicond uctor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, et c.. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the down stream products which are prohibited to be produced and sold, under any law and regulations. 030619eb a restrictions on product use

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