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realtek lrh series-gr rtd 2525/2545/2555 lrh flat panel display controller preliminary revision version 1.00 last updated: 2008/7/16
realtek lrh series-gr 2 1. features ........................................... ................................................... .....................................4 2. chip data path block diagram....................... ................................................... ...........8 3. register description............................... ................................................... ......................9 global event flag .................................. ................................................... ..........................................9 watch dog.......................................... ................................................... ...........................................14 input video capture................................ ................................................... .......................................15 input frame window ................................. ................................................... ....................................19 fifo frequency..................................... ................................................... ........................................22 scaling down control............................... ................................................... .....................................22 display format ..................................... ................................................... .........................................27 display fine tune.................................. ................................................... ........................................32 cyclic-redundant-check ............................. ................................................... ..................................33 fifo window........................................ ................................................... ........................................34 scaling up function ................................ ................................................... ......................................34 frame sync fine tune ............................... ................................................... ....................................38 sync processor..................................... ................................................... ..........................................40 macro vision ....................................... ................................................... ..........................................51 highlight window ................................... ................................................... .......................................53 color processor control............................ ................................................... .....................................58 contrast/brightness coefficient .................... ................................................... .................................59 gamma control ...................................... ................................................... .......................................60 dithering control (for display domain)............. ................................................... ...........................62 overlay/color palette/background color control ..... ................................................... .....................64 image auto function ................................ ................................................... .....................................65 dithering control (for input domain) ............... ................................................... ............................69 embedded timing controller......................... ................................................... ................................71 tcon horizontal/vertical timing setting ............ ................................................... .........................73 dot masking........................................ ................................................... ..........................................75 control for lvds ................................... ................................................... .......................................78 test function ...................................... ................................................... ............................................82 embedded osd ....................................... ................................................... ......................................88 digital filter ..................................... ................................................... .............................................89 color conversion (input domain).................... ................................................... ..............................91 paged control register ............................. ................................................... .....................................93 embedded adc (page 0) .............................. ................................................... .................................94 abl(page 0)........................................ ................................................... ........................................ 105 lvr(page 0)........................................ ................................................... ........................................ 110 smith trigger(page 0).............................. ................................................... ..................................... 111 memory pll (page 0)................................ ................................................... .............................. 111 adc pll (page 1) ................................... ................................................... ................................... 115 display pll (page 1)............................... ................................................... ................................ 126 dclk spread spectrum (page 1) ...................... ................................................... .......................... 128 mclk spread spectrum (page 1)...................... ................................................... .......................... 132 multiply pll for input cyrstal (page 1) ............ ................................................... ......... 134 audio dac (page 1)................................. ................................................... ................................ 136 overall hdmi system function block (page 2) ........ ................................................... .................. 141 hdcp 1.3 (page 2) .................................. ................................................... .................................... 148
realtek lrh series-gr 3 hdmi video and audio part (page 2)................. ................................................... ......................... 152 liveshow tm control (page 3).................................. ................................................... .................... 183 sdram control (page 4)............................. ................................................... ............................... 194 reserved (page 5) .................................. ................................................... ...................................... 207 reserved (page 6) .................................. ................................................... ...................................... 207 vivid color-video color space conversion(page 7) ... ................................................... .................. 207 vivid color-dcc (page 7)........................... ................................................... ................................. 208 icm (page 7) ....................................... ................................................... ........................................ 217 y-peaking filter and coring control (for display do main) (page 7) ..................................... ........... 219 dcr (page 7) ....................................... ................................................... ....................................... 220 pattern generator in display domain (page 7)....... ................................................... ...................... 226 reserved (page 8) .................................. ................................................... ...................................... 230 reserved (page 9) .................................. ................................................... ...................................... 231 reserved (page a) .................................. ................................................... ..................................... 232 reserved (page b) .................................. ................................................... ..................................... 232 reserved (page c) .................................. ................................................... ..................................... 232 register 1(page d)................................. ................................................... ...................................... 233 interrupt control .................................. ................................................... ................................................... .....................233 ddc................................................ ................................................... ................................................... ..........................233 ddc-ci ............................................. ................................................... ................................................... .......................238 pwm................................................ ................................................... ................................................... .........................243 register 2(page e) ................................. ................................................... ...................................... 248 pin-share .......................................... ................................................... ................................................... ........................248 cec function ....................................... ................................................... ................................................... .....................253 register 3(page f)................................. ................................................... ....................................... 257 cec analog function................................ ................................................... ................................................... ...............257 embedded osd ....................................... ................................................... .................................... 260 osd compression .................................... ................................................... ................................... 289 osd special function............................... ................................................... ................................... 290 4. electric specification ............................. ................................................... ................ 304 5. mechanical specification ........................... ................................................... ........... 305 6. ordering information ............................... ................................................... ............... 307
realtek lrh series-gr 4 1. features general programmable scaling up and down no external memory required. require only one crystal to generate all timing. programmable 3.3v detection for multi-power domain in a system 2 channels 8 bits pwm output, and wide range selectable pwm frequency. support input format up to 1920-pixel width ddc/ci(mccs) supported analog rgb input interface integrated 8-bit triple-channel 210 mhz adc/pll (optional) embedded programmable schmitt trigger of hsync support sync on green (sog) and various kinds of composite sync modes on-chip high-performance hybrid plls high resolution true 64 phase adc pll auto black level adjustment digital video input interface support 8-bit video (itu 656) format input built-in yuv to rgb color space converter & de-interlace dvi compliant digital input interface (optional) single link on-chip tmds receiver up to 165mhz adaptive algorithm for tmds capability data enable only mode support hdcp 1.1 supported (optional) auto detection /auto calibration input format detection compatibility with standard vesa mode and support user-defined mode smart engine for phase/image position/color calibration scaling fully programmable zoom ratios independent horizontal/vertical scaling advanced zoom algorithm provides high image quality sharpness/smooth filter enhancement support non-linear scaling from 4:3 to 16:9 or 16:9 to 4:3 color processor true 10 bits color processing engine srgb compliance advanced dithering logic for 18-bit panel color depth enhancement dynamic overshoot-smear canceling engine brightness and contrast control programmable 10-bit gamma support peaking/coring/xvycc function for video sharpness vividcolor tm independent color management (icm) dynamic contrast control (dcc) liveshow tm function high-performance rtc (response time compensation) with embedded sdram. output interface fully programmable display timing generator 1 and 2 pixel/clock panel support and up to 140mhz( rtd2525lrh )/170mhz( rtd2545lr h )/190mhz( RTD2555LRH ) support lvds output interface spread-spectrum dpll to reduce emi fixed last line output for perfect panel capability host interface support mcu serial bus interface. support mcu dual edge data latch. embedded osd embedded 16.5k sram dynamically stores osd command and fonts support multi-color ram font, 1, 2 and 4-bit per pixel 16 color palette with 4096 true color selection maximum 8 window with alpha-blending/ gradient/dynamic fade-in/fade-out, bordering/ shadow/3d window type rotary 90,180,270 degree independent row shadowing/bordering programmable blinking effects for each character osd-made internal pattern generator for factory mode support 12x18~4x18 hardware proportional font decompress osd font power & technology 48 pin qfn package embedded voltage regulator 0.11um process 3.3v / 1.2v power supplier
realtek lrh series-gr 5 rtd rtd rtd rtd2545 2545 2545 2545lr lrlr lr 12 11 10 9 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 r- r+ vcck pvcc txe2+ txe2- txe1+ txe1- txe0+ txe0- txo3+ txo3- txoc+ txoc- txo0- txo0+ txo1- txo1+ scl ddcsda/pwm1/irq/ tcon9 /aux- ch_n0 vcck pvcc xin ddcscl/pwm0/ tcon7 /aux- ch_p0 g- g+ txo2- txo2+ txe3+ txe3- lane3n/ v7/rxcn lane3p/ v6/rxcp lane2n/ v5/rx0n lane2p/ v4/rx0p lane1n/ v3/rx1n lane1p/ v2/rx1p v0/rx2n/ lane0n sda adc_gnd b- b+ v1/rext tmds_vdd /dp_vdd vclk/rx2p/ lane0p ahs avs bjt_b adc_vdd pin out diagram of rtd 2525/2545/2555 lrh
realtek lrh series-gr 6 48 pin-out list input port name i/o no description note b0+ ai 12 positive blue analog input b0- ai 11 negative blue analog input g0+ ai 14 positive green analog input g0- ai 13 negative green analog input r0+ ai 16 positive red analog input r0- ai 15 negative red analog input avs i 8 adc vertical sync input general schmitt trigger no power 5v tolerance ahs i 9 adc horizontal sync input adjustable schmitt trigger no power 5v tolerance pll name i/o pin no description note xi ai 45 reference clock input from external crysta l or from single-ended cmos/ttl osc 3.3v tolerance host interface name i/o pin no description note sda i/o 41 serial control i/f data (open drain w/ s t) 5v tolerance scl o 42 serial control i/f clock (open drain w/ s t) 5v tolerance tmds name i/o pin no description note rext ai 1 impedance match reference. rx2p ai 47 differential data input rx2n ai 48 differential data input rx1p ai 2 differential data input rx1n ai 3 differential data input rx0p ai 4 differential data input rx0n ai 5 differential data input rxcp ai 6 differential data input rxcn ai 7 differential data input video 8 (optional) name i/o pin no description v8_0 ~ v8_7 i 48~7 video 8 data input (3.3v toleran ce) vclk i 47 video8 clock input (3.3v tolerance) power and ground name i/o pin no description adc_gnd g 10 adc 1.2v ground adc_vdd p 17 adc 1.2v power tmds_vdd p 46 tmds 3.3v power vcck p 19/40 digital core power pvcc p 20/39 pad 3.3v power lvds display interface name i/o no description txe3+ o 21 lvds differential data output txe3- o 22 lvds differential data output txe2+ o 23 lvds differential data output txe2- o 24 lvds differential data output
realtek lrh series-gr 7 txe1+ o 25 lvds differential data output txe1- o 26 lvds differential data output txe0+ o 27 lvds differential data output txe0- o 28 lvds differential data output txo3+ o 29 lvds differential data output txo3- o 30 lvds differential data output txoc+ o 31 lvds differential clk output txoc- o 32 lvds differential clk output txo2+ o 33 lvds differential data output txo2- o 34 lvds differential data output txo1+ o 35 lvds differential data output txo1- o 36 lvds differential data output txo0+ o 37 lvds differential data output txo0- o 38 lvds differential data output ddc/ci channel name i/o no description ddcsda i/o 43 open drain, no power 5v tolerance wit h schmitt trigger pad ddcscl i 44 open drain, no power 5v tolerance with schmitt trigger pad pwm name i/o no description pwm0 o 44 open drain, with 5v tolerance pwm1 o 43 open drain, with 5v tolerance misc name i/o no description bjt_b o 18 embedded regulator p type bjt control pi n out timing controller name i/o no description tcon7 o 44 timing controller output tcon9 o 43 timing controller output
realtek lrh series-gr 8 2. chip data path block diagram adc hdmi vgip digital filter csc sd fifo/ frc su y-peaking dcc/icm srgb contrast/ brightness gamma osd overlay dithering lvds liveshow figure 1
realtek lrh series-gr 9 3. register description global event flag register::id_reg 0x00 name bit r/w default description config id 7:0 r 0x51 msb 4 bits: 0000 product code lsb 4 bits: 0001 rev. code register:: host_ctrl 0x01 name bit r/w default description config. rev 7 --- 0 reserved reset_chk 6 r/w 0 reset check once scalar is reset, this value will be cleared to 0.the purpose of it is to check if lvr has been triggered. it should be written to 1 ahead, then read it..lvr has been triggered if the value is 0,else lvr has not. rev 5:3 --- --- reserved pd_en 2 r/w 1 power down mode enable 0: normal 1: enable power down mode(default) turn off adc rgb channel/ adc band-gap/ sog/ dpll/ lvds/adc pll/ sync- proc/ tmds / hdmi-audio pll/m2pll note: for lvds power control, refer to following table. ps_en 1 r/w 0 power saving mode enable 0: normal(default) 1: enable power saving mode turn off adc rgb channel/ dpll/ lvds/ adc pll/ m2pll when power down or power saving function is enabled, internal mcu clock is forced to crystal clock. note: for lvds power control, refer to following table. sft_reset 0 r/w 0 software reset whole chip (low
realtek lrh series-gr 10 pulse at least 8ms) 0: normal (default) 1: reset all registers are reset to default except host_ctrl and power-on-latch. power down/power saving control only effective when lvds/rsd display output is double. disp_type cr 8e-00[1:0] data_type cr 28[2] port power control lvds [01] double [1] lvds mid lvds [01] double [1] lvds even lvds [01] double [1] lvds odd power down/power saving cr01 [2] /cr 01[1] lvds [01] single [0] lvds mid power up lvds mid-port cr8c-a0 [6] lvds [01] single [0] lvds even power up lvds even-port cr8c-a0 [5] lvds [01] single [0] lvds odd power up lvds odd-port cr8c-a0 [4] register:: status0 0x02 name bit r/w default description config. adcpll_nonlock 7 r 0 adc_pll non-lock if the adc_pll non-lock occurs, this bit is set to ?1?. ivs_error 6 r 0 input vsync error if the input vertical sync occurs within the programmed active period, this bit is set to ?1?. ihs_error 5 r 0 input hsync error if the input horizontal sync occurs within the programmed active period, this bit is set to ?1?. odd_occur 4 r 0 input odd toggle occur (for internal field odd toggle, refer to cr1a[5]) if the odd signal (from sav/eav or v16_odd) toggle occurs, this bit is set to ?1?. v8hv_occur 3 r 0 video8 input vertical/horizontal sync occurs if the yuv input v or h sync edge occurs, this bit is set to ?1?. adchv_occur 2 r 0 adc input vertical/horizontal sync occurs input v or h sync edge occurs; this bit
realtek lrh series-gr 11 is set to ?1?. buffer_ovf1 1 r 0 input overflow status (frame sync mode) * 1 if an overflow in the input data capture buffer occurs, this bit is set to ?1?. buffer_udf1 0 r 0 line buffer underflow status (frame sync mode) if an underflow in the line-buffer occurs, this bit is set to ?1?. write to clear status. register:: status1 0x03 name bit r/w default description config. buffer_ovf2 7 r 0 line buffer overflow status 1: line buffer overflow has occurred since the last status cleared buffer_udf2 6 r 0 line buffer underflow status 1: line buffer underflow has occurred since the last status cleared dena_stop 5 r 0 dena stop event status 1: if the dena stop event occurred since the last status cleared dena_start 4 r 0 dena start event status 1: if the dena start event occurred since the last status cleared as an interrupt source dvs_start 3 r 0 dvs start event status 1: if the dvs start event occurred since the last status cleared iena_stop 2 r 0 iena stop event status 1: if the iena stop event occurred since the last status cleared iena_start 1 r 0 iena start event status 1: if the iena start event occurred since the last status cleared ivs_start 0 r 0 ivs start event status 1: if the ivs start event occurred since the last status cleared write to clear status. * 1 only first event of input overflow/underflow is rec orded if both of them occurs.
realtek lrh series-gr 12 register::irq_ctrl0 0x04 name bit r/w default description config. irq_en 7 r/w 0 internal irq enable: (global) 0: disable these interrupt. 1: enable these interrupt. irq_adcpll 6 r/w 0 irq (adc_pll non-lock) 0: disable the adc_pll non-lock error event as an interrupt source 1: enable the adc_pll non-lock error event as an interrupt source irq_ihv 5 r/w 0 irq (input vsync/hsync error) (den across vsync or hsync) 0: disable the input vsync/hsync error event as an interrupt source 1: enable the input vsync/hsync error event as an interrupt source irq_odd 4 r/w 0 irq (input odd toggle occur) (eav/sav from video8) 0: disable input odd toggle event as an interrupt source 1: enable the input odd toggle event as an interrupt source irq_v8_hv 3 r/w 0 irq (video8 input hsync/vertical sync occurs) 0: disable the video8 input hsync or vsync event as an interrupt source 1: enable the video8 input hsync or vsync event as an interrupt sourc irq_adc_hv 2 r/w 0 irq (adc input hsync/vertical sync occurs) 0: disable the adc input hsync or vsync event as an interrupt source 1: enable the adc input hsync or vsync event as an interrupt source irq_buffer 1 r/w 0 irq (line buffer underflow/overflow status) 0: disable the line buffer underflow/overflow event as an interrupt source 1: enable the line buffer underflow/overflow event as an interrupt source
realtek lrh series-gr 13 irq_iena 0 r/w 0 irq (input ena start event occurred status) 0: disable iena start as interrupt source 1: enable iena start as interrupt source register:: hdmi_status0 0x05 name bit r/w default description config. hdmi status 0 7:0 r --- reference to crcb for hmdi function (page 2)(write 1 clear) register:: hdmi_status1 0x06 name bit r/w default description config. hdmi status 1 7:0 r --- reference to crcc for hmdi function (page 2)(write 1 clear) register:: new_added_status0 0x07 name bit r/w default description config. wstate 7 r --- wait state status new_m_state 6 r --- new mode state change_m_happen 5 r --- change mode happen (it will not be triggered while vgip active signal is low) wstate_irq_en 4 r/w 0 irq enable of wait state stat us 0:disable 1:enable new_m_state_irq _en 3 r/w 0 irq enable of new mode status 0:disable 1:enable change_m_happen _irq_en 2 r/w 0 irq enable of change mode happen status 0:disable 1:enable dp_irq 1 r --- display port irq status reserved 0 --- --- reserved register:: new_added_status1 0x08 name bit r/w default description config. reserved 7:0 --- --- reserved address: 09~0b reserved
realtek lrh series-gr 14 watch dog address: 0c watch_dog_ctrl0 default: 00h bit mode function 7 r/w auto switch when input hsync/vsync error 0: disable (default) 1: enable (see cr02[6] and cr02[5]) 6 r/w auto switch when input hsync/vsync timeout or overf low 0: disable (default) 1: enable (see cr52[4] and cr54[5:4]) 5 r/w auto switch when display vsync timeout 0: disable (default) 1: enable 4 r/w auto switch when adc-pll unlock 0: disable (default) 1: enable 3 r/w auto switch when overflow or underflow (for frame-s ync display) 0: disable (default) 1: enable 2 r/w watch-dog action if event happened (for display tim ing) 0: disable (default) 1: free run 1 r/w watch-dog action if event happened (for display dat a) 0: disable (default) 1: background (turn off overlay function and switch to background display simultaneously) 0 r display vsync timeout flag (for cr0c[5]) 0: dvs is present 1: dvs is timeout the line number of display hs is equal to display v ertical total; this bit is set to ?1?. (write to clear status). address: 0d watch_dog_ctrl1 default: 00h bit mode function 7 r/w auto switch when input hsync changed 0: disable (default) 1: enable (see cr58[3])
realtek lrh series-gr 15 6 r/w auto switch when input vsync changed 0: disable (default) 1: enable (see cr58[2]) 5 r/w wstate wd enable 0:disable(default) 1:enable 4 r/w new_m_state 0:disable(default) 1:enable 3 r/w change_mode_happen 0:disable(default) 1:enable 2:0 --- reserved address: 0e~0f reserved input video capture address: 10 vgip_ctrl (video graphic input control register) d efault: 00h bit mode function 7 r/w 8 bit random generator 0: disable(default) 1: enable 6 r/w input test mode: 0: disable (default) 1: video8 input will go through rgb channel, avs=>i vs, ahs=>ihs, vclk=>iclk 5 r/w vgip double buffer ready 0: not ready to apply 1: ready to apply when the list table of cr10[4] is set, then enable cr10[5] . finally, hardware will auto load these values into vgip double buffer registers as the trigger event happens and clear cr10[5] to 0. 4 r/w vgip double buffer mode enable (each register described below has its own double b uffer) 0: disable (original- write instantly by mcu write cycles) 1: enable (double buffer function write mode) register trigger event pllphase(crb3,crb4) falling edge of ivactive
realtek lrh series-gr 16 add 1-clk delay to ihs delay (cr12[4]) hsync synchronize edge (cr12[3]) iph_act_sta (cr14[2:0],cr15) falling edge of ivacti ve ipv_act_sta (cr18[2:0],cr19) iv_dv_lines (cr40) falling edge of ivactive ivs_delay (for capture) (cr1c,cr1e[1]) falling edge of ivactive ihs_delay (for capture) (cr1d, cr1e[0]) falling edge of ivactive 3:2 r/w input pixel format 00: embedded adc (adc_hs)(default) 01: embedded tmds 10: video8 11: reserved 1 r/w input graphic/video mode 0: from analog input (input captured by ?input capt ure window?) (default) 1: from digital input (captured start by ?enable s ignal?, but sill stored in ?capture window size?) 0 r/w input sampling run enable 0: no data is transferred (default) 1: sampling input pixels address: 11 vgip_siginv (input control signal inverted registe r) default: 00h bit mode function 7 r/w safe mode 0: normal (default) 1: safe mode enable, mask 1 frame ivs of every 2 f rame ivs, slow down input frame rate. 6 r/w ivs sync with ihs control (avoid vs bouncing) 0: enable (default) 1: disable 5 r/w hs signal inverted for field detection 0: negative edge (default) 1: positive edge 4 r/w input video odd signal invert enable 0: not inverted (odd = positive polarity) (default ) 1: inverted (odd = negative polarity) 3 r/w input vs signal polarity inverted 0: not inverted (vs = positive polarity) (default) 1: inverted (vs = negative polarity) 2 r/w input hs signal polarity inverted 0: not inverted (hs = positive polarity) (default) 1: inverted (hs = negative polarity)
realtek lrh series-gr 17 1 r/w input ena signal polarity inverted 0: not inverted (input high active) (default) 1: inverted (while input low active) 0 r/w video input clock polarity 0: rising edge latched (default) 1: falling edge latched address: 12 vgip_delay_ctrl default: 00h bit mode function 7 r 6-iclk-delay hs level latched by vs rising edge 6 r hs level latched by vs rising edge 5 r hs level latched by 6-iclk-delay vs rising edge 4 r/w/d add one clock delay to ihs delay 0: disable (default) 1: enable 3 r/w/d hsync synchronize edge 0: hsync is synchronized by the positive edge of t he input clock 1: hsync is synchronized by the negative edge of t he input clock ( hsync source is selected by cr48[0] and then sync hronized ) 2 r/w vsync synchronize edge 0: latch vs by the negative edge of input hsync (d efault) 1: latch vs by the positive edge of input hsync 1:0 r/w video input clock delay control: 00: normal (default) 01: 1ns delay 10: 2ns delay 11: 3ns delay address: 13 vgip_odd_ctrl (video graphic input odd control reg ister) default: 00h bit mode function 7 r/w odd inversion for odd-controlled-ivs-delay 0: not invert (default) 1: invert 6 r/w odd-controlled-ivs-delay one-line enable 0: disable (default) 1: enable 5 r/w safe mode odd inversion 0: not inverted (default) 1: inverted
realtek lrh series-gr 18 4 r/w force odd toggle enable (without odd/even toggle se lect in safe mode) 0: disable (default) 1: enable 3 r/w video 4:2:2->4:4:4 enable before scale-down (duplic ate) 0: disable (default) 1: enable 2 r/w decode video8 when adc or tmds active 0: disable (default) 1: enable 1 r/w eav error correction enable in video-8 0: disable 1: enable 0 r/w internal odd signal selection 0: odd signal from eav or ypbpr (default) 1: internal field detection odd signal (also suppo rt under vga, dvi input)
realtek lrh series-gr 19 input frame window (all capture window setting unit is 1) address: 14 iph_act_sta_h (input horizontal active start) de fault: 00h bit mode function 7:4 r/w/d input video horizontal active width -- high byte [11:8] 3:0 r/w/d input video horizontal active start -- high byte [11:8] address: 15 iph_act_sta_l (input horizontal active start low) default: 00h bit mode function 7:0 r/w/d input video horizontal active start -- low byte [7:0] in analog mode, iph_act_sta means the delay number of pixel clock from the lea ding edge of hs to the first pixel of each active line. actual delay numbe r of pixel clock = iph_act_sta(>=2) +2, in digital mode, iph_act_sta means the delay number of pixel clock from the lea ding edge of de to the first pixel of each active line. actual delay numbe r of pixel clock = iph_act_sta(>=0) address: 16 iph_act_wid_h (input horizontal active width high) default: 00h bit mode function 7 r/w video8 -c-port input latch bus msb to lsb swap cont rol: 0: normal (default) 1: swap video8 -c-port msb to lsb sequence into ls b to msb 6 r/w adc input g/b swap 0: no swap 1: swap 5 r/w adc input r/b swap 0: no swap 1: swap 4 r/w adc input r/g swap 0: no swap 1: swap 3 r/w double clock input 0: single clock 1: double clock this bit should be set double clock when using vide o 8 input 2:0 --- reserved b g r r g b cr16[4] cr16[5] cr16[6] rtd
realtek lrh series-gr 20 address: 17 iph_act_wid_l (input horizontal active width low) default: 00h bit mode function 7:0 r/w input video horizontal active width -- low byte [7:0] this register defines the number of active pixel cl ocks to be captured. address: 18 ipv_act_sta_h (input vertical active start high) default: 00h bit mode function 7:4 r/w input video vertical active lines ? high byte [11:8] 3:0 r/w/d input video vertical active start ? high byte [11:8] address: 19 ipv_act_sta_l (input vertical active start low) d efault: 00h bit mode function 7:0 r/w/d input video vertical active start ? low byte [7:0] the numbers of lines from the leading edge of selec ted input video vsync to the first line of the acti ve window. the value above should be larger than 1. address: 1a ipv_act_len_h (input vertical active lines) defa ult: 00h bit mode function 7 r sav/eav 2-bit error happened (set if happened and write to clear) 6 r sav/eav 1-bit error happened (set if happened and write to clear) 5 r internal field detection odd toggle happened (set if happened and write to clear) the function should be worked under no input clock 4:3 r number of input hs between 2 input vs (lsb bit [1:0]) 2:0 r/w reserved address: 1b ipv_act_len_l (input vertical active lines) defa ult: 00h bit mode function 7:0 r/w input video vertical active lines ? low byte [7:0] this register defines the number of active lines to be captured. address: 1c ivs_delay (internal input-vs delay control registe r) default: 00h bit mode function 7:0 r/w/d input vsync delay for capture[7:0] (counted by input hsync) it?s ivs delay for capture and digital filter, not for auto function address: 1d ihs_delay (internal input-hs delay control registe r) default: 00h bit mode function 7:0 r/w/d input hsync delay for capture [7:0] (counted by input pixel clock) it?s ihs delay for capture and digital filter, not for auto function address: 1e vgip_hv_delay default: 00h bit mode function 7:6 r/w input hsync delay for auto function (counted by input pixel clock)
realtek lrh series-gr 21 00: no delay 01: 32 pixels 10: 64 pixels 11: 96 pixels 5:4 r/w input vsync delay for auto function (counted by input hsync) 00: no delay 01: 3 line 10: 7 line 11: 15 line 3 r/w select dataenable or hsync to adjust clock phase 0: use dataeable to adjust clock phase (default) 1: use hsync to adjust clock phase (while input so urce as adc) 2 --- reserved 1 r/w/d input vsync delay for capture[8] (counted by input hsync) 0 r/w/d input hsync delay for capture[8] (counted by input pixel clock) address: 1f v8 source select & yuv422 to yuv444conversion default: 00h bit mode function 7 r/w reorder the data flow 0: dfilter -> color_conversion -> dithering -> hsd 1: dfilter -> dithering -> color_conversion -> hsd 6:4 --- reserved 3 r/w video 4:2:2->4:4:4 enable before scale-down 0: disable (default) 1: enable (this bit should be always enable when in video8/ h dmi yuv422 mode.) 2 r/w video 4:2:2->4:4:4 mode select 0: interpolation (default) 1: duplicate (this bit would be work only while cr1f[3] is enabl e) 1 r/w output 444 format (only work in interpolation mode ) 0: y 0 u 0 v 0 , y 1 (u 0 +u 2 )/2 (v 0 +v 2 )/2, y 2 u 2 v 2 , y 3 (u 2 +u 4 )/2 (v 2 +v 4 )/2? 1: y 0 u 0 v 1 , y 1 (u 0 +u 2 )/2v 1 , y 2 u 2 (v 1 +v 3 )/2, y 3 (u 2 +u 4 )/2v 3 ? 0 r/w uv swap (for yuv422 to yuv444) (only work in interpolation mode ) 0: sequence 444 result: y, u, v 1: sequence 444 result: y, v, u ihs_delay cr1e[0] / cr1d ihs_delay for auto cr1e[7:6] 1 clk delay cr12[4] for capture for auto ihs ivs_delay cr1e[1] / cr1c ivs_delay for auto cr1e[5:4] for capture for auto ivs figure 15: input hsync/vsync delay path diagram
realtek lrh series-gr 22 address: 20 v8clk_sel (v8clk selection setting) default: 00h bit mode function 7:6 --- reserved 5:4 r/w v8clk divider: 00: div 2 (default) 01: div 4 10: div 8 11: reserved 3 --- reserved 2:0 r/w v8clk_phase: 000: phase 0 (default) 001: phase 1 010: phase 2 (not work while div2) 011: phase 3 (not work while div2) 100: phase 4 (not work while div2 & div4) 101: phase 5 (not work while div2 & div4) 110: phase 6 (not work while div2 & div4) 111: phase 7 (not work while div2 & div4) fifo frequency address: 22 fifo frequency default: 00h bit mode function 7 r/w test mode 0: disable 1: input data of vgip replaced by background color in cr6d 6:3 r/w reserved to 0 2 r/w internal xtal frequency 0: f xtal 1: f xtal * m2pll_m / m2pll_n / 10 1:0 r/w fifo frequency 00: mpll 01: iclk 10: dclk 11: m2pll scaling down control address: 23 scale_down_ctrl (scale down control register) default:00h bit mode function 7 r/w vertical scale down function mode selection: 0: use line interpolation mode (default) 1: use drop line mode (note: this bit is only valid while cr23[0]=1?b1.) 6 r bist for line buffer one & two ok 0: fail
realtek lrh series-gr 23 1: ok 5 --- reserved 4 r/w line buffer bist function start (auto clear to 0 wh en finish) 0: finish 1: start 3 r/w horizontal non-linear scale down 0: linear 1: non-linear 2 r/w vertical scale-down compensation 0: disable (default) 1: enable 1 r/w horizontal scale down function enable: 0: disable scale down function (default) 1: enable scale down function 0 r/w vertical scale down function enable: 0: disable scale down function (default) 1: enable scale down function (note: there is a bit to select interpolation or dropping for vertical scale down at cr24[7].) address: 24 scale_down_access_port control default: 00h bit mode function 7 r/w enable scale-down access port 6:5 -- reserved to 0 4:0 r/w scale-down port address address: 25-00 v_scale_init bit mode function 7:6 -- reserved 5:0 r/w vertical scale down initial select [5:0] scale down initial point select: for example, if th e value is 43, we select the initial point is 43/64 address: 25-01 v_scale_dh (vertical scale down factor register) bit mode function 7:3 r/w reserved 2:0 r/w vertical scale down factor [18:16] address: 25-02 v_scale_dm (vertical scale down factor register) bit mode function 7:0 r/w vertical scale down factor [15:8] address: 25-03 v_scale_dl (vertical scale down factor register) bit mode function
realtek lrh series-gr 24 7:0 r/w vertical scale down factor [7:0] registers {v_scale_dh, v_scale_dm, v_scale_dl} = (y i/ym)*(2^17). the largest scale down ratio is 1/4 (integer part 2 bits) meanwhile, yi = vertical input length; ym=vertical memory write length address: 25-04 h_scale_init bit mode function 7:6 -- reserved 5:0 r/w horizontal scale down initial select [5:0] scale down initial point select: for example, if th e value is 43, we select the initial point is 43/64 address: 25-05 h_scale_dh bit mode function 7:0 r/w horizontal scale down factor [23:16] address: 25-06 h_scale_dm bit mode function 7:0 r/w horizontal scale down factor [15:8] address: 25-07 h_scale_dl bit mode function 7:0 r/w horizontal scale down factor [7:0] for linear scale down, registers {h_scale_dh, hscal e_dm, hscale_dl} = (xi/xm)*(2^20). meanwhile, xi = vertical input length; xm=vertical memory write length address: 25-08 h_scale_acch bit mode function 7 -- reserved 6:0 r/w horizontal scale down accumulated factor [14:8] address: 25-09 h_scale_accl bit mode function 7:0 r/w horizontal scale down accumulated factor [7:0] address: 25-0a sd_acc_widthh bit mode function 7:2 -- reserved 1:0 r/w horizontal scale down accumulated width [9:8] address: 25-0b sd_acc_widthl bit mode function 7:0 r/w horizontal scale down accumulated width [7:0] address: 25-0c sd_flat_widthh bit mode function 7:3 -- reserved 2:0 r/w horizontal scale down flat width [10:8] address: 25-0d sd_ flat _widthl bit mode function 7:0 r/w horizontal scale down flat width [7:0]
realtek lrh series-gr 25 address: 25-0e, 25-0f reserved address: 25-10 input pattern generator ctrl 0 default: 8?h00 bit mode function 7 r/w pattern reset to initial value 0 : 1 frame 1 : 16 frame 6 r/w random generator mode 0 : x^9 + x^3 + 1 1 : x^29+x^6+x^4+x+1 (green, blue, red ) 5 r/w data update (red) 0 : reference data enable(pixel base) 1: reference horizontal data enable end(line base) 4 r/w data update (green) 0 : reference data enable 1: reference horizontal data enable end 3 r/w data update (blue) 0 : reference data enable 1: reference horizontal data enable end 2 r/w pattern generator mode (red) 0 : random generator (ref. cr25-10[6] 1 : pattern generator (reg. cr25-11[2]) 1 r/w pattern generator mode (green) 0 : random generator (ref. cr25-10[6] 1 : pattern generator (reg. cr25-11[1]) 0 r/w pattern generator mode (blue) 0 : random generator (ref. cr25-10[6] 1 : pattern generator (reg. cr25-11[0]) address: 25-11 input pattern generator ctrl 1 default: 8?h00 bit mode function 7-3 r/w reserved to 0 2 r/w pattern generator (red) 0 : out(n) = out(n-1) 1: out(n) = out(n-1) + 1 1 r/w pattern generator (green) 0 : out(n) = out(n-1) 1: out(n) = out(n-1) + 1 0 r/w pattern generator (blue) 0 : out(n) = out(n-1) 1: out(n) = out(n-1) + 1 address: 25-12 input pattern generator red initial value defau lt: 8?h01 bit mode function 7-0 r/w red initial value [7:0] address: 25-13 input pattern generator green initial value defa ult: 8?h01 bit mode function 7-0 r/w green initial value [7:0] address: 25-14 input pattern generator blue initial value defa ult: 8?h01 bit mode function 7-0 r/w blue initial value [7:0] address: 25-15 input pattern generator red/green/blue initial val ue default: 8?h00
realtek lrh series-gr 26 bit mode function 7-6 r/w reserved to 0 5-4 r/w red initial value [9:8] 3-2 r/w green initial value [9:8] 1-0 r/w blue initial value [9:8] register::i_yuv444to422 0x26 name bits read/write reset state comments config vsd_as_4to2i n 7 r/w 0 this bit decides the data flow in i-domain: 0: h sd output as yuv444to422 input data 1: vsd output as yuv444to422 input data 4to2_as_fifoi n 6 r/w 0 this bit decides the data flow in i-domain: 0: i_buf output as fifo input data 1: yuv444to422 output as fifo input data ls_rsv_26_54 5:4 r/w 0 reserved 444to422_en 3 r/w 0 in i-domain, yuv 444 to 422: 0: disable 1: enable ls_rsv_26_2 2 r/w 0 reserved interpolate 1 r/w 0 in i-domain, yuv 444 to 422: 0: drop c directly a. uv_mode = 0: y 0 u 0 , y 1 v 0 , y 2 u 2 , y 3 v 2 ? b. uv_mode = 1: y 0 u 0 , y 1 v 1 , y 2 u 2 , y 3 v 3 ? 1: interpolation mode a. uv_mode = 0: y 0 (u 0 +u 1 )/2 , y 1 (v 0 +v 1 )/2, y 2 (u 2 +u 3 )/2 , y 3 (v 2 +v 3 )/2? b. uv_mode = 1: y 0 (u 0 +u 1 )/2 , y 1 (v 1 +v 2 )/2, y 2 (u 2 +u 3 )/2 , y 3 (v 3 +v 4 )/2? uv_mode 0 r/w 0 in i-domain, 444to422 u/v type 0: u0 v0 u2 v2 u4 v4 ? 1: u0 v1 u2 v3 u4 v5 ?
realtek lrh series-gr 27 vsd_as_4to2in hsd vsd 10 444 to 422 01 ibuf 4to2_as_fifoin to fifo from dithering or color_con version dithering/color_conv => hsd => 444to422 => i_buf => new_fifo dithering/color_conv => hsd => vsd(drop line) => 44 4to422 => i_buf => new_fifo dithering/color_conv => hsd => vsd(interpolation) = > 444to422 => new_fifo (defult setting) address: 27 reserved display format address: 28 vdis_ctrl (video display control register) defa ult: 20h bit mode function 7 r/w force display timing generator enable: (should be s et when in free-run mode) 0: wait for input ivs trigger 1: force enable 6 r/w display data output inverse enable 0: disable (default) 1: enable (only when data bus clamp to 0) 5 r/w display output force to background color 0: display output operates normally 1: display output is forced to the color as select ed by background color (cr6d) (default) 4 r/w display 18 bit rgb mode enable 0: all individual output pixels are full 24-bit rg b (default) 1: all individual output pixels are truncated to 1 8-bit rgb (lsb 2 bits = 0) 3 r/w frame sync mode enable
realtek lrh series-gr 28 0: free running mode (default) 1: frame sync mode 2 r/w display output double port enable 0: single port output (default) (not effective if cr8c-a0 [1]=1?b1) 1: double port output 1 r/w display output run enable 0: dhs, dvs, den & data bus are clamped to ?0? (de fault) 1: display output normal operation. 0 r/w display timing run enable 0: display timing generator is halted, zoom filter halted (default) 1: display timing generator and zoom filter enable d to run normally steps to disable output: first set cr28[1]=0, set cr28[6], then set cr28[0] =0 to disable output. address: 29 vdisp_siginv (display control signal inverted) default: 00h bit mode function 7 r/w dhs output format select (only available in frame s ync ) 0: the first dhs after dvs is active (default) 1: the first dhs after dvs is inactive 6 r/w display data port even/odd data swap: 0: disable (default) 1: enable 5 r/w display data port red/blue data swap 0: disable (default) 1: enable 4 r/w display data port msb/lsb data swap 0: disable (default) 1: enable 3 r/w skew display data output 0: non-skew data output (default) 1: skew data output 2 r/w display vertical sync (dvs) output invert enable: 0: display vertical sync output normal active high logic (default) 1: display vertical sync output inverted logic 1 r/w display horizontal sync (dhs) output invert enable: 0: display horizontal sync output normal active hi gh logic (default) 1: display horizontal sync output inverted logic 0 r/w display data enable (den) output invert enable: 0: display data enable output normal active high l ogic (default)
realtek lrh series-gr 29 1: display data enable output inverted logic address: 2a disp_addr (display format address port) bit mode function 7 r/w display setting double buffer enable 0 : disable 1 : enable register trigger event dh_total dvs rising odd_fixed_last even_fixed_last dvs rising 6 r/w display double buffer ready 0: not ready to apply 1: ready to apply when the list table of disp_addr[7] is set, then en able disp_addr[6], finally, hardware will auto load these value into rtd as the trigger event happens and clear disp_addr[6] to 0. 5:0 r/w display format address address: 2b disp_data (display format data port) bit mode function 7:0 r/w display format data address: 2b-00 dh_total_h (display horizontal total pixels) bit mode function 7:4 -- reserved to 0 3:0 r/w display horizontal total pixel clocks : high byte[11:8] address: 2b-01 dh_total_l (display horizontal total pixels) bit mode function 7:0 r/w display horizontal total pixel clocks: low byte[7:0] real dh_total (target value)= dh_total (register va lue)+ 4 address: 2b-02 dh_hs_end (display horizontal sync end) bit mode function 7:0 r/w display horizontal sync end[7:0]: determines the width of dhs pulse in dclk cycles address: 2b-03 dh_bkgd_sta_h (display horizontal background start ) bit mode function 7:4 -- reserved to 0 3:0 r/w display horizontal background start : high byte [11:8]
realtek lrh series-gr 30 address: 2b-04 dh_bkgd_sta_l (display horizontal background start ) bit mode function 7:0 r/w display horizontal background start : low byte [7:0] determines the number of dclk cycles from leading e dge of dhs to first pixel of background region. real dh_bkgd_sta (target value)= dh_bkgd_sta (regis ter value)+ 10 address: 2b-05 dh_act_sta_h (display horizontal active start) bit mode function 7:4 -- reserved to 0 3:0 r/w display horizontal active region start : high byte [11:8] address: 2b-06 dh_act_sta_l (display horizontal active start) bit mode function 7:0 r/w display horizontal active region start : low byte [7:0] determines the number of dclk cycles from leading e dge of dhs to first pixel of active region. real dh_act_sta (target value)= dh_act_sta (registe r value)+ 10 address: 2b-07 dh_act_end_h (display horizontal active end) bit mode function 7:4 -- reserved to 0 3:0 r/w display horizontal active end : high byte [11:8] address: 2b-08 dh_act_end_l (display horizontal active end) bit mode function 7:0 r/w display horizontal active end : low byte [7:0] determines the number of dclk cycles from leading e dge of dhs to the pixel of background region. real dh_act_end (target value)= dh_act_end (registe r value)+ 10 address: 2b-09 dh_bkgd_end_h (display horizontal background end) bit mode function 7:4 -- reserved to 0 3:0 r/w display horizontal background end : high byte [11:8] address: 2b-0a dh_bkgd_end_l (display horizontal background end) bit mode function 7:0 r/w display horizontal background end : low byte [7:0] real dh_bkgd_end (target value) = dh_bkgd_end (regi ster value)+ 10 address: 2b-0b dv_total_h (display vertical total lines) bit mode function 7:4 -- reserved to 0 3:0 r/w display vertical total : high byte [11:8] address: 2b-0c dv_total_l (display vertical total lines)
realtek lrh series-gr 31 bit mode function 7:0 r/w display vertical total: low byte [7:0] cr2b-0b, cr2b-0c are used as watch dog reference va lue in frame sync mode, the event should be the line number of display hs is equal to dv total. address: 2b-0d dvs_end (display vertical sync end) bit mode function 7:5 -- reserved to 0 4:0 r/w display vertical sync end[4:0]: determines the duration of dvs pulse in lines address: 2b-0e dv_bkgd_sta_h (display vertical background start) bit mode function 7:4 -- reserved to 0 3:0 r/w display vertical background start: high byte [11:8] determines the number of lines from leading edge of dvs to first line of background region. address: 2b-0f dv_bkgd_sta_l (display vertical background start) bit mode function 7:0 r/w display vertical background start: low byte [7:0] address: 2b-10 dv_act_sta_h (display vertical active start) bit mode function 7:4 -- reserved to 0 3:0 r/w display vertical active region start: high byte [11:8] determines the number of lines from leading edge o f dvs to first line of active region. address: 2b-11 dv_act_sta_l (display vertical active start) bit mode function 7:0 r/w display vertical active region start: low byte [7:0] address: 2b-12 dv_act_end_h (display vertical active end) bit mode function 7:4 -- reserved to 0 3:0 r/w display vertical active region end: high byte [11:8] address: 2b-13 dv_act_end_l (display vertical active end) bit mode function 7:0 r/w display vertical active region end : low byte [7:0] determine the number of lines from leading edge of dvs to the line of following background region. address: 2b-14 dv_bkgd_end_h (display vertical background end) bit mode function 7:4 -- reserved to 0
realtek lrh series-gr 32 3:0 r/w display vertical background end: high byte [11:8] address: 2b-15 dv_bkgd_end_l (display vertical background end) bit mode function 7:0 r/w display vertical background end: low byte [7:0] determine the number of lines from leading edge of dvs to the line of start of vertical blanking. address: 2b-16~2b-1f reserved display fine tune address: 2b-20 dis_timing (display clock fine tuning register) default: 00h bit mode function 7 r/w reserved to 0 6:4 r/w display output clock fine tuning control: 000: dclk rising edge correspondents with output d isplay data 001: 1ns delay 010: 2ns delay 011: 3ns delay 100: 4ns delay 101: 5ns delay 110: 6ns delay 111: 7ns delay 3 --- reserved 2 --- reserved 1 r/w dclk output enable 0: disable 1: enable 0 r/w dclk polarity inverted 0: disable 1: enable address: 2b-21 osd_reference__den default: 00h bit mode function 7:0 r/w position of reference den for osd[7:0] address: 2b-22 new_dv_ctrl default: 00h bit mode function 7 r/w new timing enable 0: disable
realtek lrh series-gr 33 1: enable 6 r/w line compensation enable 0: disable 1: enable 5 r/w pixel compensation enable 0: disable 1: enable 4 r/w reserve to 0 3:0 r/w dclk_delay[11:8] address: 2b-23 new_dv_dly default: 00h bit mode function 7:0 r/w dclk_delay[7:0] when cr2b-22[7]=1, dclk_delay[11:0] can?t be 0. address: 2b-24 sscg_new_timing_mode setting default: 00h bit mode function 7 r/w sscg new timing mode even/odd last line setting ive rse 0: no inverse 1: inverse 6 r/w sscg new timing mode even/odd last line setting ena ble 0: disable 1: enable 5:0 r/w reserve cyclic-redundant-check address: 2c op_crc_ctrl (output crc control register) de fault: 00h bit mode function 7:6 r/w crc selector 00 : crc after scale-down (before sdram) 01 : crc after scale-down (before sdram) 10 : crc after all processing 11 : reserved 5:1 -- reserved to 0 0 r/w output crc control: 0: stop or finish (default) 1: start crc function = x^24 + x^7 + x^2 + x + 1. address: 2d op _crc_checksum (output crc checksum) bit mode function
realtek lrh series-gr 34 7:0 r/w 1 st read=> output crc-24 bit 23~16 2 nd read=> output crc-24 bit 15~8 3 rd read=> out put crc-24 bit 7~0 the read pointer should be reset when 1. op_crc_byt e is written 2. output crc control starts. the read back crc value address should be auto-incr ease, the sequence is shown above fifo window address: 30 fifo_win_addr (fifo window address port) bit mode function 7:5 -- reserved to 0 4:0 r/w fifo window address port address: 31 fifo_win_data (fifo window data port) bit mode function 7:0 r/w fifo window data port port address will increase automatically after read /write. address: 31-00 drl_h_bsu (display read high byte before scaling-u p) default: 00h bit mode function 7:4 r/w display window read width before scaling up: high byte [11:8] 3:0 r/w display window read length before scaling up: high byte [11:8] address: 31-01 drw_l_bsu (display read width low byte before scal ing-up) default: 00h bit mode function 7:0 r/w display window read width before scaling up: low byte [7:0] address: 31-02 drl_l_bsu (display read length low byte before sca ling-up) default: 00h bit mode function 7:0 r/w display window read length before scaling up: low byte [7:0] the setting above should be use 2 as unit the setting above should be use 2 as unit scaling up function address: 32 scale_ctrl (scale control register) default: 00 h bit mode function 7 r/w video mode compensation: 0: disable (default)
realtek lrh series-gr 35 1: enable 6 r/w internal odd-signal inverse for video-compensation 0: no invert (default) 1: invert 5 r display line buffer ready 0: busy 1: ready 4 r/w enable full line buffer: 0: disable (default) 1: enable 3 r/w vertical line duplication 0: disable 1: enable 2 r/w horizontal pixel duplication 0: disable 1: enable 1 r/w enable the vertical filter function: 0: by pass the vertical filter function block (def ault) 1: enable the vertical filter function block 0 r/w enable the horizontal filter function: 0: by pass the horizontal filter function block (d efault) 1: enable the horizontal filter function block when using h/v duplication mode, fifo window width set original width, but fifo window height should b e 2x the original height. address: 33 sf_access_port default: 00h bit mode function 7 r/w enable scaling-factor access port 6:5 -- reserved to 0 4:0 r/w scaling factor port address when disable scaling factor access port, the access port pointer will reset to 0 address: 34-00 hor_sca_h (horizontal scale factor high) bit mode function 7:4 -- reserved 3:0 r/w bit [19:16] of horizontal scale factor address: 34-01 hor_sca_m (horizontal scale factor medium) bit mode function 7:0 r/w bit [15:8] of horizontal scale factor
realtek lrh series-gr 36 address: 34-02 hor_sca_l (horizontal scale factor low) bit mode function 7:0 r/w bit [7:0] of horizontal scale factor address: 34-03 ver_sca_h (vertical scale factor high) bit mode function 7:4 -- reserved 3:0 r/w bit [19:16] of vertical scale factor address: 34-04 ver_sca_m (vertical scale factor medium) bit mode function 7:0 r/w bit [15:8] of vertical scale factor address: 34-05 ver_sca_l (vertical scale factor low) bit mode function 7:0 r/w bit [7:0] of vertical scale factor this scale-up factor includes a 20-bit fraction par t to present a vertical scaled up size over the str eam input. for example, for 600-line original picture scaled up to 768-line, the factor should be as follows: (600/768) x 2^20 = 0.78125 x 2^20 = 819200 = c8000h = 0ch, 80h, 00h. address: 34-06 horizontal scale factor segment 1 pixel default : 00h bit mode function 7:3 -- reserved 2:0 r/w bit [10:8] of scaling factor segment 1 pixe l address: 34-07 horizontal scale factor segment 1 pixel default : 00h bit mode function 7:0 r/w bit [7:0] of scaling factor segment 1 pixel address: 34-08 horizontal scale factor segment 2 pixel default : 00h bit mode function 7:3 -- reserved 2:0 r/w bit [10:8] of scaling factor segment 2 pixe l address: 34-09 horizontal scale factor segment 2 pixel default : 00h bit mode function 7:0 r/w bit [7:0] of scaling factor segment 2 pixel address: 34-0a horizontal scale factor segment 3 pixel default : 00h bit mode function 7:3 -- reserved 2:0 r/w bit [10:8] of scaling factor segment 3 pixe l address: 34-0b horizontal scale factor segment 3 pixel default : 00h bit mode function
realtek lrh series-gr 37 7:0 r/w bit [7:0] of scaling factor segment 3 pixel address: 34-0c horizontal scale factor delta 1 default: 00h bit mode function 7:5 -- reserved 4:0 r/w bit [12:8] of horizontal scale factor delta 1 address: 34-0d horizontal scale factor delta 1 default: 00h bit mode function 7:0 r/w bit [7:0] of horizontal scale factor delta 1 address: 34-0e horizontal scale factor delta 2 default: 00h bit mode function 7:5 -- reserved 4:0 r/w bit [12:8] of horizontal scale factor delta 2 address: 34-0f horizontal scale factor delta 2 default: 00h bit mode function 7:0 r/w bit [7:0] of horizontal scale factor delta 2 address: 34-10 horizontal filter coefficient initial value def ault: c4h bit mode function 7:0 r/w accumulate horizontal filter coefficient in itial value address: 34-11 vertical filter coefficient initial value defa ult: c4h bit mode function 7:0 r/w accumulate vertical filter coefficient init ial value address: 35 filter_ctrl (filter control register) default: 00h bit mode function 7 r/w enable chroma filter coefficient access 0: disable (default) 1: enable 6 r/w select chroma h/v user defined filter coefficient t able for access channel 0: 1 st coefficient table (default) 1: 2 nd coefficient table 5 r/w select chroma horizontal user defined filter coeffi cient table 0: 1 st horizontal coefficient table (default) 1: 2 nd horizontal coefficient table 4 r/w select chroma vertical user defined filter coeffici ent table 0: 1st vertical coefficient table (default) 1: 2 nd vertical coefficient table 3 r/w enable luminance filter coefficient access 0: disable (default)
realtek lrh series-gr 38 1: enable 2 r/w select luminance h/v user defined filter coefficien t table for access channel 0: 1 st coefficient table (default) 1: 2 nd coefficient table 1 r/w select luminance horizontal user defined filter coe fficient table 0: 1 st horizontal coefficient table (default) 1: 2 nd horizontal coefficient table 0 r/w select luminance vertical user defined filter coeff icient table 0: 1st vertical coefficient table (default) 1: 2 nd vertical coefficient table the user defined filter coefficient table can be mo dified on-line. only the non-active coefficient-tab le can be modified, and then switch it to active. when cr35[7] and cr35[3] are zero, the write counte r of filter_port is reset to zero. you should reset counter before another setting. if both cr35[7] and cr35[3] are one, you can set ch roma and luminance coefficient at the same time. address: 36 filter_port (user defined filter access port) de fault: 00h bit mode function 7:0 w access port for user defined filter coefficient tab le when enable filter coefficient accessing, the first write byte is stored into the lsb(bit[7:0]) of coe fficient #1 and the second byte is into msb (bit[8:11]). theref ore, the valid write sequence for this table is c0- lsb, c0-msb, c1-lsb, c1-msb, c2-lsb, c2-msb ? c63-lsb & c63-msb, totally 64 * 2 cycles. since the 128 taps is symmetric, we need to fill the 64-coefficient se quence into table only. address: 37~3f reserved frame sync fine tune address: 40 ivs2dvs_dealy_lines (ivs to dvs lines) defaul t: 00h bit mode function 7:0 r/w ivs to dvs lines: (only for framesync mode) the number of input hs from ivs to dvs. should be double buffer by cr10[5:4] address: 41 iv_dv_delay_clk_odd (frame sync delay fine tuning) default: 00h bit mode function 7:0 r/w frame sync mode delay fine tune [7:0]
realtek lrh series-gr 39 applied to all fields when interlaced_fs_delay_fine _tuning is disabled (cr43[1] = 0) only for odd-field when interlaced_fs_delay_fine_tu ning is enabled (cr43[1] = 1) in frame sync mode , cr41[7:0] represents output vs delay fine-tuning. it delays the number of (cr41 [ 7:0] *16 + 16) input clocks if cr41[7:0] is not equal to 0. (n o delay fine-tune if cr41[7:0] = 0) address: 42 iv_dv_delay_clk_even (frame sync delay fine tuning ) default: 00h bit mode function 7:0 r/w frame sync mode delay fine tune [7:0] ?00? to disab le only for even-field when interlaced_fs_delay_fine_t uning is enabled (cr43[1] = 1) address: 43 fs_delay_fine_tuning default: 00h bit mode function 7 r/w enable measure last line by field 0 : disable 1: enable 6 r/w reference field in last line measure 0 : 0dd 1 : even 5:2 r/w reserved to 0 1 r/w interlaced_fs_delay_fine_tuning 0: disable (default) 1: enable 0 r/w internal odd-signal inverse for interlaced_fs_delay _fine_tuning 0: no invert (default) 1: invert address: 44 last_line_h default: 00h bit mode function 7 r/w last-line-width / dv-total selector : 0: cr44 [3:0] and cr45 indicate last-line width cou nted by display clock (default) 1: cr44 [3:0] and cr45 indicate dhs total number b etween 2 dvs. 6 r/w dv sync with 4x clock 0: disable 1: enable 5 r/w bist test enable 0: disable 1: enable (auto clear when finish) 4 r/w bist test result
realtek lrh series-gr 40 0: fail 1: ok 3:0 r dv total or last line width[11:8] before sync in fr ame sync mode address: 45 last_line_l bit mode function 7:0 r dv total or last line width[7:0] before sync in fra me sync mode address: 46 reserved as page selector for new sync- processor feature sync processor address: 47 sync_select default: 00h bit mode function 7 r/w on line sync processor power down (stop crystal clo ck in) 0: normal run (default) 1: power down 6 r/w hsync type detection auto run 0: manual (default) 1: automatic 5 r/w de-composite circuit enable 0: disable (default) 1: enable 4 r/w input sync. source selection 0: hs_raw(ss/cs) (default) 1: sog/soy 3 r/w sog source selection 0: sog0/soy0 (default) 1: reserved 2 r/w vga-adc hs/vs source 0: 1 st hs/vs (default) 1: reserved 1 r/w measured by crystal clock (result shown in cr59) (i n digital mode) 0: input active region (vertical iden start to iden stop) (measure at iden stop) (default) 1: display active region(vertical den start to den stop) (measure at den stop) the function should work correctly when ivs or dvs occurs and enable by cr50[4]. 0 r/w hsync & vsync measured mode 0: hs period counted by crystal clock & vs period counted by hs (analog mode) (default) 1: h resolution counted by input clock & v resolut ion counted by ena (digital mode) (get the correct resolution which is triggered by e nable signal, ena) address: 48 sync_invert default: 00h
realtek lrh series-gr 41 bit mode function 7 r/w coast signal invert enable: 0: not inverted (default) 1: inverted 6 r/w coast signal output enable: 0: disable (default) 1: enable 5 r/w hs_out signal invert enable: 0: not inverted (default) 1: inverted 4 r/w hs_out signal output enable: 0: disable (default) 1: enable 3 r/w cs_raw inverted enable 0: normal (default) 1: invert 2 r/w clamp signal output enable 0: disable (default) 1: enable 1 r/w hs recovery in coast 0: disable (default) (ss/soy) 1: enable (cs or sog ) 0 r/w hsync synchronize source 0: ahs (default) 1: feedback hs address: 49 sync_ctrl (sync control register) default: 06h bit mode function 7 r/w clk inversion to latch feedback hs for coast recove ry ( coast recovery means hs feedback to replace input hs) 0: non inversion (default) 1: inversion 6 r/w select hs_out source signal 0: bypass (sehs)(use in separate mode) 1: select de-composite hs out(dehs) (in composite mode) 5 r/w select adc_vs source signal (auto switch in auto ru n mode) 0: vs_raw 1: devs
realtek lrh series-gr 42 4 r/w clk inversion to latch adc hs for clamp 0: non inversion (default) 1: inversion 3 r/w inversion of hsync to measure vsync 0: non inversion (default) 1: inversion 2 r/w hsync measure source(adc_hs1) 0: select adc_hs 1: select sehs or dehs by cr49[6] (default) 1:0 r/w measure hsync/vsync source select: 00: tmds 01: video8 10: adc_hs1/adc_vs (default) 11: cs_raw/vs_raw address: 4a stable_high_period_h default: 00h bit mode function 7 r even/odd field of ypbpr (by line-count mode) 0: even 1: odd 6 r the toggling of polarity of ypbpr field happened (by line-count mode) 0: no toggle 1: toggle 5 r even/odd field of ypbpr (by vs-position mode) 0: even 1: odd 4 r the toggling of polarity of ypbpr field happened (by vs-position mode) 0: no toggle 1: toggle 3 r/w odd detection mode 0: line-count mode (default) 1: vs-position mode 2:0 r stable high period[10:8] compare each line?s high pulse period, if we get c ontinuous 64 lines with the same one, the period is updated as the stable period. address: 4b stable_high_period_l bit mode function 7:0 r stable high period[7:0] compare each line?s high pulse period, if we get c ontinuous 64 lines with the same one, the
realtek lrh series-gr 43 period is updated as the stable period. address: 4c vsync_counter_level_msb default: 03h bit mode function 7 r hsync type detection auto run result ready 6:4 r hsync type detection auto run result 000: no signal 001: not support 010: ypbpr 011: serration composite sync 100: xor/or-type composite sync with equalizer 101: xor/or-type composite sync without equalizer 110: hsync with vs_raw (separate hsync) 111: hsync without vs_raw (hsync only) reference when hsync type detection auto run result ready (cr4c[7]) 3 r/w reserved to 0 2:0 r/w vsync counter level count [10:8] msb vsync detection counter start value. address: 4d vsync_counter_level_lsb default: 00h bit mode function 7:0 r/w vsync counter level count [7:0] lsb address: 4e hsync_type_detection_flag bit mode function 7 r hsync overflow (16-bits) 6 r stable period change (write clear when cr4e[6]=1 or cr4f[0]=1) 5 r stable polarity change (write clear when cr4e[5]=1 or cr4f[0]=1) 4 r vs_raw edge occurs (write clear when cr4e[4]=1 or c r4f[0]=1) if vs_raw edge occurs, this bit is set to ?1?. 3 r detect capture window unlock repeated 32 times (wri te clear when cr4e[3]=1 or cr4f[0]=1) 2 r hsync with equalization (write clear when cr4e[2]=1 or cr4f[0] =1) 1 r hsync polarity change (write clear when cr4e[1]=1 o r cr4f[0]=1) 0 r detect capture window unlock (write clear when cr4e [0]=1 or cr4f[0]=1) address: 4f stable_measure default: 00h bit mode function 7 r stable flag 0: period or polarity can?t get continuous stable status. 1: both polarity and period are stable.
realtek lrh series-gr 44 6 r stable polarity 0: negative 1: positive compare each line?s polarity; if we get continuous n 64 lines with the same one, the polarity is updated as the stable polarity. 5:4 r/w feedback hsync high period select by adc clock: 00: 32 (default) 01: 64 10: 96 11: 128 3 r/w stable period tolerance 0: 2 crystal clks (default) 1: 4 crystal clks 2 r/w vsync measure invert enable 0: disable (default) 1: enable 1 r/w pop up stable value 0: no pop up (default) 1: pop up result, (cr4a[2:0], cr4b[7:0], cr4e[3], cr50[2:0], cr51[7:0]) 0 r/w stable measure start 0 : stop (default) 1 : start address: 50 stable_period_h default: 00h bit mode function 7 r measure one frame status 0: finished after 1 frame measuring / measure fini shed 1: measuring now 6 r cs_raw inverted by auto run mode 0: not inverted 1: inverted 5 r/w hs_out bypass pll into vgip 0: disable (default) 1: enable 4 r/w active region measure enable 0: disable (default) 1: enable 3 r/w adc_vs source select in test mode 0: select adc_vs source in normal mode or auto mode by cr47[6] (default)
realtek lrh series-gr 45 1: select adc_vs source in test mode (select vs_ra w or devs by cr49[5]) 2:0 r stable period[10:8] compare each line?s period, if we get continuous 6 4 lines with the same one, the period is updated as the stable period. address: 51 stable_period_l bit mode function 7:0 r stable period[7:0] compare each line?s period, if we get continuous 6 4 lines with the same one, the period is updated as the stable period. address: 52 meas_hs_per_h (hsync period measured result) defa ult: 8?b000xxxxx bit mode function 7 r/w auto measure enable 0: disable (default) 1: enable 6 r/w pop up period measurement result 0: no pop up (default) 1: pop up result 5 r/w start a hs & vs period / h & v resolution & polarit y measurement (on line monitor) 0: finished/disable (default) 1: enable to start a measurement, auto cleared aft er finished 4 r over-flow bit of input hsync period measurement 0: no over-flow occurred 1: over-flow occurred 3:0 r input hsync period measurement result: high byte[11:8] address: 53 meas_hs_per_l (hsync period measured result) bit mode function 7:0 r input hsync period measurement result: low byte[7:0] the result is expressed as the average number of cr ystal clocks (cr47[0]=0), or input clocks (cr47[0]= 1) between 2 hsync. the result is the total number of crystal/input clo cks inside 16-hsync periods divided by 16. fractional part of measure result is stored in cr56 [3:0]. address: 54 meas_vs_per_h (vsync period measured result) bit mode function 7 r input vsync polarity indicator 0: negative polarity (high period is longer than l ow one) 1: positive polarity (low period is longer than hi gh one) 6 r input hsync polarity indicator
realtek lrh series-gr 46 0: negative polarity (high period is longer than l ow one) 1: positive polarity (low period is longer than hi gh one) 5 r time-out bit of input vsync period measurement (no vsync occurred) 0: no time out 1: time out occurred 4 r over-flow bit of input vsync period measurement 0: no over-flow occurred 1: over-flow occurred 3:0 r input vsync period measurement result: high byte[11:8] address: 55 meas_vs_per_l (vsync period measured result) bit mode function 7:0 r input vsync period measurement result: low byte[7:0] this result is expressed in terms of input hs pulse s. when measured digitally, the result is expressed as the number of input ena signal within a frame. address: 56 meas_hs&vs_hi_h (hsync&vsync high period measured result) bit mode function 7:4 r input hsync high period measurement result: high byte[11:8] (cr58[0] = 0) input vsync high period measurement result: high byte[11:8] (cr58[0] = 1) 3:0 r input hsync period measurement fractional result (see cr52,53) address: 57 meas_hs&vs_hi_l (hsync&vsync high period measured result) bit mode function 7:0 r input hsync high period measurement result: low byte[7:0] (cr58[0] = 0) input vsync high period measurement result: low byte[7:0] (cr58[0] = 1) this result of hsync high-period is expressed in te rms of crystal clocks. when measured digitally, the result of hsync high-period is expressed as the number of input clocks inside the input enable signal. this result of vsync high-period is expressed in te rms of input hs pulses address: 58 meas_hs&vs_hi_sel (vsync high period measured resu lt) default:00h bit mode function 7:6 r/w hsync_max_delta 00: don?t care (cr58[3] will never go high) 01: 4-clock 10: 8-clock 11: 16-clock 5:4 r/w vsync_max_delta 00: don?t care (cr58[2] will never go high) 01: 2-hsync 10: 4-hsync
realtek lrh series-gr 47 11: 8-hsync 3 r hsync_over_range set to 1 if variation of hsync larger than hsync_m ax_delta is detected by on-line measurement (cr52[7]=1). write to clear this flag. 2 r vsync_over_range set to 1 if variation of vsync larger than vsync_ma x_delta is detected by on-line measurement (cr52[7]=1). write to clear this flag. 1 r/w start measurement after mode detection auto-mode 0: disable 1: enable (default) 0 r/w hsync/vsync high period measurement result select 0: hsync 1: vsync (see cr56~cr57) address: 59 meas_active_region_h (active region measured by cr stl_clk result) bit mode function 7:0 r/w active region measured by crystal clock 1 st read: measurement result: high byte[23:16] 2 nd read: measurement result: high byte[15:8] 3 rd read: measurement result: high byte[8:0] read pointer is auto increase, if write, the pointe r is also reset to 1 st result. address: 5a sync_test_misc default: 00h bit mode function 7 r/w clamp reference source selection 0: clamp source from normal hs 1: clamp source from cs_raw 6 r/w sync processor time-clock test mode 0: normal (default) 1: enable test mode; (switch 70ns-ck to the time- out & polarity counters) 5:3 r/w sync processor test signals output selectio n 000: disable on-line sync-processor test-signal ou tput (default) 001: adc_vs, adc_hs, adc_field, sog, vs_raw, cs_ra w, hs_out, coast 010: cs_hs, hs_yprpb_postiv, input_signal_be_inver ted, search_finish, load_search_stable48_result, load_finish_stable48_r esult, cap_hit, cap_miss 011: cs_hs ,cap_window ,de_hs ,de_vs ,de_coast ,cl amp_mask ,cap_hit ,cap_miss 100: cs_raw, hs_for_decmp, auto_det_rdy, auto_resu lt_rdy, flg_cnt_is50ms, flg_cnt_is80ms, hs_for_mv, mv_occur 101: mode_det_of, stb_per_chg, stb_pol_chg, vs_raw _vld, cap_32unlock, eq_occur, hs_pol_chg, cap_unlock 110: vs1_meas, hs1_meas, meas_clk, ms_now, reg_ms_ 1_frame_now, hsper_of , vsper_of,
realtek lrh series-gr 48 ms_timeout 111: adc_vs, clamp_mask, hs_clamp_g, hs_clamp_rb, vga_online_clamp3, vga_online_clamp2, vga_online_clamp1, vga_online_clamp0 2:0 r the number of input hs between 2 input vsync . lsb bit [2:0] for ypbpr address:5b reserved address: 5c sync_proc_port_addr default: 00h bit mode function 7:5 r/w reserved 4:0 r/w sync processor access port address address: 5d sync_proc_port_data default: 00h bit mode function 7:0 r/w sync processor access port data port address will increase automatically after read /write. address: 5d-00 g_clamp_start (clamp signal output start) defaul t: 04h bit mode function 7:0 r/w start of output clamp signal pulse for y/g channel[ 7:0]: determine the number of input double-pixel between the trailing edge of input hsync and the start of the output clamp signal. address: 5d-01 g_clamp_end (clamp signal output end) default: 1 0h bit mode function 7:0 r/w end of output clamp signal pulse for y/g channel [7 :0]: determine the number of input double-pixel between the trailing edge of input hsync and the end of the output clamp signal. address: 5d-02 br_clamp_start (clamp signal output start) defaul t: 04h bit mode function 7:0 r/w start of output clamp signal pulse for b/pb and r/p r channel [7:0]: determine the number of input double-pixel between the trailing edge of input hsync and the start of the output clamp signal. address: 5d-03 br_clamp_end (clamp signal output end) default: 10h bit mode function 7:0 r/w end of output clamp signal pulse for b/pb and r/pr channel [7:0]: determine the number of input double-pixel between the trailing edge of input hsync and the end of the output clamp signal. address: 5d-04 clamp _ctrl0 default:00h bit mode function
realtek lrh series-gr 49 7 r/w clamp trigger edge inverse for y/g channel 0: trailing edge (default) 1: leading edge 6 r/w clamp trigger edge inverse for b/pb and r/pr channe l 0: trailing edge (default) 1: leading edge 5:0 r/w mask line number before devs [5:0] address: 5d-05 clamp _ctrl1 default: 00h bit mode function 7 r/w clamp mask enable 0: disable (default) 1: enable 6 r/w select clamp mask as de vs 0: disable 1: enable 5:0 r/w mask line number after devs [5:0] cr5d-04[5:0] and cr5d-05[5:0] will set number of ma sk line before/after devs for clamp mask. address: 5d-06 clamp_ctrl2 default: 00h bit mode function 7 r/w clamp clock source 0: adc_clock (default) 1: crystal clock 6 r/w clamp counter unit (0x5d-00 ? 0x5d-03) 0: double pixels (default) 1: single pixel 5 r/w adc1_clamp_enable 0: disable (default) 1: enable 4 r/w adc0_clamp_enable 0: disable (default) 1: enable 3 r/w adc-3 clamp source 0: clamp-g (default) 1: clamp-br 2 r/w adc-2 clamp source 0: clamp-g (default) 1: clamp-br
realtek lrh series-gr 50 1 r/w adc-1 clamp source 0: clamp-g (default) 1: clamp-br 0 r/w adc-0 clamp source 0: clamp-g (default) 1: clamp-br address: 5d-07 coast_ctrl default: 21h bit mode function 7:4 r/w start of coast before devs leading edge [3:0] 3:0 r/w end of coast after devs trailing edge [3:0] address: 5d-08 capture_window_setting default: 04h bit mode function 7 r/w coast_sel 0: de_coast (default) 1: coast_org 6 r/w capture miss limit during hsync extraction 0: 32 (default) 1: 16 5 r/w capture window add step as miss lock 0: 1 crystal clks (default) 1: 2 crystal clks 4:0 r/w capture window tolerance 5?h00: 6 crystal clks for capture window 5?h01 ~ 5?b1f : 1 ~ 31 crystal clks for capture window address: 5d-09 detection_tolerance_setting default: 00h bit mode function 7 r/w reserved to 0 6:5 r/w stable period tolerance extension 00: use 0x4f[3] setting (default) 01: 4 crystal clks 10: 8 crystal clks 11: 16 crystal clks 4:0 r/w h-sync for de-composite de-bounce length 5?h00: disable de-bounce function (default) 5?h01 ~ 5?h1f : de-bounce 1 ~ 31 crystal clks for de-composite address: 5d-0a devs_cap_num_h default: 00h bit mode function 7:4 r/w reserved to 0 3:0 r the munber of capture window between devs hig h period: high byte[11:8] address: 5d-0b devs_cap_num_l default: 00h
realtek lrh series-gr 51 bit mode function 7:0 r the munber of capture window between devs hig h period: high byte[7:0] address:5d-0c~0f reserved macro vision address: 5d-10 macrovision control default: 00h bit mode function 7:4 r/w skip line[3:0] skip lines after vsync detected 3:2 r/w reserved to 0 1 r macrovision detected (on-line monitor) when detected macrovision occurred, this bit set t o 1, else clear to 0. 0 r/w macrovision enable 0: disable (default) 1: enable address: 5d-11 macrovision start line in even field bit mode function 7 r/w reserved to 0 6:0 r macrovision start line in even field [6:0] address: 5d-12 macrovision end line in even field bit mode function 7 r indicate the validity of macro vision line in even field 0: not valid 1: valid 6:0 r macrovision end line 0 [6:0] address: 5d-13 macrovision start line in odd field bit mode function 7 r/w reserved to 0 6:0 r macrovision start line in odd field [6:0] address: 5d-14 macrovision end line in odd field bit mode function 7 r indicate the validity of macro vision line in odd f ield 0: not valid 1: valid 6:0 r macrovision end line in odd field [6:0] address: 5d-15 macro vision detect de-bounce default: 00h bit mode function 7:5 r/w reserved to 0
realtek lrh series-gr 52 4:0 r/w h-sync for macro-vision detection de-bounce length 5?h00 ~ 5?h07: de-bounce 7 crystal clks for de-com posite (default) 5?h08 ~ 5?h1f: de-bounce 8 ~ 31 crystal clks for d e-composite figure 16: sync processor
realtek lrh series-gr 53 sync processor in automatic mode address 0x5e is reserved highlight window address: 60 highlight window access port control default : 00h bit mode function 7 r/w enable highlight window access port 6 r/w enable highlight window 5:4 -- reserved 3:0 r/w highlight-window port address address: 61-00 highlight window horizontal start bit mode function 7:4 -- reserved 3:0 r/w highlight window horizontal start[11:8] address: 61-01 highlight window horizontal start bit mode function 7:0 r/w highlight window horizontal start[7:0]
realtek lrh series-gr 54 address: 61-02 highlight window horizontal end bit mode function 7:4 -- reserved 3:0 r/w highlight window horizontal end[11:8] address: 61-03 highlight window horizontal end bit mode function 7:0 r/w highlight window horizontal end[7:0] address: 61-04 highlight window vertical start bit mode function 7:4 -- reserved 3:0 r/w highlight window vertical start[11:8] address: 61-05 highlight window vertical start bit mode function 7:0 r/w highlight window vertical start[7:0] address: 61-06 highlight window vertical end bit mode function 7:4 -- reserved 3:0 r/w highlight window vertical end[11:8] address: 61-07 highlight window vertical end bit mode function 7:0 r/w highlight window vertical end[7:0] highlight window horizontal/vertical reference poin t is den (display background start). address: 61-08 highlight window border bit mode function 7:4 -- reserved 3:0 r/w highlight window border width address: 61-09 highlight window border color bit mode function 7:6 -- reserved 5:0 r/w highlight window border red color msb 6bit (red col or 2-bit lsb = 00) address: 61-0a highlight window border color bit mode function 7:6 -- reserved 5:0 r/w highlight window border green color msb 6bit (green color 2-bit lsb = 00) address: 61-0b highlight window border color bit mode function
realtek lrh series-gr 55 7:6 -- reserved 5:0 r/w highlight window border blue color msb 6bit (blue c olor 2-bit lsb = 00) address: 61-0c highlight window control 0 default : 00h bit mode function 7:6 r/w contrast / brightness application control 00: set a used on full region 01: set b used inside highlight window 10: set a used outside highlight window 11: set a used outside highlight window, and set b used inside highlight window contrast (cr62[1]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[7:6]=00 || cr60[6]=0 set a set a 1 cr61-0c[7:6]=01 && cr60[6]=1 set b bypass 1 cr61-0c[7:6]=10 && cr60[6]=1 bypass set a 1 cr61-0c[7:6]=11 && cr60[6]=1 set b set a brightness (cr62[0]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[7:6]=00 || cr60[6]=0 set a set a 1 cr61-0c[7:6]=01 && cr60[6)=1 set b bypass 1 cr61-0c[7:6]=10 && cr60[6]=1 bypass set a 1 cr61-0c[7:6]=11 && cr60[6]=1 set b set a 5:4 r/w gamma application control 00: gamma used on full region 01: gamma used inside window 10: gamma used outside window 11: reserved gamma (cr67[6]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[5:4]=00 || cr60[6]=0 gamma gamma 1 cr61-0c[5:4]=01 && cr60[6]=1 gamma bypass 1 cr61-0c[5:4]=10 && cr60[6]=1 bypass gamma
realtek lrh series-gr 56 3:2 r/w dcc/icm application control 00: dcc/icm used on full region 01: dcc/icm used inside window 10: dcc/icm used outside window 11: reserved icm (cre0[7]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[3:2]=00 || cr60[6]=0 icm icm 1 cr61-0c[3:2]=01 && cr60[6]=1 icm bypass 1 cr61-0c[3:2]=10 && cr60[6]=1 bypass icm dcc (cre4[7]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[3:2]=00 || cr60[6]=0 dcc dcc 1 cr61-0c[3:2]=01 && cr60[6]=1 dcc bypass 1 cr61-0c[3:2]=10 && cr60[6]=1 bypass dcc 1:0 r/w peaking/coring application control 00:full region 01: inside window 10: outside window 11: reserved peaking (cr9a[6]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[5:4]=00 || cr60[6]=0 peaking peaking 1 cr61-0c[5:4]=01 && cr60[6]=1 peaking bypass 1 cr61-0c[5:4]=10 && cr60[6]=1 bypass peaking address: 61-0d highlight window control 1 default : 00h bit mode function
realtek lrh series-gr 57 7:6 r/w srgb application control 00: srgb used on full region 01: srgb used inside highlight window 10: srgb used outside highlight window 11: reserved srgb (cr62[2]) application control inside window outside window 0 x bypass bypass 1 cr61-0d[7:6]=00 || cr60[6]=0 srgb srgb 1 cr61-0d[7:6]=01 && cr60[6]=1 srgb bypass 1 cr61-0d[7:6]=10 && cr60[6]=1 bypass srgb 5:4 r/w dcr_app_ctrl 00: dcr used on full region. 01: dcr used inside highlight window. 10: dcr used outside highlight window. 11: reserved. dcr( page 7 crd8[0 ]) application control inside window outside window 0 x bypass bypass 1 cr61-0d[5:4]=00 || cr60[6]=0 dcr dcr 1 cr61-0d[5:4]=01 && cr60[6]=1 dcr bypass 1 cr61-0d[5:4]=10 && cr60[6]=1 bypass dcr 3:0 -- reserved to 0 (horizontal start, vertical start) (horizontal end, vertical end) border width inside window border
realtek lrh series-gr 58 inside window left-top point = (horizontal start + border width, vertical start + border width) inside window right-bottom point = (horizontal end, vertical end) border window left-top point = (horizontal start, v ertical start) border window right-bottom point = (horizontal end+ border width, vertical end + border width) border = border window ? inside window outside window = screen ? border window color processor control address: 62 color_ctrl (color control register) default: 00 h bit mode function 7 r/w srgb coefficient write ready 0: not ready or cleared after finished 1: ready to write (wait for dvs to apply) 6 r/w srgb precision 0: normal (default) 1: multiplier coefficient bit left shift 5:3 r/w srgb coefficient write enable 000: disable 001: write r channel (rrh,rrl,rgh,rgl,rbh,rbl) (ad dress reset to 0 when written) 010: write g channel (grh,gbl,ggh,ggl,gbh,gbl) (ad dress reset to 0 when written) 011: write b channel (brh,brl,bgh,bgl,bbh,bbl) (add ress reset to 0 when written) 100: r offset 101: g offset 110: b offset 2 r/w enable srgb function 0: disable (default) 1: enable 1 r/w enable contrast function: 0: disable the coefficient (default) 1: enable the coefficient 0 r/w enable brightness function: 0: disable the coefficient (default) 1: enable the coefficient address: 63 srgb_access_port bit mode function 7:0 w srgb_coef[7:0]
realtek lrh series-gr 59 for multiplier coefficient: 9 bit: 1 bit sign, 8 bi t fractional part for filling multiplier coefficient, the sequence sh ould be sign bit (high byte), 8 bit fractional (low byte) for offset coefficient: 1 sign, 5 integer, 2 bit fr actional part srgb output saturation to 1023 and clamp to 0 srgb output is 10 bit ? ? ?? ? ? ? ?? ? + + + ? ? ?? ? ? ? ?? ? + + + = ? ? ?? ? ? ? ?? ? boffset b goffset g roffset r bb bg br gb gg gr rb rg rr b g r 1 1 1 ' ' ' contrast/brightness coefficient address: 64 contrast /brightness access port control defaul t: 00h bit mode function 7 r/w enable contrast /brightness access port 6:4 -- reserved 3:0 r/w contrast /brightness port address access data port continuously will get address auto increase. address: 65-00 bri_red_coe (set a) bit mode function 7:0 r/w brightness red coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-01 bri_grn_coe (set a) bit mode function 7:0 r/w brightness green coefficient: valid range: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-02 bri_blu_coe (set a) bit mode function 7:0 r/w brightness blue coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-03 cts_red_coe (set a) bit mode function 7:0 r/w contrast red coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-04 cts_grn_coe (set a) bit mode function 7:0 r/w contrast green coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-05 cts_blu_coe (set a)
realtek lrh series-gr 60 bit mode function 7:0 r/w contrast blue coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-06 bri_red_coe (set b) bit mode function 7:0 r/w brightness red coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-07 bri_grn_coe (set b) bit mode function 7:0 r/w brightness green coefficient: valid range: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-08 bri_blu_coe (set b) bit mode function 7:0 r/w brightness blue coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-09 cts_red_coe (set b) bit mode function 7:0 r/w contrast red coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-0a cts_grn_coe (set b) bit mode function 7:0 r/w contrast green coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-0b cts_blu_coe (set b) bit mode function 7:0 r/w contrast blue coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) when highlight window is disable, coefficient set a is used. gamma control address: 66 gamma_port bit mode function 7:0 r/w access port for gamma correction table the gamma table written to this port should follow the sequences as expressed below: {2?b0, g0[9:4]}, {g0[3:0]}, 2?b0, g4[9:8]}, {g4[7:0 ]}, <- addr = 0
realtek lrh series-gr 61 {2?b0, g8[9:4]}, {g8[3:0]}, 2?b0, g12[9:8]}, {g12[7 :0]}, <- addr = 1 ?, {2?b0, g1016[9:4]}, {g1016[3:0]}, 2?b0, g1020[9:8]} , {g1020[7:0]}, <- addr = 127 {2?b0, g1023[9:4]}, {g1023[3:0]}, 4?b0}, {8?b0} <- addr = 128 when cr67[3] is set to 1, we can directly specify t he initial address of gamma table in this port. when cr67[3] is set to 1, the value of this port is the address of gamma table that you are going to r /w. when cr67[3] is set to 0, we can read the value of gamma table in the following order. {2?b0, g_4*2n [9:4]}, {g_4*2n [3:0]}, 2?b0, g4 *(2n+1)[9:8]}, {g4*(2n+1)[7:0]}, {2?b0, g_4*(2n+2)[9:4]}, {g_4*(2n+2) [3:0]}, 2?b0, g4*(2n+3) [9:8]}, {g4*(2n+3)[7:0]}, ?, {2?b0, g_1023[9:4]}, {g_1023*(2n+2) [3:0]}, 4?b0}, {8?b0} 0 4 8 1 2 1 0 1 6 1 0 2 0 1 0 2 3 0 1 0 2 3 1 0 1 2 1 6 i n o u t 0 1 2 1 2 7 2 0 2 4 2 8 3 2 3 4 3 6 1 0 0 8 1 0 0 4 1 0 0 0 9 9 6 1 2 8 1 2 6 1 2 5 a d d r address: 67 gamma_ctrl default: 00h bit mode function 7 r/w enable access channels for gamma correction coeffic ient: 0: disable these channels (default) 1: enable these channels 6 r/w gamma table enable 0: by pass (default) 1: enable 5:4 r/w color channel of gamma table 00: red channel (default) 01: green channel 10: blue channel 11: red/green/blue channel (r/g/b gamma are the sa me) 3 r/w gamma port address access enable
realtek lrh series-gr 62 0: normal function. (default) 1: gamma port is used as specifying initial address . 2:0 -- reserved to 0 access gamma_access register will reset gamma_port index. address: 68 gamma_bist (color control register) default: 00 h bit mode function 7 r/w test_mode 0: disable, dither_out = dither_result[9:2]; // t runcate to integer number (default) 1: enable, dither_out = dither_result[7:0]; // p ropagate decimal part for test 6 r/w srgb multiplier coefficient precision 0: 1-bit shift-left (default) 1: 2-bit shift-left 5:2 -- reserved to 0 1 r/w gamma bist_progress 0: bist is done (default) 1: bist is running 0 r gamma bist test result (it will go low first during bist period) 0: sram fail 1: sram ok dithering control (for display domain) register:: dithering_data_access 0x69 name bits read/ write reset state comments config dithering_da ta_access 7:0 w 0 refer to following description a. when cr6a[7:6] is 2?b01, dithering sequence tabl e access is enabled: there are three set of dithering sequence table, ea ch table contains 32 elements, s0, s1, ? , s31. each element has 2 bit to index one of 4 dithering table. input data sequence is {sr3,sr2,sr1,sr0}, {sr7,sr6, sr5,sr4}, ? , {sr31,sr30,sr29,sr28}, {sg3,sg2,sg1,s g0}, ? ,
realtek lrh series-gr 63 {sg31,sg30,sg29,sg28}, {sb3,sb2,sb1,sb0}, ? , {sb31 ,sb30,sb29,sb28} for red, green and blue channel. r + (2r+1) * c choose sequence element, where r is row number / 2, and c is column number / 2. b. when cr6a[7:6] is 2?b10, dithering table access is enabled: for dithering table access, the red, green, blue ea ch channel has 4 dithering table, each table is 2x2 elements, and one element has 4 bit for 10b/8b, the elements should fill 0 to 3, for 10b/6b, the elements should fill 0 to 15. input data sequence is [dr00 dr01],[dr02,dr03], ? , [dr30,dr31],[dr32,dr33], [dg00,dg01],[dg02,dg03], ? , [dg30,dg31],[dg32,dg33 ], [db00,db01],[db02,db03], ? , [db30,db31],[db32,db33]. d00 d01 d10 d11 d20 d21 d30 d31 d02 d03 d12 d13 d22 d23 d32 d33 c. when cr6a[7:6] is 2?b11, temporal offset access is enabled: there are 16 element for temporal offset table, t0 , t1, ? , t15. each element has 2 bit to index one of 4 temporal o ffset. input data sequence is {t3,t2,t1,t0}, {t7,t6,t5,t4} , {t11,t10,t9,t8}, {t15,t14,t13,t12}. register:: dithering_ctrl1 0x6a name bits read/ write reset state comments config dither_access 7:6 r/w 0 enable access control 00: disable (default) 01: enable access dithering sequence table 10: enable access dithering table 11: enable access temporal offset dither_en 5 r/w 0 enable dithering function 0: disable (default) 1: enable dither_temp 4 r/w 0 temporal dithering 0: disable (default) 1: enable dither_table 3 r/w 0 dithering table value sign 0: unsigned 1: signed (2?s complement) dither_mode 2 r/w 0 dithering mode 0: new (default) 1: old dither_v_fram_m 1 r/w 0 vertical frame modulation
realtek lrh series-gr 64 0: disable (default) 1: enable dither_vh_fram_ m 0 r/w 0 horizontal frame modulation 0: disable (default) 1: enable register:: dithering_ctrl2 0x6b name bits read/ write reset state comments config reserved 7:1 r/w 0 reserved dither_table_ref 0 r/w 1 table reference 0: by vs/hs 1: by den (default) overlay/color palette/background color control address: 6c overlay_ctrl (overlay display control register) default: 00h bit mode function 7:6 -- reserved to 0 5 r/w background color access enable 0: disable(reset cr6d write pointer to r) 1: enable 4:2 r/w alpha blending level (also enable osd frame control register 0x003 byte 1[3:2] 000: disable (default) 001 ~111: 1/8~ 7/8 1 r/w overlay sampling mode select: 0: single pixel per clock (default) 1: dual pixels per clock (the osd will be zoomed 2 x in horizontal scan line) 0 r/w overlay port enable: 0: disable (default) 1: enable turn off overlay enable and switch to background simultaneously when auto switch to background. address: 6d bgnd_color_ctrl default: 00h bit mode function 7:0 r/w background color rgb 8-bit value[7:0] there are 3 bytes color select of background r, g, b, once we enable background color access channel(c r6c[5] and the continuous writing sequence is r/g/b
realtek lrh series-gr 65 address: 6e overlay_lut_addr (overlay lut address) default: 00h bit mode function 7 r/w enable overlay color plate access: 0: disable (default) 1: enable 6 r/w reserved to 0 5:0 r/w overlay 16x24 look-up-table write address [5:0] auto-increment while every accessing ?overlay lut a ccess port?. address: 6f color_lut_port (lut access port) bit mode function 7:0 w color palette 16x24 look-up-table access port [7:0] using this port to access overlay color plate which addressing by the above registers. the writing sequence into lut is [r0, g0, b0, r1, g 1, b1, ? r15, g15, and b15] and the address counter will be automatic increment and circular from 0 to 47. image auto function address: 70 h_boundary_h bit mode function 7:4 r/w horizontal boundary start: high byte [11:8] 3:0 r/w horizontal boundary end: high byte [11:8] address: 71 h_boundary_sta_l bit mode function 7:0 r/w horizontal boundary start: low byte [7:0] address: 72 h_boundary_end_l bit mode function 7:0 r/w horizontal boundary end: low byte [7:0] address: 73 v_boundary_h bit mode function 7:4 r/w vertical boundary start: high byte [11:8] 3:0 r/w vertical boundary end: high byte [11:8] vertical boundary search should be limited by verti cal boundary start. address: 74 v_boundary_sta_l bit mode function 7:0 r/w vertical boundary start: low byte [7:0]
realtek lrh series-gr 66 address: 75 v_boundary_end_l bit mode function 7:0 r/w vertical boundary end: low byte [7:0] address: 76 red_noise_margin (red noise margin register) bit mode function 7:2 r/w red pixel noise margin setting register 1:0 -- reserved to 0 address: 77 grn_noise_margin (green noise margin register) bit mode function 7:2 r/w green pixel noise margin setting register 1:0 -- reserved to 0 address: 78 blu_noise_margin (blue noise margin register) bit mode function 7:2 r/w blue pixel noise margin setting register 1:0 -- reserved to 0 address: 79 diff_threshold bit mode function 7:0 r/w difference threshold (threshold for diff no matter cr7d[2] = 0 or 1) address: 7a auto_adj_ctrl0 default: 00h bit mode function 7 r/w field_select_enable: auto-function only active when even or odd field. 0: disable (default) 1: enable 6 r/w field_select: select even or odd field. active when field_select_enable . 0: active when odd signal is ?0? (default) 1: active when odd signal is ?1? 5 r/w low pass filter (121-lpf) 0: disable (default) 1: enable 4 r/w auto function acceleration : 0: disable (default) 1: enable for auto-balance (cr7d[1]=0), this function must be disabled. 3:2 r/w vertical boundary search: 00: 1 pixel over threshold (default) 01: 2 pixel over threshold
realtek lrh series-gr 67 10: 4 pixel over threshold 11: 8 pixel over threshold 1:0 r/w color source select for detection: 00: b color (default) 01: g color 10: r color 11: all ( the result will be divided by 2 ) address: 7b hw_auto_phase_ctrl0 default: 00h bit mode function 7:3 r/w number of auto-phase step (valut+1) (how many times (steps reference cr7b[2:0]) jumps w hen using hardware auto) 2:0 r/w hardware auto phase step 000: step =1 (default) 001 step =2 010: step =4 011: step =8 1xx: step =16 address: 7c hw_auto_phase_ctrl1 default: 00h bit mode function 7 r/w hardware auto phase select trigger 0: ivs 1: vertical boundary end 6:0 r/w initial phase of auto-phase (0~127) address: 7d auto_adj_ctrl1 default: 00h bit mode function 7 r/w measure digital enable info when boundary search ac tive 0: normal boundary search (default) 1: digital enable info boundary search.(digital mod e) 6 r/w hardware / software auto phase switch 0: software (default) 1: hardware 5 r/w color max or min measured select: 0: min color measured (only when balance-mode, res ult must be complemented) (default) 1: max color measured 4 r/w accumulation or compare mode 0: compare mode (default) 1: accumulation mode
realtek lrh series-gr 68 3 r/w mode selection for sod 0: sod edge mode (default) 1: sod edge + pulse mode 2 r/w type selection for diff 0: diff 1: (diff/4) * (diff/4) total result for each color is divided by 8 if this bit is 1. 1 r/w function (phase/balance) selection 0: auto-balance (default) 1: auto-phase 0 r/w start auto-function tracking function: 0: stop or finished (default) 1: start control table/ function sub-function cr7d.6 cr7d.5 cr7d.4 cr7d.3 cr7d.1 cr7c auto-balance max pixel x 1 0 0 0 x min pixel x 0 0 0 0 x auto-phase type mode1 1 1 1 0 1 th mode2 1 1 1 1 1 th accumulation all pixel 1 1 1 0 0 0 table 1 auto-tracking control table address: 7e ver_start_end_h (active region vertical start regi ster) bit mode function 7:4 r active region vertical start measurement result: bit[11:8] 3:0 r active region vertical end measurement result: bit[11:8] address: 7f ver_start_l (active region vertical start register ) bit mode function 7:0 r active region vertical start measurement result: bit[7:0] address: 80 ver_end_l (active region vertical end register) bit mode function 7:0 r active region vertical end measurement result: bit[7:0] address: 81 h_start_end_h (active region horizontal start regi ster) bit mode function 7:4 r active region horizontal start measurement result: bit [11:8] 3:0 r active region horizontal end measurement result: bit[11:8] address: 82 h_start_l (active region horizontal start register )
realtek lrh series-gr 69 bit mode function 7:0 r active region horizontal start measurement result: bit[7:0] address: 83 h_end_l (active region horizontal end register) bit mode function 7:0 r active region horizontal end measurement result: bit[7:0] address: 84 auto_phase_3 (auto phase result byte3 register) bit mode function 7:0 r auto phase measurement result: bit[31:24] address: 85 auto_phase_2 (auto phase result byte2 register) bit mode function 7:0 r auto phase measurement result: bit[23:16] address: 86 auto_phase_1 (auto phase result byte1 register) bit mode function 7:0 r auto phase measurement result: bit[15:8] address: 87 auto_phase_0 (auto phase result byte0 register) bit mode function 7:0 r auto phase measurement result: bit[7:0] the measured value of r or g or b color max or min . (auto-balance) when input is 2560x1600, there will be three case f or register 0x84~0x87: a. o nly sod + pulse for rgb 2560x1600x255x2x3 = 6266880000 need 33 bits to indi cate. cr 84~87 will give bit [32:1]. b. (sod/4)^2 / 8 + pulse for rgb 2560x1600x(255/4)^2 /8 x2x3 = 12484800000 need 34 bits to indicate. cr 84~87 will give bit [33:2] c. (sod/4)^2 /8 + pulse only for one color 2560x1600x(255/4)^2 /8 x2 = 4161600000 need 32 bits to indicate. cr 84~87 will give bit [31:0] dithering control (for input domain) register:: dithering_data_access 0x88 name bits read/ reset comments config
realtek lrh series-gr 70 write state dithering_da ta_access 7:0 w 0 refer to following description a. when cr88[7:6] is 2?b01, dithering sequence tabl e access is enabled: there are three set of dithering sequence table, ea ch table contains 32 elements, s0, s1, ? , s31. each element has 2 bit to index one of 4 dithering table. input data sequence is {sr3,sr2,sr1,sr0}, {sr7,sr6, sr5,sr4}, ? , {sr31,sr30,sr29,sr28}, {sg3,sg2,sg1,s g0}, ? , {sg31,sg30,sg29,sg28}, {sb3,sb2,sb1,sb0}, ? , {sb31 ,sb30,sb29,sb28} for red, green and blue channel. r + (2r+1) * c choose sequence element, where r is row number / 2, and c is column number / 2. b. when cr88[7:6] is 2?b10, dithering table access is enabled: for dithering table access, the red, green, blue ea ch channel has 4 dithering table, each table is 2x2 elements, and one element has 4 bit for 10b/8b, the elements should fill 0 to 3, for 10b/6b, the elements should fill 0 to 15. input data sequence is [dr00 dr01],[dr02,dr03], ? , [dr30,dr31],[dr32,dr33], [dg00,dg01],[dg02,dg03], ? , [dg30,dg31],[dg32,dg33 ], [db00,db01],[db02,db03], ? , [db30,db31],[db32,db33]. d00 d01 d10 d11 d20 d21 d30 d31 d02 d03 d12 d13 d22 d23 d32 d33 c. when cr88[7:6] is 2?b11, temporal offset access is enabled: there are 16 element for temporal offset table, t0 , t1, ? , t15. each element has 2 bit to index one of 4 temporal o ffset. input data sequence is {t3,t2,t1,t0}, {t7,t6,t5,t4} , {t11,t10,t9,t8}, {t15,t14,t13,t12}. register:: dithering_ctrl1 0x89 name bits read/ write reset state comments config dither_access 7:6 r/w 0 enable access control 00: disable (default) 01: enable access dithering sequence table 10: enable access dithering table 11: enable access temporal offset dither_en 5 r/w 0 enable dithering function 0: disable (default) 1: enable dither_temp 4 r/w 0 temporal dithering 0: disable (default) 1: enable dither_table 3 r/w 0 dithering table value sign
realtek lrh series-gr 71 0: unsigned 1: signed (2?s complement) dither_mode 2 r/w 0 dithering mode 0: new (default) 1: old dither_v_fram_m 1 r/w 0 vertical frame modulation 0: disable (default) 1: enable dither_vh_fram_ m 0 r/w 0 horizontal frame modulation 0: disable (default) 1: enable address 0x8a are reserved embedded timing controller address: 8b tcon_addr _port d efault: 00h bit mode function 7:0 r/w address port for embedded tcon access address: 8c tcon_data _port default: 00h bit mode function 7:0 r/w data port for embedded tcon access address: 8c-00 tc_ctrl0 (timing controller control register1) default: 01h bit mode function 7 r/w enable timing controller function (global) 0: disable (default) 1: enable all tcon pins will be initialized when enabled and goes low when disabled. 6 r/w tcon [n] toggle function reset 0: not reset (default) 1: reset by dvs 5 r/w inactive period data controlled by internal tcon [1 3] 0: den (default) 1: tcon [13] 4 r/w tcon_hs compensation 0: real tcon_hs = tcon_hs-4 1: real tcon_hs = tcon_hs-27
realtek lrh series-gr 72 if setting tcon_hs > dh_total, then setting tcon_hs must subtract dh_total. 3 --- reserve to 0 2 --- reserve to 0 1:0 r/w disp_type 01: lvds (default) others are reserved address: 8c-01 tc_ctrl1 (timing controller control register1) default: 00h bit mode function 7:0 r/w reserved to 0 address: 8c-02 pixel threshold msb default: 00h bit mode function 7 r/w 2-line sum of difference threshold 1 value: bit [8] , ie:th1 (also refer to cr8c-03) 6 r/w 2-line sum of difference threshold 2 value: bit [8] , ie:th2 (also refer to cr8c-04) 5:0 r/w over difference line threshold value: bit [9:4] notes: bit[3:0] are zeros address: 8c-03 pixel threshold high value for smart polarity (th1) default: 00h bit mode function 7:0 r/w 2 line sum of difference threshold 1 value: bit [7: 0], ie:th1 (also refer to cr8c-02[7]) address: 8c-04 pixel threshold low value for smart polarity (th2) default: 00h bit mode function 7:0 r/w 2 line sum of difference threshold 2 value: bit [7: 0], ie:th2 (also refer to cr8c-02[6]) address: 8c-05 line threshold value for smart polar ity default: 00h bit mode function 7 r/w measure dot pattern over threshold 1: run. auto: always measure (reference to cr8c-05[5]) manual: start to measure, clear after finish 0: stop 6 r dot pattern sum of difference measure result 1: over threshold 0: under threshold 5 r/w anti-flicker auto-measure control 1: auto 0: manual
realtek lrh series-gr 73 4:1 r/w reserved 0 r/w anti-flicker measure mode 0: dot-based (original) 1: pixel-based over difference line threshold value shall not exce ed 0x190. address: 8c-06~07 reserved to 0 tcon horizontal/vertical timing setting address: 8c-08 tcon [0]_vs_lsb (tcon [0] vertical s tart lsb register) bit mode function 7:0 w line number [7:0] at which tcon control generation begins address: 8c-09 tcon [0]_vs_msb (tcon [0] vertical s tart/end msb register) bit mode function 7:4 w line number [11:8] at which tcon control generation ends 3:0 w line number [11:8] at which tcon control generation begins address: 8c-0a tcon [0]_ve_lsb (tcon [0] vertical e nd lsb register) bit mode function 7:0 w line number [7:0] at which tcon control generation ends address: 8c-0b tcon [0]_hs_lsb (tcon [0] horizontal start lsb register) bit mode function 7:0 w pixel count [7:0] at which tcon goes active address: 8c-0c tcon [0]_hs_msb (tcon [0] horizontal start/end msb register) bit mode function 7:4 w pixel count [11:8] at which tcon goes inactive 3:0 w pixel count [11:8] at which tcon goes active to be triggered on rising edge of the dclk address: 8c-0d tcon [0]_he_lsb (tcon [0] horizontal end lsb register) bit mode function 7:0 w pixel count [7:0] at which tcon goes inactive if the register number is large than display format , the horizontal component is always on. real tcon_hs = tcon_hs-4, real tcon_hs = tcon_hs-4 address: 8c-0e tcon [0]_ctrl (tcon [0] control regi ster) default: 00h bit mode function 7 r/w tcon [n] enabl e (local) 0: disable (tcon [n] output clamp to ?0?) (default ) 1: enable
realtek lrh series-gr 74 6 r/w polarity control 0: normal output (default) 1: inverted output 5:4 -- reserved to 0 3 r/w toggle circuit enable/disable 0: normal tcon output (default) 1: toggle circuit enable when using toggle circuit enable mode, the tcon[n] will be 1 clock earlier than tcon[n- 1] and then toggling together, finally output will be 1 cl ock delay comparing to toggling result. 2:0 r/w tcon [13:10] & tcon [7:4] (tcon combination select) tcon [13] has inactive data controller function. tcon [13]~[10] has dot masking function tcon [7] has flicking reduce function. 000: normal tcon output (default) 001: select tcon [n] ?and? with tcon [n-1] 010: select tcon [n] ?or? with tcon [n-1] 011: select tcon [n] ?xor? with tcon [n-1] 100: select tcon [n-1] rising edge as toggle trigg er signal (when toggle enable) 101: select tcon [n-1] rising edge as toggle trigg er signal, then ?and? (when toggle enable) 110: select tcon [n-1] rising edge as toggle trigg er signal, then ?or? (when toggle enable) 111: select tcon [n] and tcon [n-1] on alternating frames. --------------------------------------------------- --------------------------------------------------- -------------- tcon [9:8] (tcon combination select) 000: normal tcon output 001: select tcon [n] ?and? with tcon [n-1] 010: select tcon [n] ?or? with tcon [n-1] 011: select tcon [n] ?xor? with tcon [n-1] 100: select tcon [n-1] rising edge as toggle trigg er signal (when toggle enable) 101: select tcon [n-1] rising edge as toggle trigg er signal, then ?and? (when toggle enable) 110: select tcon [n-1] rising edge as toggle trigg er signal, then ?or? (when toggle enable) 111: select tcon [n] and tcon [n-1] reference odd s ignal as alternating frames. --------------------------------------------------- --------------------------------------------------- -------------- tcon [3] (tcon combination select) 000: normal tcon output 001: select tcon [3] ?and? with tcon [2] 010: select tcon [3] ?or? with tcon [2] 011: select tcon [3] ?xor? with tcon [2] 100: select tcon [2] rising edge as toggle trigger signal (when toggle enable)
realtek lrh series-gr 75 101: select tcon [2] rising edge as toggle trigger signal, then ?and? (when toggle enable) 110: select tcon [2] rising edge as toggle trigger signal, then ?or? (when toggle enable) 111: select reset(odd=0) or set(odd=1) tcon [3] by dvs, when toggle function enable --------------------------------------------------- --------------------------------------------------- -------------- tcon [2] (clock toggle function )//toggle function is inactive 00x: normal tcon output 010: select dclk/2 when tcon [2] is ?0? 011: select dclk/2 when tcon [2] is ?1? 100: select dclk/4 when tcon [2] is ?0? 101: select dclk/4 when tcon [2] is ?1? 110: select dclk/8 when tcon [2] is ?0? 111: select dclk/8 when tcon [2] is ?1? --------------------------------------------------- --------------------------------------------------- -------------- tcon [1] xx0: normal tcon output xx1: reverse-control signal output --------------------------------------------------- --------------------------------------------------- -------------- tcon [0] 00x: normal tcon output 010: even ?rev? 18/24-bit function (?rev0? on tcon [0]) odd ?rev? 18/24-bit function (?rev1? on tcon [ 1]) 011: all ?rev? 36/48-bit function (?rev? on tcon [ 0], can also on tcon [1]) 100: even data output inversion controlled by tcon [0] is ?0? odd data output inversion controlled by tcon [ 1] is ?0? 101: even data output inversion controlled by tcon [0] is ?1? odd data output inversion controlled by tcon [ 1] is ?1? dot masking address: 8c-5f/67/6f/77 tc_dot_masking_ctrl d efault: 00h bit mode function 7:3 r/w reserved to 0 2 r/w red dot masking enable 0: disable (default) 1: enable 1 r/w green dot masking enable 0: disable (default) 1: enable
realtek lrh series-gr 76 0 r/w blue dot masking enable 0: disable (default) 1: enable when applying dot masking, the timing setting for t con will be real tcon_mask_sta = tcon_sta+2 real tcon_mask_end = tcon_end +2 tcon [0] ~ tcon [13] control registers address map address data(# bits) default 0a,09,08 tcon [0]_vs_reg (11) 0d,0c,0b tcon [0]_hs_reg (11) 0e tcon [0]_ctrl_reg 00 0f reserved 12,11,10 tcon [1]_vs_reg (11) 15,14,13 tcon [1]_hs_reg (11) 16 tcon [1]_ctrl_reg 00 17 reserved 1a,19,18 tcon [2]_vs_reg (11) 1d,1c,1b tcon [2]_hs_reg (11) 1e tcon [2]_ctrl_reg 00 1f reserved 22,21,20 tcon [3]_vs_reg (11) 25,24,23 tcon [3]_hs_reg (11) 26 tcon [3]_ctrl_reg 00 27 reserved 2a,29,28 tcon [4]_vs_reg (11) 2d,2c,2b tcon [4]_hs_reg (11) 2e tcon [4]_ctrl_reg 00 2f reserved 32,31,30 tcon [5]_vs_reg (11) 35,34,33 tcon [5]_hs_reg (11) 36 tcon [5]_ctrl_reg 00
realtek lrh series-gr 77 37 reserved 3a,39,38 tcon [6]_vs_reg (11) 3d,3c,3b tcon [6]_hs_reg (11) 3e tcon [6]_ctrl_reg 00 3f reserved 42,41,40 tcon [7]_vs_reg (11) 45,44,43 tcon [7]_hs_reg (11) 46 tcon [7]_ctrl_reg 00 47 reserved 4a,49,48 tcon [8]_vs_reg (11) 4d,4c,4b tcon [8]_hs_reg (11) 4e tcon [8]_ctrl_reg 00 4f reserved 52,51,50 tcon [9]_vs_reg (11) 55,54,53 tcon [9]_hs_reg (11) 56 tcon [9]_ctrl_reg 00 57 reserved 5a,59,58 tcon [10]_vs_reg (11) 5d,5c,5b tcon [10]_hs_reg (11) 5e tcon [10]_ctrl_reg 00 5f tcon [10]_ctrl_reg 62,61,60 tcon [11]_vs_reg (11) 65,64,63 tcon [11]_hs_reg (11) 66 tcon [11]_ctrl_reg 00 67 tcon [11]_ctrl_reg 00 6a,69,68 tcon [12]_vs_reg (11) 6d,6c,6b tcon [12]_hs_reg (11) 6e tcon [12]_ctrl_reg 00 6f tcon [12]_ctrl_reg 00
realtek lrh series-gr 78 72,71,70 tcon [13]_vs_reg (11) 75,74,73 tcon [13]_hs_reg (11) 76 tcon [13]_ctrl_reg 00 77 tcon [13]_ctrl_reg 00 control for lvds address: 8c-a0 lvds_ctrl0 default: 00h bit mode function 7 -- reserved to 0 5 r/w power up lvds even-port (pin 86~95) 0: power down (default) 1: normal 4 r/w power up lvds odd-port (pin 74~83) 0: power down (default) 1: normal 3:2 r/w watch dog model 00: enable watch dog(default) 01: keep pll vco = 1v 1x: disable watch dog 1 r/w reserved to 0 0 r watch dog control flag 0: watch dog not active (default) 1: watch dog active, reset pll and set vco = 1v address: 8c-a1 lvds_ctrl1 default: 14h bit mode function 7 r/w cklagl: inverse the ck port 0: lead (default) 1: lag t/14 5:3 r/w ststl [2:0]: select test attribute 000: wd 001: vcom 010: ib40u (default) 011: ibvocm 100: plltst-fbak
realtek lrh series-gr 79 101: plltst-fin 110: lvtst-ckdin 111: lvtst-lvdsin[6] 2:0 r/w lvds output common mode (default: 100) 000 : 1.07v 001 : 1.12v 010 : 1.17v 011 : 1.22v 100 : 1.29v (default) 101 : 1.33v 110 : 1.38v 111 : 1.43v address: 8c-a2 lvds_ctrl2 default: 43h bit mode function 7:6 r/w sbgl 00: 1.164v 01: 1.244v (default) 10: 1.324v 11: 1.404v 5 r/w enib40ux2l: double the lvds output swing 0: 1x 1: 2x 4 r/w sibxl : select 20ua source if disp_type=lvds 0: from bandgap (default) 1: from adc 3 r/w pll lock edge 0: positive 1: negative 2:0 r/w sibgenl (lvds current source correction), 40u: lvds driving current, 100u: lvds vocm(default) 000 : 25ua/ 62.5ua 001 : 30ua/ 75ua 010 : 35ua/ 87.5ua 011 : 40ua/ 100ua (default) 100 : 45ua/ 112.5ua 101 : 50ua/ 125ua 110 : 55ua/ 137.5ua
realtek lrh series-gr 80 111 : 60ua/ 150ua address: 8c-a3 lvds_ctrl3 default: 1ch bit mode function 7 r/w envbpbl: enable vco_d2s current up 0: disable (default) 1: enable 6 r/w reserved to 0 5:3 r/w sil [2:0] : pll charge pump current (i=5ua+5ua*code) (default : 011) 2:1 r/w srl [1:0] : pll resistor (r=6k+2k*code) (default: 10) 0 r/w bmts : bit-mapping table select 0: table 1 (default) 1: table 2 tclk+ lvds bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 txe0 er1 er0 eg0 er5 er4 er3 er2 er1 er0 eg0 er5 txe1 eg2 eg1 eb1 eb0 eg5 eg4 eg3 eg2 eg1 eb1 eb0 txe2 eb3 eb2 den vs hs eb5 eb4 eb3 eb2 den*6 vs*5 txe3 er7 er6 rsv eb7 eb6 eg7 eg6 er7 er6 rsv*7 eb7 txo0 or1 or0 og0 or5 or4 or3 or2 or1 or0 og0 or5 txo1 og2 og1 ob1 ob0 og5 og4 og3 og2 og1 ob1 ob0 txo2 ob3 ob2 den vs hs ob5 ob4 ob3 ob2 den*2 vs*1 txo3 or7 or6 rsv ob7 ob6 og7 og6 or7 or6 rsv*3 ob7 table 1 bit-mapping 6bit(5~0)+2bit(7~6) tclk+ lvds bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 txe0 er3 er2 eg2 er7 er6 er5 er4 er3 er2 eg2 er7 txe1 eg4 eg3 eb3 eb2 eg7 eg6 eg5 eg4 eg3 eb3 eb2 txe2 eb5 eb4 den vs hs eb7 eb6 eb5 eb4 den*6 vs*5 txe3 er1 er0 rsv eb1 eb0 eg1 eg0 er1 er0 rsv*7 eb1 txo0 or3 or2 og2 or7 or6 or5 or4 or3 or2 og2 or7 txo1 og4 og3 ob3 ob2 og7 og6 og5 og4 og3 ob3 ob2 txo2 ob5 ob4 den vs hs ob7 ob6 ob5 ob4 den*2 vs*1 txo3 or1 or0 rsv ob1 ob0 og1 og0 or1 or0 rsv*3 ob1 table 2 bit-mapping 6bit(7~2)+2bit(1~0) address: 8c-a4 lvds_ctrl4 default: 80h bit mode function 7:6 r/w e_rsv : even port reserve signal select 11: always ?1?
realtek lrh series-gr 81 10: always ?0? 01: tcon [11] 00: pwm_0 5:4 r/w e_den : even port data enable signal select 11: always ?1? 10: always ?0? 01: tcon [9] 00: dena 3:2 r/w e_vs : even port vs signal select 11: always ?1? 10: dena 01: tcon [7] 00: dvs 1:0 r/w e_hs : even port hs signal select 11: always ?1? 10: dena 01: tcon [5] 00: dhs address: 8c-a5 lvds_ctrl5 default: 80h bit mode function 7:6 r/w o_rsv : odd port reserve signal select 11: always ?1? 10: always ?0? 01: tcon [13] 00: pwm_1 5:4 r/w o_den : odd port data enable signal select 11: always ?1? 10: always ?0? 01: tcon [9] 00: dena 3:2 r/w o_vs : odd port vs signal select 11: always ?1? 10: dena 01: tcon [7] 00: dvs 1:0 r/w o_hs : odd port hs signal select 11: always ?1? 10: dena
realtek lrh series-gr 82 01: tcon [5] 00: dhs address: 8c-a6 lvds_ctrl6 default: 02h bit mode function 7 r/w rsds differential pair pn swap (data) (also refer to cr29[6:4]) 0: no swap (default) 1: swap 6:4 -- reserved to 0 3 r/w dalagl: inverse the data port 0: lead (default) 1: lag t/14 2 r/w reserved 1 r/w endul: odd clock pair current double(odd b port) 0: 1x 1: 2x (default) 0 -- reserved to 0 test function register::pin_config_addr_port 0x8d name bit r/w default description config pin_config_addr_p ort 7:0 r/w 00 address port for pin configuration control access register::pin_config_data_port 0x8e name bit r/w default description config pin_config_data_p ort 7:0 r/w 00 data port for pin configuration control access register::test_mode 0x00 name bit r/w default description config select_data_test_mo de 7 r/w 0 select data test mode msb(for 48pin) 0: select data test mode [15:0] to pin 36~21 1: select data test mode [29:16] to pin 36~21 test mode select 6:5 r/w 00 00:normal 01:test_output mode others are reserved
realtek lrh series-gr 83 test_output_mode 4 r/w 0 0:select data test mode select data test output to 128pin{ 124~121,114~108,105~100,72~64, 54~51} depend on bit6~bit4 48pin(36~21)depend on bit7~bit4 1:pll test mode {dpll, m2pll,audio_pll, mpll, ckt_pll27x, ck108_pll27x, dpllstatus,test1out, test2out, fav4, xclk} will be outputted to 128pin{124,113,51,71,110,101,108, 105,54,67,64} 48pin{29,37,21,35,none,none,25,23,27,3 3,31} when set to 1, clock frequency of some test pin could be divided by assigning its corresponding tst_clk_ctrl data_test_mode 3:0 r/w 0 0000: 1?b0, z0tst[3:0], pclk_tst, red[9:2], green[9:2], blue[9:2] through vgip 0001: 1'b0, z0tst[3:0], adc_clk, red[7:0], green[7:0], blue[7:0] after scale down 0010: z0tst[3:0], adc_clk, ivs_dly, ihs_dly, ifd_odd, iena, vsd_den, vsd_act,auto_hs, auto_vs, auto_field, 1'b0, coast, test_s1, test_s2, clamp_g, clamp_br, sog_in0, sog_in1, fav4,final_pe_com, t_s[1:0], pe_extrab, high_88, recur_delay_chain_en, high_127 0011: z0tst[3:0], adc_clk, mcuwr, mcurd, mcu_adr_inc, min[7:0], mcuwr, mcurd, madr[7:0], sdmout_tst[3:0] 0100: 1'b0, adc_clk, raw_vs, raw_hs, raw_odd, raw_den, sdmout_tst[3:0], green[9:0], red[9:0] through vgip 0101: 1'b0, adc_clk, red[9:0], green[9:0], raw_vs, raw_hs, en_flag, meas_ihs, hsout_sync_proc, coast, clamp_g, clamp_br 0110: 1'b0, adc_clk, raw_vs, raw_hs, test_s1, test_s2, raw_filed, blue[9:0], green[9:0], hs0_schmitt, hs1_schmitt, 1'b0 0111: 3?b0 , adc_clk, green[9:0], iclk_tst, raw_vs, raw_hs, raw_filed, fifo_clk, internal_crystal, test_s1, test_s2, sync_pro_tst[7:0] 1000: audio_dac enable signal test pin: dac_2ch_otpin[29:0] 1001: vsdmain test mode: pclk_tst, 3?b0, vsd_act, vsd_den, vsd_pr[7:0], vsd_y[7:0], vsd_pb[7:0] 1010: auto_soy test mode reserved 1011: 6?b0, adc snr rgb 8-bitx3 output 1100: embedded mcu test out mode
realtek lrh series-gr 84 1101: hdmi test in mode 128 pin hdmi_tst_in [29:0] assign to {124~121, 114~108, 105~100, 72~64, 54~51} 48 pin hdmi_tst_in [15:0] assign to {36~21} 1110: hdmi test out mode 128 pin hdmi_tst_out [29:0] assign to {124~121, 114~108, 105~100, 72~64, 54~51} 48 pin hdmi_tst_out [15:0] assign to {36~21} 1111: 6?b0, adc snr rgb 8 - bitx3 output reserved when set to 0010/0110/0111,test_s1 & test_s2 can be assigned by ?select_tst_s1s2? others are reserved register::tst_clk_ctrl0 0x01 name bits read/ write reset state comments config dpll_oen 7 r/w 0 dpll frequency output enable 0: output disabled 1: output enabled m2pll_oen 6 r/w 0 m2pll frequency output enable 0: output disabled 1: output enabled audio_pll_oen 5 r/w 0 audio_pll frequency output en able 0: output disabled 1: output enabled mpll_oen 4 r/w 0 mpll frequency output enable 0: output disabled 1: output enabled clk108_pll27x_ oen 3 r/w 0 clk108_pll27x frequency output enable 0: output disabled 1: output enabled test1out_oen 2 r/w 0 test1out frequency output enab le 0: output disabled 1: output enabled test2out_oen 1 r/w 0 test2out frequency output enab le 0: output disabled 1: output enabled fav4_oen 0 r/w 0 fav4 frequency output enable 0: output disabled 1: output enabled register::tst_clk_ctrl1 0x02 name bits read/ write reset state comments config xclk_oen 7 r/w 0 xclk frequency output enable 0: output disabled 1: output enabled ckt_pll27x_oen 6 r/w 0 ckt_pll27x frequency output enable
realtek lrh series-gr 85 0: output disabled 1: output enabled rev 5:0 --- --- reserved register::tst_clk_ctrl2 0x03 name bit r/w default description config mpll_div_ctrl 7:6 r/w 00 mpll frequency is divided by 00:1 01:2 10:4 11:8 dpll_div_ctrl 5:4 r/w 00 dpll frequency is divided by 00:1 01:2 10:4 11:8 m2pll_div_ctrl 3:2 r/w 11 m2pll frequency is divided by 00:1 01:2 10:4 11:8 audio_pll_div_ct rl 1:0 r/w 00 audio pll frequency is divided by 00:1 01:2 10:4 11:8 register:: tst_clk_ctrl3 0x04 name bit r/w default description config fav4 _div_ctrl 7:6 r/w 00 fav frequency is divided by 00:1 01:2 10:4 11:8 test1out _div_ctrl 5:4 r/w 00 test1out frequency is divided by 00:1 01:2 10:4
realtek lrh series-gr 86 11:8 test2out _div_ctrl 3:2 r/w 00 test2out frequency is divided by 00:1 01:2 10:4 11:8 108_pll27xdiv_ctr l 1 r/w 0 0:divided by 1 1:divided by 4 ckt_pll27x div_ctrl 0 r/w 0 0:divided by 1 1:divided by4 register:: select_tst_s1s2 0x05 name bit r/w default description config reserved 7 r/w 0 reserved select_tst_s1 6:4 r/w 001 select test function of test_s1 3?b000: dpll clock (tie low now) 3?b001: plls fbk clock 3?b010: ckoad2(high speed) 3?b011: pll status 3?b100: hsout 3?b101: adc clock(from plls)(high speed) 3?b110: empty flag 3?b111: bvs(video8) reserved 3 r/w 0 reserved select_tst_s2 2:0 r/w 010 select test function of test_s1 3?b000: plls phase swallow clock (high speed) 3?b001: dpll status(tie low now) 3?b010: plls phase0 clock(high speed) 3?b011: m2pll clock(not in apll) 3?b100: hsfb 3?b101: tp2_mx5 3?b110: full flag 3?b111: bhs(video8)
realtek lrh series-gr 87 register:: select_tstinclock 0x06 name bit r/w default description config dpll_tst_in 7 r/w 0 0:normal 1:dclk enter from pin 34 adcpll_tst_in 6 r/w 0 0:normal 1:adc clk enter from pin 35 m2pll_tst_in 5 r/w 0 0:normal 1:m2pll clk enter from pin 36 hdmi_cp_aclk _tst_in 4 r/w 0 0:normal 1:hdmi_cp_aclk enter from pin 37 hdmi_cp_clk _tst_in 3 r/w 0 0:normal 1:hdmi_cp_clk enter from pin 38 scan_clk_tst_i n 2 r/w 1 0:normal 1:scan clk enter from pin 21 dpll_ndiv2_en 1 r/w 0 dpll test mode divider enable 0:use pin 34 div2 as dclk 1:use pin 34 as dclk mpll_tst_in 0 r/w 0 0:normal 1:mpll clk enter from pin 33 test mode in fifo register:: adc test mode 0x07 name bit r/w default description config adc_test_mode 7 r/w 0 0:disable 1:enable adc_test_mode _2 6 r/w 0 useless fifo_test_mode 5 r/w 0 0:disable 1:enable test the crc from fifo and open the pattern gen to d domain. pattern gen seed ( r = 01,g=00,b=00) adc_test_start 4 r 0 under adc_test_mode = 1, adc_test_start will high when the new fifo is full then read out data from fifo by sending dclk from outside test pin. rev 3:0 --- --- reserved
realtek lrh series-gr 88 register:: adc test mode addr msb 0x08 name bit r/w default description config rev 7:2 --- --- reserved adc_test_addr[ 9:8] 1:0 r/w 0x00 read the fifo initial addr. register:: adc test mode addr lsb 0x09 name bit r/w default description config adc_test_addr[ 7:0] 7:0 r/w 0x04 read the fifo initial addr. register:: adc fifo crc 0x0a name bit r/w default description config new_fifo_crc[2 3:16] 7:0 r 0 new fifo crc register:: adc fifo crc 0x0b name bit r/w default description config new_fifo_crc[1 5:8] 7:0 r 0 new fifo crc register:: adc fifo crc 0x0c name bit r/w default description config new_fifo_crc[7: 0] 7:0 r 0 new fifo crc embedded osd address: 90 osd_addr_msb (osd address msb 8-bit) bit mode function 7:0 r/w osd msb 8-bit address address: 91 osd _addr_lsb (osd address lsb 8-bit) bit mode function 7:0 r/w osd lsb 8-bit address address: 92 osd_data_port (osd data port)
realtek lrh series-gr 89 bit mode function 7:0 w data port for embedded osd access refer to the embedded osd application note for the detailed. address: 93 osd_scramble default: 05h bit mode function 7 r/w bist start 0: stop (default) 1: start (auto clear) 6 r bist result 0: fail (default) 1: success 5 r mcu writes data when osd on status (queue 1 byte da ta) 0: mcu writes data to osd but not to real position (there is one level buffer here) 1: mcu doesn?t write data, or data has been writte n to real position 4 r double_buffer_write_status 0: double buffer write out is finish, or data write to double buffer is not ready, or no double buffer function. 1: after data write to dbuf and before dbuf write o ut, such that double buffer is busy. 3 r/w osdadrhsb 0: if initial address lower than or equal to 12k 1: if initial address higher than 12k the bit will be designed to control 16.5k bytes sra m. however it will have no effect for window setting. also please remember to set {osdadr hsb, osdadrmsb(cr90), osdadrlsb(cr91) } again while you like to r/w a new address. 2:0 r/w double buffer depth (default=6) 000~101=>1~6 address: 94 osd_test bit mode function 7:0 r/w testing pattern address:95~97 reserved digital filter address: 98 digital_filter_ctrl default: 00h bit mode function 7:4 r/w access port write enable 0000: disable
realtek lrh series-gr 90 0001: phase access port 0010: negative smear access port 0011: positive smear access port 0100: negative ringing access port 0101: positive ringing access port 0110: mismatch access port 0111: y(b)/pb(g)/pr(r) channel digital filter enabl e 1xxx: noise reduction access port 3:2 r/w two condition occur continuous (ringing to smear) 00: disable( hardware is off , depend on firmware) 01: only reduce ringing condition 10: only reduce smear condition 11: no adjust (hardware is on, but do nothing) 1 r/w when noise reduction and mismatch occur, select 0: mismatch 1: noise reduction 0 -- reserved to 0 address: 99 digital_filter_port default: 00h digital_filter_ctrl[7:4] = 0111 bit mode function 7 r/w y en (g) : function enable 0: function disable 1: function enable 6 r/w pb en (b) : function enable 0: function disable 1: function enable 5 r/w pr en (r) : function enable 0: function disable 1: function enable 4 r/w initial value : 0: raw data 1: extension 3:0 -- reserved to 0 digital_filter_ctrl[7:4] = 000 ~ 110 bit mode function 7 r/w en : function enable
realtek lrh series-gr 91 0: function disable 1: function enable 6:4 r/w thd_offset threshold value of phase and mismatch and noise red uction or offset value of smear and ringing 3:2 r/w div: divider value of phase and mismatch or offset valu e of smear and ringing 00: 0 01: 1 10: 2 11: 3 1:0 -- reserved to 0 thd_offset define: the thd value definition of phase enhance function bit6~4 000 001 010 011 100 101 110 111 value 112 128 144 160 176 192 208 224 the offset value definition of smear and ringing re duce function bit6~4 000 001 010 011 100 101 110 111 value no use 16 32 48 64 80 96 112 the thd value definition of mismatch enhance functi on bit6~4 000 xx1 value 1 2 the thd value definition of noise reduction functio n bit6~4 000 001 010 011 100 101 110 111 value 0 1 2 3 4 5 6 7 color conversion (input domain) address: 9c yuv_rgb_ctrl (yuv <-> rgb control register) defau lt: 10h bit mode function 7 r/w y_out shift 0: bypass 1: y_out+64 6 r/w cbcr_out_shift: 0 : bypass 1: cb_out+512, cr_out+512 5 --- reserved 4 r/w color conversion type 0: yuv->rgb 1: rgb->yuv (u,v are translated to unsigned 10-bit number) 3 r/w enable yuv/rgb coefficient access: 0: disable 1: enable if this bit is set to 0, the address of the data po rt will reset to 0, and continuously writes 18 byte s 2 r/w cb cr clamp 0: bypass
realtek lrh series-gr 92 1: cb-512, cr-512 (msb inversion) 1 r/w y gain/offset: 0 : bypass 1: (y-64)*1.164 0 r/w enable yuv <-> rgb conversion: 0: disable yuv<->rgb conversion (default) 1: enable yuv<->rgb conversion address: 9d yuv_rgb_coef_data bit mode function 7:0 w coef_data[7:0] yuv->rgb matrix : (cr9c[4] = 0) - cr9c[1] = 0, cr9c[2] = 1, r = h00*y + h01*(cb-512) + h02*(cr-512) g = h10*y + h11*(cb-512) + h12*(cr-512) b = h20*y + h21*(cb-512) + h22*(cr-512) - cr9c[1] = 1, cr9c[2] = 1, r = h00*(1.164*(y-64)) + h01*(cb-512) + h02*(cr-512 ) g = h10*(1.164*(y-64)) + h11*(cb-512) + h12*(cr-512 ) b = h20*(1.164*(y-64)) + h21*(cb-512) + h22*(cr-512 ) rgb->yuv matrix : (cr9c[4] = 1, cr9c[2:1] = 00) y = h00*r + h01*g + h02*b cb = h10*r + h11*g + h12*b cr = h20*r + h21*g + h22*b a ll ? h ? coefficients are expressed as 2 ? s complement with 4-bit signed-extension, 2-bit int eger and 10-bit fractional number. (0x0400 means 1.0) when color conversion setting is yuv->rgb (cr9c[4]= 0), h00, h10 and h20 is not effective(force to 1.0 internally). integer part is only effective for h02, h21. for ot her coefficients, integer part must be the same as signed- extension. coefficient sequence (18-byte) : h00 (high-byte), h 00 (low-byte), h01 (high-byte), h01 (low-byte), h02 (high-byte), h02 (low-byte), h10 (h igh-byte), h10 (low-byte), h11 (high-byte), h11 (low-byte), h12 (high-byte), h12 (low-byte), h2 0 (high-byte), h20 (low-byte), h21 (high-byte), h21 (low-byte), h22 (high-byte), h22 ( low-byte). default value: h00=0105h,h01=0202,h02=0063h,h10=ff6 9h,h11=fed8h,h12=01c0h,h20=01c0h,h21=fe89h,h22=ff8h
realtek lrh series-gr 93 paged control register address: 9f page_sel default: 00h bit mode function 7:5 r/w reserved to 0 4:0 r/w page selector (cra0~crff) page 0: embedded adc/abl/lvr/smith trigger page 1: pll page 2: hdmi/dvi/hdcp page 3: liveshowtm control page 4: sdram control page 5: sdr_fifo control page 6: reserved page 7: vivid color/dcc/icm page 8: reserved page 9: reserved page a: reserved page b: displayport page c: displayport page d: mcu page e: mcu page f: mcu page 10: sdram pin control others: reserved
embedded adc (page 0) register::adc_power_sog_soy_control[7:0] 0xba name bit r/w default description config reserved 7:6 r/w 0b0 reserved adc_sog1_dac 5:0 r/w 0b100000 reserved(sog0/1 dac input), 1-a only, sog1 reserved. register:: adc_2x_sample[7:0] 0xbb name bit r/w default description config adc_2x_sample[ 7] 7 r/w 0b0 adc 2x over sample (0:1x 1:2x) adc_2x_sample[ 6] 6 r/w 0b0 2x clock polarity (0:normal 1:inverted) adc_2x_sample[ 5] 5 r/w 0b0 1x clock polarity (0:normal 1:inverted) adc_2x_sample[ 4:3] 4:3 r/w 0b00000 reserved adc_2x_sample[ 2] 2 r/w 0b0 clock input select (0:from ckoad_v33, 1:from ckoad_v12) adc_2x_sample[ 1:0] 1:0 r/w 0b0 reserved register:: adc_clock[7:0] 0xbc name bit r/w default description config adc_clock[7] 7 r/w 0b0 input clock polarity (0:negative 1:positive) adc_clock[6] 6 r/w 0b0 output divider clock polarity (0:normal 1:inverted) adc_clock[5:4] 5:4 r/w 0b0 adc_out_pixel delay (00:1.05n 01:1.39n 10:1.69n 11:1.97n) adc_clock[3] 3 r/w 0b0 1x or 2x from apll (0:1x 1:2x) adc_clock[2] 2 r/w 0b0 single ended or diff. clock from apll (0:diff. 1:single ended) adc_clock[1:0] 1:0 r/w 0b1 duty stablizer(00: 48% 01:50% 10: 51% 11:52%)
register:: adc_test[7:0] 0xbd name bit r/w default description config adc_test[7] 7 r/w 0b0 r,b clamp vaule from g (0: no 1: yes) adc gain calibration adc_test[6:4] 6:4 r/w 0b000 test ouput selection (pad: sogin0, sogin1) sogin0 (000:x 001:gnd 010:gnd 011:gnd 100:gnd 101:vmid 110:voffset 111:vdd) adc_test[3] 3 r/w 0b0 reserved adc_test[2] 2 r/w 0b0 reserved adc_test[1:0] 1:0 r/w 0b00 clock output divider (00: 1/1 01: 1/2 10: 1/3 11: 1/4) register::rgb gain_lsb 0xbe name bit r/w default description config reserved 7:6 r/w 0b0 reserved adc_gai_red[1:0 ] 5:4 r/w 0x0 red channel gain adjust[1:0] adc_gai_grn[1:0 ] 3:2 r/w 0x0 green channel gain adjust[1:0] adc_gai_blu[1:0 ] 1:0 r/w 0x0 blue channel gain adjust[1:0] register::rgb offset_lsb 0xbf name bit r/w default description config reserved 7:6 r/w 0b0 reserved adc_off_red[1:0 ] 5:4 r/w 0x0 red channel offset adjust[1:0] adc_off_grn[1:0 ] 3:2 r/w 0x0 green channel offset adjust[1:0] adc_off_blu[1:0 ] 1:0 r/w 0x0 blue channel offset adjust[1:0] register::red gain_msb 0xc0
name bit r/w default description config adc_gai_red[9:2 ] 7:0 r/w 0x80 red channel gain adjust[9:2] register::green gain_msb 0xc1 name bit r/w default description config adc_gai_grn[9:2 ] 7:0 r/w 0x80 green channel gain adjust[9:2] register::blue gain_msb 0xc2 name bit r/w default description config adc_gai_blu[9:2 ] 7:0 r/w 0x80 blue channel gain adjust[9:2] register::red offset_msb 0xc3 name bit r/w default description config adc_off_red[9:2 ] 7:0 r/w 0x80 red channel offset adjust[9:2] register::green offset_msb 0xc4 name bit r/w default description config adc_off_grn[9:2 ] 7:0 r/w 0x80 green channel offset adjust[9:2] register::blue offset_msb 0xc5 name bit r/w default description config adc_off_blu[9:2 ] 7:0 r/w 0x80 blue channel offset adjust[9:2] register:: adc_power[7:0] 0xc6 name bit r/w default description config adc_power[7] 7 --- 0 reserved adc_power[6] 6 r/w 0 adc clock power on (0: power down
1: power on) adc_power[5] 5 r/w 0b0 sog_adc0 power on (0: power down 1: power on) adc_power[4] 4 --- 0 reserved adc_power[3] 3 r/w 0b1 bandgap power on (0: power down 1: power on) adc_power[2] 2 r/w 0b0 red channel adc power on (0: power down 1: power on) adc_power[1] 1 r/w 0b0 green channel adc power on (0: power down 1: power on) adc_power[0] 0 r/w 0b0 blue channel adc power on (0: power down 1: power on) register:: adc_ibias0[7:0] 0xc7 name bit r/w default description config adc_ibias0[7:4] 7:4 r/w 0101 reserved adc_ibias0[3:2] 3:2 r/w 0b01 bias current of lvds20u (00:16u 01:20u 10:24u 11:28u) adc_ibias0[1:0] 1:0 r/w -- reserved register:: adc_ibias1[7:0] 0xc8 name bit r/w default description config adc_ibias1[7:6] 7:6 r/w 0b01 reserved adc_ibias1[5:4] 5:4 r/w 01 reserved adc_ibias1[3:2] 3:2 r/w 0b01 bias current of lsadc6 (00:16u 01:20u 10:24u 11:28u) adc_ibias1[1:0] 1:0 r/w 0b01 bias current of lsadc10 (00:16u 01:20u 10:24u 11:28u) register:: adc_ibias2[7:0] 0xc9 name bit r/w default description config adc_ibias2[7:5] 7:5 r/w 0b01 reserved adc_ibias2[4:2] 4:2 r/w 0b001 bias current of dac (000:22.5u 001:25u 010:27.5u 011:30u) adc_ibias2[1:0] 1:0 r/w 0b01 bias current of audio_dac (00:32u 01:40u 10:48u 11:56u)
register:: adc_ ibias3[7:0] 0xca name bit r/w default description config adc_ibias3[7:6] 7:6 r/w 0b01 bias current of adc_sf (00:15u 01:20u 10:25u 11:30 adc_ibias3[5:3] 5:3 r/w 0b011 bias current of 1.2v mbias (000:17.5u 001:20u 010:22.5u 011:25u 100:27.5u 101:30u 110:32.5u 111:35u) adc_ibias3[2:0] 2:0 r/w 0b100 bias current of sh,mdac (000:6u 001:8u 010:10u 011:12u 100:14 101:17 110:20u 111:24u) bias current of subadc (000:12u 001:18u 010:24u 011:27u 100:30u 101:33u 110:39u 111:45u) subadc (000:10u 001:10u 010:10u 011:10u 100:20u 101:20u 110:20u 111:20u) register:: adc_ ibias4[7:0] 0xcb name bit r/w default description config adc_ibias4[7:6] 7:6 r/w 0b01 bias current of dpll20u (00:16u 01:20u 10:24u 11:28u) adc_ibias4[5:4] 5:4 r/w 0b01 bias current of apll_ib60u (00:48u 01:60u 10:72u 11:84u) adc_ibias4[3:2] 3:2 r/w 0b01 reserved adc_ibias4[1:0] 1:0 r/w 0b01 bias current of m2pll_20u (00:16u 01:20u 10:24u 11:28u) register:: adc_ vbias0[7:0] 0xcc name bit r/w default description config adc_vbias0[7:6] 7:6 r/w 0b01 reserved adc_vbias0[5:4] 5:4 r/w 0b01 1. 5v regulator adjuset (00:1.4 01:1.5 10:1.6 11:1.7) adc_vbias0[3:2] 3:2 r/w 0b00 reserved adc_vbias0[1:0] 1:0 r/w 0b01 bandgap voltage (00:1.15 01:1.25 10:1.34 11:1.42)
register:: adc_vbias1[7:0] 0xcd name bit r/w default description config adc_vbias1[7] 7 r/w 0b0 adc gain calibration (0: normal 1: calibration) adc_vbias1[6] 6 r/w 0b0 r channel clamp to -300mv (0: 0mv 1:-300mv) adc_vbias1[5] 5 r/w 0b0 g channel clamp to -300mv (0: 0mv 1:-300mv) adc_vbias1[4] 4 r/w 0b0 b channel clamp to -300mv (0: 0mv 1:-300mv) adc_vbias1[3] 3 r/w 0b1 sh boot enable (0:no boost, 1: boost) adc_vbias1[2] 2 r/w 0b0 sh boot adjuest (0:0.8, 1:0.85) adc_vbias1[1:0] 1:0 r/w 0b01 reserved register:: adc_ctl_rgb[7:0] 0xce name bit r/w default description config adc_ctl_rgb[7:4 ] 7:4 r/w 0b1000 sh gain(0000:0.95, 0001:1, 0010:1.05, 0011:1.1, 0100:1.15, 0101:1.2, 0110:1.25, 0111:1.3, 1000:1.35, 1001:1.4, 1010:1.45) adc_ctl_rgb[3] 3 r/w 0b0 dual (0: input0, 1:force to ground ) adc_ctl_rgb[2] 2 r/w 0b1 single ended or diff. input (0: single ended 1: diff) adc_ctl_rgb[1:0 ] 1:0 r/w 0b10 bandwidth (00: 75m 01: 150m 10: 300m 11: 500m) register:: adc_ctl_red[7:0] 0xcf name bit r/w default description config adc_ctl_red[7] 7 r/w 0b0 rgb/yprpb clamp (0: rgb 1:yprpb) //adc_vbias1[6]==0 adc_ctl_red[6:4 ] 6:4 r/w 0b100 clamp voltage (0v~700mv, step=100mv) adc_ctl_red[3] 3 r/w 0b0 offset depends on gain (0: rgb yes, yprpb no 1:rgb no, yprpb no)
adc_ctl_red[2:0 ] 2:0 r/w 0b000 red channel adc fine tune delay, step=90ps register:: adc_ctl_grn[7:0] 0xd0 name bit r/w default description config adc_ctl_grn[7] 7 r/w 0b0 rgb/yprpb clamp (0: rgb 1:yprpb) adc_ctl_grn[6: 4] 6:4 r/w 0b100 clamp voltage (0v~700mv, step=100mv) adc_ctl_grn[3] 3 r/w 0b0 offset depends on gain (0: rgb yes, yprpb no 1:rgb no, yprpb no) adc_ctl_grn[2: 0] 2:0 r/w 0b0 green channel adc fine tune delay, step=90ps register:: adc_ctl_blu[7:0] 0xd1 name bit r/w default description config adc_ctl_blu[7] 7 r/w 0b0 rgb/yprpb clamp (0: rgb 1:yprpb) adc_ctl_blu[6:4 ] 6:4 r/w 0b100 clamp voltage (0v~700mv, step=100mv) adc_ctl_blu[3] 3 r/w 0b0 offset depends on gain (0: rgb yes, yprpb no 1:rgb no, yprpb no) adc_ctl_blu[2:0 ] 2:0 r/w 0b0 blue channel adc fine tune delay, step=90ps register:: adc_sog_cmp[7:0] 0xd2 name bit r/w default description config adc_sog_cmp[7: 4] 7:4 r/w 0b0000 sog0 input mux select (0000: r0, 0001:g0, 0010:b0, 0011: sog0 ) adc_sog_cmp[3: 0] 3:0 r/w 0b0000 reserved register:: adc_dcr_ctrl[7:0] 0xd3 name bit r/w default description config adc_dcr_ctrl[7 ] 7 r/w 0 red_0 dc restore enable (0:disable 1:enable)
adc_dcr_ctrl[6 ] 6 r/w 0 green_0 dc restore enable (0:disable 1:enable) adc_dcr_ctrl[5 ] 5 r/w 0 blue_0 dc restore enable (0:disable 1:enable) adc_dcr_ctrl[4 ] 4 r/w 0 sog0 dc restore enable(0:disable 1:enable) adc_dcr_ctrl[3 ] 3 r/w 0 reserved adc_dcr_ctrl[2 ] 2 r/w 0 reserved adc_dcr_ctrl[1 ] 1 r/w 0 reserved adc_dcr_ctrl[0 ] 0 r/w 0 reserved register:: adc_clamp_ctrl0[7:0] 0xd4 name bit r/w default description config adc_clamp_ctr l0[7] 7 r/w 0 red_0 clamp enable (0: disable 1:enable) adc_clamp_ctr l0[6] 6 r/w 0 green_0 clamp enable (0: disable 1:enable) adc_clamp_ctr l0[5] 5 r/w 0 blue_0 clamp enable (0: disable 1:enable) adc_clamp_ctr l0[4] 4 r/w 0 sog0 clamp enable(0:disable 1:enable) adc_clamp_ctr l0[3] 3 r/w 0 reserved adc_clamp_ctr l0[2] 2 r/w 0 reserved adc_clamp_ctr l0[1] 1 r/w 0 reserved adc_clamp_ctr l0[0] 0 r/w 0 reserved register:: adc_clamp_ctrl1[7:0] 0xd5 name bit r/w default description config
adc_clamp_ctr l1[7] 7 r/w 0 red channel clamp voltage (0: ir=400mv 1: ir=100mv) adc_clamp_ctr l1[6] 6 r/w 0 red channel clamp source select (0: r0=dac, r1=ir 1: r0=ir, r1=dac) adc_clamp_ctr l1[5] 5 r/w 0 green channel clamp voltage (0: ir=400mv 1: ir=100mv) adc_clamp_ctr l1[4] 4 r/w 0 green channel clamp source select (0: g0=dac, g1=ir 1: g0=ir, g1=dac) adc_clamp_ctr l1[3] 3 r/w 0 blue channel clamp mode select (0: ir=400mv 1: ir=100mv) adc_clamp_ctr l1[2] 2 r/w 0 blue channel clamp source select (0: b0=dac, b1=ir 1: b0=ir, b1=dac) adc_clamp_ctr l1[1] 1 r/w 0 sog0 clamp - 300mv (0: noraml clamp 1:clamp -300m) //ir adc_clamp_ctr l1[0] 0 r/w 0 reserved register:: adc_clamp_ctrl2[7:0] 0xd6 name bit r/w default description config adc_clamp_ctr l2[7:6] 7:6 r/w 0b01 input0 and sog0 dc restore resister (00:open 01:500k 10:1m 11:5m) adc_clamp_ctr l1[5:4] 5:4 r/w 0b01 reserved adc_clamp_ctr l1[3] 3 r/w 0 rgb input range adjust (0: 0.5v-1.0v, 1:0.25v-1.25v) adc_clamp_ctr l1[2] 2 r/w 0 red channel clamp to top (0: noraml 1: top) adc_clamp_ctr l1[1] 1 r/w 0 green channel clamp to t op (0: noraml 1: top) adc_clamp_ctr l1[0] 0 r/w 0 blue channel clamp to top (0: noraml 1: top) register::adc_sog_dac_soy_control[7:0] 0xd7 name bit r/w default description config reserved 7:6 --- 0b0 reserved adc_sog0_dac[5 5:0 r/w 0b100000 sog0 dac input
:0] address:d8 ptnpos_h default: 00h bit mode function 7:4 r/w test pattern v position register [11:8] assign the test pattern digitized position in line after v_start. 3:0 r/w test pattern h position register [11:8] assign the test pattern digitized position in pixe l after h_start. address: d9 ptnpos_v_l bit mode function 7:0 r/w test pattern v position register [7:0] assign the test pattern digitized position in line after v_start.. address:da ptnpos_h_l bit mode function 7:0 r/w test pattern h position register [7:0] assign the test pattern digitized position in line after h_start.. use ptnpos to assign the pixel position after hsync leading edge that input signal digitized. each ti me the ptnpos is written, the digitized results will be lo aded into ptnrd, ptngd and ptnbd. for test issue, m ake the input signal a fixed pattern before ptnpos is writt en. then the same digitized output will be got. address: db ptnrd bit mode function 7:0 r test pattern red-channel digitized result. address: dc ptngd bit mode function 7:0 r test pattern green-channel digitized result. address:dd ptnbd bit mode function 7:0 r test pattern blue-channel digitized result. address:de test_pattern_ctrl default: 00h bit mode function 7 r/w enable test 0: finish (and result sequence is r-g-b) (default) 1: start 6:0 -- reserved register:: ebd_reglator_vol[7:0] 0xdf name bit r/w default description config ebd_reglator_ vol[7:6] 7:6 r/w 0b00 reserved rbg33 5:4 r/w 00 select bandgap output voltage @ tt60 00 : vbg = 1.22 v 01 : vbg = 1.13 v 10 : vbg = 1.32 v 11 : vbg = 1.41 v vinsel 3 r/w 0 select reference voltage to reg_op 0 : from bandgap
1 : from ? vdd of power supply* resistance ratio ? vsel 2:0 r/w 000 select output voltage of regulator 000 : 1.203 v 001 : 1.143 v 010 : 1.085 v 011 : 1.246 v 100 : 1.298 v 101 : 1.355 v 110 : 1.424 v 111 : 1.508 v
abl(page 0) address: e2 auto_black_level_ctrl1 default: 00h bit mode function 7 r/w abl mode 0: rbg (default) 1: ypbpr 6 r/w on-line/off-line abl mode 0: off-line (default) 1: on-line 5:4 r/w width of abl region in each line 00: 16 pixels (default) 01: 32 pixels 10: 64 pixels 11: 4 pixels 3 r r/pr channel abl result (write clear) 0: not equal 1: equal (black level = target value) on-line mode: |black level - target value| <=lock_m gn off-line mode: |black level - target value| <= eq_m gn 2 r g/y channel abl result (write clear) 0: not equal 1: equal (black level = target value) on-line mode: |black level - target value| <= lock _mgn off-line mode: |black level - target value| <= eq_m gn 1 r b/pb channel abl result (write clear) 0: not equal 1: equal (black level = target value) on-line mode: |black level - target value| <= lock _mgn off-line mode: |black level - target value| <= eq_m gn 0 r/w auto black level enable (write 0 force stop) 0: finished/disable (default) 1: enable to start abl, auto cleared after finishe d cleared to 0 when off-line mode completes. parameters can only be changed when en_abl is 0 the on-line mode never stops unless en_abl is 0. off-line mode completes when max_frame is measured or the result is equal.
abl must be disabled before switching on-line/off-l ine mode and then enable again. address: e3 auto_black_level_ctrl2 default: 84h bit mode function 7:6 r/w line averaged for each abl adjustment 00: 8 01: 16 10: 32 (default) 11: 64 5 -- reserved 4:0 r/w start vertical position of abl in each line determine the start line of auto-black-level after the leading edge of vsync address: e4 auto_black_level_ctrl3 default: 10h bit mode function 7:4 r/w y/r/g/b target value 0000: 1 0001: 2 (default) 0010: 3 0011: 4 ?. 1111:16 (pb/pr target level is fixed 128) 3:2 r/w lock margin 00: 1 (default) 01: 2 10: 4 11: 6 1:0 r/w end vertical position of abl measurement region [9: 8] determine the last line of auto-black-level measure ment for every frame/field countd by double line off-line mode rule: measures once for each field / frame, and the offse t is the delta. on-line mode rule: if (delta <= eq_mgn) offset = 0 else if (delta < l_mgn) offset = +/-1 else offset = +/-l_mgn adc offset is updated immediately. address: e5 auto_black_level_ctrl4 default: 82h
bit mode function 7:0 r/w end vertical position of abl measurement region [7: 0] determine the last line of auto-black-level measure ment for every frame/field counted by double line. note: abl will fail if end vertical position < star t vertical position + average line(crc1[7:6]) address: e6 auto_black_level_ctrl5 default: 04h bit mode function 7:0 r/w start position of abl in each line determine the start position of auto-black-level af ter the trailing edge of reference signal. (when abl mode in ypbpr, the reference signal is in put hsync. in rgb mode, the reference signal is clamp signal.) in each region, hardware compare the average value in the target region (fixed 16 input pixels after s tart position of abl) with target value and add +1/-1 or +l_mgn /- l_mgn to adc offset. ( + for greater tha n target value, - for smaller than target value). address: e7 auto_black_level_ctrl6 default: c0h bit mode function 7:6 r/w large error margin (l_mgn) (for on-line mode) 00: 2 01: 4 10: 6 11: 8 (default) 5:4 r/w max. frame/field count (for off-line mode) 00: 4 (default) 01: 5 10: 6 11: 7 3 -- reserved 2:0 r/w lines delayed between each measurement region (for on-line mode) 000: 16 (default) 001: 32 010: 64 011: 128 100: 192 101: 256 110: 384 111: 640
address: e8 auto_black_level_ctrl7 default: 60h bit mode function 7 -- reserved 6 r/w equal condition (off-line mode) 0: to trigger status until measurement achieve max frame/field count. 1: to trigger status once if |black level - target value| <= eq_mgn. (default) (if set 0, the abl result will not go low even nois e comes for the next frames.) 5 r/w measure pixels method 1: minimum value (default) 0: average value 4 r/w measure error flag reset 0: normal 1: reset 3 r measure error flag 0: normal 1: error (this flag is occurred when hsync trailing edge is met during measurement.) 2 r/w hsync start reference select 0: hs leading edge (default) 1: hs trailing edge 1:0 r/w equal margin (eq_mgn) 00: 0 (default) 01: 1 10: 2 11: 3 address: e9 auto_black_level_red_value bit mode function 7:0 r minimum/average value of red channel in test mode ( only show msb 8bit.) address: ea auto_black_level_green_value bit mode function 7:0 r minimum/average value of green channel in test mode (only show msb 8bit.) address: eb auto_black_level_blue_value bit mode function 7:0 r minimum/average value of blue channel in test mode (only show msb 8bit.)
address: ec auto_black_level_noise_value_of_red_channel bit mode function 7:0 r noise value of red channel in test mode after equal status is triggered. (only show msb 8bit.) address: ed auto_black_level_noise_value_of_green_channel bit mode function 7:0 r noise value of green channel in test mode after equ al status is triggered. (only show msb 8bit.) address: ee auto_black_level_noise_value_of_blue_channel bit mode function 7:0 r noise value of blue channel in test mode after equa l status is triggered. (only show msb 8bit.) image image image image hs hshs hs vs vsvs vs vsta vsta vsta vsta avg for abl avg for abl avg for abl avg for abl hsta hsta hsta hsta 16/32/64 16/32/64 16/32/64 16/32/64 hs/clamp hs/clamp hs/clamp hs/clamp len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) avg for abl avg for abl avg for abl avg for abl len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) delay_len delay_len delay_len delay_len delay_len delay_len delay_len delay_len avg for abl avg for abl avg for abl avg for abl len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) delay_len_last delay_len_last delay_len_last delay_len_last delay_len - delay_len_last delay_len - delay_len_last delay_len - delay_len_last delay_len - delay_len_last vend vend vend vend
figure-2: auto black level active region ? case 1 image image image image hs hshs hs vs vsvs vs vsta vsta vsta vsta avg for abl avg for abl avg for abl avg for abl hsta hsta hsta hsta 16/32/64 16/32/64 16/32/64 16/32/64 hs/clamp hs/clamp hs/clamp hs/clamp len-len_p1 len-len_p1 len-len_p1 len-len_p1 avg for abl avg for abl avg for abl avg for abl len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) delay_len delay_len delay_len delay_len delay_len delay_len delay_len delay_len avg for abl avg for abl avg for abl avg for abl len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) len (8/16/32/64) delay_len delay_len delay_len delay_len avg for abl avg for abl avg for abl avg for abl len_p1 (< len) len_p1 (< len) len_p1 (< len) len_p1 (< len) vend vend vend vend figure-3: auto black level active region ? case 2 lvr(page 0) address: f3 power_on_reset default: 94h bit mode function 7:6 r/w negative threshold value for power on reset 00:1.8v 01:2.2v 10:2.0v (default) 11:2.4v 5:4 r/w pormcuvset (lvr threshold voltage) 00:1.22v 01:1.13v (default) 10:1.32v 11:1.41v 3:0 r/w reserved to 0x04
smith trigger(page 0) address:f 4 hs_schmitt_trigge_ctrl default:e1h bit mode function 7 r/w hsync schmitt power down (only for schmitt trigger new mode) 0: power down 1: normal (default) 6 r/w polarity select 0: negative hsync (high level) 1: positive hsync (low level) (default) 5 r/w schmitt trigger mode 0: old mode 1: new mode(default) 4 r/w threshold voltage fine tune (only for schmitt trigg er new mode) 0: 0v (default) 1: -0.1v 3:2 r/w positive threshold voltage 1:0 r/w negative threshold voltage there is a mode of the hsync schmitt trigger. 1. new mode: fully programmable schmitt trigger. the following table will determine the schmitt trig ger positive and negative voltage: bit[6]=1 (positive hsync) bit[6] = 0 (negative hsync) bit[3:2] v t + bit[1:0] v t - bit[3:2] v t + bit[1:0] v t - 00 1.4v 00 v t + - 1.2v 00 1.8v 00 v t + - 1.2v 01 1.6v 01 v t + - 1.0v 01 2.0v 01 v t + - 1.0v 10 1.8v 10 v t + - 0.8v 10 2.2v 10 v t + - 0.8v 11 2.0v 11 v t + - 0.6v 11 2.4v 11 v t + - 0.6v after we get the threshold voltage by the table, we still can fine tune it: final positive threshold voltage = v t + - 0.1* bit[4] final negative threshold voltage = v t - - 0.1* bit[4] memory pll (page 0) register::mpll_m 0xf5 name bits r/w default comments config mpll_m[7:0] 7:0 r/w 4e mpll dpm value - 2 register::mpll_n 0xf6 name bits r/w default comments config mpll_reserve1 7 r/w 0 reserved
mpll_bpn 6 r/w 0 mpllbpn 0: n divider enable. 1: n divider disable, out=ckxtal. mpll_o[1:0] 5:4 r/w 1 mpll output divider 00: div1 01: div2 (default) 10: div4 11: div8 mpll_n[3:0] 3:0 r/w 3 mpll dpn value - 2 assume mpll_m=0x7d, dpm=0x7d+2=127; mpll_n=0x0a, dp n=0x0a+2=12; divider=1/4, f_in = 24.576mhz. f_mpll = f_in x dpm / dpn x divider = 2 4.576 x 127 / 12 / 4 = 65.024mhz. crf5~crf6 are double buffer. register::mpll_crnt 0xf7 name bits r/w default comments config mpll_rs[2:0] 7:5 r/w 3 mpll loop filter resister control 000: 16k 001: 18k 010: 20k 011: 22k (default) 100: 24k 101: 26k 110: 28k 111: 30k mpll_cs[1:0] 4:3 r/w 2 mpll loop filter capacitor control 00: 18p 01: 20p 10: 24p (default) 11: 28p mpll_ip[2:0] 2:0 r/w 2 mpll charger pump current control icp=(2.5ua+2.5ua*bit[0]+5ua*bit[1]+10ua*bit[2]) keep dpm/icp constant=10.67 register::mpll_wd 0xf8 name bits r/w default comments config
mpll_wdo 7 r 0 mpll wd status 0: normal 1: abnormal mpll_wdrst 6 r/w 0 mpll wd reset 0: normal (default) 1: reset mpll_wdset 5 r/w 0 mpll wd set 0: normal (default) 1: set mpll_fupdn 4 r/w 1 mpll freqency tuning 0: freq up 1: freq dn(default) mpll_stop 3 r/w 1 mpll freqency tuning 0: disable 1: enable (default) mpll_freeze 2 r/w 0 mpll output freeze 0: normal (default) 1: freeze active high. mpll_vcorstb 1 r/w 0 reset vco 0: normal (default) 1: reset active high. mpll_pwdn 0 r/w 1 power down mpll 0: power on 1: power down(default) active high. register::mpll_cal 0xf9 name bits r/w default comments config mpll_vcomd[1:0] 7:6 r/w 3 mpll vco default mode 00: vco slowest 11: vco fastest (default) mpll_calbp 5 r/w 0 mpll bypass calibration 0: reference by calibration result(default) 1: reference by cr-f9[7:6] active high.
mpll_calsw 4 r/w 0 calibration validated go high after power on 1200us. 0: reference by cr-f9[7:6] 1: refernect by calibration result mpll_callch 3 r/w 0 latch calibration go high after power on 1100us. 0: disable latch 1: enable latch mpll_cmpen 2 r/w 0 cmp enable go high after power on 1000us. 0: diable cmpen 1: enable cmpen mpll_cp 1 r/w 0 cp control 0: 1.77pf` 1: 2.1pf mpll_reserve 0 r/w 1 reserved for mpll phase swallow circuit 0: path0 1: path1
adc pll (page 1) address: a0 pll_div_ctrl default: 08h bit mode function 7 r/w dds tracking edge 0: hs positive edge (default) 1: hs negative edge 6 r/w tracking direction inversion 0: if hs leads hsfb => phase lead => m, k (default) 1: if hs lags hsfb => phase lag => m, k 5:4 r/w waiting hs lines to start counting divider for fast lock function 00: 4 (default) 01: 3 10: 2 11: 1 3:2 r/w delay compensation mode 00: mode 0 no delay from pll phase0 to dds pfd input 01: mode 1 delay the path from pll phase0 to dds pfd input to be around 4.2 ns 10: mode 2 (default) delay the path from pll phase0 to dds pfd input to be around 4.6 ns 11: mode 3 delay the path from pll phase0 to dds pfd input to be around 5 ns 1 r/w reserved to 0 0 r/w reserved to 0 address: a1 i_code_m default: 01h bit mode function 7 r/w reserved to 0 6:0 r/w i_code[14:8] address: a2 i_code_l default: 04h bit mode function 7:0 r/w i_code[7:0] address: a3 p_code default: 20h bit mode function 7:0 r/w p_code[7:0] address: a4 pfd_calibrated_results default: 8?b0xxxxxxx bit mode function 7 r/w pfd calibration enable (auto clear when finished) overwrite 0 to 1 return a new pfd calibrated value . 6:4 r/w reserved to 0 3:0 r pfd calibrated results [11:8] address: a5 pfd_calibrated_results default: 8?bxxxxxxxx bit mode function 7:0 r pfd calibrated results [7:0]
address: a6 pe_mearsure default: 8?b0xxxxxxx bit mode function 7 r/w pe measure enable (auto clear when finished) 0: disable (default) 1: start pe measurement, clear after finish. 6:4 r/w reserved to 0 3:0 r pe value result [11:8] address: a7 pe_mearsure default: 8?bxxxxxxxx bit mode function 7:0 r pe value result [7:0] address: a8 pe_max_measure default: 8?b0xxxxxxx bit mode function 7 r/w pe max. measure enable 0: disable (default) 1: start pe max. measurement 6:4 r/w reserved to 0 3:0 r pe max value [11:8] address: a9 pe_max_measure default: 8?bxxxxxxxx bit mode function 7:0 r pe max value [7:0] address: aa fast_pll_ctrl defa ult: 00h bit mode function 7 r/w pe max. measure clear 0: clear (default) 1: write ?1? to clear pe max. value 6 r/w enable apll setting 0: disable (default) 1: enable (auto clear when finished) when craa[5] enabled, enable this bit will write p_ code, i_code, pll m/n, pll k, plldiv and dds sum_i at the end of input vertical data ena ble 5 r/w enable fast pll mechanism 0: disable (default) 1: enable (auto clear when finished) 4 r/w force apll setting enable
force to write pll m/n, k, plldiv and sum_i while g ot no v_active signal 0: disable (default) 1: enable (auto clear when finished) 3 r/w dds sum_i setting updated enable 0: disable (default) 1: enable (auto clear when finished) 2 r/w measure sum_i 0: disable 1: enable (auto clear after finish) 1 r/w enable port ab 0: disable port ab access 1: enable port ab access when this bit is 0, port address will be reset to 0 0, and will auto increase when read or write 0 r/w select sum_i for read 1: select sum_i_now [26:0] for read 0: select sum_i_pre [26:0] for read address: ab fast_pll_sum_i bit mode function 7:0 r/w sum_i_pre (auto increase) 1 st [00000, sum_i [26:24]] 2 nd sum_i [23:16] 3 rd sum_i [15:8] 4 th sum_i [7:0] sum_i [26] is the signed bit the operation steps are as following: sum_i access port indexing=0 , sum_i access port indexing=1 , sum_i selection =1 , fast lock function=1 latch sum_i_now=1 read sum_i_now from sum_i_access_port for 4 times: sum_i_now [26:24] sum_i_now [23:16] sum_i_now [15:8] sum_i_now [7:0] calculate new freq. sum_i_pre and write to sum_i_ac cess_port for 4 times:
sum_i_pre [26:24] sum_i_pre [23:16] sum_i_pre [15:8] sum_i_pre [7:0] sum_i_pre_set =1 write pll2 m/n code and dds feed back divider write new p/i code setting auto load =1 wait for next frame start or polling reg [2e].6 address: ac pll_m (m parameter register) default: 09h bit mode function 7:0 r/w pllm[7:0] (pll dpm value ? 3) address: ad pll_n (n parameter register) default: 20h bit mode function 7:4 r/w pllsphnext[3:0] (k) (default is 0000) 3 r/w pllsnbp 0: n is followed by the value of reg ad [2:0] 1: n is always 1 2:0 r/w plln[2:0] (pll dpn value ? 2) (default is 000) it is supposed to be always bigger than 2 pll1_n modify to only 4-bit. assume pll1_m=0x0b, p1m=0x0b+3=14; pll1_n=0x03, p1n =0x03+2=5; k=7; f_in = 24.576mhz. f_pll = f_in x ( (p1m+7/16) / p1n ) = 24.576 x 14.4 375 / 5 = 70.9632mhz if the target frequency is f_adc, the constraint of f_pll is (m+-7/16)/n * xtclk < f_pll1 < (m+8/16)/n *xtclk although the new dds provides +15/-16 phase margin for tracking. however it is better not to set m, n and k to be some freq. that pll has to swallow +15/-16 phase s. because under that condition, sdm will get satur ation problem. for no shrink ic => plln setting will have no limit ation for shrink ic and timing factor predicted as 0.8 => crystal clock 27 mhz => plln can?t be 0 while apll vco is lower than 167mhz crystal clock 24.576 mhz => plln can?t be 0 wh ile apll vco is lower than 84 mhz for shrink ic and timing factor predicted as 0.9 => crystal clock 27 mhz => plln can?t be 0 while apll vco is lower than 74 mhz crystal clock 24.576 mhz => plln can?t be 0 wh ile apll vco is lower than 52 mhz address: ae pll_crnt (pll current/resistor register) default : 6fh bit mode function 7:5 r/w pllvr [2:0] (pll loop filter resister control) 000: 7k 001: 9.5k 010: 12k 011: 14.5k(default)
100: 17k 101: 19.5k 110: 22k 111: 24.5k 4:0 r/w pllsi [4:0] (pll charger pump current ichdpll) (def ault: 00011b) icp = 2.5ua+2.5ua*bit[0]+5ua*bit[1]+10ua*bit[2]+20 ua*bit[3]+30ua*bit[4] keep icp/dpm constant address: af pll_wd (pll watch dog register) defa ult: 09h bit mode function 7 r pllstatus (pll wd status) 0: normal (default) 1: abnormal 6 r/w pllwdrst (pll wd reset) 0: normal (default) 1: reset 5 r/w pllwdset (pll wd set) 0: normal (default) 1: set 4:3 r/w pllwdvset[1:0] (pll wd voltage set) 00: 2.46v 01: 1.92v(default) 10: 1.36v 11: 1.00v 2 r/w hs_dds2synp latch edge 0: falling edge (default) 1: rising 1 r/w reset dds 0: normal (default) 1: reset whole dds 0 r/w pllpwdn (pll power down) 0: normal run 1: power down (default) hsfb_dds2synp & hs_dds2synp will be both sampled by af [2] address: b0 pll_mix default: 8?b0000_000x bit mode function 7 r/w pllsvr3 6 --- reserved to 0 5 r/w pllsvc3
4 --- reserved to 0 3 --- reserved to 0 2:1 r/w adckmode [1:0] (adc input clock select mode) 00: single clock mode (default) 01: single inverse-clock mode 10: external clock mode 11: dual clock mode (1x and 2x clock) 0 r swallow phase enable (k mask disabled) the pll can? t enable swallow phase function while pll just be p ower up. waiting for 64 clock cycles then start to enable phase swallow function. while power down, the counter will be reset. while power up, the counter start to work address: b1 plldiv_h default: 45h bit mode function 7 --- reserved to 0 6 r/w phase_select_method 0: manual 1: look-up-table (default) 5 r/w pllph0path 0: short path (default) 1: long path (compensate pll_adc path delay) 4 r/w plld2 0:adc clk=1/2 vco clk (default) 1:adc clk=1/4 vco clk 3:0 r/w pll divider ratio control. high-byte [11:8]. (defau lt: 5h) address: b2 plldiv_l default: 2eh bit mode function 7:0 r/w pll divider ratio control . low-byte [7:0] . plldiv should be double buffered when plldiv_lo cha nges and iden_stop occurs. this register determines the number of output pixel per horizontal line. pll derives the sampling cloc k and data output clock (dclk) from input hsync. the real operation divider ratio = plldiv+1 the power up default value of plldiv is 053fh(=1343 , vesa timing standard, 1024x768 60hz, horizontal time). the setting of plldiv must include sync, back-porch , left border, active, right border, and front-porc h times. control-register b1 & b2 will filled in when contro l-register b2 is written. address: b3 pllphase_ctrl0 (select phase to a/d) default: 30h bit mode function 7 r/w plld2x control (default=0) 6 r/w plld2y control (default=0)
5 r/w pllx (pll x phase control) (default=1) 4 r/w plly (pll x phase control) (default=1) 3:0 r/w pllsck [4:1] (pll 32 phase pre-select control) (default=0h) address: b4 pllphase_ctrl1 (select phase to a/d) defaul t: 00h bit mode function 7 r/w pllsck [0] (pll 32 phase pre-select control) (default=0) 6 r/w msb of 128 phase (only for adc clk=1/4 vco clk) (default=0) 5:0 r/w phase select the index of look-up-table[5:0] (default=0) when phase_select_method=1, phase is selected by cr b4[6:0]. when phase_select_method=0, plld2x, plld2y, pllx, p lly, pllsclk[4:0] should be double buffered when pllsck[0] is updated address: b5 pll_phase_interpolation default: 50h bit mode function 7:6 r/w pll phase interpolation control load (default: 01) 5:3 r/w pll phase interpolation control source (default: 01 0) 2:1 r/w pll add phase delay 00: original phase selected by x,y and 16-phase pre -select 01-11: add 1-3 delay to original phase selected by x,y and 32-phase pre-select 0 r/w reserved to 0 phase [xy^^^^^] phase [xy ^^^^^] phase [xy ^^^^^] phase [xy ^^^^^] 0 [11 00000] 16 [01 10000 ] 32 [10 00000] 48 [00 10000] 1 [11 00001] 17 [01 10001 ] 33 [10 00001] 49 [00 10001] 2 [11 00010] 18 [01 10010 ] 34 [10 00010] 50 [00 10010] 3 [11 00011] 19 [01 10011] 35 [10 00011] 51 [00 10011] 4 [11 00100] 20 [01 10100] 36 [10 00100] 52 [00 10100] 5 [11 00101] 21 [00 10101] 37 [10 00101] 53 [00 10101] 6 [11 00110] 22 [00 10110] 38 [10 00110] 54 [00 10110] 7 [11 00111] 23 [01 10111] 39 [10 00111] 55 [00 10111] 8 [11 01000] 24 [01 11000] 40 [10 01000] 56 [00 11000] 9 [11 01001] 25 [01 11001] 41 [10 01001] 57 [00 11001] 10 [01 01010] 26 [10 11010] 42 [10 01010] 58 [11 11010] 11 [01 01011] 27 [10 11011] 43 [10 01011] 59 [11 11011] 12 [01 01100] 28 [10 11100] 44 [00 01100] 60 [11 11100] 13 [01 01101] 29 [10 11101] 45 [00 01101] 61 [11 11101]
14 [01 01110] 30 [10 11110] 46 [00 01110] 62 [11 11110] 15 [01 01111] 31 [10 11111] 47 [00 01111] 63 [11 11111] address: b6 p_code mapping methods default: 18h bit mode function 7:6 r/w mapping method: 00: normal mapping p_code x g value (default) 01: nonlinear mapping i smaller than q(pe) 2 4 8 16 32 64 p_code x 1 2 4 8 32 128 128 10: nonlinear mapping ii p_code x 1 2 2 8 32 256 256 11: nonlinear mapping iii p_code x 1 2 8 16 32 128 512 5:2 r/w g value 0000: 0 0001: 1 0010: 4 0011: 16 0100: 64 0101: 128 0110: 256 (default) 0111: 512 1000: 1/4 1001: 1/16 1010: 1/64 1011: reserved to 0 1100: reserved to 0 1101: reserved to 0 1110: reserved to 0 1111: reserved to 0 1 r/w adaptive tracking enable for i_code 0: disable to use adaptive i_code (default) 1: enable to use adaptive i_code 0 r/w adaptive tracking enable for p_code 0: disable to use adaptive p_code (default) 1: enable to use adaptive p_code address: b7 pe tracking method default: 02h
bit mode function 7:6 r/w threshold value of q (pe) to decide if starting adaptive tracking 00: 2 (default) 01: 4 10: 8 11: 15 5:4 r/w threshold times to decide if starting adaptive trac king while q(pe) < threshold value successively 00: 3 (default) 01: 7 10: 11 11: 15 3 r/w mask high speed testing pins (test1out, test2out, f av4) 0: normal 1: mask 2 r/w adaptive tracking enable => refer to b6 [1:0] to de cide if i_code or p_code enables adaptive tracking or not 0: disable (default) 1: enable 1:0 r/w decrease ratio for adaptive tracking adaptive tracking will be enabled while getting q ( pe) <=2 for over 8 times, and it will be triggered only under delay-chain mode 00: 1/2 01: 1/4 10: 1/8 (default) 11: 1/16 address: b8 dds_mix_1 default: 06h bit mode function 7:6 r dds tracking state [1:0] 00: not lock 01: lock 10: unlock but not using new tracking mode yet 11: unlock & using new tracking mode 5:4 r/w reserved to 0 3:1 r/w judge threshold lock already => while q (pe) keep s maller than threshold for 32 hs 000: 2 001: 4 010: 6
011: 8 (default) 100: 16 101: 32 110: 64 111: 120 0 r pll lock already 0: not lock already 1: lock already address: b9 dds_mix_2 default: 00h bit mode function 7:0 r/w p_code_max[16:9] set p_code_max value to clamp the gain of apll address: ba dds_mix_3 default: 00h bit mode function 7:0 r/w p_code_max[8:1] set p_code_max value to clamp the gain of apll address: bb dds_mix_4 default: 1bh bit mode function 7 r/w p_code_max[0] set p_code_max value to clamp the gain of apll 6 r/w new mode enable 0: disable new mode tracking (default) 1: enable new mode tracking 5:3 r/w new mode enable threshold 000: 8 001: 20 010: 60 011: 120 (default) 100: 200 101: 450 110: 800 111: 1200 2:0 r/w new mode lock threshold=> while q (pe) keep smaller than threshold for 32 hs 000: 2 001: 4 010: 6 011: 8 (default) 100: 16
101: 32 110: 64 111: 120 new mode enable threshold should be larger than new mode lock threshold, otherwise, the track state will always be at lock state and new mode function will not be enabled while new mode enable threshold < q (pe) < new mode lock threshold address: bc dds_mix_5 default: a0h bit mode function 7:6 r/w delay chain length select (only valid while new mod e enable and track state is 01 10 11) 00: cnt=7 => 59.6ns 01: cnt=15 => 117ns 10: cnt=23 => 184.4ns (default) 11: cnt=31 => 246.8ns 5:4 r/w phase error sample period choose (only valid while new mode enable and track state is 01 10 11) 00: every 1 cycle sample 01: every 2 cycle sample 10: every 3 cycle sample (default) 11: every 4 cycle sample 3 r/w delay chain reset period select 0: short reset (2ns) (default) 1: long reset (1 fbck) 2 r/w reset delay chain saturation flag 0: normal (default) 1: reset flag 1 r delay chain saturation flag 0: not saturate 1: saturate => it need to enlarge the sample period or set bigger n code 0 r/w apll_free_run enable 0: normal state (default) 1: force apll to free run state while we got delay chain saturation flag 1?b1, that means that the big jitter is bigger than what we image and we have to reset the delay chain length setting bc [7:6]. also we have to enlarge the sampling period & delay chain length the choice for sampling period will be set by the r ule as following: (delay chain length * 78 +50) * each tap delay + 10 (ns) must be < n * t xclk * sample period if delay chain saturation flag goes high, then we m ust enlarge the delay chain length & set bigger sampling period
while we enable free run mode, dds will keep reset status until disable free run address: bd dds_mix_6 bit mode function 7:0 r final m code to apll while we like to read final m code & k code, we hav e to enable measure pe (page 1-cra6[7]) first. otherwise we will get glitch valu e address: be dds_mix_7 default: 00h bit mode function 7:4 r final k code to apll 3:1 r/w change mode threshold => triggered by any q (pe) > threshold 000: 600 (default) 001: 850 010: 1100 011: 1350 100: 1600 101: 1850 110: 2100 111: 2350 0 r/w new_mode_i_code_en 0: while new mode enable, i code will have no effect on sum_i. all phase error will be compensated by p code (default) 1: while new mode enable, i code will be operated a s normal state for apll interrupt status that include 4 different types: no lock: initial is 1 => over lock threshold b8 [3: 1] => 1 wait state: initial is 1 => valid only while u enab le new mode => over new mode enable threshold bb [5 :3] => 1 new mode state: initial is 1 => valid only while u enable new mode => over new mode lock threshold bb [2:0] => 1 change mode happen state: initial is 1 => over chan ge mode threshold be [3:1] => 1 display pll (page 1) register::dpll_m 0xbf name bits r/w default comments config dpll_m[7:0] 7:0 r/w 4e dpll dpm value - 2
register::dpll_n 0xc0 name bits r/w default comments config dpll_reserve1 7 r/w 0 reserved dpll_bpn 6 r/w 0 dpllbpn 0: n divider enable. 1: n divider disable, out=ckxtal. dpll_o[1:0] 5:4 r/w 1 dpll output divider 00: div1 01: div2 (default) 10: div4 11: div8 dpll_n[3:0] 3:0 r/w 3 dpll dpn value - 2 assume dpll_m=0x7d, dpm=0x7d+2=127; dpll_n=0x0a, dp n=0x0a+2=12; divider=1/4, f_in = 24.576mhz. f_dpll = f_in x dpm / dpn x divider = 2 4.576 x 127 / 12 / 4 = 65.024mhz. crbf~crc0 are double buffer. register::dpll_crn t 0xc1 name bits r/w default comments config dpll_rs[2:0] 7:5 r/w 3 dpll loop filter resister control 000: 16k 001: 18k 010: 20k 011: 22k (default) 100: 24k 101: 26k 110: 28k 111: 30k dpll_cs[1:0] 4:3 r/w 2 dpll loop filter capacitor control 00: 18p 01: 20p 10: 24p (default) 11: 28p dpll_ip[2:0] 2:0 r/w 2 dpll charger pump current control icp=(2.5ua+2.5ua*bit[0]+5ua*bit[1]+10ua*bit[2]) keep dpm/icp constant=10.67
dclk spread spectrum (page 1) register::dpll_wd 0xc2 name bits r/w default comments config dpll_wdo 7 r 0 dpll wd status 0: normal 1: abnormal dpll_wdrst 6 r/w 0 dpll wd reset 0: normal (default) 1: reset dpll_wdset 5 r/w 0 dpll wd set 0: normal (default) 1: set dpll_fupdn 4 r/w 1 dpll freqency tuning 0: freq up 1: freq dn(default) dpll_stop 3 r/w 1 dpll freqency tuning 0: disable 1: enable (default) dpll_freeze 2 r/w 0 dpll output freeze 0: normal (default) 1: freeze active high. dpll_vcorstb 1 r/w 0 reset vco 0: normal (default) 1: reset active high. dpll_pwdn 0 r/w 1 power down dpll 0: power on 1: power down(default) active high. register::dpll_cal 0xc3 name bits r/w default comments config dpll_vcomd[1:0] 7:6 r/w 3 dpll vco default mode 00: vco slowest 11: vco fastest (default)
dpll_calbp 5 r/w 0 dpll bypass calibration 0: reference by calibration result(default) 1: reference by crc3[7:6] active high. dpll_calsw 4 r/w 0 calibration validated go high after power on 1200us. 0: reference by crc3[7:6] 1: refernect by cal result dpll_callch 3 r/w 0 latch calibration go high after power on 1100us. 0: disable latch 1: enable latch dpll_cmpen 2 r/w 0 cmp enable go high after power on 1000us. 0: diable cmpen 1: enable cmpen dpll_cp 1 r/w 0 cp control 0: 1.77pf` 1: 2.1pf dpll_reserve 0 r/w 1 reserved for dpll phase swallow circuit 0: path0 1: path1 register:: initial dclk_fine_tune_offset_msb 0xc4 name bits r/w default comments config dpll_linear_change 7 r/w 0 linear change offset value function 0 : disable 1: enable (auto clear when finish) it should work on dds spread spectrum output function enable. when function is done, the initial offset and dpllupdn value would be the target offset and dpllupdn value. dpll_even_old_en 6 r/w 0 only even / odd field mode enable 0: disable (default)
1: enable dpll_even_od_sel 5 r/w 0 even / odd field select 0: even (default) 1: odd dpll_fupdn 4 r/w 1 dpllfupdn (dpll frequency tuning) 0: freq up 1: freq down (default) dclk_offset[11:8] 3:0 r/w 0 initial dclk offset [11:8] in fixed last line dvtotal & dhtotal register:: initial dclk_fine_tune_offset_lsb 0xc5 name bits r/w default comments config dclk_offset[7:0] 7:0 r/w 0 initial dclk offset [7:0] in fixed last line dvtotal & dhtotal register:: dclk_spread_spectrum 0xc6 name bits r/w default comments config dclk_spread_range 7:4 r/w 0 dclk spreading range (0.0~7.5%) the bigger setting, the spreading range will bigger , but not uniform dclk_fmdiv 3 r/w 0 spread spectrum fmdiv (ssp_fmdiv)//(0) 0: 33k 1: 66k dclk_ready 2 r/w 0 spread spectrum setting ready for writing (auto clear) 0: not ready 1: ready to write freq_synthesis_sel 1:0 r/w 0 frequency synthesis select (f & f-n*df) 00~11: n=1~4 the ?spread spectrum setting ready for writing? mea ns 4 kinds of registers will be set after this bit is set: 1. dclk spreading range 2. spread spectrum fmdiv 3. dclk offset setting 4. frequency synthesis select register:: even_fixed_last_line_msb 0xc7 name bits r/w default comments config even_fixed_last_line[11:8] 6:4 r/w 3 even fixed last line length [11:8]
even_fixed_dvtotal[11:8] 3:0 r/w 0 even fixed dvtotal [11:8] register:: even_fixed_last_line_lsb 0xc8 name bits r/w default comments config even_fixed_dvtotal[7:0] 7:0 r/w 0 even fixed dvtotal [7:0] register:: even fixed_last_line_ length_lsb 0xc9 name bits r/w default comments config even_fixed_dvtotal[7:0] 7:0 r/w 0 even fixed last line length [7:0] if even / odd mode disable, we use even_fixed_last only. if even/odd mode enable, the even / odd field would be reference different setting. fixed last line value can?t be zero, and can?t smal ler than dh_sync width. register:: fixed_last_line_ctrl 0xca name bits r/w default comments config rsv_ca_76 7:6 -- 0 reserved to 0 measure_phase 5 r/w 0 measure the phase about fixed dvtotal & last line dhtotal function 0 : disable 1 : enable (auto clear when finish) mark_phase_tracking 4 r/w 0 mark phase tracking about fixed dvtotal & last line dhtotal function 0 : disable 1 : enable ned_fixed_last_line_mode 3 r/w 0 enable new design function in fixed last line mode 0: disable (default) 1: enable dclk_dds 2 r/w 0 dds spread spectrum test enable 0: disable (default) 1: enable dclk_fixed_last_line_en 1 r/w 0 enable the fixed dvtotal & last line dhtotal function 0: disable (default) 1: enable
dclk_dds_en 0 r/w 0 enable dds spread spectrum output function 0: disable (default) 1: enable procedure: first, we have set m/n code and then we need to tun e dclk offset to achieve frame-sync, every step of offset frequency is dclk/ 15 2 . when we finished the frame-sync, we turn on crca[1] to let the system running in to free-run mode, at this time, the crc7,crc8,crc9 are the reference dv and d h total and fixed last line length. but the free-run mode dvs? should be close to frame -sync mode dvs to achieve pseudo-frame-sync( actual ly, it is free run mode now) then we use crc6[1:0] (f-n*df) to keep dvs? and dvs very closely to achieve pseudo-frame-sync. notice: in rtd2472rd, when all the setting above is ready, then we open spread spectrum function, the dclk offset will shift, please keep the dclk offset keep s steady when we open spread spectrum function. in real free-run mode, the dv_total refers to cr2b- 0b/cr2b-0c, and in fixed-last-line mode, and disable ?even/odd mode? then the free-run timing dv _total refers to crc7/crc8, at this time cr2b-0b/cr2b-0c serve for vsync-timeout watch dog r eference. register:: odd_fixed_last_line_msb 0xcb name bits r/w default comments config odd_fixed_last_line_leng[11:8] 6:4 r/w 0 odd fixed last line length [11:8] odd_fixed_dvtotal[11:8] 3:0 r/w 0 odd fixed dvtotal [11:8] register:: odd_fixed_last_line_dvtotal _lsb 0xcc name bits r/w default comments config odd_fixed_dvtotal[7:0] 7:0 r/w 0 odd fixed dvtotal [7:0] mclk spread spectrum (page 1) register:: mclk_fine_tune_offset_msb 0xcd name bits r/w default comments config
rsv_fa_74 7:4 --- 0 reserved mclk_offset[11:8] 3:0 r/w 0 mclk offset [11:8] register:: mclk_fine_tune_offset_lsb 0xce name bits r/w default comments config mclk_offset[7:0] 7:0 r/w 0 mclk offset [7:0] register:: mclk_spread_spectrum 0xcf name bits r/w default comments config mclk_spread_range 7:4 r/w 3 mclk spreading range (0.0~7.5%) the bigger setting, the spreading range will bigger , but not uniform mclk_fmdiv 3 r/w 0 spread spectrum fmdiv (ssp_fmdiv)//(0) 0: 33k 1: 66k mclk_ready 2 r/w 0 spread spectrum setting ready for writing (auto clear) 0: not ready 1: ready to write mclk_dds 1 r/w 0 dds spread spectrum test enable 0: disable (default) 1: enable mclk_dds_en 0 r/w 0 enable dds spread spectrum output function 0: disable (default) 1: enable the ?spread spectrum setting ready for writing? mea ns 3 kinds of registers will be set after this bit is set: 1. mclk spreading range 2. spread spectrum fmdiv 3. mclk offset setting register:: phase_line_lsb 0xd0 name bits r/w default comments config phase_line[7:0] 7:0 r 0 phase line [7:0]
register:: phase_pixel_pixel 0xd1 name bits r/w default comments config phase_pixel[7:0] 7:0 r 0 lead phase pixel [7:0] register:: target_dclk_fine_tune_offset_msb 0xd2 name bits r/w default comments config rsv_d2_75 7:5 --- 0 reserved target_dpllupdb 4 r/w 1 target dpllupdn (dpll frequency tuning up/down) 0: freq up 1: freq down (default) target_dclk_offset[11:8] 3:0 r/w 0 target dclk offset [11:8] in fixed last line dvtotal & dhtotal register:: target_dclk_fine_tune_offset_lsb 0xd3 name bits r/w default comments config target_dclk_offset[7:0] 3:0 r/w 0 target dclk offset [7:0] in fixed last line dvtotal & dhtotal register::dpll_result 0xd4 name bits r/w default comments config rsv_d4_74 7:4 --- 0 reserved dpll_vo2 3 r 0 dpll cal out2 dpll_vo1 2 r 0 dpll cal out1 dpll_cal[1:0] 1:0 r 0 dpll calibrated vco code multiply pll for input cyrstal (page 1) register::m2pll_m 0xe0 name bits r/w default comments config
m2pll_m[7:0] 7:0 r/w 69 m2pll dpm value ? 2 (m) * pll output=input*(m/p) register::m2pll_n 0xe1 name bits r/w default comments config m2pll_cp 7 r/w 0 cp control 0:cp=1.77pf 1:cp=2.1pf m2pll_bpn 6 r/w 0 m2pllbpn=0 , n divder enable m2pllbpn=1, n divder disable , out=ckxtal m2pll_o[1:0] 5:4 r/w 1 m2pll output divider 00:div1, 01:div2, 10:div4, 11:div8 m2pll_n[3:0] 3:0 r/w 3 m2pll dpn value - 2 note: cre0~e1 are double buffer cre2~e3 are not controlled by software reset. register::m2pll_crnt 0xe4 name bits r/w default comments config m2pll_rs[2:0] 7:5 r/w 3 m2pll loop filter resister control(rs) 000:16k, 001:18k, 010:20k, 011:22k 100: 24k, 101: 26k, 110:28k, 111:30k m2pll_cs[1:0] 4:3 r/w 2 m2pll loop filter capacitor control(cs) 00:18p, 01:20p, 10:24p, 11:28p m2pll_ip[1:0] 2:0 r/w 2 m2pll charge pump current control icp=(2.5ua+2.5ua*bit[0]+5ua*bit[1]+10ua*bit[2]) keep dpm/icp constant=10.67 register::m2pll_wd 0xe5 name bits r/w default comments config m2pll_wdo 7 r 0 m2pll wd status register 0:normal 1:abnormal m2pll_wdrst 6 r/w 0 m2pll wd reset 0:normal
1:reset m2pll_wdset 5 r/w 0 m2pll wd set 0:normal 1:set m2pll_vcomd[1:0] 4:3 r/w 3 m2pll vco default mode 00: vco slowest 11: vco fastest m2pll_freeze 2 r/w 0 m2pll output freeze 0:normal 1:freeze (active high) m2pll_vcorstb 1 r/w 0 reset vco (active high) m2pll_pwdn 0 r/w 0 power down m2pll (active high) audio dac (page 1) register:: bb_power0 0xf0 name bits r/w default comments config bb_pow_ain 7 r/w 0 power down control for ain buffer (0:power down, 1:power on) bb_pow_ainvol 6 r/w 0 power down control for ain volume control (0:power down, 1:power on) bb_pow_aout 5 r/w 1 power down control for aout amplifier (0:power down, 1:power on) bb_pow_dac 4 r/w 0 power down control for dac (0:power d own, 1:power on) bb_pow_dacvol 3 r/w 0 power down control for dac volume control (0:power down, 1:power on) bb_pow_dacvref 2 r/w 0 power down control for dac reference voltage buffer (0:power down, 1:power on) bb_pow_df2se 1 r/w 0 power down control for df2se (0:power down, 1:power on) bb_pow_hpout 0 r/w 1 power down control for hpout amplifier (0:power down, 1:power on) register:: bb_power1 0xf1 name bits r/w default comments config
reserved 7:2 -- 0 reserved bb_pow_mbias 1 r/w 1 power dow n control for bias generator (0:power down, 1:power on) bb_pow_vref 0 r/w 1 power down control for analog ground generator (0:power down, 1:power on) register:: ain_control 0xf2 name bits r/w default comments config reserved 7 -- 0 reserved bb_en_ain 6 r/w 0 enable ain (0:disable, 1:enable) bb_ainvol 5:0 r/w 0x27 volume control for ain (00h:-58.5db~37h:24db) register:: dac_control 0xf3 name bits r/w default comments config reserved 7:6 -- 0 reserved bb_dacvol 5:0 r/w 0x27 volume control for dac output (00h:-58.5db~37h:24db) register:: aout_control 0xf4 name bits r/w default comments config bb_mute_aout_l 7 r/w 1 mute control for aout_l (0:unmute, 1:mute) bb_mute_aout_r 6 r/w 1 mute control for aout_r (0:unmute, 1:mute) bb_mux_aout 5 r/w 0 source selection for aout (0:from dac, 1:from ain) bb_outen_aout 4 r/w 0 output enable for aout (0:disable, 1:enable) bb_swap_aout 3 r/w 0 swap l/r control for aout (0:no swap, 1: swap l/r) reserved 2:0 -- 0 reserved register:: hpout_control 0xf5
name bits r/w default comments config bb_mute_hpout_l 7 r/w 1 mute control for hpout_l (0:unmute, 1:mute) bb_mute_hpout_r 6 r/w 1 mute control for hpout_r (0:unmute, 1:mute) bb_mux_hpout 5 r/w 0 source selection for hpout (0:from dac, 1:from ain) bb_outen_hpout 4 r/w 0 output enable for hpout (0:disable, 1:enable) bb_swap_hpout 3 r/w 0 swap l/r control for hpout (0:no swap, 1: swap l/r) reserved 2:0 -- 0 reserved register:: mbias_control0 0xf6 name bits r/w default comments config bb_mbias_amp 7:6 r/w 10 bias current selection for output amplifier (00b:10u, 01b:15u, 10b:20u, 11b:30u) bb_mbias_dacvref 5:4 r/w 10 bias current selection for dacvref (00b:10u, 01b:15u, 10b:20u, 11b:30u) bb_mbias_daop 3:2 r/w 10 bias current sele ction for daop (00b:10u, 01b:15u, 10b:20u, 11b:30u) bb_mbias_darefbuf 1:0 r/w 10 bias current selection for darefbuf (00b:10u, 01b:15u, 10b:20u, 11b:30u) register:: mbias_control1 0xf7 name bits r/w default comments config bb_mbias_df2se 7:6 r/w 10 bias current selection for df2se (00b:10u, 01b:15u, 10b:20u, 11b:30u) bb_mbias_in_mc3 5:4 r/w 10 bias current selection for input buffer (00b:10u, 01b:15u, 10b:20u, 11b:30u) bb_mbias_vol 3:2 r/w 10 bias current selection for volume control (00b:10u, 01b:15u, 10b:20u, 11b:30u) bb_mbias_vref 1:0 r/w 10 bias current selection for analog ground generator (00b:10u, 01b:15u, 10b:20u, 11b:30u) register:: vref_control 0xf8
name bits r/w default comments config bb_vref_vag 7:6 r/w 01 analog ground volta ge selection (00b:1.717 ,01b:1.65, 10b:1.58, 11b:1.51) bb_dacvref_mode 5 r/w 1 dac reference voltage source (0:internal generation, 1:external given) reserved 4:0 -- 0 reserved register:: modulator_control 0xf9 name bits r/w default comments config bb_mod_clk_rate 7:6 r/w 00 00:mclk(256fs) 01:aclk(128fs) 10:sclk(64fs) bb_mod_rst_n 5 r/w 1 for second time to reset sigma- delta modulator(after reset up sample filter about 22*(1/fs) ) 0: reset 1: no reset bb_debug_en 4 r/w 0 debug mode enable bb_debug_mode 3:1 r/w 0 support 8 sets debug mode. bb_out_l_r_sel 0 r/w 0 debug mode, adding l or r output 16bits in digital function register:: bist_control 0xfa name bits r/w default comments config bb_bist_mode 7 r/w 0 0: disable 1: enable bb_bist_rst_n 6 r/w 1 0: reset 1: no reset bb_bist_done 5 r 0 0: bist is running 1: bist done bb_bist_fail 4 r 0 0: bist ok 1: bist fail
bb_ft_en 3 r/w 0 for ft and test performance 1:iinput pcm data from test pin in. 0:pcm data from digital circuit. bb_48pin_mode 2 r/w 0 1:16bits test in (pcm data). 0:22bits test in. (pcm data) bb_48pin_mode reserved 1:0 -- 0 reserved
overall hdmi system function block (page 2) tmds receiver hdmi ip data part de, vs, hs, ctrl(4), clk data (24) i2s(3)*4 spdif(1)*4 ddc(2) cec crystal clock host interface bck test i/o hdmi f/w ip tmds data recovery ( rx & align & sync..) 10*3ch clock (de) hdmi ip control part host interface ck +/- rx0 +/- rx1 +/- rx2 +/-
error correction hs_dec vs_dec hs' vs' mu x hs_gen vs_gen h/v occur flag de_only register: tmds_msr 0xa1 name bits r/w reset state comments tmm 7 r/w 0 transition measurement method 0: measure the number of transition for n-clock dur ation (tmds_ncp[3:0]) 1: measure the number of transition smaller than 16 /64 clock period (tmds_ctc) for 1-frame duration mt 6:4 r/w 0 measure times(exponential of 2) 000: 1 001: 2 010: 4 011: 8 100: 16 101: not available 110: not available 111: not available this function will do bit [6:4] times, each time la sts for bit [3:0]/12 ms. ncp 3:0 r/w 0 numbers of clock period, measurement duration (wher e clock frequency is 12khz) 0000: 16 0001: 1 0010: 2 0011: 3 ??. 1111: 15 this function will do bit [6:4] times, each time la sts for bit [3:0]/12 ms. register: tmds_mrr0 0xa2 name bits r/w reset state comments tms 7 r/w 0 transition measurement 0: stop measure, cleared after finish (default) 1: start measure mrs 6:5 r/w 0 measure result select 00: ave value (default)
01: max value 10: min value ms 4:3 r/w 0 measure select 00: measure hsync transition times before error co rrection. 01: measure hsync transition times after error cor rection. 10: measure data enable transition times before er ror correction. 11: measure data enable transition times after err or correction. reserved 2:1 --- reserved ctc 0 r/w 0 criterion of transition count , duration smaller than 0: 16 clock 1: 64 clock register: tmds_mrr1 0xa3 name bits r/w reset state comments reserved 7 --- 0 reserved vmr 6:0 r 0 value of measure result [6:0] (item refer to ms) register:: tmds_ctrl 0xa4 name bits r/w reset state comments bcd 7 r x b-channel detect (de low 128 clock)(write 1 clear) 0:no 1:yes gcd 6 r x g channel detect (de low 128 clock)(write 1 clear) 0: no 1:yes rcd 5 r x r channel detect (de low 128 clock)(write 1 clear) 0: no 1: yes ho 4 r x hsync occur (write 1 clear) 0: no 1: yes yo 3 r x vsync occur (write 1 clear) 0: no 1: yes crcts 2:1 r/w 0 crc type select 00: do crc only with de 01: do crc only with dien (data island enable) 10: do crc with both de and dien 11: reserved crcc 0 r/w 0 crc check register:: tmds_crcob2 0xa5 name bits r/w reset state comments crcob2 7:0 r -- 1 st read=> output crc-48 bit 47~40 2 nd read=> output crc-48 bit 39~32 3 rd read=> out put crc-48 bit 31~24 4 th read=> out put crc-48 bit 23~16 5 th read=> out put crc-48 bit 15~8 6 th read=> out put crc-48 bit 7~0
the read pointer should be reset when 1. crc output byte is written 2. crc check starts. the read back crc value address should be auto-incr ease, the sequence is shown above register:: tmds_outctl 0xa6 name bits r/w reset state comments aoe 7 r/w 0 auto output enable 0: disable (default) 1: enable trcoe 6 r/w 0 tmds r channel output enable 0: disable (default) 1: enable tgcoe 5: r/w 0 tmds g channel output enable 0: disable (default) 1: enable tbcoe 4 r/w 0 tmds b channel output enable 0: disable (default) 1: enable ocke 3 r/w 0 oclk enable 0: disable (default) 1: enable ockie 2 r/w 0 oclk invert enable 0: normal (default) 1: enable reserved 1 r/w 0 reserved clk25xi nv 0 r/w 0 input 1x clock invert 0: no invert (default) 1: invert register: tmds_pwdctl 0xa7 name bits r/w reset state comments deo 7 r/w 0 de-only: generate vs/hs from de signal 0: disable (default) 1: enable brcw 6 r/w 0 b/r channel swap 0: no swap (default) 1: swap pnsw 5 r/w 0 p/n swap 0:no swap(default) 1:swap iccaf 4 r/w 0 input channel control by auto function 0: manual 1: auto (default) ecc 3 r/w 0 enable clock channel: turn on clock channel pll (fo r manual use) 0: disable (default) 1: enable erip 2 r/w 0 enable red input port (for manual use, cut off 50oh m internal resistor) 0: disable (default) 1: enable egip 1 r/w 0 enable green input port (for manual use, cut off 50 ohm internal resistor) 0: disable (default) 1: enable ebip 0 r/w 0 enable blue input port (for manual use, cut off 50o hm internal resistor)
0: disable (default) 1: enable register:: tmds_acc0 0xa8 name bits r/w reset state comments reserved 7:0 -- -- reserved register:: tmds_acc1 0xa9 name bits r/w reset state comments reserved 7:0 -- -- reserved register:: tmds_abc 0xaa name bits r/w reset state comments reserved 7:0 r/w -- reserved to 0 register:: tmds_acc2 0xab name bits r/w reset state comments reserved 7:0 r/w -- reserved to 0 register:: tmds_z0cc2 0xac name bits r/w reset state comments ddcdbn c 7 r/w 1 hdcp ddc debounce 0: disable 1: enable hde 6 r/w 0 hdmi/dvi function enable (hdcp enable is moved to hdcp ) 0: disable, gated clock and cut off tmds pull up re sistor for saving power. 1: enable, reserved 5:0 r/w -- reserved to 0 register:: tmds_cps 0xad name bits r/w reset state comments pll_div2_ en 7 r/w 0 hdmi output clock div 2 (enable this register if 2x clock is needed) 0: disable 1: enable reserved 6:0 -- 0 reserved. register:: tmds_rps 0xae name bits r/w reset state comments reserved 7:0 -- 0 reserved to 0 register:: tmds_wdc 0xaf name bits r/w reset state comments
reserved 7:0 -- 0 reserved to 0 register 0xb0~0xb3 are reserved. register:: tmds_dpc0 0xb4 name bits r/w reset state comments dpc_pp 7:4 r 0 pp value of hdmi 1.3 deep color mode. (if dpc_auto( 0xb8[2]) ==0, this bit is r/w; otherwise, it is read-only) dpc_cd 3:0 r 0 cd value of hdmi 1.3 deep color mode. (if dpc_auto(0xb8[2]) ==0, this bit is r/w; otherwise, it is read-only) register:: tmds_udc0 0xb5 name bits r/w reset state comments dpc_bypass_ dis 7 r/w 0 disable deep color mode 0: disable 1: enable reserved 6:3 -- 0 reserved. cptest 2 r 0 cptest 0: normal mode, in which clock and data from analog are used. 1: select tstckin/tstdin as input 2x5 clock and dat a respectively, for testing. hmtm 1:0 r/w 0 hdcp mp testing mode force ctl[3:0] always equal to 00:original 01:ctrl=1001 10:ctrl=1000 11:ctrl=0000 register:: tmds_udc1 0xb6 name bits r/w reset state comments no_clk_in 7 r 0 no clock input. 0: normal, 1: no clock cdr_rdy_red 6 r 0 cdr ready of red channel cdr_rdy_grn 5 r 0 cdr ready of green channel cdr_rdy_blu 4 r 0 cdr ready of blue channel reserved 3:0 -- 0 reserved. register:: tmds_udc2 0xb7 name bits r/w reset state comments nl 7:5 r/w 0 errc_sel<1:0> 000: original signal 001: 1 cycle debouncing 010: 1+8 cycle debouncing 011: 1+8 cycle debouncing + de masking transition o f vs/hs
100: 1+8 cycle debouncing + de masking transition o f vs/hs + masking first 8-line de nlfw 4:0 r/w 0 debug_sel register:: tmds_dpc1 0xb8 name bits r/w reset state comments reserved 7:4 -- 0 reserved. dpc_clk_sou rce 3 r/w 0 select the reference clock of deep color pll 0: recovered tmds clock 1: original tmds clock dpc_auto 2 r/w 1 0: manual mode (cd/pp/default_ phase fields are s pecified by fw) 1: auto mode (cd/pp/default_ phase are directly dec oded by hw) dpc_default_ ph 1 r/w 0 default phase of hdmi 1.3 deep color mode. (if dpc_auto(0xb8[2]) ==0, this bit is r/w; otherwi se, it is read-only) dpc_pp_vali d 0 r/w 0 phase valid of hdmi 1.3 deep color mode. (if dpc_auto(0xb8[2]) ==0, this bit is r/w; otherwi se, it is read-only)
hdcp 1.3 (page 2) register:: hdcp_cr 0xc0 name bits r/w reset state comments reserve 7 r 0 reserved. reserve 6 r 0 reserved. ivsp 5 r 0 indicate vsync polarity 0: positive, which means vs pulse is high. 1: negative invvs 4 r/w 0 invert vsync for hdcp high: inverted low: not inverted ivspm 3 r/w 0 indicate vsync polarity mode: high: manual, decided by invvs low: auto, indicate by ivsp maddf 2 r/w 0 mcu access ddc data first 0: enable ddc channel and mcu access only when ddc is not busy 1: disable ddc channel and mcu access only dkapde 1 r/w 0 device key access port download enable high: enable low: disable, this would reset the address of devic e key access port to 0. enable 0 r/w 0 hdcp enable high: auto enable hdcp function, when tx i2c write aksv, low: disable hdcp, except for output. register:: hdcp_dkap 0xc1 name bits r/w reset state comments dkap 7:0 r/w 0 when enable device key accessing 40x 56 table, the 56-bit key table will be transferred to 64-bit pseudo data with 7 th , 15 th , 23rd, 31st, 39 th , 47 th , 55 th bits inserted. the inserted data are ?0?.and the write sequence is : {d0-byte0, d0-byte1, d0-byte2, d0-byte3,d0-byte4, d 0-byte5, d0-byte6, d0-byte7}, {d1-byte0, d1-byte1, 1-byte2,d1-byte3, d1-byte4, d1-byte5, d1-byte6, d1-byte7}, ????????????????? accessing this port must be coded/decoded by realte k protection code. register:: hdcp_pcr 0xc2 name bits r/w reset state comments rev 7:5 --- reserved enc_tog 4 r 0 enc toggled. avmute_ dis 3 r/w 1 auto enc_dis when avmute 0: non active 1: active ddcsel 2:0 r/w 0 ddc channel sel for key access 00: ddcscl1/ddcsda1 01: ddcscl2/ddcsda2 1x: reserved. apai 0 r/w 0 hdcp accessing port auto increase (for host side)
0: auto increase 1: keep in the same address. register:: hdcp_ap 0xc3 name bits r/w reset state comments ap 7:0 r/w 0 address port for embedded hdcp access , auto increase after data_port being accessed . (for host side controlled by apai) register:: hdcp_dp 0xc4 name bits r/w reset state comments dp 7:0 r/w 0 data port for embedded hdcp access note : 1. when accessing this ddc register map by ddc, the address should increase automatically, except for the first accessing address is ksv_fifo, 0x43. following register is assigned by ?hdcp-address por t?, ?hdcp-data port? register:: hdcp_fcr 0xc0 name bits r/w reset state comments reserved 7 r -- reserved fc 6:0 r 0 hdcp_frame counter [6:0] register:: hdcp_sir 0xc1 name bits r/w reset state comments ast 7 r 0 authst (means bksv of rtd pass tx authorization, tx is ready to do hdcp transaction) akm 6 r 0 authkm (means rtd finish computing km, ri) //hidden adne 5 r 0 authdone (means tx admitted ri value, start to do h dcp transmission) rea 4 r/w 0 re_auth encm 3 r/w 0 enc_method ence 2 r 0 enc_error nc 1 r 0 no ctrl(hdcp1.0: no ctrl[3], hdcp1.1: ctrl is not 1 001 nor 0001) ib 0 r 0 internal buffer for ainfo[1]. since ainfo[1] in ddc port is 0 at most of time, we need to know what tx wrote. hdcp 1.1/1.0 decide flow. 1. if hdmi conditions happen, hdcp 1.1 is used. 2. when last byte of aksv is written, ainfo[1] indicat es hdcp 1.0/1.1 mode. oess is the same as hdcp 1.0. we could tell it by a info[1] in ddc .
hdcp 1.0/1.1 decide flow (before auth) hdmi ? hdcp 1.1 y wait for last aksv write n ainfo[1] == 1? y n hdcp 1.0 init hdcp 1.0 initial flow. hdcp total flow idle last aksv written? authentication (blockcipher) n y av_mute? y av_mute n ini_pow_on or reset enc_en? frame signal n frame key calculate? advance_cipher? (ac) y n y video_en? dataisd_en? decrypt video (streamcipher) decrypt dataisd (streamcipher) video_en? dataisland_en? line key calc (rekeycipher) y y n n y y n enable signal wait for signals frame signal enable signal 100 ms 58 clocks frame key calculate 118 clocks hdcp 1.0 disable ? hdcp 1.0/1.1 difference item description hdcp 1.0 hdcp 1.1
1 fast reset no constraint in 1.0 it must be done 2 ddc : ainfo useless double buffer 3 ddc : pj no this feature update per 16 frames 4 ddc : bcaps[1] no this feature it is used to tell if rx supports 1.1 5 ddc : bstatus no this feature hdmi mode mapping 6 ddc : short read read ri. read ri & pj. 7 oess/eess only oess compatible depend on ddc info . sync. 8 support protocol dvi ( de only ) dvi & hdmi ( de & dien) 9 ctlx position ctl3 follows vs all info must be in opp. window. 10 error correction no the requirement error correc tion for enc_en/dis 11 vs polarity distinguishment no clear description 1. init is neg. 2. vs debouncing befor de. 3. vs por for open opp window. 12 13 14 frame counter hdcp 1.0 : increase by vs(ctl3). hdcp 1.1 : in oess mode, increase by enc_en in eess mode, increase when a. av_mute = false. & b. ac = 1 or en c_en = 1. note : 1. hdcp output must be always enable for dvi/hdmi. 2. the sub-descriptions i of ri & j of pj are the same .
hdmi video and audio part (page 2) hdmi ip data part hdmi ip control part hdcp ip
register:: hdmi_apc 0xc8 name bits r/w reset state comments reserved 7:1 r/w 0 reserved to 0
aaif 0 r/w 0 address auto increase function 0: if read/write ?hdmi data port? continuously with out assign ?hdmi address port?, address would be not added by one au tomatically. 1: if read/write ?hdmi data port? continuously with out assign ?hdmi address port?, address would be added by one automa tically. register:: hdmi_ap 0xc9 name bits r/w reset state comments ap 7:0 r/w 0 address port for hdmi register:: hdmi_dp 0xca name bits r/w reset state comments dp 7:0 r/w 0 data port for hdmi hdmi register in address data port access addr. name description 0x00 hdmi_scr system control 0x01 hdmi_n_val n times of condition a 0x02 hdmi_bchcr bch control bits 0x03 hdmi_afcr audio flow control 0x04 hdmi_afsr audio fifo status 0x05 hdmi_magcr manual audio gain coefficient 0x06 hdmi_aagcr auto audio gain control 0x10 hdmi_cmcr clock mux control 0x11 hdmi_mcapr m code of audio pll 0x12 hdmi_scapr s code of audio pll 0x13 hdmi_dcapr0 msb of d code of audio pll 0x14 hdmi_dcapr1 lsb of d code of audio pll 0x15 hdmi_pscr phase swallow control 0x16 hdmi_fddr fifo depth at de rising 0x17 hdmi_fddf fifo depth at de falling 0x18 hdmi_mfddr maximum fifo depth at de rising 0x19 hdmi_mfddf minimum fifo depth at de falling 0x1a hdmi_ftr fifo trend register 0x1b hdmi_fbr fifo boundary register 0x1c hdmi_icpsncr0 i code of phase swallow and n/ct s register 0
0x1d hdmi_icpsncr1 i code of phase swallow and n/ct s register 1 0x1e hdmi_pcpsncr0 p code of phase swallow and n/ct s register 0 0x1f hdmi_pcpsncr1 p code of phase swallow and n/ct s register 1 0x20 hdmi_ictpsr0 i code of trend for phase swallow register 0 0x21 hdmi_ictpsr1 i code of trend for phase swallow register 1 0x22 hdmi_pctpsr0 p code of trend for phase swallow register 0 0x23 hdmi_pctpsr1 p code of trend for phase swallow register 1 0x24 hdmi_icbpsr0 i code of boundary for phase swal low register 0 0x25 hdmi_icbpsr1 i code of boundary for phase swal low register 1 0x26 hdmi_pcbpsr0 p code of boundary for phase swal low register 0 0x27 hdmi_pcbpsr1 p code of boundary for phase swal low register 1 0x28 hdmi_ntx1024tr0 number of tx in 1024 tv regist er 0 0x29 hdmi_pcbpsr1 number of tx in 1024 tv register 1 0x2a hdmi_stbpr stop time for boundary pe register 0x2b hdmi_ncper n and cts phase error register 0x2c hdmi_petr phase error threshold register 0x2d hdmi_aapnr action for audio pll non-lock regis ter 0x2e hdmi_apdmcr audio pll debug mode control regis ter 0x30 hdmi_avmcr audio and video mute control regist er 0x31 hdmi_wdcr0 watch dog control register 0 0x32 hdmi_wdcr1 watch dog control register 1 0x33 hdmi_wdcr1 watch dog control register 2 0x34 hdmi_dbcr hdmi double buffer control register 0x35 hdmi_aptmcr0 audio pll test mode control regis ter 0 0x36 hdmi_aptmcr1 audio pll test mode control regis ter 1 0x38 hdmi_dpcr0 dpll control register 0 0x39 hdmi_dpcr1 dpll control register 1 0x3a hdmi_dpcr2 dpll control register 2 0x3b hdmi_dpcr3 dpll control register 3 0x40 hdmi_awdsr audio watch dog status register 0x41 hdmi_vwdsr video watch dog status register 0x42 hdmi_pamicr packet acquire mechanism interrupt control register 0x43 hdmi_ptrsv1 packet type of rsv1 packet 0x44 hdmi_ptrsv2 packet type of rsv2 packet
0x45 hdmi_pvgcr0 packet variation global control re gister 0 0x46 hdmi_pvgcr1 packet variation global control re gister 1 0x47 hdmi_pvgcr2 packet variation global control re gister 2 0x48 hdmi_pvsr0 packet variation status register 0 0x49 hdmi_pvsr1 packet variation status register 1 0x4a hdmi_pvsr2 packet variation status register 2 0x50 hdmi_vcr video control register 0x51 hdmi_acrcr acr control register 0x52 hdmi_acrsr0 acr status register 0 0x53 hdmi_acrsr1 acr status register 1 0x54 hdmi_acrsr2 acr status register 2 0x55 hdmi_acrsr3 acr status register 3 0x56 hdmi_acrsr4 acr status register 4 0x57 hdmi_acs0 audio channel status 0 0x58 hdmi_acs1 audio channel status 1 0x59 hdmi_acs2 audio channel status 2 0x5a hdmi_acs3 audio channel status 3 0x5b hdmi_acs4 audio channel status 4 0x60 hdmi_intcr hdmi interrupt control register 0x61 hdmi_alcr audio layout control register 0x62 hdmi_aocr audio output control register 0x70 hdmi_bcsr hdmi basic coding status register 0x71 hdmi_asr0 audio status register 0 0x72 hdmi_asr1 audio status register 1 register:: hdmi_sr 0xcb name bits r/w reset state comments reserved 7 --- 0 reserved avmute 6 r 0 av_mute flag of general control packet 0: if hw receive clear _avmute flag of general cont rol packet ,this bit shall assign to 0 until hw receive set _avmute 1: if hw receive set_avmute flag of general control packet ,this bit shall assign to 1 until hw receive clear_avmute note : if hw never receives ?general control packet?, this bit shall set to 0. if hw receive ?general control packet? with clear_a vmute flag = 0 & set_avmute flag = 0, this bit shall keep previous v alue.
if hw receive ?general control packet? with clear_a vmute flag = 1 & set_avmute flag = 1, this bit shall keep previous v alue, but set ?general control packet error flag?. vic 5 r 0 if vic(in avi infoframe) is different with pervious value ,this bit would be assigned to 1 until clear this bit. (write 1 cle ar for each bit) spdiftyp e 4 r 0 spdif coding type 0: lpcm 1: non-lpcm pllsts 3 r 0 pll status. this bit is global status, we could wat ch more detail information in pll detail status byte. (write 1 clear for each bit) 1: non-lock 0: lock afifoof 2 r 0 0: audio fifo isn?t overflow for x samples 1: audio fifo is overflow for x sample (write 1 clear for each bit) if audio fifo has stayed at overflow state for x-sa mple periods, this bit would be set to ?1? until f/w clear this bit. afifouf 1 r 0 0: audio fifo isn?t underflow for y samples 1: audio fifo is underflow for y sample (write 1 clear for each bit) if audio fifo has stayed at underflow state for y-s ample periods, this bit would be set to ?1? until f/w clear this bit. mode 0 r 0 hdmi/dvi mode detected by auto function, even in ma nual mode, this bit could indicate decision of auto function. 0: dvi 1: hdmi fw should read ?pll status? after 0.66ms~3 ms from fw clear this bit. register:: hdmi_gpvs 0xcc name bits r/w reset state comments nps 7 r 0 null packet status pis 6:5 r 0 packet input status 6: rsv1 received 5: rsv0 received pvs 4:0 r 0 packet variation status 0: avi infoframe 1: audio infoframe 2: acp 3: isrc1 4: mpeg infoframe note. write 1 clear ?packet variation status?: 1. ?packet variation status? means packet content vari ation, bit4 ~ bit 0 corresponds to avi info-frame, audio info-frame, acp, isrc1, and mpeg info-frame respect ively. 2. before fw process the corresponding action item, fw should clear the corresponding bit of ?global pack et variation status?. 3. then fw read the content of the corresponding packe t, polling ?global packet variation status?, check if corresponding bit of ?global packet variation statu s? is 0, and execute follow-up action item if .this bit is 0. 4. jump to step 2 if this bit is 1. 5. the variation result appears in ?global packet vari ation status? after the corresponding packet finish transmitting. ?packet input status?: 1. ?packet input status? represents updated status of rsv1, rsv0 respectively. if it is updated, ?packet input status? is assigned to 1 until f/w clear this bit. 2. ?null packet status? :when receive null packet , ?n ull packet status? is assigned to 1until f/w clear this bit 3. if one bit of ?packet variation status? is cleared, the corresponding bit of ?local variation flag for detail info? is also cleared. register:: hdmi_psap 0xcd
name bits r/w reset state comments apss 7:0 r/w 0 address for packet storage sram register:: hdmi_psdp 0xce name bits r/w reset state comments dpss 7:0 r 0 data port for packet storage sram bch is stored in the 1 st address of each packet type, its content is stated as following; bit0: 2-bit error for bch header (0: 2-bit error do esn?t occur; 1: 2-bit error occurs) bit1: 2-bit error for bch block 0 (0: 2-bit error d oesn?t occur; 1: 2-bit error occurs) bit2: 2-bit error for bch block 1 (0: 2-bit error d oesn?t occur; 1: 2-bit error occurs) bit3: 2-bit error for bch block 2 (0: 2-bit error d oesn?t occur; 1: 2-bit error occurs) bit4: 2-bit error for bch block 3 (0: 2-bit error d oesn?t occur; 1: 2-bit error occurs) bit5: checksum result (0: checksum error doesn?t oc cur; 1: checksum error occurs) packet type and address packet type variation status storage ( byte ) ( + means bch) address needed ( 8 bits/add ) address avi info 9+1(global) 16+ 17 0~16 audio info 4+1 8+ 9 17~25 acp 3+1 4+ 5 26~30 isrc1 1+1 18+ 19 31~49 isrc2 x 18+ 19 50~68 mpeg info 3+1 8+ 9 69~77 rsv0 1, only global 30+ 31 78~108 rsv1 1, only global 30+ 31 109~139 table 2 packet type and address sram map table following register is assigned by ?hdmi-address port?, ?hdmi-data port? register:: hdmi_scr 0x00 name bits r/w reset state comments reserved 7:4 -- 0 reserved to 0 mode 3 r/w 0 hdmi/dvi switch mode 0: auto detect flow is as fig.1 1: manual msmode 2 r/w 0 manual switch hdmi/dvi 0: dvi 1: hdmi cabs 1 r/w 0 dvi/hdmi condition a, b select 0: condition a: detect data island preamble + data island guard band (appear count is decided by ?n?) condition b: detect if data island preamble + dat a island guard band
appear in continuous 30 or 2 frames(decide by bit 0 ) 1: condition a: detect data island preamble + data island guard band & video preamble + video guard band(appear count is decided by ?n?) condition b: detect if data island preamble + dat a island guard band & video preamble + video guard band appear in continu ous 30 or 2 frames(decide by bit 0) fcddip 0 r/w 0 frame count to detect data island packet (condition b) 0: 2 frames 1: 30 frames
1. hdmi/dvi auto switch mode , the information must be passed to hdcp : dvi/hdmi decision flow is shown as below. d v i/ h d m i d e c id e flow c o nd itio n a ? h d m i y d v i (in it) c o nd itio n b ? y n n fig 1 2. power saving for hdmi/hdcp : in power saving mode, tmds channel green/red are al ways turn off. hdmi is power down. there are only tmds clock input frequency detect an d channel blue de decoder working. the channel blue de decoder is active after clock f requency is ok. register:: hdmi_n_val 0x01 name bits r/w reset state comments nval 7:0 r/w 1 n= 00 : x 01 : 1 ff : 255 n = 1 ~ 255 , n can?t be assigned to 0x00 register:: hdmi_bchcr 0x02 name bits r/w reset state comments reserved 7:6 --- 0 reserved to 0 spcss 5 r/w 0 spdif preamble channel status source, when pll is non-lock 0: input audio sample (normal) 1: internal system enrwe 4 r/w 0 enable noise reduction when bch error is greater th an one. 1: enable noise reduction 0: disable noise reduction bche 3 r/w 1 bch function enable 1: enable bch function 0: disable bch function, bit[2:1] are always 2?b00. bches 2 r 0 bch function?s result, one bit error. it is set by this case, and cleared by write 1. this bit is the result of oring 5 bits bch 1 bit er ror.
1: one bit error occurs. 0: no error occurs note: if bch detect 1-bit error, this bit would be assigned to 1 until clear this bit bches2 1 r 0 bch function?s result, two bits error. it is set by this case, and cleared by write 1. this bit is the result of oring 5 bits bch 1 bit er ror. 1: 2-bit error occurs 0: 2-bit error don?t occurs if bch detect 2-bit error, this bit would be assign ed to 1 until clear this bit pe 0 r/w 0 the processing for packet with two or more bch erro r (not include audio packet) 1: block info frame message 0: as correct frame, decided by f/w note! audio samples always go to fifo register:: hdmi_afcr 0x03 name bits r/w reset state comments reserved 7 --- 0 reserved to 0 aoem 6 r/w 1 audio output enable mode 1: auto audio output flow, bit[5:0] could be assign ed by hw, but couldn?t be assigned by fw. 0: manual audio output flow, bit[5:0] could be assi gned by fw, but couldn?t be assigned by hw. aoc 5 r 0 audio output on/off control 0: audio output off, cut off audio output immediate ly in ?manual audio output flow? , and audio output is turned on by aut o audio output flow gradually in ?auto audio output flow?. 1: audio output on, switch on audio output immediat ely in ?manual audio output flow?, and audio output is turned on by auto audio output flow gradually in ?auto audio output flow?. audio_t est_ena ble 4 r/w 1 0:disable 1:generate sine wave to iis/spdif internally this is assigned to ?1? in iis/spdif test mode, but it is assigned to ?0? in normal mode. mgc 3 r/w 0 manual gain contro l 1: enable gain control, gain is decided by ?manual audio gain coefficient? 0: disable gain control, gain = 1 afifowe 2 r/w 0 audio fifo write enable 0: disable, no audio sample would go in audio fifo. this bit would clear audio fifo status, including read/write address, ov fl, unfl, and etc. 1: enable fifo audio write, and enable bit[1:0] fun ction, read control . (if buffer write to target depth, new data read out act ion is controlled by bit1). afifore 1:0 r/w 0 audio fifo read enable, this bit is only active whe n bit[2] = 1, 00: no audio frequency read, only drop old data whe n new data in. 01: audio sample which read form fifo repeats previ ous sample, only drop old data when new data in. 1x: use audio frequency to read out fifo.
audio noise reduction 1 backup packet(prev) bch ok ? read required packet(current) ctrl data y play current data read next required packet(next) ctrl data n bch ok ? y n play average of prev & next play prev packet register:: hdmi_afsr 0x04 name bits r/w reset state comments reserved 7:6 --- 0 reserved bistr 5 r 1 audio fifo bist result 0: fail 1: success bists 4 r/w 0 audio fifo bist start (embedded test pattern) 0: stop 1: start(auto clear) afifof 3 r 0 audio fifo full (write clear) 0: indicate fifo is not full. 1: indicate fifo is full. afifoe 2 r 0 audio fifo empty(write clear) 0: indicate fifo is not empty. 1: indicate fifo is empty. reserved 1:0 --- 0 reserved to 0 register:: hdmi_magcr 0x05 name bits r/w reset state comments mg 7:0 r/w 0 manual gain . unsigned floating. note, gain value here is alway s less than 1 . 8?h00 = 0 8?hff = 1 ? 2^-8 only valid when ?manual gain control? is enabled in ?manual audio output flow? register:: hdmi_magcr 0x06 name bits r/w reset comments
state reserved 7:6 --- 0 reserved to 0 agi 5:3 r/w 4 auto gain incremental 000 : 2^ -8 001 : 2^ -7 010 : 2^ -6 ? 111 : 2^ -1 agd 2:0 r/w 4 auto gain delay 000 : 2^0 sample 001 : 2^1 samples 010 : 2^2 samples ? 111 : 2^7 samples the total meanings of this byte are: when function is on, gain increase from 0 to 1 with ?incremental? per ?delay?. when function is off, gain decrease from 1 to 0 wit h ?-inc? per ?delay?. so that the default value means increase 2^-5 per 1 6 samples. only valid in ?auto audio output flow?
audio clock regeneration definition : fx : frequency of crystal fps : frequency after p.s fv : frequency of video ffb : feed back frequency fa : audio frequency p.s : phase swallow fout : 128 * fa p : number of phase far : recovered 128 * fa d : p.s density, shift d phase per cycle fm : freq. of mux-clock df : fine tune of d fvco : frequency after vco t* : period of f* note!!! signed number and detail procedures are not ready. register:: hdmi_cmcr 0x10 name bits r/w reset state comments icmux 7 r/w 0 input clock mux 1: use video clock as input 0: use crystal clock as input ocs 6:5 r/w 2 output clock select 00: use crystal clock as output clock. 01: use bckin as output clock 1x: use generated clock, far, as output clock (must set when power-saving) dbdcb 4 r/w 0 double buffer download control bit enable is also triggered by hw, ref. ?phase error m ode?. 1: write current data to active buffer. 0: after write done, this bit would be cleared auto matically. when set this bit to 1, ? k?, ?s?, ?s1?, ?m?, ?d?, ?o?, ?dpllbpn?, ?in/out clk mux?, ?phase tracking enable control bits? woul d fill in after finish current audio pll cycle and then set this bit to 0. kcapll 3:0 r/w 3 k code of audio pll , the value set here adding 1 is real div value 0000: div 2 1111: div 17
if ?dpllbpn? == 1'b1, no div, else, div number is d ecided by these four bits. note: 1. when reading the registers with double buffers, the read-out value is the value in the 2nd buffer, not the value just written. 2. the meaning of default value of registers with doub le buffers is that default values of both 1 st registers and 2nd buffer are the value written in spec. register:: hdmi_mcapr 0x11 name bits r/w reset state comments mc 7:0 r/w 4e m code 00: div 2 ff: div 257 register:: hdmi_scapr 0x12 name bits r/w reset state comments slc 7 r/w 0 s1 code 0: div 1 1: div 2 sc 6:0 r/w 5 s/2 code register:: hdmi_dcapr0 0x13 name bits r/w reset state comments dcapr 7:0 r/w 0 d[15:8] register:: hdmi_dcapr1 0x14 name bits r/w reset state comments dcapr 7:0 r/w 0 d[7:0] register:: hdmi_pscr 0x15 name bits r/w reset state comments fdint 7:5 r/w 7 when max. fifo depth increase for n times or min. f ifo depth decrease for n times, turn fifo tracking mechanism 000 : xx 001 : n=2,don?t use this value for normal case 010 : n=3 011 : n=4 100 : n=5 101 : n=6 110 : n=7 111 : n=8 etcn 4 r/w 0 enable tracking of cts & n 0: disable. 1: enable. etfd 3 r/w 0 enable tracking of the trend of fifo depth 0: disable. 1: enable. etfbc 2 r/w 0 enable tracking of fifo boundary condition (this bit is suggested to be 1) 0: disable. 1: enable. pecs 1:0 r/w 1 phase error count source(cts & n) 00 : phase error counted by video clock 01 : phase error counted by crystal clock
10 : phase error counted by fps/4, fdds 11 : it is too fast, about 500mhz,to be used note. phase tracking control bits is bit4~bit2. register:: hdmi_fddr 0x16 name bits r/w reset state comments fddr 7:0 r 0 fifo depth at de rising , this unit is number of samples, register:: hdmi_fddf 0x17 name bits r/w reset state comments fddf 7:0 r 0 fifo depth at de falling register:: hdmi_mfddr 0x18 name bits r/w reset state comments mfddr 7:0 r 0 max. fifo depth at de rising . auto clear to 0x00 when up-trend is confirmed and frequency up is triggered. write 1 to clear this byte as 0x00.the clear action needs video clock to work. register:: hdmi_mfddf 0x19 name bits r/w reset state comments mfddf 7:0 r 0 min. fifo depth at de falling . auto clear to 0xff when down-trend is confirmed and frequency down is triggered. write 1 to clear this byte as 0x00.the clear action needs video clock to work. write 1 to clear. register:: hdmi_ftr 0x1a name bits r/w reset state comments tl2der 7:6 r 0 trend of latest 2 de rising . 0x: the same 10: trend down, which means fifo depth goes lower a nd lower. 11: trend up, which means fifo depth goes larger an d larger. tl2def 5:4 r 0 trend of latest 2 de falling . 0x: the same 10: trend down, which means fifo depth goes lower a nd lower. 11: trend up, which means fifo depth goes larger an d larger. tt 3:0 r/w 7 target times for summation of one trend to decide t he trend . times = value set + 1 0000 : 1, 1111 : 16 register:: hdmi_fbr 0x1b name bits r/w reset state comments tfd 7:3 r/w e target fifo depth , the unit is 4 address, and 16 bits in one address . bad 2:0 r/w 2 boundary address distance for triggering audio pll tracking where boundary address= value set * 4, and 16 bits per ad dress. 4 bytes*16 bits is one sample. when the value is 2,number of sample is 0,1,31,and 32 will trigger boundary condition. value 0 can?t be used. register:: hdmi_icpsncr0 0x1c name bits r/w reset state comments
ic 7:0 r/w 0 i code of n/cts [15:8] register:: hdmi_icpsncr1 0x1d name bits r/w reset state comments ic 7:0 r/w 0 i code of n/cts [7:0] register:: hdmi_pcpsncr0 0x1e name bits r/w reset state comments pc 7:0 r/w 0 p code of n/cts [15:8] register:: hdmi_pcpsncr1 0x1f name bits r/w reset state comments pc 7:0 r/w 0 p code of n/cts [7:0] register:: hdmi_ictpsr0 0x20 name bits r/w reset state comments ict 7:0 r/w 0 i code of trend [15:8] register:: hdmi_ictpsr1 0x21 name bits r/w reset state comments ict 7:0 r/w 0 i code of trend [7:0] register:: hdmi_pctpsr0 0x22 name bits r/w reset state comments pct 7:0 r/w 0 p code of trend [15:8] register:: hdmi_pctpsr1 0x23 name bits r/w reset state comments pct 7:0 r/w 0 p code of trend [7:0] register:: hdmi_icbpsr0 0x24 name bits r/w reset state comments icb 7:0 r/w 0 i code of boundary [15:8] register:: hdmi_icbpsr1 0x25 name bits r/w reset state comments icb 7:0 r/w 0 i code of boundary [7:0] register:: hdmi_pcbpsr0 0x26 name bits r/w reset state comments pcb 7:0 r/w 0 p code of boundary [15:8] register:: hdmi_pcbpsr1 0x27 name bits r/w reset state comments pcb 7:0 r/w 0 p code of boundary [7:0]
register:: hdmi_ntx1024tr0 0x28 name bits r/w reset state comments reserved 7:4 --- 0 reserved to 0 rm 3 r/w 0 restart measure . measure the length of 1024 tv by crystal. the res ult is readable from the following bits. 1: enable measure. writing 1 would clear the answer . this bit would be auto cleared after measure done. 0: indicating measure is done. nt 2:0 r 0 number of tx for 1024 tv [10:8] , (how many tx = 1024 * tv) register:: hdmi_ntx1024tr1 0x29 name bits r/w reset state comments nt 7:0 r/w 0 number of tx for 1024 tv [7:0] , (how many tx = 1024 * tv) register:: hdmi_stbpr 0x2a name bits r/w reset state comments ftb 7:0 r/w 0 the fast time for boundary df repeating . the unit is 16 crystal clock. 8?h00: 16 crystal clock. 8?h7f: 128 * 16 crystal clock. register:: hdmi_ncper 0x2b name bits r/w reset state comments ncper 7:0 r 0 phase error equals how many numbers of measuring cl ock, pe[7:0] note!! the active pi code of cts&n would have propo rtional alike relation with phase error. the value of this byte is record of the maximum val ue after last write. write this byte when fpec exists would clear the va lue to 0. when ?pe_mode?==1, delay mode, the max value of pha se error is 40. when ?pe_mode?==1, clock mode, the max value of pha se error is ff. register:: hdmi_petr 0x2c name bits r/w reset state comments petr 7:0 r/w ff phase error threshold of audio pll non-lock if ?phase error? is greater than phase error thresh old, ?pll status? would be automatically assigned t o 1 until fw clear it. register:: hdmi_aapnr 0x2d name bits r/w reset state comments cmvtc 7 r/w 0 clear max value ( 18, 19 ) when trend condition is sure. 1: enable trend to clear max value 0: disable this function cmvbc 6 r/w 0 clear max value (18, 19) when boundary condition is sure. 1: enable boundary to clear max value 0: disable this function ssdmou 5 r 0 flag of sum_r of sdm overflow/underflow ( read only ) 1: overflow or underflow happened 0: no overflow, no underflow tef 4 r/w 0 trend error flag 1: detect up and down at the same time. clear only when disable sdm ( 2d[1] = 0 ) 0: trend is ok. w1c5 3 w 0 write 1 to clear bit [5]
pem 2 r/w 0 phase error mode , 1: use delay to calculate, each unit is 0.1 ns. 0: use clock to calculate, the clock select is at ? pe count source?. esdm 1 r/w 0 enable sdm (phase swallow) 1: enable 0: disable, there won?t be phase swallow operating in the loop of pll. reserved 0 --- 0 reserved register:: hdmi_apdmcr 0x2e name bits r/w reset state comments reserved 7:6 --- 0 reserved edm 5 r/w 0 enable debug mode 0: normal run 1: enable when test mode pst 4 r/w 0 phase swallow trend 0: fast direction 1: slow direction psc 3:0 r/w 0 phase swallow cycle. any bit is set to 1 for swallow, 0 for hold. behavior description of audio pll non-clock when system receive new audio or video timing , aud io pll would non-lock ,and watch dog mechanism woul d force audio output to mute state(i2s dac: mclk,sclk , and lrck normal output, but sdata output zero),so system should provide a stable fout to i2s dac in a udio mute state. in the transition form normal fout to mute fout , f out frequency couldn?t change too much, for this re ason ,hw provide double buffers of mechanism of ? k?, ?s?, ? s1?, ?m?, ?d?, ?o?, ?dpllbpn?, ?in/out clk mux?, ?p hase tracking enable control bits?. for initial state, a stable fv input to audio pll, and audio pll would lock by use suitable ?kmsdo?&pi code.the suitable ?kmsdo? could be named as ?kmsdo1 ?,and it would save in 2nd buffer(the value of 2nd buffer could be applied to audio pll directly , and that o f 1st buffer is used to backup, when ?double buffer download control bit? is assigned to 1,the value of 1st buff er would be downloaded to 2nd buffer).f/w should ca lculate ?kmsdo2? of crystal clock input to produce a fout w hich is the same as present fout ,then save kmsdo2 in 1st buffer of kmsdo, f/w also assign ?phase tracking co ntrol bits? to 000?b in 1 st buffer, and assign ?input clock mux? to ?crystal input? in 1st budder. when audio pll is non-lock(change audio frequency o r video frequency),the 1st buffer content of ?kmsdo ?, ?phase tracking control bits?, and ?input clock mux ? would download to their corresponding 2nd buffers . then audio pll would switch input to crystal in, apply kmsdo2, and disable phase tracking at the same time, and pr ovide a stable fout to i2sdac foe mute state. in mute state, f/w calculate kmsdo(kmsdo3) of new a udio or video timing, assign kmsdo3 in 1st buffer of kmsdo, f/w also assign ?enable setting? in 1st b uffer of phase tracking enable control, and assign ?video input? to second buffer of input clock mux.
assign pi code, then double buffer download control bit is assigned to 1, audio pll would switch input to video in, apply kmsdo3, and disable phase tracking at the same time, and provide a fout for new video and audio timing. register:: hdmi_avmcr 0x30 name bits r/w reset state comments reserved 7 -- 0 reserved aoc 6 r/w 0 audio output enable/disable control 1: enable 0: disable if this bit is enabled, audio output signal would b e controlled by bit4. when fw set this bit to 1, then hw will return this bit to 0 if audio pll non-lock if audio pll non-lock. aomc 5 r/w 0 audio output mute control 1: normal output 0: mute if bit 5 is 0, output of i2s & spdif shall be disab led regardless of 1 or 0 in this bit for ?auto audio output flow?. when fw set this bit to 1,then hw will return this bit to 0 if audio pll is non-lock awd 4 r/w 0 if audio watch dog event occur, audio output would be 0: mute 1: disable ve 3 r/w 0 video enable 1: enable video output 0: disable video output ampic 2 r/w 0 audio mute pin invert control, execute when mute/di sable happens . 0: when event (audio mute or disable) occur, set th is pin to low voltage, others maintain high. 1: when event (audio mute or disable) occur, set th is pin to high voltage, others maintain low vdpic 1 r/w 0 video disable pin invert control 0: when event (video disable) occurred, set this pi n to low voltage, others maintain high. 1: when event (video disable) occurred, set this pi n to high voltage, others maintain low. nfpss 0 r/w 0 irq output pin polarity inverse 0: no inverse, which means h : irq, l : no irq 1: inverse, which means h : no irq l : irq definition: disable video assign ?de pins?, ?vs pin?, ?hs pin?, ?ctrl(4) pins ?, ?clk pin?, ?data(24) pins? to zero , refer to ?global system? mute audio 1. in i2s application, keep mclk*4, sclk*4, and lrck*4 to normal output,but cut sdata*4 to zero. 2. in spdif application,keep preamble(m,b,w) to normal output, but cut other bits to zero.
disable audio i2s => assign mclk*4, sclk*4, and lrck*4 and sdata* 4 to zero. spdif => assign all bits to zero. register:: hdmi_wdcr0 0x31 name bits r/w reset state comments asmfe 7 r/w 1 auto set_ avmute function enable 0: if hw receives set_avmute flag, don?t mute/disab le audio & disable video by hw. 1: if hw receives set_avmute flag, mute/disable aud io & disable video by hw. note: if ?clear_avmute? and ?set_avmute? of the general c ontrol packet are all 1, keep previous a/v output state, a nd pull up ?general control packet error flag? reserved 6 --- 1 reserved to 1 reserved 5 --- 0 reserved to 0 awdct 4 r/w 0 audio watch dog for audio coding type(decode from s pdif, code type only include lpcm or non-lpcm) 0: if coding type is different with previous type, don?t mute/disable audio by hw. 1: if coding type is different with previous type, mute/disable audio by hw. awdap 3 r/w 0 audio watch dog enable for audio pll 0: if audio pll is non-lock, don?t mute/disable aud io by hw. 1: if audio pll is non-lock, mute audio , mute/disa ble audio by hw. awdfo 2 r/w 0 audio watch dog function for audio fifo overflow fo r ?x? sample. 0: if audio fifo is overflow for x samples , don?t mute/disable audio by hw. 1: if audio fifo is overflow for x samples, mute/di sable audio by hw. awdfu 1 r/w 0 audio watch dog function for audio fifo underflow f or ?y? sample. 0: if audio fifo is underflow for y samples, don?t mute/disable audio by hw. 1: if audio fifo is underflow for y samples, mute/d isable audio by hw. ct 0 r/w 0 ?spdif coding type? is decoded by 0: channel status bit 1 1: valid bit audio/video watch dog for ?packet acquire mechanism ? is listed in packet acquire mechanism unit. register:: hdmi_wdcr1 0x32 name bits r/w reset state comments awdck 7 r/w 0 audio watch dog for tmds clock 1: if tmds clock disappears, mute or disable audio. 0 : if tmds clock disappears, doesn?t mute or disable audio. awdlf 6 r/w 0 audio watch dog for layout field of audio sample pa cket 1: if layout field is different with previous value , mute or disable audio. 0: if layout field is different with previous value , don?t mute or disable audio. rev 5 --- 0 reserved vwdact 4 r/w 0 video watch dog for audio coding type 1: if coding type is different with previous type, disable video 0: if coding type is different with previous type, don?t disable video xv 3:0 r/w 0 x value 0000: 1 0001: 3 ~
1111: 31 register:: hdmi_wdcr2 0x33 name bits r/w reset state comments vwdap 7 r/w 0 video watch dog enable for audio pll 1: if audio pll is non-lock, disable video 0: if audio pll is non-lock, don?t disable video vwdlf 6 r/w 0 video watch dog for layout field of audio sample pa cket 1: if layout field is different with previous value , disable video. 0: if layout field is different with previous value , don?t disable video. vwdafo 5 r/w 0 video watch dog function for audio fifo overflow. 1: if audio fifo is overflow for ?x? samples, disab le video. 0: if audio fifo is overflow for ?x? samples, don?t disable video. vwdafu 4 r/w 0 video watch dog function for audio fifo underfloww . 1: if audio fifo is underflow for ?y? samples, disa ble video. 0: if audio fifo is overflow for ?y? samples, don?t disable video yv 3:0 r/w 0 y value 0000:1 0001:3 ~ 1111:31 register:: hdmi_dbcr 0x34 name bits r/w reset state comments reserved 7:4 --- 0 reserved aldbfv 3 r/w 0 auto load double buffer when tmds clock disappear 0: if tmds clock disappear , don?t assign ?double b uffer download control bit? to 1 by hw 1: if tmds clock disappear, assign ?double buffer d ownload control bit? to 1 by hw. note: if this bit is 0, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by assigned ?double buffer download control bit? to 1. if this bit is 1, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by hw if fv < 25mhz or fv > 165mhz. aldbfo 2 r/w 0 auto load double buffer when fifo overflow is for x samples. 0: if audio fifo is overflow for x samples, don?t a ssign ?double buffer download control bit? to 1 by hw 1: if fifo is overflow for x samples, assign ?doubl e buffer download control bit? to 1 by hw. note: if this bit is 0, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by assigned ?double buffer download control bit? to 1. if this bit is 1, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by hw if fifo is overflow for x samples. aldbfu 1 r/w 0 auto load double buffer when fifo underflow is for y samples. 0: if audio fifo is underflow for y samples, don?t assign ?double buffer download control bit? to 1 by hw 1: if fifo is underflow for y samples, assign ?doub le buffer download control bit? to 1 by hw. note: if this bit is 0, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by assigned ?double buffer download control bit? to 1. if this bit is 1, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by hw if fifo is underflow for y samples. aldbpn 0 r/w 0 auto load double buffer when pll non-lock. this function needs crystal clock to work, which me ans it can?t work when
power down. after pll non-lock, 0: if audio pll non-lock occurred, don?t assign ?do uble buffer download control bit? to 1 by hw 1: if audio pll non-lock occurred, assign ?double b uffer download control bit? to 1 by hw. note: if this bit is 0, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by assigned ?double buffer download control bit? to 1. if this bit is 1, ?phase tracking control bits? sha ll be downloaded to 2 nd buffer by hw if ?pll status? is non-lock. register:: hdmi_ aptmcr0 0x35 name bits r/w reset state comments fps 7:4 r/w 0 1 st phase shift amount for a step sps 3:0 r/w 0 2 nd phase shift amount for a step register:: hdmi_ aptmcr1 0x36 name bits r/w reset state comments reserved 7 --- 0 reserved plltm 6 r/w 0 pll test mode enable 1: enable 0: disable fpsd 5 r/w 0 1 st phase shift direction 0: upwards 1: downwards spsd 4 r/w 0 2 nd phase shift direction 0: upwards 1: downwards nfpss 3:0 r/w 0 number of 1 st phase shift step in test mode, pll shift its phase by 16 steps perio dically. the steps which are performed in 1 st phase each 16 steps could be assigned by ?number of 1 st phase shift step?, remaining steps are performed i n 2 nd phase. register:: hdmi_dpcr0 0x38 name bits r/w reset state comments dpllc2 7 r/w 1 dpllpwdn 0: power up 1: power down dpllc1 6 r/w 0 dpllfreeze 0: normal 1: freeze dpllc0 5:4 r/w 0 dpllo div 2^(dpllo) dpll_cal bp 3 r/w 0 dpll bypass calibration(active high) dpll_cal sw 2 r/w 0 calibration validated (go high after power on 1200u s) dpll_cal lch 1 r/w 0 latch calibration (go high after power on 1100us) dpll_cmp en 0 r/w 0 cmp enable (go high after power on 1000us) register:: hdmi_dpcr1 0x39 name bits r/w reset comments
state dpll_rs 7:5 r/w 3 dpll loop filter resister control rs: 000:16k 001:18k 010:20k 011:22k 100: 24k 101: 26k 110:28k 111:30k dpll_cs 4:3 r/w 2 dpll loop filter capacitor control cs= 00:18p, 01:20p, 10:24p, 11:28p dpll_ip 2:0 r/w 2 dpll charge pump current control icp=(2.5ua+2.5ua*bit[0]+5ua*bit[1]+10ua*bit[2]) keep dpm/icp constant=10.67 register:: hdmi_dpcr2 0x3a name bits r/w reset state comments dpllstatus 7 r 0 dpllstatus(dpll wd status) 0:normal 1:abnormal dpllwdrst 6 r/w 0 dpllwdrst(dpll wd reset) 0:normal 1:reset dpllwdset 5 r/w 0 dpllwdset(dpll wd set) 0:normal 1:set dpll_vcomd 4:3 r/w 3 dpll vco default mode 00: vco slowest, 11: vco fastest dpllreserve 2 r/w 1 dpllreserve, phase swallow circuit clock select 0: fvco, default is 1 1: fps dpllstop 1 r/w 1 dpllstop(dpll frequency tuning enable) 0:disable 1:enable dpll_cp 0 r/w 0 cp control 0:cp=1.77pf 1:cp=2.1pf register:: hdmi_dpcr3 0x3b name bits r/w reset state comments dpll_vo2 7 r 0 dpll cal out2 dpll_vo1 6 r 0 dpll cal out1 dpll_cal 5:4 r 0 dpll calibrated vco code reserved 3 r/w 0 reserved. dpllbpn 2 r/w 0 dpllbpn 0: divider k enable 1: divider k disable(k=1) dpll_res erve1 1 r/w 0 dpll_reserve1 dpllvcor stb 0 r/w 0 reset vco (active high)
packet acquire mechanism register:: hdmi_awdsr 0x40 name bits r/w reset state comments reserved 7:5 --- 0 reserved to 0 awdpvsb 4:0 r/w 0 audio watch dog for packet variation status bit if a bit is assigned to 1 and the corresponding bit of ?global packet variation status? is 1, audio ou tput will be disabled/muted. register:: hdmi_vwdsr 0x41 name bits r/w reset state comments reserved 7:5 --- 0 reserved to 0 vwdpvsb 4:0 r/w 0 video watch dog for packet variation status bit if a bit is assigned to 1 and the corresponding bit of ?global packet variation status? is 1, video ou tput will be disabled. register:: hdmi_pamicr 0x42 name bits r/w reset state comments reserved 7:5 --- 0 reserved to 0 icpvsb 4:0 r/w 0 irq control for packet variation status bit if a bit is assigned to 1 and the corresponding bit of ?global packet variation status? is 1, issue ir q signal. note: the corresponding bit of ?global packet varia tion status? means bit0 maps to bit 0 of ?global pa cket variation status ,bit1? maps to bit 1 of ?global packet varia tion status?,?etc. register:: hdmi_ptrsv1 0x43 name bits r/w reset state comments pt 7:0 r/w 0 packet type of rsv1 packet register:: hdmi_ptrsv2 0x44 name bits r/w reset state comments pt 7:0 r/w 0 packet type of rsv2 packet register:: hdmi_pvgcr0 0x45 name bits r/w reset state comments pvsef 7:0 r/w ff bit7 ~ bit0 of packet variation status enable flag register:: hdmi_pvgcr1 0x46 name bits r/w reset state comments pvsef 7:0 r/w ff bit15 ~ bit8 of packet variation status enable flag register:: hdmi_pvgcr2 0x47 name bits r/w reset state comments reserved 7:4 --- 0 reserved pvsef 3:0 r/w f bit19 ~ bit16 of packet variation status enable fla g when the bits of enable ?packet variation global co ntrol register? are set, the corresponding ?packet variation status register? bits will or to ?packet variation global control register?. register:: hdmi_pvsr0 0x48 name bits r/w reset state comments
pvs 7:0 r 0 bit7 ~ bit0 of packet variation status register:: hdmi_pvsr1 0x49 name bits r/w reset state comments pvs 7:0 r 0 bit15 ~ bit8 of packet variation status register:: hdmi_pvsr2 0x4a name bits r/w reset state comments reserved 7:4 --- 0 reserved pvs 3:0 r 0 bit19 ~ bit16 of packet variation status there are 20 bits ?enable flags to global packet va riation?. each bit is set to watching a standard ty pe of received packet content, and checking if it changed from the previous received packet. if received packet content changed from previous re ceived one, the relative bit in ?local variation fl ag for detail info.? register will be set, and it will trigger th e ?global packet variation status? set. the following table presents the detail of ?local v ariation flag for detail info.? infoframe bit description 0 y0y1change 1 a0,r0,r1,r2,r3 change 2 s0,s1 any bit change 3 c0,c1 change 4 m0,m1 change 5 vic0 ~ vic6 change 6 pr0 ~ pr6 change 7 sc1,sc0 change avi 8 b0,b1,top bar, bottom bar, left bar , right bar c hange 9 cc0~cc3 change 10 ca0~ca7 change 11 lsv0~lsv3 change audio 12 dm_inh any bit change 13 acp_type change 14 dvd-audio_type_dependent_generation change acp 15 copy_permission, copy_number,quality,& transacti on change isrc1 16 isrc_status change 17 mb#3~mb#0 change 18 fr0 change mpeg 19 mf1,mf0 change register:: hdmi_vcr 0x50 name bits r/w reset state comments eoi 7 r/w 0 even/odd inverse 0: normal
1: inverse eot 6 r 0 even/odd toggle (write 1 clear) 0: progressive 1: interlace se 5 r 0 even/odd signal error (write 1 clear) 0: normal 1: error rs 4 r/w 0 the reference signal for executing info-frame autom atically. 0: den 1: vsync dsc 3:0 r/w 0 down sample control (only valid if video down sampl ing auto mode disable) 0000: pixel down sample for 1 time( no down sample ) 0001: pixel down sample for 2 times 0010: pixel down sample for 3 times 0011: pixel down sample for 4 times 0100: pixel down sample for 5 times 0101: pixel down sample for 6 times 0110: pixel down sample for 7 times 0111: pixel down sample for 8 times 1000: pixel down sample for 9 times 1001: pixel down sample for 10 times others : xxx register:: hdmi_acrcr 0x51 name bits r/w reset state comments hdirq 7 r/w 0 hdmi/dvi change interrupt enable 0:disable 1:enable csam 6 r/w 1 color space translation 0: manual 1: auto csc 5:4 r/w 0 color space control (if csam=1, csc will be read-on ly) 00: rgb 01: ycrcb-422 10: ycrcb-444 11: reserved reserved 3 -- 0 reserved to 0 prdsam 2 r/w 1 pixel repetition down sampling auto mode 1: auto, the circuit resolve the repeat number, and enable it in next frame. the result could be read in bits for repeat number. 0: manual, f/w sets repeat number, the number is se t in bits for repeat number. pucnr 1 r/w 0 pop up cts&n result 0: no pop up 1: pop up result (pop up cts&n which is acquired co mpletely. if present n&cts is acquiring, pop up previous complete n&cts) if the info is updating, hw will refuse this comman d. pucsr 0 r/w 0 pop up channel status result 0: no pop up 1: pop up result ( pop up channel status which is a cquired completely. if present channel status is acquiring, pop up previou s complete channel status) register:: hdmi_acrsr0 0x52 name bits r/w reset state comments cts 7:0 r 0 cts in usage, cts[19:12]
register:: hdmi_acrsr1 0x53 name bits r/w reset state comments cts 7:0 r 0 cts in usage, cts[11:4] register:: hdmi_acrsr2 0x54 name bits r/w reset state comments cts 7:4 r 0 cts in usage, cts[3:0] n 3:0 r 0 n in usage, n[19:16] register:: hdmi_acrsr3 0x55 name bits r/w reset state comments n 7:0 r 0 n in usage, n[15:8] register:: hdmi_acrsr4 0x56 name bits r/w reset state comments n 7:0 r 0 n in usage, n[7:0] register:: hdmi_acs0 0x57 name bits r/w reset state comments cs 7:0 r 0 channel status bit7~ bit0 register:: hdmi_acs1 0x58 name bits r/w reset state comments cs 7:0 r 0 channel status bit 15~ bit 8 register:: hdmi_acs2 0x59 name bits r/w reset state comments cs 7:0 r 0 channel status bit23~ bit 16 register:: hdmi_acs3 0x5a name bits r/w reset state comments cs 7:0 r 0 channel status bit 31~ bit 24 register:: hdmi_acs4 0x5b name bits r/w reset state comments cs 7:0 r 0 channel status bit 39~ bit 32 register:: hdmi_intcr 0x60 name bits r/w reset state comments pending 7 r 0 when irq occurred, this bit would be assigned to 1 by hw, and irq would be pended until fw clear this bit.(write 1 cl ear) avmute 6 r/w 0 if get general control packet and the corresponding set_avmute flag & clear_avmute flag is different with previous values 0: irq don?t occur. 1: irq occur.
fifod 5 r/w 0 if fifo depth reach target (used for manual audio flow) 0: irq don?t occur 1: irq occur act 4 r/w 0 audio coding type 0: if audio coding type is different with previous value, irq doesn?t occur. 1: if audio coding type is different with previous value, irq occurs. apll 3 r/w 0 audio pll 0: if audio pll is non-lock, irq doesn?t occur 1: if audio pll is non-lock, irq occurs afifoo 2 r/w 0 audio fifo overflow 0: if audio fifo is overflow for x samples , irq do esn?t occur. 1: if audio fifo is overflow for x samples , irq oc curs. afifou 1 r/w 0 audio fifo underflow 0: if audio fifo is underflow for y samples , irq d oesn?t occur. 1: if audio fifo is underflow for y samples , irq o ccurs. vc 0 r/w 0 1: if video clock is higher than 165mhz or lower than 25mhz (refer to nl), irq doesn?t occur. 0: if video clock is higher than 165mhz or lower th an 25mhz (refer to nl), irq occurs. register:: hdmi_alcr 0x61 name bits r/w reset state comments lo1 7:6 r/w 0 speaker location of i2s #1 & spdif out#1 00: from subpacket0 of audio sample packet 01: from subpacket1 of audio sample packet 10: from subpacket2 of audio sample packet 11: from subpacket3 of audio sample packet lo2 5:4 r/w 1 speaker location of i2s #2 & spdif out #2 lo3 3:2 r/w 2 speaker location of i2s #3 & spdif out #3 lo4 1:0 r/w 3 speaker location of i2s #4 & spdif out #4 register:: hdmi_aocr 0x62 name bits r/w reset state comments spdifo1 7 r/w 0 spdif 1 output switch 0: cutoff 1: normal spdifo2 6 r/w 0 spdif 2 output switch spdifo3 5 r/w 0 spdif 3 output switch spdifo4 4 r/w 0 spdif 4 output switch i2so1 3 r/w 0 i2s 1 output switch 0: cutoff 1: normal i2so2 2 r/w 0 i2s 2 output switch i2so3 1 r/w 0 i2s 3 output switch i2so4 0 r/w 0 i2s 4 output switch register:: hdmi_bcsr 0x70 name bits r/w reset state comments reserved 7:6 --- 0 reserved to 0 nvlgb 5 r 0 video no leading guard band if no leading gb after video preamble (it is only t riggered in hdmi mode), this bit would be assigned to 1 until clear this bit write 1 to clear. nalgb 4 r 0 audio no leading guard band if no leading gb after audio preamble (it is only t riggered in hdmi
mode), this bit would be assigned to 1 until clear this bit write 1 to clear. natgb 3 r 0 audio no trailing guard band if audio packets without trailing gb, this bit woul d be assigned to 1 until clear this bit. write 1 to clear. ngb 2 r 0 no guard band if any type of gb is not synchronous in 3 channels( audio is only 2 channel ), this bit would be assigned to 1 until cl ear this bit. write 1 to clear. pe 1 r 0 packet error if size of data island packet is not times of 32, t his bit would be assigned to 1 until clear this bit. write 1 to clear. gcp 0 r 0 general control packet error flag : if hw receive general control packet with clear_avm ute=1 & set_avmute=1 ,assign this bit to 1 until clear this bit write 1 to clear. register:: hdmi_asr0 0x71 name bits r/w reset state comments reserved 7:3 --- 0 reserved to 0 fsre 2 r 0 fs regeneration error if cts & n received 0, this bit would be assigned t o 1 until clear this bit write 1 to clear. fsif 1 r 0 fs from infoframe if audio frequency from infoframe ready, this bit w ould be assigned to 1 until clear this bit write 1 to clear. fscs 0 r 0 fs from channel status if audio frequency from channel status ready, this bit would be assigned to 1 until clear this bit write 1 to clear. register:: hdmi_asr1 0x72 name bits r/w reset state comments reserved 7 --- 0 reserved fbif 6:4 r 0 frequency bits from info frame 000: refer to channel status bits 001: 32k 010: 44.1k 011: 48k 100: 88.2k 101: 96k 110: 176.4k 111: 192k fbcs 3:0 r 0 frequency bits from channel status . (pop up with channel status simultaneously) 0010: 22.05k 0000: 44.1k 1001: 88.2k 0011: 176.4k 0110: 24k 0100: 48k 0101: 96k 0111: 192k 1100: 32k
1000: sampling frequency not inidicated register:: tmds_dpc_set0 0x80 name bits r/w reset state comments dpc_en 7 r/w 0 phase_errcnt_i n 6:4 r/w 0 max. times of phase error to rise error flag 3 ?b000 count 8 times 3 ?b001~3?b111 count 1~7 times phase_clrcnt_i n 3:1 r/w 0 max. times of sync. signal to clear the phase error counter according to ?phase_clr_sel? 3 ?b000 count 8 times 3 ?b001~3?b111 count 1~7 times phase_clr_sel 0 r/w 0 unit of ?phase_clrcnt_in? 0: use v sync 1: use h sync register:: tmds_dpc_set1 0x81 name bits r/w reset state comments set_full_noti 7:4 r/w 0 set full notifier level ( recommend: 3?d7) 3 ?b000~3?b111 set 0~7 set_empty_noti 3:0 r/w 0 set empty notifier level ( recommend: 3?d3) 3 ?b000~3?b111 set 0~7 register:: tmds_dpc_set2 0x82 name bits r/w reset state comments fifo_errcnt_in 7:5 r/w 0 max. times of fifo error to rise error flag 3?b000 count 8 times 3?b001~3?b111 count 1~7 times clr_phase_flag 4 r/w 0 clear phase error flag clr_fifo_flag 3 r/w 0 clear fifo error flag dpc_phase_ok 2 r 0 phase locking ok
dpc_phase_err _flag 1 r 0 become 1 when phase error than ?phase_errcnt_in? nu mber dpc_fifo_err_fl ag 0 r 0 become 1 when fifo error than ?fifo_errcnt_in? numb er register:: tmds_dpc_set3 0x83 name bits r/w reset state comments dpc_fifo_over_ flag 7 r 0 become 1 when internal fifo receive writing signal while it is full. dpc_fifo_under _flag 6 r 0 become 1 when internal fifo receive reading signal while it is empty. dpc_fifo_over_ xflag 5 r 0 become 1 when internal fifo receive writing signal while it is full. if (fifo_under_xflag=1), this flag is not active. dpc_fifo_under _xflag 4 r 0 become 1 when internal fifo receive reading signal while it is empty. if (fifo_over_xflag=1), this flag is not active. reserved 3:0 -- 0 reserved
liveshow tm control (page 3) register::ls_ctrl0 0xa1 name bits read/write reset state comments ls_bypass 7 r/w 0 display pixel resolution 0: bypass liveshow tm processing 1: enable liveshow tm procesing ls_buf_en 6 r/w 0 enable sdram buffer access 0: disable 1: enable ls_pd_est 5 r/w 0 level estimation 0: disable 1: enable ls_cprs_en 4 r/w 0 huffman data compression 0: disable 1: enable ls_gain_en 3 r/w 0 delta gain adjustment 0: disable (delta gain=1) 1: enable ls_disp_res 2 r/w 0 display pixel resolution 0: 8-bit 1: 6-bit source_res 1:0 r/w 0 source pixel resolution 00: 6bit 01: 5bit 1x: 4bit (pixel resolution after rounding in previous path. pixel resolution for compression.) register::ls_ctrl1 0xa2 name bits read/write reset state comments ls_in_win 7 r/w 0 liveshow tm inside highlight window 0: disable 1: enable ls_out_win 6 r/w 0 liveshow tm outside highlight window 0: disable
1: enable ls_ofst_en 5 r/w 0 offset compensation 0: disable 1: enable ls_nr_en 4 r/w 0 low-bit noise reduction 0: disable 1: enable ls_nr_md 3 r/w 0 low-bit noise reduction mode 0: rgb independent mode (old mode: rtd2363-like) 1: rgb related mode (new mode) ls_nr_thd 2:0 r/w 0 low-bit noise reduction thresho ld 000`b: 4 001`b: 6 010`b: 8 011`b: 10 100`b: 12 101`b: 14 110`b: 16 111`b: 18 register::ls_cprs_ctrl 0xa4 name bits read/write reset state description im_cprs_type 7 r/w 0 compression type 0: channel g, r reference to b 1: 3 independent channels ls_mem_res 6:5 r/w 0 sdram pixel resolution 00: 4-bit 01: 5-bit 1x: 6-bit (effective only when ls_cprs_en=1, sdram pixel resolution must always equal or less than source pixel resolution (source_res)) rgb_yc_sel 4 r/w 0 new od algorithm 0: rgb rounding/compression 1: yc rounding de_buf_empty_ dly 3 r/w 1 decode buf empty flag delay option 0: no delay for decode pre buf empty flag
1: delay until buf_wr_adr reach 15 to let empty flag be normal ls_rsv_a4_20 2 :0 r/w 0 reserved register::tg_size_h 0xa5 name bits read/write reset state description ls_rsv_a5_71 7:1 r/w 0 reserved tg_size_h 0 r/w 0 target size for compression (unit: 64 bit) threshold = {(num_break*6)+ (num_n*length_n)}/64+7 note: 1. header(2x64)+dummy rounding effect(3x64)+reserved block(2x64) =7x64-bit 2. num_n = number matched for code n criteria. 3. length_n = length of code n, calculated by huffman tree generation. 4. num_break = number of pixel matched the break criteria. 5. max. target-size = 256 (unit: 64-bit) threshold must be set in even number register::tg_size_l 0xa6 name bits read/write reset state description tg_size_l 7:0 r/w 0x00 target size for compression (unit: 64 bit) threshold = {(num_break*6)+ (num_n*length_n)}/64+7 note: 1. header(2x64)+dummy rounding effect(3x64)+reserved block(2x64) =7x64-bit 2. num_n = number matched for code n criteria. 3. length_n = length of code n, calculated by huffman tree generation. 4. num_break = number of pixel matched the break criteria. 5. max. target-size = 256 (unit: 64-bit) threshold must be set in even number register::grp_num_h 0xa7 name bits read/write reset state description ls_rsv_a7_72 7:3 r/w 0 reserved grp_num_h 2:0 r/w 0 number of pixel per group to be analyzed and compressed. (max. group number = 1280)
register::grp_num_l 0xa8 name bits read/write reset state description grp_num_l 7:0 r/w 0 number of pixel per group to be analyzed and compressed. (max. group number = 1280) register::fail_cnt_h 0xa9 name bits read/write reset state description ls_rsv_a9_74 7:4 r/w 0 reserved fail_cnt_h 3:0 r 0 the count of compression fail register::fail_cnt_l 0xaa name bits read/write reset state description fail_cnt_l 7:0 r 0 the count of compression fail (updated when dvs occurred) compression format: {1}, {symbol0 3-bit code length, 7bit code}, ?, {sy mbol7 3-bit code length, 7bit code}, {b0 code}, {g0 code}, {r0 code}, {b1 code}, {g1 code}, {r1 code}?. non-compression format: {0}, {b0 4-bit msb}, {g0 4-bit msb}, {r0 4-bit msb} , {b1 4-bit msb}, {g1 4-bit msb}, {r1 4-bit msb}?. register::ls_lut_row_addr 0xae name bits read/write reset state description ls_lut_acs_en 7 r/w 0 lut access enable 0: disabled 1: enabled ls_rsv_ae_66 6 r/w 0 reserved ls_lut_row 5:0 r/w 0 lut row selector(current frame as index) register::ls_lut_col_addr 0xaf name bits read/write reset state description ls_lut_sel 7:6 r/w 0 lut channel selector 00: red channel 01: green channel 10: blue channel
11: all channels ls_lut_col 5:0 r/w 0 lut column selector (previous frame as index) register::ls_lut_data 0xb0 name bits read/write reset state description ls_lut_data 7:0 r/w 0 lut data port register::delta_gain 0xb1 name bits read/write reset state description ls_rsv_b1_77 7 r/w 0 reserved delta_gain 6:0 r/w 0 delta gain setting 0x00 -> gain = 0 0x40 -> gain = 1 0x7f -> gain =127/64 (effective only when ls_gain_en=1) register::udst_thd 0xb2 name bits read/write reset state description ls_rsv_b2_77 7 r/w 0 reserved udst_thd 6:0 r/w 0 undershoot threshold (2?s comple ment) 0x00 -> thd = 0 0x7f -> thd = -127 (effective only when ls_ofst_en =1) register::ovst_thd 0xb3 name bits read/write reset state description ls_rsv_b3_77 7 r/w 0 reserved ovst_thd 6:0 r/w 0 overshoot threshold 0x00 -> thd = 0 0x7f -> thd = 127 (effective only when ls_ofst_en =1) register::udst_gain 0xb4 name bits read/write reset state description ls_rsv_b4_76 7:6 r/w 0 reserved udst_gain 5:0 r/w 0 undershoot gain 0x00 -> gain = 0/128
0x3f -> gain = 63/128 (effective only when ls_ofst_en =1) register::ovst_gain 0xb5 name bits read/write reset state description ls_rsv_b5_76 7:6 r/w 0 reserved ovst_gain 5:0 r/w 0 overshoot gain 0x00 -> gain = 0/128 0x3f -> gain = 63/128 (effective only when ls_ofst_en =1) register::ls_status0 0xb6 name bits read/write reset state comments ls_rbuf_full 7 r 0 set if buf_r is full (on-line mo nitor) ls_rbuf_epty 6 r 0 set if buf_r is empty (on-line m onitor) ls_rbuf_udfw 5 r 0 set if buf_r is underflow ls_wbuf_full 4 r 0 set if buf_w is full (on-line mo nitor) ls_wbuf_epty 3 r 0 set if buf_w is empty (on-line m onitor) ls_wbuf_ovfw 2 r 0 set if buf_w is overflow reserved 1 -- 0 reserved ls_status0_rst 0 r/w 0 write 1 to reset buf and fif o status (auto clear after done) register::ls_status1 0xb7 name bits read/write reset state comments ls_rfifo_full 7 r 0 set if fifo_r is full (on-line monitor) ls_rfifo_epty 6 r 0 set if fifo_r is empty (on-line monitor) ls_rfifo_ovfw 5 r 0 set if fifo_r is overflow befor e ls_rfifo_udfw is set ls_rfifo_udfw 4 r 0 set if fifo_r is underflow befo re ls_rfifo_ovfw is set ls_wfifo_full 3 r 0 set if fifo_w is full (on-line monitor) ls_wfifo_epty 2 r 0 set if fifo_w is empty (on-line monitor) ls_wfifo_ovfw 1 r 0 set if fifo_w is overflow befor e ls_wfifo_udfw is set
ls_wfifo_udfw 0 r 0 set if fifo_w is underflow befo re ls_wfifo_ovfw is set register::ls_wtlvl_w 0xc0 name bits read/write reset state comments reserved 7 -- 0 reserved ls_wtlvl_w 6:0 r/w 0x40 when fifo depth is over wtl vl, fifo write data ((num*len)+rem) * 64 = one frame/line data the assigned value multiplied by 2 is the real value. register::ls_wtlvl_r 0xc1 name bits read/write reset state comments reserved 7 -- 0 reserved ls_wtlvl_r 6:0 r/w 0x40 when fifo depth is over wtl vl, fifo write data ((num*len)+rem) * 64 = one frame/line data the assigned value multiplied by 2 is the real value. register::ls_mem_fifo_rw_num_h 0xc2 name bits read/write reset state comments ls_mfrw_no_h 7:0 r/w 0x01 ls_men_fifo_rw_num [15:8] the read/write times of total memory access. register::ls_mem_fifo_rw_num_l 0xc3 name bits read/write reset state comments ls_mfrw_no_l 7:0 r/w 0x00 ls_mem_fifo_rw_num [7:0] the read/write times of total memory access. register::ls_mem_fifo_rw_len 0xc4
name bits read/write reset state comments ls_mfrw_len 7:0 r/w 0x80 ls_mem_fifo_rw_len [7:0] the read/write number of words in each memory access. register::ls_mem_fifo_rw_remain 0xc5 name bits read/write reset state comments ls_mfrw_rm 7:0 r/w 0x80 ls_mem_fifo_rw_ remain [7:0 ] the read/write number of words at the last access. this register must be 4x. register::ls_mem_start_addr_h 0xc6 name bits read/write reset state comments ls_rsv_c6_77 7 r/w 0 reserved ls_mem_adr_h 6:0 r/w 0x00 ls_mem_start_addr [22:16] start address of ls memory block (total 22/23 bits) . if the columns per bank are 256, and bank = 4 , sdr am address [22:0] is: 1?b0+r[11:0]+b[1:0]+c[7:0] if the columns per bank are 256, and bank = 2 , sdr am address [22:0] is: 2?b0+r[11:0]+b[0]+c[7:0] if the columns per bank are 512, and bank = 4 , sdr am address [22:0] is: r[11:0]+b[1:0]+c[8:0] if the columns per bank are 512, and bank = 2 , sdr am address [22:0] is: 1?b0+r[11:0]+b[0]+c[8:0] register::ls_mem_start_addr_m 0xc7 name bits read/write reset state comments ls_mem_adr_m 7:0 r/w 0x00 ls_mem_start_addr [15:8] start address of ls memory block (total 22/23 bits) register::ls_mem_start_addr_l 0xc8 name bits read/write reset state comments ls_mem_adr_l 7:0 r/w 0x00 ls_mem_start_addr [7:0] start address of ls memory block (total 22/23
bits) register::ls_bist_ctrl 0xc9 name bits read/write reset state comments ls_test 7:6 r/w 0 reserved for testing ls_rsv_c9_5 5 r/w 0 reserved freeze_mode 4 r/w 0 freeze mode enable ls_test_en 3 r/w 0 liveshow tm test enable. 0: disable 1: enable ls_test_mode 2 r/w 0 liveshow tm test mode. 0: bypass interpolated delta 1: bypass lut4 value ls_bist_start 1 r/w 0 liveshow tm memory bist start. set 1 to start and auto-clear after finished. ls_bist_result 0 r 0 liveshow tm memory bist result. 0: failed 1: pass register::ls_comp_chk 0xca name bits read/write reset state comments config ls_rsv_c9_77 7 r/w 0 reserved prebuf_udfw 6 r 0 decompression previous buffer under flow prebuf_sta_clr 5 r 0 decompression previous buffer status clear wclr_out rebuf_ovfw_vd um 4 r 0 reorder buffer overflow by vsync dummy purge, the previous frame result rebuf_ovfw_gd um_msb 3:0 r 0 reorder buffer overflow by group dummy purge, the previous frame result, update by vsync, msb
register::ls_frame0 0xcc name bits read/write reset state comments config cur_bypass_en 7 r/w 0 in current frame path, bypass the conversion path and go through od_lut directly: 0: disable 1: enable ls_rsv_cc_65 6:5 r/w 0 reserved cur_rgb2yuv_en 4 r/w 0 in current frame path, rgb to yuv: 0: disable 1: enable cur_444to422_en 3 r/w 0 in current frame path, yuv 444 to 422: 0: disable 1: enable ls_rsv_cc_21 2:1 r/w 0 reserved uv_mode 0 r/w 0 in current/previous frame path, 444to422 u/v type 0: u0 v0 u2 v2 u4 v4 ? 1: u0 v1 u2 v3 u4 v5 ? register::ls_frame1 0xcd name bits read/write reset state comments config cur_422to444_en 7 r/w 0 in current frame path, yuv 422 to 444: 0: disable 1: enable cur_duplicate 6 r/w 0 in current frame path, yuv 422 to 444: 0: interpolation mode 1: duplication mode interpolation mode: original sequence: y0u0, y1v0, y2u2, y3v2, y4u4, y5v4,.... final sequences: y0u0v0, y1((u0+u2)/2)((v0+v2)/2), y2u2v2, y3((u2+u4)/2)((v2+v4)/2), y4u4v4, ... duplication mode: original sequence: y0u0, y1v0, y2u2, y3v2, y4u4, y5v4,.... register::ls_comp_reovfw 0xcb name bits read/write reset state comments config rebuf_ovfw_gd um_lsb 7:0 r 0 reorder buffer overflow by group dummy purge, the previous frame result, update by vsync, lsb
final sequences: y0u0v0, y1u0v0, y2u2v2, y3u2v2, y4u4v4, y5u5v5,... ls_rsv_cd_5 5 r/w 0 reserved cur_yuv2rgb_en 4 r/w 0 in current frame path, yuv to rgb: 0: disable 1: enable pre_422to444_en 3 r/w 0 in previous frame path, yuv 422 to 444: 0: disable 1: enable pre_duplicate 2 r/w 0 in previous frame path, yuv 422 to 444: 0: interpolation mode 1: duplication mode ls_rsv_cd_1 1 r/w 0 reserved pre_yuv2rgb_en 0 r/w 0 in previous frame path, yuv to rgb: 0: disable 1: enable register::ls_frame2 0xce name bits read/write reset state comments config cur_round 7:6 r/w 0 the current pixel after rgb->yuv, 444->422 rounding mode setting 00: no rounding (keep original 10bit) 01: 6bit rounding 10: 4bit rounding 11: 5bit rounding est_value 5:0 r/w 0 user defined level estimation value: 0~63 (when level estimation enabled, i.e. cra1[5]==1, and working under yc rounding mode, cra4[4] = 1?b1)
sdram control (page 4) register::sdr_ctrl0 0xa1 name bits read/ write reset state comments config sdr_rsv_a1_76 7:6 r/w 0 reserved sdr_wr_delay 5:3 r/w ? b011 delay from row active to write 000: reserved 001: reserved 010: 2 mclk 011: 3 mclk 100: 4 mclk 101: 5 mclk 110: reserved 111: reserved sdr_rd_delay 2:0 r/w ?b011 delay from row active to data valid 000: reserved 001: reserved 010: 2 mclk 011: 3 mclk 100: 4 mclk 101: 5 mclk 110: reserved 111: reserved register::sdr_ctrl1 0xa2 name bits read/ write reset state comments config sdr_cl 7:5 r/w ?b011 cas latency of sdram 000: reserved 001: reserved 010: 2 mclk 011: 3 mclk 100: reserved 101: reserved 110: reserved 111: reserved
if mclk >100mhz, sdr_cl should be 3 mclk. sdr_rsv_a2_40 4:0 r/w 4 reserved register::sdr_aref_time 0xa3 name bits read/ write reset state comments config sdr_aref_time 7:0 r/w 0x0d auto refresh time. (the period of initial refresh time in mclk cycle) register::sdr_prcg 0xa4 name bits read/ write reset state comments config sdr_prcg_bit 7 r/w 0 precharge all banks by 0: a8 1: a10 sdr_prcg_do 6 r/w 0 force to precharge all banks sdr_col_num 5 r/w 0 columns per bank 0: 256 1: 512 sdr_reset 4 r/w 0 sdr reset 0: normal 1: reset sdr_prcg_dly 3:0 r/w 3 precharge delay cycle (the i nterval from precharge to next valid command) register::sdr_mem_type 0xa5 name bits read/ write reset state comments config sdr_mem_size 7:6 r/w 0 sdram memory size 00: 1mx16x1pcs 01: 1mx16x2pcs 10: 2mx32x1pcs 11: 2mx32x2pcs sdr_bank_sel 5 r/w 0 banks per sdram 0: 4 bank
1: 2 bank sdr_abr_status 4 r 0 arbiter recovery happen sdr_abr_rec_en 3 r/w 0 arbiter recovery enable, reset state machin e sdr_cas_latn 2:0 r/w 1 cas latency for controller 000: reserved 001: 1 010: 1 011: 2 100: 2 101: 3 110: 3 111: 4 register::sdr_slew_rate 0xa6 name bits read/ write reset state comments config sdr_rsv_a6_73 7:3 r/w 0 reserved sdr_auto_gati ng 2 r/w 0 auto gating cke 0: disable 1: enable sdr_cke_l 1 r/w 0 force cke low (for power-down mod e) 0: disable 1: enable sdr_cke_h 0 r/w 0 force cke high (for testing) 0: disable 1: enable register::sdr_aref_cnt 0xa7 name bits read/ write reset state comments config sdr_aref_cnt8 7:0 r/w 0x81 number of auto refresh ( n*8 ) register::reserved 0xa8 name bits read/ write reset state comments config reserved 7:0 r/w 0 reserved
register::reserved 0xa9 name bits read/ write reset state comments config reserved 7:0 r/w 0 reserved register::sdr_rsc_aref 0xaa name bits read/ write reset state comments config sdr_rsc_aref 7:0 r 0xff token ring bit[7:0] register::sdr_rsc_mcu 0xab name bits read/ write reset state comments config sdr_rsc_mcu 7:0 r/w/d 0x20 token ring bit[7:0] register::sdr_rsc_cap1 0xac name bits read/ write reset state comments config sdr_rsc_cap1 7:0 r/w/d 0xaa token ring bit[7:0] register::reserved 0xad name bits read/ write reset state comments config reserved 7:0 r/w 0 reserved register::sdr_rsc_main 0xae name bits read/ write reset state comments config sdr_rsc_main 7:0 r/w/d 0x55 token ring bit[7:0] register::reserved 0xaf name bits read/ reset comments config
write state reserved 7:0 r/w 0 reserved register::sdr_rsc_rtc_rd 0xb0 name bits read/ write reset state comments config sdr_rsc_rtc_rd 7:0 r/w/d 0xaa token ring bit[7:0] register::sdr_rsc_rtc_wr 0xb1 name bits read/ write reset state comments config sdr_rsc_rtc_wr 7:0 r/w/d 0x55 token ring bit[7:0] (double-buffer) token-ring access before aref register::reserved 0xb2 name bits read/ write reset state comments config reserved 7:0 r/w 0 reserved register::reserved 0xb3 name bits read/ write reset state comments config reserved 7:0 r/w 0 reserved register::sdr_abtr_status0 0xb4 name bits read/ write reset state comments config sdr_abtr_rtcr 7 r 0 rtc read arbiter status sdr_abtr_rtcw 6 r 0 rtc write arbiter status sdr_abtr_main 5 r 0 main read arbiter status reserved 4 -- 0 reserved sdr_abtr_cap1 3 r 0 cap1 write arbiter status reserved 2 -- 0 reserved sdr_abtr_mcu 1 r 0 mcu r/w arbiter status
sdr_abtr_aref 0 r 0 aref arbiter status write-clear register::sdr_abtr_status 1 0xb5 name bits read/ write reset state comments config reserved 7:1 -- 0 reserved sdr_reset_rdy 0 r 0 sdr reset ready register::reserved 0xb6 name bits read/ write reset state comments config reserved 7:0 r/w 0 reserved register::reserved 0xb7 name bits read/ write reset state comments config reserved 7:0 r/w 0 reserved register::sdr_addr_h 0xb8 name bits read/ write reset state comments config reserved 7 -- 0 reserved sdr_addr_h 6:0 r/w 0 sdr_addr [22:16] if the columns per bank are 256,bit[5:0] is assigne d to r[11:6] and bit[6] is reserved. if the columns per bank are 512,bit[6:0] is assigne d to r[11:5] if the columns per bank are 256, sdram address [22: 0] is: r[11:0]+b[1:0]+c[7:0] if the columns per bank are 512, sdram address [22: 0] is: r[11:0]+b[1:0]+c[8:0] register::sdr_addr_m 0xb9 name bits read/ write reset state comments config sdr_addr_m 7:0 r/w 0 sdr_addr [15:8] if the columns per bank are 256, bit[7:2] is assigned to r[5:0] bit[1:0] is assigned to b[1:0] if the columns per bank are 512,bit bit[7:3] is assigned to r[4:0] bit[2:1] is assigned to b[1:0] bit[0] is assigned to c[8]
register::sdr_addr_l 0xba name bits read/ write reset state comments config sdr_addr_l 7:0 r/w 0 sdr_addr [7:0] bitp7:0] is assigned to c[7:0] regardless of column s per bank are 256 or 512. register::sdr_access_cmd 0xbb name bits read/ write reset state comments config sdr_acs_cmd 7:5 r/w 0 sdr_access_command (clear to 000 after finish) 000: nop or finish 001: pre-charge (all bank or single bank) 010: auto-refresh (step by step or auto arbiter) 011: load mode register (step by step or auto initi alization) (load mode register will reset dll of dram, we must idle ~200cycles before next "read") 100: write command (buf sdr) 101: read command(sdr buf) 110: reserved 111: reserved sdr_dbuf_idx 4:0 r/w 0 data_buffer_index specifies the next access byte in the buffer. register::sdr_data_buf 0xbc name bits read/ write reset state comments config sdr_data_buf 7:0 r/w 0 sdr_data_buffer sequential 8-word (32 byte) read/write from low to high address auto-increase. data_buffer_index specifies the next access byte in the buffer. sdr_access (read/write) can be used for mcu acces how to modify only one-byte in sdr? read 32 bytes, only modify one index-select byte, write 32 bytes. register::sdr_mcu_rd_len 0xbd name bits read/ write reset state comments config mcurd_tst_en 7 r/w 0 on-line test mcurd sdram enabl e mcurd_len 6:0 r/w 0 mcu read sram length register::phase calibration 0xbe name bits read/ write reset state comments config
reserve 7:5 r/w 0 ph_cal_up_sel 4 r/w 0 phase calibration wait event select 0 : sdram write (not include mcu write to sdram) 1: display vertical front porch phcal_wait_en 3 r/w 0 calibration wait event (ref. cr_be[4]) phcal_en 2 r/w 0 phase calibration enable 0: finish 1: enable (auto-clear by hw) rd_ph_db_en 1 r/w 0 double buffer enable(update sra m datat dqs fine dly) rd_ph_db_start 0 r/w 0 start double buffer (ref. cr _be[4]) 0: finish 1: start (auto clear by hw) register::calibration_result 0xbf name bits read/ write reset state comments config reserve 7 r 0 phcal_cnt 6:0 r 0 register::sdr_clk_dly1 0xc0 name bits read/ write reset state comments config mclko_inv 7 r/w/d 0 mclk ouput invert 0 : non invert 1: inert reserve 6:0 r/w 0 register::sdr_clk_dly2 0xc1 name bits read/ write reset state comments config mclk_fine_tune 7:0 r/w/d 0 mclk delay fine tune[7:0]
register::dqs0_dly1 0xc2 name bits read/ write reset state comments config sdr_d0_lft_off 7 r 0 sdram data [15:0] latch fine-t une status 0: actived 1: inactived dqs0_coarse_dly 6:5 r/w/d 0 sdram data [15:0]coarse dly [1:0] 00: 0 01: 90 10: 180 11: 270 reserve 4:0 r/w 0 register::dqs0_dly2 0xc3 name bits read/ write reset state comments config dqs0_fine_dly 7:0 r/w/d 0 sdram data[15:0] fine dly [7:0] register::dqs1_dly1 0xc4 name bits read/ write reset state comments config sdr_d1_lft_off 7 r 0 sdram data [31:16] latch fine- tune status 0: actived 1: inactived dqs1_coarse_dly 6:5 r/w/d 0 sdram data[31:16] coarse dly [1:0] 00: 0 01: 90 10: 180 11: 270 reserve 4:0 r/w 0 register::dqs1_dly2 0xc5 name bits read/ write reset state comments config
dqs1_fine_dly 7:0 r/w/d 0 sdram data[31:16] fine dly [7:0] register::dqs2_dly1 0xc6 name bits read/ write reset state comments config sdr_d2_lft_off 7 r 0 sdram data [47:32] latch fine- tune status 0: actived 1: inactived dqs2_coarse_dly 6:5 r/w/d 0 sdram data[47:32] coarse dly [1:0] 00: 0 01: 90 10: 180 11: 270 reserve 4:0 r/w 0 note: reserve for 64 bits sdram register::dqs2_dly2 0xc7 name bits read/ write reset state comments config dqs2_fine_dly 7:0 r/w/d 0 sdram data[47:32] fine dly [7:0] note: reserve for 64 bits sdram register::dqs3_dly1 0xc8 name bits read/ write reset state comments config sdr_d3_lft_off 7 r 0 sdram data [63:48] latch fine- tune status 0: actived 1: inactived dqs3_coarse_dly 6:5 r/w/d 0 sdram data coarse dly [1:0] 00: 0 01: 90 10: 180 11: 270 reserve 4:0 r/w 0 note: reserve for 64 bits sdram
register::dqs3_dly2 0xc9 name bits read/ write reset state comments config dqs3_fine_dly 7:0 r/w/d 0 sdram data[63:48] fine dly [7:0] note: reserve for 64 bits sdram register::sec_dqs0_dly 0xca name bits read/ write reset state comments config sec_dqs0_fine_dly 7:0 r/w 0 sdram data[15:0] fine d ly [7:0] phase switch setting for on-line mcurd to check phase register::sec_dqs1_dly 0xcb name bits read/ write reset state comments config sec_dqs1_fine_dly 7:0 r/w 0 sdram data[31:16] fine dly [7:0] phase switch setting for on-line mcurd to check phase register::sec_dqs2_dly 0xcc name bits read/ write reset state comments config sec_dqs2_fine_dly 7:0 r/w 0 sdram data[47:32] fine dly [7:0] phase switch setting for on-line mcurd to check phase note: reserve for 64 bits sdram register::sec_dqs3_dly 0xcd name bits read/ write reset state comments config sec_dqs3_fine_dly 7:0 r/w 0 sdram data[63:48] fine dly [7:0] phase switch setting for on-line mcurd to check phase note: reserve for 64 bits sdram address: ce~fb reserved
register::extended_mode_register 0xfc name bits read/ write reset state comments config mcurd_crc_en 7 r/w 0 crc enable for mcu read from s dram only reserve 6:5 r/w 0 emr_config[11:8] 3:0 r/w 0 extended_mode_register[1 1:8] register::extended_mode_register 0xfd name bits read/ write reset state comments config emr_config[7:0] 7:0 r/w 0 extended_mode_register[7: 0] register::random_generator 0xfe name bits read/ write reset state comments config rst_random_sel 7 r/w 0 sdram controller random gene rator reset 0: dvs 1: ivs rst_crc_sel 6 r/w 0 sdram controller crc reset 0: dvs 1: ivs random_en 5 r/w 0 sdram controller random generator enable crc_start 4 r/w 0 sdram controller crc start 0: finish 1: start (auto-clear by hw) crc_adr_port 3:0 r/w 0 address port for crff register::crc_data_port 0xff name bits read/ write reset state comments config crc_data_port 7:0 r 0 crc data port

reserved (page 5) reserved (page 6) vivid color-video color space conversion(page 7) register:: yuv2rgb_ctrl 0xbf name bits read/ write reset state comments config dummy 7:2 r/w 0 reserved access 1 r/w 0 enable yuv/rgb coefficient access 0: disable 1: enable enable 0 r/w 0 enable yuv to rgb conversion 0: disable yuv-to-rgb conversion 1: enable yuv-to-rgb conversion register:: yuv2rgb_access 0xc0 name bits read/ write reset state comments config write_enabled 7:3 r/w 0 yuv coefficient write enable: 00000: k11 high byte 00001: k11 low byte 00010: k13 high byte 00011: k13 low byte 00100: k22 high byte 00101: k22 low byte 00110: k23 high byte 00111: k23 low byte 01000: k32 high byte 01001: k32 low byte 01010: roffset high byte 01011: roffset low byte 01100: goffset high byte 01101: goffset low byte 01110: boffset high byte 01111: boffset low byte 10000: rgain high byte 10001: rgain low byte 10010: ggain high byte 10011: ggain low byte 10100: bgain high byte 10101: bgain low byte 10110~11111: reserved cb_cr_clamp 2 r/w 0 cb cr clamp 0: bypass 1: cb-( 128 ), cr-( 128 ) y_clamp 1 r/w 0 y clamp 0: bypass 1: y-( 16 ) y signed 0 r/w 0 y signed selection 0: (y-16)-> unsigned 1: (y-16)-> signed register:: yuv_rgb_coef_data 0xc1 name bits read/ write reset state comments config coef 7:0 w - coef_data[7:0]
yuv/rgb matrix ? ? ?? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? ?? ? ? ? = ? ? ?? ? ? ? ?? ? ) 128 ( ) 128 ( ) 16 ( 0 0 32 11 23 22 11 13 11 v or v u or u y or y k k k k k k k b g r + ? ? ?? ? ? ? ?? ? offset offset offset b g r then, gain gain gain r r r g g g b b b ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? where y: s(9,0) ./ u(9,0) when cr c0[0]=0 u, v: s(8,0) . k11: u(12, 10) 12 bits, 2 bit integer and 10-bit fr actional bits. (default: 0x0400h) k13: u(11, 10) 11 bits, 1 bit integer and 10-bit fr actional bits (default: 0x 048f h) k22, k23: u(10, 10) 10 bits, all fractional bits (d efault: k22: 0x 0194 h, k23: 0x 0252 h) k32: u(12, 10) 12 bits, 2 bit integer and 10-bit fr actional bits (default: 0x 0820 h) k11?: s(15,4) roffset, goffset, boffset: s(14,4) 14 bits, 10 bit signed integer and 4-bit fractiona l bits. (default: 0x000h) k13?: s(15,4) k22?, k23?: s(11,2) k32?: s(13,2) rgain, ggain, bgain: u(10, 9) 10bits, 1 bit integer and 9-bit fractional bits. (default: 0x0200h) operation description k11? = k11*y u(12,10) * s(9,0) = s(21,10) truncatin g to s(15,4) k13? = k13*v u(11,10) * s(8,0) = s(19,10) truncatin g to s(14,4) r?? = k11?+k13? s(15,4) + s(14,4) = s(15,4) r? = r?? + roffset s(15,4) + s(14,4) = s(15,4) trun cating to s(13,2) k22? = k22*u u(10,10) * s(9,0) = s(19,10) truncatin g to s(13,4) k23? = k23*v u(10,10) * s(8,0) = s(18,10) truncatin g to s(13,4) g?? = k11?-k22?-k23? s(15,4)+ s(13,4)+ s(13,4) = s( 15,4) g? = g?? + goffset s(15,4) + s(14,4) = s(15,4) trun cating to s(13,2) k32? = k32*u u(12,10) * s(8,0) = s(20,10) truncatin g to s(15,4) b?? = k11?+k32? s(15,4)+ s(15,4) = s(15,4) b? = b?? + boffset s(15,4) + s(14,4) = s(15,4) trun cating to s(13,2) r=rgain*r? u(10,9)*s(13,2)=s(23,11) rounding to u(1 0,0) (clamp) g=ggain*g? u(10,9)*s(13,2)=s(23,11) rounding to u(1 0,0) (clamp) b=bgain*b? u(10,9)*s(13,2)=s(23,11) rounding to u(1 0,0) (clamp) address 0xc2~0xc6 are reserved vivid color-dcc (page 7) register:: dcc_ctrl_0 0xc7 name bits r/w default comments config dcc_en 7 r/w 0 dcc_enable 0: disable 1: enable y_formula 6 r/w 0 y_formula 0: y = (2r+5g+b)/8 1: y = (5r+8g+3b)/16 sc_en 5 r/w 0 soft_clamp 0: disable
1: enable dcc_mode 4 r/w 0 dcc_mode 0: auto mode 1: manual mode scg_en 3 r/w 0 scene_change 0: disable scene-change function 1: enable scene-change function in auto mode bwl_exp 2 r/w 0 bwl_exp 0: disable black/white level expansion 1: enable black/white level expansion in auto mode page_sel 1:0 r/w 0 dcc_page_sel 00: page 0 (for histogram / ymin-max / soft-clampin g / scene-change) 01: page 1 (for y-curve / wbl expansion) 10: page 2 (for calculation parameter) 11: page 3 (for testing and debug) register:: dcc_ctrl_1 0xc8 name bits r/w default comments config gain_en 7 r/w 0 dcc gain control enable 0: disable 1: enable note: dcc gain control enable must delay mov_avg_len frame after dcc enable. dcc_flag 6 r 0 1: time to write highlight window position & normal ized factor, write to clear sat_comp_en 5 r/w 0 saturation compensation enable 0: disable 1: enable bld_mode 4 r/w 0 blending factor control mode 0: old mode 1: new mode (diff. regions have diff. blending fact or) reserved 3:0 -- 0x00 reserved to 0 register:: dcc address port 0xc9 name bits r/w default comments config dcc_addr 7:0 r/w 0x00 dcc address register:: dcc data port 0xca name bits r/w default comments config dcc_data 7:0 r/w 0x00 dcc data register:: nor_factor_h (page0) (access [c9,ca]) 0x00 name bits r/w default comments config reserved 7:6 -- -- reserved nor_fac_h 5:0 r/w 0x00 bit[21:16] of normalized factor; nf=(255/n)*(2^22)
register:: nor_factor_m (page0) (access [c9,ca]) 0x01 name bits r/w default comments config nor_fac_m 7:0 r/w 0x00 bit[15:8] of normalized factor; nf=(255/n)*(2^22) register:: nor_factor_l (page0) (access [c9,ca]) 0x02 name bits r/w default comments config nor_fac_l 7:0 r/w 0x00 bit[7:0] of normalized factor; nf=(255/n)*(2^22) register:: bbe_ctrl (page0) (acce ss[c9,ca]) 0x03 name bits r/w default comments config bbe_en 7 r/w 0 bbe_ena 0: disable black-background exception 1: enable black-background exception reserved 6:4 -- -- reserved bbe_thd 3:0 r/w 0x4 bbe_thd 8-bit rgb threshold for black-background exception register:: nflt_ctrl (page0) (acce ss[c9,ca]) 0x04 name bits r/w default comments config hnflt_en 7 r/w 0 hnflt_ena 0: disable histogram noise filter 1: enable histogram noise filter hnflt_thd 6:4 r/w 0 hnflt_thd threshold for histogram noise filter ynflt_en 3 r/w 0 ynflt_ena 0: disable ymax / ymin noise filter 1: enable ymax / ymin noise filter ynflt_thd 2:0 r/w 0 ynflt_thd threshold for ymax/ymin noise filter (= 4*ynflt_thd ) register:: hist_ctrl (page0) (acce ss[c9,ca]) 0x05 name bits r/w default comments config rh0_limiter 7 r/w 0 rh0_limiter 0: disable rh0 limiter 1: enable rh0 limiter rh1_limiter 6 r/w 0 rh1_limiter 0: disable rh1 limiter 1: enable rh1 limiter real_ma_len 5:3 r -- real mov_avg_len may be different with mov_avg_len, if scg enable mov_avg_len 2:0 r/w 0 mov_avg_len 000: histogram moving average length = 1 001: histogram moving average length = 2 010: histogram moving average length = 4 011: histogram moving average length = 8
100: histogram moving average length = 16 101~111: reserved register:: soft_clamp (page0) (acces s[c9,ca]) 0x06 name bits r/w default comments config soft_clamp 7:0 r/w 0xb0 slope of soft-clamping (= soft_clamp / 256) register:: y_max_lb (page0) (acce ss[c9,ca]) 0x07 name bits r/w default comments config y_max_lb 7:0 r/w 0xff lower bound of y_max (= 4*y_max_lb) register:: y_min_hb (page0) (acce ss[c9,ca]) 0x08 name bits r/w default comments config y_min_hb 7:0 r/w 0x00 higher bound of y_min (= 4*y_min_hb) register:: scg_period (page0) (acces s[c9,ca]) 0x09 name bits r/w default comments config scg_mode 7 r/w 0 scene-change control mode 0: old mode (2553v) 1: new mode (2622) reserved 6:5 -- -- reserved scg_period 4:0 r/w 0x10 scene-change mode period = 1~32. note: scg_period >= mov_avg_len, cred-05[2:0](page0) register:: scg_lb (page0) (acce ss[c9,ca]) 0x0a name bits r/w default comments config scg_lb 7:0 r/w 0x00 scg_diff lower bound for exiting scene-change mode register:: scg_hb (page0) (acce ss[c9,ca]) 0x0b name bits r/w default comments config scg_hb 7:0 r/w 0xff scg_diff higher bound for exiting scene-change mode register:: popup_ctrl (page0) (acces s[c9,ca]) 0x0c name bits r/w default comments config reserved 7:1 -- -- reserved popup_bit 0 r -- reg[0d]~reg[16] are updated every frame. once popup_bit is read, the value of reg[0d] ~ reg[16] w ill not be updated until reg[16] is read.
register:: scg_diff (page0) (acce ss[c9,ca]) 0x0d name bits r/w default comments config scg_diff 7:0 r -- = (histogram difference between current frame and average) / 8 = diff[10:0]>>3 register:: y_max_val (page0) (acces s[c9,ca]) 0x0e name bits r/w default comments config y_max_val 7:0 r -- = max { y_max_lb, (y maximum in current frame / 4) } register:: y_min_val (page0) (acce ss[c9,ca]) 0x0f name bits r/w default comments config y_min_val 7:0 r -- = min { y_min_hb, (y minimum in current frame / 4) } register:: s0_value (page0) (acce ss[c9,ca]) 0x10 name bits r/w default comments config s0_value 7:0 r -- normalized histogram s0 value register:: s1_value (page0) (acce ss[c9,ca]) 0x11 name bits r/w default comments config s1_value 7:0 r -- normalized histogram s1 value register:: s2_value (page0) (acce ss[c9,ca]) 0x12 name bits r/w default comments config s2_value 7:0 r -- normalized histogram s2 value register:: s3_value (page0) (acce ss[c9,ca]) 0x13 name bits r/w default comments config s3_value 7:0 r -- normalized histogram s3 value register:: s4_value (page0) (acce ss[c9,ca]) 0x14 name bits r/w default comments config s4_value 7:0 r -- normalized histogram s4 value register:: s5_value (page0) (acce ss[c9,ca]) 0x15 name bits r/w default comments config s5_value 7:0 r -- normalized histogram s5 value
register:: s6_value (page0) (acce ss[c9,ca]) 0x16 name bits r/w default comments config s6_value 7:0 r -- normalized histogram s6 value register:: yhl_thd (page0) (acces s[c9,ca]) 0x17 name bits r/w default comments config yhl_thd 7:0 r/w 0x00 y_h and y_l theshold when diff[10:0] < yh l_thd[7:0], y_h and y_l keep the previous values register:: def_crv[01] (page1) (acce ss[c9,ca]) 0x00 name bits r/w default comments config def_crv01 7:0 r/w 0x10 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[02] (page1) (acce ss[c9,ca]) 0x01 name bits r/w default comments config def_crv02 7:0 r/w 0x20 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[03] (page1) (acce ss[c9,ca]) 0x02 name bits r/w default comments config def_crv03 7:0 r/w 0x30 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[04] (page1) (acce ss[c9,ca]) 0x03 name bits r/w default comments config def_crv04 7:0 r/w 0x40 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[05] (page1) (acce ss[c9,ca]) 0x04 name bits r/w default comments config def_crv05 7:0 r/w 0x50 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[06] (page1) (acce ss[c9,ca]) 0x05 name bits r/w default comments config def_crv06 7:0 r/w 0x60 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[07] (page1) (acce ss[c9,ca]) 0x06
name bits r/w default comments config def_crv07 7:0 r/w 0x70 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[08] (page1) (acce ss[c9,ca]) 0x07 name bits r/w default comments config def_crv08 7:0 r/w 0x80 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[09] (page1) (acce ss[c9,ca]) 0x08 name bits r/w default comments config def_crv09 7:0 r/w 0x90 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[10] (page1) (acce ss[c9,ca]) 0x09 name bits r/w default comments config def_crv10 7:0 r/w 0xa0 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[11] (page1) (acce ss[c9,ca]) 0x0a name bits r/w default comments config def_crv11 7:0 r/w 0xb0 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[12] (page1) (acce ss[c9,ca]) 0x0b name bits r/w default comments config def_crv12 7:0 r/w 0xc0 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[13] (page1) (acce ss[c9,ca]) 0x0c name bits r/w default comments config def_crv13 7:0 r/w 0xd0 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[14] (page1) (acce ss[c9,ca]) 0x0d name bits r/w default comments config def_crv14 7:0 r/w 0xe0 pre-defined y-curve; keep def_crv[n] def_crv[n-1] register:: def_crv[15] (page1) (acce ss[c9,ca]) 0x0e name bits r/w default comments config def_crv15 7:0 r/w 0xf0 pre-defined y-curve; keep def_crv[n] def_crv[n-1]
register:: def_crv[16] (page1) (acce ss[c9,ca]) 0x0f name bits r/w default comments config def_crv16 7:0 r/w 0x00 pre-defined y-curve; keep def_crv[n] def_crv[n-1] note : default = 0x00 means 0x100 (256) when y-curve boundary is changed (def_crv[16] != 0x 00), disable histogram noise filter. registers below is effective only when auto mode is disable and black/white level expansion is enabled . when auto mode is enabled (dcc_mode=0), y_bl_bias a nd y_wl_bias are read-only. register:: y_bl_bias (page1) (acce ss[c9,ca]) 0x10 name bits r/w default comments config y_bl_bias 7:0 r/w 0x00 y offset for black-level expansion (y_l' = 4*y_bl_bias) register:: y_wl_bias (page1) (acce ss[c9,ca]) 0x11 name bits r/w default comments config y_wl_bias 7:0 r/w 0x00 y offset for while-level expansion ( 1023-y_h' = 4*y_wl_bias) load double buffer cred-00 ~ cred-11 (page1) after write cred-11 when dcc enable register:: sat_factor (page1) (acces s[c9,ca]) 0x12 name bits r/w default comments config reserved 7:6 -- -- reserved sat_factor 5:0 r/w 0x00 saturation compensation factor = 0 ~ 32. registers below is effective only when auto mode is enabled. in manual mode (dcc_mode=1), bld_val will be fixed to 0. it means y-curve is fully determined by def_cur[01~15] register:: bld_ub (page1) (acce ss[c9,ca]) 0x13 name bits r/w default comments config bld_ub 7:0 r/w 0x00 upper bound of blending factor register:: bld_lb (page1) (acce ss[c9,ca]) 0x14 name bits r/w default comments config bld_lb 7:0 r/w 0x00 lower bound of blending factor
register:: dev_factor (page1) (acces s[c9,ca]) 0x15 name bits r/w default comments config dev_factor 7:0 r/w 0x00 deviation weighting factor register:: bld_val_sel (page1) (acces s[c9,ca]) 0x16 name bits r/w default comments config wl_range 7:6 r/w 0x00 white-level range 00: yi = 512 (z8) 01: yi = 576 (z9) 10: yi = 640 (z10) 11: yi = 704 (z11) wl_bld_val 5:4 r/w 0x00 white-level blending factor 00: 0 (user-defined curve) 01: r/2 10: r 11: 2r bl_range 3:2 r/w 0x00 black-level range 00: yi = 448 (z7) 01: yi = 384 (z6) 10: yi = 320 (z5) 11: yi = 256 (z4) bl_bld_val 1:0 r/w 0x00 black-level blending factor 00: 0 (user-defined curve) 01: r/2 10: r 11: 2r register:: bld_val (page1) (acce ss[c9,ca]) 0x17 name bits r/w default comments config bld_val 7:0 r -- = max{ bld_ub ? [(dev_val*dev_factor)/ 256], bld_lb} register:: dev_val_hi (page1) (acce ss[c9,ca]) 0x18 name bits r/w default comments config dev_val_hi 7:0 r -- bit[8:1] of deviation value register:: dev_val_lo (page1) (acces s[c9,ca]) 0x19 name bits r/w default comments config dev_val_lo 7 r -- bit[0] of deviation value reserved 6:0 -- -- reserved register:: sram initial value (page2) (a ccess[c9,ca]) 0x00~0x8f name bits r/w default comments config sram_xx 7:0 w -- addr 00: sram_00 addr 01: sram_01
?. addr 8f : sram_8f register:: sram_bist (page3) (acce ss[c9,ca]) 0x00 name bits r/w default comments config bist_en 7 r/w 0 bist_en 0: disable 1: enable ram_mode 6 r/w 0 ram_mode 0: dclk domain mode (normal mode, bist) 1: mcu domain mode (scg test) reserved 5:2 -- -- reserved bist_period 1 r -- bist_period 0: bist is done 1: bist is running bist_ok 0 r -- bist_ok 0: sram fail 1: sram ok icm (page 7) address: d0 icm control default: 00h bit mode function 7 r/w icm enable 0: disable 1: enable 6 r/w y correction mode 0: dy = (8du+dv)/8 1: dy = (6du+dv)/8 5 r/w icm u/v delta range: 0: original -128~+127 1: double -256~254 4 r/w cm0 enable 0: disable 1: enable 3 r/w cm1 enable 0: disable 1: enable 2 r/w cm2 enable 0: disable 1: enable 1 r/w cm3 enable 0: disable 1: enable 0 r/w cm4 enable 0: disable 1: enable address: d1 icm_sel default: 00h bit mode function 7:5 r/w icm test mode 000: disable 001: bypass u, v result 010: bypass hue/saturation result 011: bypass du, dv value
1xx: r,b as lut input, and bypass lut output to r/g /b output 4 -- reserved 3 r/w cm5 enable 0: disbale 1: enable 2:0 r/w cm select 000: select chroma modifier 0 for accessing through data port 001: select chroma modifier 1 for accessing through data port 010: select chroma modifier 2 for accessing through data port 011: select chroma modifier 3 for accessing through data port 100: select chroma modifier 4 for accessing through data port 101: select chroma modifier 5 for accessing through data port 110~111: reserved address: d2 icm_addr default: 00h bit mode function 7:0 r/w icm port address address: d3 icm_data bit mode function 7:0 r/w icm port data icm_addr will be increased automatically after each byte of icm_data has been accessed. address: d3-00 mst_hue_hb default: x0h bit mode function 7:4 -- reserved 3:0 w high byte[11:8] of master hue for chroma modi fier n. address: d3-01 mst_hue_lb default: 00h bit mode function 7:0 w low byte[7:0] of master hue for chroma modifi er n. address: d3-02 hue_set default: 00h bit mode function 7:6 w cm[n]_lwid 00: cm[n] left width = 64 01: cm[n] left width = 128 10: cm[n] left width = 256 11: cm[n] left width = 512 5:4 w cm[n]_lbuf 00: cm[n] left buffer = 0 01: cm[n] left buffer = 64 10: cm[n] left buffer = 128 11: cm[n] left buffer = 256 3:2 w cm[n]_rwid 00: cm[n] right width = 64 01: cm[n] right width = 128 10: cm[n] right width = 256 11: cm[n] right width = 512 1:0 w cm[n]_rbuf 00: cm[n] right buffer = 0 01: cm[n] right buffer = 64 10: cm[n] right buffer = 128 11: cm[n] right buffer = 256 address: d3-03~32 u/v offset default: 00h bit mode function 7:0 w addr 03: u offset 00, -128~127 addr 04: v offset 00, -128~127 addr 05: u offset 01, -128~127 addr 06: v offset 01, -128~127 addr 07: u offset 02, -128~127 addr 08: v offset 02, -128~127 addr 09: u offset 03, -128~127
addr 0a: v offset 03, -128~127 addr 0b: u offset 04, -128~127 addr 0c: v offset 04, -128~127 addr 0d: u offset 05, -128~127 addr 0e: v offset 05, -128~127 addr 0f: u offset 06, -128~127 addr 10: v offset 06, -128~127 addr 11: u offset 07, -128~127 addr 12: v offset 07, -128~127 addr 13: u offset 10, -128~127 addr 14: v offset 10, -128~127 addr 15: u offset 11, -128~127 addr 16: v offset 11, -128~127 addr 17: u offset 12, -128~127 addr 18: v offset 12, -128~127 addr 19: u offset 13, -128~127 addr 1a: v offset 13, -128~127 addr 1b: u offset 14, -128~127 addr 1c: v offset 14, -128~127 addr 1d: u offset 15, -128~127 addr 1e: v offset 15, -128~127 addr 1f: u offset 16, -128~127 addr 20: v offset 16, -128~127 addr 21: u offset 17, -128~127 addr 22: v offset 17, -128~127 addr 23: u offset 20, -128~127 addr 24: v offset 20, -128~127 addr 25: u offset 21, -128~127 addr 26: v offset 21, -128~127 addr 27: u offset 22, -128~127 addr 28: v offset 22, -128~127 addr 29: u offset 23, -128~127 addr 2a: v offset 23, -128~127 addr 2b: u offset 24, -128~127 addr 2c: v offset 24, -128~127 addr 2d: u offset 25, -128~127 addr 2e: v offset 25, -128~127 addr 2f: u offset 26, -128~127 addr 30: v offset 26, -128~127 addr 31: u offset 27, -128~127 addr 32: v offset 27, -128~127 y-peaking filter and coring control (for display do main) (page 7) address: d6 peaking/coring access port control default: 00h bit mode function 7 r/w enable peaking / coring access port 6 r/w peaking/coring enable 0: disable 1: enable 5 r/w y peaking coefficient resolution 0: n/32 1: n/64
4:3 -- reserved 2:0 r/w peaking/coring port address address: d7-00 peaking_coef0 bit mode function 7:0 r/w coefficient c0 of peaking filter: valid range: -128/32(-128) ~ 127/32 (127) (2?s com plement) address: d7-01 peaking_coef1 bit mode function 7:0 r/w coefficient c1 of peaking filter: valid range: -128/32(-128) ~ 127/32 (127) (2?s com plement) address: d7-02 peaking_coef2 bit mode function 7:0 r/w coefficient c2 of peaking filter: valid range: -128/32(-128) ~ 127/32 (127) (2?s com plement) address: d7-03 coring_min bit mode function 7:5 r/w reserved 4:0 r/w coring minimum value address: d7-04 coring_max_pos bit mode function 7:0 r/w coring maximum positive value address: d7-05 coring_max_neg bit mode function 7:0 r/w coring maximum negitive value (2?s complement) y?[n] = c0*y[n] + c1*(y[n-1]+y[n+1]) + c2*(y[n-2]+y [n+2]) , -256<=y?<=255 ypeak = y?[n] ? coring_min, if y?[n] >= 0, = y'[n] + coring_min, if y'[n] < 0 if ( |y'[n]| <= coring_min ) y"[n] = 0, else if ypeak >= coring_max_pos y"[n] = coring_max_pos else if ypeak <= coring_max_neg y"[n] = coring_max_neg else y"[n] = ypeak yo[n] = y[n] + y??[n], 0 <= yo[n] <= 255 dcr (page 7) register::dcr address port 0xd8 name bits r/w default comments config
dcr_addr 7:2 -- 0 dcr address result_read 1 r/w 0 0: disable read to refresh measure result. 1: read dcr measure result. measure_start 0 r/w 0 0: finish or disable 1: start dcr computation. register:: dcr data port 0xd9 name bits r/w default comments config dcr_data 7:0 r/w 0x00 dcr data register:: dcr_theshold1 (access[d8,d9]) 0x00 name bits r/w default comments config threshold1_value 7:0 r/w 0x08 dcr threshold1. (r+g+b)*0.75 if we want to set threshold1 = 200. threshold1_valu e = 200*0.75 = 150. register:: dcr_theshold2 (access[d8,d9]) 0x01 name bits r/w default comments config threshold2_value 7:0 r/w 0x60 dcr threshold2. (threshold2 > threshold1 ) (r+g+b)*0.75 if we want to set threshold2 = 200. threshold2_valu e = 200*0.75 = 150. register::dcr_above_th1_num_2 (access[d8,d9]) 0x02 name bits r/w default comments config above_th1_num_2 7:0 r 0 total pixel number above threshold1: bit[23:16] register::dcr_above_th1_num_1 (access[d8,d9]) 0x03 name bits r/w default comments config above_th1_num_1 7:0 r 0 total pixel number above threshold1: bit[15:8] register::dcr_above_th1_num_0 (access[d8,d9]) 0x04
name bits r/w default comments config above_th1_num_0 7:0 r 0 total pixel number above threshold1: bit[7:0] register::dcr_above_th1_val_3 (access[d8,d9]) 0x05 name bits r/w default comments config above_th1_val_3 7:0 r 0 total sum (r+g+b) of pixel value above threshold1: bit[31:24] register::dcr_above_th1_val_2 (access[d8,d9]) 0x06 name bits r/w default comments config above_th1_val_2 7:0 r 0 total sum (r+g+b) of pixel value above threshold1: bit[23:16] register::dcr_above_th1_val_1 (access[d8,d9]) 0x07 name bits r/w default comments config above_th1_val_1 7:0 r 0 total sum (r+g+b) of pixe l value above threshold1: bit[15:8] register::dcr_above_th1_val_0 (access[d8,d9]) 0x08 name bits r/w default comments config above_th1_val_0 7:0 r 0 total sum (r+g+b) of pixel value above threshold1: bit[7:0] register::dcr_above_th2_num_2 (access[d8,d9]) 0x09 name bits r/w default comments config above_th2_num_2 7:0 r 0 total pixel number above threshold2: bit[23:16] register::dcr_above_th2_num_1 (access[d8,d9]) 0x0a name bits r/w default comments config
above_th2_num_1 7:0 r 0 total pixel number above threshold2: bit[15:8] register::dcr_above_th2_num_0 (access[d8,d9]) 0x0b name bits r/w default comments config above_th2_num_0 7:0 r 0 total pixel number above threshold2: bit[7:0] register::dcr_above_th2_val_3 (access[d8,d9]) 0x0c name bits r/w default comments config above_th2_val_3 7:0 r 0 total sum (r+g+b) of pixel value above threshold2: bit[31:24] register::dcr_above_th2_val_2 (access[d8,d9]) 0x0d name bits r/w default comments config above_th2_val_2 7:0 r 0 total sum ( r+g+b) of pixel value above threshold2: bit[23:16] register::dcr_above_th2_val_1 (access[d8,d9]) 0x0e name bits r/w default comments config above_th2_val_1 7:0 r 0 total sum (r+g+b) of pixel value above threshold2: bit[15:8] register::dcr_above_th2_val_0 (access[d8,d9]) 0x0f name bits r/w default comments config above_th2_val_0 7:0 r 0 total sum (r+g+b) of pixel value above threshold2: bit[7:0] register::dcr_high_lv_num_r_1 (access[d8,d9]) 0x10 name bits r/w default comments config high_lv_num_r_1 7:0 r 0 dynamically detect highest level pixel number of re d channel. rmax_num[15:8]
register::dcr_high_lv_num_r_0 (access[d8,d9]) 0x11 name bits r/w default comments config high_lv_num_r_0 7:0 r 0 dynamically detect highest level pixel numb er of red channel. rmax_num[7:0] register::dcr_low_lv_num_r_1 (access[d8,d9]) 0x12 name bits r/w default comments config low_lv_num_r_1 7:0 r 0 dynamically detect the lowest level pixel number of red channel. rmin_num[15:8] register::dcr_low_lv_num_r_0 (access[d8,d9]) 0x13 name bits r/w default comments config low_lv_num_r_0 7:0 r 0 dynamically detect the lowest level pixel number of red channel. rmin_num[7:0] register::dcr_high_lv_val_r (access[d8,d9]) 0x14 name bits r/w default comments config high_lv_val_r 7:0 r 0 dynamically detect highest level value of red c hannel. register::dcr_low_lv_val_r (access[d8,d9]) 0x15 name bits r/w default comments config low_lv_val_r 7:0 r 0 dynamically detect the lowest level value of re d channel. register::dcr_high_lv_num_g_1 (access[d8,d9]) 0x16 name bits r/w default comments config
high_lv_num_g_1 7:0 r 0 dynamically detect the highest level pixel numb er of green channel. gmax_num[15:8] register::dcr_high_lv_num_g_0 (access[d8,d9]) 0x17 name bits r/w default comments config high_lv_num_g_0 7:0 r 0 dynamically detect the highest level pixel numb er of green channel. gmax_num[7:0] register::dcr_low_lv_num_g_1 (access[d8,d9]) 0x18 name bits r/w default comments config low_lv_num_g_1 7:0 r 0 dynamically detect the lowest level pixel numbe r of green channel. gmin_num[15:8] register::dcr_low_lv_num_g_0 (access[d8,d9]) 0x19 name bits r/w default comments config low_lv_num_g_0 7:0 r 0 dynamically detect the lowest level pixel numbe r of green channel. gmin_num[7:0] register::dcr_high_lv_val_g (access[d8,d9]) 0x1a name bits r/w default comments config high_lv_val_g 7:0 r 0 dynamically detect the highest level value of g reen channel. register::dcr_low_lv_val_g (access[d8,d9]) 0x1b name bits r/w default comments config low_lv_val_g 7:0 r 0 dynamically detect the lowest level value of gr een channel. register::dcr_high_lv_num_b_1 (access[d8,d9]) 0x1c name bits r/w default comments config
high_lv_num_b_1 7:0 r 0 dynamically detect the highest level pixel numb er of blue channel. bmax_num[15:8] register::dcr_high_lv_num_b_0 (access[d8,d9]) 0x1d name bits r/w default comments config high_lv_num_b_0 7:0 r 0 dynamically detect the highest level pixel numb er of blue channel. bmax_num[7:0] register::dcr_low_lv_num_b_1 (access[d8,d9]) 0x1e name bits r/w default comments config low_lv_num_b_1 7:0 r 0 dynamically detect the lowest level pixel numbe r of blue channel. bmin_num[15:8] register:: dcr_high_lv_val_b (access[d8,d9]) 0x20 name bits r/w default comments config high_lv_val_b 7:0 r 0 dynamically detect the highest level value of b lue channel. register:: dcr_low_lv_val_b (access[d8,d9]) 0x21 name bits r/w default comments config low_lv_val_b 7:0 r 0 dynamically detect the lowest level value of bl ue channel. pattern generator in display domain (page 7) rtd3182 supports programmable patterns, such as gra y-level, chessboard, dot-pattern, etc., for register::dcr_low_lv_num_b_0 (access[d8,d9]) 0x1f name bits r/w default comments config low_lv_num_b_0 7:0 r 0 dynamically detect the lowest level pixel numbe r of blue channel. bmin_num[7:0]
display image testing. register::disp_pg_r_ctrl 0xf0 name bits r/w default comments config pg_enable 7 r/w 0 dispaly pattern gen. function enable pg_r_ctrl_dum 6 r/w 0 dummy pg_rout_inv_en 5 r/w 0 inverse data output pg_r_clamp_en 4 r/w 0 adder result clamp to 10?h3fff line_r_tog_en 3 r/w 0 data toggled in each pixel-step line_r_inc_en 2 r/w 0 data increment in each line-step pixel_r_tog_en 1 r/w 0 data toggled in each pixel-step pixel_r_inc_en 0 r/w 0 data incremented in each pixel-step register::disp_pg_g_ctrl 0xf1 name bits r/w default comments config pg_g_ctrl_dum 7:6 r/w 0 dummy pg_gout_inv_en 5 r/w 0 inverse data output pg_g_clamp_en 4 r/w 0 adder result clamp to 10?h3fff
line_g_tog_en 3 r/w 0 data toggled in each pixel-step line_g_inc_en 2 r/w 0 data increment in each line-step pixel_g_tog_en 1 r/w 0 data toggled in each pixel-step pixel_g_inc_en 0 r/w 0 data incremented in each pixel-step register::disp_pg_b_ctrl 0xf2 name bits r/w default comments config pg_b_ctrl_dum 7:6 r/w 0 dummy pg_bout_inv_en 5 r/w 0 inverse data output pg_b_clamp_en 4 r/w 0 adder result clamp to 10?h3fff line_b_tog_en 3 r/w 0 data toggled in each pixel-step line_b_inc_en 2 r/w 0 data increment in each line-step pixel_b_tog_en 1 r/w 0 data toggled in each pixel-step pixel_b_inc_en 0 r/w 0 data incremented in each pixel-step register::disp_pg_r_initial 0xf3 name bits r/w default comments config pg_r_init 7:0 r/w 0 initial pattern value for red data [9:2] register::disp_pg_g_initial 0xf4 name bits r/w default comments config pg_g_init 7:0 r/w 0 initial pattern value for green data [9:2] register::disp_pg_b_initial 0xf5 name bits r/w default comments config pg_b_init 7:0 r/w 0 initial pattern value for blue data [9:2] register::disp_pg_pixel_delta 0xf6 name bits r/w default comments config pg_pixel_delta 7:0 r/w 0 pixel delta value for incremental register::disp_pg_line_delta 0xf7 name bits r/w default comments config pg_line_delta 7:0 r/w 0 line delta value for incremental register::disp_pg_pixel_step_msb 0xf8
name bits r/w default comments config pg_pixel_step_m 7:0 r/w 01h pixel step for toggle/incremental, can not be 0 register::disp_pg_line_step_msb 0xf9 name bits r/w default comments config pg_line_step_m 7:0 r/w 01h line step for toggle/incremental, can not be 0 register::disp_pg step_lsb 0xfa name bits r/w default comments config line_step_dum 7:6 r/w 0 dummy pg_line_step_l 5:4 r/w 0 decimal part for line-step pixel_step_dum 3:2 r/w 0 dummy pg_pixel_step_l 1:0 r/w 0 decimal part for pixel-step ex: if the pattern is 256 gray level in 640 pixels, the wanted pixel_step is 640/256 = 2.5. hence, pg_pixel_step_m = 2h and pg_pixel_step_l = 2?b10. ( {pg_pixel_step_m, pg_pixel_step_l} = 2.5 ).
reserved (page 8)
reserved (page 9)
reserved (page a) reserved (page b) reserved (page c)
register 1(page d) interrupt control register::irq_status 0xff00 name bits r/w default comments config reserved 7 -- -- reserved m2pll_irq_event 6 r/w 0 m2pll-abnormal event status 1. select m2pll as clock source, but m2pll power down, power saving or output disable, clear this bi t to disable the interrupt rport wport cec_irq_event 5 r/w 0 cec event status 1. if cec func irq event occurred since the last status cleared rport wport sca_irq_event 4 r/w 0 scalar-related event status 1. if scalar integrated irq event occurred since th e last status cleared rport wport reserved 3:1 -- 0 reserved to 0 ddc_irq_event 0 r/w 0 ddc event status 1: if the ddc irq event occurred since the last sta tus cleared rport wport register:: rev_dummy1 rev_dummy1 rev_dummy1 rev_dummy1 0xff02 0xff02 0xff02 0xff02 name bits r/w default comments config rev_dummy1 7:0 r/w 00 dummy1 ddc rtd3580 has three ddc ports. the mcu can access the following three ddc interface: ddc_ram1 (fd80~fdff) through pin asdl and asda by a dc ddc channel. ddc_ram2 (fe00~fe7f) through pin dsdl and dsda by d vi ddc channel. besides, the ddc_ram1, ddc_ram2, can be assigned fr om 128 to 256bytes. the actual
sizes of each ddc_ram are determined by the combina tion of addcram_st, dddcram_st, and hddcram_st. the ddc rams are shared with mcu?s xsram, configuration must be take care for reserving xsram for programming. for example, set addcram_st = 0x2, dddcram_st = 0x3, , dvi ddc. the xsram for mcu is 512 bytes and adc ddc/hdmi ddc is used with 256 bytes. the ddc of rtd3580 is compliant with vesa ddc stand ard. all ddc slaves are in ddc1 mode after reset. when a high to low transition is detected on ascl/dscl pin, the ddc slave will enter ddc2 transition mode. the ddc slave can revert to ddc1 mode if the scl signal keeps unchanged for 128 vsync periods in ddc2 trans ition mode and rvt_a_ddc1_en / rvt_d_ddc1_en = 1. in ddc2 transition mode, the ddc slave will lock in ddc2 mode if a valid control byte is received. furthermore, user c an force the ddc slave to operate ddc2 mode by setting a_ddc2 / d_ddc2 = 1. register:: adc_segment_address 0xff19 name bits r/w default comments config adc_seg_addr 7:1 r/w 0x30 adc slave address for segment control reserved 0 -- -- reserved register:: adc_segment_data 0xff1a name bits r/w default comments config adc_seg_data 7:0 r/w 0x00 data access for slave id, adc_segment_address, in adc ddc rport wport register::adc_ddc_enable 0xff1b name bits r/w default comments config a_ddc_addr 7:5 r/w 0 adc ddc channel address least significant 3 bits (the default ddc channel address msb 4 bits is ?a? ) a _scl_dbn_sel 4 r/w 0 scl debounce clock selection 0: de-bounce clock (after clock divider) 1: de-bounce reference clock a_ddc_w_sta 3 r/w 0 adc ddc write status (for ext ernal ddc access only) it is cleared after write. (no matter what the dat a are) rport wport
a_ddcram_w_en 2 r/w 0 adc ddc sram write enable (for external ddc access only) 0: disable 1: enable a_dbn_en 1 r/w 1 adc ddc de-bounce enable 0: disable 1: enable (with crystal/4) a_ddc_en 0 r/w 0 adc ddc channel enable bit 0: mcu access enable 1: ddc channel enable register::adc_ddc_control_1 0xff1c name bits r/w default comments config a_dbn_clk_sel 7:6 r/w 0 de-bounce clock divider 00: 1/1 reference clock 01: 1/2 reference clock 1x: 1/4 reference clock a_stop_dbn_sel 5:4 r/w 0 de-bounce sda stage 0x: latch one stage 10: latch two stage 11: latch three stage a_sys_ck_sel 3 r/w 0 de-bounce reference clock 0: crystal clock 1. serial flash clock (m2pll / flash_div) a_ddc2 2 r/w 0 force to adc ddc to ddc2 mode 0: normal operation 1: ddc2 is active rst_a_ddc 1 r/w 0 reset adc ddc circuit 0: normal operation 1: reset (auto cleared) rport wport rvt_a_ddc1_en 0 r/w 0 adc ddc revert to ddc1 enable(scl idle for 128 vsync) 0: disable 1: enable
register::adc_ddc_control_2 0xff1d name bits r/w default comments config a_seg_wr_en 7 r/w 0 enable interrupt of adc segme nt address write 0: disable 1: enable reserved 6:2 -- -- reserved a_seg_wr 1 r/w 0 adc ddc segment write status 0: no external write after clear 1: new external write after clear it is cleared after write wport rport a_force_scl_l 0 r/w 0 force external scl bus low 1: driving scl = 0 after external scl = 0 0: release scl register::dvi_ddc_enable 0xff1e name bits r/w default comments config d_ddc_addr 7:5 r/w 0 dvi ddc channel address least significant 3 bits (the default ddc channel address msb 4 bits is ?a? ) d_scl_dbn_sel 4 r/w 0 scl debounce clock selection 0: de-bounce clock (after clock divider) 1: de-bounce reference clock d_ddc_w_sta 3 r/w 0 dvi ddc external write status (for external ddc a ccess only) it is cleared after write. wport rport d_ddcram_w_en 2 r/w 0 dvi ddc external write enable (for external ddc a ccess only) 0: disable 1: enable d_dbn_en 1 r/w 1 dvi ddc debounce enable 0: disable 1: enable (with crystal/4) d_ddc_en 0 r/w 0 dvi ddc channel enable switch 0: mcu access enable 1: external ddc access enable register::dvi_ddc_control_1 0xff1f name bits r/w default comments config
d_dbn_clk_sel 7:6 r/w 0 de-bounce clock divider 00: 1/1 reference clock 01: 1/2 reference clock 1x: 1/4 reference clock d_stop_dbn_sel 5:4 r/w 0 de-bounce sda stage 0x: latch one stage 10: latch two stage 11: latch three stage d_sys_ck_sel 3 r/w 0 de-bounce reference clock 0: crystal clock 1. serial flash clock (m2pll / flash_div) d_ddc2 2 r/w 0 force to dvi ddc to ddc2 mode 0: normal operation 1: ddc2 is active rst_d_ddc 1 r/w 0 reset dvi ddc circuit 0: normal operation 1: reset (auto cleared) rport wport rvt_d_ddc1_en 0 r/w 0 dvi ddc revert to ddc1 enable(scl idle for 128 vsync) 0: disable 1: enable register::dvi_ddc_control_2 0xff20 name bits r/w default comments config reserved 7:2 -- -- reserved d_seg_wr 1 r/w 0 dvi ddc segment write status 0: no external write after clear 1: new external write after clear it is cleared after write wport rport d_force_scl_l 0 r/w 0 force external scl bus low 1: driving scl = 0 after external scl = 0 0: release scl register::ddcram_partition 0xff21 name bits r/w default comments config reserved 7:6 - addcram_st 5:4 r/w 0x3 addc ram start address is 0x00 + addcram_st*0x80, addcram size =
dddcram_st ? addcram_st dddcram_st 3:2 r/w 0x3 dddc ram start address is 0x80 + dddcram_st*0x80, dddcram size = hddcram_st ? dddcram_st reserved 1:0 reserved register::vsync_sel 0xff22 name bits r/w default comments config reserved 7:4 - vs_con1 3:2 r/w 0 00: vsync1 signal is connected to adc ddc 01: vsync1 signal is connected to dvi ddc 1x: vsync1 signal is not connected reserved 1:0 -- 0 reserved ddc-ci register::iic_set_slave 0xff23 name bits r/w default comments config iic_addr 7:1 r/w 37 iic slave address to decode ch_sel 0 r/w 0 channel select, overridden by hch_sel(0xff2b[0]) = 1 0: from adc ddc 1: from dvi ddc register::iic_sub_in 0xff24 name bits r/w default comments config iic_sub_addr 7:0 r 00 iic sub-address received register::iic_data_in 0xff25 name bits r/w default comments config iic_d_in 7:0 r 00 iic data received. 16-bytes depth read in buff er mode rport register::iic_data_out 0xff26 name bits r/w default comments config iic_d_out 7:0 w 00 iic data to be transmitted rport
wport register::iic_status 0xff27 name bits r/w default comments config a_wr_i 7 r/w 0 if adc ddc detects a stop condition in write mode, this bit is set to ?1? . write 0 to clear. rport wport d_wr_i 6 r/w 0 if dvi ddc detects a stop condition in write mode, this bit is set to ?1? . write 0 to clear. rport wport ddc_128vs1_i 5 r/w 0 in ddc2 transition mode, scl idle for 128 vsync. write 0 to clear. rport wport stop_i 4 r/w 0 if iic detects a stop condition(slave address must match), this bit is set to ?1? . write 0 to clear. rport wport d_out_i 3 r 0 if iic_data_out loaded to serial-out-byte, this bit is set to ?1?. write iic_data_out (ff25) to clear. d_in_i 2 r 0 if iic_data_in latched, this bit is set to ?1? . read iic_data_in (ff24) to clear. sub_i 1 r/w 0 if iic_sub latched, this bit is set to ?1? wr ite 0 to clear. rport wport slv_i 0 r/w 0 if iic_slave latched, this bit is set to ?1? write 0 to clear. rport wport register::iic_irq_control 0xff28 name bit s r/w defaul t comments config awi_en 7 r/w 0 0: disable the a_wr_i signal as an interrupt source 1: enable the a_wr_i signal as an interrupt source dwi_en 6 r/w 0 0: disable the d_wr_i signal as an interrupt source 1: enable the d_wr_i signal as an interrupt source ddc_128vsi1_en 5 r/w 0 0: disable the 128vs1_i signal as an interrup t source 1: enable the 128vs1_i signal as an interrupt sourc e
stopi_en 4 r/w 0 0: disable the stop_i signal as an interrupt source 1: enable the stop_i signal as an interrupt source doi_en 3 r/w 0 0: disable the d_out_i signal as an interrup t source 1: enable the d_out_i signal as an interrupt sourc e dii_en 2 r/w 0 0: disable the d_in_i signal as an interrupt source 1: enable the d_in_i signal as an interrupt source subi_en 1 r/w 0 0: disable the sub_i signal as an interrupt source 1: enable the sub_i signal as an interrupt source slvi_en 0 r/w 0 0: disable the slv_i signal as an interrupt source 1: enable the slv_i signal as an interrupt source register::iic_status2 0xff29 name bits r/w default comments config iic_force_scl_l 7 r/w 0 force scl = 0 when one of the following tow case happen: 1. iic_buf_full = 1 in write mode 2. iic_buf_empty = 1 in read mode force_nack 6 r/w 0 force iic return nack when one of the following tow case happen: iic_buf_full = 1 in write mode iic_buf_ov 5 r/w 0 iic_data_buffer overflow. write ?0? to clear rport wport iic_buf_un 4 r/w 0 iic_data_buffer underflow. write ?0? to clear rport wport ddc_128vs2_i 3 r/w 0 in ddc2 transition mode, scl idle for 128 vsync. write 0 to clear. write ?0? to clear rport wport iic_buf_full 2 r 0 iic_data_buffer full if iic_data buffer is full, this bit is set to ?1? . (on- line monitor) the iic_data buffer full status will be on-line- monitor the condition, once it becomes full, it kept high, if it is not-full, then it goes low. iic_buf_empty 1 r 0 iic_data_buffer empty
if iic_data buffer is empty, this bit is set to ?1 ? . (on-line monitor) the iic_data buffer empty status will be on-line-monitor the condition, once it becomes empty, it kept high, if it is not-empty, then it goes low. reserved 0 r/w 0 reserved rport wport register::iic_irq_control2 0xff2a name bits r/w default comments config auto_rst_buf 7 r/w 0 auto reset iic_data buffer 0: disable 1: enable in host (pc) write enable, when iic write (no start after iic_sub), reset iic_data buffer. rst_data_buf 6 r/w 0 reset iic_data buffer 0: finish 1: reset wport rport data_buf_wen 5 r/w 0 iic_data buffer write enable 0: host (pc) write enable 1: slave (mcu) write enable both pc and mcu can read iic_data buffer, but only one can write iic_data buffer. dummy_2 4:3 r/w 0 reserved ddc_buf_full_en 2 r/w 0 0: disable the ddc_data_buffer full signal as an interrupt source 1: enable the ddc_data_buffer full signal as an interrupt source ddc_buf_empty_en 1 r/w 0 0: disable the ddc_data_buffer empty signal as an interrupt source 1: enable the ddc_data_ buffer empty signal as an interrupt source reserved 0 reserved register::iic_channel_control 0xff2b name bits r/w defaul t comments config
reserved 7:2 -- 0 reserved rls_scl_su 1 r/w 0 set iic data setup time when hol ding scl low 0: use delay chain (~5ns) 1: use crystal clock to increase data setup time re lative to scl clock line reserved 0 -- 0 reserved the access ports below are used for external host i nterface only. register::adc_ddc_index 0xff2f name bits r/w default comments config a_ddc_index 7:0 r/w 0 ddc sram read/write index register [7:0] rpo rt wport register::adc_ddc_access_port 0xff30 name bits r/w default comments config a_ddc_access_port 7:0 r/w 0 ddc sram read/write port rport wport register::dvi_ddc_index 0xff31 name bits r/w default comments config d_ddc_index 7:0 r/w 0 ddc sram read/write index register [7:0] rpo rt wport register::dvi_ddc_access_port 0xff32 name bits r/w default comments config d_ddc_access_port 7:0 r/w 0 ddc sram read/write port rport wport register:: ddcci_remain_data 0xff35 name bits r/w default comments config reserved 7:5 -- 0 reserved ddcci_remain_len 4:0 r 0 ddcci remaining data length (= write_pointer ? read_pointer)
register:: dvi_segment_address 0xff36 name bits r/w default comments config dvi_seg_addr 7:1 r/w 0x30 dvi ddc slave address for segment control reserved 0 -- -- reserved register:: dvi_segment_data 0xff37 name bits r/w default comments config dvi_seg_data 7:0 r/w 0x00 data access for slave id, dvi_segment_address, in dvi ddc rport wport pwm rtd3580 supports 6 channels of pwm dac. the resolut ion of each pwm is 12-bit. pwm0, pwm1, pwm2, are connected to da0, da1, da2, respec tively. the figure below represents the pwm clock generator. based on the clock, we mak e up the pwm waveform which frequency is 1/4096 of the pwm clock. the pwm duty registers have 12-bit resolution. thes e registers have double buffer mechanism. when write the msb bit, the 12-bit data will be loa ded. the pwm frequency is : fpwm= fclk /2 m /(n+1) /4096 the pwm frequency range is : fclk=27m, fpwm = 6.6khz ~ 0.2hz fclk=243m, fpwm = 60khz ~ 1.8hz 1/2 m 1/(n+1) osc pll pwm clock generator first stage output second stage output 243mhz 27mhz fclk register::pwm_ck_sel 0xff3a
name bits r/w default comments config pwm_ck_sel_dummy 7:6 r/w 0 dummy reserved 5:3 reserved pwm2_ck_sel 2 r/w 0 pwmx clock generator input source 0: crystal 1: pll output pwm1_ck_sel 1 r/w 0 pwmx clock generator input source 0: crystal 1: pll output pwm0_ck_sel 0 r/w 0 pwmx clock generator input source 0: crystal 1: pll output register::pwm03_m 0xff3b name bits r/w default comments config reserved 7:6 reserved pwm2_m 5:4 r/w 0 pwmx clock first stage divider pwm1_m 3:2 r/w 0 pwmx clock first stage divider pwm0_m 1:0 r/w 0 pwmx clock first stage divider register::pwm45_m 0xff3c name bits r/w default comments config pwm_m_dummy 7:4 r/w 0 dummy reserved 3:0 reserved register::pwm01_n_msb 0xff3d name bits r/w default comments config pwm1h_n 7:4 r/w 0 pwmx clock second stage divider msb[11:8] pwm0h_n 3:0 r/w 0 pwmx clock second stage divider msb[11:8]
register::pwm0_n_lsb 0xff3e name bits r/w default comments config pwm0l_n 7:0 r/w 0 pwmx clock second stage divider lsb[7:0] register::pwm1_n_lsb 0xff3f name bits r/w default comments config pwm1l_n 7:0 r/w 0 pwmx clock second stage divider lsb[7:0] register::pwm23_n_msb 0xff40 name bits r/w default comments config reserved 7:4 reserved pwm2h_n 3:0 r/w 0 pwmx clock second stage divider msb[11:8] register::pwm2_n_lsb 0xff41 name bits r/w default comments config pwm2l_n 7:0 r/w 0 pwmx clock second stage divider lsb[7:0] register::pwml 0xff46 name bits r/w default comments config pwm_w_db_wr 7 r/w 0 write 1 to set pwm_width if pwm_w_db_en = 1?b1. auto-clear after pwm_width was loaded rport wport pwm_w_db_mode 6 r/w 0 pwm width setting double-buffer mode 0: setting active after pwm_w_db_wr = 1 1: setting active after pwm_w_db_wr = 1 & dvs. reserved 5:3 reserved pwm2l 2 r/w 0 0: enable active h 1: enable active l pwm1l 1 r/w 0 0: enable active h 1: enable active l pwm0l 0 r/w 0 0: enable active h 1: enable active l register::pwm_vs_ctrl 0xff47 name bits r/w default comments config
pwm_vs_ctrl_dum 7:6 r/w 0 dummy reserved 5:3 reserved pwm2_vs_rst_en 2 r/w 0 0: disable 1: enable pwm2 reset by dvs pwm1_vs_rst_en 1 r/w 0 0: disable 1: enable pwm1 reset by dvs pwm0_vs_rst_en 0 r/w 0 0: disable 1: enable pwm0 reset by dvs register::pwm_en 0xff48 name bits r/w default comments config pwm_w_db_en 7 r/w 0 0: pwm width set when write msb 1: pwm width setting double-buffered enable pwm_width_sel 6 r/w 0 0: pwmxl_dut is active 1: pwmxl_dut is inactive, forced to 4?h0 internally reserved 5:3 reserved pwm2_en 2 r/w 0 0: pwm output disable 1: pwm output enable pwm1_en 1 r/w 0 0: pwm output disable 1: pwm output enable pwm0_en 0 r/w 0 0: pwm output disable 1: pwm output enable register::pwm_ck 0xff49 name bits r/w default comments config pwm_ck_dummy 7:6 r/w 0 dummy reserved 5:3 reserved pwm2_ck 2 r/w 0 0: select first stage output 1: select second stage output pwm1_ck 1 r/w 0 0: select first stage output 1: select second stage output pwm0_ck 0 r/w 0 0: select first stage output 1: select second stage output register::pwm0h_dut 0xff4a name bits r/w default comments config pwm0h_dut 7:0 r/w 0 pwm0[11:4] duty width when write the msb bit (pwm_w_db_en=0) , the 12-bit rport
data will be loaded. wport register::pwm1h_dut 0xff4b name bits r/w default comments config pwm1h_dut 7:0 r/w 0 pwm1[11:4] duty width when write the msb bit (pwm_w_db_en=0) , the 12-bit data will be loaded. rport wport register::pwm01l_dut 0xff4c name bits r/w default comments config pwm1l_dut 7:4 r/w 0 pwm1[3:0] duty width rport wport pwm0l_dut 3:0 r/w 0 pwm0[3:0] duty width rport wport register::pwm2h_dut 0xff4d name bits r/w default comments config pwm2h_dut 7:0 r/w 0 pwm2[11:4] duty width when write the msb bit (pwm_w_db_en=0) , the 12-bit data will be loaded. rport wport register::pwm23l_dut 0xff4f name bits r/w default comments config reserved 7:4 reserved pwm2l_dut 3:0 r/w 0 pwm2[3:0] duty width rport wport register:: rev_dum rev_dum rev_dum rev_dummy3 my3 my3 my3 0x 0x0x 0xff ffff ff5 55 53 33 3 name bits r/w default comments config rev_dummy3 7:0 r/w 00 dummy3
register 2(page e) 0xff76~0xff93 reserved pin-share register:: pin_share _ctrl00 0xff94 name bits read/ write reset state comments config video8_sel 7 r/w 0x0 video8 source select 0: pin47~48, pin1~7 (qfn48) or pin62~64, pin1~6 (qfn64) 1: pin59, pin62~63, pin1~6 (qfn64) reserved 6:3 r/w 0x00 reserved to 0 sdram_en 2 r/w 0x00 sdram enable 0: no sdram 1: mcm sdram sdram_size 1 r/w 0x0 sdram size 0: 1mx16 sdram 1: 1mx32 sdram package_type 0 r/w 0x0 package type 0: 48pin package 1: 64pin package register:: pin_share_ctrl01 0xff95 name bits read/ write reset state comments config dqm3 7 r/w 0x0 sdr dqm3 (udqm) ? data input/output mask 0: non-active 1: active dqm2 6 r/w 0x0 sdr dqm2 (ldqm) ? data input/output mask 0: non-active 1: active dqm1 5 r/w 0x0 sdr dqm1 ? data input/output mask 0: non-active 1: active dqm0 4 r/w 0x0 sdr dqm0 ? data input/output mask 0: non-active 1: active ddcscl1 3:2 r/w 0x0 pin44 (48pin) / pin58 (64pin) (pad_ddcscl1) 00: ddcscl

01: pwm0 10: tcon7 11: aux-ch_p0 ddcsda1 1:0 r/w 0x0 pin43 (48pin) / pin57 (64pin) (pad_ddcsda1) 00: ddcsda

01: pwm1 10: tcon9 11: aux-ch_n0/irq effectively only if crff95[3:2] != 2'b11,when
crff95[3:2]=11,output is aux-ch_n0 register:: pin_share_ctrl01 0xff96 name bits read/ write reset state comments config ddcsda2 7:6 r/w 0x0 pin56 (64pin) (pad_ddcsda2) 00: ddcsda

01: mck 10: tcon11 11: aux-ch_n1 aud_houtl 5:4 r/w 0x0 pin26 (64pin) 00: audio (houtl) 01: tcon0 10: pwm0 aud_houtr 3 r/w 0x0 pin27-28 (64pin) 0: audio (houtr, ref) 1: tcon7, tcon5 ddcsda2 2:0 r/w 0x0 pin55 (64pin) (pad_ddcscl2) 000: ddcscl

001: sck 010: tcon8 011: aux-ch_p1 100: irq register:: pin_share _ctrl03 0xff97 name bits read/ write reset state comments config reserved 7:6 r/w 0x0 reserved to 0 spdif0 5:4 r/w 0x0 pin59 (64pin) (pad_spdif0) 00: tcon10 01: pwm1 10: sd0 11: spdif0 effectively only if crff96[7] = 1?b0 scl 3:2 r/w 0x0 pin42 (48pin) / pin54 (64pin) (pad_scl) 00: tcon13 01: pwm2 10: ws 11: spdif0 effectively only in 1-wire host interface condition cec 1:0 r/w 0x0 pin30 (64pin) (pad_cec) 00: cec 01: pwm1 10: tcon3 11: reserved register:: pin_driving_ctrl10 0xff98 name bits read/ write reset state comments config e2ctrl10_7 7 r/w 0 driving current control ? pin26~28 (64pin) 0: low 1: high e2ctrl10_6 6 r/w 0 reserved to 0 e2ctrl10_5_4 5:4 r/w 0x2 driving current control ? pin21~38 (48pin) / pin33~50 (64pin)
- ttl x0: 8ma x1: 12ma - lvds 00: 2.5ma 01: 3.0ma 10: 3.5ma 11: 4.0ma e2ctrl10_3 3 r/w 0 schmitt trigger control ? pin30 (64pin) 0: on 1: off reserved to 0 e2ctrl10_2 2 r/w 0 slew rate control ? pin30 (64p in) 0: fast 1: slow reserved to 0 e2ctrl10_1 1 r/w 0 driving current control ? pin30 (64pin) 0: low 1: high e2ctrl10_0 0 r/w 0 reserved to 0 register:: pin_driving_ctrl11 0xff99 name bits read/ write reset state comments config e2ctrl11_7 7 r/w 0 schmitt trigger control ? pin41~42 (48pin) / pin53~54 (64pin) 0: on 1: off e2ctrl11_6 6 r/w 0 slew rate control ? pin41~42 (48pin) / pin53~54 (64pin) 0: fast 1: slow e2ctrl11_5 5 r/w 0 driving current control ? pin41~42 (48pin) / pin53~54 (64pin) 0: low 1: high e2ctrl11_4 4 r/w 0 reserved to 0 e2ctrl11_3 3 r/w 0 schmitt trigger control ? pin55~56 (64pin) 0: on 1: off reserved to 0 e2ctrl11_2 2 r/w 0 slew rate control ? pin55~56 (64pin) 0: fast 1: slow reserved to 0 e2ctrl11_1 1 r/w 0 driving current control ? pin55~56 (64pin) 0: low 1: high e2ctrl11_0 0 r/w 0 reserved to 0 register:: pin_driving_ctrl12 0xff9a name bits read/ write reset state comments config e2ctrl12_7 7 r/w 0 schmitt trigger control ? pin43~44 (48pin) / pin57~58 (64pin) 0: on 1: off reserved to 0 e2ctrl12_6 6 r/w 0 slew rate control ? pin43~44 (48pin) /
pin57~58 (64pin) 0: fast 1: slow reserved to 0 e2ctrl12_5 5 r/w 0 driving current control ? pin43~44 (48pin) / pin57~58 (64pin) 0: low 1: high e2ctrl12_4 4 r/w 0 reserved to 0 e2ctrl12_3 3 r/w 0 schmitt trigger control ? pin59 (64pin) 0: on 1: off e2ctrl12_2 2 r/w 0 slew rate control ? pin59 (64pin) 0: fast 1: slow e2ctrl12_1 1 r/w 0 driving current control ? pin59 (64pin) 0: low 1: high e2ctrl12_0 0 r/w 0 reserved to 0 register:: pin_driving_ctrl13 0xff9b name bits read/ write reset state comments config e2ctrl13_7 7 r/w 0 schmitt trigger control ? sdr clk 0: on 1: off e2ctrl13_6 6 r/w 0 slew rate control ? sdr clk 0: fast 1: slow e2ctrl13_5 5 r/w 0 driving current control ? sdr clk 0: low 1: high e2ctrl13_4 4 r/w 0 reserved to 0 e2ctrl13_3 3 r/w 0 schmitt trigger control ? sdr control 0: on 1: off e2ctrl13_2 2 r/w 0 slew rate control ? sdr control 0: fast 1: slow e2ctrl13_1 1 r/w 0 driving current control ? sdr control 0: low 1: high e2ctrl13_0 0 r/w 0 reserved to 0 register:: pin_driving_ctrl14 0xff9c name bits read/ write reset state comments config e2ctrl14_7 7 r/w 0 schmitt trigger control ? dq31~24 (dq8~11) 0: on 1: off e2ctrl14_6 6 r/w 0 slew rate control ? dq31~24 (dq8~11) 0: fast 1: slow e2ctrl14_5 5 r/w 0 driving current control ? dq31~24 (dq8~11) 0: low 1: high e2ctrl14_4 4 r/w 0 reserved to 0 e2ctrl14_3 3 r/w 0 schmitt trigger control ? dq23~16 (dq4~7) 0: on
1: off e2ctrl14_2 2 r/w 0 slew rate control ? dq23~16 (dq4~7) 0: fast 1: slow e2ctrl14_1 1 r/w 0 driving current control ? dq23~16 (dq4~7) 0: low 1: high e2ctrl14_0 0 r/w 0 reserved to 0 register:: pin_driving_ctrl15 0xff9d name bits read/ write reset state comments config e2ctrl15_7 7 r/w 0 schmitt trigger control ? dq15~8 (dq12~15) 0: on 1: off e2ctrl15_6 6 r/w 0 slew rate control ? dq15~8 (dq12~15) 0: fast 1: slow e2ctrl15_5 5 r/w 0 driving current control? dq15~8 (dq12~15) 0: low 1: high e2ctrl15_4 4 r/w 0 reserved to 0 e2ctrl15_3 3 r/w 0 schmitt trigger control ? dq7~0 (dq0~3) 0: on 1: off e2ctrl15_2 2 r/w 0 slew rate control ? dq7~0 (dq0~3) 0: fast 1: slow e2ctrl15_1 1 r/w 0 driving current control ? dq7~0 (dq0~3) 0: low 1: high e2ctrl15_0 0 r/w 0 reserved to 0 register:: pin_driving_ctrl16 0xff9e name bits read/ write reset state comments config e2ctrl16_7 7 r/w 0 schmitt trigger control ? sdr address 0: on 1: off e2ctrl16_6 6 r/w 0 slew rate control ? sdr address 0: fast 1: slow e2ctrl16_5 5 r/w 0 driving current control ? sdr address 0: low 1: high e2ctrl16_4 4 r/w 0 reserved to 0 e2ctrl16_3 3 r/w 0 schmitt trigger control ? sdr dqm 0: on 1: off e2ctrl16_2 2 r/w 0 slew rate control ? sdr dqm 0: fast 1: slow e2ctrl16_1 1 r/w 0 driving current control ? sdr dqm 0: low 1: high e2ctrl16_0 0 r/w 0 reserved to 0
address: 0xff9f reserved to 0 cec function cec control register in cec function, write_reg pulses should have dista nces larger than 3 xtal clk period at least. register:: cec_cr_1 0xffaa name bits r/w default comments config reserved 7:5 -- -- ini_adr_sel 4 r/w 0 1:initial address change 0:use original address ini_adr 3:0 r/w 0x1 initial address when ini_adr_sel = 1 register::cec_cr0 0xffab name bits r/w default comments config cec_mode 7:6 r/w 0x0 00: disable cec module 01: enable cec normal operation 10: pad output test mode. 11: digital loopback, tx data will be loopback befo re pad . note. 1. as cec module is disabled, rx will not ack any transaction which destination address is the same with ceclocaddr or 0xf. test_mode_pad_data 5 r/w 0x1 0: cec pad output low 1: cec pad output high test_mode_pad_en 4 r/w 0x0 0 output high impedance 1 pad output enable this bit is active with cec_mode=10 only. logical_addr 3:0 r/w 0xf cec device logical (local) address register::cec_cr1 0xffac name bits r/w default comments config timer_div 7:0 r/w 0x14 dac enp(enable pulse) divides into timer enable pul se. and timer enable pulse is equal to input sample ena ble pulse. its default value is 0.8mhz divides into 20 to 40khz(25us). cec clock frequency is used for the bit timers in t he receiver and transmitter modes. register::cec_cr2 0xffad name bits r/w default comments config pre_div 7:0 r/w 0x21 divisor for cec dac clock busclk cecdiv ck_cec 162mhz 202 0.8019mhz
27mhz 33 0.8182mhz register::cec_cr3 0xffae name bits r/w default comments config unreg_ack_en 7 r/w 0x0 if rx logical addr = 0xf, wh en receiving a broadcast signal (destination addr = 0xf) 1 : respons e ack 2 : non to response ack pad_s_ctrl 6:5 r/w 0x1 cec pad current control of charge pump 00: 0.75 ua 01: 1 ua 10: 1.25 ua 11: 1.5 ua pad_delay 4:0 r/w 0x03 the delay from cec pad going high to being disable. delay: (1+cecpaddelay)*25us typical value: 01~03 (50us~100us) for normal mode only. register::cec_rt0 0xffaf name bits r/w default comments config cec_rt0_rsv 7:6 r/w 0x0 reserved register wt_cnt 5:0 r - retry wait time register::cec_rt1 0xffb0 name bits r/w default comments config cec_rt1_rsv 7:5 r/w 0x0 lattest 4 r - 1: the last initiator own cec bus is this device retry_no 3:0 r/w 0x5 maximum re-transmission times for a single frame, w hen device is a initiator and device detect low impedan ce error. in continue mode, retry is inactive. register::cec_rx0 0xffb1 name bits r/w default comments config rx_en 7 r - write 1 to enable rx as cec_enable=1 and cecrxen=0, rx will ack the transaction which destination address is the same w ith ceclocaddr or 0xf wclr_out rx_rst 6 r/w 0x0 write 1 to reset rx state and its fifo status after finishing each transaction, software should r eset rx part to clear cecrxeom, cecrxint and cecrxfifoov status bits. rx_continuous 5 r/w 0x0 0/1 normal mode / continuous mode in continuous mode, rxint will be set to 1 when rx receive new 8 bytes or eom. in normal mode, rxint will be set to 1 iff rx recei ve eom. rx_int_en 4 r/w 0x0 1 : cec rx interrupt enable if enabled, hardware will trigger interrupt per 8 b ytes received or eom init_addr 3:0 r - the latest initiator address (when device is a follower) register::cec_rx1 0xffb2 name bits r/w default comments config rx_eom 7 r - when eom is received, rxen will be res et to 0 and
rxint will be set to 1. rx_int 6 r - 1 : cec rx interrupt pending (write 1 to clear) wclr_out rx_fifo_ov 5 r - 1 : overflow status for cec 16-byt e fifo rx_fifo_cnt 4:0 r - the number of byte has been received by rx register::cec_tx0 0xffb3 name bits r/w default comments config tx_en 7 r - write 1 to enable tx transmission tx will detect signal free time, and then transmiss ion and re-try automatically. wclr_out tx_rst 6 r/w 0x0 write 1 to reset tx state and its fifo status after finishing each transaction, software should r eset tx part to clear cectxeom, cectxint and cectxfifoud status bits. tx_continuous 5 r/w 0x0 tx continuous mode 0: normal mode 1: continuous mode, software should clear this bit as the last byte is written into tx fifo to indicate t he end of transmitting data. tx_int_en 4 r/w 0x0 1 : cec tx interrupt enable if enabled, hardware will trigger interrupt per 8 b ytes transmitted or eom dest_addr 3:0 r/w 0x0 destination address (when device is a initi ator) register::cec_tx1 0xffb4 name bits r/w default comments config tx_eom 7 r - the transmission has ended. tx_int 6 r - 1 : cec tx interrupt pending (write 1 to clear) wclr_ou t tx_fifo_ud 5 r - 1 : underflow status for cec 16-by te tx fifo tx_fifo_cnt 4:0 r - the number of byte will been tr ansmitted by tx note : following table illustrates the status with the combination of cectxen, cectxeom, cectxint and cectxcontinue after transmitting. cectxen cectxeom cectxint cectxcontinue complete transmission incorrectly and not in continue mode 0 0 1 0 complete transmission correctly and not in continue mode 0 1 1 0 complete transmission incorrectly and in continue mode 0 0 1 0 transmitted 8 bytes correctly and still in continue mode, software should push data into tx fifo as necessary 1 0 1 1 complete transmission and in continue mode 0 1 1 0 (because software clear to 0 after pushing
remaining datum into tx fifo) tx fifo is underflow (in continue mode only) note : this is the same with cectxfifoud=1 0 0 1 1 register::cec_tx_fifo 0xffb5 name bits r/w default comments config tx_dat 7:0 r/w - tx fifo data output port rport wport register::cec_rx_fifo 0xffb6 name bits r/w default comments config rx_dat 7:0 r/w - rx fifo data input port rport wport register::cec_rx_start0 0xffb7 name bits r/w default comments config rx_start_low 7:0 r/w 0x8c minimum width (3.5ms) register::cec_rx_start1 0xffb8 name bits r/w default comments config rx_start_period 7:0 r/w 0xbc maximum width (4.7ms) register::cec_rx_data0 0xffb9 name bits r/w default comments config rx_data_sample 7:0 r/w 0x2a sample time (1.05ms) register::cec_rx_data1 0xffba name bits r/w default comments config rx_data_period 7:0 r/w 0x52, minimum data bit width (2.05ms) register::cec_tx_start0 0xffbb name bits r/w default comments config tx_start_low 7:0 r/w 0x94 3.7ms (0.025*148) register::cec_tx_start1 0xffbc name bits r/w default comments config tx_start_high 7:0 r/w 0x20 0.8ms (4.5ms ? 3.7ms) register::cec_tx_data0 0xffbd name bits r/w default comments config tx_data_low 7:0 r/w 0x18 0.6ms register::cec_tx_data1 0xffbe name bits r/w default comments config tx_data_01 7:0 r/w 0x24 0.9ms register::cec_tx_data2 0xffbf name bits r/w default comments config tx_data_high 7:0 r/w 0x24 0.9ms
register 3(page f) cec analog function register::aut_ok_control 0xffe7 name bits r/w default comments config cec27k_en 7 r/w 1 27k pull up resistor enable 0: disable 1: enable cec27k_autok 6 r/w 1 cec 27k pull up resistor auto calibration e nable 0: disable 1: enable cec_entst 5 r/w 0 cec debug enable 0: disable 1: enable cec27k_adjr 4:0 r/w 0x10 cec 27k pull up resistor hand mode setting: register::cec_analog_r 0xff e8 name bits r/w default comments config reserved 7 -- -- reserved to 0 cec_tst 6:1 r - cec block debug signal out cec_z0_ok 0 r - cec 27k calibration register:: rev_dummy rev_dummy rev_dummy rev_dummy4 44 4 0x 0x0x 0xff ffff ffe ee e9 99 9 name bits r/w default comments config rev_dummy4 7:0 r/w 00 dummy4
register::mcu_control 0xffed name bits r/w default comments config reserved 7:6 -- -- reserved flash_clk_div 5:2 r/w 2 spi-flash clock divider, its clock source is selected by mcu_clk_sel, default is mcu_clk_sel/2 mcu_clk_sel 1 r/w 0 cpu clock source select 0: cpu clock is from crystal divided by div 1: cpu clock is from pll divided by div reserved 0 -- -- reserved register::mcu_clock_control 0xffee name bits r/w default comments config reserved 7:6 -- -- rerserved mcu_clk_div 5:2 r/w 1 mcu clock is flash clock/mcu_clk_div. sof_rst 1 r/w 0 software reset mcu 0: no effect 1: reset rtd3580 rport wport sca_hrst 0 r/w 0 hardware reset for scalar 0: no effect 1: reset scalar module register::ram_test 0xffef name bits r/w default comments config reserved 7:4 -- 0 reserved ext_ram_bist 3 r/w 0 start bist function for mcu external ram (5 12 bytes) 0: finished and clear 1: start rport wport
ext_ram_sta 2 r 0 test result about mcu external ram 0: fail 1: ok reserved 1:0 -- 0 reserved
embedded osd addressing and accessing register address bit 7 6 5 4 3 2 1 0 high byte a15 a14 a13 a12 a11 a10 a9 a8 low byte a7 a6 a5 a4 a3 a2 a1 a0 figure 4. addressing and accessing registers date bit byte 0 d7 d6 d5 d4 d3 d2 d1 d0 byte 1 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 d7 d6 d5 d4 d3 d2 d1 d0 figure 2. data registers all kind of registers can be controlled and accesse d by these 2 bytes, and each address contains 3-byt e data, details are described as follows: write mode : [a15:a14] select which byte to write -00: byte 0 -01:byte 1 -10: byte 2 ?11: all *all data are sorted by these three bytes (byte0~byte2) [a13] auto load (double buffer) [a12] address indicator - 0: window and frame control registers. -1: font select and font map sram [a11:a0] address mapping - font select and font map sram address: 000~eff 3.75k*3byte -frame control register address: 000~0xx (latch) -window control register address: 100~1xx (latch) * selection of sram address or latch address select ion is determined by a12! example: bit [15:14]=00
-all data followed are written to byte0 and addre ss increases. byte0 byte0 byte0? (address will auto increase) bit [15:14] =01 -all data followed are written to byte1 and address increases. byte1 byte1 byte1? (address will auto increase) bit [15:14] =11 - address will be increased after each 3-byte data written. byte0 byte1 byte2 byte0 byte1 byte2? (address will auto increase) window control registers windows all support shadow/border/3d button window0, 5, 6, 7 support gradient functions. window 4, 5, 6, 7 start/end resolution are 1line(pi xel), window 0, 1, 2, 3 start/end resolution are 4line(pixel), all window start and end position include the special effect (border/shadow/3d button) been assigned font comes after windows by 10 pixels, so you shoul d compensate 10 pixels on windows to meet font position window 0 shadow/border/gradient address: 100h byte 0 bit mode function 7:6 -- reserved 5:3 w window 0 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 0 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thick ness byte 1 bit mode function 7:4 w window 0 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border col or 3:0 w window 0 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function
7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease 1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient
window 0 start position address: 101h byte 0 bit mode function 7:2 w window 0 horizontal start [5:0] 1 w window 0 horizontal start [11] pixel 0 w window 0 vertical start [11] line byte 1 bit mode function 7:5 w window 0 vertical start [2:0] line 4:0 w window 0 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 0 vertical start [10:3] line start position must be increments of four. window 0 end position address: 102h byte 0 bit mode function 7:2 w window 0 horizontal end [5:0] 1 w window 0 horizontal end [11] pixel 0 w window 0 vertical end [11] line byte 1 bit mode function 7:5 w window 0 vertical end [2:0] line 4:0 w window 0 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 0 vertical end [10:3] line end position must be increments of four. window 0 control address: 103h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved
6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 0 color index in 16-color lut byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable 1: enable 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 0 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 0 enable 0: disable 1: enable
window 1 shadow/border/gradient address: 104h byte 0 bit mode function 7:6 w reserved 5:3 w window 1 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 1 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thick ness byte 1 bit mode function 7:4 w window 1 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border col or 3:0 w window 1 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function 7:0 w reserved window 1 start position address: 105h byte 0 bit mode function 7:2 w window 1 horizontal start [5:0] 1 w window 1 horizontal start [11] pixel 0 w window 1 vertical start [11] line byte 1 bit mode function 7:5 w window 1 vertical start [2:0] line 4:0 w window 1 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 1 vertical start [10:3] line start position must be increments of four. window 1 end position address: 106h
byte 0 bit mode function 7:2 w window 1 horizontal end [5:0] 1 w window 1 horizontal end [11] pixel 0 w window 1 vertical end [11] line byte 1 bit mode function 7:5 w window 1 vertical end [2:0] line 4:0 w window 1 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 1 vertical end [10:3] line end position must be increments of four.
window 1 control address: 107h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 1 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 1 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 1 enable 0: disable 1: enable window 2 shadow/border/gradient address: 108h byte 0 bit mode function 7:6 w reserved 5:3 w window 2 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 2 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thick ness
byte 1 bit mode function 7:4 w window 2 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border col or 3:0 w window 2 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function 7:0 w reserved window 2 start position address: 109h byte 0 bit mode function 7:2 w window 2 horizontal start [5:0] 1 w window 2 horizontal start [11] pixel 0 w window 2 vertical start [11] line byte 1 bit mode function 7:5 w window 2 vertical start [2:0] line 4:0 w window 2 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 2 vertical start [10:3] line start position must be increments of four. window 2 end position address: 10ah byte 0 bit mode function 7:2 w window 2 horizontal end [5:0] 1 w window 2 horizontal end [11] pixel 0 w window 2 vertical end [11] line byte 1 bit mode function 7:5 w window 2 vertical end [2:0] line 4:0 w window 2 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 2 vertical end [10:3] line
end position must be increments of four. window 2 control address: 10bh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 2 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 2 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 2 enable 0: disable 1: enable window 3 shadow/border/gradient address: 10ch byte 0 bit mode function 7:6 w reserved 5:3 w window 3 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 3 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thick ness
byte 1 bit mode function 7:4 w window 3 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border col or 3:0 w window 3 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function 7:0 w reserved window 3 start position address: 10dh byte 0 bit mode function 7:2 w window 3 horizontal start [5:0] 1 w window 3 horizontal start [11] pixel 0 w window 3 vertical start [11] line byte 1 bit mode function 7:5 w window 3 vertical start [2:0] line 4:0 w window 3 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 3 vertical start [10:3] line start position must be increments of four. window 3 end position address: 10eh byte 0 bit mode function 7:2 w window 3 horizontal end [5:0] 1 w window 3 horizontal end [11] pixel 0 w window 3 vertical end [11] line byte 1 bit mode function 7:5 w window 3 vertical end [2:0] line 4:0 w window 3 horizontal end [10:6] pixel byte 2 bit mode function
7:0 w window 3 vertical end [10:3] line end position must be increments of four. window 3 control address: 10fh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 3 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 3 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 3 enable 0: disable 1: enable window 4 shadow/border/gradient address: 110h byte 0 bit mode function 7:6 w reserved 5:3 w window 4 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 4 shadow/border height in line unit 000~111: 1 ~ 8 line
it must be the same as bit[5:3] for 3d button thick ness byte 1 bit mode function 7:4 w window 4 shadow color index in 16-color lut for 3d window, it is the left-top/ bottom border co lor 3:0 w window 4 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function 7:0 w reserved window 4 start position address: 111h byte 0 bit mode function 7:2 w window 4 horizontal start [5:0] 1 w window 4 horizontal start [11] pixel 0 w window 4 vertical start [11] line byte 1 bit mode function 7:5 w window 4 vertical start [2:0] line 4:0 w window 4 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 4 vertical start [10:3] line window 4 end position address: 112h byte 0 bit mode function 7:2 w window 4 horizontal end [5:0] 1 w window 4 horizontal end [11] pixel 0 w window 4 vertical end [11] line byte 1 bit mode function 7:5 w window 4 vertical end [2:0] line 4:0 w window 4 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 4 vertical end [10:3] line
window 4 control address: 113h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 4 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 4 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 4 enable 0: disable 1: enable window 5 shadow/border/gradient address: 114h byte 0 bit mode function 7:6 w reserved 5:3 w window 5 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 5 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thick ness byte 1
bit mode function 7:4 w window 5 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border col or 3:0 w window 5 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function 7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease 1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient window 5 start position address: 115h byte 0 bit mode function 7:2 w window 5 horizontal start [5:0] 1 w window 5 horizontal start [11] pixel 0 w window 5 vertical start [11] line byte 1 bit mode function 7:5 w window 5 vertical start [2:0] line 4:0 w window 5 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 5 vertical start [10:3] line
window 5 end position address: 116h byte 0 bit mode function 7:2 w window 5 horizontal end [5:0] 1 w window 5 horizontal end [11] pixel 0 w window 5 vertical end [11] line byte 1 bit mode function 7:5 w window 5 vertical end [2:0] line 4:0 w window 5 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 5 vertical end [10:3] line window 5 control address: 117h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved 6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 5 color index in 16-color lut byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable
1: enable 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 5 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 5 enable 0: disable 1: enable window 6 shadow/border/gradient address: 118h byte 0 bit mode function 7:6 w reserved 5:3 w window 6 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 6 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thick ness ps: this is for non-rotary, rotate 270, rotate 90 a nd 180. byte 1 bit mode function 7:4 w window 6 shadow color index in 16-color lut for 3d window, it is the left-top/ bottom border co lor 3:0 w window 6 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function
7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease 1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient window 6 start position address: 119h byte 0 bit mode function 7:2 w window 6 horizontal start [5:0] 1 w window 6 horizontal start [11] pixel 0 w window 6 vertical start [11] line byte 1 bit mode function 7:5 w window 6 vertical start [2:0] line 4:0 w window 6 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 6 vertical start [10:3] line window 6 end position address: 11ah byte 0 bit mode function 7:2 w window 6 horizontal end [5:0] 1 w window 6 horizontal end [11] pixel
0 w window 6 vertical end [11] line byte 1 bit mode function 7:5 w window 6 vertical end [2:0] line 4:0 w window 6 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 6 vertical end [10:3] line window 6 control address: 11bh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved 6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 6 color index in 16-color lut byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable 1: enable 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 6 type
000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 6 enable 0: disable 1: enable window 7 shadow/border/gradient address: 11ch byte 0 bit mode function 7:6 w reserved 5:3 w window 7 shadow/border width or 3d button thi ckness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 7 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thick ness ps: this is for non-rotary, rotate 270, rotate 90 a nd 180. byte 1 bit mode function 7:4 w window 7 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border col or 3:0 w window 7 border color index in 16-color lut for 3d window, it is the right-bottom/top border co lor byte 2 bit mode function 7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease
1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient window 7 start position address: 11dh byte 0 bit mode function 7:2 w window 7 horizontal start [5:0] 1 w window 7 horizontal stat [11] pixel 0 w window 7 vertical start [11] line byte 1 bit mode function 7:5 w window 7 vertical start [2:0] line 4:0 w window 7 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 7 vertical start [10:3] line window 7 end position address: 11eh byte 0 bit mode function 7:2 w window 7 horizontal end [5:0] 1 w window 7 horizontal end [11] pixel 0 w window 7 vertical end [11] line byte 1 bit mode function 7:5 w window 7 vertical end [2:0] line 4:0 w window 7 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 7 vertical end [10:3] line
window 7 control address: 11fh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved 6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 7 color index in 16-color lut byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable 1: enable 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 7 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border
0 w window 7 enable 0: disable 1: enable
3d button type 1 3d button type 2
type 1 type 1 type 1 type 1 type 2 type 2 type 2 type 2 type 3 type 3 type 3 type 3 type 4 type 4 type 4 type 4 width height shadow in all direction osd appear range transparent start end window mask fade/in out function
frame control registers address: 000h byte 0 bit mode function 7:0 r/w vertical delay [10:3] the bits define the vertical starting address. tota l 2048 step unit: 1 line vertical delay minimum should set 1 byte 1 bit mode function 7:0 r/w horizontal delay [9:2] the bits define the horizontal starting address. to tal 1024 step unit:4 pixels horizontal delay minimum should set 2 byte 2 default: xxxx_xxx0b bit mode function 7:6 r/w horizontal delay bit [1:0] 5:3 r/w vertical delay [2:0] 2:1 r/w display zone, for smaller character width 00: middle 01: left 10: right 11: reserved 0 r/w osd enable 0: osd circuit is inactivated 1: osd circuit is activated when osd is disabled, double width (address 0x003 b yte1[1]) must be disabled to save power. these three bytes have their own double-buffer.
address 001h ~ address002h are reserved address: 003h byte 0 default: 00h bit mode function 7 r/w specific color blending (blending type 2) 0: disable 1: enable 6:5 r/w window 7special function 00: disable 01: blending (blending type 3) 10: window 7 mask region appear 11: window 7 mask region transparent 4 r/w osd vertical start input signal source select 0: select dvs as osd vsync input 1: select ena as osd vsync input 3:0 r/w blending color from 16-color lut (blending type 2) byte 1 default: 00h bit mode function 7:4 r/w char shadow/border color 3: 2 r/w alpha blending type (blending type 1) 00: disable alpha blending 01: only window blending 10: all blending 11: window and character background blending 1 r/w double width enable (for all osd including windows and characters) 0: normal 1: double 0 r/w double height enable (for all osd including windows and characters) 0: normal 1: double total blending area = blending type1 area + blendin g type 2 area + blending type 3 area byte 2 default: 00h bit mode function 7:6 r/w font downloaded swap control 0x: no swap 10: ccw 11: cw
5 r buffer empty 0: empty 1: not empty 4 r buffer valid 0: done 1: buffer is writing to sdram 3 r/w reset buffer write 1 to reset and auto-clear after finished. 2 r/w hardware rotation enable 0: disable 1: enable (default) osd compression function must be enabled simultaneo usly. 1 r/w global blinking enable 0: disable 1: enable 0 r/w rotation 0: normal (data latch 24 bit per 24 bit) 1: rotation (data latch 18 bit per 24 bit) bit 7 6 5 4 3 2 1 0 firmware a b c d e f g h cw a e b f c g d h ccw e a f b g c h d
figure 3 non-rotated memory alignments 23 6 figure 4 rotated memory alignments base address offset address: 004h byte 0 bit mode function 7:0 r/w font select base address[7:0] byte 1 bit mode function 7:4 r/w font select base address[11:8] 3:0 r/w font base address[3:0] byte 2 bit mode function 7:0 r/w font base address[11:4] when osd special function for pop-on is enabled (os d[008]), font select base address here will not be effective. 23~12 bit(high) 11~0 bit(low)
osd compression address: 005h byte 0 bit mode function 7:4 r/w 4-bit value for vlc code 0 3:0 r/w 4-bit value for vlc code 100 byte 1 bit mode function 7:4 r/w 4-bit value for vlc code 1010 3:0 r/w 4-bit value for vlc code 1011 byte 2 bit mode function 7:4 r/w 4-bit value for vlc code 1100 3:0 r/w 4-bit value for vlc code 1101 0 address: 006h byte 0 bit mode function 7:4 r/w 4-bit value for vlc code 1101 1 3:0 r/w 4-bit value for vlc code 1110 0 byte 1 bit mode function 7:4 r/w 4-bit value for vlc code 1110 10 3:0 r/w 4-bit value for vlc code 1110 11 byte 2 bit mode function 7:4 r/w 4-bit value for vlc code 1111 00 3:0 r/w 4-bit value for vlc code 1111 01 address: 007h byte 0 bit mode function 7:4 r/w 4-bit value for vlc code 1111 100 3:0 r/w 4-bit value for vlc code 1111 101 byte 1 bit mode function 7:4 r/w 4-bit value for vlc code 1111 110 3:0 r/w 4-bit value for vlc code 1111 1110
byte 2 default: xxxx_xxx0b bit mode function 7:1 -- reserved 0 r/w osd compression (4bit/symbol, vlc code 1111_1111 re presents the end of data) (only for sram) 0: disable 1: enable note: 1. if enable osd compression or auto load (double buff er), only one byte can be read after writing addres s at 0x90, 0x91. 2. for osd compression, msb 4 bits of original byte is first transferred to corresponding vlc code, and t hen lsb 4 bits is transferred. vlc code is placed from lsb to msb of compression font. for example, 4-bit valu e for vlc code 1100 is 4?b0101, and 4-bit value for vlc c ode 100 is 4?b0001. original data 0x15 is transferr ed to compression x0011001. 3. osd double buffer and compression can?t be enabled simultaneous. 4. when power-down mode or lack of crystal clock, osd compression font can?t be write. 5. after osd enable, it is better to delay 1 dvs to st art writing osd compression data. osd special function address: 008h byte 0 default: 0x00 bit mode function 7 r/w osd special function enable 0: disable 1: enable 6 r/w osd special function select (effective only when bi t[7]=1) 0: roll-up 1: pop-on 5 r/w osd vertical boundary function enable 0: disable 1: enable 4:1 r/w reserved to 0 0 r/w display base select (effective only when bit[7:6]=1 1`b) 0: base 0 1: base 1 byte 1 default: 0x00 bit mode function 7:0 r/w row command base 0 [7:0] byte 2 default: 0x00
bit mode function 7:0 r/w row command base 1 [7:0] address: 009h byte 0 default: 0x00 bit mode function 7:4 r/w font select base 0 [11:8] 3:0 r/w font select base 1 [11:8] byte 1 default: 0x00 bit mode function 7:0 r/w font select base 0 [7:0] byte 2 default: 0x00 bit mode function 7:0 r/w font select base 1 [7:0] (not effective when roll-u p) address: 00ah byte 0 default: 0x00 bit mode function 7 r/w reserved 6:4 r/w osd vertical upper boundary [10:8] 3 r/w reserved 2:0 r/w osd vertical lower boundary [10:8] byte 1 default: 0x00 bit mode function 7:0 r/w osd vertical upper boundary [7:0] byte 2 default: 0x00 bit mode function 7:0 r/w osd vertical lower boundary [7:0] address: 00bh byte 0 default: 0x00 bit mode function 7 r/w font base address[12] 6 r/w window 6 special blending function 0: off 1: on 5:4 r/w blending type of window 7 00: no blending for both f/b 01: only blending for foreground 10: only blending for background 11: both blending for f/b
3:2 r/w blending type of window 6 00: no blending for both f/b 01: only blending for foreground 10: only blending for background 11: both blending for f/b 2:0 -- reserved byte 1 default: 0x00 bit mode function 7:0 -- reserved byte 2 default: 0x00 bit mode function 7:0 -- reserved note: 1. when osd special function for pop-on is enabled, fo nt select base address in osd[004] will not be effe ctive anymore. 2. when osd vertical boundary function is enabled, osd image above upper boundary and below lower boundar y will be invisible. 3. when roll-up function is enabled, osd will always s tart from the row-command pointed by base0, and aft er the row-command pointed by base1 has been dealt wit h, the next row-command will be the first one in os d sram. row-command processing will terminate in the row-command before the one pointed by base0. (for example, r1 is pointed by base0, and r5 is pointed by base1. osd will show r1 as the first row, follow ed by r2, r3, r4, r5, and r0 as last row.) 4. when pop-on function is enabled, osd will start fro m the row command pointed by the base selected as display base(selected by osd[008][0.0]), and termin ate when end-command is encountered. that is, all row-command will be separated into two non-overlay subset which is enclosed by the row-command pointed by base and end-command. osd sram (map and font registers) r0 r1 r2 ?. rn end c01 c02 b03 c04 ? c11 c12 c13 ? ? ? ? cn1 cn2 ? 1-bit font start ? ? ? 2-bit font start ?
? 4-bit font start ? ? ? 16.5k bytes sram 1. row command r0 r1 r2 r3 r?. rn end row command r0~rn represent the start of new row. each command contains 3 bytes data which define the length of a row and other attributes. osd end command repr esent the end of osd. r0 is set in address 0 of sra m. 2. character/blank command (font select) character command is used to select which character font is show. each command contains three bytes wh ich specify its attribute and 1,2 or 4bit per pixel. bl ank command represents blank pixel to separate the preceding character and following character. use two or more blank command if the character distance exceeds 255 pixel. the font select base address in frame control regis ter represents the address of the first character i n row 0, that is, c01 in the above figure. the following characte r/blank is write in the next address. c11 represent s the first character in row1, c12 represents the second charac ter in row1, and so on. the address of the first character cn1 in row n = f ont select base address + row 0 font base length + row 1 font base length + ?+row n-1 font base length.
3. font user fonts are stored as bit map data. for normal f ont, one font has 12x18 pixel, and for rotation fon t, one has 18x12 pixel. one pixel use 1, 2 or 4 bits. for 12x18 font, one 1-bit font requires 9 * 24bit sram one 2-bit font requires 18 * 24bit sram one 4-bit font requires 36 * 24bit sram for 18x12 font, one 1-bit font requires 12 * 24bit sram one 2-bit font requires 24 * 24bit sram one 4-bit font requires 48 * 24bit sram font base address in frame control register point t o the start of 1-bit font. for normal (12x18) font: 1-bit font, if cs = 128, real address of font = fon t base address + 9 * 128 2-bit font, if cs = 128, real address of font = font base address + 18 * 128 4-bit font, if cs = 128, real address of font = font base address + 36 * 128 for rotational (18x12) font: 1-bit font, if cs = 128, real address of font = fon t base address + 12 * 128 2-bit font, if cs = 128, real address of font = font base address + 24 * 128 4-bit font, if cs = 128, real address of font = font base address + 48 * 128 where cs is character selector in character comm and. note that row command, font select and font share t he same osd sram. when we download the font, we have to set the frame control 002h byte1 [1:0] to set the method of hard ware bit swap. if the osd is counter-clock-wise rotated, we have to set to 0x01 (the 8 bits of every byte of fo nt sram downloaded by firmware will be in a sequence of ?7 5 3 1 6 4 2 0? (from msb to lsb) and should be rea rranged to ?7 6 5 4 3 2 1 0? by hardware). if it is clock-wise rotated, we have to set to 0x10 (the 8 bits of eve ry byte of font sram downloaded by firmware will be in a sequence o f ?6 4 2 0 7 5 3 1? (from msb to lsb) and should b e rearranged to ?7 6 5 4 3 2 1 0? by hardware). after we finish the downloading or if we don?t have to r otate the osd, we have to set it to 0x00 .
row command byte 0 bit mode function 7 w 1: row start command 0: osd end command each row must start with row-command, last word of osd map must be end-command 6 r/w vbi osd function enable 0: normal osd function as usual 1: support vbi osd functions like underline, b/f se parated blink and 512 fonts select 5 w reserved 4:2 w character border/shadow 000: none 001: border 100: shadow (left-top) 101: shadow (left-bottom) 110: shadow (right-top) 111: shadow (right-bottom) 1 w double character width 0: x1 1: x2 0 w double character height 0: x1 1: x2 byte 1 bit mode function 7:3 w row height (1~32) 2:0 w column space 0~7 pixel column space when char is doubled, so is column space. notice: when character height/width is doubled, the row hei ght/column space definition also twice. if the row height is larger than character height, the eff ect is just like space between rows. if it is small er than character height, it will drop last several bo ttom line of character. when using 1/2/4lut font, column space and font sma ller than row height, the color of column space and row space is the same as font background color, only 4 bit true color font mode, the
color is transparent 12 25 a 1/2/4lut bg color the same as character background ,4 true color mode, bg color is transparent row space color column space color byte 2 bit mode function 7:0 w row length unit: font base character command (for blank) byte 0 bit mode function 7 w 0 6 w blinking effect 0: disable 1: enable 5:0 w reserved byte 1 bit mode function 7:0 w blank pixel length at least 3 pixels, and can?t exceed 255 pixels. byte 2 bit mode function 7:5 w reserved 4 w reserved 3:0 w blank color ? select one of 16-color lut
(0 is special for transparent) character command (for 1-bit ram font) byte 0 bit mode function 7 w 1 6 w character blinking effect 0: disable 1: enable 5:4 w 00 (font type 00: 1-bit ram font 01: 4-bit ram font 1x: 2-bit ram font) 3:0 w vbi osd disable: character width (only for 1-pixel font, doubled whe n specifying double-width in row/blank command register) for 12x18 font: 0100: 4-pixel 0101: 5-pixel 0110: 6-pixel 0111: 7-pixel 1000: 8-pixel 1001: 9-pixel 1010: 10-pixel 1011 :11-pixel 1100: 12-pixel for 18x12 font (rotated) 0000: 4-pixel 0001: 5-pixel 0010: 6-pixel 0011: 7-pixel 0100: 8-pixel 0101: 9-pixel 0110: 10-pixel 0111: 11-pixel 1000: 12-pixel 1001:13-pixel 1010:14-pixel 1011:15- pixel 1100: 16-pixel 1101:17-pixel 1110:18-pixel vbi osd enable: while vbi osd enable, 1 bit font will be no rotated and 12-pixel fonts always. then the [3:0] setting will be as following : [3]: character select[8] support 512 font while vbi osd enable [2]: additional blinking effect {[6], [2]} 00: no blink for both f/b 01: only blink for foreground 10: only blink for background 11: both blink for f/b [1]: underline enable
underline will be at 17th & 18th line and got the s ame color with foreground [0]: reserved when using border/shadow/ effect, the width of the 1-bit font should at least 6 pixel. byte 1 bit mode function 7:0 w character select [7:0] byte 2 bit mode function 7:4 w foreground color select one of 16-color from color lut 3:0 w background color select one of 16-color from color lut (0 is special for transparent) character command (for 2-bit ram font) byte 0 bit mode function 7 w 1 6 w msb of foreground color 11, background 00 5 w 1 4 w msb of foreground color 10, foreground 01 3:1 w foreground color 11 select one of 8 color from color lut add byte0 [6] as msb for 16-color lut. 0 w background color 00 bit[2] select one of 8 color from color lut byte 1 bit mode function 7:0 w character select [7:0] byte 2 bit mode function 7:6 w background color 00 bit[1:0] select one of 8 color from color lut while 0 is special for transparent add byte0 [6] as msb for 16-color lut. once we fill 0000 or 1000(msb follow byte0[6]), bg appears transparent. 5:3 w foreground color 10
select one of 8 color from color lut add byte0 [4] as msb for 16-color lut. 2:0 w foreground color 01 select one of 8 color from color lut add byte0 [4] as msb for 16-color lut. character command (for 4-bit ram font) byte 0 bit mode function 7 w 1 6 w character blinking effect 0: disable 1: enable 5:4 w 01 (font type 00: 1-bit ram font 01: 4-bit ram font 1x: 2-bit ram font) 3:0 w (for byte1[7] = 0) select one color from 16-color lut as background (for byte1[7] = 1) red color level msb 4 bits for 8 bits color level (lsb 4 bits are 1 111) byte 1 bit mode function 7 w 0: 4bit look up table, 0000?b is transparent. 1: 3bit specify r,g,b pattern, color level defined in byte0[3:0],byte2. one mask bit defines foreground or background. 6:0 w character select [6:0] when 4-bit look-up table mode color of column space is the same as background. when 4-bit look-up table mode and pixel value is 00 00, and byte0[3:0]=0000 means transparent. when true color mode and pixel value is 0000 it is transparent byte 2 bit mode function 7:4 w (for byte1[7] = 1) green color level msb 4 bits for 8 bits color level (lsb 4 bits are 1 111)
3:0 w (for byte1[7] = 1) blue color level msb 4 bits for 8 bits color level (lsb 4 bits are 1 111)
t window 0 window 1 window 2 window 3 window 4 window 5 a window 7 window 6 display priority we have four windows with gradient and four windows without gradient, the window priority is as above, character should be always on the top lay er of the window. pattern gen. use osd to replace display pattern generator. chess board : make a font as below if we want to fill to the full 1280x1024 screen wit h character, we need 1280*1024 pixels. required character is: using 12*18 font 1280/12 = 106.7 -> 107 1024/18 = 56.9 -> 57 107*57 = 6099 character the required number of character map is larger than ram size. we must turn on double width
or double height function to reduce the half of cha racter map. so the basic unit to chessboard is 2x2 pixel. you c an use larger chessboard instead of 2x2 pixels unit, such as 4x4 and so on. gray level we can display 256 gray level by gradient window, 8 and 16 gray level by character map. 32 and 64 gray level is not supported.

4. electric specification dc characteristics table 3 absolute maximum ratings parameter symbol min typ max units voltage on input (5v tolerant) v in -1 5 v supply voltage pvcc 3.0 3.3 3.6 v supply voltage vcck 1.08 1.2 1.32 v electrostatic discharge v esd 2.5 kv latch-up i la 100 ma ambient operating temperature t a 0 70 oc storage temperature (plastic) t stg -55 125 oc thermal resistance (junction to air) ja 47.4 oc/w junction acceptable temperature t j 125 oc under 2-layer pcb dimension 50 x 70 mm, thickness: 1.6mm top layer: 65% coverage of cu, 0.5oz thickness bottom layer: 95% coverage of cu, 0.5oz thickness via underneath package: 12 (diameter: 12 mil)
5. mechanical specification plastic quad flat no-lead package 48 leads 7x7mm 2 outline
dimension in mm dimension in inch symbol min nom max min nom max a 0.75 0.85 1.00 0.030 0.034 0.039 a 1 0.00 0.02 0.05 0.000 0.001 0.002 a 2 0.55 0.65 0.80 0.022 0.026 0.032 a 3 0.20 ref 0.008 ref b 0.18 0.25 0.30 0.007 0.010 0.012 d/e 7.00bsc 0.276bsc d 1 /e 1 6.75bsc 0.266bsc d 2 /e 2 4.80 5.05 5.30 0.189 0.199 0.209 e 0.50bsc 0.020bsc l 0.30 0.40 0.50 0.012 0.016 0.020 0 o 14 o 0 o 14 o aaa 0.15 0.006 bbb 0.10 0.004 ccc 0.10 0.004 ddd 0.05 0.002 eee 0.08 0.003 fff 0.10 0.004 notes 1. dimensions d1 and e1 do not include mold protrusion . 2. controlling dimension millimeter(mm). 3. reference documentl jedec mo-220.
6. ordering information part adc dvi od resolution output pkg rtd2525lrh 210m y y 1440x900 lvds qfn48 rtd2545lrh 210m y y 1680x1050 lvds qfn48 RTD2555LRH 210m y y 1920x1050 lvds qfn48

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