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1 ? fn6570.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. isl97636 8-channel led driver the isl97636 is an integrat ed power led driver that controls 8 channels of led current for lcd backlight applications. the isl97636 is cap able of driving typically 72 (8x9) pieces of 3.5v/30ma or 80 (8x10) pieces of 3.2v/20ma leds. the isl97636? s contains 8 channels of voltage controlled cu rrent sources with typical currents matching of 1%, which compensate for the non-uniformity effect of forward voltages variance in the led stacks. to minimize the voltage headroom and power loss in the typical multi-strings operation, the isl97636 features a dynamic headroom control that monitors the highest led forward voltage string and uses its feedback signal for output regulation. the led brightness can be pulse width modulated with an applied pwm signal from dc to audio noise free 20khz. the isl97636 features extensiv e protection functions that include string open and short circuit detections, ovp, otp, thermal shutdown and an optional input overcurrent protection with master fault disconnect switch. available in the 24 ld 4mmx4mm qfn, the isl97636 operates from -40c to +85c wi th input voltage ranges from 6v to 24v for high leds count applications. features ? 8 channels ? 6v to 24v input ? 34.5v output max ? drive maximally 72 (3.5v/30ma each) or 80 (3.2v/20ma each) leds ? current matching 1% typ ? dynamic headroom control ? pwm signal up to 20khz dimming ? protections - string open circuit detection - string short circuit detection with selectable thresholds - over-temperat ure protection - overvoltage protection - optional input overcurrent protection w/disconnect sw ? 1.2mhz switching frequency ? 24 ld 4mmx4mm qfn package ? pb-free (rohs compliant) applications ? notebook displays led backlighting ? lcd monitor led backlighting ? automotive displays led backlighting ? automotive or traffic lighting ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL97636IRZ* 976 36irz 24 ld 4x4 qfn l24.4x4d *add ?-t? or ?-tk? suffix for tape and reel. please refer to tb347 for details on reel specifications note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant an d compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet may 9, 2008
2 fn6570.0 may 9, 2008 typical application circuit 7 vbl+ = 6v to 24v pwmi/en comp vin fault ovp pgnd rset v out = 34.5v, 30ma per string vdc lx iin0 iin3 iin2 iin4 iin5 23 24 6 11 9 10 12 17 13 14 15 16 19 21 22 lx 20 pgnd 18 gnd 5 isl97636 iin1 8 iin6 iin7 isl97636
3 fn6570.0 may 9, 2008 block diagram figure 1. isl97636 block diagram 34.5v, 30ma per string (8 x 9 = 72 leds) generator vin comp + - + - iin0 iin7 vbl+ = 6v to 24v fet driver reg lx isl97636 ramp comp imax ilimit pwm/oc/sc highest vf string detect vdc sensor pgnd fault + - gnd reference vin gm amp + - + - iin0 logic ovp lx osc and = 0 oc, sc detect fault detect fault detect temp fault/detect pwmi/en rset + oc, sc detect pwm generator o/p short fault detect isl97636
4 fn6570.0 may 9, 2008 absolute maxi mum ratings (t a = +25c) thermal information vin, fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 24v vdc, comp, rset, en/pwm . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v ovp, iin0 - iin7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 36v pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above voltage ratings are all with respect to gnd pin operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . 39 2 thermal characterization (typical, note 3) psi jt (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~0.7 maximum continuous junction temperature . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside assumed under ideal case temperature . 3. psi jt is the junction-to-top thermal resistance. if the package top te mperature can be measured, with this rating then the die junct ion temperature can be estimated more accurately than the jc and jc thermal resistance ratings. 4. limits established by characteri zation and are not production tested. electrical specifications all specifications below are tested at t a = -40c to +85c; v in = 12v, en = 5v, r set = 36.6k ; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterizati on and are not production tested. parameter description condition min typ max unit general vin backlight supply voltage 9 leds per channel (3.5v/30ma type) 624v ivin_stby vin shutdown current 5a v out output voltage 34.5 v vuvlo undervoltage lockout threshold 2.45 2.8 v vuvlo_hys undervoltage lockout hysteresis 300 mv ss soft-start 1ms pwm generator en/pwm en/pwm voltage range 2.7 5.5 v enmin minimum enable signal 40 s tmax_pwm_off maximum pwmi off time before shutdown en/pwmi toggles 28 ms regulator vdc ldo output voltage v in > 6v 5.0 5.5 v ivdc_stby standby current en/pwm = 0v 20 a ivdc active current en/pwm = 5v 10 ma vldo vdc ldo dropout voltage v in > 5.5v, 30ma 30 200 mv boost swilimit boost fet current limit t a = +25c 2.3 3.2 a t a = -40c, +85c 2.2 a r ds(on) internal boost switch on-resistance 130 260 m isl97636
5 fn6570.0 may 9, 2008 eff_peak peak efficiency vin = 18v, 72 leds, 20ma each, l = 8.2h with dcr 106m , t a = +25c 91 % vin = 12v, 72 leds, 20ma each, l = 8.2h with dcr 106m , t a = +25c 90 % vin = 6v, 72 leds, 20ma each, l = 8.2h with dcr 106m , t a = +25c 86 % i out / v in line regulation 0.1 % dmax boost maximum duty cycle 82 % dmin boost minimum duty cycle 7 % f s switching frequency 1.0 1.2 1.3 mhz ilx_leakage lx leakage current vlx = 36v, en = 0 10 a reference imatch channel-to-channel current matching i out = 30ma -3.5 1 +3.5 % i acc current accuracy 3 % fault detection vsc short circuit threshold pwm dimming = 100% 7.8 8 8.8 v vtemp_acc over-temperature threshold accuracy 5 c vovplo overvoltage limit on ovp pin 1.17 1.2 1.23 v ovphys ovp hysteresis 20 mv ovpfault ovp short detection fault level 300 mv current sources v headroom dominant channel current source headroom at iin pin i led = 20ma t a = +25 c 100 mv v rset voltage at rset pin r set = 36.6k 680 700 720 mv iledmax maximum led current per channel r set = 20.9k 35 ma fault pin ifault fault pull-down current v in = 12v 101830a vfault fault clamp voltage with respect to v in v in = 12, v in - vfault 7.5 v ilxstartup lx start-up current vdc = 5.2v 1 2.7 7 ma electrical specifications all specifications below are tested at t a = -40c to +85c; v in = 12v, en = 5v, r set = 36.6k ; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterizati on and are not production tested. (continued) parameter description condition min typ max unit isl97636
6 fn6570.0 may 9, 2008 typical performance curves figure 2. efficiency, l = 8.2h with dcr = 106m , c o = 4x4.7f/50v figure 3. efficiency, l = 10h with dcr = 129m , c o = 4x4.7f/50v figure 4. 3 efficiency, l = 10h with dcr = 500m , 1mm, c o = 4x4.7f/50v figure 5. current regulation figure 6. channel-to-channel current matching fig ure 7. current matching vs duty cycle vs dimming frequency 66 68 70 72 74 76 78 80 82 84 86 88 90 92 0 20 40 60 80 100 120 140 160 180 i o (ma) efficiency (%) l = 8.2h ihlp-2525bd-01 dcr = 106m i sat = 3a 9s8p - 6v 9s6p - 6v 7s8p - 6v 7s6p - 6v 9s6p - 12v 7s8p - 18v 9s6p - 18v 7s8p - 6v 9s8p - 12v 7s6p - 12v 7s8p - 12v 7s6p - 18v 9s8p - 18v 66 68 70 72 74 76 78 80 82 84 86 88 90 92 0 20 40 60 80 100 120 140 160 180 efficiency (%) i o (ma) 7s8p - 6v 7s6p - 6v 9s6p - 12v 7s8p - 6v 9s8p - 12v 7s6p - 12v 7s8p - 12v 9s8p - 18v 9s8p - 6v 9s6p - 6v 9s6p - 18v 7s8p - 18v 7s6p - 18v l = 10h ihlp-2525bd-01 dcr = 129m i sat = 2.5a 66 68 70 72 74 76 78 80 82 84 86 88 90 92 0 20 40 60 80 100 120 140 160 180 i o (ma) efficiency (%) 9s8p - 6v 9s6p - 6v 7s8p - 6v 7s6p - 6v 9s6p - 12v 9s6p - 18v 7s8p - 6v 9s8p - 12v 7s6p - 12v 7s8p - 12v 7s8p - 18v 9s8p - 18v 7s6p - 18v l = 10h dcr = ~500m <1mm height -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 4 6 8 10 12 14 16 18 20 22 24 26 v in (v) current variation (%) 20ma -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 channels current matching (%) 6v/1ma 6v/20ma 12v/1ma 12v/20ma 0.5 0.6 0.7 0.8 0.9 1.0 0 102030405060708090100 pwm duty cycle (%) current matching (%) v in = 12v 10khz 1khz 100khz 200khz 20khz isl97636
7 fn6570.0 may 9, 2008 figure 8. pwm dimming linearity figure 9. lx, viin, il and i o at pwm dimming (54 leds, 20ma, v in = 12v) figure 10. i l at 50% pwm dimming (54leds, 20ma, v in = 12v, l = 8.2h) figure 11. i l zoom in at pwm dimming zoom in (54 leds, 20ma, v in = 12v, l = 8.2h) figure 12. i led at 50% pwm dimming (54 leds, 20ma, v in = 12v) figure 13. lx at 50% pwm dimming (54 leds, 20ma, v in = 12v) typical performance curves (continued) 0 20 40 60 80 100 120 140 160 180 0 102030405060708090100 pwm duty cycle (%) total output current (ma) 8 channels 9 leds per channel v in = 18v v in = 6v v in = 12v isl97636
8 fn6570.0 may 9, 2008 figure 14. lx zoom in at 50% dimming (54 leds, 20ma, v in = 12v) figure 15. ripple voltage (54 leds, v in = 12v, 20ma each, c out = 4x4.7f/50v) figure 16. ripple voltage zoom in (54 leds, v in = 12v, 20ma each, c out = 4x4.7f/50v) typical performance curves (continued) isl97636
9 fn6570.0 may 9, 2008 pinout isl97636 (24 ld qfn) top view vdc vin comp fault lx lx iin7 iin6 iin5 iin4 rset iin3 gnd gnd fpwm vlevel gnd pwmi/en pgnd pgnd ovp iin0 iin1 iin2 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 pin descriptions (i = input, o = output, s = supply) pin name type description 1, 2 gnd s analog gnd 3 fpwm - not used. leave floating and connect any thing will have no effect on operation. 4 vlevel - not used. leave floating and connect anything will have no effect on operation. 5 gnd s analog gnd and led power return 6 en/pwmi i dual functions: enable pin and pwm brightness control pin. do not leave en/pwmi floating. the device needs 40s for initial power-up enable, then this pin can be applie d with a pwm signal with off time no longer than 28ms. 7 iin7 i input 7 to current source, fb, and monitoring 8 iin6 i input 6 to current source, fb, and monitoring 9 iin5 i input 5 to current source, fb, and monitoring 10 iin4 i input 4 to current source, fb, and monitoring 11 rset i resistor connection for setting led curren t, (see equation 1 for calculating the iledpeak) 12 iin3 i input 3 to current source, fb, and monitoring 13 iin2 i input 2 to current source, fb, and monitoring 14 iin1 i input 1 to current source, fb, and monitoring 15 iin0 i input 0 to current source, fb, and monitoring 16 ovp i overvoltage protection input 17 pgnd s power ground (lx power return) 18 pgnd s power ground (lx power return) 19 lx i input to boost switch 20 lx i input to boost switch 21 fault o fault disconnect switch 22 comp o boost compensation pin 23 vin s input voltage for the device and led power 24 vdc s de-couple capacitor for internally generated supply rail. if 2.7v < vbl+ < 5.5v, apply vdc di rectly with a supply voltage of 2.7v to 5.5v isl97636
10 fn6570.0 may 9, 2008 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the isl97636 employes current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly changed to an ac/dc adapter without rendering a noticeable visual nuisance. the number of leds that can be driven by isl97636 depends on the type of led chosen in the application. the isl97636 is capable of boosting up to 34.5v and typically driving 9 leds in series for each of the 8 channels, enabling a total of 72 pieces of the 3.5v/30ma type of leds. enable and pwmi the en/pwmi pin serves dual purposes; it is used as an enable signal and can be used for pwm input signal for dimming. if a pwm signal is applied to this pin, the first pulse of minimum 40s will be used as an enable signal. if there is no signal for longer than 28ms, the device will enter shutdown. the en/pwmi pin cannot be floating, thus a 10k pull-down resistor may need to be added. current matching and current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 17. the led peak current is set by translating the r set current to the output with a scaling factor of 733/r set . the source terminals of the current source mosfets are designed as 100mv to minimize the power lo ss. the sources of errors of the channel-to-channel current matching come from the op amp?s offset, internal layout and reference and these parameters are optimized for current matching and absolute current accuracy. the absolute accuracy is also determined by the external r set , and therefore a 1% tolerance resistor should be used. dynamic headroom control the isl97636 features a proprietary dynamic headroom control circuit that detects the highest forward voltage string or effectively the lowest volt age from any of the iin pins. when this lowest i in voltage is lower than the short circuit threshold, v sc , such voltage will be used as the feedback signal for the boost regulator. the boost makes the output to the correct level such that the lo west iin pin is at the target headroom voltage. since all led stacks are connected to the same output voltage, the other iin pins will have a higher voltage, but the regulated cu rrent source circuit on each channel will ensure that each channel has the same current. the output voltage will regulate cycle by cycle and it is always referenced to the highest forward voltage string in the architecture. dimming controls the isl97636 allows two wa ys of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment 2. pwm chopping of the led current defined in step 1. maximum dc current setting the initial brightness should be set by choosing an appropriate value for r set . this should be chosen to fix the maximum possible led current: dc current adjustment r set can be a dcp (digitally controlled potentiometer) for dc current adjustment but minimum resistance should not be lower than 21k for a maximum of 35ma. figure 17. simplified current source circuit ref + - + - pwm dimming rset + ref + - + - rset - i ledmax 733 r set --------------- = (eq. 1) isl97636
11 fn6570.0 may 9, 2008 for example, if the maximum required led current (i led(max) ) is 20ma, rearranging equation 1 yields equation 3: pwm current control the average led current of each channel can be controlled by an external pwmi signal, as shown in equation 3: the pwm dimming frequency can be, for example, 20khz, but there are minimum on and off time requirements such that the dimming will be in the range of 10% to 99.5%. if the dimming frequency is below 5khz, the dimming range can be 1% to 99.5%. the pwm dimming off time cannot be longer than 28ms or else the driver will enter shutdown. 5v low dropout regulator a 5.2v ldo regulator is present at the vdc pin to develop the necessary low voltage supply which is used by the chips internal control circuitry. because vdc is an ldo pin, it requires a bypass capacitor of 1f or more for the regulation. for applications with an input voltage 5.5v, the vin and vdc pins can be connected together. the vdc pin can be used as a coarse reference with few ma sourcing capability. inrush control and soft-start the isl97636 has separately built-in independent inrush control and soft-start functions. the inrush control function is built around the short circuit protection fet, and is only available in applications which include this device. at start-up, the fault protection fet is turned on slowly due to a 30a pull-down current output from the fault pin. this discharges the fault fet's gate-source capacitance, turning on the fet in a controlled fashion. as this happens, the output capacitor is charged slowly through the weakly turned on fet before it becomes fully enhanced. this results in a low inrush current. this current can be further reduced by adding a capacitor (in the 1nf to 5nf range) across the gate source terminals of the fet. once the chip detects that the fault protection fet is turned on hard, it is assumed that inrush is complete. at this point, the boost regulator will begin to switch and the current in the inductor will ramp-up. the current in the boost power switch is monitored and the switching terminated in any cycle where the current exceeds the current limit. the isl97636 includes a soft-start feature where this current limit starts at a low value (375ma). this is step ped up to the final 3a current limit in seven further steps of 375ma. these steps will happen over a 1ms total time, such that after 1ms the final limit will be reached. this allows the output capacitor to be charged to the required val ue at a low current limit and prevents high input current fo r systems that have only a low to medium output current requirement. for systems with no ma ster fault protection fet, the inrush current will flow towards c out when vin is applied and it is determined by the ramp rate of vin and the values of c out and l. fault protection and monitoring the isl97636 features extensiv e protection functions to cover all the perceivable failure conditions. the failure mode of a led can be either open circuit or as a short. the behavior of an open circuited led can additionally take the form of either infinite resistance or, for some leds, a zener diode, which is integrated into the device in parallel with the now opened led. for basic leds (which do not have built-in zener diodes), an open circuit failure of an led will only result in the loss of one channel of leds without affecting other channels. similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step c hanges in led duty cycle) can transiently look like led fault modes. the isl97636 uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the led stacks to fault out. see table 1 for more details. a fault condition that results in an input current that exceeds the devices electrical limits will result in a shutdown of all output channels. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above 8v (the action taken is described in table 1.) open circuit protection (ocp) when one of the leds becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the isl97636 monitors the current in each channel such that any string wh ich reaches at least 75% of the intended output current is considered ?good?. should the current subsequently fall below 50% of the target, the channel will be considered an ?open circ uit?. furthermore, should the boost output of the isl97636 reach the ovp limit or should the lower over-temperature threshold be reached, all channels which are not ?good? wi ll immediately be considered as ?open circuit?. detection of an ?open circuit? channel will result in a time-out before disabling of the affected channel. this time-out is sped up when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip poi nt from being reached. r set 733 0.02 ? 36.6k == (eq. 2) i led ave () i led pwmi = (eq. 3) isl97636
12 fn6570.0 may 9, 2008 some users employ some special types of leds that have zener diode structure in parallel with the led for esd enhancement and enabling open circuit operation. when this type of led is open circuit ed, the effect is as if the led forward voltage has increased but no lighting. any affected string will not be disabled, unless the failure results in the boost ovp limit being reached, allowing all other leds in the string to remain functional. care should be taken in this case that the boost ovp limit and scp limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. this is due to the increased forward voltage of the faulty channel making all other channels look as if they have led shorts. see table 1 for details regarding responses to fault conditions. overvoltage protection (ovp) the integrated ovp circuit m onitors the output voltage and keeps the voltage at a safe level. the ovp threshold is set as: these resistors should be large to minimize the power loss. for example, a 1m r upper and 39k r lower sets ovp to 32.2v. large ovp resistors also allow c out discharges slowly during the pwm off time. undervoltage lockout if the input voltage falls below the uvlo level of 2.45v, the device will stop switching and reset. operation will restart when the voltage comes back into the operating range. input overcurrent protection during normal switching operation, the current through the internal boost power fet is monitored. if the current exceeds the current limit, the internal switch will be turned off. this monitoring happens on a cycle-by-cycle basis in a self protecting way. additionally, the isl97636 monitors the voltage at the lx and ovp pins. at start-up, a fi xed current is injected out of the lx pins and into the output capacitor. the device will not start-up unless the voltage at lx exceeds 1.2v. furthermore, should the voltage at lx not rise above this threshold during any subsequent period where the power fet is not switched on, it will immediately disable the input protection fet. the ovp pin is also monitored such that if it rises above and subsequently falls below 20% of the target ovp level, the input protection fet will also be switched off. over-temperature protection (otp) the isl97636 includes two over-temperature thresholds. the lower threshold is set to +130c. when this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as ?open circuit? and disabled after a ti me-out period. this time-out period is also reduced to 800s when it is above the lower threshold. the intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit t he upper temperature threshold. the upper threshold is set to +150c. each time this is reached, the boost will stop s witching and the output current sources will be switched off. once the device has cooled to approximately +100c, the dev ice will restart with the dc led current level reduced to 77% of the initial setting. if the dissipation problem persists, su bsequent hitting of the limit will cause identical behavior, with the current reduced in steps to 53% and finally 30%. unless disabled via the en pin, the device stays in an active state throughout. for the extensive fault protection conditions, please refer to figure 18 and table 1 for details. ovp 1.21v r upper r lower + () r lower ? = (eq. 4) isl97636
13 fn6570.0 may 9, 2008 table 1. protections table case failure mode detection mode failed channel action good channels action vout regulated by 1 ch0 short circuit upper over-temperature protection limit (otp) not triggered and viin0 < vsc ch0 on and burns power ch1 through ch7 normal highest vf of ch1 through ch7 2 ch0 short circuit upper otp triggered but vin0 < vsc ch0 goes off until chip cooled and then comes back on with current reduced to 76%. further otp triggers result in reduction to 53%, then 30%. same as ch0 highest vf of ch1 through ch7 3 ch0 short circuit upper otp not triggered but viin0 > vsc ch0 doubled after 6ms time-out. time-out reduced to 420s if above lower otp limit ch1 through ch7 normal highest vf of ch1 through ch7 4 ch0 open circuit with infinite resistance upper otp not triggered and viin0 < vsc vout will ramp to ovp. ch0 will time-out after 6ms (800s if above lower otp limit) and switch off. vout will drop to normal level. ch1 through ch7 normal highest vf of ch1 through ch7 5 ch0 led open circuit but has paralleled zener upper otp not triggered and viin0 < vsc ch0 remains on and has highest vf, thus vout increases ch1 through ch7 on, q1 through q7 burn power vf of ch0 figure 18. simplified fault protections q7 vsc iin7 vset pwm/oc0/sc0 ref fet driver lx imax ilimit driver fault ovp vin t2 otp thrm shdn q0 vsc iin0 vout vset pwm/oc7/sc7 temp sensor logic lx t1 otp thrm shdn o/p short fault detect logic pwm generator isl97636
14 fn6570.0 may 9, 2008 components selections according to the inductor voltage-second balance principle, the change of inductor current during the switching regulator on time is equal to the change of inductor current during the switching regulator off time. since the voltage across an inductor is: and i l @ on = i l @ off, therefore: where d is the switching duty cycle defined by the turn-on time over the s witching period. v d is schottky diode forward voltage that can be neglected for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle respectively as: input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. this reduces interaction between the regulator and input supply, improving system stability. the hi gh switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. a capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as x5r or x7r ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to ot her ceramic capacitors. in boost mode, input current fl ows continuously into the inductor, with an ac ripple component proportional to the rate of inductor charging only and smaller value input capacitors may be used. it is recommended that an input capacitor of at least 10f be used. ensure the voltage rating of the input capacitor is suitable to handle the full supply range. 6 ch0 led open circuit but has paralleled zener upper otp triggered but viin0 < vsc ch0 goes off until chip cooled and then comes back on with current reduced to 76%. further otp triggers result in reduction to 53%, then 30%. same as ch0 vf of ch0 7 ch0 led open circuit but has paralleled zener upper otp not triggered but viin0 > vsc ch0 off ch1 through ch7 normal highest vf of ch1 through ch7 upper otp not triggered but viinx > vsc ch0 remains on and has highest vf, thus vout increases. vout increases then ch-x switches off. this is an unwanted shut off and the effect can be minimized by setting ovp at an appropriate level. vf of ch0 8 channel-to-channel vf too high lower otp triggered but viinx < vsc any channel at below 50% of the target current will fault out after 400s. remaining channels driven with normal current. highest vf of ch0 through ch7 9 channel-to-channel vf too high upper otp triggered but viinx < vsc all channels switched off until chip cooled and then comes back on with current reduced to 76%. further otp triggers result in reduction to 53%, then 30%. highest vf of ch0 through ch7 10 output led stack voltage too high vout > vovp driven with normal current. any channel that is below 50% of the target current will time-out after 6ms. highest vf of ch0 through ch7 11 vout/lx shorted to gnd lx current and timing are monitored. ovp pin monitored for excursions below 20% of ovp threshold fault switch disabled and system s hutdown until fault goes away, vout is checked at start-up with a low curr ent from lx to check for presence of short before the fault switch is enabled. table 1. protections table (continued) case failure mode detection mode failed channel action good channels action vout regulated by v l l i l t ? = (eq. 5) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 6) v o v i 11d ? () ? = ? (eq. 7) dv o ( v i ) v o ? ? = (eq. 8) isl97636
15 fn6570.0 may 9, 2008 inductor the selection of the inductor should be based on its maximum current (i sat ) characteristics, power dissipation (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. its maximum current capability must be adequate to handle the peak current at the worst case condition. if an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi susceptible applications, such as led backlighting. the peak current can be deriv ed from the fact that the voltage across the inductor during the off period can be shown as: the choice of 85% is just an average term for the efficiency approximation. the first term is average current that is inversely proportional to the input voltage. the second term is inductor current change that is inversely proportional to l and f s . as a result, for a given switching frequency and minimum input voltage the system operates, the inductor i sat must be chosen carefully. at a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. thus the higher the inductance, the lower the peak current capability. the isl97636 current limit may also have to be taken into account. output capacitors the output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. output ripple voltage consists of the discharge of the output capacitor for i lpeak during fet on and the voltage drop due to flowing through the esr of the output capacitor. the ripple voltage can be shown as: the conservation of charge principle in equation 8 also brings up a fact that during the boost switch off period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. as a result, the user needs to se lect an output capacitor with low esd and with a enough input ripple current capability. output ripple v co can be reduced by increasing c o or f s , or using small esr capacitors. in general, ceramic capacitors are the best choice for output capacitors in small to medium sized lcd backlight applications due to their cost, form factor, and low esr. a larger output capacitor will also ease the driver response during pwm dimming off period due to the longer sample and hold effect of the output drooping. the driver does not need to boost harder in the ne xt on period that minimizes transient current. the output capacitor is also needed for compensation, and in general, 2x4.7f/50v ceramic capacitors are suitable for the notebook display backlight applications. schottky diode a high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. low forward voltage and reverse leakage current will minimize losses, making schottky diodes the preferred choice. although the schottky diode turns on only during the boost switch off period, it carries the same peak current as the inductor?s, and therefore, a suitable current rated schottky diode must be used. applications high current applications each channel of the isl97636 can support up to 35ma. for applications that need higher current, multiple channels can be grouped to achieve the desirable current. for example, the cathode of the last led can be connected to iin0 to iin2; this configuration can be treated as a single string with 105ma current driving capability. compensation the isl97636 has two main elements in the system; the current mode boost regulator and the op amp based multi-channel current sources. the isl97636 incorporates a transconductance amplifier in its feedback path to allow the user some levels of adjustme nt on the transient response and better regulation. the isl97636 uses current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. the fast current feedback loop does not require any compensation. the slow voltage loop must be compensated for stable operation. the il peak v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f s ) ? ? [] ? + ? = (eq. 9) v co i ( o c o df s ) i ( o esr () + ? ? = (eq. 10) figure 19. grouping multiple channels for high current applications iin0 iin1 iin2 v out isl97636
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6570.0 may 9, 2008 compensation network is a series rc, cc1 network from comp pin to ground and an optional cc2 capacitor connected to the comp pin. the rc sets the high frequency integrator gain for fast transient response and the cc1 sets the integrator zero to ensure loop stability. for most applications, rc is in the range of 200 to 3k and cc1 is in the range of 27nf to 37nf. depending upon the pcb layout, a cc2, in range of 100nf, may be needed to create a pole to cancel the output capacitor esr?s zero effect for stability. the isl97636 evaluation board is configured with rc1 of 500 , cc1 of 33nf, and cc2 of 0, which achieves stability. in the actual applications, these values may need to be tuned empirically but the recommended values are usually a good starting point. isl97636
17 fn6570.0 may 9, 2008 vin pwmi/en c6 4.7/50v c11 1/10v r2 r4 39k d1 ss15 ovp r3 1m smbclk 1 smbdat 2 fpwm 3 pwmo 4 gnd 5 iin7 7 iin6 8 iin5 9 iin4 10 rset 11 iin1 14 iin0 15 ovp 16 pgnd 17 pgnd 18 lx 20 fault 21 comp 22 vin 23 vdc 24 pwmi/en 6 iin3 12 lx 19 iin2 13 u1 isl97636 c1 10/25v c10 33n r7 500 c7 4.7/50v c12 0.1/10v c2 0.1/25v c4 10/25v 1 2 5 6 4 3 q1 fdma530pz led1 led2 led3 led4 led5 led6 led7 led8 led9 led10 led11 led12 led13 led14 led15 led16 led17 led18 led19 led20 led21 led22 led23 led24 led25 led26 led27 led28 led29 led30 led31 led32 led33 led34 led35 led36 led37 led38 led39 led40 led41 led42 led43 led44 led45 led46 led47 led48 led55 led56 led57 led58 led59 led60 led61 led62 led64 led65 led66 led67 led68 led69 led70 led71 led49 led50 led51 led52 led53 led63 led72 led54 l1 8.2h l1 : ihlp-2525bd-01 vishay inductor, d1 : ss15 - vishay schottky diode, 5 notes: figure 20. typical application circuit 36.6k c20 for 2 layers board, layout pgnd (noisy ground) on top layer and agnd (quiet ground) on bottom layer. tie pgnd and agnd only at one point by doing this: bridge u1 pgnd (pins 18 and 19) and agnd (pin 5) to the package thermal pad. put multiple vias on the thermal pad that connects to the bottom side agnd. isl97636
18 fn6570.0 may 9, 2008 isl97636 package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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