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march 2011 FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMC8200S rev.c4 FDMC8200S dual n-channel powertrench ? mosfet 30 v, 10 m , 20 m features q1: n-channel ? max r ds(on) = 20 m at v gs = 10 v, i d = 6 a ? max r ds(on) = 32 m at v gs = 4.5 v, i d = 5 a q2: n-channel ? max r ds(on) = 10 m at v gs = 10 v, i d = 8.5 a ? max r ds(on) = 13.5 m at v gs = 4.5 v, i d = 7.2 a ? rohs compliant general description this device includes two specia lized n-channel mosfets in a due power33(3mm x 3mm mlp) package. the switch node has been internally connected to enable easy placement and routing of synchronous buck converters . the control mosfet (q1) and synchronous mosfet (q2) hav e been designed to provide optimal power efficiency. applications ? mobile computing ? mobile internet devices ? general purpose point of load bottom bottom power33 pin 1 g1 d1 d1 d1 d1 d 2 / s 1 g2 s2 s2 s2 v in v in v in v in s w i t c h n o d e g ls gnd gnd gnd g hs 4 3 2 1 5 6 7 8 q 1 q 2 mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage (note 4) 20 20 v i d drain current -continuous (pack age limited) t c = 25 c 18 13 a -continuous (silicon limited) t c = 25 c 23 46 -continuous t a = 25 c 6 1a 8.5 1b -pulsed 40 27 e as single pulse avalanche energy (note 3) 12 32 p d power dissipation for single operati on t a = 25c 1.9 1a 2.5 1b w power dissipation for single operati on t a = 25c 0.7 1c 1.0 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 65 1a 50 1b c/w r ja thermal resistance, junction to ambient 180 1c 125 1d r jc thermal resistance, junction to case 7.5 4.2 device marking device package reel size tape width quantity FDMC8200S FDMC8200S power 33 13? 12 mm 3000 units
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMC8200S rev.c4 electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 1ma, v gs = 0 v q1 q2 30 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c i d = 1ma, referenced to 25c q1 q2 14 13 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v q1 q2 1 500 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 1ma q1 q2 1.0 1.0 2.3 2.0 3.0 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25c i d = 1ma, referenced to 25c q1 q2 -5 -6 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 6 a v gs = 4.5 v, i d = 5 a v gs = 10 v, i d = 6 a, t j = 125c q1 16 24 22 20 32 28 m v gs = 10 v, i d = 8.5 a v gs = 4.5 v, i d = 7.2 a v gs = 10 v, i d = 8.5 a, t j = 125c q2 7.8 10.3 11.4 10.0 13.5 13.1 g fs forward transconductance v dd = 5 v, i d = 6 a v dd = 5 v, i d = 8.5 a q1 q2 29 43 s c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1 mhz q1 q2 495 1080 660 1436 pf c oss output capacitance q1 q2 145 373 195 495 pf c rss reverse transfer capacitance q1 q2 20 35 30 52 pf r g gate resistance q1 q2 0.2 0.2 1.4 1.2 4.2 3.6 t d(on) turn-on delay time q1 v dd = 15 v, i d = 1 a, v gs = 10 v, r gen = 6 q2 v dd = 15 v, i d = 1 a, v gs = 10 v, r gen = 6 q1 q2 11 7.6 20 15 ns t r rise time q1 q2 3.1 1.8 10 10 ns t d(off) turn-off delay time q1 q2 35 21 56 34 ns t f fall time q1 q2 1.3 8.5 10 17 ns q g(tot) total gate charge v gs = 0 v to 10 v q1 v dd = 15 v, i d = 6 a q1 q2 7.3 15.7 10 22 nc q g(tot) total gate charge v gs = 0 v to 4.5 v q1 q2 3.1 7.2 4.3 10 nc q gs gate to source charge q2 v dd = 15 v i d = 8.5 a q1 q2 1.8 3 nc q gd gate to drain ?miller? charge q1 q2 1 1.9 nc
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMC8200S rev.c4 electrical characteristics t j = 25c unless otherwise noted drain-source diod e characteristics notes: 1. r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3.starting q1: t = 25 c, l = 1 mh, i = 5 a, vgs = 10v, vdd = 27v, 100% test at l = 3 mh, i = 4 a; q2: t = 25 c, l = 1 mh, i = 8 a, vgs = 10v, vdd = 27v, 100% test at l = 3 mh, i = 3.2 a. 4. as an n-ch device, the negative vgs rating is for low duty cycle pulse ocurrence only. no continuous rating is implied. symbol parameter test conditions type min typ max units v sd source-drain diode forward voltage v gs = 0 v, i s = 6 a (note 2) v gs = 0 v, i s = 8.5 a (note 2) v gs = 0 v, i s = 1.3 a (note 2) q1 q2 q2 0.8 0.8 0.6 1.2 1.2 0.8 v t rr reverse recovery time q1 i f = 6 a, di/dt = 100 a/s q2 i f = 8.5 a, di/dt = 300 a/s q1 q2 13 20 24 32 ns q rr reverse recovery charge q1 q2 2.3 15 10 24 nc a.65 c/w when mounted on a 1 in 2 pad of 2 oz copper c. 180 c/w when mounted on a minimum pad of 2 oz copper b.50 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 125 c/w when mounted on a minimum pad of 2 oz copper
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMC8200S rev.c4 typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 v gs = 10 v v gs = 4 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 3.5 v v gs = 4.5 v v gs = 6 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 10203040 0 1 2 3 4 v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 6 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.8 1.0 1.2 1.4 1.6 i d = 6 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 20 40 60 80 100 t j = 125 o c i d = 6 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 2.0 2.5 3.0 3.5 4.0 4.5 0 10 20 30 40 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 40 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMC8200S rev.c4 figure 7. 02468 0 2 4 6 8 10 i d = 6 a v dd = 10 v v dd = 15 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 20 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 7 1 2 3 4 5 6 7 8 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 5 10 15 20 25 limited by package r t jc = 7.5 o c/w v gs = 4.5 v v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100200 0.01 0.1 1 10 50 10 s 1 s dc 100 ms 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c 0.01 0.1 1 10 100200 0.001 0.01 0.1 1 10 100 10 s 1 s dc 100 ms 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 180 o c/w t c = 25 o c figure 12. 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 single pulse r t ja = 125 o c/w t a = 25 o c v gs = 10 v p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMC8200S rev.c4 figure 13. junction-to-ambient transient thermal response curve p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.003 0.01 0.1 1 single pulse r t ja = 180 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMC8200S rev.c4 typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 14. on- region characteristics figure 15. normalized on-resistance vs drain current and gate voltage figure 16. normalized on-resistance vs junction temperature figure 17. on-resistance vs gate to source voltage figure 18. transfer characteristics figure 19. source to drain diode forward voltage vs source current 0.00.51.01.5 0 9 18 27 v gs = 3.5 v v gs = 3 v pulse duration = 80 s duty cycle = 0.5% max v gs = 4.5 v v gs = 4 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) 091827 1 2 3 4 v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 3 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.8 1.0 1.2 1.4 1.6 i d = 8.5 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 0 20 40 60 80 100 t j = 125 o c i d = 8.5 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m pulse duration = 80 s duty cycle = 0.5% max 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 9 18 27 t j = 150 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 30 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 8 www.fairchildsemi.com FDMC8200S rev.c4 typical characteristi cs (q2 n-channel) t j = 25c unless otherwise noted figure 20. gate charge characteristics figure 21. capacitance vs drain to source voltage figure 22. unclamped inductive switching capability f i g u r e 2 3 . m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 2 4 . f o r w a r d b i a s s a f e operating area figure 25. single pulse maximum power dissipation 0246810121416 0 2 4 6 8 10 i d = 8.5 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v 0.1 1 10 30 10 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 0.01 0.1 1 10 30 1 10 20 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 25 50 75 100 125 150 0 3 6 9 12 15 limited by package v gs = 4.5 v r ja = 50 o c/w v gs = 10 v i d , drain current (a) t a , case temperature ( o c ) 0.01 0.1 1 10 100200 0.01 0.1 1 10 50 10 s 1 s dc 100 ms 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r ja = 125 o c/w t a = 25 o c 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 single pulse r ja = 125 o c/w t a = 25 o c v gs = 10 v p ( pk ) , peak transient power (w) t, pulse width (sec)
typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 26. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 125 o c/w ( note 1b ) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 9 www.fairchildsemi.com FDMC8200S rev.c4
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 10 www.fairchildsemi.com FDMC8200S rev.c4 syncfet schottky body diode characteristics fairchild?s syncfet process emb eds a schottky diode in parallel with powertrench mosfet. th is diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 14 shows the reverses recovery characteristic of the FDMC8200S. schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. this will increase the power in the device. figure 27. FDMC8200S syncfet body diode reverse recovery characteristic 0 20406080100 -2 -1 0 1 2 3 4 5 6 7 di/dt = 300 a/ s current (a) time (ns) figure 28. syncfet body diode reverses leakage versus drain-source voltage 0 5 10 15 20 25 30 0.000001 0.00001 0.0001 0.001 0.01 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (a) v ds , reverse voltage (v) typical characteristics (continued)
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 11 www.fairchildsemi.com FDMC8200S rev.c4 dimensional outline and pad layout
FDMC8200S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 12 www.fairchildsemi.com FDMC8200S rev.c4 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairch ild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the term s of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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