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1 radiation hardened, high performance industry standard single-ended current mode pwm controller ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh the isl7884xaseh is a high performance, radiation hardened drop-in replacement for the popular 28c4x and 18c4x pwm controllers suitable for a wide range of power conversion applications including boost, flyback, and isolated output configurations. its fast sign al propagatio n and output switching characteristics make this an ideal product for existing and new designs. features include up to 13.2v op eration, low operating current, 90a typical start-up current, adjustable operating frequency to 1mhz, and high peak current drive capability with 50ns rise and fall times. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed in the ordering information must be used when ordering. detailed electrical specifications for the isl788xaseh are contained in smd 5962-07249 . a ?hot-link? is provided on our website for downloading. applications ? current mode switching power supplies ? isolated buck and flyback regulators ? boost regulators ? direction and speed control in motors ? control of high current fet drivers features ? electrically screened to dla smd # 5962-07249 ? qml qualified per mil-prf-38535 requirements ? 1a mosfet gate driver ? 90a typical start-up current, 125a max ? 35ns propagation delay current sense to output ? fast transient response with peak current mode control ? 9v to 13.2v operation ? adjustable switching frequency to 1mhz ? 50ns rise and fall times with 1nf output load ? trimmed timing capacitor discharge current for accurate deadtime/maximum du ty cycle control ? 1.5mhz bandwidth error amplifier ? tight tolerance voltage reference over line, load and temperature ? 3% current li mit threshold ? pb-free available (rohs compliant) ? radiation environment: - high dose rate (50 - 300rad(si)/s). . . . . . . . . 100 krad(si) - low dose rate (0.01rad(si)/s). . . . . . . 100 krad(si) (note) note: product capability established by initial characterization. the ?eh? version is acceptance tested on a wafer by wafer basis to 50 krad(si) at low dose rate. part number rising uvlo max. duty cycle ISL78840ASEH 7.0 100% isl78841aseh 7.0 50% isl78843aseh 8.4v 100% isl78845aseh 8.4v 50% pin configurations ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh (8 ld flatpack) top view ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh (8 ld sbdip) top view 8 7 6 5 2 3 4 1 comp fb cs rtct v ref v dd out gnd comp fb cs rtct 1 2 3 4 8 7 6 5 v ref v dd out gnd may 29, 2012 fn7952.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 2 fn7952.0 may 29, 2012 ordering information ordering number part number (notes 1, 2) temp. range (c) package (pb-free) pkg. dwg. # 5962r0724905vpc ISL78840ASEHvd -55 to +125 8 ld sbdip d8.3 5962r0724906vpc isl78841asehvd -55 to +125 8 ld sbdip d8.3 5962r0724907vpc isl78843asehvd -55 to +125 8 ld sbdip d8.3 5962r0724908vpc isl78845asehvd -55 to +125 8 ld sbdip d8.3 5962r0724905vxc ISL78840ASEHvf -55 to +125 8 ld flatpack k8.a 5962r0724906vxc isl78841asehvf -55 to +125 8 ld flatpack k8.a 5962r0724907vxc isl78843asehvf -55 to +125 8 ld flatpack k8.a 5962r0724908vxc isl78845asehvf -55 to +125 8 ld flatpack k8.a 5962r0724905v9a ISL78840ASEHvx -55 to +125 die 5962r0724906v9a isl78841asehvx -55 to +125 die 5962r0724907v9a isl78843asehvx -55 to +125 die 5962r0724908v9a isl78845asehvx -55 to +125 die notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for ISL78840ASEH , isl78841aseh , isl78843aseh , isl78845aseh . for more information on msl please see techbrief tb363 .
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 3 fn7952.0 may 29, 2012 functional block diagram t q q on 150k 100k v dd cs out fb rtct gnd v ref pwm comparator reset dominant 2.5v enable 8.4ma 2.9v 1.0v oscillator comparator <10ns + - start/stop uv comparator v ref 5v + - + - 100mv error amplifier + - v ref + - on + - s r q q comp v ref uv comparator 4.65v 4.80v + - a = 0.5 + - clock 1.1v clamp 2r r vf total = 1.15v a v ref fault ok v dd 36k isl78841a, only isl78845a
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 4 fn7952.0 may 29, 2012 typical application - 48v in put dual output flyback v in + v in - return t1 q3 36v to 75v vr1 +1.8v +3.3v c1 c2 c3 r1 r3 c4 q1 r4 cr6 c5 r22 u2 cr2 cr5 cr4 c17 r21 u3 r16 c14 c13 r15 r19 r17 r18 r20 c15 c16 c12 c11 r13 c8 r10 r6 cr1 + + c21 c19 c22 c20 + + c6 isl7884xaseh v dd rtct cs fb out comp v ref gnd r26 r27 u4 r28
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 5 fn7952.0 may 29, 2012 typical application - boost converter vin+ vin- c1 q1 r1 r4 cr1 c9 r7 c2 c5 c6 c7 r3 + r2 c4 l1 c3 vin+ u1 isl7884xaseh out cs rtct fb comp v ref v dd gnd +vout r6 r5 return c10 c8 r8 r9
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 6 fn7952.0 may 29, 2012 absolute maximum rating s thermal information supply voltage v dd without beam . . . . . . . . . . . . . . .gnd -0.3v to +30.0v supply voltage v dd under beam . . . . . . . . . . . . . . . . .gnd -0.3v to +14.7v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to v dd + 0.3v signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1a esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c supply voltage (typical note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 9v to 13.2v thermal resistance (typical) ja (c/w) jc (c/w) 8 ld flatpack package (notes 3, 4) 140 15 8 ld sbdip package (notes 3, 4) 98 15 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp radiation information maximum total dose dose rate = 50 - 100radsi/s . . . . . . . . . . . . . . . . . . . . . . . 100 krads (si) dose rate = 0.01rad(si)/s (note 6). . . . . . . . . . . . . . . . . . . . . 100 krad (si) seb (no burnout) (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 80mev/mg/cm 2 sel (no latchup) (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 80mev/mg/cm 2 set (regulated v out within 3%) (note 9) . . . . . . . . . . . . 40mev/mg/cm 2 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 4. for jc , the "case temp" location is the center of the ceramic on the package underside. 5. all voltages are with respect to gnd. 6. product capability established by initial characterization. the ?eh? version is acceptance tested on a wafer by wafer basis t o 50 krad(si) at low dose rate. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. v dd = 13.2v, r t = 10k ? , c t = 3.3nf, t a = -55 to +125c. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -55 to +125c. parameter test conditions min (note 10) typ max (note 10) units undervoltage lockout start threshold isl78840a, isl78841a 6.5 7.0 7.5 v isl78843a, isl78845a 8.0 8.4 9.0 v stop threshold isl78840a, isl78841a 6.1 6.6 6.9 v isl78843a, isl78845a 7.3 7.6 8.0 v hysteresis isl78840a, isl78841a - 0.4 - v isl78843a, isl78845a - 0.8 - v start-up current, i dd v dd < start threshold - 90 125 a v dd < start threshold, 100krad - 300 500 a operating current, i dd (note 7) - 2.9 4.0 ma operating supply current, i d includes 1nf gate loading - 4.75 5.5 ma reference voltage overall accuracy over line (v dd = 9v to 13.2v), load of 1ma and 10ma, temperature 4.925 5.000 5.050 v long term stability t a = +125c, 1000 hours (note 8) - 5 - mv current limit, sourcing -20 - - ma current limit, sinking 5 - - ma current sense input bias current v cs = 1v -1.0 - 1.0 a input signal, maximum 0.97 1.00 1.03 v
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 7 fn7952.0 may 29, 2012 gain, a cs = v comp / v cs 0 < v cs < 910mv, v fb = 0v 2.75 2.82 3.15 v/v cs to out delay - 35 55 ns error amplifier open loop voltage gain (note 8) - 90 - db unity gain bandwidth (note 8) - 1.5 - mhz reference voltage, v ref v fb = v comp 2.475 2.500 2.530 v fb input bias current, fbi ib v fb = 0v -1.0 -0.2 1.0 a comp sink current v comp = 1.5v, v fb = 2.7v 1.0 - - ma comp source current v comp = 1.5v, v fb = 2.3v -0.4 - - ma comp voh v fb = 2.3v 4.80 - v ref v comp vol v fb = 2.7v 0.4 - 1.0 v psrr frequency = 120hz, v dd = 9v to 13.2v (note 8) - 80 - db oscillator frequency accuracy initial, t a = +25c 48 51 53 khz frequency variation with v dd t a = +25c, (f 13.2v - f 9v )/f 12v -0.21.0% temperature stability (note 8) - 5 - % amplitude, peak-to-peak static test - 1.75 - v rtct discharge voltage (valley voltage) static test - 1.0 - v discharge current rtct = 2.0v 6.5 7.8 8.5 ma output gate voh v dd to out, i out = -100ma - 1.0 2.0 v gate vol out to gnd, i out = 100ma - 1.0 2.0 v peak output current c out = 1nf (note 8) - 1.0 - a rise time c out = 1nf - 35 60 ns fall time c out = 1nf - 20 40 ns output off state leakage v dd = 5v - - 50 a pwm maximum duty cycle (isl78840a, isl78843a) comp = v ref 94.0 96.0 - % maximum duty cycle (isl78841a, isl78845a) comp = v ref 47.0 48.0 - % minimum duty cycle comp = gnd - - 0 % notes: 7. this is the v dd current consumed when the device is active but not switching. does not include gate drive current. 8. limits established by characteriza tion and are not production tested. 9. see tests performed with vref bypass capacitor of 0.22f and f sw = 200khz. seb/l tests done on a standalo ne open loop configuration. set tests done in a closed loop configuration. for sel no hard latch requiring manual interven tion were observed. for more information se e: isl7884xasrh see test report . 10. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise sp ecified. temperature limits established b y characterization and are not production tested. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. v dd = 13.2v, r t = 10k ? , c t = 3.3nf, t a = -55 to +125c. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -55 to +125c. (continued) parameter test conditions min (note 10) typ max (note 10) units
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 8 fn7952.0 may 29, 2012 pin descriptions rtct - this is the oscillator timing control pin. the operational frequency and maximum duty cycle are set by connecting a resistor, rt, between v ref and this pin and a timing capacitor, ct, from this pin to gnd. the oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0mhz. the charge time, t c , the discharge time, t d , the switching frequency, f, and the maximum duty cycle, d max , can be approximated from equations 1 through 4: the formulae have increased error at higher frequencies due to propagation delays. figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given switching frequency for the is l78841aseh, isl78845aseh. the value for the ISL78840ASEH, isl7 8843aseh will be twice that shown in figure 4. comp - comp is the output of the error amplifier and the input of the pwm comparator. the control loop frequency compensation network is connected between the comp and fb pins. fb - the output voltage feedback is connected to the inverting input of the error amplifier through this pin. the non-inverting input of the error amplifier is internally tied to a reference voltage. cs - this is the current sense input to the pwm comparator. the range of the input signal is nominally 0v to 1.0v and has an internal offset of 100mv. gnd - gnd is the power and small sign al reference ground for all functions. out - this is the drive output to the power switching device. it is a high current output capable of driving the gate of a power mosfet with peak currents of 1.0a. this gate output is actively held low when v dd is below the uvlo threshold. v dd - v dd is the power connection for the device. the total supply current will depend on the lo ad applied to out. total i dd current is the sum of the operating current and the average output current. knowing the operating frequency, f, and the mosfet gate charge, qg, the average output current can be calculated from equation 5: typical performance curves figure 1. frequency vs temperature figure 2. reference voltage vs temperature figure 3. ea reference vs temperature figure 4. resistance for ct capacitor values given -60 -40 -20 0 20 40 60 80 100 120 140 0.98 0.99 1.00 1.01 temperature (c) normalized frequency -60 -40 -20 0 20 40 60 80 100 0.995 0.996 0.997 0.998 0.999 1.000 1.001 temperature (c) normalized v ref 140 120 -60 -40 -20 0 20 40 60 80 100 120 140 0.996 0.997 0.998 1.000 1.001 temperature (c) normalized ea reference 110100 1 10 100 10 3 rt (k ? ) frequency (khz) 100pf 220pf 330pf 470pf 1.0nf 2.2nf 3.3nf 4.7nf 6.8nf (eq. 1) t c 0.533 rt ct ?? t d rt ? ct in 0.008 rt 3.83 ? ? 0.008 rt 1.71 ? ? --------------------------------------------- ? ? ? ? ?? (eq. 2) f1t c t d + () ? = (eq. 3) dt c f ? = (eq. 4) i out qg f = (eq. 5)
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 9 fn7952.0 may 29, 2012 to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the v dd and gnd pins as possible. v ref - the 5.00v reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. the recommended bypass to gnd cap is in the range 0.1f to 0.22f. a typical value of 0.15f can be used. functional description features the isl7884xaseh current mode pwm makes an ideal choice for low-cost flyback and forward topology applications. with its greatly improved performance over industry standard parts, it is the obvious choice for new desi gns or existing designs which require updating. oscillator the isl7884xaseh has a sawtooth oscillator with a programmable frequency range to 2mhz, which can be programmed with a resistor from v ref and a capacitor to gnd on the rtct pin. (please refer to figure 4 for the resistor and capacitance required for a given frequency). soft-start operation soft-start must be implemented externally. one method, illustrated below, clamps the voltage on comp. the comp pin is clamped to the voltage on capacitor c 1 plus a base-emitter junction by transistor q 1 . c 1 is charged from v ref through resistor r 1 and the base current of q 1 . at power-up c 1 is fully discharged, comp is at ~0.7v, and the duty cycle is zero. as c 1 charges, the voltage on comp increases, and the duty cycle increases in proportion to the voltage on c 1 . when comp reaches the steady state operating point, the control loop takes over and soft-start is complete. c 1 continues to charge up to v ref and no longer affects comp. during power-down, diode d 1 quickly discharges c 1 so that the soft-start circuit is properly initialized prior to the next power-on sequence. gate drive the isl7884xaseh is capable of sourcing and sinking 1a peak current. to limit the peak current through the ic, an optional external resistor may be placed between the totem-pole output of the ic (out pin) and the gate of the mosfet. this small series resistor also damps any oscillatio ns caused by the resonant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. tid en vironment of >50krads requires the use of a bleeder resistor of 10k from the out pin to gnd. slope compensation for applications where the maximu m duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. the amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. for applications where the duty cycl e is greater than 50%, slope compensation is required to prevent instability. slope compensation may be accomplished by summing an external ramp with the current fe edback signal or by subtracting the external ramp from the voltage feedback error signal. adding the external ramp to the current feedback signal is the more popular method. from the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, fm, without slope compensation is calculated in equation 6: where sn is the slope of the sawtooth signal and tsw is the duration of the half-cycle. when an external ramp is added, the modulator gain becomes equation 7: where se is slope of the extern al ramp and becomes equation 8: the criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at the switching frequency. the double-pole will be critically damped if the q-factor is set to 1, over-damped for q < 1, and under-damped for q > 1. an under-damped condition may result in current loop instability. where d is the percent of on-time during a switching cycle. setting q = 1 and solving for se yields equation 10: since sn and se are the on-time slopes of the current ramp and the external ramp, respectively, they can be multiplied by t on to obtain the voltage change that occurs during t on . where v n is the change in the current feedback signal ( i) during the on-time and ve is the voltag e that must be added by the external ramp. figure 5. soft-start v ref comp gnd isl7884xaseh c 1 q 1 d 1 r 1 fm 1 sntsw ----------------- - = (eq. 6) fm 1 sn se + () tsw ------------------------------------ - 1 m c sntsw -------------------------- == (eq. 7) m c 1 se sn ------- + = (eq. 8) q 1 m c 1d ? () 0.5 ? () ------------------------------------------------- = (eq. 9) e s n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 10) v e v n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 11)
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 10 fn7952.0 may 29, 2012 for a flyback converter, vn can be solved in terms of input voltage, current transducer components, and primary inductance, yielding equation 12: where r cs is the current sense resistor, t sw is the switching period, l p is the primary inductance, v in is the minimum input voltage, and d is the maximum duty cycle. the current sense signal at the end of the on time for ccm operation is equation 13: where v cs is the voltage across the current sense resistor, l s is the secondary winding inductance, and i o is the output current at current limit. equation 13 assumes the voltage drop across the output rectifier is negligible. since the peak current limit thresh old is 1.00v, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold as: shown in equation 14. substituting equations 12 and 13 into equation 14 and solving for r cs yields equation 15: adding slope compensation is accomplished in the isl7884xaseh using an external buffer transistor and the rtct signal. a typical application sums the buffered rtct signal with the current sense feedback and applies the result to the cs pin as shown in figure 6. assuming the designer has selected values for the rc filter (r 6 and c 4 ) placed on the cs pin, the value of r 9 required to add the appropriate external ramp can be found by superposition. the factor of 2.05 in equation 16 arises from the peak amplitude of the sawtooth waveform on rtct minus a base-emitter junction drop. that voltage multiplied by the maximum duty cycle is the voltage source for the slope compensation. rearranging to solve for r 9 yields equation 17: the value of r cs determined in equation 15 must be rescaled so that the current sense signal presented at the cs pin is that predicted by equation 13. the divider created by r 6 and r 9 makes this necessary. example: v in = 12v v o = 48v l s = 800h ns/np = 10 lp = 8.0h i o = 200ma switching frequency, f sw = 200khz duty cycle, d = 28.6% r 6 = 499 ? solve for the current sense resistor, r cs , using equation 15. r cs = 295m ? determine the amount of voltage, ve, that must be added to the current feedback signal using equation 12. ve = 92.4mv using equation 17, solve for the summing resistor, r 9 , from ct to cs. r 9 = 2.67k ? determine the new value of r cs (r? cs ) using equation 18. r? cs = 350m ? additional slope compensation may be considered for design margin. the above discussion determines the minimum external ramp that is required. the buffer transistor used to create the external ramp from rtct should have a sufficiently high gain (>200) so as to minimize the required base current. whatever base current is required reduces the charging current into rtct and will reduce the oscillator frequency. v e dt ? sw v in r cs ?? l p ---------------------------------------------------- 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = v (eq. 12) v cs n s r cs ? n p ------------------------ i o 1d ? () v o t ?? sw 2l s ---------------------------------------------- + ?? ?? ?? = v (eq. 13) v e v cs + 1v = (eq. 14) r cs 1 dt sw v in ?? l p --------------------------------- 1 -- - 0.5 + 1d ? ----------------- - 1 ? ?? ?? ?? ?? ? n s n p ------ - i o 1d ? () v o t sw ?? 2l s ---------------------------------------------- + ?? ?? ?? ? + ------------------------------------------------------------------------------------------------------------------------------- ------------------------- - = (eq. 15) cs rtct r6 c4 r9 isl78843aseh v ref figure 6. slope compensation v e 2.05d r 6 ? r 6 r 9 + --------------------------- - = v (eq. 16) r 9 2.05d v e ? () r 6 ? v e --------------------------------------------- - = (eq. 17) r cs r 6 r 9 + r 9 -------------------- - r cs ? = (eq. 18)
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 11 fn7952.0 may 29, 2012 fault conditions a fault condition occurs if v ref falls below 4.65v. when a fault is detected, out is disabled. when v ref exceeds 4.80v, the fault condition clears, and out is enabled. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. a unique section of the ground plane must be designated for high di/dt currents associated with the output stage. v dd should be bypassed directly to gnd with good high frequency capacitors. references [1] ridley, r., ?a new continuous-time model for current mode control?, ieee transactions on power electronics, vol. 6, no. 2, april 1991.
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 12 fn7952.0 may 29, 2012 package characteristics weight of packaged device 8 ld mini dip: 0.7004 grams 8 ld flatpack: 0.3605 grams die characteristics die dimensions 2030m x 2030m (80 mils x 80 mils) thickness: 482m 25.4m (19.0 mils 1 mil) interface materials glassivation type: silicon oxide and silicon nitride thickness: 0.3m 0.03m to 1.2m 0.12m top metallization type: alcu (99.5%/0.5%) thickness: 2.7m 0.4m substrate silicon backside finish silicon process 0.6m bicmos junction isolated assembly related information substrate potential unbiased additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 1278 die map
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 13 fn7952.0 may 29, 2012 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL78840ASEH , isl78841aseh , isl78843aseh , isl78845aseh to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change may 4, 2012 fn7952.0 initial release.
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 14 fn7952.0 may 29, 2012 package outline drawing k8.a 8 lead ceramic metal seal flatpack package rev 2, 12/10 lead finish side view top view -d- -c- 0.265 (6.75) 0.115 (2.92) 0.026 (0.66) 0.265 (6.73) seating and 0.180 (4.57) 0.03 (0.76) min base plane -h- 0.09 (0.23) 0.005 (0.13) pin no. 1 id area 0.050 (1.27 bsc) 0.022 (0.56) 0.015 (0.38) min 0.245 (6.22) 0.070 (1.18) 0.170 (4.32) 0.370 (9.40) 0.250 (6.35) 0.04 (0.10) 0.245 (6.22) 1. adjacent to pin one and shall be loca ted within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the fini shed lead surfaces, when solder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads. 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0. 038mm) maximum when solder dip lead finish is applied. 7. 8. notes: 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 dimensioning and tolerancing per ansi y14.5m - 1982. controlling dimension: inch. index area: a notch or a pin one identification mark shall be located if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the section a-a base metal 0.007 (0.18) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.045 (1.14)
ISL78840ASEH, isl78841aseh, isl78843aseh, isl78845aseh 15 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7952.0 may 29, 2012 for additional products, see www.intersil.com/product_tree ceramic dual-in-line meta l seal packages (sbdip) notes: 1. index area: a notch or a pin one iden tification mark shall be located ad- jacent to pin one and shall be locat ed within the shaded area shown. the manufacturer?s identification shal l not be used as a pin one identi- fication mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead platin g and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d8.3 mil-std-1835 cdip2-t8 (d-4, configuration c) 8 lead ceramic dual-in-li ne metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.405 - 10.29 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n8 88 rev. 0 4/94

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