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TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 1 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. features n input ports ? rgb analog input port supports up to 165 mhz (uxga @ 60hz) ? full sog and composite sync support, including copy protected signals n display processing engine ? patent-pending hybrid image resolution converter ? variable sharpness control ? interlaced to progressive conversion ? patent-pending dynamic frame-rate generator (dfr) C short line storage frame extension technique eliminates short lines in output frames ? media window enhancement (mwe) note ? peaking & coring functions for sharpness enhancement and noise reduction ? brightness and contrast control ? programmable 10-bit gamma correction ? srgb support n auto-detection / auto-tune support ? auto input signal format (sog, composite, separated hsync and vsync) ? input mode detection support analyzes input video signal (h/v polarity, h/v frequency, interlace/field detect) C extensive status registers support robust detection of all vesa & ibm modes ? auto-tuning function including support for phase selection, image position, offset & gain and jitter detection ? smart screen-fitting n on-screen display controller (osd) ? built- in osd generator with 291 character font programmable ram ? internal osd rotation degree of 90 and 270 ? supports 2/4/8 multi-color fonts ? supports 8/16/256 color palette ? supports 1k code attributes ? gradient color function ? hardware button animation function ? pattern generator for production test ? supports osd mux and alpha blending capability n output display interface ? supports 6/8-bit lvds panel interface ? supports up to sxga display resolution with up to 135 mhz dot clock ? spread spectrum output frequency for emi suppression ? pwm backlight intensity control n dpms support ? full green mode dpms support ? low standby power (< 16ma) n embedded mcu ? 8032 cpu ? isp support ? uart support ? 19 gpio n external connection/component ? built-in ddc circuit ? ddc2b/2bi/2b+/ci support ? supports external serial flash note: the optional mwe function is available with tsum16awk. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 2 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. block diagram analog interface engine display processing engine osd clock gen mcu interface serial flash xtal/ext clk to panel analog rgb analog hsync/vsync lvds panel interface general description the TSUM16AK is total solution graphics processing ic for lcd monitors with panel resolutions up to sxga. it is configured with a high-speed integrated triple-adc/pll, a high quality display processing engine, and an integrated output display interface that can support lvds panel interface format. to further reduce system costs, the TSUM16AK also integrates intelligent power management control capability for green-mode requirements and spread-spectrum support for emi management. the TSUM16AK incorporates the world s first coherent oversampled rgb graphics adc in a monitor controller system 1 . the oversampling adc samples the input rgb signals at a frequency that is much higher than the signal source pixel rate. this can preserve details in the video signal that ordinarily would be lost due to input signal jitter or bandwidth limitations in non-oversampled systems. the TSUM16AK also incorporates a new dynamic frame rate (dfr) generator 2 for the digital output video to the display panel that preserves the advantages of a fixed output clock rate, while eliminating the output end of frame short-line. 1,2 patent pending free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 3 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. pin diagram (TSUM16AK) pin 1 1 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 36 37 38 3 9 4 0 67 66 65 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 6 4 81 80 79 78 77 76 75 74 73 72 71 70 69 68 84 83 82 r i n 0 m r i n 0 p g i n 0 m g i n 0 p s o g i n 0 b i n 0 m b i n 0 p g n d g n d r e x t a v d d _ a d c a v d d _ a d c csz sdi gpio_p23 gpio_p22 vddc gnd vddc sck rst xout vctrl vddc gpio_p12 gnd xin nc nc gnd sdo r e f m r e f p h s y n c 0 v s y n c 0 gpio_p15/pwm0 pwm1/gpio_p25 gpio_p00/sar1 gpio_p01/sar2 gpio_p02/sar3 gpio_p07 pwm0/gpio_p26 gpio_p16/pwm2 gpio_p27/pwm1 rstn gpio_p06 88 87 86 85 91 90 89 95 94 93 92 98 97 96 102 101 100 99 1 0 5 1 0 4 1 0 3 1 0 8 1 0 7 1 0 6 1 1 1 1 1 0 1 0 9 1 1 4 1 1 3 1 1 2 1 1 7 1 1 6 1 1 5 1 2 0 1 1 9 1 1 8 1 2 3 1 2 2 1 2 1 1 2 6 1 2 5 1 2 4 1 2 8 1 2 7 avdd_mpll v d d p m o d e [ 1 ] mode[0] vddp a v d d _ p l l a v d d _ a d c pwm2/gpio_p24 vddp gpio_p13 gpio_p14 vddp gpio_p03 bypass l v b 0 m g n d v d d p v d d c l v b 0 p l v b 1 m l v b 1 p l v b 2 m l v b 2 p l v b c k m l v b c k p l v b 3 m l v b 3 p l v a 0 m l v a 0 p l v a 1 m l v a 1 p l v a 2 m l v a 2 p l v a c k m l v a c k p l v a 3 m l v a 3 p n c nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc t s u m 1 6 a k x x x x x x x x x x x x x x x x ddca_sda/rs232_tx ddca_scl/rs232_rx gpio_p11/i2c_mda gpio_p10/i2c_mcl n c n c n c n c n c n c n c n c nc nc nc nc nc nc nc nc nc nc nc nc nc free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 4 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. pin description analog interface pin name pin type function pin hsync0 schmitt trigger input w/ 5v-tolerant analog hsync input 63 vsync0 schmitt trigger input w/ 5v-tolerant analog vsync input 64 refp internal adc top de-coupling pin 62 refm internal adc bottom de-coupling pin 61 rin0p analog input analog red input 59 rin0m analog input reference ground for analog red input 58 sogin0 analog input sync-on-green input 57 gin0p analog input analog green input 56 gin0m analog input reference ground for analog green input 55 bin0p analog input analog blue input 54 bin0m analog input reference ground for analog blue input 53 rext external resistor 390 ohm to avdd_adc 51 serial flash interface pin name pin type function pin sdo input w/ 5v-tolerant spi flash serial data output 70 csz output spi flash chip select 71 sck output spi flash serial clock 72 sdi output spi flash serial data input 73 lvds interface pin name pin type function pin lva0m output a-link negative lvds differential data output 114 lva0p output a-link positive lvds differential data output 113 lva1m output a-link negative lvds differential data output 112 lva1p output a-link positive lvds differential data output 111 lva2m output a-link negative lvds differential data output 110 lva2p output a-link positive lvds differential data output 109 lva3m output a-link negative lvds differential data output 106 lva3p output a-link positive lvds differential data output 105 free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 5 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. pin name pin type function pin lvackm output a-link negative lvds differential clock output 108 lvackp output a-link positive lvds differential clock output 107 lvb0m output b-link negative lvds differential data output 127 lvb0p output b-link positive lvds differential data output 126 lvb1m output b-link negative lvds differential data output 125 lvb1p output b-link positive lvds differential data output 124 lvb2m output b-link negative lvds differential data output 123 lvb2p output b-link positive lvds differential data output 122 lvb3m output b-link negative lvds differential data output 119 lvb3p output b-link positive lvds differential data output 118 lvbckm output b-link negative lvds differential clock output 121 lvbckp output b-link positive lvds differential clock output 120 gpio interface pin name pin type function pin gpio_p12 i/o w/ 5v-tolerant general purpose input/output; 4ma programmable driving strength 20 pwm1/ gpio_p25 i/o w/ 5v-tolerant pulse width modulation output; 4ma driving strength/ general purpose input/output; 4ma driving strength 21 gpio_p00/ sar1 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ sar adc input 23 gpio_p01/ sar2 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ sar adc input 24 gpio_p02/ sar3 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ sar adc input 25 gpio_p03 i/o w/ 5v-tolerant general purpose input/output; 4ma programmable driving strength 26 gpio_p06 i/o w/ 5v-tolerant general purpose input/output; 6/12ma programmable driving strength 27 gpio_p07 i/o w/ 5v-tolerant general purpose input/output; 6/12ma programmable driving strength 28 pwm0/ gpio_p26 i/o w/ 5v-tolerant pulse width modulation output; 4ma driving strength/ general purpose input/output; 4ma driving strength 29 gpio_p13 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength 30 gpio_p14 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength 31 free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 6 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. pin name pin type function pin gpio_p16/ pwm2 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ pulse width modulation output; 4ma driving strength 35 gpio_p15 /pwm0 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ pulse width modulation output; 4ma driving strength 69 gpio_p23 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength 74 gpio_p22 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength 75 gpio_p11/ i2c_mda i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ i2c master data; 4ma driving strength 76 gpio_p10/ i2c_mcl i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ i2c master clock; 4ma driving strength 77 pwm2/ gpio_p24 i/o w/ 5v-tolerant pulse width modulation output; 4ma driving strength/ general purpose input/output; 4ma driving strength 78 gpio_p27 /pwm1 i/o w/ 5v-tolerant general purpose input/output; 4ma driving strength/ pulse width modulation output; 4ma driving strength 79 misc. interface pin name pin type function pin bypass for external bypass capacitor 4 rst input w/ 5v-tolerant chip reset; high reset 19 rstn input w/ 5v-tolerant chip reset; low reset 22 vctrl output regulator control 11 chip configuration input mode[1:0] chip operation mode[1:0] input 00 normal operation 102, 104 ddca_sda/ rs232_tx i/o w/ 5v-tolerant ddc data for analog interface; 4ma driving strength / uart transmitter/gpio 65 ddca_scl/ rs232_rx input w/ 5v-tolerant ddc clock for analog interface/ uart receiver/gpio 66 xin crystal oscillator input xin 32 xout crystal oscillator output xout 33 power pins pin name pin type function pin avdd_adc 3.3v power adc power 44, 50, 60 avdd_mpll 3.3v power mpll power 34 avdd_pll 3.3v power pll power 52 free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 7 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. pin name pin type function pin vddp 3.3v power digital output power 14, 67, 95, 103, 115 vddc 1.8v power digital core power 12, 68, 97, 117 gnd ground ground 13, 38, 41, 47, 96, 116 no connects pin name pin type function pin nc no connects 1-3, 5-10, 15-18, 36, 37, 39, 40, 42, 43, 45, 46, 48, 49, 80-94, 98-101, 128 free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 8 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. electrical specifications analog interface characteristics parameter min typ max unit resolution 8 bits dc accuracy differential nonlinearity 0.5 +1.50/-1.0 lsb integral nonlinearity 1 lsb no missing codes guaranteed analog input input voltage range minimum 0.5 v p-p maximum 1.0 v p-p input bias current 1 ua input full-scale matching 1.5 %fs brightness level adjustment 62 %fs switching performance hsync input frequency 15 200 khz pll clock rate 12 220 mhz pll jitter 500 ps p-p sampling phase tempco tbd ps/ c digital inputs input voltage, high (v ih ) 2.5 v input voltage, low (v il ) 0.8 v input current, high (i ih ) -1.0 ua input current, low (i il ) 1.0 ua input capacitance 5 pf digital outputs output voltage, high (v oh ) vddp-0.1 v output voltage, low (v ol ) 0.1 v dynamic performance analog bandwidth, full power 250 mhz channel to channel matching 0.5% full-scale specifications are subject ed to change without notice. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 9 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. absolute maximum ratings parameter symbol min typ max units 3.3v supply voltages v vdd_33 -0.3 3.6 v 1.8v supply voltages v vdd_18 -0.3 1.98 v input voltage (5v tolerant inputs) v in5vtol -0.3 5.0 v input voltage (non 5v tolerant inputs) v in -0.3 v vdd_33 v ambient operating temperature t a 0 70 c storage temperature t stg -40 150 c junction temperature t j 150 c thermal resistance (junction to air) natural conversion ja 34 c/w thermal resistance (junction to case) natural conversion jc 6.0 c/w note: stress above those listed under absolute maximum rating may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide model temperature range package description package option TSUM16AK 0 c to +70 c pqfp 128 tsum16awk 0 c to +70 c pqfp 128 TSUM16AK-lf 0 c to +70 c pqfp 128 tsum16awk-lf 0 c to +70 c pqfp 128 note: product suffix lf represents lead-free version, and w represents mwe function. marking information TSUM16AK operation code b date code (yyww) lot number operation code a part number disclaimer mstar semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. no responsibility is assumed by mstar semiconductor arising out of the application or user of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. electrostatic charges accumulate on both test equipment and human body and can discharge without detection. TSUM16AK comes with esd protection circuitry; however, the device may be permanently damaged when subjected to high energy discharges. the device should be handled with proper esd precautions to prevent malfunction and performance degradation. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 10 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. revision history document description date TSUM16AK_ds_v01 ? initial release mar 2005 TSUM16AK_ds_v02 ? updated register table apr 2005 TSUM16AK_ds_v03 ? updated register table may 2005 TSUM16AK_ds_v04 ? updated register table nov 2005 TSUM16AK_ds_v10 ? official release ? updated register table nov 2005 free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 11 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. mechanical dimensions l e e 1 e 2 d d1 d2 l 1 a1 a2 a c b e q q 1 seating plane gauge plane 0.25mm r1 r2 s q 2 q 3 millimeter inch symbol min. nom. max. min. nom. max. a - - 3.40 - - 0.134 a1 0.25 - - 0.010 - - a2 2.50 2.72 2.90 0.098 0.107 0.114 d 23.20 0.913 d1 20.00 0.787 d2 18.50 0.728 e 17.20 0.677 e1 14.00 0.551 e2 12.50 0.492 r1 0.13 - - 0.005 - - r2 0.13 - 0.30 0.005 - 0.012 millimeter inch symbol min. nom. max. min. nom. max. q 0 - 7 0 - 7 q 1 0 - - 0 - - q 2, q 3 (alloy) 7 ref 7 ref q 2, q 3 (copper) 15 ref 15 ref b 0.170 0.200 0.270 0.007 0.008 0.011 c 0.11 0.15 0.23 0.004 0.006 0.009 e 0.50 bsc. 0.020 bsc. l 0.73 0.88 1.03 0.029 0.035 0.041 l1 1.60 ref 0.063 ref s 0.20 - - 0.008 - - free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 12 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. register description general control register index mnemonic bits description regbk 7:0 default : access : r/w porr 7 power on reset ready (read only). 0: not ready. 1: ready. - 6:4 reserved. - 3 reserved. - 2 reserved. 00h regbk[1:0] 1:0 register bank select. 00: register of digital image processor. 01: register of internal adc, dvi/hdcp receiver. 10: register of timing controller. 11: register of ace function. adc register (bank = 01, registers 0000h ~ 00ffh) adc register (bank=01) index mnemonic bits description dbfc 7:0 default : 0x00 access : r/w - 7:1 reserved. 01h dbvb 0 double buffer load at vertical blanking. 0: disable. 1: enable. plldivm 7:0 default : 0x69 access : r/w 02h plldiv[11:4] 7:0 pll divider ratio. when bank 1 register 3dh[4] = 0 adc pll will multiply the horizontal line frequency by plldiv[11:0] + 3 to generate the adc sampling clock. when bank 1 register 3dh[4] = 1 adc pll will multiply the horizontal line frequency by (plldiv[11:0] +3)*2 to generate the adc sampling clock. plldivl 7:0 default : 0x50 access : r/w plldiv[3:0] 7:4 pll divider ratio. please see the description of plldiv[11:4]. - 3 reserved. 03h stat[2:0] 2:0 status select. selects 1/8 internal pll status values to read from register 16h. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 13 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. adc register (bank=01) redgain 7:0 default : 0x80 access : r/w 04h redgain 7:0 red channel gain adjust. grngain 7:0 default : 0x80 access : r/w 05h grngain 7:0 green channel gain adjust. blugain 7:0 default : 0x80 access : r/w 06h blugain 7:0 blue channel gain adjust. redofst 7:0 default : 0x80 access : r/w 07h redofst 7:0 red channel offset adjust. grnofst 7:0 default : 0x80 access : r/w 08h grnofst 7:0 green channel offset adjust. bluofst 7:0 default : 0x80 access : r/w 09h bluofst 7:0 blue channel offset adjust. clpace 7:0 default: 0x05 access : r/w 0ah clpace 7:0 clamp placement based on adc clock. cldur 7:0 default : 0x05 access : r/w 0bh cldur 7:0 clamp duration based on adc clock. gctrl 7:0 default : 0x82 access : r/w hsp 7 input hsync polarity. 0: active low. 1: active high. eclk 6 external clock. 0: adc clock from internal adc pll. 1: adc clock from external clock. hsle 5 hs lock edge. determines which edge of hsync the adc pll will lock to, assuming hsp is set correctly. 0: leading edge of hsync. 1: trailing edge of hsync. clpe 4 clamp reference edge. 0: trailing edge of hsync. 1: leading edge of hsync. ccdis 3 disable pll watchdog timer. 0: always enable clamp. 1: disable clamp during active coast. 0ch wdis 2 disable watchdog timer. 0: enable pll watchdog timer. a watchdog timer is used to reset the adc pll when the pll remains much higher than plldiv*hsync_freq for a predetermined period. see wdtol (register 30h). free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 14 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. adc register (bank=01) 1: disable pll watchdog timer (should only be used when dpl_s = 0). cstp 1 coast polarity. 0: active low. 1: active high. drbs 0 dvi input red/blue swap (dvi features only). 0: normal. 1: swap. bwcoef 7:0 default : 0x02 access : r/w dmode[1:0] 7:6 damping coefficient mode control. 00: default value C backward compatibility mode. 01: reserved. 10: automatic dcoef control (recommended mode). 11: reserved. 0dh bwcoef[5:0] 5:0 pll loop filter control. fcoef 7:0 default : 0x09 access : r/w 7:5 reserved. 0eh freqcoef[4:0] 4:0 pll loop filter control. dcoef 7:0 default : 0x05 access : r/w 7:4 reserved. 0fh dampcoef[3:0] 3:0 pll loop filter control. clkctrl1 7:0 default : 0x08 access : r/w - 7 reserved. 10h phase[6:0] 6:0 clock phase adjust (should be always set to phasecc + 8). clkctrl2 7:0 default : 0x00 access : r/w - 7 reserved. 11h phasecc[6:0] 6:0 clock phase adjust for adc sampling time point. phase is adjustable between 0 and 360 in 5.6 steps. vcoctrl 7:0 default : 0x15 access : r/w pdgt 7 phase digitizer frequency compensation disable. 12h dpl_s[2:0] 6:4 vco range. sets adc pll frequency range. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 15 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. adc register (bank=01) setcnt[3:0] 3:0 setting time for adc pll phase detector, in adc clock periods. rt_ctl 7:0 default : 0x10 access : r/w sftf 7 dvi error correction enable (dvi feature only). 0: error correction disable. 1: error correction enable. defe 6 dvi r/g/b alignment edge on de (dvi feature only). 0: de leading edge. 1: de trailing edge. wdf 5 dvi word alignment edge on de (dvi feature only). 0: disable. 1: enable. 13h rt_ctl[4:0] 4:0 resistor termination control for dvi (dvi feature only). sog_lvl 7:0 default : 0x10 access : r/w rmid 7 middle clamp of red channel. 0: disable. 1: enable (used when ypbpr input). bmid 6 middle clamp of blue channel. 0: disable. 1: enable (used when ypbpr input). sogflt 5 sog filter (low-pass filter on sog input). 0: disable. 1: enable. 14h sog_lvl[4:0] 4:0 sog trigger level. 5 b00000: 10mv; 5 b00001: 20mv; 5 b11110: 310mv; 5 b11111: 320mv. hs_lvl 7:0 default: 0x00 access : r/w adcbw[2:0] 7:5 adc bandwidth. - 4:3 reserved. 15h hl_lvl[2:0] 2:0 hsync trigger level. status1 7:0 default: - access : ro note: pll status is read based on stat[2:0] (reg_10h and reg_11h). stat2 stat[1:0] 0 00 7 lock: pll lock status. if 1, pll is in lock. 16h 6 iq: pll lock status. if 1, pll is in stable lock, and now capable of filtering spurious hsync inputs. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 16 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. adc register (bank=01) 5 slow. 4 fast. 3:0 reserved. - 7:0 default : - access : - 17h - 7:0 reserved. status5 7:0 default: - access : ro 18h rcmp[7:0] 7:0 dvi termination resistor status in 2 s complement (dvi feature only). positive value represents resistor value on low side, and rt_ctl needs to adjust to higher values for compensation. negative value represents resistor value on high side, and rt_ctl needs to adjust to lower values for compensation. status4 7:0 default: access : ro 19h ph_stat[7:0] 7 dvi phase status indicator in 2 s complement (dvi feature only). status5 7:0 default : - access : ro 1ah ph_stat[15:8] 7 dvi phase status indicator in 2 s complement (dvi feature only). dvi_phr 7:0 default : 0x80 access : r/w ovpr 7 1bh ovphr 6:0 freeze and override dvi red channel pll phase selection with ovphr[6:0]. dvi_phg 7:0 default : 0x80 access : r/w ovpg 7 1ch ovphg 6:0 freeze and override dvi red channel pll phase selection with ovphg[6:0]. dvi_phb 7:0 default : 0x80 access : r/w ovpb 7 1dh ovphb 6:0 freeze and override dvi red channel pll phase selection with ovphb[6:0]. dvi_erst 7:0 default : 0x00 access : r/w 1eh drr_st[7:0] 7:0 dvi bit error status indicator. dvi_erth 7:0 default : 0x00 access : r/w err_th[7:0] / clpskip[7:0] 7:0 dvi bit error tolerance threshold. / clamp skipping on/select in adc mode. clpskip[7] 7 clamp skipping on. 1fh clpskip[3:0] 3:0 clamping skipping select. testen 7:0 default : 0x00 access : r/w 20h testen 7 enable test mode. 0: disable. 1: enable. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 17 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. adc register (bank=01) - 6 reserved. errchsel[1:0] 5:4 channel select for dvi error status indicator (dvi feature only). 00: red channel. 01: green channel. 10: blue channel. 11: reserved. errd 3 dvi bit error status indicator (err_st) enable (dvi feature only). 0: normal. 1: read status. rdst 2 terminator resistance status (rcmp) and dvi phase status enable (dvi feature only). 0: normal. 1: read status. phsel[1:0] 1:0 channel select for dvi phase status (dvi feature only). 00: red channel. 01: green channel. 10: blue channel. 11: reserved. - 7:0 default : - access : - 21h ~ 2ch - 7:0 reserved. testmod 7:0 default : 0x06 access : r/w - 7 reserved. - 6:5 reserved. 2dh testmod[4:0] 4:0 lvds/rsds differential output swing control. 5 b01000: 5.0ma for lvds/ 2.5ma for rsds 5 b00111: 4.6ma for lvds/ 2.3ma for rsds 5 b00110: 4.2ma for lvds/ 2.1ma for rsds - 7:0 default : - access : - 2eh ~ 2fh - 7:0 reserved. pllctrlv 7:0 default : 0xc6 access : r/w wdtol[1:0] 7:6 pll watchdog threshold. iqclr_th[2:0] 5:3 pll unstable lock threshold. 30h iqset_th[2:0] 2:0 pll stable lock threshold. - 7:0 default : - access : - 31h ~ 5fh - 7:0 reserved. sarctrl1 7:0 default : 0x40 access : r/w 60h sa_smpsts 7 saradc sample status. w: one shot mode saradc sample start. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 18 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. adc register (bank=01) r: one shot mode saradc sample ready. sa_pwrdn 6 saradc power down. 0: active. 1: power down. sa_smpmd 5 saradc sample mode. 0: one shot mode. 1: free-run mode. sa_sngmd 4 saradc single mode. only sample channel at bit[1:0]. - 3:2 reserved. sa_sngmdchn[1:0] 1:0 saradc single mode channel. sarctrl2 7:0 default : 0x20 access : r/w 61h sa_smpclk[7:0] 7:0 saradc sample period * 4 sample clock in one shot mode. sarctrl3 7:0 default : 0x00 access : r/w - 7:4 reserved. 62h sa_in_gpio_sel[3:0] 3:0 saradc input/gpio select. 0: gpio 1: saradc input. sarctrl4 7:0 default : 0x00 access : r/w sar_cur 7:6 select sar adc current. 00: 100%. 01: 120%. 10: 150%. 11: 300%. - 5 reserved. sar_divclk0 4:3 divide clock again. 00: by 4. 01: by 16. 10: by 64. 11: by 256. 63h sar_divclk1 2:0 divide input clock. 000: by 2. 001: by 3. 010: by 4. 011: by 5. 100: by 6. 101: by 7. 110: by 8. 111: by 10. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 19 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. adc register (bank=01) - 7:0 default : - access : - 64h ~ 65h - 7:0 reserved. misc 7:0 default : 0xe7 access : r/w spi_csz_prd[2:0] 7:5 spi csz high period+1 (unit: crystal clock). spi_frd_en 4 spi fast read enable. mcupll_clk_sel [1:0] 3:2 mcu pll clock select. 01: x1. 10: x2. 11: x3. cannot set to 0. 66h - 1:0 reserved. - 7:0 default : - access : - 67h - 7:0 reserved. gpio_i_sel 7:0 default : 0x00 access : r/w - 7:4 reserved. gpio_i_sel[3:2] 3:2 gpio_p07/gpio_p06 current select. 0: 6ma. 1: 12ma. 68h - 1:0 reserved. - 7:0 default : - access : - 69h ~ ffh - 7:0 reserved. digital image processor register (bank = 00, registers 0000h ~ 00ffh) digital image processor register (bank=00) index mnemonic bits description dbfc 7:0 default : 0x80 access : r/w 7:3 reserved. dbl[1:0] 2:1 double buffer load. 00: keep old register value. 01: load new data (auto reset to 00 when load finish). 10: automatically load data at vsync blanking. 11: reserved. 01h dbc 0 double buffer control. 0: double buffer disable. 1: double buffer enable. iselect 7:0 default : 0x00 access : r/w 02h nis 7 output lock mode. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 20 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 0: lock input (input signal exits). 1: free-run (no input signal). stype[1:0] 6:5 input sync type. 00: auto detected. 01: input is separated hsync and vsync. 10: input is composite sync. 11: input is sync-on-green (sog). comp 4 csync/sog select (only useful when stype = 00). 0: csync. 1: sog. csc 3 csc function. 0: disable (rgb -> rgb). 1: enable (ycbcr -> rgb). ihsu 2 input sync usage. when isel=00 or 01: 0: use hsync to perform mode detection, hsout from adc to sample pixel. 1: use hsync only. when isel=10: 0: normal. 1: enable de ahead/delay adjust. when isel=11: 0: normal. 1: output black at blanking. isel[1:0] 1:0 00: analog 1. 01: analog 2. 10: dvi. 11: video. - 7:0 default : - access : - 03h - 7:0 reserved. ipctrl2 7:0 default : 0x18 access : r/w dhsr 7 digital input horizontal sample range. 0: use de as sample range, only v position can be adjusted. 1: use sprhst and sprhdc as sample range, both h and v position can be adjusted. deon 6 de only. hsync and vsync are ignored. 0: disable. 1: enable. 04h ivsd 5 input vsync delay select. 0: delay 1/4 input hsync (recommended). free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 21 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: no delay. hse 4 input hsync reference edge select. 0: from hsync leading edge, default value. 1: from hsync tailing edge. vse 3 input vsync reference edge select. 0: from vsync leading edge, default value. 1: from vsync tailing edge. esls 2 early sample line select. 0: 8 lines. 1: 16 lines. vwrp 1 input image vertical wrap. 0: disable. 1: enable. hwrp 0 input image horizontal wrap. 0: disable. 1: enable. sprvst-l 7:0 default : 0x10 access : r/w, db 05h sprvst[7:0] 7:0 image vertical sample start point, count by input hsync. sprvst-h 7:0 default : 0x00 access : r/w, db 7:3 reserved. 06h sprvst[10:8] 2:0 image vertical sample start point, count by input hsync. when reg. 52, 51, 50 < 90 00 00, sprhst is multiplied by 2 internally. sprhst-l 7:0 default : 0x01 access : r/w, db 07h sprhst[7:0] 7:0 image horizontal sample start point, count by input dot clock. sprhst-h 7:0 default : 0x00 access : r/w, db sprhstlsb 7 back 1 lsb, sample range will move 1 pixel left. ichm1 6 invert a/b channel mode 1(debug mode) ichm2 5 invert a/b channel mode 2(debug mode) - 4 reserved. 08h sprgst[11:8] 3:0 image horizontal sample start point, count by input dot clock. sprvdc-l 7:0 default : 0x10 access : r/w, db 09h sprvdc[7:0] 7:0 image vertical resolution (vertical display enable area count by line). sprvdc-h 7:0 default: 0x00 access : r/w 7:3 reserved. 0ah sprvdc[10:8] 2:0 image vertical resolution (vertical display enable area count by free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 22 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) line). when reg. 52, 51, 50 < 90 00 00, sprvst is multiplied by 2 internally. sprhdc-l 7:0 default : 0x10 access : r/w 0bh sprhdc[7:0] 7:0 image horizontal resolution (horizontal display enable area count by pixel). sprhdc-l 7:0 default : 0x00 access : r/w 7:4 reserved. 0ch sprhdc[11:8] 3:0 image horizontal resolution (horizontal display enable area count by pixel). - 7:0 default : - access : - 0dh ~ 0eh - 7:0 reserved. lyl 7:0 default : 0x00 access : r/w 7:5 reserved. 3lvrcen 4 3 line vertical resolution conversion enable. 0fh lyl[3:0] 3:0 lock y line. devst-l 7:0 default : 0x00 access : r/w 10h devst[7:0] 7:0 output de vertical start. devst-h 7:0 default : 0x00 access : r/w 7:3 reserved. 11h devst[10:8] 2:0 see description for devst[7:0]. dehst-l 7:0 default : 0x03 access : r/w 12h dehst[7:0] 7:0 output de horizontal start. dehst-h 7:0 default : 0x00 access : r/w 7:3 reserved. 13h dehst[10:8] 2:0 see description for dehst[7:0]. devend-l 7:0 default : 0x06 access : r/w 14h devend[7:0] 7:0 output de vertical end. devend-h 7:0 default : 0x00 access : r/w 7:3 reserved. 15h devend[10:8] 2:0 see description for devend[7:0]. dehend-l 7:0 default : 0x00 access : r/w 16h devend[7:0] 7:0 output de horizontal end. dehend-h 7:0 default : 0x00 access : r/w 7:3 reserved. 17h devend[10:8] 2:0 see description for devend[7:0]. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 23 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) oihst-l 7:0 default : 0x00 access : r/w 18h oihst[7:0] 7:0 output image window horizontal start. oihst-h 7:0 default : 0x00 access : r/w 7:3 reserved. 19h oihst[10:8] 2:0 see description for oihst[7:0]. oivend-l 7:0 default : 0x06 access : r/w 1ah oivend[7:0] 7:0 output image window vertical end. oivend-h 7:0 default : 0x00 access : r/w 7:3 reserved. 1bh oivend[10:8] 2:0 see description for oivend[7:0]. oihend-l 7:0 default : 0x00 access : r/w 1ch oihend[7:0] 7:0 output image window horizontal end. oihend-h 7:0 default : 0x00 access : r/w 7:3 reserved. 1dh oihend[10:8] 2:0 see description for oihend[7:0]. vdtot-l 7:0 default : 0x03 access : r/w 1eh vdtot[7:0] 7:0 output vertical total. vdtot-h 7:0 default : 0x00 access : r/w 7:3 reserved. 1fh vdtot[10:8] 2:0 see description for vdtot[7:0]. vsst-l 7:0 default : 0x03 access : r/w 20h vsst[7:0] 7:0 output vsync start (only useful when aovs=1). vsst-h 7:0 default : 0x00 access : r/w 7:4 reserved. vsru 3 vsync register usage. 0: registers 20h C 23h are used to define output vsync. 1: registers 20h and 21h are used to define no signal vsync. registers 22h and 23h are used to define minimum h total. 21h vsst[10:8] 2:0 see description for vsst[7:0]. vsend-l 7:0 default : 0x06 access : r/w 22h vsend[7:0] 7:0 output vsync end (only useful when aovs=1). vsend-h 7:0 default : 0x00 access : r/w db 7:3 reserved. 23h vsend[10:8] 2:0 see description for vsend[7:0]. 24h hdtot-l 7:0 default : 0x03 access : r/w db free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 24 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) hdtot[7:0] 7:0 output horizontal total. hdtot-h 7:0 default : 0x00 access : r/w 7:4 reserved. 25h hdtot[11:8] 3:0 see description for hdtot[7:0]. hsend 7:0 default : 0x00 access : r/w 26h hsend[7:0] 7:6 output hsync pulse width. osctrl1 7:0 default : 0x4c access : r/w aovs 7 auto output vsync. 0: ovsync is defined automatically. 1: ovsync is defined manually (register 0x20 C 0x23). - 6 reserved. hrsm 5 hsync remove mode. 0: normal. 1: remove hsync when gpoa (bank 2 register 0x62 C 0x6a) is low. vsgp 4 vsync use gpo9. 0: disable. 1: enable (using bank 2 register 0x59 C 0x61 to define ovsync). ehtt 3 even h total. 0: enable, output h total always be even pixels. 1: disable, output h total always be odd pixels. - 2 reserved. ahrt 1 auto h total and read start tuning enable. 0: disable. 1: enable. 27h ctrl 0 0: disable. 1: enable. osctrl2 7:0 default : 0x00 access : r/w 28h - 7:0 reserved. - 7:0 default : - access : - 29h - 7:0 reserved. brc 7:0 default : 0x00 access : r/w - 7:1 reserved. 2ah brc 0 brightness function, reference to register 2bh, 2ch, and 2eh. 0: off. 1: on. 2bh bcr 7:0 default : 0x80 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 25 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) bcr[7:0] 7:0 brightness coefficient C red color. 00h: -128. 80h: 0, default value. ffh: +127. bcg 7:0 default : 0x80 access : r/w 2ch bcg[7:0] 7:0 brightness coefficient C green color. 00h: -128. 80h: 0, default value. ffh: +127. bcb 7:0 default : 0x80 access : r/w 2dh bcb[7:0] 7:0 brightness coefficient C blue color. 00h: -128. 80h: 0, default value. ffh: +127. cntr 7:0 default : 0x00 access : r/w - 7 reserved. cnren[6:5] 6:5 contrast noise rounding enable. 11: enable. cclr 4 contrast coefficient lsb C red color. cclg 3 contrast coefficient lsb C green color. cclb 2 contrast coefficient lsb C blue color. cntt 1 contrast type select. 0: use 0 as center point. 1: use 128 as center point. 2eh cntr 0 contrast function. 0: off. 1: on. ccr 7:0 default : 0x80 access : r/w 2fh ccr[7:0] 7:0 contrast coefficient C red color. 00h: 0.0000000. 80h: 1.0000000. default value. ffh: 1.1111111. ccg 7:0 default : 0x80 access : r/w 30h ccg[7:0] 7:0 contrast coefficient C green color. 00h: 0.0000000. 80h: 1.0000000. default value. ffh: 1.1111111. ccb 7:0 default : 0x80 access : r/w 31h ccb[7:0] 7:0 contrast coefficient C blue color. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 26 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 00h: 0.0000000. 80h: 1.0000000. default value. ffh: 1.1111111. fwc 7:0 default : 0x00 access : r/w - 7:6 reserved. - 5 reserved. - 4 reserved. - 3 reserved. - 2:1 reserved. 32h fwc 0 border color (will be used when output is in free-run mode). 0: off. 1: on. fcr 7:0 default : 0x00 access : r/w 33h fcr[7:0] 7:0 border color C red channel. fcg 7:0 default : 0x00 access : r/w 34h fcg[7:0] 7:0 border color C green channel. fcr 7:0 default : 0x00 access : r/w 35h fcb[7:0] 7:0 border color C blue channel. dithctrl 7:0 default : 0x02 access : r/w dithg[1:0] 7:6 dither coefficient for g channel. dithb[1:0] 5:4 dither coefficient for b channel. srot 3 spatial coefficient rotate. 0: disable. 1: enable. trot 2 temporal coefficient rotate. 0: disable. 1: enable. obn 1 output bits number (used for 8/10-bit gamma). 0: 8-bit output. 1: 6-bit output (power on default value). 36h dith 0 dither function. 0: off. 1: on. dithcoef 7:0 default : 0x20 access : r/w tl[1:0] 7:6 top C left dither coefficient. tr[1:0] 5:4 top C right dither coefficient. 37h bl[1:0] 3:2 bottom C left dither coefficient. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 27 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) br[1:0] 1:0 bottom C right dither coefficient. trfn 7:0 default : 0x00 access : r/w psrd 7 pseudo random, resets every 4 frames. 0: enable. 1: disable. ndmd 6 noise dithering method. datp 5 dither based on auto phase threshold. 0: disable. 1: enable. drt 4 dither rotate type. 0: eor. 1: rotate. dt3 3 dither type 2 control. 0: disable dither type 2. 1: enable dither type 2. dt2 2 dither type 2. 0: output data bits 1 and 0 according to input pixel value. 1: output data bits 2, 1 and 0 according to input pixel value. dt1 1 dither type 1. 0: normal. 1: output data bits 1 and 0 are always 00. 38h tdfnc 0 tempo-dither frame number control. 0: tempo-dither every frame. 1: tempo-dither every 2 frames. dithctrl2 7:0 default : 0x00 access : r/w - 7:5 reserved. gammapr 4 gamma protection. - 3 reserved. rsdshsizectrl 2 rsds panel output h size (when 9fh[4]=0). 0: 1280. 1: 1440. - 1 reserved. 39h gateclk 0 gated clock. bfracdiv_l 7:0 default : 0x00 access : r/w 3ah bfracdiv[7:0] 0 blanking fraction divider. bfracdiv_h 7:0 default : 0x00 access : r/w - 7:3 reserved. 3bh bfracdiv[15:8] 7:0 see description for bfracdiv[7:0]. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 28 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) bfracv_l 7:0 default : 0x00 access : ro 3ch bfracv[7:0] 0 blanking fraction value. bfracv_h 7:0 default : 0x00 access : ro - 7:3 reserved. 3dh bfracv[10:8] 2:0 see description for bfracv[7:0]. - 7:0 default : - access : - 3eh ~ 3fh - 7:0 reserved. gammac 7:0 default : 0x00 access : r/w - 7:6 reserved. dithmtype 5 dither function minus type gnren 4 gamma noise round enable. btcs[1:0] 3:2 gamma table channel select. 00: write red channel. 01: write green channel. 10: write blue channel. 11: write red/green/blue channel. gtio 1 gamma table i/o access. 0: disable. 1: enable. 40h gcfe 0 gamma correction function enable. 0: off. 1: on. gammap 7:0 default : 0x00 access : r/w 41h gammap[7:0] 7:0 gamma data port. octrl1 7:0 default : 0x00 access : r/w lcps 7 lvds channel polarity swap (p/n swap). 0: disable. 1: enable. 42h lcs 6 lvds channel swap. 0: disable. 1: enable. when enabled in dual lvds: lva0m/lva3m swap, lva0p/lva3p swap, lva1m/lvackm swap, lva1p/lvackp swap, lvb0m/lvb3m swap, lvb0p/lvb3p swap, lvb1m/lvbckm swap, lvb1p/lvbckp swap. when enabled in single lvds: lva0m/lva3m swap, lva0p/lva3p swap, lva1m/lvackm swap, lva1p/lvackp swap. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 29 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) mlxt 5 msb/lsb exchange type. 0: always reverse bit[7:0]. 1: reverse bit[7:2] when 6-bit panel. ltim 4 lvds ti mode. 0: normal. 1: ti mode. omlx 3 odd channel msb/lsb exchange. 0: normal. 1: exchange. emlx 2 even channel msb/lsb exchange. 0: normal. 1: exchange. orbx 1 odd channel red/blue bus exchange. 0: normal. 1: exchange. erbx 0 even channel red/blue bus exchange. 0: normal. 1: exchange. octrl2 7:0 default : 0x00 access : r/w tcop 7 tcon control pin port select (only used when )bn=1, 6-bit output). 0: use output data port. 1: use video in port. dot 6 differential output type. 0: lvds/rsds. 1: reduced-swing lvds/increased-swing rsds. whts 5 white screen (screen off). 0: disable. 1: enable. blsk 4 black screen (screen off). 0: disable. 1: enable. rev 3 reverse luminosity. 0: off. 1: on. sto 2 stagger output (only used when dpo=1). 0: disable. 1: enable. 43h dpx 1 a/b port swap (only used when dpo=1). 0: disable. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 30 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: enable. dpo 0 dual pixel output. 0: single pixel. 1: dual pixel. octrl3 7:0 default : 0x00 access : r/w - 7:5 reserved. cksel[4:0] 4:0 enable clock of internal control. supposed input interface (adc/dvi) as the left-side. 44h cksel[4] cksel[3] cksel[2] cksel[1] cksel[0] 4 3 2 1 0 enable clock of down-side gpo. enable clock of up-side channel. enable clock of down-side channel. enable clock of right-side gpo. enable clock and output current of right-side channel. please use adc bank register 0x2d bit 7 to control lvds internal clock. 01h: lvds output. 1dh: dual-link rsds output with down-side gpo. 0fh: dual-link rsds output with right-side gpo. 15h: single-link rsds output with down-side gpo. 07h: single-link rsds output with right-side gpo. 00h: ttl output. - 7:0 default : - access : - 45h ~ 4ah - 7:0 reserved. blendc 7:0 default : 0x00 access : r/w - 7 reserved. ckind[3:0] 6:3 color index of color key. 0000: color index 0. 0001: color index 1. 1111: color index 15. when osd register 0x10[7]=1, osd is not backward compatible. when osd register 0x10[7]=0, osd is backward compatible. when 8-color palette is selected, only ckind[2:0] are used. when 16-color palette is selected, osd0xe0 bit[6] is color key bit[3] instead of using ckind[3]. 4bh abm[2:0] 2:0 alpha blending mode. 000: no alpha blending. 001: background alpha blending. 010: foreground alpha blending. 011: color key alpha blending. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 31 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 100: not color key alpha blending. 101: entire osd alpha blending. 11x: reserved. blendl 7:0 default : 0x00 access : r/w - 7:6 reserved. nbm 5 new blending level. 0: original blending level (blendl = 000 means 0% transparency). 1: new blending level (blendl = 000 means 12.5% transparency). - 4:3 reserved. 4ch blendl[2:0] 2:0 osd alpha blending level. 000: 12.5% transparency. 001: 25.0% transparency. 010: 37.5% transparency. 011: 50.0%% transparency. 100: 62.5% transparency. 101: 75.0% transparency. 110: 87.5% transparency. 111: 100% transparency. - 7:0 default : - access : - 4dh ~ 4fh - 7:0 reserved. rdcrh-l 7:0 default : 0x00 access : r/w 50h rdcrh[7:0] 7:0 horizontal resolution down-conversion ratio (4 bits integer, 19 bits fraction), support to 1/15.9999. (don t support horizontal resolution up-conversion) xxxx.xxxxxxxxxxxxxxxxxxx rdcrh-m 7:0 default : 0x00 access : r/w 51h rdcrh[15:8] 7:0 see description for rdcrh[7:0]. rdcrh-h 7:0 default : 0x00 access : r/w rdcenh 7 horizontal resolution down-conversion enable. (don t support horizontal resolution up-conversion) 0: disable. 1: enable. 52h rdcrh[22:16] 6:0 see description for rdcrh[7:0]. rcrv-l 7:0 default : 0x00 access : r/w 53h rcrv[7:0] 7:0 vertical resolution conversion ratio (2 bits integer, 20 bits fraction), support to 1/2.9999. xx.xxxxxxxxxxxxxxxxxxxx free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 32 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) rcrv-m 7:0 default : 0x00 access : r/w 54h rcrv[15:8] 7:0 see description for rcrv[7:0]. rcrv-h 7:0 default : 0x00 access : r/w rcenv 7 vertical resolution conversion enable. 0: disable. 1: enable. vfmd 6 vertical resolution conversion factor mode. 0: n-1/m-1 for vertical resolution conversion factor. 1: n/m for vertical resolution conversion factor. 55h rcrv[21:16] 5:0 see description for rcrv[7:0]. rdcfh 7:0 default : 00x0 access : - rdcfh1[3:0] 7:4 horizontal resolution down-conversion filter for edge. 56h rdcfh2[3:0] 3:0 horizontal resolution down-conversion filter for no edge. rcfv 7:0 default : 0x00 access : - 57h rcfv[7:0] 7:0 vertical resolution conversion filter. 57h 5ah description 00 x bi 11 00 bi 11 22 bg (2) 11 33 bg (1.5) 22 33 bm (1.5) 33 11 bs (0.75) 55 00 cb (0) hdsusg 7:0 default : 0x00 access : - 58h hdsusg[7:0] 7:0 horizontal dsus resolution down-conversion parameter. hdsusl 7:0 default : 0x00 access : - - 7 reserved. hfmd 6 horizontal resolution down-conversion factor mode. 0: n-1/m-1 for horizontal resolution down-conversion factor. 1: n/m for horizontal resolution down-conversion factor. gsr 5 gray scale sensitive register io. 0: disable. 1: enable. tsr 4 text sensitive register io. 0: disable. 1: enable. 59h txtjl[3:0] 3:0 text judge level. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 33 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) vdsusg 7:0 default: 0x00 access : - m_csc_en 7 main window csc enable (rgb-> yuv) s_csc_en 6 ace window csc enable (rgb-> yuv) 5ah vdsusg[5:0] 5:0 vertical dsus resolution conversion parameter. vdsusl 7:0 default: 0x01 access : - mcks 7 manual clock select. 0: auto select. 1: manual select. iock 6 input / fix clock select (when mcks=1). 0: fixclk faster, fixclk defined by reg_d1h, bit[7]. 1: idclk faster. gse 5 gray scale sensitive function enable. 0: disable. 1: enable. tse 4 text sensitive function enable. 0: disable. 1: enable. 5bh dsusl[3:0] 3:0 dsus resolution conversion parameter level. pfen 7:0 default: 0x00 access : r/w - 7:6 reserved. pfcoef-h[4] 5 1: add 2 to coefficient values of pfcoef-h[3:0] (see below). pfcoef-l[4] 4 1: add 2 to coefficient values of pfcoef-l[3:0] (see below). ace_en 3 ace function enable 0: disable 1: enable - 2:1 reserved. 5ch pfen 0 post filter enable. 0: disable. 1: enable. pfcoef 7:0 default: 0x00 access : r/w 5dh pfcoef-h[3:0] 7:4 post filter h coefficient for edge part. 0000: blur C 0.0; 0001: 0.125; 0010: 0.25; 0011: 0.375; 0100: 0.5; 0101: 0.625; 0110: 0.75; 0111: 8.875; free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 34 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1000: no action C 1.0; 1001: 1.125; 1010: 1.25; 1011: 1.375; 1100: 1.5; 1101: 1.625; 1110: 1.75; 1111: sharp C 1.875. pfcoef-l[3:0] 3:0 post filter l coefficient for edge part. 0000: blur C 0.0; 0001: 0.125; 0010: 0.25; 0011: 0.375; 0100: 0.5; 0101: 0.625; 0110: 0.75; 0111: 0.875; 1000: no action C 1.0; 1001: 1.125; 1010: 1.25; 1011: 1.375; 1100: 1.5; 1101: 1.625; 1110: 1.75; 1111: sharp C 1.875. - 7:0 default: 0x00 access : r/w cthrd[7:4] 7:4 coring threshold. - 3 reserved. stp[2:1] 2:1 step. 5eh vden 0 video enable. - 7:0 default : - access : - 5fh ~ 62h - 7:0 reserved. pg_swch 7:0 default : 0x15 access : r/w pg_swch[7] 7 must set to '0' for gpio_p27/pwm1. pg_swch[6] 6 must set to '0' for gpio_p24/pwm2. pg_swch[5] 5 gpio_p16/pwm2 select. 0: pwm2. 1: gpio_p16. 63h pg_swch[4] 4 gpio_p24/pwm2 select. 0: pwm2. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 35 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: gpio_p24. pg_swch[3] 3 gpio_p27/pwm1 select. 0: pwm1. 1: gpio_p27. pg_swch[2] 2 gpio_p25/pwm1 select. 0: pwm1. 1: gpio_p25. pg_swch[1] 1 gpio_p15/pwm0 select. 0: pwm0. 1: gpio_p15. pg_swch[0] 0 gpio_p26/pwm0 select. 0: pwm0. 1: gpio_p26. - 7:0 default : - access : - 64h - 7:0 reserved. ftapen 7:0 default : 0x00 access : r/w - 7:6 reserved. srgbne 5 srgb noise round enable. 0: disable. 1: enable. srbgp 4 srgb precision. 0: normal. 1: shift 2 bits. srgbg 3 srgb go through gamma. 0: bypass gamma. 1: go to gamma. tpp 2 test pattern position. 0: after srgb. 1: before srgb. 65h ffsel[1:0] 1:0 filter function select. 00: disable. 01: enable 3 tap function. 1x: enable srgb function. srgb12 7:0 default : 0x00 access : r/w 66h srgb12[7:0] 7:0 coefficient 12, 1 sign bit, 7 bits. srgb13 7:0 default : 0x00 access : r/w 67h srgb13[7:0] 7:0 coefficient 13, 1 sign bit, 7 bits. 68h srgb21 7:0 default : 0x00 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 36 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) srgb21[7:0] 7:0 coefficient 21, 1 sign bit, 7 bits. srgb23 7:0 default : 0x00 access : r/w 69h srgb23[7:0] 7:0 coefficient 23, 1 sign bit, 7 bits. srgb31 7:0 default : 0x00 access : r/w 6ah srgb31[7:0] 7:0 coefficient 31, 1 sign bit, 7 bits. srgb32 7:0 default : 0x00 access : r/w 6bh srgb32[7:0] 7:0 coefficient 32, 1 sign bit, 7 bits. - 7:0 default : - access : - 6ch ~ 6eh - 7:0 reserved. intmds 7:0 default : 0x00 access : r/w - 7:5 reserved. ilim 4 insert line when interlace mode. 0: do not insert. 1: insert. oddf 3 shift odd field. 0: shift even field. 1: shift odd field. 6fh sln[2:0] 2:0 shift line numbers. 000: shift 0 line between odd and even fields. 001: shift 1 line between odd and even fields. 010: shift 2 line between odd and even fields. 011: shift 3 line between odd and even fields. 1xx: shift 4 line between odd and even fields. - 7:0 default : - access : r/w 71h ~ 77h - 7:0 reserved. atgctrl 7:0 default : 0x00 access : r/w maxr 7 max value flag for red channel (read only). 0: normal. 1: max value (255) value when agr = 0. output over max value (255) when agr = 1. maxg 6 max value flag for green channel (read only). 0: normal. 1: max value (255) value when agr = 0. output over max value (255) when agr = 1. 78h maxb 5 max value flag for blue channel (read only). 0: normal. 1: max value (255) value when agr = 0. output over max value (255) when agr = 1. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 37 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) ace 4 adc calibration enable. 0: disable. 1: enable. agr 3 auto gain result selection. 0: output has max/min value. 1: output is overflow/underflow. atgm 2 auto gain mode. 0: normal mode (result will be cleared every frame). 1: history mode (result remains not cleared till atge = 0). atgr 1 auto gain result ready. 0: result not ready. 1: result ready. atge 0 auto gain function enable. 0: disable. 1: enable. atgst 7:0 default : - access : ro vclp 7 video auto gain mode. 0: rgb mode. 1: ypbpr mode. - 6 reserved. calr 5 calibration value flag for red channel. 0: normal. 1: calibration result (needs to increase offset) when ace = 1. calg 4 calibration value flag for green channel. 0: normal. 1: calibration result (needs to increase offset) when ace = 1. calb 3 calibration value flag for blue channel. 0: normal. 1: calibration result (needs to increase offset) when ace = 1. minr 2 min value flag for red channel. 0: normal. 1: min value (0) present when agr = 0, ace = 0. output under min value (0) when agr = 1, ace = 0. calibration result (needs to decrease offset) when ace = 1. ming 1 min value flag for green channel. 0: normal. 1: min value (0) present when agr = 0, ace = 0. output under min value (0) when agr = 1, ace = 0. calibration result (needs to decrease offset) when ace = 1. 79h minb 0 min value flag for blue channel. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 38 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 0: normal. 1: min value (0) present when agr = 0, ace = 0. output under min value (0) when agr = 1, ace = 0. calibration result (needs to decrease offset) when ace = 1. atfchsel 7:0 default: 0x00 access : r/w - 7:6 reserved. atpchsel[1:0] 5:4 auto phase r/g/b channel select 00: r/g/b 3 channels 01: only r channel 10: only g channel 11: only b channel - 3 reserved. 7ah atgchsel[2:0] 2:0 auto gain r/g/b channel min/max value select. 000: r min value 001: g min value 010: b min value 011: r max value 100: g max value 101: b max value 11x: reserved atoctrl 7:0 default : 0x00 access : r/w jitlr 7 jitter function left / right result for 86h and 87h. 0: left result. 1: right result. jits 6 jitter software clear. 0: not clear. 1: clear. - 5 reserved. jitm 4 jitter function mode. 0: update every frame. 1: keep the history value. jitr 3 jitter function result. 0: no jitter. 1: jitter present. atom 2 auto position function mode. 0: update every frame. 1: keep the history value. 7bh ator 1 auto position result ready. 0: result ready. 1: result not ready. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 39 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) atoe 0 auto position function enable. 0: disable. 1: enable. disable-to-enable needs at least 2 frame apart for ready bit to settle. aovdv 7:0 default : 0x00 access : r/w aovdv[3:0] 7:5 auto position valid data value. 0000: valid if data >= 0000 0000. 0001: valid if data >= 0001 0000. 0010: valid if data >= 0010 0000. 1111: valid if data >= 1111 0000. 7ch - 4:0 reserved. atgvalue 7:0 default: - access : ro 7dh atgvalue[7:0] 7:0 auto gain result based on 7ah[2:0]. aovst-l 7:0 default : - access : ro 7eh aovst [7:0] 7:0 auto position detected result vertical starting point. aovst-h 7:0 default : - access : ro - 7:3 reserved. 7fh aovst[10:8] 2:0 see description for aovst [7:0]. aohst-l 7:0 default : - access : ro 80h aohst[7:0] 7:0 auto position detected result horizontal starting point. aohst-h 7:0 default : - access : ro - 7:4 reserved. 81h aohst[11:8] 3:0 see description for aohst [7:0]. aovend-l 7:0 default : - access : ro 82h aovend[7:0] 7:0 auto position detected result vertical end point. aovend-h 7:0 default : - access : ro - 7:3 reserved. 83h aovend[10:8] 2:0 see description for aovend[7:0]. aohend-l 7:0 default : - access : ro 84h aohend[7:0] 7:0 auto position detected result horizontal end point. aohend-h 7:0 default : - access : ro - 7:4 reserved. 85h aohend[11:8] 2:0 see description for aohend[7:0]. 86h jlr-l 7:0 default : - access : ro free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 40 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) jlr[7:0] 7:0 jitter function detected left/right most point state (previous frame) depend on reg_7bh[7]. jlr-h 7:0 default : - access : ro - 7:3 reserved. 87h jlr[10:8] 2:0 see description for jlr[7:0]. anrf 7:0 default : - access : ro - 7:6 reserved. hnen 5 high level noise reduction enable. 0: disable. 1: enable. bgen 4 background noise reduction enable. 0: disable. 1: enable. - 3 reserved. 88h anlv[2:0] 2:0 auto noise level. 111: noise level = 16. atpgth 7:0 default : 0x01 access : r/w 89h atpgth[7:0] 7:0 auto phase gray scale threshold for atpv3 when atpn4 = 0. atptth 7:0 default : 0x10 access : r/w 8ah atptth[7:0] 7:0 auto phase text threshold for atpv4. atpctrl 7:0 default : 0x00 access : r/w - 7 reserved. gry 6 gray scale detect (read only). txt 5 text detect (read only). apmask[2:0] 4:2 nose mask. 000: mask 0 bit, default value. 001: mask 1 bit. 010: mask 2 bit. 011: mask 3 bit. 100: mask 4 bit. 101: mask 5 bit. 110: mask 6 bit. 111: mask 7 bit. atpr 1 auto phase result ready. 0: result not ready. 1: result ready. 8bh atpe 0 auto phase function enable. 0: disable. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 41 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: enable. atpv1 7:0 default : - access : ro 8ch atpvalue[7:0] 7:0 auto phase value. atpv2 7:0 default : - access : ro 8dh atpvalue[15:8] 7:0 see description for atpvalue[7:0]. atpv3 7:0 default : - access : ro 8eh atpvalue[23:16] 7:0 see description for atpvalue[7:0]. atpv4 7:0 default : - access : ro 8fh atpvalue[31:24] 7:0 see description for atpvalue[7:0]. asctrl 7:0 default : 0x90 access : r/w ivb 7 input vsync blanking status. 0: in display. 1: in blanking. - 6 reserved. dline[1:0] 5:4 delay line. - 3:2 reserved. under 1 under run status. 90h over 0 over run status. lpvp-l 7:0 default : - access : ro 91h lpvp[7:0] 7:0 locking point vertical position. lpvp-h 7:0 default : - access : ro - 7:3 reserved. 92h lpvp[10:8] 2:0 see description for lpvp[7:0]. ifracw-l 7:0 default : - access : ro 93h ifracw[7:0] 7:0 insert fraction width. ifracw-h 7:0 default : - access : r/w - 7 reserved. - 6 reserved. field 5 field select.. sfracu 4 stop fraction update. - 3 reserved. 94h ifracw[10:8] 2:0 see description for ifracw[7:0]. (read only) lvsst-l 7:0 default : - access : ro 95h lvsstat[7:0] 7:0 locking vertical total line number. 96h lvsst-h 7:0 default : - access : ro free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 42 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) - 7 reserved. - 6:3 reserved. lvsstat[10:8] 2:0 see description for lvsstat[7:0]. lhtst-l 7:0 default : - access : ro 97h lhtstat[7:0] 7:0 locking htotal status. lhtst-h 7:0 default : - access : ro - 7:3 reserved. 98h lhtstat[10:8] 2:0 see description for lhtstat[7:0]. lfrst-l 7:0 default : 0x00 access : r/w 99h lftstat[7:0] 7:0 locking fraction status. lfrst-h 7:0 default : 0x00 access : r/w - 7:3 reserved. 9ah lftstat[10:8] 2:0 see description for lftstat[7:0]. lmargin 7:0 default : 0x00 access : r/w 9bh lhttmgn[7:0] 7:0 locking h total margin. lrsv-l 7:0 default : 0x00 access : r/w 9ch lrsvalue[7:0] 7:0 locking read start value. lrsv-h 7:0 default : 0x00 access : r/w - 7:3 reserved. 9dh lrsvalue[10:8] 2:0 see description for lrsvalue[7:0]. lmargin 7:0 default : 0x00 access : r/w 9eh lsscmgn[7:0] 7:0 locking ssc margin. rsdshsizemd 7:0 default : - access : - - 7:5 reserved. rsdshsizemd 4 rsds panel output h size control. 0: rsds h size is defined by 39h[2]. 1: rsds h size is defined by output h ds size. 9fh - 3:0 reserved. osdioa 7:0 default : 0x10 access : r/w osbm 7 osd sram i/o access burst mode. 0: disable. 1: enable. clr 6 osd clear bit (write only). 0: normal. 1: clear code with 00h, attribute with 00h. a0h cp 5 osd 256 color palette i/o access. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 43 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 0: disable. 1: enable. rf 4 osd ram font i/o access. 0: disable. 1: enable. dc 3 osd display code i/o access. 0: disable. 1: enable. da 2 osd display attribute i/o access. 0: disable. 1: enable. orbw 1 osd register burst write mode. 0: disable. 1: enable. - 0 reserved. osdra 7:0 default : 0x00 access : r/w - 7 reserved. a1h osdra[6:0] 6:0 osd register address port. osdrd 7:0 default : 0x00 access : r/w a2h osdrd[7:0] 7:0 osd register data port. ramfa 7:0 default: access : r/w a3h ramfa[7:0] 7:0 osd ram font address port. ramfd 7:0 default : 0x00 access : r/w a4h ramfd[7:0] 7:0 osd ram font data port. dispca-l 7:0 default : 0x00 access : r/w a5h dispca[7:0] 7:0 osd display code address code. dispca-h 7:0 default : 0x00 access : r/w - 7:2 reserved. a6h dispca[9:8] 1:0 see description for dispca[7:0]. dispcd 7:0 default : 0x00 access : r/w a7h dispcd[7:0] 7:0 osd display code data port. dispaa-l 7:0 default : 0x00 access : r/w a8h dispaa[7:0] 7:0 osd display attribute address port. dispaa-h 7:0 default : 0x00 access : r/w - 7:3 reserved. a9h dispaa[10:8] 2:0 see description for dispaa[7:0]. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 44 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) dispad 7:0 default : 0x00 access : r/w aah dispad 7:0 osd display attribute data port. bank 0 register 0xd0[0] = 0 fsm 7:0 default : 0x00 access : r/w fsmen 7 frame rate control enable. 0: disable. 1: enable. fsmratio[3:0] 6:3 output frame rate / input frame rate. bit[3]: 1/2; bit[2]: 1/4; bit[1]: 1/8; bit[0]: 1/16. - 2:0 reserved. bank 0 register 0xd0[0] = 1 tstdata 7:0 default : 0x00 access : r/w abh tstdata[7:0] 7:0 lvds/rsds test mode data. when lvds output, use tstdata[7:1]. when rsds output, use tstdata[7:0]. 256cpa 7:0 default : - access : wo ach 256cpa[7:0] 7:0 osd 256 color palette address port. 256cpd 7:0 default : - access : wo adh 256cpd[7:0] 7:0 osd 256 color palette data port. osddf 7:0 default : 0x00 access : r/w ramfa[8] 7 see description for ramfa[7:0]. - 6:4 reserved. dispcd[8] 3 see description for dispcd[7:0]. aeh - 2:0 reserved. - 7:0 default : - access : - afh - 7:0 reserved. wdten 7:0 default : 0x01 access : r/w - 7:2 reserved. wdtc 1 watchdog timer clear (protected by wdtkey). 0: normal. 1: clear. b0h wdte 0 watchdog timer enable (protected by wdtdey). 0: disable. 1: enable. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 45 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) wdtkey 7:0 default : 0x00 access : r/w b1h wdtkey 7:0 watchdog timer enable key. to disable/clear watchdog timer, you must first write the wdtkey with 55h, aah to unlock. wdtcnt 7:0 default : 0x03 access : r/w b2h wdtcnt 7:0 watchdog timer counter. the clock of watchdog timer is frequency of xtal/(256*1024). dvi_ddcen 7:0 default : 0x1e access : r/w csok 7 ddc check sum (read only). 0: check sum not okay. 1: check sum okay. csok1 6 ddc check sum1 (read only). 0: check sum1 not okay. 1: check sum1 okay. mstr_fnsh 5 ddc master finish. already access 128 or 256 byte data (read only). 0: not finish. 1: finish. mstr_ok 4 ddc master receives 128 acks. 0: ng. 1: ok. f128_adc 3 the order of the edid data saved in 24c16. 0: 0-127->dvi, 12-255->adc 1: 0-127->adc, 128-255->dvi sel256 2 the master download 128 or 256 bytes 0: 128 bytes. 1: 256 bytes dmen 1 ddc master function enable. 0: disable. 1: enable. b3h dmstart 0 ddc master function start 0: no action. 1: start dvi_ctrl 7:0 default : 0x8a access : r/w d_en1 7 dvi ddc function enable. 0: disable. 1: enable. b4h dflt 6 ddc filter. 0: enable. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 46 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: disable. diwp 5 dvi ddc two-wire serial bus bus write protect. 0: enable. 1: disable. bypass_ddc 4 bypass ddc ports to master ports 0: not bypass 1: bypass bypass_sel 3 bypass selection 0: adc 1: dvi d_bsy1 2 ddc busy (read only). 0: not busy. 1: busy. d_rw1 1 ddc last read/write status (read only). 0: write. 1: read. d_dty1 0 ddc sram dirty status (read/clear). 0: not dirty. 1: dirty. dvi_ddc_last 7:0 default : - access : ro - 7 reserved. b5h ddc_last1[6:0] 6:0 ddc last r/w address. dvi_ddcaddr 7:0 default : 0x8a access : r/w en_read 7 enable ddc sram to be read. b6h ddc_addrp1[6:0] 6:0 ddc address port. dvi_ddcdata 7:0 default : 0x00 access : r/w b7h ddcdatap1[7:0] 7:0 ddc data port. adc_ddcen 7:0 default : 0x1e access : r/w d_en1 7 adc ddc function enable. 0: disable. 1: enable. - 6 reserved. ddc_nwprtct 5 ddc sram written by iic protection. 0: not protected. 1: protected. b8h slew_ctrl 4:3 ddc slew control. 0: no delay when drive 1. 1: delay 1 clock when drive 1. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 47 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 10: delay 2 clocks when drive 1. 11: delay 3 clocks when drive 1. d_bsy1 2 ddc busy (read only). 0: not busy. 1: busy. d_rw1 1 ddc last read/write status (read only). 0: write. 1: read. d_dty1 0 ddc sram dirty status (read/clear). 0: not dirty. 1: dirty. d_dty1. adc_ddc_last 7:0 default : - access : ro - 7 reserved. b9h ddc_last1[6:0] 6:0 ddc last r/w address. adc_ddcaddr 7:0 default : 0x8a access : r/w en_read 7 enable ddc sram to be read. bah ddc_addrp1[6:0] 6:0 ddc address port. adc_ddcdata 7:0 default : 0x00 access : r/w bbh ddcdatap1[7:0] 7:0 ddc data port. miscfc 7:0 default : 0x00 access : r/w aft 7 atp filter for text (4 frames). 0: disable. 1: enable. idhtt 6 de only mode htt count by idclk. 0: disable. 1: enable. vsgr 5 vsync glitch removal with line less than 2 (de only). 0: disable. 1: enable. vsp 4 vsync protect with v total (de only). 0: disable. 1: enable. lbgc 3 lb clock no gating mode. 0: disable. 1: enable. bch degp 2 de only mode glitch protect for position. 0: disable. 1: enable. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 48 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) - 1:0 reserved. hdcpctrl 7:0 default : 0x00 access : r/w over2pin 7:6 0: not toggling (default). 1: toggling. - 5:4 reserved. - 3 reserved hdcps 2 hdcp select. 0: 74 register (from two-wire serial bus, id =74h) (default). 1: from internal hdcp sram. bdh hdcpadr[9:8] 1:0 hdcp address port (default=0), bit 9 is reserved. hdcpadr 7:0 default : 0x16 access : r/w beh hdcpadr[7:0] 7:0 hdcp address port (default=0), bit 9 is reserved. hdcpdat 7:0 default : 0x00 access : r/w bfh hdcpdat[7:0] 7:0 hdcp data port. dpmstatus 7:0 default : 0x08 access : r/w vs 7 vsync toggling status. 0: not toggling. 1: toggling. hs 6 hsync toggling status. 0: not toggling. 1: toggling. scdt 5 scdt status. 0: no scdt. 1: scdt valid. dev 4 de with valid blanking. 0: not valid. 1: valid. autoon 3 hardware power on upon detecting valid dvi input. 0: disable. 1: enable. auto 2 hardware auto detection on dvi input. 0: disable. 1: enable. manual 1 manual detection on dvi input. 0: off. 1: on. c0h manualgo 0 manual detection trigger, auto clear to 0 if finish. 0: off. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 49 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: on. note: this register is only valid when f0h[1:0] = 2 b10. dpmctl 7:0 default : 0x00 access : r/w dpmprd 7:6 hardware auto detection cycle time. 00: default. 01: short. 10: shortest. dmppulse 5:3 hardware auto detection pulse width manual detection pm dvi input. 000: shortest. 111: longest. demon 2 dvi de monitor enable. 0: disable. 1: enable. hvmon 1 dvi hsync and vsync monitor enable. 0: disable. 1: enable. c1h hmon 0 dvi hsync monitor enable. 0: disable. 1: enable. note: this register is only valid when f0h[1:0] = 2 b10. pwmdiv0 7:0 default : 0x00 access : r/w c2h pwmdiv0[7:0] 7:0 pwm clock divider for pwm0. pwm0c 7:0 default : 0x00 access : r/w c3h pwm0c[7:0] 7:0 pwm0 coarse adjustment. pwm_div1 7:0 default : 0x00 access : r/w c4h pwm_div1[7:0] 7:0 pwm clock divider for pwm1. pwm1c 7:0 default : 0x00 access : r/w c5h pwm1c[7:0] 7:0 pwm1 coarse adjustment. pwm_div2 7:0 default : 0x00 access : r/w c6h pwm_div2[7:0] 7:0 pwm clock divider for pwm2. pwm2c 7:0 default : 0x00 access : r/w c7h pwm2c[7:0] 7:0 pwm2 coarse adjustment. pwmext 7:0 default : 0x00 access : r/w - 7 reserved. c8h - 6 reserved. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 50 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) - 5 reserved. - 4 reserved. pwm2[8] 3 pwm2 bit 8. pwm1[8] 2 pwm1 bit 8. pwm0[8] 1 pwm0 bit 8. - 0 reserved. - 7:0 default : 0x00 access : - c9h - 7:0 reserved. intctrol 7:0 default : 0x00 access : r/w hchgm 7 hsync changing detect method. 0: interrupt only occurred at start and end of transition. 1: interrupt occurred at every line. dcmd 6 dvi clock missing detected (read only; dvi feature only, independent of bank 0 register 0x02h, isel[1:0]). 0: dvi clock is ok, freq(dvi)>freq(xtal)*ebh/128. 1: dvi clock is missing, freq(dvi) TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 51 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: generate a level trigger interrupt. intpulse 7:0 default : 0x0f access : r/w cbh intpulse[7:0] 7:0 interrupt pulse width by reference clock. intsta 7:0 default : 0x00 access : r/w cch intsta[7:0] 7:0 interrupt status byte a. bit 7: input vsync changed (co-work with register e7h). bit 6: input hsync changed (co-work with register e6h). bit 5: input vsync disappear. bit 4: input hsync disappear. bit 3: input vsync edge. bit 2: input hsync edge. bit 1: adc0 hsync0 pin toggling (independent with reg_02h, isel[1:0]). bit 0: composite sync / sog status change. intstb 7:0 default : 0x06 access : r/c cdh intstb[7:0] 7:0 interrupt status control byte b. bit 7: auto phase ready. bit 6: auto position ready. bit 5: auto gain ready. bit 4: jitter detected. bit 3: adc1 hsync1 pin toggling. bit 2: dvi clock status change; no clock <-> with clock. bit 1: watchdog timer. bit 0: under-run / over-run occurred. intena 7:0 default : 0x00 access : r/c ceh intena[7:0] 7:0 interrupt enable control byte a. 0: disable interrupt. 1: enable interrupt. intenb 7:0 default : 0x00 access : r/w cfh intenb[7:0] 7:0 interrupt enable control byte a. 0: disable interrupt. 1: enable interrupt. pllctrl1 7:0 default : 0x00 access : r/w xout 7 enable pwm1 as xtal clock output. 0: disable. 1: enable. d0h eock 6 use external clock (pin #) as output dot clock. 0: disable (use internal dot clock). 1: enable (use external dot clock). free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 52 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) xdiv 5:4 xtal clock divided by: 00: 16; 01: 08; 10: 04; 11: 01. bpm 3 bypass clock mode (idclk as odclk). 0: disable. 1: enable. tstm 2 test mode. 0: disable. 1: enable. pten 1 pll test register protect bit. 0: disable. 1: enable. lrtm 0 lvds/rsds test mode enable. 0: disable. 1: enable. pllctrl2 7:0 default : 0x00 access : r/w mppdiv 7 master pll post divider. 0: div 3 (143 mhz). 1: div 2.5 (172 mhz), for output dot clock higher than 143 mhz (vertical = 85 mhz). lp_por 6 output pll power on reset. lp_rst 5 output pll reset. lp_pd 4 output pll power down. mp_k 3 master pll output frequency divided by 2. mp_port 2 master pll power on reset. mp_rst 1 master pll reset. d1h mp_pd 0 master pll power down. mpll_m 7:0 default : 0x6f access : r/w mp_ictrl[2:0] 7:5 master pll current control. d2h mpll_m[4:0] 4:0 master pll divider. lpll_m 7:0 default : 0x02 access : r/w - 7:6 reserved. sdmd 5 output pll spread spectrum mode. 0: normal. 1: reverse for mode 1. d3h lpll_m[4:0] 4:0 output pll divider 1. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 53 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) lpll_ctl2 7:0 default : 0x0b access : r/w - 7:6 reserved. lp_tp 5 output pll type. 0: lvds. 1: rsds/ttl. lp_k[1:0] 4:3 output pll divider 2. 00: 8; 01: 4; 10: 2; 11: 1. d4h lp_ictrol[2:0] 2:0 output pll current control. lpll_set 7:0 default : 0x44 access : r/w, db d5h lp_set[7:0] 7:0 output pll set. lpll_set 7:0 default : 0x55 access : r/w, db d6h lp_set[15:8] 7:0 see description for lp_set[7:0]. lpll_set 7:0 default : 0x24 access : r/w, db d7h lp_set[23:16] 7:0 see description for lp_set[7:0]. lpll_step 7:0 default : 0x20 access : r/w, db d8h lpll_step[7:0] 7:0 output pll spread spectrum step. lpll_step 7:0 default : 0x00 access : r/w, db - 7:3 reserved. d9h lpll_step[10:8] 2:0 see description for lpll_step[7:0]. lpll_span 7:0 default : 0x00 access : r/w, db dah lp_span[7:0] 7:0 output pll spread spectrum span. lpll_span 7:0 default : 0x00 access : r/w, db - 7:3 reserved. dbh lp_span[10:8] 2:0 see description for lp_span[7:0]. mpll_tst 7:0 default : 0x00 access : r/w dch mp_test[7:0] 7:0 lpll_tsta 7:0 default : 0x00 access : r/w ddh lp_testa[7:0] 7:0 lpll_tstd 7:0 default : 0x00 access : r/w lp_lsta 7 lpll lock status. deh lp_testd[7:0] 6:0 - 7:0 default : access : - dfh - 7:0 reserved. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 54 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) status1 7:0 default : - access : ro - 7:4 reserved. ihsm 3 input normalized hsync pin monitor. show input hsync pin directly. ivsm 2 input normalized vsync pin monitor. show input vsync pin directly. ohsm 1 output normalized hsync pin monitor. show output hsync pin directly. e0h ovsm 0 output normalized vsync pin monitor. show output vsync pin directly. status2 7:0 default : - access : ro vsact 7 input vsync active. 0: not detected. 1: detected. hsact 6 input hsync active. 0: not detected. 1: detected. csd 5 composite sync detected status. 0: input is not composite sync. 1: input is detected as composite sync. sogd 4 sync-on-green detected status. 0: input is not sog. 1: input is detected as sog. intm 3 interlace / non-interlace detecting result by this chip. 0: non-interlace. 1: interlace. intf 2 input odd/even field detecting result by this chip. 0: even. 1: odd. ihsp 1 incoming input hsync polarity detecting result by this chip. 0: active low. 1: active high. e1h ivsp 0 incoming input vsync polarity detecting result by this chip. 0: active low. 1: active high. vtotal-l 7:0 default : - access : ro e2h vtotal[7:0] 7:0 input vertical total, count by hsync. vtotal-h 7:0 default : - access : ro e3h - 7:3 reserved. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 55 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) vtotal[10:8] 2:0 see description for vtotal[7:0]. hsprd-l 7:0 default : - access : ro e4h hsprd[7:0] 7:0 input horizontal period, count by reference clock. hsprd-h 7:0 default : - access : ro ihdm 7 input hsync period detect mode. 0: one line. 1: 16 lines. - 6:5 reserved. e5h hsprd[12:8] 4:0 see description for hsprd[7:0]. hstol 7:0 default : 0x05 access : r/w vs2hs 7 input vsync too close to input hsync. def 6 de follow mode (for de to de period is not fixed). e6h hstol[5:0] 5:0 hsync tolerance. 5: default value. vstol 7:0 default : 0x01 access : r/w - 7 reserved. - 6 reserved. angf 5 auto no signal filter mode. ang 4 auto no signal. e7h vstol[3:0] 3:0 vsync tolerance. 1: default value. isovrd 7:0 default : 0x00 access : r/w sl 7 shift line. 0: shift line method 0. 1: shift line method 1 for interlace mode. cshs 6 hsync in coast. 0: hsout (recommended). 1: re-shaped hsync. uvsp 5 user defined input vsync polarity, active when ivsj =1. 0: active low. 1: active high. ivsj 4 input vsync polarity judgment. 0: use result of internal circuit detection. 1: defined by user (uvsp). e8h uhsp 3 user defined input hsync polarity, active when ivsj =1. 0: active low. 1: active high. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 56 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) ihsj 2 input hsync polarity judgment. 0: use result of internal circuit detection. 1: defined by user (uhsp). uint 1 user defined non-interlace/interlace, active when intj = 1. 0: non-interlace. 1: interlace. intj 0 interlace judgment. 0: use result of internal circuit detection. 1: defined by user (uint). mdctrl 7:0 default : 0x00 access : r/w rcfcpb 7 resolution conversion filter compatible select. 0: compatible with old filter. 1: use new filter. verr 6 video ccir656 error correct. 0: disable. 1: enable. scsel[1:0] 5:4 software compatibility select. vfiv 3 video field inversion. 0: normal. 1: invert. vexf 2 video external field. 0: use result of internal circuit detection. 1: use external field. intf 1 interlace field detect method select. 0: use the hsync numbers of a field to judge. 1: use the relationship of vsync and hsync to judge. e9h ifi 0 interlace field invert. 0: normal. 1: invert. dvickd 7:0 default : - access : ro note: when bank 0 reg 02h[1:0] = 2 b10 (dvi feature only) of 7 dvi clock detection overflow (dvi feature only). 0: not overflow. 1: overflow. eah dvickd[6:0] 6:0 dvi clock detection report, based on oscillator clock (dvi feature only). freq(dvi) = freq(xtal) * dvickd[6:0] * 2/128, if of = 0. freq(dvi) > freq(xtal) * 2, if of = 1. ebh dvickth 7:0 default : 0x1e access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 57 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) note: when bank 0 reg 02h[1:0] = 2 b10 (dvi feature only) dvickth[7:0] 7:0 dvi clock detection threshold, see cah for usage (default 0x1e). cah[6] = 0: dvi clock is ok, freq(dvi) > freq(xtal) * ebh/128. cah[6] = 1: dvi clock is missing, freq(dvi) < freq(xtal) * ebh/128. where ebh default to 0x1e(30). minvtt 7:0 default : 0x00 access : r/w vfrm 7 video in free run mode (read only) ech minvtt[6:0] 6:0 define min vtt * 16 for progressive vtt. coctrl1 7:0 default : 0x00 access : r/w - 7:6 reserved. avis 5 analog video input select. 0: pc. 1: component analog video. dlyv 4 analog delay line for component analog video input. 0: delay 1 line. 1: do not delay. cscm 3 composite sync cut mode. 0: disable. 1: enable. exvs 2 external vsync polarity (only used when covs is 1). 0: normal. 1: invert. covs 1 coast vsync select. 0: internal vsep. 1: external vsync. edh cta 0 coast to adc. 0: disable. 1: enable. coctrl2 7:0 default : 0x00 access : r/w eeh cost[7:0] 7:0 front tuning. 00: coast start from 1 hsync leading edge. 01: coast start from 2 hsync leading edge, default value. 254: coast start from 255 hsync leading edge. 255: coast start from 256 hsync leading edge. coctrl3 7:0 default : 0x00 access : r/w efh coend[7:0] 7:0 end tuning. 00: coast end at 1 hsync leading edge. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 58 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 01: coast end at 2 hsync leading edge, default value. 254: coast end at 255 hsync leading edge. 255: coast end at 256 hsync leading edge. pdmd 7:0 default : 0x13 access : r/w apdld 7 automatically power down when low power using digital pin. 0: disable. 1: enable. apdla 6 automatically power down when low power using analog pin. 0: disable. 1: enable. phsrm 5 pd hdcp sram. pdds 4 power down ddc sram. 0: normal. 1: power down while not used. gclk[1:0] 3:2 gated clock for sram (excluding ddc sram). 00: normal. 01: v blank. 10: h blank and v blank. 11: reserved. f0h pdmd 0 power down mode. 00: normal. 01: output (osd) only (used when no input signal). 10: biu, mode detection, gout are functional. 11: all chip power down. swrst 7:0 default : 0x80 access : r/w dpdmd 7 deep power down mode. 0: disable. 1: enable. - 6 reserved. adcr 5 adc reset. 0: normal operation. 1: reset adc. gpr 4 graphic port reset. 0: normal operation. 1: reset. dpr 3 display port reset. 0: normal operation. 1: reset. f1h biur 2 biu reset. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 59 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 0: normal operation. 1: reset biu. osdr 1 internal osd reset. 0: normal operation. 1: reset internal osd. swr 0 software reset (reset gp, dp, biu, osd and adc). 0: normal operation. 1: reset. osctrl 7:0 default : 0x00 access : r/w oclkdly[3:0] / 7:4 ockdly[3:0]: oclk delay adjustment (tcon feature only). 0: 16 step to adjust. 1: typical 0.8ns delay/step. rsck_ske[3] rsck_ske[2:0] 7 6:4 rsds clock inverted. 0: normal clock out. 1: rsds clock output inverted. rsds clock skew adjust. 000: max setup time / min hold time to rsds data output. 001: 011: 111: min setup time / max hold time to rsds data output. oclk 3 output clk control. 0: normal. 1: invert. ode 2 output de control. 0: active high. 1: active low. ovs 1 output vsync control. 0: active high. 1: active low. f2h ohs 0 output hsync control. 0: active high. 1: active low. isctrl 7:0 default : 0x10 access : r/w dege 7 de or hsync post glitch removal function enable. 0: disable. 1: enable. degr[2:0] 6:4 de or hsync post glitch removal range. f3h hsfl 3 input hsync filter. when input source is analog: 0: filter off. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 60 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 1: filter on. when input source is dvi: 0: normal. 1: more tolerance for unstable de. issm 2 input sync sample mode. 0: normal. 1: glitch-removal. - 1 reserved. scki 0 input sample clk invert. 0: normal. 1: invert. tristate 7:0 default : 0x7f access : r/w - 7 reserved. tcs 6 hsync/vsync control signal pin tri-state control (tcon feature only). 0: normal. 1: tri-state. oedb 5 output even data bus pin control. 0: normal. 1: tri-state. oodb 4 output odd data bus pin control. 0: normal. 1: tri-state. ovs 3 ovsync pin control. 0: normal. 1: tri-state. ohs 2 ohsync pin control. 0: normal. 1: tri-state. ode 1 ode pin control. 0: normal. 1: tri-state. f4h oclk 0 oclk pin control. 0: normal. 1: tri-state. odrv 7:0 default : 0x55 access : r/w f5h dedrv[1:0] 7:6 output de driving current select. 00: 4ma; 01: 6ma; 10: 8ma; free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 61 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) 11: 12ma. clkdrv[1:0] 5:4 output clock driving current select. 00: 4ma; 01: 6ma; 10: 8ma; 11: 12ma. odddrv[1:0] 3:2 output data odd channel driving current select. 00: 4ma; 01: 6ma; 10: 8ma; 11: 12ma. evendrv[1:0] 1:0 output data even channel driving current select. 00: 4ma; 01: 6ma; 10: 8ma; 11: 12ma. eclkdly 7:0 default : 0x00 access : r/w - 7:6 reserved. skew[1:0] 5:4 output data skew. eclkdly[3:0] / 3:0 eclk delay adjustment (tcon feature only). 0: 16 steps to adjust. 1: typical 0.8ns delay/step. f6h testmod[15:14] testmod[13] testmod[12] 3:2 1 0 reserved. rsds differential output clock test mode. 0: normal operation. 1: set rsds differential output clock low. rsds differential output clock test mode. 0: normal operation. 1: set rsds differential output clock high. rsdstest 7:0 default : - access : ro - 7:4 reserved. hsrmp 3 hdcp sram pass. hsrmf 2 hdcp sram finish. rsrp 1 rsds sram test result. 0: not pass. 1: pass. f7h rsrf 0 rsds sram test finish. 0: not finish. 1: finish. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 62 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) test 7:0 default : 0x05 access : r/w - 7 reserved. - 6 reserved. - 5:4 reserved. f8h testmd[3:0] 3:0 test mode. 0110: vs/hs/de output while lvds output other: reserved. sramtest 7:0 default : - access : ro dsrp 7 ddc sram test result. 0: not pass. 1: pass. dsrf 6 ddc sram test finish. 0: not finish. 1: finish. gsrp 5 gamma sram test result. 0: not pass. 1: pass. gsrf 4 gamma sram test finish. 0: not finish. 1: finish. osrp 3 internal osd sram test result. 0: not pass. 1: pass. osrf 2 internal osd sram test finish. 0: not finish. 1: finish. lsrp 1 line buffer sram test result. 0: not pass. 1: pass. f9h lsrf 0 line buffer sram test finish. 0: not finish. 1: finish. dimd 7:0 default : 0x00 access : r/w - 7:5 reserved. vdoe 4 video reference edge.(for non-standard signal) ipavg 3 interlace period average. fah aclksw 2 auto clock switch 0: auto clock switch when detected clock great than expect value 1: disable auto clock switch free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 63 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. digital image processor register (bank=00) - 1:0 reserved. - 7:0 default : - access : - fbh ~ ffh - 7:0 reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) osd register (indirect mapping, using bank 0 register a1h/a2h) index mnemonic bits description osddbc 7:0 default : 0x00 access : r/w - 7:3 reserved. dbl[1:0] 2:1 double buffer load. 00: keep old register value. 01: load new data (auto reset to 00 when load finish). 10: automatically load data at vsync blanking. 11: reserved. 01h dbe 0 double buffer enable. 0: disable. 1: enable. ohsta-l 7:0 default : 0x00 access : r/w db 02h ohsta[7:0] 7:0 osd window horizontal start position. ohsta-h 7:0 default : 0x00 access : r/w db - 7:1 reserved. 03h ohsta[8] 0 see description for ohsta[7:0]. ovsta-l 7:0 default : 0x00 access : r/w db 04h ovsta[7:0] 7:0 osd window vertical start position. ovsta-h 7:0 default : 0x00 access : r/w db - 7:1 reserved. 05h ovsta[8] 0 see description for ovsta[7:0]. osdw 7:0 default : 0x00 access : r/w db - 7:6 reserved. 06h osdw[5:0] 5:0 osd window width = osdw + 1 (column), maximum 64 columns. osdh 7:0 default : 0x00 access : r/w db - 7:5 reserved. 07h osdh[4:0] 4:0 osd window vertical height = osdh + 1 (row), maximum 32 rows. 08h ohspa 7:0 default : 0x00 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 64 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) - 7:6 reserved. ohspa[5:0] 5:0 osd window horizontal space start position = ohspa + 1 (row). ovspa 7:0 default : 0x00 access : r/w - 7:5 reserved. 09h ovspa[4:0] 4:0 osd window vertical space start position = ovspa + 1 (column). ospw 7:0 default : 0x00 access : r/w 0ah ospw[7:0] 7:0 osd space width = 8 * ospw (pixel). osph 7:0 default : 0x00 access : r/w 0bh osph[7:0] 7:0 osd space height = 8 * osph (pixel). iosdc1 7:0 default : 0x00 access : r/w, db ovs[1:0] 7:6 osd vertical scaling. 00: vertical normal size. 01: vertical enlarged x2 by repeated pixels. 10: vertical enlarged x3 by repeated pixels. 11: vertical enlarged by x4 by repeated pixels. ohs[1:0] 5:4 osd horizontal scaling. 00: horizontal normal size. 01: horizontal enlarged x2 by repeated pixels. 10: horizontal enlarged x3 by repeated pixels. 11: horizontal enlarged by x4 by repeated pixels. c1c 3 character 1 line color. 0: disable. 1: enable. rot[1:0] 2:1 rotate. 00: not rotate. 01: rotate 90 . 10: rotate 270 . 11: reserved. 0ch mwin 0 osd main window display. 0: main window off. 1: main window on. iosdc2 7:0 default : 0x00 access : r/w cf8e 7 8 color font enable. 0: disable. 1: enable. 0dh bclr[2:0] 6:4 osd border color index; bclr[3] is located at reg 0e[5]. 0000: color index 0. 0001: color index 1. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 65 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) 1111: color index 15. bdc 3 osd character border type select. 0: all direction font boundary (border). 1: bottom-right direction font boundary (shadow). bdw 2 osd character border width control. 0: one pixel width for all scale. 1: scale with ovs[1:0] and ohs[1:0]. c16_pal 1 color palette select. 0: 8 color palette. 1: 16 color palette. cf4e 0 4 color font enable. 0: disable. 1: enable. iosdc3 7:0 default : 0x00 access : r/w, db c4te 7 osd 4-color transparency enable. 0: disable. 1: enable. color index bit 3 of color key. note: when osd register 0x10[7]=0, osd is backward compatible. ckind[3] 6 reserved. note: when osd register 0x10[7]=1, osd is not backward compatible. bclr[3] 5 border color bit 3. this bit should work with osd 0dh[6:4]. sdc 4 osd window shadow control. 0: off. 1: on. 0eh sclr[3:0] 3:0 osd window shadow color index. 0000: color index 0. 0001: color index 1. 1111: color index 15. oshc 7:0 default : 0x00 access : r/w osdsh[3:0] 7:4 osd shadow height. 0fh osdsw[3:0] 3:0 osd shadow width. ocff 7:0 default : 0x00 access : r/w ocff 7 osd backward compatibility. 0: backward compatible. 1: not backward compatible. 10h mfcs 6 osd 256 color palette mono font color select. 0: use 256 color palette select method. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 66 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) 1: use 16 color palette select method. - 5 reserved. - 4 reserved. cfctosd 3 color font code address type. 0: ram base. 1: code base. c256p_sel 2 osd 256 palette select. 0: select 8 or 16 color palette. 1: select 256 color palette. pal_ext 1 osd 16/256 palette extended method. 0: extended lsb. 1: extended 0. - 4 reserved. osdcfa 7:0 default : 0x00 access : r/w 11h osdcfa[7:0] 7:0 osd 4 color ram font starting address. ocbufo 7:0 default : 0x00 access : r/w cos 7 osd code buffer offset select. 0: use osdw[5:0] as offset. 1: use ooffset[5:0] as offset. - 6 reserved. 12h ooffset 5:0 osd code buffer offset value. osdba-l 7:0 default : 0x00 access : r/w, db 13h osdba[7:0] 7:0 osd code base address. osdba-h 7:0 default : 0x00 access : r/w, db - 7:2 reserved. 14h osdba[9:8] 1:0 see description for osdba[7:0]. gcctrl 7:0 default : 0x00 access : r/w gvs[1:0] 7:6 gradually color vertical scaling. 00: vertical normal size. 01: vertical enlarged x2 by repeated pixels. 10: vertical enlarged x3 by repeated pixels. 11: vertical enlarged x4 by repeated pixels. ghs[1:0] 5:4 gradually color horizontal scaling. 00: horizontal normal size. 01: horizontal enlarged x2 by repeated pixels. 10: horizontal enlarged x3 by repeated pixels. 11: horizontal enlarged x4 by repeated pixels. 15h - 6 reserved. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 67 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) ooffset 5:0 osd code buffer offset value. gradclr 7:0 default : 0x00 access : r/w nclren 7 new ini color enable. 0: original function. 1: frame color at bank 0 reg 0x33, 0x34 and 0x35. f/b 6 gradually applied color. 0: background color. 1: foreground color. rclr[1:0] 5:4 red starting gradually color. 00: red color is 00h. 01: red color is 55h. 10: red color is aah. 11: red color is ffh. gclr[1:0] 5:4 green starting gradually color. 00: green color is 00h. 01: green color is 55h. 10: green color is aah. 11: green color is ffh. 16h bclr[1:0] 5:4 blue starting gradually color. 00: blue color is 00h. 01: blue color is 55h. 10: blue color is aah. 11: blue color is ffh. hgradcr 7:0 default : 0x00 access : r/w sr 7 sign bit of red color. 0: increase. 1: decrease. irh 6 inverse bit of red color. 0: normal. 1: invert. 17h r_gradh[5:0] 5:0 increase/decrease value of red color. hgradcg 7:0 default : 0x00 access : r/w sg 7 sign bit of green color. 0: increase. 1: decrease. igh 6 inverse bit of green color. 0: normal. 1: invert. 18h g_gradh[5:0] 5:0 increase/decrease value of green color. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 68 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) hgradcb 7:0 default : 0x00 access : r/w sb 7 sign bit of blue color. 0: increase. 1: decrease. ibh 6 inverse bit of blue color. 0: normal. 1: invert. 19h b_gradh[5:0] 5:0 increase/decrease value of blue color. hgradsr 7:0 default : 0x00 access : r/w 1ah hgradsr[7:0] 7:0 horizontal gradually step of red color. hgradsg 7:0 default : 0x00 access : r/w 1bh hgradsg[7:0] 7:0 horizontal gradually step of green color. hgradsb 7:0 default : 0x00 access : r/w hgradsb[7:0] 7:0 horizontal gradually step of blue color. 1ch for example, of rclr=0, r_gradh=16h, and hgradsr=20h, then pixel 0 ~ 19 = 0; pixel 20 ~ 39 = 16; pixel 40 ~ 59 = 32; etc. vgradcr 7:0 default : 0x00 access : r/w sr 7 sign bit of red color. 0: increase. 1: decrease. irv 6 inverse bit of red color. 0: normal. 1: invert. 1dh r_gradv[5:0] 5:0 increase/decrease value of red color. vgradcg 7:0 default : 0x00 access : r/w sg 7 sign bit of green color. 0: increase. 1: decrease. igv 6 inverse bit of green color. 0: normal. 1: invert. 1eh g_gradv[5:0] 5:0 increase/decrease value of green color. vgradcb 7:0 default : 0x00 access : r/w 1fh sb 7 sign bit of blue color. 0: increase. 1: decrease. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 69 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) ibv 6 inverse bit of blue color. 0: normal. 1: invert. b_gradv[5:0] 5:0 increase/decrease value of blue color. vgradsr 7:0 default : 0x00 access : r/w 20h vgradsr[7:0] 7:0 vertical gradually step of red color. vgradsg 7:0 default : 0x00 access : r/w 21h vgradsg[7:0] 7:0 vertical gradually step of green color. vgradsb 7:0 default : 0x00 access : r/w 22h vgradsb[7:0] 7:0 vertical gradually step of blue color. subw0c 7:0 default : 0x00 access : r/w, db - 7:4 reserved. btn0 3 enable button function for sub window 0. 0: off. 1: on. bd0 2 enable osd sub window 0 border. 0: disable. 1: enable. s0c 1 sub window 0 color select. if button function is disabled: 0: from sub window 0 attribute. 1: from attribute ram. if button function is enable: 0: set this bit with 0. use sub window 0 attribute to select fg/bg color and use attribute ram to select button type. 23h s0e 0 enable osd sub window 0. 0: disable. 1: enable. sw0hst 7:0 default : 0x00 access : r/w, db - 7:6 reserved. 24h sw0hst[5:0] 5:0 sub window 0 horizontal start position. sw0hend 7:0 default : 0x00 access : r/w, db - 7:6 reserved. 25h sw0hend[5:0] 5:0 sub window 0 horizontal end position. sw0vst 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 26h sw0vst[4:0] 4:0 sub window 0 vertical start position. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 70 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) sw0vend 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 27h sw0vend[4:0] 4:0 sub window 0 vertical end position. subw0a2 7:0 default : 0x00 access : r/w note: when button function is enabled, the fg/bg color is defined by window attribute, character attribute is used to define button function border type and s0c (sub window color select) is disabled. blnk 7 osd sub window 0 blink control. 0: disable. 1: enable. when 16 color palette is selected, blnk will be fgclr[3]. fgclr[2:0] 6:4 osd sub window 0 foreground color select. 000: color index 0. 001: color index 1. 111: color index 7. tran 5 osd sub window 0 transparency control. 0: disable. 1: enable. when 16 color palette is selected, tran will be bgclr[3]. 28h bgclr[2:0] 2:0 osd sub window 0 background color select. 000: color index 0. 001: color index 1. 111: color index 7. subw0a2 7:0 default : 0x00 access : r/w, db btncsel[2:0] 7:5 when osd register 0x10[7]=0, osd is backward compatible. reserved. btncsel[2] btncsel[1] btncsel[0] 7 6 5 when osd register 0x10[7]=1, osd is not backward compatible. button red color is selected. button green color is selected. button blue color is selected. btnu 4 button up control. 0: button up. 1: button down. 28h btntype[3:0] 3:0 button border type. 0: no button. 1: free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 71 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) 1 2 3 4 5 6 7 8 9 a b c d e f | | - - | | - - note: the register of sub window 1, 2, and 3 are very similar with sub window 0 subw1c 7:0 default : 0x00 access : r/w, db - 7:4 reserved. btn1 3 enable button function for sub window 1. bd1 2 enable osd sub window 1 border. s1c 1 sub window 1 color select. 29h s1e 0 enable osd sub window 1. sw1hst 7:0 default : 0x00 access : r/w, db - 7:6 reserved. 2ah sw1hst[5:0] 5:0 sub window 1 horizontal start position. sw1hend 7:0 default : 0x00 access : r/w, db - 7:6 reserved. 2bh sw1hend[5:0] 5:0 sub window 1 horizontal end position. sw1vst 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 2ch sw1vst[4:0] 4:0 sub window 1 vertical start position. sw1vend 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 2dh sw1vend[4:0] 4:0 sub window 1 vertical end position. subw1a 7:0 default : 0x00 access : r/w blnk 7 osd sub window 1 blink control. fgclr[2:0] 6:4 osd sub window 1 foreground color select. tran 5 osd sub window 1 transparency control. 2eh bgclr[2:0] 2:0 osd sub window 1 background color select. subw2c 7:0 default : 0x00 access : r/w, db - 7:4 reserved. btn2 3 enable button function for sub window 2. bd2 2 enable osd sub window 2 border. s2c 1 sub window 2 color select. 2fh s2e 0 enable osd sub window 2. 30h sw2hst 7:0 default : 0x00 access : r/w, db free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 72 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) - 7:6 reserved. sw2hst[5:0] 5:0 sub window 2 horizontal start position. sw2hend 7:0 default : 0x00 access : r/w, db - 7:6 reserved. 31h sw2hend[5:0] 5:0 sub window 2 horizontal end position. sw2vst 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 32h sw2vst[4:0] 4:0 sub window 2 vertical start position. sw2vend 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 33h sw2vend[4:0] 4:0 sub window 2 vertical end position. subw2a 7:0 default : 0x00 access : r/w blnk 7 osd sub window 2 blink control. fgclr[2:0] 6:4 osd sub window 2 foreground color select. tran 5 osd sub window 2 transparency control. 34h bgclr[2:0] 2:0 osd sub window 2 background color select. subw3c 7:0 default : 0x00 access : r/w, db - 7:4 reserved. btn3 3 enable button function for sub window 3. bd3 2 enable osd sub window 3 border. s3c 1 sub window 3 color select. 35h s3e 0 enable osd sub window 3. sw3hst 7:0 default : 0x00 access : r/w, db - 7:6 reserved. 36h sw3hst[5:0] 5:0 sub window 3 horizontal start position. sw3hend 7:0 default : 0x00 access : r/w, db - 7:6 reserved. 37h sw3hend[5:0] 5:0 sub window 3 horizontal end position. sw2vst 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 38h sw3vst[4:0] 4:0 sub window 3 vertical start position. sw2vend 7:0 default : 0x00 access : r/w, db - 7:5 reserved. 39h sw3vend[4:0] 4:0 sub window 3 vertical end position. 3ah subw3a 7:0 default : 0x00 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 73 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) blnk 7 osd sub window 3 blink control. fgclr[2:0] 6:4 osd sub window 3 foreground color select. tran 5 osd sub window 3 transparency control. bgclr[2:0] 2:0 osd sub window 3 background color select. osd8cffa 7:0 default : 0x00 access : r/w 3bh osd8cffa[7:0] 7:0 osd 8 color font ram start address. osd8cfca 7:0 default : 0x00 access : r/w 3ch osd8cfca[7:0] 7:0 osd 8 color font code start address. 256cpkey0 7:0 default : 0x00 access : r/w 3dh 256cpkey0[7:0] 7:0 256 color palette key 0. 256cpkey1 7:0 default : 0x00 access : r/w 3eh 256cpkey1[7:0] 7:0 256 color palette key 1. 256cpkey2 7:0 default : 0x00 access : r/w 3fh 256cpkey2[7:0] 7:0 256 color palette key 2. 256cpclci 7:0 default : 0x00 access : r/w 40h 256cpclci[7:0] 7:0 256 color palette character 1 line color index. osdcfha 7:0 default : 0x00 access : r/w osd8cffa[8] 7 see description for osd8cffa[7:0]. osd8cfca[8] see description for osd8cfca[7:0]. - 5:4 reserved. osd4cfa[8] 3 see description for osd4cfa[7:0]. 41h - 2:0 reserved. - 7:0 default : - access : - 42h ~ 57h - 7:0 reserved. osd 8-color palette (when c16_pal=0), 8-bit resolution clr0r 7:0 default : 0x00 access : r/w 58h clr0r[7:0] 7:0 r component of index 0. clr0g 7:0 default : 0x00 access : r/w 59h clr0g[7:0] 7:0 g component of index 0. clr0b 7:0 default : 0x00 access : r/w 5ah clr0b[7:0] 7:0 b component of index 0. clr1r 7:0 default : 0x00 access : r/w 5bh clr1r[7:0] 7:0 r component of index 1. clr1g 7:0 default : 0x00 access : r/w 5ch clr1g[7:0] 7:0 g component of index 1. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 74 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) clr1b 7:0 default : 0x00 access : r/w 5dh clr1b[7:0] 7:0 b component of index 1. clr2r 7:0 default : 0x00 access : r/w 5eh clr2r[7:0] 7:0 r component of index 2. clr2g 7:0 default : 0x00 access : r/w 5fh clr2g[7:0] 7:0 g component of index 2. clr2b 7:0 default : 0x00 access : r/w 60h clr2b[7:0] 7:0 b component of index 2. clr3r 7:0 default : 0x00 access : r/w 61h clr3r[7:0] 7:0 r component of index 3. clr3g 7:0 default : 0x00 access : r/w 62h clr3g[7:0] 7:0 g component of index 3. clr3b 7:0 default : 0x00 access : r/w 63h clr3b[7:0] 7:0 b component of index 3. clr4r 7:0 default : 0x00 access : r/w 64h clr4r[7:0] 7:0 r component of index 4. clr4g 7:0 default : 0x00 access : r/w 65h clr4g[7:0] 7:0 g component of index 4. clr4b 7:0 default : 0x00 access : r/w 66h clr4b[7:0] 7:0 b component of index 4. clr5r 7:0 default : 0x00 access : r/w 67h clr5r[7:0] 7:0 r component of index 5. clr5g 7:0 default : 0x00 access : r/w 68h clr5g[7:0] 7:0 g component of index 5. clr5b 7:0 default : 0x00 access : r/w 69h clr5b[7:0] 7:0 b component of index 5. clr6r 7:0 default : 0x00 access : r/w 6ah clr6r[7:0] 7:0 r component of index 6. clr6g 7:0 default : 0x00 access : r/w 6bh clr6g[7:0] 7:0 g component of index 6. clr6b 7:0 default : 0x00 access : r/w 6ch clr6b[7:0] 7:0 b component of index 6. clr7r 7:0 default : 0x00 access : r/w 6dh clr7r[7:0] 7:0 r component of index 7. 6eh clr7g 7:0 default : 0x00 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 75 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) clr7g[7:0] 7:0 g component of index 7. clr7b 7:0 default : 0x00 access : r/w 6fh clr7b[7:0] 7:0 b component of index 7. osd 16-color palette (when c16_pal=1), 4-bit resolution 16 color format: col[7:4], 4 h0 clr0r 7:0 default : 0x00 access : r/w clr0r[7:4] 7:4 r component of index 0. 58h clr8r[7:4] 3:0 r component of index 8. clr0g 7:0 default : 0x00 access : r/w clr0g[7:4] 7:4 g component of index 0. 59h clr8g[7:4] 3:0 g component of index 8. clr0b 7:0 default : 0x00 access : r/w clr0b[7:4] 7:4 b component of index 0. 5ah clr8b[7:4] 3:0 b component of index 8. clr1r 7:0 default : 0x00 access : r/w clr1r[7:4] 7:4 r component of index 1. 5bh clr9r[7:4] 3:0 r component of index 9. clr1g 7:0 default : 0x00 access : r/w clr1g[7:4] 7:4 g component of index 1. 5ch clr9g[7:4] 3:0 g component of index 9. clr1b 7:0 default : 0x00 access : r/w clr1b[7:4] 7:4 b component of index 1. 5dh clr9b[7:4] 3:0 b component of index 9. clr2r 7:0 default : 0x00 access : r/w clr2r[7:4] 7:4 r component of index 2. 5eh clr10r[7:4] 3:0 r component of index 10. clr2g 7:0 default : 0x00 access : r/w clr2g[7:4] 7:4 g component of index 2. 5fh clr10g[7:4] 3:0 g component of index 10. clr2b 7:0 default : 0x00 access : r/w clr2b[7:4] 7:4 b component of index 2. 60h clr10b[7:4] 3:0 b component of index 10. clr3r 7:0 default : 0x00 access : r/w clr3r[7:4] 7:4 r component of index 3. 61h clr11r[7:4] 3:0 r component of index 11. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 76 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) clr3g 7:0 default : 0x00 access : r/w clr3g[7:4] 7:4 g component of index 3. 62h clr11g[7:4] 3:0 g component of index 11. clr4b 7:0 default : 0x00 access : r/w clr4b[7:4] 7:4 b component of index 3. 63h clr11b[7:4] 3:0 b component of index 11. clr4r 7:0 default : 0x00 access : r/w clr4r[7:4] 7:4 r component of index 4. 64h clr12r[7:4] 3:0 r component of index 12. clr4g 7:0 default : 0x00 access : r/w clr4g[7:4] 7:4 g component of index 4. 65h clr12g[7:4] 3:0 g component of index 12. clr4b 7:0 default : 0x00 access : r/w clr4b[7:4] 7:4 b component of index 4. 66h clr12b[7:4] 3:0 b component of index 12. clr5r 7:0 default : 0x00 access : r/w clr5r[7:4] 7:4 r component of index 5. 67h clr13r[7:4] 3:0 r component of index 13. clr5g 7:0 default : 0x00 access : r/w clr5g[7:4] 7:4 g component of index 5. 68h clr13g[7:4] 3:0 g component of index 13. clr5b 7:0 default : 0x00 access : r/w clr5b[7:4] 7:4 b component of index 5. 69h clr13b[7:4] 3:0 b component of index 13. clr6r 7:0 default : 0x00 access : r/w clr6r[7:4] 7:4 r component of index 6. 6ah clr14r[7:4] 3:0 r component of index 14. clr6g 7:0 default : 0x00 access : r/w clr6g[7:4] 7:4 g component of index 6. 6bh clr14g[7:4] 3:0 g component of index 14. clr6b 7:0 default : 0x00 access : r/w clr6b[7:4] 7:4 b component of index 6. 6ch clr14b[7:4] 3:0 b component of index 14. clr7r 7:0 default : 0x00 access : r/w 6dh clr7r[7:4] 7:4 r component of index 7. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 77 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping, using bank 0 register a1h/a2h) clr15r[7:4] 3:0 r component of index 15. clr7g 7:0 default : 0x00 access : r/w clr7g[7:4] 7:4 g component of index 7. 6eh clr15g[7:4] 3:0 g component of index 15. clr7b 7:0 default : 0x00 access : r/w clr7b[7:4] 7:4 b component of index 7. 6fh clr15b[7:4] 3:0 b component of index 15. - 7:0 default : 0x00 access : - 70h - 7:0 reserved. osdrtp 7:0 default : 0x00 access : r/w - 7:3 reserved. rtpt 2 osd random test pattern type. 0: rgb is same. 1: rgb is different. 71h osdrtp 1:0 osd random test pattern. 00: disable. 01: 1 random bit. 10: 2 random bit. 11: reserved. atr0data 7:0 default : 0x00 access : r/w 72h atr0kdata[7:0] 7:0 atr sram address0 data read back. tcon register (bank = 02, registers 0000h ~ 00ffh) tcon register (bank = 02) index mnemonic bits description - 7:0 default : - access : - 01h - 7:0 reserved. ofc1 7:0 default : 0x02 access : r/w ifc 7 inversion function combined. 0: odd data inversion determined by oinv, even data inversion determined by einv. 1: odd/even data inversion both determined by oinv. ifs 6 inversion function swap. 0: oinv/einv = 0 when data is inverted. 1: oinv/einv = 1 when data is inverted. 02h ife 5 inversion function enable. 0: disable. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 78 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) 1: enable. when enabled, an ind ication is output for each data bus. if the number of transitions from pixel to pixel exceed 24 bits from 48 bits (or 18 bits from 36 bits for 6-bit panels), the data is inverted and an indication corresponding to that bus is set active. dpfs 4 data polarity function swap (useful when dpfe = 1). 0: odd data inversion determined by opol, even data inversion determined by epol. 1: odd data inversion determined by opol, even data opposite of odd data. dpfc 3 data polarity function control. 0: data inversion when opol/epol is 0. 1: data inversion when opol/epol is 1. dpfe 2 data polarity function enable. 0: disable. 1: enable (line inversion, use opol/epol to determine that polarity of the output data). eef 1 early end function. 0: disable. 1: enable. tcen 0 timing controller enable. 0: disable. 1: enable. ofc2 7:0 default : 0x00 access : r/w espp 7 even start pulse position. 0: start pulse before data. 1: start pulse after data. espo[2:0] 6:4 even start pulse offset. 000: start pulse 0 clocks before/after data. 001: start pulse 1 clocks before/after data. 010: start pulse 2 clocks before/after data. 111: start pulse 7 clocks before/after data. 03h ospp 3 odd start pulse position. 0: start pulse before data. 1: start pulse after data. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 79 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) ospo[2:0] 2:0 odd start pulse offset. 000: start pulse 0 clocks before/after data. 001: start pulse 1 clocks before/after data. 010: start pulse 2 clocks before/after data. 111: start pulse 7 clocks before/after data. odpc 7:0 default : 0x00 access : r/w oespdc[1:0] 7:6 osp/esp drive control. 00: 4ma. 01: 6ma. 10: 8ma. 11: 12ma. godc[1:0] 5:4 opol/epol/gpo drive control. 00: 4ma. 01: 6ma. 10: 8ma. 11: 12ma. ecp 3 eclk polarity. 0: normal. 1: inverted. - 2 reserved. ocp 1 oclk polarity. 0: normal. 1: inverted. 04h - 0 reserved. odc 7:0 default : 0x00 access : r/w eddc[1:0] 7:6 einv driver control. 00: 4ma. 01: 6ma. 10: 8ma. 11: 12ma. oidc 5:4 oinv drive control. - 3 reserved. oftg 2 one frame toggle mode. 05h rsbmlsw 1 rsds b-port msb/lsb swap. bank 0 reg 0x42[5] = 0 and 0x42[2] = 1: 0: default. 1: b-port msb/lsb swap for 8-bit rsds output. bank 0 reg 0x42[5] = 0 and 0x42[2] = 1: free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 80 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) 0: default. 1: b-port msb/lsb swap for 6-bit rsds output. rsamlsw 0 rsds a-port msb/lsb swap. bank 0 reg 0x42[5] = 0 and 0x42[3] = 1: 0: default. 1: a-port msb/lsb swap for 8-bit rsds output. bank 0 reg 0x42[5] = 0 and 0x42[3] = 1: 0: default. 1: a-port msb/lsb swap for 6-bit rsds output. gpo4adf 7:0 default : 0x00 access : r/w - 7:3 reserved. 06h gpo4adf[2:0] 2:0 gpo4 (oe) active delay time. 000: no delay. 001: delay 1 frame. 111: delay 7 frames. ifctrl 7:0 default : 0x00 access : r/w wdg 7 white data generation (tcon feature only). 0: black data generation during vertical blanking (gpoa). 1: enable white data generation during vertical blanking (gpoa). pua 6 power-up active (tcon feature only). 0: outputs inactive. 1: outputs active. g0at 5 gpo0 auto toggle (tcon feature only). 0: disable. 1: enable. gdeen 4 gate de enable. dati 3 data invert (tcon feature only). 0: off. 1: on. polb 2 polarity blanked enable (tcon feature only). 0: disable. 1: enable (epol/opol will be forced to blanked when gpoa is low). spb 1 start pulse blanked enable (tcon feature only). 0: disable. 1: enable (epol/opol will be forced to blanked when gpoa is low). 07h clkb 0 clock blanked enable. 0: disable. 1: enable (eclk/oclk will be forced to blanked when gpoa is low). 08h g0vst-l 7:0 default : 0x00 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 81 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) g0vst[7:0] 7:0 line number that gpo0 start. g0vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 09h g0vst[10:8] 2:0 see description for g0vst[7:0]. g0vend-l 7:0 default : 0x00 access : r/w 0ah g0vend[7:0] 7:0 line number that gpo0 ends. g0vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 0bh g0vend[10:8] 2:0 see description for g0vend[7:0]. g0hst-l 7:0 default : 0x00 access : r/w 0ch g0hst[7:0] 7:0 pixel number that gpo0 start. g0hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 0dh g0vht[10:8] 2:0 pixel description for g0hst[7:0]. g0hend-l 7:0 default : 0x00 access : r/w 0eh g0hend[7:0] 7:0 pixel number that gpo0 ends. g0hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 0fh g0hend[10:8] 2:0 see description for g0hend[7:0]. c0ctrl 7:0 default : 0x00 access : r/w c0cs[2:0] 7:5 gpo0 combination select. 000: no combination. 001: and. 010: or. 011: select gpo# and gpo#-1 on alternating frames. 1xx: auto select 1 or 2 line toggle according to atp value. g0ts[1:0] 4:3 gpo0 type select. when toggle mode=0: 00: normal. 01: duration is greater than a line time. 10: every two lines have one gpo0 pulse. 11: every three lines have one gpo0 pulse. when toggle mode=1: 00: one line toggle. 01: reserved. 10: two lines toggle. 11: three lines toggle. 10h g0es 2 gpo0 early start function. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 82 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) 0: normal. 1: early start capability. the value in the vertical start register (g0vst) is subtracted from the total number of lines/frames to determine the vertical start position. g0tc 1 gpo0 toggle circuit enable. 0: normal. 1: toggle. toggle mode is useful in pol generation when alternating polarity is required from line to line. frame to frame polarity changes are made by programming an odd # in the vertical duration when in toggle mode. g0op 0 gpo0 output polarity. 0: active high. 1: active low. g1vst-l 7:0 default : 0x00 access : r/w 11h g1vst[7:0] 7:0 line number that gpo1 start. g1vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 12h g1vst[10:8] 2:0 see description for g1vst[7:0]. g1vend-l 7:0 default : 0x00 access : r/w 13h g1vend[7:0] 7:0 line number that gpo1 ends. g1vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 14h g1vend[10:8] 2:0 see description for g1vend[7:0]. g1hst-l 7:0 default : 0x00 access : r/w 15h g1hst[7:0] 7:0 pixel number that gpo1 start. g1hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 16h g1vht[10:8] 2:0 pixel description for g1hst[7:0]. g1hend-l 7:0 default : 0x00 access : r/w 17h g1hend[7:0] 7:0 pixel number that gpo1 ends. g1hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 18h g1hend[10:8] 2:0 see description for g1hend[7:0]. c1ctrl 7:0 default : 0x00 access : r/w 19h c1cs[2:0] 7:5 gpo1 combination select. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 83 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) g1ts[1:0] 4:3 gpo1 type select. g1es 2 gpo1 early start function. g1tc 1 gpo1 toggle circuit enable. g1op 0 gpo1 output polarity. g2vst-l 7:0 default : 0x00 access : r/w 1ah g2vst[7:0] 7:0 line number that gpo2 start. g2vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 1bh g2vst[10:8] 2:0 see description for g2vst[7:0]. g2vend-l 7:0 default : 0x00 access : r/w 1ch g2vend[7:0] 7:0 line number that gpo2 ends. g2vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 1dh g2vend[10:8] 2:0 see description for g2vend[7:0]. g2hst-l 7:0 default : 0x00 access : r/w 1eh g2hst[7:0] 7:0 pixel number that gpo2 start. g2hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 1fh g2vht[10:8] 2:0 pixel description for g2hst[7:0]. g2hend-l 7:0 default : 0x00 access : r/w 20h g2hend[7:0] 7:0 pixel number that gpo2 ends. g2hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 21h g2hend[10:8] 2:0 see description for g2hend[7:0]. c2ctrl 7:0 default : 0x00 access : r/w c2cs[2:0] 7:5 gpo2 combination select. g2ts[1:0] 4:3 gpo2 type select. g2es 2 gpo2 early start function. g2tc 1 gpo2 toggle circuit enable. 22h g2op 0 gpo2 output polarity. g3vst-l 7:0 default : 0x00 access : r/w 23h g3vst[7:0] 7:0 line number that gpo3 start. g3vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 24h g3vst[10:8] 2:0 see description for g3vst[7:0]. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 84 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) g3vend-l 7:0 default : 0x00 access : r/w 25h g3vend[7:0] 7:0 line number that gpo3 ends. g3vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 26h g3vend[10:8] 2:0 see description for g3vend[7:0]. g3hst-l 7:0 default : 0x00 access : r/w 27h g3hst[7:0] 7:0 pixel number that gpo3 start. g3hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 28h g3vht[10:8] 2:0 pixel description for 3hst[7:0]. g3hend-l 7:0 default : 0x00 access : r/w 29h g3hend[7:0] 7:0 pixel number that gpo3 ends. g3hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 2ah g3hend[10:8] 2:0 see description for g3hend[7:0]. c3ctrl 7:0 default : 0x00 access : r/w c3cs[2:0] 7:5 gpo3 combination select. g3ts[1:0] 4:3 gpo3 type select. g3es 2 gpo3 early start function. g3tc 1 gpo3 toggle circuit enable. 2bh g3op 0 gpo3 output polarity. g4vst-l 7:0 default : 0x00 access : r/w 2ch g4vst[7:0] 7:0 line number that gpo4 start. g4vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 2dh g4vst[10:8] 2:0 see description for g4vst[7:0]. g4vend-l 7:0 default : 0x00 access : r/w 2eh g4vend[7:0] 7:0 line number that gpo4 ends. g4vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 2fh g4vend[10:8] 2:0 see description for g4vend[7:0]. g4hst-l 7:0 default : 0x00 access : r/w 30h g4hst[7:0] 7:0 pixel number that gpo4 start. g4hst -h 7:0 default : 0x00 access : r/w 31h - 7:3 reserved. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 85 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) g4vht[10:8] 2:0 pixel description for g4hst[7:0]. g4hend-l 7:0 default : 0x00 access : r/w 32h g4hend[7:0] 7:0 pixel number that gpo4 ends. g4hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 33h g4hend[10:8] 2:0 see description for g4hend[7:0]. c4ctrl 7:0 default : 0x00 access : r/w c4cs[2:0] 7:5 gpo4 combination select. g4ts[1:0] 4:3 gpo4 type select. g4es 2 gpo4 early start function. g4tc 1 gpo4 toggle circuit enable. 34h g4op 0 gpo4 output polarity. g5vst-l 7:0 default : 0x00 access : r/w 35h g5vst[7:0] 7:0 line number that gpo5 start. g5vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 36h g5vst[10:8] 2:0 see description for g5vst[7:0]. g5vend-l 7:0 default : 0x00 access : r/w 37h g5vend[7:0] 7:0 line number that gpo5 ends. g5vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 38h g5vend[10:8] 2:0 see description for g5vend[7:0]. g5hst-l 7:0 default : 0x00 access : r/w 39h g5hst[7:0] 7:0 pixel number that gpo5 start. g5hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 3ah g5vht[10:8] 2:0 pixel description for g5hst[7:0]. g5hend-l 7:0 default : 0x00 access : r/w 3bh g5hend[7:0] 7:0 pixel number that gpo5 ends. g5hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 3ch g5hend[10:8] 2:0 see description for g5hend[7:0]. c5ctrl 7:0 default : 0x00 access : r/w c5cs[2:0] 7:5 gpo5 combination select. 3dh g5ts[1:0] 4:3 gpo5 type select. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 86 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) g5es 2 gpo5 early start function. g5tc 1 gpo5 toggle circuit enable. g5op 0 gpo5 output polarity. g6vst-l 7:0 default : 0x00 access : r/w 3eh g6vst[7:0] 7:0 line number that gpo6 start. g6vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 3fh g6vst[10:8] 2:0 see description for g6vst[7:0]. g6vend-l 7:0 default : 0x00 access : r/w 40h g6vend[7:0] 7:0 line number that gpo6 ends. g6vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 41h g6vend[10:8] 2:0 see description for g6vend[7:0]. g6hst-l 7:0 default : 0x00 access : r/w 42h g6hst[7:0] 7:0 pixel number that gpo6 start. g6hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 43h g6vht[10:8] 2:0 pixel description for g6hst[7:0]. g6hend-l 7:0 default : 0x00 access : r/w 44h g6hend[7:0] 7:0 pixel number that gpo6 ends. g6hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 45h g6hend[10:8] 2:0 see description for g6hend[7:0]. c6ctrl 7:0 default : 0x00 access : r/w c6cs[2:0] 7:5 gpo6 combination select. g6ts[1:0] 4:3 gpo6 type select. g6es 2 gpo6 early start function. g6tc 1 gpo6 toggle circuit enable. 46h g6op 0 gpo6 output polarity. g7vst-l 7:0 default : 0x00 access : r/w 47h g7vst[7:0] 7:0 line number that gpo7 start. g7vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 48h g7vst[10:8] 2:0 see description for g7vst[7:0]. 49h g7vend-l 7:0 default : 0x00 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 87 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) g7vend[7:0] 7:0 line number that gpo7 ends. g7vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 4ah g7vend[10:8] 2:0 see description for g7vend[7:0]. g7hst-l 7:0 default : 0x00 access : r/w 4bh g7hst[7:0] 7:0 pixel number that gpo7 start. g7hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 4ch g7vht[10:8] 2:0 pixel description for g7hst[7:0]. g7hend-l 7:0 default : 0x00 access : r/w 4dh g7hend[7:0] 7:0 pixel number that gpo7 ends. g7hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 4eh g7hend[10:8] 2:0 see description for g7hend[7:0]. c7ctrl 7:0 default : access : r/w c7cs[2:0] 7:5 gpo7 combination select. g7ts[1:0] 4:3 gpo7 type select. g7es 2 gpo7 early start function. g7tc 1 gpo7 toggle circuit enable. 4fh g7op 0 gpo7 output polarity. g8vst-l 7:0 default : 0x00 access : r/w 50h g8vst[7:0] 7:0 when bank 0 register abh[7] = 0: g8vst[10:0]: line number that gpo8 start. when bank 0 register abh[7] = 1: g8vst-l[7:0]: gpo[7:0] gating control. g8vst-h[1:0]: o(e)sp / o(e)inv gating control. g8vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 51h g8vst[10:8] 2:0 see description for g8vst[7:0]. g8vend-l 7:0 default : 0x00 access : r/w 52h g8vend[7:0] 7:0 line number that gpo8 ends. g8vend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 53h g8vend[10:8] 2:0 see description for g8vend[7:0]. g8hst-l 7:0 default : 0x00 access : r/w 54h g8hst[7:0] 7:0 pixel number that gpo8 start. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 88 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) g8hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 55h g8vht[10:8] 2:0 pixel description for g8hst[7:0]. g8hend-l 7:0 default : 0x00 access : r/w 56h g8hend[7:0] 7:0 pixel number that gpo8 ends. g8hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 57h g8hend[10:8] 2:0 see description for g8hend[7:0]. c6ctrl 7:0 default : 0x00 access : r/w c8cs[2:0] 7:5 gpo8 combination select. g8ts[1:0] 4:3 gpo8 type select. g8es 2 gpo8 early start function. g8tc 1 gpo8 toggle circuit enable. 58h g8op 0 gpo8 output polarity. g9vst-l 7:0 default : 0x07 access : r/w 59h g9vst[7:0] 7:0 line number that gpo9 start. g9vst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 5ah g9vst[10:8] 2:0 see description for g9vst[7:0]. g9vend-l 7:0 default : 0x05 access : r/w 5bh g9vend[7:0] 7:0 line number that gpo9 ends. g9vend -h 7:0 default : 0x07 access : r/w - 7:3 reserved. 5ch g9vend[10:8] 2:0 see description for g9vend[7:0]. g9hst-l 7:0 default : 0x00 access : r/w 5dh g9hst[7:0] 7:0 pixel number that gpo9 start. g9hst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 5eh g9vht[10:8] 2:0 pixel description for g9hst[7:0]. g9hend-l 7:0 default : 0x00 access : r/w 5fh g9hend[7:0] 7:0 pixel number that gpo9 ends. g9hend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 60h g9hend[10:8] 2:0 see description for g9hend[7:0]. 61h c9ctrl 7:0 default : 0x04 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 89 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. tcon register (bank = 02) c9cs[2:0] 7:5 gpo9 combination select. g9ts[1:0] 4:3 gpo9 type select. g9es 2 gpo9 early start function. g9tc 1 gpo9 toggle circuit enable. g9op 0 gpo9 output polarity. gavst-l 7:0 default : 0x00 access : r/w 62h g7vst[7:0] 7:0 line number that gpoa start. gavst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 63h gavst[10:8] 2:0 see description for gavst[7:0]. gavend-l 7:0 default : 0x00 access : r/w 64h gavend[7:0] 7:0 line number that gpoa ends. gavend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 65h gavend[10:8] 2:0 see description for gavend[7:0]. gahst-l 7:0 default : 0x00 access : r/w 66h gahst[7:0] 7:0 pixel number that gpoa start. gahst -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 67h gavht[10:8] 2:0 pixel description for gahst[7:0]. gahend-l 7:0 default : 0x00 access : r/w 68h gahend[7:0] 7:0 pixel number that gpoa ends. gahend -h 7:0 default : 0x00 access : r/w - 7:3 reserved. 69h gahend[10:8] 2:0 see description for gahend[7:0]. cactrl 7:0 default : 0x00 access : r/w cacs[2:0] 7:5 gpoa combination select. gats[1:0] 4:3 gpoa type select. gaes 2 gpoa early start function. gatc 1 gpoa toggle circuit enable. 6ah gaop 0 gpoa output polarity. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 90 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. mwe register (bank = 03) mwe register (bank = 03) index mnemonic bits description - 7:0 default : - access : - 01h ~ 16h - 7:0 reserved. sw2ctl 7:0 default : 0x00 access : r/w, db - 7 reserved. mwew3en 6 mwe window 3 enable mwew2en 5 mwe window 2 enable mwew1en 4 mwe window 1enable. - 3:2 reserved. 17h mwe_wsel[1:0] 1:0 mwe window select. 00: mwe window 0. 01: mwe window 1. 10: mwe window 2. 11: mwe window 3. mwehst-l 7:0 default : 0x00 access : r/w, db 18h mwehst[7:0] 7:0 mwe window horizontal start. mwehst-h 7:0 default : 0x00 access : r/w, db - 7:3 reserved. 19h mwehst[10:8] 2:0 see description for mwehst[7:0]. mwevend-l 7:0 default : 0x06 access : r/w, db 1ah mwevend[7:0] 7:0 mwe window vertical end. mwevend-h 7:0 default : 0x00 access : r/w, db - 7:3 reserved. 1bh mwevend[10:8] 2:0 see description for mwevend[7:0]. mwehend-l 7:0 default : 0x00 access : r/w, db 1ch mwehend[7:0] 7:0 mwe window horizontal end. mwehend-h 7:0 default : 0x00 access : r/w, db - 7:3 reserved. 1dh mwehend[10:8] 2:0 see description for mwehend[7:0]. mwevst-l 7:0 default : 0x00 access : r/w, db 1eh mwevst[7:0] 7:0 mwe of sub window vertical start. mwevst-h 7:0 default : 0x00 access : r/w, db - 7:3 reserved. 1fh mwevst [10:8] 2:0 see description for mwevst [7:0]. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 91 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. mwe register (bank = 03) - 7:0 default : - access : - 20h ~ 3ah - 7:0 reserved. sppctrl 7:0 default : 0x01 access : r/w - 7:3 reserved. mwecen 2 mwe window c peaking enable. mweyen 1 mwe window y peaking enable. 3bh mwepen 0 mwe window peaking function enable. scoring 7:0 default : 0x00 access : r/w scth_2[3:0] 7:4 mwe window coring threshold. 3ch scth_1[3:0] 3:0 mwe window coring threshold. mwecpk 7:0 default : 0x08 access : r/w cpk_stp[1:0] 7:6 mwe window c peaking step. - 5 reserved. 3dh cpk_coef[4:0] 4:0 mwe window c peaking coefficient. - 7:0 default : - access : - 3eh - 7:0 reserved. mweypk 7:0 default : 0x08 access : r/w ypk_stp[1:0] 7:6 mwe window y peaking step. - 5 reserved. 3fh ypk_coef[4:0] 4:0 mwe window y peaking coefficient. sgammac 7:0 default : 0x00 access : r/w - 7:5 reserved. sgcr 4 mwe window gamma correction rounding function. 0: disable. 1: enable. - 3:1 reserved. 40h sgcb 0 mwe window gamma correction function control. 0: bypass gamma correction function. 1: enable gamma correction function. - 7:0 default: 0x00 access : r/w 41h ~ ffh - 7:0 reserved. mcu control register (registers c000h ~ c0ffh) mcu control register index mnemonic bits description free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 92 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. mcu control register - 7:0 default : - access : - 00h ~ 07h - 7:0 reserved. wd_swz1 7:0 default : 0xaa access : r/w 08h wd_swz[7:0] 7:0 watchdog timer software disable key low byte. wd_swz2 7:0 default : 0x55 access : r/w 09h wd_swz[15:8] 7:0 watchdog timer software disable key high byte watchdog timer can be disabled by software only when sfr_d8[1]=0, xfr_c008=8 h55 & xfr_c009=8 haa). - 7:0 default : - access : - 0ah ~ 0fh - 7:0 reserved. intmask_en_adc 7:0 default : 0x00 access : r/w 10h inmask_en_adc[7:0] 7:0 6: en_start. 5: en_stop. 4: en_datr. 3: en_datw. 0: en_id. adc_int_flag 7:0 default : 0x00 access : r/w 11h adc_int_flag[7:0] 7:0 6: start. 5: stop. 4: datr. 3: datw. 2: rw. 1: adr. 0: id. adc_wbuf_rdp 7:0 default : 0x00 access : ro 12h adc_wbuf_rdp[7:0] 7:0 adc ddcci host write buffer. adc_rbuf_wdp 7:0 default : 0x00 access : r/w 13h adc_wbuf_wdp[7:0] 7:0 adc ddcci host read buffer. inmask_en_dvi 7:0 default : 0x00 access : r/w 14h inmask_en_dvi[7:0] 7:0 6: en_start. 5: en_stop. 4: en_datr. 3: en_datw. 0: en_id. dvi_int_flag 7:0 default : 0x00 access : r/w 15h dvi_int_flag[7:0] 7:0 6: start. 5: stop. 4: datr. free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 93 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. mcu control register 3: datw. 2: rw. 1: adr. 0: id. dvi_wbuf_rdp 7:0 default : 0x00 access : ro 16h dvi_wbuf_rdp[7:0] 7:0 dvi ddcci host write buffer. dvi_rbuf_wdp 7:0 default : 0x00 access : r/w 17h dvi_wbuf_wdp[7:0] 7:0 dvi ddcci host write buffer. ddc2bi_ctrl 7:0 default : 0x00 access : r/w 18h ddc2bi_ctrl[7:0] 7:0 6: std_rom_io. 5: std_adc_io. 4: std_dvi_io. 1: en_no_ack. 0: en_hold_ck. 19h adc_2bi_id 7:0 default : 0xb7 access : r/w en_adc_2bi 7 enable ddc2bi function(adc). adc_2bi_id 6:0 two-wire serial bus slave address[7:1] of ddc2bi. dvi_2bi_id 7:0 default : 0xb7 access : r/w en_dvi_2bi 7 enable ddc2bi function(dvi). 1ah dvi_2bi_id 6:0 two-wire serial bus slave address[7:1] of ddc2bi. - 7:0 default : - access : - 1bh ~ 20h - 7:0 reserved. keypad_adc1 7:0 default : 0x00 access : ro - 7:6 reserved. 21h keypad_adc1[5:0] 5:0 keypad adc register 1. keypad_adc2 7:0 default : 0x00 access : ro - 7:6 reserved. 22h keypad_adc2[5:0] 5:0 keypad adc register 2. keypad_adc3 7:0 default : 0x00 access : ro - 7:6 reserved. 23h keypad_adc3[5:0] 5:0 keypad adc register 3. - 7:0 default : - access : - 24h ~ 2fh - 7:0 reserved. mcu_p0_out_en 7:0 default : 0x00 access : r/w 30h mcu_p0_out_en[7:0] 7:0 mcu port 0 output enable control (force input / output mode). 31h mcu_p0_fmd 7:0 default : 0x00 access : - free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 94 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. mcu control register mcu_p0_fmd 7:0 mcu port 0 force mode. 0: input. 1: output. mcu_p0_rod_en 7:0 default : 0x00 access : r/w 32h mcu_p0_rod_en[7:0] 7:0 mcu port 0 real open drain mode enable. 0: drive high at 1 st low to high clock. 1: never drive high. mcu_p1_out_en 7:0 default : 0x00 access : r/w 33h mcu_p1_out_en[7:0] 7:0 mcu port 1 output enable control (force input / output mode). mcu_p1_fmd 7:0 default : 0x00 access : - 34h mcu_p1_fmd 7:0 mcu port 1 force mode. 0: input. 1: output. mcu_p1_rod_en 7:0 default : 0x00 access : r/w 35h mcu_p1_rod_en[7:0] 7:0 mcu port 1 real open drain mode enable. 0: drive high at 1 st low to high clock. 1: never drive high. mcu_p2_out_en 7:0 default : 0x00 access : r/w 36h mcu_p2_out_en[7:0] 7:0 mcu port 2 output enable control (force input / output mode). mcu_p2_fmd 7:0 default : 0x00 access : - 37h mcu_p2_fmd 7:0 mcu port 2 force mode. 0: input. 1: output. mcu_p2_rod_en 7:0 default : 0x00 access : r/w 38h mcu_p2_rod_en[7:0] 7:0 mcu port 2 real open drain mode enable. 0: drive high at 1 st low to high clock. 1: never drive high. mcu_p3_out_en 7:0 default : 0x00 access : r/w 39h mcu_p3_out_en[7:0] 7:0 mcu port 3 output enable control (force input / output mode). mcu_p3_fmd 7:0 default : 0x00 access : - 3ah mcu_p3_fmd 7:0 mcu port 3 force mode. 0: input. 1: output. mcu_p3_rod_en 7:0 default : 0x00 access : r/w 3bh mcu_p3_rod_en[7:0] 7:0 mcu port 3 real open drain mode enable. 0: drive high at 1 st low to high clock. 1: never drive high. 3ch mcu_p4_out_en 7:0 default : 0x00 access : r/w free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 95 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. mcu control register mcu_p4_out_en[7:0] 7:0 mcu port 4 output enable control (force input / output mode). mcu_p4_fmd 7:0 default : 0x00 access : - 3dh mcu_p4_fmd 7:0 mcu port 4 force mode. 0: input. 1: output. mcu_p4_rod_en 7:0 default : 0x00 access : r/w 3eh mcu_p4_rod_en[7:0] 7:0 mcu port 4 real open drain mode enable. 0: drive high at 1 st low to high clock. 1: never drive high. - 7:0 default : - access : r/w 3fh ~ ffh - 7:0 reserved. register table revision history date bank register 01/28/05 created first version. 0 0x63, 0xc2-0xc8, 0xf1 1 0x51, 0x63, 0x66 3 updated for clarification. 02/04/05 mcu 0x0a, 0x20-0x23 03/01/05 1 0x2d 0 0xb3-0xbb 04/08/05 mcu 0x19, 0x1a 05/18/05 00 0x57h, 0x81h 09/20/05 00 0x63 11/07/05 00 0x39, 0x9f free datasheet http://
TSUM16AK sxga lcd controller with mcu, analog interface and dual lvds transmitter data sheet version 1.0 version 1.0 - 96 - 11/29/2005 copyright ? 2005 mstar semiconductor, inc. all rights reserved. this page is intended to leave blank. free datasheet http://

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