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NB639 high efficiency , fast transient, 8a , 28v sy nchronous step-down converter in a tiny qfn20 (3x4mm) package NB639 rev.1.13 www.monolithicpower.com 1 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology descri ption the NB639 is a fully integrated, high frequen cy synchronous rectif ied step-down switch mode converter. it offers a very compac t solution t o achieve 8a continuous output curre nt over a wide input supply range with excellent load and line regulation. the NB639 o perates at high efficiency over a wide output curre nt load rang e. to further optimize efficiency at light load, this device?s v cc supply is designed to be biased externally. constant-on-time (cot) control mode provi des fast transient respo n se and eases loop stabilization. full pro t e c t i on fea t ur e s in clude scp , ocp, ovp, uvp an d t h e r mal sh utd o w n. the nb 639 requ ir es a m i n i mum num ber of r e a d ily availab l e st and ard exte rna l compo nen ts and is availab l e in a sp a c e- saving qf n20 (3x4m m ) packa ge . features ? wide 4.5v to 28v operating input range ? 8a output current ? internal 30 m ? high-si de, 12m ? low-side power mos f ets ? proprietary switching l o ss reduction technique ? 1% reference voltage ? programma ble soft start time ? soft shutdown ? programma ble switchin g frequency ? scp, ocp, ovp, uvp protection and thermal sh utdown ? output adjustable from 0.8v to 13v ? availa ble i n a q f n 2 0 ( 3 x 4 m m ) packa g e appli c ations ? notebook systems and i/o power ? networking systems ? optical communication systems ? distributed power pol systems all m ps p ar t s ar e le ad- fre e an d adh er e to th e r ohs d i r e ctiv e. f o r m p s g r e e n sta t u s , plea se v isit mps w ebsite under quali t y assuran c e. ?mp s ? an d ?t he f u ture o f ana l o g ic t e chno lo gy ? ar e re gi ste r ed tr ade ma r ks o f monolithic power systems, inc. typical application http://
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 2 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. ordering information part number* package top marking NB639dl qfn20 (3x4mm) 639 * for tap e & reel, ad d suf f ix ?z (e.g. NB639dl?z ) for rohs co mpliant pa ckaging, ad d su ffix ?lf (e.g. NB639 dl ?lf ?z) package reference t op view 1 2 3 4 5 6 16 15 14 13 12 agnd freq fb ss en pgood pgnd pgnd pgnd pgnd pgnd pgnd sw sw bst exposed p ad on backside in sw sw vcc in in in in sw sw 789 1 0 11 20 19 18 17 absolute m a xi mum ratings (1) supply voltage v in ....................................... 30v supply voltage v cc ........................................ 6v v sw ........................................ -0.3v to v in + 0.3v v bst ...................................................... v sw + 6v i vin (rms) ........................................................ 3.5a v pgood ................................... -0.3v to v cc +0.6v all other pins .................................. -0.3v to +6v continuous power dissipation (t a = +25c) (2) ???? ? ???? ? ???? ? ????.2. 6w junction te mperature ............................... 150 c lead temperature .................................... 260 c storage temperature ............... -65 c to +150 c recommended operating conditions (3) supply voltage v in ........................... 4.5v to 28v supply voltage v cc ........................................ 5v output voltage v out ......................... 0.8v to 13v operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc q f n 2 0 ( 3 x 4 m m ) ...................... 48 ...... 10 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction tempe r ature t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the ma ximu m allow able cont inuous po w e r di ssipation at an y ambient tem peratur e is calculated b y p d (max)=(t j (max)- t a )/ ja . excee d ing the maximum allow able po wer dissipation w ill cause ex cessive die temperature, and the reg u l ator w ill go into thermal sh utdo w n . inte rnal thermal shutdo w n circuitr y protects the device from perma ne nt damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on je sd51-7, 4 - la y e r pcb.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 3 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. electri c al characteristi cs v in = 12v, v cc =5v, t a = +25 c, unle ss otherw i s e noted. parameters symbol condition min typ max units input supply curre n t (shutdo wn ) i in v en = 0v 0 a input supply curre n t (quie s cent ) i in v en = 2v, v fb = 1v 40 a v cc supply current (quie s cent ) i v cc v en = 2v, v fb = 1v 350 a hs s w it ch o n re sist a n c e (5) hs rds-on 30 m ? ls s w it ch on resi st an ce (5 ) ls rds-on 12 m ? switch leakage sw lkg v en = 0v , v sw = 0v o r 12v 0 10 a current limit i li m i t 16.5 a one-shot on time t on r freq =348 k ? , v out =1.05v 360 ns minimum off time (5) t off 100 ns fold-ba ck off time (5) t fb i li m =1 (hig h) 7.5 s ocp hold-off time (5) t oc i li m = 1 (high) 40 s feedb ack vol t age v fb 807 815 823 mv feedb ack cu rre nt i fb v fb = 815mv 10 50 na soft start chargin g cu rren t +i ss v ss =0v 8.5 a soft stop discha r gin g cu rrent -i ss v ss =0.815v 8.5 a powe r goo d risi ng th re shold pgoo d vth - hi 0.9 v fb powe r goo d falling th re shold pgoo d vth - lo 0.85 v fb powe r goo d risi ng d e lay t pgood ts s = 1m s 1 ms powe r goo d risi ng d e lay t pgood tss = 2m s 1.5 ms powe r goo d risi ng d e lay t pgood ts s = 3m s 2 ms en rising threshold en vth-hi 1.05 1.35 1.60 v en thresh old hysteresi s en vth-h y s 250 420 550 mv en input cu rrent i en v en = 2v 2 a v cc under-voltage lo cko u t thre sh old ri sing v cc uv vth 3.8 4.0 4.2 v v cc under-voltage lo cko u t thre sh old hy stere s i s v cc uv hy s 880 mv v out over-vo l tage prote c tion thre sh old v ovp 1.25 v fb v out unde r-v oltage detecti on thre sh old v uvp 0.7 v fb therm a l shut down t sd 150 c therm a l shut down hyste r e s is t sd-h y s 25 c notes : 5) guaranteed by design.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 4 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. pin functio n s pin # nam e description 1 agnd analog ground. 2 freq frequency set during ccm operation. the on period is determined by the input voltage and the frequency-set resistor conne cted to freq pin. connect a resistor to in for line feed-forward. decouple with a 1nf capacitor. 3 fb feedback. an external resistor divider fr om the output to gnd, tapped to the fb pin, sets the output voltage. 4 ss soft start. conne ct an external ss capa cito r to prog ram the soft start time for the swit ch mod e regul ator. wh en the en pin beco m e s high, an intern al current sou r ce (8.5ua) charges up the ss capacitor and t he ss voltage slowly ramps up from 0 to v fb smoothly. when the en pin becomes low, an internal current source (8.5 a ) discharges the ss capacitor and the ss voltage slowly ramps down. 5 en en=1 to enable the NB639. for automatic start-up, connect en pin to in with a 100k ? resistor. it includes an internal 1m ? pull-down resistor. 6 pgoo d powe r goo d output. the output of this pin i s an o pen d r ain a n d is hig h if the output voltag e is hig h e r th an 90% of th e nomin al vol t age. the r e i s del ay from fb 90% to pgood hig h , whi c h is 5 0 % of ss time plus 0.5ms. 7 bst bootstrap. a capacitor connected between sw and bs pins is required to form a floating supply across the high-side switch driver. 8, 19 in supply voltage. the NB639 operates from a +4.5v to +28v input rail. c1 is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 9, 10, 17, 18 sw switch output. use wide pcb trac es and multiple vias to make the connection. 11-1 6 pgnd system ground. this pin is the referenc e ground of the regulated output voltage. for this reason care must be taken in pcb layout. 20 vcc external 5v supply. this 5v supply has to be applied in order to bias the device. decouple with a 1f capacitor as close to this pin as possible.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 5 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in =12v, v out =1.05v, l=1.0h, t a =+25c, unless otherwise noted.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 6 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1.0h, t a =+25c, unless otherwise noted.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 7 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1.0h, t a =+25c, unless otherwise noted.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 8 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. block diagram figure 1?functional block diagram
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 9 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. operation pwm operation the NB639 is a fully integrated synchronous rectified step-down switch mode converter. constant-on-time (cot) control is employed to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) is below the reference voltage (v ref ) which indicates insufficient output voltage. the on period is determined by the input voltage and the frequency-set resistor as follows: fre q on in 12 r ( k ) t( n s ) v( v ) 0 . 4 = ? ( 1 ) after the on period elapses, the hs-fet is turned off, or becomes off state. it is turned on again when v fb drops below v ref . by repeating operation th is way, the converter r egulates th e output voltage. the inte grated low-side mosfet (ls-fet) is turned on w hen the hs-fet is in it s off state to minimize the conduction loss. the re will be a de ad short be tween input and gnd i f both hs-fet and ls-fet are turned on at th e same time. it?s calle d shoot-through. in order to avoid shoot-through, a dead-time (dt) is internally generated between hs-f et off and ls- fet on, or ls-fet off and hs-fet on. heav y - loa d operatio n figure 2?heav y loa d operatio n as figure 2 shows, when the outp u t current is high, the hs-fet and ls-fet repeat on/off a s described a bove. in this operation, the inducto r current will never go to zero. it?s calle d continuous- c onduction- mode (ccm) operation. in ccm operation, the switching frequ ency (f sw ) is fairly consta nt. light-load operation when the load current decreases, the NB639 reduces the switching fr equency automatically to maintain high efficiency. the light load operation is shown in figure 3. the v fb does not reach v ref when the inductor current is approaching zero. as the output curr ent reduces from heavy- load condition, the inductor current also decreases, and eventually comes close to zer o . the ls-fet driver turns into tri-state (high z) whenever th e inductor current reaches zero level. a current modulator takes over the control of l s - fet and limits the ind u ctor curren t to less th an 600 a. hen c e, the output capacit ors dischar ge slowly to gnd through ls-fet as well as r1 a n d r2. as a result, the efficiency at light load condition is greatly improved. at light lo ad condition, t he hs-fet is not tur ned on a s frequently as at heavy load condition. this is called skip mode. figure 3?light load operation as the output current increases from the lig ht load condition, the time period within which t he current modulator regulates beco m es shorter. the hs-fet is turned on more frequently. hence, t h e s w i t c h i n g f r e q u e n c y i n c r e a s e s co rrespondingly. the output current reaches the crit ical level when the current modulator time is zero. the critica l level of th e output current is d e termined as follows:
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 10 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. in o u t out out sw i n (v v ) v i 2l f v ? = ( 2 ) it turns into pwm mode once the output current exceeds the critica l level. after that, the switching frequency stays fairly constant over the output current rang e. sw itching frequenc y constant-on-time (cot) control is used in the NB639 and there is no dedicated o scillator in t h e ic. the inpu t voltage is f eed-forwarded to the on - time one-shot timer through the resistor r freq . the duty ra tio is kept as v out /v in . hence, the switching frequency is fairly con s tant over t h e input voltag e range. the switch ing frequen c y can be set a s follows: 6 sw fre q in delay in o u t 10 f( k h z ) 12 r ( k ) v( v ) t( n s ) v( v ) 0 . 4 v ( v ) = + ? (3) where t delay is the comparator de lay. it?s about 40ns. NB639 is optimized to operate at high switch ing frequency with high e fficiency. high switchin g frequency makes it possible to utilize small size d lc filter co mponents to save system pcb space. ramp com pensation figure 4 and figure 5 show jitter occurring in both pwm mode and skip mode. when there is noise in the v fb downwa r d slope, the on time o f the hs-fet driver de viates from its intende d location an d produces jitter. it is necessary to understand that there is a relationsh i p between a system?s stability and t he steepne ss of the v fb ripple?s downward slope. the slope steepness o f the v fb ripple dominates in noise immunity. the magnitude of the v fb ripple doesn?t affect the noise immunity directly. v re f v fb hs dr i ver v noise jitter v slo pe1 figure 4?jitter in pwm mode v fb hs dr i ver jitter v ref v slo pe2 v noise figure 5?jitter in skip mode when the output capa citors are ceramic ones, the esr ripple is not high enough t o stabilize t he system, an d external ramp co mpensation is needed. i i fb i c4 i r4 i fb figure 6?simplified circuit in pwm mode w i th external ramp compensation in pwm mo de, an equivalent circu i t with hs-fet off and the use of an external ramp compensation circuit ( r 4, c4) is simplified in figure 6. the external ramp is derived from th e inductor rip p le current. if one chooses c4, r1, and r2 to meet the follo wing condition:
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 11 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. 12 sw 4 1 2 rr 11 2f c 5 r r ?? < ?? + ?? (4) then one ca n have: r 4 c4 f b c4 ii i i =+ (5) the downward slope o f the v fb ripple can b e estimated as: out slo p e 1 v v r4 c 4 ? = (6) as one can see from equation (6 ), if there is instability in pwm mod e , one can reduce eith er r4 or c4. if c4 can not be reduced further due to limitation from equation (4), then one can only reduce r4. from bench experiment s, vslope1 is expected to be around 20~40v/ms. in the case of poscap or other types of capacitor with higher e s r, the external ramp is not necessa ry. figure 7?simplified circuit in pwm mode w i thout ext e rnal ramp compensation figure 7 sh ows the equivalent circuit in pwm mode with the hs-fet off an d without an external ramp circuit. the esr ripple dominates the output ripple. the downward slope of the v fb ripple is: ref sl op e 1 es r v v l ? = ( 7 ) from equation (7), o ne can see that th e downward slope of v fb ripple is proportional to esr/l. therefore, it?s necessary to know th e minimu m esr value of the ou tp ut capacitor s when no external ramp is used. th ere is also a limitation w i th inducta nce in th is case. t h e smaller the inductance, the more sta b le it will be. from our b ench experiments, it is recommend ed to keep vslope1 aroun d 15~30v/ms. while in skip mode, the downward slope is n o t related to th e external ramp. in skip m ode, the downward slope of the v fb ripple is the same whether the external ramp is used or not. figure 8 sh ows an equivalent circuit with hs-fet off and the current modulato r regulating the ls-fet. the down w ard slope of the v fb ripple can be de termined as follows (i mod is ignored h e re): () ref sl o pe 2 12 o u t v v rr c ? = + (8) i mod figure 8?simplified circuit in skip mode to keep th e system stable during light lo ad condition, th e values of the fb re sistors should not be too big. it is re commended to keep the v slope2 valu e around 0.4~0.8mv/ ms. it sho u ld be noted th at im od is excluded from the equatio n because it d oes not impact the system?s stability at light load conditions. bootstrap charging the floating power mosfet driver i s recommend ed to be powered by a n external v cc through d2 as shown in figure 9. this floatin g driver has its own uvl o protection. this uvlo?s rising thre s hold is 2.2 v with a hy steresis of 150m v. u1 will regulate to m a intain bst voltage across c4 if (v cc -v sw ) is less tha n 3.5v. the recommend ed external bst diode d2 is in4148, and the bst cap c4 is 0.1~1 f.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 12 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. v in v out d1 m1 bst vcc c4 d2 l1 sw u1 3.5v c2 figure 9?bootstrap charging circuit soft start/stop the nb63 9 employs soft start/stop (ss) mechanism to ensure smooth o utput during power-up and power shutdown. when the en pin becomes high, an internal current source (8.5 a) charges up the ss cap. the ss cap voltag e takes over the v ref voltage to the pwm comparator. the output voltage smoothly ramp s up with the ss voltage. once the ss voltage reaches the same level as the ref voltage, it keeps ramping up while ref takes over the pwm comp arator. at this point, the soft sta r t finishes and it enters into steady state operation. when the en pin bec omes low, the ss cap voltage is discharged t h rough an 8.5 a internal current sou r ce. once the ss voltage reache s ref voltage , it take s over the pwm comparator. the output voltage will decrease smoothly with ss voltage until zero le vel. the s s cap valu e can be deter mined as follows: ss s s ss re f t( m s ) i ( a ) c( n f ) v( v ) = (9) if the outpu t capacitors have large capacitance value, it?s n o t recomme nded to set the ss time too small. a minimal value of 4. 7nf should be used if the output capacitance value is large r than 330uf. pow e r good (pgood) the NB639 has power -good (pgood) outp u t. the pgood pin is the open drain of a mosfet. it should be connecte d to v cc or other volta ge source thro ugh a resistor (e.g. 10 0k). after the input voltage is applied , the mosf et is turned on, so that the pgood pin is pu lled to gnd before ss ready. after fb voltage reaches 90 % of ref voltage, the pgood pin is pulled h i g h after a delay. the pgood delay time is determined as follow s : p good s s t ( ms ) 0 . 5 t ( ms ) 0 . 5 = + (10) when the fb voltage drops to 85 % of the ref voltage, the pgood pin will be pulle d low. over-cu rre nt protection (ocp) and sho r t- circuit protection (scp) the NB639 has cycle- b y-cycle over-current limi t control. the inductor cu rrent is monitored durin g the on state. once it detects that the inductor current is higher than the current limit, the hs- fet is turn ed off. at t he same time, the ocp timer is started. the ocp timer is set as 40 s. if in the following 40 s, the current lim it is hit for every cycle, then it?ll tri gger ocp. the converter needs power cycle to re start after it triggers ocp. when the current limit is hit and the fb voltage is lower than 50% of the ref voltage, the devic e considers th is as a dea d short on the output and triggers ocp immediately. this is short circu it protection ( s cp). over/under-voltage protection (ovp/uvp) the NB639 monitors the output voltage through a resistor d i vider feedback (fb) volta ge to dete c t overvoltage and unde rvoltage on the outpu t. when the fb voltage is higher than 125% of th e ref v o ltage, it?ll trigg e r o vp. once it trigg e rs ovp, the l s -fet is always on while the hs-f et is always off. it needs power cycle to power up again. when the fb vol t age is belo w 50% of th e ref voltage (0.815v), uvp will be triggere d . usually, uvp accompanies a h i t in current limit and this results in scp. uvlo p r otection the NB639 has under-voltage lock-out protection (uvlo). when v cc is higher than the uvlo rising threshold voltage, the NB639 will be powered up. it shuts off when v cc is lower than the uvlo falling threshold voltage. this is non- latch protection.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 13 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. thermal shutdow n thermal shutdown is employed in the NB639. the junction temperature of the ic is internally monitored. if the junction temperature exceeds the threshold value (typically 150oc), the converter shuts off. this is non-latch protection. there is about 25oc hysteresis. once the junction temperature drops to around 125oc, it initiates a soft start.
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 14 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. appli c ation information setting the output voltage the output voltage is set by using a resistor divider from the output voltage to fb pin. when there is no external ramp employed, the output voltage is set by feedback resistors r1 and r2. first, choose a value for r2. a value within 5k ? -40k ? is recommended to ensure stable operation. then, r1 is determined as follows: ou t r e f ref vv r1 r 2 v ? = (11) when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacit or c4.the output voltage is influen ced by ramp voltage v ramp except r divider. the v ramp can b e calculated a s shown in equation 19. choose a value within 5k ? -40k ? for r2. the value of r1 then is deter mined as follows: re f ra m p ou t r e f r a mp 1 r1 1 vv 1 2 1 r4 r2 v v v 2 = + ? ?? ? ? ?? ?? (12) using equation 12 to calculate the o u tput voltage can be com p licated. furtherm o re, as v ramp changes du e to changes in v out an d v in , v fb al so varies. to i m prove the output voltage accuracy and simplify the calcula tion of r2 in equation 12, a dc-blocking capacitor cdc can be added. figure 10 shows a simplified cir cuit with extern al ramp compensation an d a dc-blocking capacitor . with this ca pacitor, r1 can easily b e obtained by using equation 11. cdc is sug gested to b e 1-4.7 f for better d c blocking p e rformance. figure 10?simplified circuit w i th external ramp com pensation and dc-bloc king capacitor. input capacitor the input current to the step-down converter is discontinu o u s. therefor e, a capacitor is require d to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic ca pacitors are recommen ded for best performance. in the layout, it?s recommended to put the inpu t capacitor s as close to the in pin as possible. the capa citance va ries significantly over temperature. capacitors with x 5 r and x 7 r ceramic die l ectrics are recommen ded because they are fairly stable over temperature. the capacitors must also have a r i pple current rating greater than the maxi mum input ripple current of th e converter. the input r i pple curren t can be estimated as follows: ou t o u t ci n o ut in i n vv ii ( 1 ) vv = ? (13) the worst-case conditio n occurs at: out ci n i i 2 = (14) for sim plifi c ation, cho o se the in put capacit or whose rms current rating is greate r than half of the maxi mu m load current. the input ca pacitance value determines the inpu t voltage ripple of the co nverter. if there is inp u t voltage ripple requirement in the sy stem design , choose the input cap a citor that meets th e specifi c ation .
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 15 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. the input voltage ripple can be estimated as follows: out o u t out in sw i n in in iv v v( 1 ) fc v v = ? (15) the worst-case conditio n occurs at v in = 2v out , where: out in sw in i 1 v 4f c = ( 1 6 ) output cap acitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors a r e recommended. the o u tput voltag e ripple can b e estimated as: ou t o u t ou t esr sw in sw out vv 1 v( 1 ) ( r ) fl v 8 f c = ? + (17 ) where r esr is the equivalent serie s resistance (esr) of the output capa citor. in the case of ceramic capacitors, th e impedance at the switching frequency is domi nated by th e capacitan ce . the outpu t voltage rip p le is mainly caused by the capacita n ce. for sim plification, th e output voltage ripple ca n be estimated as: out o ut ou t 2 in sw o u t vv v( 1 ) v 8f l c = ? ( 1 8 ) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the volt age ramp is expected to be around 30mv. the e x ternal ramp can be ge nerated thr ough resist or r4 and capacitor c 4 using the following equ ation: in out o n ra m p (v v ) t v r4 c 4 ? = (19) the c4 should be chosen so that it meets the following co ndition: 12 sw 1 2 rr 11 () 2f c 4 5 r r < + ( 2 0 ) in the case of poscap capacitor s, the esr dominates the impedance at the switching frequency. the ramp voltage gene rated from the esr is high enough to stabilize the system. therefore, an external ramp is n o t needed. a minimu m esr value of 12m ? is required to ensure sta b le operation of the converter. for simplificatio n, the output ripple can b e approximate d as: out o u t ou t esr sw in vv v( 1 ) r fl v = ? (21) inductor the inductor is re quired to sup p ly constan t current to the output lo ad while be ing driven by the switch ing input voltage. a larger valu e inductor will result in less ripple cu rrent that wi ll result in lower output ripple voltage. however, a larger value inductor will have a la rger physical size, highe r series r e sistance, and/or low e r saturation current. a good rule for determining the inductor value is to allow the peak-to-pea k ripple curre nt in the ind u ctor to be approximate l y 30~40% of the ma ximum switch current limit. also, make sure that th e peak indu ctor current is below the maxi mum switch current limit. the inductance value can be calcula t ed as: ou t ou t sw l i n vv l( 1 ) fi v = ? ( 22) where i l is the peak-to-peak inductor ripple current. choose an inductor tha t will not sa turate under the maxi mu m inductor peak curren t. the peak inductor curr ent can be calculated a s : ou t o u t lp o u t sw in vv ii ( 1 ) 2f l v =+ ? (23)
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 16 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. table 1?inductor selection guide part numb er manufac ture r inducta nce (h ) dc r (m ? ) curre nt rating (a) dimensions l x w x h (m m 3 ) s w i t ching freque nc y (kh z ) pcmc-13 5 t-r68m f cyntec 0.68 1.7 34 13.5 x 12.6 x 4.8 600 fda12 54-1r0m toko 1 2 25.2 13.5 x 12.6 x 5.4 300~600 fda12 54-1r2m toko 1.2 2.05 20.2 13.5 x 12.6 x 5.4 300~600 t y pical des i gn parameter tables the following tables include r e commende d component values for typical ou tput voltages (1.05v, 1.2v, 1.8v, 2. 5v, 3.3v) and switching frequencies (300khz, 500khz, and 700khz). refer to tables 2-4 for design cases witho u t external ra mp compen sation and tables 5-7 for design case s with external ramp compensation. external ra mp is not needed when high-esr capacitors, such a s ele c trolytic or poscaps are used. external ramp is needed when low-esr capacitors, such as cer a mic capacitors are use d . for cases n o t listed in this datashe et, a calcula t or in excel spreadsheet can also be requested through a lo cal sale s re presentative to assist with the calcu l ation. table 2?300khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r freq (k ? ) 1.05 2.2 12.1 43 301 1.2 2.2 12.1 24 360 1.8 2.2 19.6 15.8 499 2.5 2.2 30 14.7 680 3.3 2.2 40.2 13.3 806 table 3?500khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r freq (k ? ) 1.05 1 12.1 43 180 1.2 1 12.1 24 200 1.8 1 19.6 15.8 309 2.5 1 30 14.7 402 3.3 1 40.2 13.3 523 table 4?700khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r freq (k ? ) 1.05 1 12.1 43 120 1.2 1 12.1 24 140 1.8 1 19.6 15.8 210 2.5 1 30 14.7 309 3.3 1 40.2 12.4 402 table 5?300khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r freq (k ? ) 1.05 2.2 12.1 43 330 220 301 1.2 2 .2 12.1 24 330 220 360 1.8 2 .2 19.6 15.2 499 220 499 2.5 2 .2 30 14.7 499 220 680 3.3 2 .2 40.2 13 604 220 806 table 6?500khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r freq (k ? ) 1.05 1 12.1 43 330 220 180 1.2 1 12.1 24 330 220 196 1.8 1 19.6 15.8 330 220 309 2.5 1 30 14.7 383 220 402 3.3 1 40.2 12 499 220 522 table 7?700khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r freq (k ? ) 1.05 1 12.1 43 220 220 120 1.2 1 12.1 24 220 220 140 1.8 1 19.6 15.8 261 220 210 2.5 1 30 14.3 261 220 270 3.3 1 40.2 12 360 220 383
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 17 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical application figure 11 ? t y pical application circuit w i t h lo w esr ceramic ca pacitor figure 12 ? t y pical application circuit w i t h no external ramp figure 13 ? typical application circuit with low esr ceramic capacitor and dc-blocking capacitor .
NB639 ? high efficiency, fast transie nt synchronous step-down converter NB639 rev.1.13 www.monolithicpower.com 18 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. layout recommendation 1. the high current paths (gnd, in, and sw) should be placed very close to the device with short, d i rect and wide traces. 2. put the input capacitor s as close to the i n and gnd pi ns as possib l e. 3. put the decoupling cap a citor as close to the v cc and gnd pins as po ssible. 4. keep the switching no de sw short and away from the feedback netw o rk. 5. the external feedback resistor s should be placed next to the fb pin. make sure that there is no via on the fb trace. 6. keep the bst voltage path (bst, c bst, and sw) as shor t as possible . 7. keep the bo ttom in and sw pads c onnected with large copper to achieve better thermal performance. 8. four-layer layout is stro ngly recommended to achieve better thermal performance. r3 c3 p g o o d f r e q a g n d 1 6 1 5 1 4 1 3 1 2 1 1 1 2 3 4 5 6 e n s s p g n d f b s w i n p g n d p g n d p g n d p g n d p g n d c6 r3 r3 r5 r6 c6 i n i n s w c6 d2 top la y er s inner1 la y e r gn d inner2 la y e r bottom la yer figure 14?pcb la y o u t
NB639 ? high efficiency, fast transie nt synchronous step-down converter notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. NB639 rev. 1.13 www.monolithicpower.com 19 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. package informati o n qfn20 (3x4mm)

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