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ds031 august 1, 2003 www.xilinx.com product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. this document includes all four modules of the virtex-ii platform fpga data sheet. module 1: introduction and overview ds031-1 (v2.0) august 1, 2003 7pages ? summary of features general description device/package combinations and maximum i/o ordering information module 2: functional description ds031-2 (v3.0) august 1, 2003 40 pages detailed description digitally controlled impedance (dci) configurable logic blocks (clbs) sum of products 3-state buffers 18-kb block selectram? resources 18-bit x 18-bit multipliers global clock multiplexer buffers digital clock manager (dcm) active interconnect technology creating a design configuration module 3: dc and switching characteristics ds031-3 (v3.0) august 1, 2003 38 pages electrical characteristics performance characteristics switching characteristics pin-to-pin output parameter guidelines pin-to-pin input parameter guidelines dcm timing parameters module 4: pinout information ds031-4 (v2.0) august 1, 2003 225 pages pin definitions pinout tables - cs144 chip-scale bga package - fg256 fine-pitch bga package - fg456 fine-pitch bga package - fg676 fine-pitch bga package - bg575 standard bga package - bg728 standard bga package - ff896 flip-chip fine-pitch bga package - ff1152 flip-chip fine-pitch bga package - ff1517 flip-chip fine-pitch bga package - bf957flip-chip bga package important note: the virtex-ii platform fpga data sheet is created and published in separate modules. this complete version is provided for easy downloading and searching of the complete document. page, figure, and table numbers begin at 1 for each module, and each module has its own revision history at the end. use the pdf "bookmarks" pane for easy navigation in this volume. 0 virtex?-ii platform fpgas: complete data sheet ds031 august 1, 2003 00 product specification r
? 2001-2002 xilinx, inc. all rights reserved. all xilinx trademark s, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds031-1 (v2.0) august 1, 2003 www.xilinx.com module 1 of 4 product specification 1-800-255-7778 1 summary of virtex-ii features industry first platform fpga solution ip-immersion architecture - densities from 40k to 8m system gates - 420 mhz internal clock speed (advance data) - 840+ mb/s i/o (advance data) selectram? memory hierarchy - 3 mb of dual-port ram in 18 kbit block selectram resources - up to 1.5 mb of distributed selectram resources high-performance interfaces to external memory - dram interfaces sdr / ddr sdram network fcram reduced latency dram - sram interfaces sdr / ddr sram qdr? sram - cam interfaces arithmetic functions - dedicated 18-bit x 18 -bit multiplier blocks - fast look-ahead carry logic chains flexible logic resources - up to 93,184 internal registers / latches with clock enable - up to 93,184 look-up tables (luts) or cascadable 16-bit shift registers - wide multiplexers and wide-input function support - horizontal cascade chain and sum-of-products support - internal 3-state bussing high-performance clock management circuitry - up to 12 dcm (digital clock manager) modules precise clock de-skew flexible frequency synthesis high-resolution phase shifting - 16 global clock multiplexer buffers active interconnect technology - fourth generation segmented routing structure - predictable, fast routing delay, independent of fanout selectio?-ultra technology - up to 1,108 user i/os - 19 single-ended and six differential standards - programmable sink current (2 ma to 24 ma) per i/o - digitally controlled imp edance (dci) i/o: on-chip termination resistors for single-ended i/o standards - pci-x compatible (133 mhz and 66 mhz) at 3.3v - pci compliant (66 mhz and 33 mhz) at 3.3v - cardbus compliant (33 mhz) at 3.3v - differential signaling 840 mb/s low-voltage differential signaling i/o (lvds) with current mode drivers bus lvds i/o lightning data transport (ldt) i/o with current driver buffers low-voltage positive emitter-coupled logic (lvpecl) i/o built-in ddr input and output registers - proprietary high-performance selectlink technology high-bandwidth data path double data rate (ddr) link web-based hdl generation methodology supported by xilinx foundation? and alliance series? development systems - integrated vhdl and verilog design flows - compilation of 10m system gates designs - internet team design (itd) tool sram-based in-system configuration - fast selectmap configuration - triple data encryption standard (des) security option (bitstream encryption) - ieee 1532 support - partial reconfiguration - unlimited reprogrammability - readback capability 0.15 m 8-layer metal process with 0.12 m high-speed transistors 1.5v (v ccint ) core power supply, dedicated 3.3v v ccaux auxiliary and v cco i/o power supplies ieee 1149.1 compatible boundary-scan logic support flip-chip and wire-bond ball grid array (bga) packages in three standard fine pitches (0.80 mm, 1.00 mm, and 1.27 mm) 100% factory tested 0 7 virtex?-ii platform fpgas: introduction and overview ds031-1 (v2.0) august 1, 2003 00 product specification r
virtex?-ii platform fpgas: introduction and overview r ds031-1 (v2.0) august 1, 2003 www.xilinx.com module 1 of 4 product specification 1-800-255-7778 2 general description the virtex-ii family is a platform fpga developed for high performance from low-density to high-density designs that are based on ip cores and customized modules. the family delivers complete solutions for telecommunication, wire- less, networking, video, and dsp applications, including pci, lvds, and ddr interfaces. the leading-edge 0.15 m / 0.12 m cmos 8-layer metal process and the virtex-ii architecture are optimized for high speed with low power consumption. combining a wide vari- ety of flexible features and a large range of densities up to 10 million system gates, the virtex-ii family enhances pro- grammable logic design capabilities and is a powerful alter- native to mask-programmed gates arrays. as shown in ta bl e 1 , the virtex-ii family comprises 11 members, ranging from 40k to 8m system gates. packaging offerings include ball grid array (bga) packages with 0.80 mm, 1.00 mm, and 1.27 mm pitches. in addition to tra- ditional wire-bond interconnects, flip-chip interconnect is used in some of the bga offerings. the use of flip-chip interconnect offers more i/os than is possible in wire-bond versions of the similar packages. flip-chip construction offers the combination of high pin count with high thermal capacity. ta b l e 2 shows the maximum number of user i/os available. the virtex-ii device/package combination table ( ta b l e 6 at the end of this section) details the maximum number of i/os for each device and package using wire-bond or flip-chip technology. ta bl e 1 : virtex-ii field-programmable gate array family members device system gates clb (1 clb = 4 slices = max 128 bits) multiplier blocks selectram blocks dcms max i/o pads (1) array row x col. slices maximum distributed ram kbits 18 kbit blocks max ram (kbits) xc2v40 40k 8 x 8 256 8 4 4 72 4 88 xc2v80 80k 16 x 8 512 16 8 8 144 4 120 xc2v250 250k 24 x 16 1,536 48 24 24 432 8 200 xc2v500 500k 32 x 24 3,072 96 32 32 576 8 264 xc2v1000 1m 40 x 32 5,120 160 40 40 720 8 432 xc2v1500 1.5m 48 x 40 7,680 240 48 48 864 8 528 XC2V2000 2m 56 x 48 10,752 336 56 56 1,008 8 624 xc2v3000 3m 64 x 56 14,336 448 96 96 1,728 12 720 xc2v4000 4m 80 x 72 23,040 720 120 120 2,160 12 912 xc2v6000 6m 96 x 88 33,792 1,056 144 144 2,592 12 1,104 xc2v8000 8m 112 x 104 46,592 1,456 168 168 3,024 12 1,108 notes: 1. see details in table 2, ?maximum number of user i/o pads? . ta b l e 2 : maximum number of user i/o pads device wire-bond flip-chip xc2v40 88 - xc2v80 120 - xc2v250 200 - xc2v500 264 - xc2v1000 328 432 xc2v1500 392 528 XC2V2000 - 624 xc2v3000 516 720 xc2v4000 - 912 xc2v6000 - 1,104 xc2v8000 - 1,108
virtex?-ii platform fpgas: introduction and overview r ds031-1 (v2.0) august 1, 2003 www.xilinx.com module 1 of 4 product specification 1-800-255-7778 3 architecture virtex-ii array overview virtex-ii devices are user-programmable gate arrays with various configurable elements. the virtex-ii architecture is optimized for high-density and high-performance logic designs. as shown in figure 1 , the programmable device is comprised of input/output blocks (iobs) and internal configurable logic blocks (clbs). programmable i/o blocks provide the interface between package pins and the internal configurable logic. most popular and leading-edge i/o standards are supported by the programmable iobs. the internal configurable logic includes four major elements organized in a regular array. configurable logic blocks (clbs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. bufts (3-state buffers) associated with each clb element drive dedicated segmentable horizontal routing resources. block selectram memory modules provide large 18 kbit storage elements of dual-port ram. multiplier blocks are 18-bit x 18-bit dedicated multipliers. dcm (digital clock manager) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, coarse- and fine-grained clock phase shifting. a new generation of programmable routing resources called active interconnect technology interconnects all of these elements. the general routing matrix (grm) is an array of routing switches. each programmable element is tied to a switch matrix, allowing multip le connections to the general routing matrix. the overall programmable interconnection is hierarchical and designed to support high-speed designs. all programmable elements, including the routing resources, are controlled by values stored in static memory cells. these values are loaded in the memory cells during configuration and can be reloaded to change the functions of the programmable elements. virtex-ii features this section briefly describes virtex-ii features. input/output blocks (iobs) iobs are programmable and can be categorized as follows: input block with an optional single-data-rate or double-data-rate (ddr) register output block with an optional single-data-rate or ddr register, and an optional 3-state buffer, to be driven directly or through a single or ddr register bidirectional block (any combination of input and output configurations) these registers are either edge-triggered d-type flip-flops or level-sensitive latches. iobs support the following single-ended i/o standards: lvttl, lvcmos (3.3v, 2.5v, 1.8v, and 1.5v) pci-x compatible (133 mhz and 66 mhz) at 3.3v pci compliant (66 mhz and 33 mhz) at 3.3v cardbus compliant (33 mhz) at 3.3v figure 1: virtex-ii architecture overview global clock mux dcm dcm iob clb programmable i/os block selectram multiplier configurable logic ds031_28_100900
virtex?-ii platform fpgas: introduction and overview r ds031-1 (v2.0) august 1, 2003 www.xilinx.com module 1 of 4 product specification 1-800-255-7778 4 gtl and gtlp hstl (class i, ii, iii, and iv) sstl (3.3v and 2.5v, class i and ii) agp-2x the digitally controlled impedance (dci) i/o feature auto- matically provides on-chip termination for each i/o element. the iob elements also support the following differential sig- naling i/o standards: lvds b lv d s ( b u s lv d s ) ulvds ldt lvpecl two adjacent pads are used for each differential pair. two or four iob blocks connect to one switch matrix to access the routing resources. configurable logic blocks (clbs) clb resources include four slices and two 3-state buffers. each slice is equivalent and contains: two function generators (f & g) two storage elements arithmetic logic gates large multiplexers wide function capability fast carry look-ahead chain horizontal cascade chain (or gate) the function generators f & g are configurable as 4-input look-up tables (luts), as 16-bit shift registers, or as 16-bit distributed selectram memory. in addition, the two storage elements are either edge-trig- gered d-type flip-flops or level-sensitive latches. each clb has internal fast interconnect and connects to a switch matrix to access general routing resources. block selectram memory the block selectram memory resources are 18 kb of dual-port ram, programmable from 16k x 1 bit to 512 x 36 bits, in various depth and width configurations. each port is totally synchronous and independent, offering three "read-during-write" modes. block selectram memory is cascadable to implement large embedded storage blocks. supported memory configurations for dual-port and sin- gle-port modes are shown in ta b l e 3 . a multiplier block is associated with each selectram mem- ory block. the multiplier block is a dedicated 18 x 18-bit multiplier and is optimized for operations based on the block selectram content on one port. the 18 x 18 multiplier can be used independently of the block selectram resource. read/multiply/accumulate operations and dsp filter struc- tures are extremely efficient. both the selectram memory and the multiplier resource are connected to four switch matrices to access the general routing resources. global clocking the dcm and global clock multiplexer buffers provide a complete solution for designing high-speed clocking schemes. up to 12 dcm blocks are available. to generate de-skewed internal or external clocks, each dcm can be used to elimi- nate clock distribution delay. the dcm also provides 90-, 180-, and 270-degree phase-shifted versions of its output clocks. fine-grained phase shifting offers high-resolution phase adjustments in increments of 1/256 of the clock period. very flexible frequency synthesis provides a clock output frequency equal to any m/d ratio of the input clock frequency, where m and d are two integers. for the exact timing parameters, see virtex-ii electrical characteris- tics . virtex-ii devices have 16 global clock mux buffers, with up to eight clock nets per quadrant. each global clock mux buffer can select one of the two clock inputs and switch glitch-free from one clock to the other. each dcm block is able to drive up to four of the 16 global clock mux buffers. routing resources the iob, clb, block selectram, multiplier, and dcm ele- ments all use the same interconnect scheme and the same access to the global routing matrix. timing models are shared, greatly improving the predictability of the perfor- mance of high-speed designs. there are a total of 16 global clock lines, with eight available per quadrant. in addition, 24 vertical and horizontal long lines per row or column as well as massive secondary and local routing resources provide fast interconnect. virtex-ii buffered interconnects are relatively unaffected by net fanout and the interconnect layout is designed to minimize crosstalk. horizontal and vertical routing resources for each row or column include: 24 long lines 120 hex lines 40 double lines 16 direct connect lines (total in all four directions) ta bl e 3 : dual-port and single-port configurations 16k x 1 bit 2k x 9 bits 8k x 2 bits 1k x 18 bits 4k x 4 bits 512 x 36 bits
virtex?-ii platform fpgas: introduction and overview r ds031-1 (v2.0) august 1, 2003 www.xilinx.com module 1 of 4 product specification 1-800-255-7778 5 boundary scan boundary scan instructions a nd associated data registers support a standard methodology for accessing and config- uring virtex-ii devices that complies with ieee standards 1149.1 ? 1993 and 1532. a system mode and a test mode are implemented. in system mode, a virtex-ii device per- forms its intended mission even while executing non-test boundary-scan instructions. in test mode, boundary-scan test instructions control the i/o pins for testing purposes. the virtex-ii test access port (tap) supports bypass, preload, sample, idcode , and usercode non-test instructions. the extest, intest, and highz test instruc- tions are also supported. configuration virtex-ii devices are configured by loading data into internal configuration memory, using the following five modes: slave-serial mode master-serial mode slave selectmap mode master selectmap mode boundary-scan mode (ieee 1532) a data encryption standard (des) decryptor is available on-chip to secure the bitstreams. one or two triple-des key sets can be used to optionally encrypt the configuration information. readback and integrated logic analyzer configuration data stored in virtex-ii configuration memory can be read back for verification. along with the configura- tion data, the contents of all flip-flops/latches, distributed selectram, and block select ram memory resources can be read back. this capability is useful for real-time debug- ging. the integrated logic analyzer (ila) core and software pro- vides a complete solution for accessing and verifying virtex-ii devices. virtex-ii device/package combinations and maximum i/o wire-bond and flip-chip packages are available. ta bl e 4 and ta b l e 5 show the maximum possible number of user i/os in wire-bond and flip-chip packages, respectively. ta b l e 6 shows the number of available user i/os for all device/pack- age combinations. cs denotes wire-bond chip-scale ball grid array (bga) (0.80 mm pitch). fg denotes wire-bond fine-pitch bga (1.00 mm pitch). ff denotes flip-chip fine-pitch bga (1.00 mm pitch). bg denotes standard bga (1.27 mm pitch). bf denotes flip-chip bga (1.27 mm pitch). the number of i/os per package include all user i/os except the 15 control pins (cclk, done, m0, m1, m2, prog_b, pwrdwn_b, tck, tdi, tdo, tms, hswap_en, dxn, dxp, and rsvd) and vbatt. ta bl e 4 : wire-bond packages information package cs144 fg256 fg456 fg676 bg575 bg728 pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27 size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35 i/os 92 172 324 484 408 516 ta bl e 5 : flip-chip packages information package ff896 ff1152 ff1517 bf957 pitch (mm) 1.00 1.00 1.00 1.27 size (mm) 31 x 31 35 x 35 40 x 40 40 x 40 i/os 624 824 1,108 684
virtex?-ii platform fpgas: introduction and overview r ds031-1 (v2.0) august 1, 2003 www.xilinx.com module 1 of 4 product specification 1-800-255-7778 6 virtex-ii ordering information ta bl e 6 : virtex-ii device/package combinations and maximum number of available i/os (advance information) package available i/os xc2v 40 xc2v 80 xc2v 250 xc2v 500 xc2v 1000 xc2v 1500 xc2v 2000 xc2v 3000 xc2v 4000 xc2v 6000 xc2v 8000 cs144889292-------- fg25688120172172172------ fg456--200264324------ fg676 - - - - - 392 456 484 - - - ff896 - - - - 432 528 624 - - - - ff1152 - - - - - - - 720 824 824 824 ff1517--------9121,1041,108 bg575 - - - - 328 392 408 - - - - bg728-------516--- bf957 - - - - - - 624 684 684 684 - notes: 1. all devices in a particular package are pinout (footprint) co mpatible. in addition, the fg456 and fg676 packages are compatib le, as are the ff896 and ff1152 packages. figure 2: virtex-ii ordering information example: xc2v1000-5fg456c device type temperature range c = commercial (tj = 0?c to +85?c) i = industrial (tj = ?40?c to +100?c) number of pins package type speed grade (-4, -5, -6) ds031_35_033001
virtex?-ii platform fpgas: introduction and overview r ds031-1 (v2.0) august 1, 2003 www.xilinx.com module 1 of 4 product specification 1-800-255-7778 7 revision history this section records the change history for this module of the data sheet. virtex-ii data sheet the virtex-ii data sheet contains the following modules: virtex?-ii platform fpgas: introduction and overview (module 1) virtex?-ii platform fpgas: detailed description (module 2) virtex?-ii platform fpgas: dc and switching characteristics (module 3) virtex?-ii platform fpgas: pinout information (module 4) date version revision 11/07/00 1.0 early access draft. 12/06/00 1.1 initial release. 01/15/01 1.2 added values to the tables in the virtex-ii performance characteristics and virtex-ii switching characteristics sections. 01/25/01 1.3 the data sheet was divided into four modules (per the current style standard). 04/02/01 1.5 skipped v1.4 to sync up modules. reverted to traditional double-column format. 07/30/01 1.6 made minor changes to items listed under summary of virtex-ii features . 10/02/01 1.7 minor edits. 07/16/02 1.8 updated virtex-ii device/package combinations shown in ta bl e 6 . 09/26/02 1.9 updated ta b l e 2 and ta b l e 6 to reflect supported virtex-ii device/package combinations. 08/01/03 2.0 all virtex-ii devices and speed grades now production. see table 13, module 3.
? 2001-2002 xilinx, inc. all rights reserved. all xilinx trademark s, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 1 detailed description input/output blocks (iobs) virtex-ii i/o blocks (iobs) are provided in groups of two or four on the perimeter of each device. each iob can be used as input and/or output for single-ended i/os. two iobs can be used as a differential pair. a differential pair is always connected to the same swit ch matrix, as shown in figure 1 . iob blocks are designed for high performances i/os, sup- porting 19 single-ended standards, as well as differential signaling with lvds, ldt, bus lvds, and lvpecl. note: differential i/os must use the same clock. supported i/o standards virtex-ii iob blocks feature selecti/o-ultra inputs and out- puts that support a wide variety of i/o signaling standards. in addition to the internal supply voltage (vccint = 1.5v), output driver supply voltage (vcco) is dependent on the i/o standard (see ta b l e 1 ). an auxiliary supply voltage (vccaux = 3.3 v) is required, regardless of the i/o stan- dard used. for exact supply voltage absolute maximum rat- ings, see dc input and output levels in module 3. 0 40 virtex?-ii platform fpgas: detailed description ds031-2 (v3.0) august 1, 2003 00 product specification r figure 1: virtex-ii input/output tile iob pad4 iob pad3 differential pair iob pad2 iob pad1 differential pair switch matrix ds031_30_101600 ta b l e 1 : supported single-ended i/o standards i/o standard output v cco input v cco input v ref board termination voltage (v tt ) lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lvcmos15 1.5 1.5 n/a n/a pci33_3 3.3 3.3 n/a n/a pci66_3 3.3 3.3 n/a n/a pci-x 3.3 3.3 n/a n/a gtl note (1) note (1) 0.8 1.2 gtlp note (1) note (1) 1.0 1.5 hstl_i 1.5 n/a 0.75 0.75 hstl_ii 1.5 n/a 0.75 0.75 hstl_iii 1.5 n/a 0.9 1.5 hstl_iv 1.5 n/a 0.9 1.5 hstl_i 1.8 n/a 0.9 0.9 hstl_ii 1.8 n/a 0.9 0.9 hstl_iii 1.8 n/a 1.1 1.8 hstl_iv 1.8 n/a 1.1 1.8 sstl2_i 2.5 n/a 1.25 1.25 sstl2_ii 2.5 n/a 1.25 1.25 sstl3_i 3.3 n/a 1.5 1.5 sstl3_ii 3.3 n/a 1.5 1.5 agp-2x/agp 3.3 n/a 1.32 n/a notes: 1. v cco of gtl or gtlp should not be lower than the termination voltage or the voltage seen at the i/o pad.
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 2 all of the user iobs have fixed-clamp diodes to vcco and to ground. as outputs, these iobs are not compatible or compliant with 5v i/o standards. as inputs, these iobs are not normally 5v tolerant, but can be used with 5v i/o stan- dards when external current-limiting resistors are used. for more details, see the ?5v tolerant i/os? tech topic at www.xilinx.com . ta bl e 3 lists supported i/o standards with digitally con- trolled impedance. see digitally controlled impedance (dci) , page 8 . logic resources iob blocks include six storage elements, as shown in figure 2 . each storage element can be configured either as an edge-triggered d-type flip-flop or as a level-sensitive latch. on the input, output, and 3-state path, one or two ddr reg- isters can be used. double data rate is directly accomplished by the two regis- ters on each path, clocked by the rising edges (or falling edges) from two different clock nets. the two clock signals are generated by the dcm and must be 180 degrees out of phase, as shown in figure 3 . there are two input, output, and 3-state data signals, each being alternately clocked out. ta bl e 2 : supported differential signal i/o standards i/o standard output v cco input v cco input v ref output v od lvpecl_33 3.3 n/a n/a 490 mv to 1.22v ldt_25 2.5 n/a n/a 0.430 - 0.670 lvds_33 3.3 n/a n/a 0.250 - 0.400 lvds_25 2.5 n/a n/a 0.250 - 0.400 lvdsext_33 3.3 n/a n/a 0.330 - 0.700 lvdsext_25 2.5 n/a n/a 0.330 - 0.700 blvds_25 2.5 n/a n/a 0.250 - 0.450 ulvds_25 2.5 n/a n/a 0.430 - 0.670 ta b l e 3 : supported dci i/o standards i/o standard output v cco input v cco input v ref termination type lvdci_33 (1) 3.3 3.3 n/a series lvdci_dv2_33 (1) 3.3 3.3 n/a series lvdci_25 (1) 2.5 2.5 n/a series lvdci_dv2_25 (1) 2.5 2.5 n/a series lvdci_18 (1) 1.8 1.8 n/a series lvdci_dv2_18 (1) 1.8 1.8 n/a series lvdci_15 (1) 1.5 1.5 n/a series lvdci_dv2_15 (1) 1.5 1.5 n/a series gtl_dci 1.2 1.2 0.8 single gtlp_dci 1.5 1.5 1.0 single hstl_i_dci 1.5 1.5 0.75 split hstl_ii_dci 1.5 1.5 0.75 split hstl_iii_dci 1.5 1.5 0.9 single hstl_iv_dci 1.5 1.5 0.9 single hstl_i_dci_18 1.8 1.8 0.9 split hstl_ii_dci_18 1.8 1.8 0.9 split hstl_iii_dci_18 1.8 1.8 1.08 single hstl_iv_dci_18 1.8 1.8 1.08 single sstl2_i_dci (2) 2.5 2.5 1.25 split sstl2_ii_dci (2) 2.5 2.5 1.25 split sstl3_i_dci (2) 3.3 3.3 1.5 split sstl3_ii_dci (2) 3.3 3.3 1.5 split notes: 1. lvdci_xx and lvdci_dv2_xx are lvcmos controlled impedance buffers, matching the reference resistors or half of the reference resistors. 2. these are sstl compatible.
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 3 the ddr mechanism shown in figure 3 can be used to mir- ror a copy of the clock on the output. this is useful for prop- agating a clock along the data that has an identical delay. it is also useful for multiple clock generation, where there is a unique clock driver for every clock load. virtex-ii devices can produce many copies of a clock with very little skew. each group of two registers has a clock enable signal (ice for the input registers, oce for the output registers, and tce for the 3-state registers). the clock enable signals are active high by default. if left unconnected, the clock enable for that storage element defaults to the active state. each iob block has common sy nchronous or asynchronous set and reset (sr and rev signals). sr forces the storage element into the state specified by the srhigh or srlow attribute. srhigh forces a logic ?1?. srlow forces a logic ?0?. w hen sr is used, a second input (rev) forces the storage element into the opposite state. the reset condition predominates over the set condition. the ini- tial state after configuration or global initialization state is defined by a separate init0 and init1 attribute. by default, the srlow attribute forces init0, and the srhigh attribute forces init1. for each storage element, the srhigh, srlow, init0, and init1 attributes are independent. synchronous or asynchronous set / reset is consistent in an iob block. all the control signals have independent polarity. any inverter placed on a control input is automatically absorbed. each register or latch (independent of all other registers or latches) (see figure 4 ) can be configured as follows: no set or reset synchronous set synchronous reset synchronous set and reset asynchronous set (preset) asynchronous reset (clear) asynchronous set and reset (preset and clear) figure 2: virtex-ii iob block reg ock1 reg ock2 reg ick1 reg ick2 ddr mux input pa d 3-state reg ock1 reg ock2 ddr mux output iob ds031_29_100900 figure 3: double data rate registers d1 clk1 ddr mux q1 fddr d2 clk2 (50/50 duty cycle clock) clock qq q2 d1 clk1 ddr mux dcm q1 fddr d2 clk2 q2 180 0 ds031_26_100900
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 4 the synchronous reset overrides a set, and an asynchro- nous clear overrides a preset. input/output individual options each device pad has optional pull-up and pull-down in all selecti/o-ultra configurations. each device pad has optional weak-keeper in lvttl, lvcmos, and pci selecti/o-ultra configurat ions, as illustrated in figure 5 . values of the optional pull-up and pull-down resistors are in the range 10 - 60 k ? , which is the specification for v cco when operating at 3.3v (from 3.0 to 3.6v only). the clamp diode is always present, even when power is not. figure 4: register / latch configuration in an iob block ff latch sr rev d1 q1 ce ck1 ff latch sr rev d2 ff1 ff2 ddr mux q2 ce ck2 rev sr (o/t) clk1 (oq or tq) (o/t) ce (o/t) 1 (o/t) clk2 (o/t) 2 attribute init1 init0 srhigh srlow attribute init1 init0 srhigh srlow reset type sync async ds031_25_110300 shared by all registers figure 5: lvttl, lvcmos or pci selecti/o-ultra standards v cco v cco v cco weak keeper program delay obuf ibuf program current clamp diode 10-60k ? 10-60k ? pa d v ccaux = 3.3v ds031_23_011601 v ccint = 1.5v
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 5 the optional weak-keeper circuit is connected to each user i/o pad. when selected, the circuit monitors the voltage on the pad and weakly drives the pin high or low. if the pin is connected to a multiple-source signal, the weak-keeper holds the signal in its last state if all drivers are disabled. maintaining a valid logic level in this way eliminates bus chatter. an enabled pull-up or pull-down overrides the weak-keeper circuit. lvttl sinks and sources current up to 24 ma. the current is programmable for lvttl and lvcmos selecti/o-ultra standards (see ta b l e 4 ). drive-strength and slew-rate con- trols for each output driver, minimize bus transients. for lvdci and lvdci_dv2 standards, drive strength and slew-rate controls are not available. figure 6 shows the sstl2, sstl3, and hstl configura- tions. hstl can sink current up to 48 ma. (hstl iv) all pads are protected against damage from electrostatic discharge (esd) and from over-voltage transients. virtex-ii uses two memory cells to control the configuration of an i/o as an input. this is to reduce the probability of an i/o con- figured as an input from flipping to an output when sub- jected to a single event upset (seu) in space applications. prior to configuration, all out puts not involved in configura- tion are forced into their high-impedance state. the pull-down resistors and the weak-keeper circuits are inac- tive. the dedicated pin hswap_en controls the pull-up resistors prior to configuration. by default, hswap_en is set high, which disables the pull-up resistors on user i/o pins. when hswap_en is set low, the pull-up resistors are activated on user i/o pins. all virtex-ii iobs support i eee 1149.1 compatible boundary scan testing. input path the virtex-ii iob input path routes input signals directly to internal logic and / or through an optional input flip-flop or latch, or through t he ddr input registers. an optional delay element at the d-input of the storage element eliminates pad-to-pad hold time. the delay is matched to the internal clock-distribution delay of the virtex-ii device, and when used, assures that the pad-to-pad hold time is zero. each input buffer can be configured to conform to any of the low-voltage signaling standards supported. in some of these standards the input buff er utilizes a user-supplied threshold voltage, v ref . the need to supply v ref imposes constraints on which standards can be used in the same bank. see i/o banking description. output path the output path includes a 3-state output buffer that drives the output signal onto the pad. the output and / or the 3-state signal can be routed to the buffer directly from the internal logic or through an output / 3-state flip-flop or latch, or through the ddr output / 3-state registers. each output driver can be individually programmed for a wide range of low-voltage signaling standards. in most sig- naling standards, the output high voltage depends on an externally supplied v cco voltage. the need to supply v cco imposes constraints on which standards can be used in the same bank. see i/o banking description. i/o banking some of the i/o standards described above require v cco and v ref voltages. these voltages are externally supplied and connected to device pins that serve groups of iob blocks, called banks. consequently, restrictions exist about which i/o standards can be combined within a given bank. ta bl e 4 : lvttl and lvcmos programmable currents (sink and source) selecti/o-ultra programmable current (worst-case guaranteed minimum) lvttl 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma lvcmos33 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma lvcmos25 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma lvcmos18 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma n/a lvcmos15 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma n/a figure 6: sstl or hstl selecti/o-ultra standards v cco obuf v ref clamp diode pa d v ccaux = 3.3v v ccint = 1.5v ds031_24_100900
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 6 eight i/o banks result from dividing each edge of the fpga into two banks, as shown in figure 7 and figure 8 . each bank has multiple v cco pins, all of which must be con- nected to the same voltage. this voltage is determined by the output standards in use. some input standards require a user-supplied threshold voltage (v ref ), and certain user-i/o pins are automatically configured as v ref inputs. approximately one in six of the i/o pins in the bank assume this role. v ref pins within a bank are interconnected internally, and consequently only one v ref voltage can be used within each bank. however, for correct operation, all v ref pins in the bank must be connected to the external reference volt- age source. the v cco and the v ref pins for each bank appear in the device pinout tables. within a given package, the number of v ref and v cco pins can vary depending on the size of device. in larger devices, more i/o pins convert to v ref pins. since these are always a superset of the v ref pins used for smaller devices, it is possible to design a pcb that permits migration to a larger device if necessary. all v ref pins for the largest device anticipated must be con- nected to the v ref voltage and not used for i/o. in smaller devices, some v cco pins used in larger devices do not con- nect within the package. these unconnected pins can be left unconnected externally, or, if necessary, they can be connected to v cco to permit migration to a larger device. rules for combining i/o standards in the same bank the following rules must be obeyed to combine different input, output, and bi-directional standards in the same bank: 1. combining output standards only. output standards with the same output v cco requirement can be combined in the same bank. compatible example: sstl2_i and lvds_25_dci outputs incompatible example: sstl2_i (output v cco = 2.5v) and lvcmos33 (output v cco = 3.3v) outputs 2. combining input standards only. input standards with the same input v cco and input v ref requirements can be combined in the same bank. compatible example: lvcmos15 and hstl_iv inputs incompatible example: lvcmos15 (input v cco = 1.5v) and lvcmos18 (input v cco = 1.8v) inputs incompatible example: hstl_i_dci_18 (v ref = 0.9v) and hstl_iv_dci_18 (v ref = 1.1v) inputs 3. combining input standards and output standards. input standards and output standards with the same input v cco and output v cco requirement can be combined in the same bank. compatible example: lvds_25 output and hstl_i input incompatible example: lvds_25 output (output v cco = 2.5v) and hstl_i_dci_18 input (input v cco = 1.8v) 4. combining bi-directional standards with input or output standards. when combining bi-directional i/o with other standards, make sure the bi-directional standard can meet rules 1 through 3 above. 5. additional rules for combining dci i/o standards. a. no more than one single termination type (input or output) is allowed in the same bank. incompatible example: hstl_iv_dci input and hstl_iii_dci input b. no more than one split termination type (input or output) is allowed in the same bank. incompatible example: hstl_i_dci input and hstl_ii_dci input the implementation tools will enforce these design rules. figure 7: virtex-ii i/o banks: top view for wire-bond packages (cs, fg, & bg) figure 8: virtex-ii i/o banks: top view for flip-chip packages (ff & bf) ug002_c2_014_112900 bank 0 bank 1 bank 5 bank 4 bank 7 bank 6 bank 2 bank 3 ds031_66_112900 bank 1 bank 0 bank 4 bank 5 bank 2 bank 3 bank 7 bank 6
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 7 ta bl e 5 summarizes all standards and voltage supplies. table 5: summary of voltage supply requirements for all input and output standards i/o standard v cco v ref termination type output input input output input lvds_33 3.3 n/r n/r (1) n/r n/r lvdsext_33 n/r n/r n/r lvpecl_33 n/r n/r n/r sstl3_i 1.5 n/r n/r sstl3_ii 1.5 n/r n/r agp 1.32 n/r n/r lvt t l 3.3 n/r n/r n/r lvc m o s 3 3 n/r n/r n/r lvdci_33 n/r series n/r lvdci_dv2_33 n/r series n/r pci33_3 n/r n/r n/r pci66_3 n/r n/r n/r pcix n/r n/r n/r lvds_33_dci n/r n/r split lvdsext_33_dci n/r n/r split sstl3_i_dci 1.5 n/r split sstl3_ii_dci 1.5 split split lvds_25 2.5 n/r n/r n/r n/r lvdsext_25 n/r n/r n/r ldt_25 n/r n/r n/r ulvds_25 n/r n/r n/r blvds_25 n/r n/r n/r sstl2_i 1.25 n/r n/r sstl2_ii 1.25 n/r n/r lvc m o s 2 5 2.5 n/r n/r n/r lvdci_25 n/r series n/r lvdci_dv2_25 n/r series n/r lvds_25_dci n/r n/r split lvdsext_25_dci n/r n/r split sstl2_i_dci 1.25 n/r split sstl2_ii_dci 1.25 split split hstl_iii_18 1.8 n/r 1.1 n/r n/r hstl_iv_18 1.1 n/r n/r hstl_i_18 0.9 n/r n/r hstl_ii_18 0.9 n/r n/r sstl18_i 0.9 n/r n/r sstl18_ii 0.9 n/r n/r lv c m o s1 8 1.8 n/r n/r n/r lvdci_18 n/r series n/r lvdci_dv2_18 n/r series n/r hstl_iii_dci_18 1.1 n/r single hstl_iv_dci_18 1.1 single single hstl_i_dci_18 0.9 n/r split hstl_ii_dci_18 0.9 split split sstl18_i_dci 0.9 n/r split sstl18_ii_dci 0.9 split split hstl_iii 1.5 n/r 0.9 n/r n/r hstl_iv 0.9 n/r n/r hstl_i 0.75 n/r n/r hstl_ii 0.75 n/r n/r lv c m o s1 5 1.5 n/r n/r n/r lvdci_15 n/r series n/r lvdci_dv2_15 n/r series n/r gtlp_dci 1 single single hstl_iii_dci 0.9 n/r single hstl_iv_dci 0.9 single single hstl_i_dci 0.75 n/r split hstl_ii_dci 0.75 split split gtl_dci 1.2 1.2 0.8 single single gtlp n/r n/r 1n/rn/r gtl 0.8 n/r n/r notes: 1. n/r = no requirement. ta b l e 5 : summary of voltage supply requirements for all input and output standards (continued) i/o standard v cco v ref termination type output input input output input
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 8 digitally controlled impedance (dci) today?s chip output signals with fast edge rates require ter- mination to prevent reflections and maintain signal integrity. high pin count packages (especially ball grid arrays) can not accommodate external termination resistors. virtex-ii xcite dci provides controlled impedance drivers and on-chip termination for single-ended and differential i/os. this eliminates the need for external resistors, and improves signal integrity. the dci feature can be used on any iob by selecting one of the dci i/o standards. when applied to inputs, dci pr ovides input parallel termina- tion. when applied to outputs, dci provides controlled impedance drivers (series termination) or output parallel termination. dci operates independently on each i/o bank. when a dci i/o standard is used in a particular i/o bank, external refer- ence resistors must be connected to two dual-function pins on the bank. these resistors, voltage reference of n transis- tor (vrn) and the voltage reference of p transistor (vrp) are shown in figure 9 . when used with a terminated i/o standard, the value of resistors are specified by the standard (typically 50 ? ). when used with a controlled impedance driver, the resistors set the output impedance of the driver within the specified range (25 ? to 100 ?) . for all series and parallel termina- tions listed in ta b l e 6 and ta b l e 7 , the reference resistors must have the same value for any given bank. one percent resistors are recommended. the dci system adjusts the i/o impedance to match the two external reference resistors, or half of the reference resis- tors, and compensates for impedance changes due to volt- age and/or temperature fluctuations. the adjustment is done by turning parallel transistors in the iob on or off. controlled impedance drivers (series termination) dci can be used to provide a buffer with a controlled output impedance. it is desirable for this output impedance to match the transmission line impedance (z). virtex-ii input buffers also support lvdci and lvdci_dv2 i/o standards. controlled impedance drivers (parallel termination) dci also provides on-chip termination for sstl3, sstl2, hstl (class i, ii, iii, or iv), and gtl/gtlp receivers or transmitters on bi directional lines. ta b l e 7 lists the on-chip parallel terminations available in vir- tex-ii devices. v cco must be set according to ta b l e 3 . note that there is a v cco requirement for gtl_dci and gtlp_dci, due to the on-chip termination resistor. figure 9: dci in a virtex-ii bank ds031_50_101200 v cco gnd dci dci dci dci vrn vrp 1 bank r ref (1%) r ref (1%) figure 10: internal series termination ta b l e 6 : selecti/o-ultra controlled impedance buffers v cco dci dci half impedance 3.3 v lvdci_33 lvdci_dv2_33 2.5 v lvdci_25 lvdci_dv2_25 1.8 v lvdci_18 lvdci_dv2_18 1.5 v lvdci_15 lvdci_dv2_15 ta b l e 7 : selecti/o-ultra buffers with on-chip parallel termination i/o standard external termination on-chip termination sstl3 class i sstl3_i sstl3_i_dci (1) sstl3 class ii sstl3_ii sstl3_ii_dci (1) sstl2 class i sstl2_i sstl2_i_dci (1) sstl2 class ii sstl2_ii sstl2_ii_dci (1) hstl class i hstl_i hstl_i_dci hstl class ii hstl_ii hstl_ii_dci hstl class iii hstl_iii hstl_iii_dci hstl class iv hstl_iv hstl_iv_dci gtl gtl gtl_dci gtlp gtlp gtlp_dci notes: 1. sstl compatible z iob z virtex-ii dci ds031_51_110600 v cco = 3.3 v, 2.5 v, 1.8 v or 1.5 v
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 9 figure 11 provides examples illustrating the use of the hstl_i _dci, hstl_ii_dci, hstl_iii _dci, and hstl_iv_dci i/o standards. for a complete list, see the virtex-ii user guide. figure 11: hstl dci usage examples virtex-ii dci rr v cco v cco rr v cco v cco r v cco r v cco virtex-ii dci virtex-ii dci r v cco r v cco virtex-ii dci rr v cco /2 v cco /2 2r virtex-ii dci 2r r v cco v cco /2 virtex-ii dci 2r r v cco /2 2r v cco 2r virtex-ii dci 2r v cco virtex-ii dci 2r 2r v cco ds031_65a_100201 conventional dci transmit conventional receive conventional transmit dci receive dci transmit dci receive bidirectional reference resistor recommended z 0 (1 ) vrn = vrp = r = z 0 50 ? vrn = vrp = r = z 0 50 ? vrn = vrp = r = z 0 50 ? vrn = vrp = r = z 0 50 ? hstl_i hstl_ii hstl_iii hstl_iv n/a n/a virtex-ii dci r v cco r v cco r v cco virtex-ii dci r v cco virtex-ii dci z 0 r v cco /2 virtex-ii dci r v cco /2 virtex-ii dci 2r 2r v cco virtex-ii dci virtex-ii dci 2r 2r v cco z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 virtex-ii dci virtex-ii dci z 0 virtex-ii dci 2r 2r v cco 2r 2r v cco virtex-ii dci z 0 virtex-ii dci r v cco r v cco note: 1. z 0 is the recommended pcb trace impedance.
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 10 figure 12 provides examples illustrating the use of the sstl2 _i_dci, sstl2_ii_dci , sstl3_i_dci, and sstl3_ii_dci i/o standards. for a complete list, see the virtex-ii user guide. figure 12: sstl dci usage examples ds031_65b_112502 conventional dci transmit conventional receive conventional transmit dci receive dci transmit dci receive bidirectional reference resistor recommended z 0 (2 ) vrn = vrp = r = z 0 50 ? vrn = vrp = r = z 0 50 ? vrn = vrp = r = z 0 50 ? vrn = vrp = r = z 0 50 ? sstl2_i sstl2_ii sstl3_i sstl3_ii n/a n/a virtex-ii dci z 0 r v cco /2 z 0 r/2 rr v cco /2 v cco /2 z 0 r/2 rr v cco /2 v cco /2 z 0 r/2 r v cco /2 z 0 r/2 r v cco/2 z 0 r/2 virtex-ii dci 2r 2r v cco r v cco/2 z 0 r/2 virtex-ii dci 2r 2r v cco z 0 r/2 virtex-ii dci 2r 2r v cco z 0 r/2 virtex-ii dci 2r 2r v cco virtex-ii dci r v cco v cco /2 2r virtex-ii dci r v cco v cco /2 2r virtex-ii dci r v cco /2 z 0 z 0 z 0 virtex-ii dci r v cco /2 z 0 2r 2r 2r virtex-ii dci 2r v cco virtex-ii dci 2r 2r v cco z 0 virtex-ii dci virtex-ii dci 2r 2r v cco z 0 2r virtex-ii dci 2r v cco virtex-ii dci 2r 2r v cco z 0 virtex-ii dci 2r 2r v cco virtex-ii dci z 0 virtex-ii dci 2r 2r v cco 2r 2r v cco virtex-ii dci z 0 virtex-ii dci 2r 2r v cco 2r 2r v cco 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) 25 ? ( 1) notes: 1. the sstl-compatible 25 ? series resistor is accounted for in the dci buffer, and it is not dci controlled. 2. z 0 is the recommended pcb trace impedance.
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 11 figure 13 provides examples illustra ting the use of the lvds_dci and lvdsext _dci i/o standards. for a complete list, see the virtex-ii user guide. figure 13: lvds dci usage examples ds031_65c_022103 conventional conventional transmit dci receive reference resistor recommended z 0 vrn = vrp = r = z 0 50 ? lvds_dci and lvdsext_dci receiver virtex-ii lvds dci z 0 2r 2r v cco z 0 2r 2r v cco virtex-ii lvds z 0 2r z 0 note: only lvds25_dci is supported (v cco = 2.5v only)
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 12 configurable logic blocks (clbs) the virtex-ii configurable logic blocks (clb) are organized in an array and are used to build combinatorial and synchro- nous logic designs. each clb element is tied to a switch matrix to access the general routing matrix, as shown in figure 14 . a clb element comprises 4 similar slices, with fast local feedback within the clb. the four slices are split in two columns of two slices with two independent carry logic chains and one common shift chain. slice description each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and two storage elements. as shown in figure 15 , each 4-input function generator is programmable as a 4-input lut, 16 bits of distributed selectram memory, or a 16-bit vari- able-tap shift register element. the output from the function generator in each slice drives both the slice output and the d input of the storage element. figure 16 shows a more detailed view of a single slice. configurations look-up table virtex-ii function generators are implemented as 4-input look-up tables (luts). four independent inputs are pro- vided to each of the two function generators in a slice (f and g). these function generators are each capable of imple- menting any arbitrarily defined boolean function of four inputs. the propagation delay is therefore independent of the function implemented. signals from the function gener- ators can exit the slice (x or y output), can input the xor dedicated gate (see arithmetic logic), or input the carry-logic multiplexer (see fast look-ahead carry logic), or feed the d input of the storage element, or go to the muxf5 (not shown in figure 16 ). in addition to the basic luts, the virtex-ii slice contains logic (muxf5 and muxfx multiplexers) that combines function generators to provide any function of five, six, seven, or eight inputs. the muxfx are either muxf6, muxf7 or muxf8 according to the slice considered in the clb. selected functions up to nine inputs (muxf5 multi- plexer) can be implemented in one slice. the muxfx can also be a muxf6, muxf7, or muxf8 multiplexers to map any functions of six, seven, or eight inputs and selected wide logic functions. register/latch the storage elements in a virtex-ii slice can be configured either as edge-triggered d-type flip-flops or as level-sensi- tive latches. the d input can be directly driven by the x or y output via the dx or dy input, or by the slice inputs bypass- ing the function generators via the bx or by input. the clock enable signal (ce) is active high by default. if left uncon- nected, the clock enable for that storage element defaults to the active state. in addition to clock (ck) and clock enable (ce) signals, each slice has set and reset signals (sr and by slice inputs). sr forces the storage element into the state speci- fied by the attribute srhigh or srlow. srhigh forces a logic ?1? when sr is asserted. srlow forces a logic ?0?. when sr is used, a second input (by) forces the storage element into the opposite state. the reset condition is pre- dominant over the set condition. (see figure 17 .) the initial state after configurat ion or global initial state is defined by a separate init0 and init1 attribute. by default, setting the srlow attribute sets init0, and setting the srhigh attribute sets init1. for each slice, set and reset can be set to be synchronous or asynchronous. virtex-ii de vices also have the ability to set init0 and init1 independent of srhigh and srlow. the control signals clock (clk), clock enable (ce) and set/reset (sr) are common to both storage elements in one slice. all of the control signals have independent polarity. any inverter placed on a control input is automatically absorbed. figure 14: virtex-ii clb element figure 15: virtex-ii slice configuration slice x1y1 slice x1y0 slice x0y1 slice x0y0 fast connects to neighbors switch matrix ds031_32_101600 shift cin cout tbuf x0y1 cout cin tbuf x0y0 register muxf5 muxfx cy srl16 ram16 lut g register arithmetic logic cy lut f ds031_31_100900 srl16 ram16 orcy
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 13 figure 16: virtex-ii slice (top half) g4 sopin a4 g3 a3 g2 a2 g1 a1 wg4 wg4 wg3 wg3 wg2 wg2 wg1 by wg1 dual-port lut ff latch ram rom shift-reg d 0 mc15 ws sr sr rev di g y g2 g1 by 1 0 prod dq ce ce ck clk muxcy yb dig dy y 0 1 muxcy 0 1 1 sopout dymux gymux ybmux orcy wsg we[2:0] shiftout cyog xorg we clk wsf altdig ce sr clk slicewe[2:0] multand shared between x & y registers shiftin cout cin ds031_01_112502 q
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 14 the set and reset functionality of a register or a latch can be configured as follows: no set or reset synchronous set synchronous reset synchronous set and reset asynchronous set (preset) asynchronous reset (clear) asynchronous set and re set (preset and clear) the synchronous reset has precedence over a set, and an asynchronous clear has precedence over a preset. distributed selectram memory each function generator (lut) can implement a 16 x 1-bit synchronous ram resource ca lled a distributed selectram element. the selectram elements are configurable within a clb to implement the following: single-port 16 x 8 bit ram single-port 32 x 4 bit ram single-port 64 x 2 bit ram single-port 128 x 1 bit ram dual-port 16 x 4 bit ram dual-port 32 x 2 bit ram dual-port 64 x 1 bit ram distributed selectram memory modules are synchronous (write) resources. the combinatorial read access time is extremely fast, while the syn chronous write simplifies high-speed designs. a synchronous read can be imple- mented with a storage element in the same slice. the dis- tributed selectram memory and the storage element share the same clock input. a write enable (we) input is active high, and is driven by the sr input. ta b l e 8 shows the number of luts (2 per slice) occupied by each distributed selectram configuration. for single-port configurations, distributed selectram mem- ory has one address port for synchronous writes and asyn- chronous reads. for dual-port configurations, distributed selectram mem- ory has one port for synchronous writes and asynchronous reads and another port for asynchronous reads. the func- tion generator (lut) has separated read address inputs (a1, a2, a3, a4) and write address inputs (wg1/wf1, wg2/wf2, wg3/wf 3, wg4/wf4). in single-port mode, read and write addresses share the same address bus. in dual-port mode, one function genera- tor (r/w port) is connected with shared read and write addresses. the second function generator has the a inputs (read) connected to the second read-only port address and the w inputs (write) shared with the first read/write port address. figure 17: register / latch configuration in a slice ff ffy latch sr rev dq ce ck yq ff ffx latch sr rev d q ce ck xq ce dx dy by clk bx sr attribute init1 init0 srhigh srlow attribute init1 init0 srhigh srlow reset type sync async ds031_22_110600 ta b l e 8 : distributed selectram configurations ram number of luts 16 x 1s 1 16 x 1d 2 32 x 1s 2 32 x 1d 4 64 x 1s 4 64 x 1d 8 128 x 1s 8 notes: 1. s = single-port configuration; d = dual-port configuration
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 15 figure 18 , figure 19 , and figure 20 illustrate various exam- ple configurations. similar to the ram configuration, each function generator (lut) can implement a 16 x 1-bit rom. five configurations are available: rom16x1, rom32x1, rom64x1, rom128x1, and rom256x1. the rom elements are cas- cadable to implement wider or/and deeper rom. rom con- tents are loaded at configuration. ta bl e 9 shows the number of luts occupied by each configuration. figure 18: distributed selectram (ram16x1s) figure 19: single-port distributed selectram (ram32x1s) a[3:0] d d di ws wsg we wclk ram 16x1s d q ram we ck a[4:1] wg[4:1] output registered output (optional) (sr) 4 4 (by) ds031_02_100900 a[3:0] d wsg f5mux we wclk ram 32x1s d q we we0 ck wsf d di ws ram g[4:1] a[4] wg[4:1] d di ws ram f[4:1] wf[4:1] output registered output (optional) (sr) 4 (by) (bx) 4 ds031_03_110100 figure 20: dual-port distributed selectram (ram16x1d) ta b l e 9 : rom configuration rom number of luts 16 x 1 1 32 x 1 2 64 x 1 4 128 x 1 8 (1 clb) 256 x 1 16 (2 clbs) a[3:0] d wsg we wclk ram 16x1d we ck d di ws ram g[4:1] wg[4:1] dual_port ram dual_port 4 (by) dpra[3:0] spo a[3:0] wsg we ck d di ws g[4:1] wg[4:1] dpo 4 4 ds031_04_110100 (sr)
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 16 shift registers each function generator can also be configured as a 16-bit shift register. the write operation is synchronous with a clock input (clk) and an optional clock enable, as shown in figure 21 . a dynamic read access is performed through the 4-bit address bus, a[3:0]. the configurable 16-bit shift regis- ter cannot be set or reset. the read is asynchronous, how- ever the storage element or flip-flop is available to implement a synchronous read. the storage element should always be used with a constant address. for exam- ple, when building an 8-bit shift register and configuring the addresses to point to the 7th bit, the 8th bit can be the flip-flop. the overall system performance is improved by using the superior clock-to-out of the flip-flops. an additional dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the ordinary lut output. (see figure 22 .) longer shift registers can be built with dynamic access to any bit in the chain. the shift register chaining and the muxf5, muxf6, and muxf7 multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one clb. figure 21: shift register configurations a[3:0] shiftin shiftout d(by) d mc15 di wsg ce (sr) clk srlc16 d q shift-reg we ck a[4:1] output registered output (optional) 4 ds031_05_110600 ws figure 22: cascadable shift register srlc16 mc15 mc15 d srlc16 di shiftin cascadable out slice s0 slice s1 slice s2 slice s3 1 shift chain in clb clb ds031_06_110200 ff ff d srlc16 mc15 mc15 d srlc16 di shiftin shiftout ff ff d srlc16 mc15 mc15 d srlc16 di di shiftin in shiftout ff ff d srlc16 mc15 mc15 d srlc16 di shiftout ff ff d di di di out
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 17 multiplexers virtex-ii function generators and associated multiplexers can implement the following: 4:1 multiplexer in one slice 8:1 multiplexer in two slices 16:1 multiplexer in one clb element (4 slices) 32:1 multiplexer in two clb elements (8 slices) each virtex-ii slice has one muxf5 multiplexer and one muxfx multiplexer. the mu xfx multiplexer implements the muxf6, muxf7, or muxf8, as shown in figure 23 . each clb element has two muxf6 multiplexers, one muxf7 multiplexer and one muxf8 multiplexer. examples of multiplexers are shown in the virtex-ii user guide . any lut can implement a 2:1 multiplexer. fast lookahead carry logic dedicated carry logic provides fast arithmetic addition and subtraction. the virtex-ii clb has two separate carry chains, as shown in the figure 24 . the height of the carry chains is two bits per slice. the carry chain in the virtex-ii device is running upward. the dedi- cated carry path and carry multiplexer (muxcy) can also be used to cascade function generators for implementing wide logic functions. arithmetic logic the arithmetic logic includes an xor gate that allows a 2-bit full adder to be implemented within a slice. in addition, a dedicated and (mult_and) gate (shown in figure 16 ) improves the efficiency of multiplier implementation. figure 23: muxf5 and muxfx multiplexers slice s1 slice s0 slice s3 slice s2 clb ds031_08_100201 f5 f6 f5 f7 f5 f6 f5 f8 muxf8 combines the two muxf7 outputs (two clbs) muxf6 combines the two muxf5 outputs from slices s2 and s3 muxf7 combines the two muxf6 outputs from slices s0 and s2 muxf6 combines the two muxf5 outputs from slices s0 and s1 g f g f g f g f
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 18 figure 24: fast carry logic path ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy cin cin cin cout ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy cin cout cout to cin of s2 of the next clb cout to s0 of the next clb (first carry chain) (second carry chain) slice s1 slice s0 slice s3 slice s2 clb ds031_07_110200
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 19 sum of products each virtex-ii slice has a dedicated or gate named orcy, oring together outputs from the slices carryout and the orcy from an adjacent slice. the orcy gate with the dedicated sum of products (sop) chain are designed for implementing large, flexible sop chains. one input of each orcy is con- nected through the fast sop chain to the output of the previous orcy in the same slice row. the second input is connected to the output of the top muxcy in the same slice, as shown in figure 25 . luts and muxcys can implement large and gates or other combinatorial logic functions. figure 26 illustrates lut and muxcy resources configured as a 16-input and gate. figure 25: horizontal cascade chain muxcy 4 muxcy 4 slice 1 ds031_64_110300 orcy lut lut muxcy 4 muxcy 4 slice 0 v cc lut lut muxcy 4 muxcy 4 slice 3 orcy lut lut muxcy 4 muxcy 4 slice 2 v cc lut lut sop clb muxcy 4 muxcy 4 slice 1 orcy lut lut muxcy 4 muxcy 4 slice 0 v cc lut lut muxcy 4 muxcy 4 slice 3 orcy lut lut muxcy 4 muxcy 4 slice 2 v cc lut lut clb figure 26: wide-input and gate (16 inputs) muxcy and 4 16 muxcy 4 ?0? 01 01 ?0? 01 ?0? muxcy 4 slice out out slice lut ds031_41_110600 lut lut v cc muxcy 4 01 lut
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 20 3-state buffers introduction each virtex-ii clb contains two 3-state drivers (tbufs) that can drive on-chip busses. each 3-state buffer has its own 3-state control pin and its own input pin. each of the four slices have access to the two 3-state buff- ers through the switch matrix, as shown in figure 27 . tbufs in neighboring clbs can access slice outputs by direct connects. the outputs of the 3-state buffers drive hor- izontal routing resources used to implement 3-state busses. the 3-state buffer logic is implemented using and-or logic rather than 3-state drivers, so that timing is more predict- able and less load dependant especially with larger devices. locations / organization four horizontal routing resources per clb are provided for on-chip 3-state busses. each 3-state buffer has access alternately to two horizontal lines, which can be partitioned as shown in figure 28 . the switch matrices corresponding to selectram memory and mu ltiplier or i/o blocks are skipped. number of 3-state buffers ta b l e 1 0 shows the number of 3-state buffers available in each virtex-ii device. the number of 3-state buffers is twice the number of clb elements. clb/slice configurations ta bl e 1 1 summarizes the logic resources in one clb. all of the clbs are identical and each clb or slice can be implemented in one of the configurations listed. ta b l e 1 2 shows the available re sources in all clbs. figure 27: virtex-ii 3-state buffers slice s3 slice s2 slice s1 slice s0 switch matrix ds031_37_060700 tbuf tbuf table 10: virtex-ii 3-state buffers device 3-state buffers per row total number of 3-state buffers xc2v40 16 128 xc2v80 16 256 xc2v250 32 768 xc2v500 48 1,536 xc2v1000 64 2,560 xc2v1500 80 3,840 XC2V2000 96 5,376 xc2v3000 112 7,168 xc2v4000 144 11,520 xc2v6000 176 16,896 xc2v8000 208 23,296 figure 28: 3-state buffer connection to horizontal lines switch matrix clb-ii switch matrix clb-ii ds031_09_032700 programmable connection 3 - state lines
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 21 18 kbit block selectram resources introduction virtex-ii devices incorporate large amounts of 18 kbit block selectram. these complement the distributed selectram resources that provide shallow ram structures imple- mented in clbs. each virtex -ii block selectram is an 18 kbit true dual-port ram with two independently clocked and independently controlled synchronous ports that access a common storage area. both ports are functionally identical. clk, en, we, and ssr polarities are defined through con- figuration. each port has the following ty pes of inputs: clock and clock enable, write enable, set/reset, and address, as well as separate data/parity data inputs (for write) and data/parity data outputs (for read). operation is synchronous; the block selectram behaves like a register. control, address and data inputs must (and need only) be valid during the set-up time window prior to a rising (or falling, a configuration option) clock edge. data outputs change as a result of the same clock edge. configuration the virtex-ii block selectram supports various configura- tions, including single- and dual-port ram and various data/address aspect ratios. supported memory configura- tions for single- and dual-port modes are shown in ta b l e 1 3 . ta bl e 1 1 : logic resources in one clb slices luts flip-flops mult_ands arithmetic & carry-chains sop chains distributed selectram shift registers tbuf 4 8 8 8 2 2 128 bits 128 bits 2 ta bl e 1 2 : virtex-ii logic resources available in all clbs device clb array: row x column number of slices number of luts max distributed selectram or shift register (bits) number of flip-flops number of carry-chains (1) number of sop chains (1) xc2v40 8 x 8 256 512 8,192 512 16 16 xc2v80 16 x 8 512 1,024 16,384 1,024 16 32 xc2v250 24 x 16 1,536 3,072 49,152 3,072 32 48 xc2v500 32 x 24 3,072 6,144 98,304 6,144 48 64 xc2v1000 40 x 32 5,120 10,240 163,840 10,240 64 80 xc2v1500 48 x 40 7,680 15,360 245,760 15,360 80 96 XC2V2000 56 x 48 10,752 21,504 344,064 21,504 96 112 xc2v3000 64 x 56 14,336 28,672 458,752 28,672 112 128 xc2v4000 80 x 72 23,040 46,080 737,280 46,080 144 160 xc2v6000 96 x 88 33,792 67,584 1,081,344 67,584 176 192 xc2v8000 112 x 104 46,592 93,184 1,490,944 93,184 208 224 notes: 1. the carry-chains and sop chains can be split or cascaded. table 13: dual- and single-port configurations 16k x 1 bit 2k x 9 bits 8k x 2 bits 1k x 18 bits 4k x 4 bits 512 x 36 bits
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 22 single-port configuration as a single-port ram, the block selectram has access to the 18 kbit memory locations in any of the 2k x 9-bit, 1k x 18-bit, or 512 x 36-bit configurations and to 16 kbit memory locations in any of the 16k x 1-bit, 8k x 2-bit, or 4k x 4-bit configurations. the advantage of the 9-bit, 18-bit and 36-bit widths is the ability to store a parity bit for each eight bits. parity bits must be generated or checked exter- nally in user logic. in such ca ses, the width is viewed as 8 + 1, 16 + 2, or 32 + 4. these extra parity bits are stored and behave exactly as the other bits, including the timing param- eters. video applications can use the 9-bit ratio of virtex-ii block selectram memory to advantage. e ach block selectram cell is a fully synchronous memory as illustrated in figure 29 . input data bus and output data bus widths are identical. dual-port configuration as a dual-port ram, each port of block selectram has access to a common 18 kbit memory resource. these are fully synchronous ports with independent control signals for each port. the data widths of the two ports can be config- ured independently, providing built-in bus-width conversion. ta b l e 1 4 illustrates the different co nfigurations available on ports a & b. if both ports are configured in either 2k x 9-bit, 1k x 18-bit, or 512 x 36-bit configurations, the 18 kbit block is accessi- ble from port a or b. if both ports are configured in either 16k x 1-bit, 8k x 2-bit. or 4k x 4-bit configurations, the 16 k-bit block is accessible from port a or port b. all other configurations result in one port having access to an 18 kbit memory block and the other port having access to a 16 k-bit subset of the memory block equal to 16 kbits. figure 29: 18 kbit block selectram memory in single-port mode dop dip addr we en ssr clk 18 kbit block selectram ds031_10_071602 di do ta bl e 1 4 : dual-port mode configurations port a 16k x 1 16k x 1 16k x 1 16k x 1 16k x 1 16k x 1 port b 16k x 1 8k x 2 4k x 4 2k x 9 1k x 18 512 x 36 port a 8k x 2 8k x 2 8k x 2 8k x 2 8k x 2 port b 8k x 2 4k x 4 2k x 9 1k x 18 512 x 36 port a 4k x 4 4k x 4 4k x 4 4k x 4 port b 4k x 4 2k x 9 1k x 18 512 x 36 port a 2k x 9 2k x 9 2k x 9 port b 2k x 9 1k x 18 512 x 36 port a 1k x 18 1k x 18 port b 1k x 18 512 x 36 port a 512 x 36 port b 512 x 36
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 23 each block selectram cell is a fully synchronous memory, as illustrated in figure 30 . the two ports have independent inputs and outputs and are independently clocked. port aspect ratios ta bl e 1 5 shows the depth and the width aspect ratios for the 18 kbit block selectram. virtex-ii block selectram also includes dedicated routing res ources to provide an efficient interface with clbs, block selectram, and multipliers. read/write operations the virtex-ii block selectram read operation is fully syn- chronous. an address is presented, and the read operation is enabled by control signals wea and web in addition to ena or enb. then, depending on clock polarity, a rising or falling clock edge causes the st ored data to be loaded into output registers. the write operation is also fully synchronous. data and address are presented, and the write operation is enabled by control signals wea or web in addition to ena or enb. then, again depending on the clock input mode, a rising or falling clock edge causes the da ta to be loaded into the memory cell addressed. a write operation performs a simultaneous read operation. three different options are available, selected by configura- tion: 1. ?write_first? the ?write_first? option is a transparent mode. the same clock edge that writes the data input (di) into the memory also transfers di into the output registers do as shown in figure 31 . figure 30: 18 kbit block selectram in dual-port mode dopa dopb dipa addra wea ena ssra clka dipb addrb web enb ssrb clkb 18 kbit block selectram ds031_11_071602 dob doa dia dib table 15: 18 kbit block selectram port aspect ratio width depth address bus data bus parity bus 1 16,384 addr[13:0] data[0] n/a 2 8,192 addr[12:0] data[1:0] n/a 4 4,096 addr[11:0] data[3:0] n/a 9 2,048 addr[10:0] data[7:0] parity[0] 18 1,024 addr[9:0] data[15:0] parity[1:0] 36 512 addr[8:0] data[31:0] parity[3:0] figure 31: write_first mode clk we data_in data_in new aa address internal memory do data_out = data_in data_out di ds031_14_102000 new ram contents new old
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 24 2. ?read_first? the ?read_first? option is a read-before-write mode. the same clock edge that writes data input (di) into the memory also transfers the prior content of the memory cell addressed into the data output registers do, as shown in figure 32 . 3. ?no_change? the ?no_change? option maintains the content of the output registers, regardless of the write operation. the clock edge during the write mode has no effect on the content of the data output register do. when the port is configured as ?no_change?, only a read operation loads a new value in the output register do, as shown in figure 33 . figure 32: read_first mode clk we data_in data_in new aa old address internal memory do prior stored data data_out di ds031_13_102000 ram contents new old figure 33: no_change mode clk we data_in data_in new aa last read cycle content (no change) address internal memory do no change during write data_out di ds031_12_102000 ram contents new old
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 25 control pins and attributes virtex-ii selectram memory has two independent ports with the control signals described in ta bl e 1 6 . all control inputs including the clock have an optional inversion. initial memory content is determined by the init_xx attributes. separate attributes determine the output register value after device configuration (init) and ssr is asserted (srval). both attributes (init_b and srval) are available for each port when a block selectram resource is config- ured as dual-port ram. locations virtex-ii selectram memory blocks are located in either four or six columns. the number of blocks per column depends of the device array size and is equivalent to the number of clbs in a column divided by four. column loca- tions are shown in ta bl e 1 7 . ta bl e 1 6 : control functions control signal function clk read and write clock en enable affects read, write, set, reset we write enable ssr set do register to srval (attribute) table 17: selectram memory floor plan device columns selectram blocks per column total xc2v40 2 2 4 xc2v80 2 4 8 xc2v250 4 6 24 xc2v500 4 8 32 xc2v1000 4 10 40 xc2v1500 4 12 48 XC2V2000 4 14 56 xc2v3000 6 16 96 xc2v4000 6 20 120 xc2v6000 6 24 144 xc2v8000 6 28 168 figure 34: block selectram (2-column, 4-column, and 6-column) 2 clb columns 2 clb columns 2 clb columns n clb columns 2 clb columns n clb columns 2 clb columns 2 clb columns 2 clb columns n clb columns n clb columns n clb columns 2 clb columns n clb columns selectram blocks selectram blocks ds031_38_101000 2 clb column 2 clb columns selectram blocks 2 clb column 2 clb columns
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 26 total amount of selectram memory ta bl e 1 8 shows the amount of block selectram memory available for each virtex-ii device. the 18 kbit selectram blocks are cascadable to implement deeper or wider single- or dual-port memory resources. 18-bit x 18-bit multipliers introduction a virtex-ii multiplier block is an 18-bit by 18-bit 2?s comple- ment signed multiplier. virtex-ii devices incorporate many embedded multiplier blocks. these multipliers can be asso- ciated with an 18 kbit block selectram resource or can be used independently. they are optimized for high-speed operations and have a lower power consumption compared to an 18-bit x 18-bit multiplier in slices. each selectram memory and multiplier block is tied to four switch matrices, as shown in figure 35 . association with bl ock selectram memory the interconnect is designe d to allow selectram memory and multiplier blocks to be used at the same time, but some interconnect is shared between the selectram and the multiplier. thus, selectram memo ry can be used only up to 18 bits wide when the multiplier is used, because the multi- plier shares inputs with the upper data bits of the selectram memory. this sharing of the interconnect is optimized for an 18-bit-wide block selectram resource feeding the multi- plier. the use of selectram memory and the multiplier with an accumulator in luts allows for implementation of a digi- tal signal processor (dsp) multiplier-accumulator (mac) function, which is commonly used in finite and infinite impulse response (fir a nd iir) digital filters. configuration the multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). both a and b are 18-bit-wide inputs, and the output is 36 bits. figure 36 shows a multiplier block. ta bl e 1 8 : virtex-ii selectram memory available device total selectram memory blocks in kbits in bits xc2v40 4 72 73,728 xc2v80 8 144 147,456 xc2v250 24 432 442,368 xc2v500 32 576 589,824 xc2v1000 40 720 737,280 xc2v1500 48 864 884,736 XC2V2000 56 1,008 1,032,192 xc2v3000 96 1,728 1,769,472 xc2v4000 120 2,160 2,211,840 xc2v6000 144 2,592 2,654,208 xc2v8000 168 3,024 3,096,576 figure 35: selectram and multiplier blocks figure 36: multiplier block switch matrix switch matrix 18-kbit block selectram 18 x 18 multiplier switch matrix switch matrix ds031_33_101000 mult 18 x 18 a[17:0] p[35:0] b[17:0] multiplier block ds031_40_100400
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 27 locations / organization multiplier organization is identi cal to the 18 kbit selectram organization, because each multiplier is associated with an 18 kbit block selectram resource. in addition to the built-in multiplier blocks, the clb elements have dedicated logic to implement efficient multipliers in logic. (refer to configurable logic blocks (clbs) ). table 19: multiplier floor plan device columns multipliers per column total xc2v40 2 2 4 xc2v80 2 4 8 xc2v250 4 6 24 xc2v500 4 8 32 xc2v1000 4 10 40 xc2v1500 4 12 48 XC2V2000 4 14 56 xc2v3000 6 16 96 xc2v4000 6 20 120 xc2v6000 6 24 144 xc2v8000 6 28 168 figure 37: multipliers (2-column, 4-column, and 6-column) ds031_39_101000 2 clb columns 2 clb columns 2 clb columns n clb columns 2 clb columns n clb columns 2 clb columns 2 clb columns 2 clb columns n clb columns n clb columns n clb columns 2 clb columns n clb columns multiplier blocks multiplier blocks 2 clb column 2 clb columns multiplier blocks 2 clb column 2 clb columns
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 28 global clock multiplexer buffers virtex-ii devices have 16 clock input pins that can also be used as regular user i/os. eight clock pads are on the top edge of the device, in the middle of the array, and eight are on the bottom edge, as illustrated in figure 38 . the global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution in virtex-ii devices. like the clock pads, eight global clock multiplexer buffers are on the top edge of the device and eight are on the bottom edge. each global clock buffer can either be driven by the clock pad to distribute a clock directly to the device, or driven by the digital clock manager (dcm), discussed in digital clock manager (dcm) , page 30 . each global clock buffer can also be driven by local interconnects. the dcm has clock output(s) that can be connected to global clock buffer inputs, as shown in figure 39 . global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in clbs and iobs, and selectram blocks. eight global clocks can be used in each quadrant of the virtex-ii device. designers should consider the clock distri- bution detail of the device prior to pin-locking and floorplan- ning (see the virtex-ii user guide ). figure 40 shows clock distribution in virtex-ii devices. figure 38: virtex-ii clock pads 8 clock pads 8 clock pads virtex-ii device ds031_42_101000 figure 39: virtex-ii clock distribution configurations clock pad clock buffer i 0 clock distribution clock pad clock buffer i 0 clock distribution clkin clkout dcm ds031_43_101000 figure 40: virtex-ii clock distribution 8 8 8 8 nw nw ne sw se ne sw se ds031_45_120200 8 bufgmux 8 bufgmux 8 max 8 bufgmux 8 bufgmux 16 clocks 16 clocks
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 29 in each quadrant, up to eight clocks are organized in clock rows. a clock row supports up to 16 clb rows (eight up and eight down). for the largest devices a new clock row is added, as necessary. to reduce power consumption, any unused clock branches remain static. global clocks are driven by dedicated clock buffers (bufg), which can also be used to gate the clock (bufgce) or to mul- tiplex between two independent clock inputs (bufgmux). the most common configuration option of this element is as a buffer. a bufg function in this (global buffer) mode, is shown in figure 41 . the virtex-ii global clock buffer bufg can also be config- ured as a clock enable/disable circuit ( figure 42 ), as well as a two-input clock multiplexer ( figure 43 ). a functional description of these two options is provided below. each of them can be used in either of two modes, selected by con- figuration: rising clock edge or falling clock edge. this section describes the rising clock edge option. for the opposite option, falling clock edg e, just change all "rising" references to "falling" and all "high" references to "low", except for the description of the ce or s levels. the rising clock edge option uses the bufgce and bufgmux prim- itives. the falling clock edge option uses the bufgce_1 and bufgmux_1 primitives. bufgce if the ce input is active (high) prior to the incoming rising clock edge, this low-to-high-to-low clock pulse passes through the clock buffer. any level change of ce during the incoming clock high time has no effect. if the ce input is inactive (low ) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays low. any level change of ce during the incoming clock high time has no effect. ce must not change during a short setup window just prior to the rising clock edge on the bufgce input i. violating this setup time requirement can result in an undefined runt pulse output. bufgmux bufgmux can switch between two unrelated, even asyn- chronous clocks. basically, a low on s selects the i0 input, a high on s selects the i1 input. switching from one clock to the other is done in such a way that the output high and low time is never shorter than the shortest high or low time of either input clock. as long as the presently selected clock is high, any level change of s has no effect . if the presently selected clock is low while s changes, or if it goes low after s has changed, the output is kept low until the other ("to-be-selected") clock has made a transition from high to low. at that instant, the new clock starts driv- ing the output. the two clock inputs can be asynchronous with regard to each other, and the s input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock; that is, prior to the rising edge of the bufgmux output o. violating this setup time requirement can result in an undefined runt pulse output. all virtex-ii devices have 16 global clock multiplexer buffers. figure 44 shows a switchover from clk0 to clk1. the current clock is clk0. s is activated high. if clk0 is currently high, th e multiplexer waits for clk0 to go low. once clk0 is low, the multiplexer output stays low until clk1 transitions high to low. when clk1 transitions from high to low, the output switches to clk1. no glitches or short pulses can appear on the output. figure 41: virtex-ii bufg function figure 42: virtex-ii bufgce function o i bufg ds031_61_101200 o i ce bufgce ds031_62_101200 figure 43: virtex-ii bufgmux function figure 44: clock multiplexer waveform diagram o i0 i1 s bufgmux ds031_63_112900 s clk0 clk1 out wait for low switch ds031_46_112900
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 30 digital clock manager (dcm) the virtex-ii dcm offers a wide range of powerful clock management features. clock de-skew : the dcm generates new system clocks (either internally or externally to the fpga), which are phase-aligned to the input clock, thus eliminating clock distribution delays. frequency synthesis : the dcm generates a wide range of output clock frequencies, performing very flexible clock multiplication and division. phase shifting : the dcm provides both coarse phase shifting and fine-grained phase shifting with dynamic phase shift control. the dcm utilizes fully digital delay lines allowing robust high-precision control of clock phase and frequency. it also utilizes fully digital feedback systems, operating dynamically to compensate for temperature and voltage variations dur- ing operation. up to four of the nine dcm clock outputs can drive inputs to global clock buffers or global clock multiplexer buffers simul- taneously (see figure 45 ). all dcm clock outputs can simul- taneously drive general routing resources, including routes to output buffers. the dcm can be configured to delay the completion of the virtex-ii configuration process until after the dcm has achieved lock. this guarantees that the chip does not begin operating until after the system clocks generated by the dcm have stabilized. the dcm has the following general control signals: rst input pin : resets the entire dcm locked output pin: asserted high when all enabled dcm circuits have locked. status output pins (active high): shown in ta b l e 2 0 . clock de-skew the dcm de-skews the output clocks relative to the input clock by automatically adjusting a digital delay line. addi- tional delay is introduced so that clock edges arrive at inter- nal registers and block rams simultaneously with the clock edges arriving at the input clock pad. alternatively, external clocks, which are also de-skewed relative to the input clock, can be generated for board-level routing. all dcm output clocks are phase-aligned to clk0 and, therefore, are also phase-aligned to the input clock. to achieve clock de-skew, the clkfb input must be con- nected, and its source must be either clk0 or clk2x. note that clkfb must always be connected, unless only the clkfx or clkfx180 outputs are used and de-skew is not required. frequency synthesis the dcm provides flexible methods for generating new clock frequencies. each method has a different operating frequency range and different ac characteristics. the clk2x and clk2x180 outputs double the clock frequency. the clkdv output creates divided output clocks with divi- sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. the clkfx and clkfx180 outputs can be used to pro- duce clocks at the following frequency: freq clkfx = (m/d) * freq clkin where m and d are two integers. specifications for m and d are provided under dcm timing parameters in module 3. by default, m=4 and d=1, which results in a clock output fre- quency four times faster than the clock input frequency (clkin). clk2x180 is phase shifted 180 degrees relative to clk2x. clkfx180 is phase shifted 180 degrees relative to clkfx. all frequency synthesis outputs automatically have 50/50 duty cycles (with the exception of the clkdv output when performing a non-integer divide in high-frequency mode). figure 45: digital clock manager clkin clkfb clk180 clk270 clk0 clk90 clk2x clk2x180 clkdv dcm ds031_67_112900 clkfx clkfx180 locked status[7:0] psdone rst dssen psincdec psen psclk clock signal control signal table 20: dcm status pins status pin function 0 phase shift overflow 1 clkin stopped 2 clkfx stopped 3n/a 4n/a 5n/a 6n/a 7n/a
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 31 note that clk2x and clk2 x180 are not available in high-frequency mode. phase shifting the dcm provides additional control over clock skew through either coarse or fine-grained phase shifting. the clk0, clk90, clk180, and clk270 outputs are each phase shifted by ? of the input clock period relative to each other, providing coarse phase control. note that clk90 and clk270 are not available in high-frequency mode. fine-phase adjustment affects all nine dcm output clocks. when activated, the phase shift between the rising edges of clkin and clkfb is a specified fraction of the input clock period. in variable mode, the phase_shift value can also be dynamically incremented or decremented as determined by psincdec synchronously to psclk, when the psen input is active. figure 46 illustrates the effe cts of fine-phase shifting. for more information on dcm features, see the virtex-ii user guide . ta b l e 2 1 lists fine-phase shifting control pins, when used in variable mode. two separate components of the phase shift range must be understood: phase_shift attribute range fine_shift_range dcm timing parameter range the phase_shift attribute is the numerator in the following equation: phase shift (ns) = ( phase_shift /256) * period clkin the full range of this attribute is always -255 to +255, but its practical range varies with clkin frequency, as constrained by the fine_shift_range component, which represents the total delay achievable by the phase shift delay line. total delay is a function of the number of delay taps used in the circuit. across process, voltag e, and temperature, this abso- lute range is guaranteed to be as specified under dcm tim- ing parameters in module 3. absolute range (fixed mode) = fine_shift_range absolute range (variable mode) = fine_shift_range /2 the reason for the difference between fixed and variable modes is as follows. for variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the dcm sets the "zero phase skew" point as the middle of the delay line, thus dividing the total delay line range in half. in fixed mode, since the phase_shift value never changes after configu- ration, the entire delay line is available for insertion into either the clkin or clkfb path (to create either positive or negative skew). taking both of these components into consideration, the fol- lowing are some usage examples: if period clkin = 2 * fine_shift_range , then phase_shift in fixed mode is limited to 128, and in variable mode it is limited to 64. if period clkin = fine_shift_range , then table 21: fine-phase shifting control pins control pin direction function psincdec in increment or decrement psen in enable phase shift psclk in clock for phase shift psdone out active when completed figure 46: fine-phase shifting effects clkout_phase_shift = fixed clkout_phase_shift = variable clkout_phase_shift = none clkin clkin clkin clkfb (ps/256) x period clkin (ps negative) (ps/256) x period clkin (ps positive) (ps/256) x period clkin (ps negative) (ps/256) x period clkin (ps positive) ds031_48_101201 clkfb clkfb
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 32 phase_shift in fixed mode is limited to 255, and in variable mode it is limited to 128. if period clkin 0.5 * fine_shift_range , then phase_shift is limited to 255 in either mode. operating modes the frequency ranges of dcm input and output clocks depend on the operating mode specified, either low-frequency mode or high-frequency mode, according to ta bl e 2 2 . (for actual values, see virtex-ii switching char- acteristics in module 3). the cl k2x, clk2x180, clk90, and clk270 outputs are not available in high-frequency mode. high or low-frequency mode is selected by an attribute. locations/organization virtex-ii dcms are placed on the top and bottom of each block ram and multiplier column. the number of dcms depends on the device size, as shown in ta bl e 2 3 . ta bl e 2 2 : dcm frequency ranges output clock low-frequency mode high-frequency mode clkin input clk output clkin input clk output clk0, clk180 clkin_freq_dll_lf clkout_freq_ 1x_lf clkin_freq_dll_hf clkout_freq_1x_hf clk90, clk270 clkin_freq_d ll_lf clkout_freq_1x_lf na na clk2x, clk2x180 clkin_freq_dll_lf clkout_freq_2x_lf na na clkdv clkin_freq_dll_lf clkout_freq_dv_l f clkin_freq_dll_hf clkout_freq_dv_hf clkfx, clkfx180 clkin_ freq_fx_lf clkout_fre q_fx_lf clkin_freq_fx_hf clkout_freq_fx_hf ta bl e 2 3 : dcm organization device columns dcms xc2v40 2 4 xc2v80 2 4 xc2v250 4 8 xc2v500 4 8 xc2v1000 4 8 xc2v1500 4 8 XC2V2000 4 8 xc2v3000 6 12 xc2v4000 6 12 xc2v6000 6 12 xc2v8000 6 12
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 33 active interconnect technology local and global virtex-ii routing resources are optimized for spee d and timing predictability, as well as to facilitate ip cor es implementation. virtex-ii active interconnect technology is a fully buffered programmable routing matrix. all routing resources are segmented to offer the advantages of a hierarchical solution. virtex-ii logic features like clbs, iobs, block ram, multipliers, and dcms are all connected to an identical switch matrix for access to global routing resources, as shown in figure 47 . each virtex-ii device can be represented as an array of switch matrixes with logic blocks attach ed, as illustrated in figure 48 . figure 47: active interconnect technology figure 48: routing resources switch matrix switch matrix switch matrix switch matrix switch matrix clb 18kb bram mult 18 x 18 switch matrix iob switch matrix dcm ds031_55_101000 switch matrix iob switch matrix iob switch matrix iob switch matrix dcm switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix selectram multiplier ds031_34_110300
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 34 place-and-route software takes advantage of this regular array to deliver optimum system performance and fast com- pile times. the segmented routing resources are essential to guarantee ip cores portabilit y and to efficiently handle an incremental design flow that is based on modular imple- mentations. total design time is reduced due to fewer and shorter design iterations. hierarchical routing resources most virtex-ii signals are routed using the global routing resources, which are located in horizontal and vertical rout- ing channels between each switch matrix. as shown in figure 49 , virtex-ii has fully buffered program- mable interconnections, with a number of resources counted between any two adjacent switch matrix rows or columns. fanout has minimal impact on the performance of each net. the long lines are bidirect ional wires that distribute signals across the device. vertical and horizontal long lines span the full height and width of the device. the hex lines route signals to every third or sixth block away in all four directions. organized in a staggered pattern, hex lines can only be driven from one end. hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). the double lines route signals to every first or second block away in all four directions. organized in a staggered pattern, double lines can be driven only at their endpoints. double-line signals can be accessed either at the endpoints or at the midpoint (one block from the source). the direct connect lines route signals to neighboring blocks: vertically, horizontally, and diagonally. the fast connect lines are the internal clb local interconnections from lut outputs to lut inputs. dedicated routing in addition to the global and local routing resources, dedi- cated signals are available. there are eight global clock nets per quadrant (see global clock multiplexer buffers ). horizontal routing resources are provided for on-chip 3-state busses. four partitionable bus lines are provided per clb row, permitting multiple busses within a row. (see 3-state buffers .) two dedicated carry-chain resources per slice column (two per clb column) propagate carry-chain muxcy output signals vertically to the adjacent slice. (see clb/slice configurations .) figure 49: hierarchical routing resources 24 horizontal long lines 24 vertical long lines 120 horizontal hex lines 120 vertical hex lines 40 horizontal double lines 40 vertical double lines 16 direct connections (total in all four directions) 8 fast connects ds031_60_110200
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 35 one dedicated sop chain per slice row (two per clb row) propagate orcy output logic signals horizontally to the adjacent slice. (see sum of products .) one dedicated shift-chain per clb connects the output of luts in shift-register mode to the input of the next lut in shift-register mode (vertically) inside the clb. (see shift registers , page 16 .) creating a design creating virtex-ii designs is easy with xilinx integrated syn- thesis environment (ise) de velopment systems, which sup- port advanced design capab ilities, including proactive timing closure, integrated logic analysis, and the fastest place and route runtimes in the industry. ise solutions enable designers to get the performance they need, quickly and easily. as a result of the ongoing cooperative development efforts between xilinx and eda allianc e partners, designers can take advantage of the benefits provided by eda technolo- gies in the programmable logi c design process. xilinx devel- opment systems are available in a number of easy to use configurations, collectively known as the ise series. ise alliance the ise alliance solution is designed to plug and play within an existing design environment. built using industry standard data formats and netlists, these stable, flexible products enable alliance eda partners to deliver their best design automation capabilities to xilinx customers, along with the time to market benefits of proactive timing closure. ise foundation the ise foundation solution delivers the benefits of true hdl-based design in a seamlessly integrated design envi- ronment. an intuitive project navigator, as well as powerful hdl design and two hdl synthesis tools, ensure that high-quality results are achieved quickly and easily. the ise foundation product includes: state diagram entry using xilinx statecad automatic hdl testbenc h generation using xilinx hdlbencher hdl simulation using modelsim xe design flow virtex-ii design flow proceeds as follows: design entry synthesis implementation verification most programmable logic designers iterate through these steps several times in the process of completing a design. design entry all xilinx ise development sy stems support the mainstream eda design entry capabilities , ranging from schematic design to advanced hdl design methodologies. given the high densities of the virtex-ii family, designs are created most efficiently using hdls. to further improve their time to market, many xilinx customers employ incremental, modu- lar, and intellectual property (ip) design techniques. when properly used, these techniques further accelerate the logic design process. to enable designers to leverage existing investments in eda tools, and to ensure high performance design flows, xilinx jointly develops tools with leading eda vendors, including: aldec ? cadence ? exemplar ? mentor graphics ? model technology ? synopsys ? synplicity ? complete information on allianc e series partners and their associated design flows is available at www.xilinx.com on the xilinx alliance series web page. the ise foundation product offers schematic entry and hdl design capabilities as pa rt of an integrated design solution - enabling one-stop shopping. these capabilities are powerful, easy to use, and they support the full portfolio of xilinx programmable logic de vices. hdl design capabil- ities include a color-coded hdl editor with integrated lan- guage templates, state diagram entry, and core generation capabilities. synthesis the ise alliance product is engineered to support advanced design flows with the industry's best synthesis tools. advanced design methodologies include: physical synthesis incremental synthesis rtl floorplanning direct physical mapping the ise foundation product seamlessly integrates synthesis capabilities purchased directly from exemplar, synopsys, and synplicity. in addition, it incl udes the capabilities of xilinx synthesis technology. a benefit of having two seamlessly integrated synthesis engines within an ise design flow is the ability to apply alter- native sets of optimization techniques on designs, helping to ensure that designers can meet even the toughest timing requirements.
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 36 design implementation the ise series development systems include xilinx tim- ing-driven implementation tools, frequently called ?place and route? or ?fitting? software. this robust suite of tools enables the creation of an intu itive, flexible, tightly inte- grated design flow that efficiently bridges ?logical? and ?physical? design domains. this simplifies the task of defin- ing a design, including its behavior, timing requirements, and optional layout (or floorplanning), as well as simplifying the task of analyzing reports generated during the imple- mentation process. the virtex-ii implementation process is comprised of syn- thesis, translation, mapping, place and route, and configu- ration file generation. while the tools can be run individually, many designers choose to run the entire implementation process with the click of a button. to assist those who prefer to script their design flows, xilinx provides xflow, an auto- mated single command line process. design verification in addition to conventional design verification using static timing analysis or simulation techniques, xilinx offers pow- erful in-circuit de bugging techniques using chipscope ila (integrated logic analysis). the reconfigurable nature of xilinx fpgas means that designs can be verified in real time without the need for extensive sets of software simula- tion vectors. for simulation, the system extracts post-layout timing infor- mation from the design database, and back-annotates this information into the netlist for use by the simulator. the back annotation featur es a variety of patented xilinx techniques, resulting in the industry?s mo st powerful simulation flows. alternatively, timing-critical portions of a design can be ver- ified using the xilinx static ti ming analyzer or a third party static timing analysis tool like synopsys prime time?, by exporting timing data in the stamp data format. for in-circuit debugging, chipscope ila enables designers to analyze the real-time behavior of a device while operating at full system speeds. logic analysis commands and cap- tured data are transferred between the chipscope software and ila cores within the virtex-ii fpga, using industry standard jtag protocols. these jtag transactions are driven over an optional download cable (multilinx or jtag), connecting the virtex de vice in the target system to a pc or workstation. chipscope ila was designed to look and feel like a logic analyzer, making it easy to begin debugging a design imme- diately. modifications to the desired logic analysis can be downloaded directly into the system in a matter of minutes. other unique features of virtex-ii design flow xilinx design flows feature a nu mber of unique capabilities. among these are efficient incremental hdl design flows; a robust capability that is enab led by xilinx exclusive hierar- chical floorplanning capabilit ies. another powerful design capability only available in the xilinx design flow is ?modular design?, part of the xilinx suit e of team design tools, which enables autonomous design, implementation, and verifica- tion of design modules. incremental synthesis xilinx unique hierarchical fl oorplanning capabilities enable designers to create a programmable logic design by isolating design changes within one hierarchical ?logic block?, and perform synthesis, verification and implementation pro- cesses on that specific logic bl ock. by preserving the logic in unchanged portions of a design, xilinx incremental design makes the high-density design process more efficient. xilinx hierarchical floorplanning capabilities can be speci- fied using the high-level floorplanner or a preferred rtl floorplanner (see the xilinx web site for a list of supported eda partners). when used in conjunction with one of the eda partners? floorplanners, higher performance results can be achieved, as many synthesis tools use this more predictable detailed physical implementation information to establish more aggressive and accurate timing estimates when performing their logic optimizations. modular design xilinx innovative modular desig n capabilities take the incre- mental design process one step further by enabling the designer to delegate respon sibility for completing the design, synthesis, verification, and implementation of a hier- archical ?logic block? to an arbitrary number of designers - assigning a specific region within the target fpga for exclu- sive use by each of the team members. this team design capability enables an autonomous approach to design modules, changing the hand-off point to the lead designer or integrator from ?my module works in simulation? to ?my module works in the fpga?. this unique design methodology also leve rages the xilinx hierarchical floorplanning capabilities an d enables the xilinx (or eda partner) floorplanner to manage the efficient implementa- tion of very high-density fpgas. configuration virtex-ii devices are configured by loading application spe- cific configuration data into the internal configuration mem- ory. configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used as general purpose inputs and outputs once config- uration is complete. depending on the system design, several configuration modes are supported, selectable via mode pins. the mode pins m2, m1 and m0 are dedicated pins. an additional pin, hswap_en is used in conjunction with the mode pins to select whether user i/o pins have pull-ups during configura- tion. by default, hswap_en is tied high (internal pull-up) which shuts off the pull-ups on the user i/o pins during con- figuration. when hswap_en is tied low, user i/os have
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 37 pull-ups during configuration. other dedicated pins are cclk (the configuration clock pin), done, prog_b, and the boundary-scan pins: tdi, tdo, tms, and tck. depending on the configuration mode chosen, cclk can be an output generated by the fpga, or an input accepting an externally generated clock. the configuration pins and boundary scan pins are independent of the v cco . the aux- iliary power supply (v ccaux ) of 3.3v is used for these pins. all configuration pins are lvttl 12 ma. (see virtex-ii dc characteristics in module 3.) a persist option is available wh ich can be used to force the configuration pins to retain their configuration function even after device configuration is complete. if the persist option is not selected then the configuration pins with the exception of cclk, prog_b, and done can be used as user i/o in normal operation. the persist option does not apply to the boundary-scan related pins. the persist feature is valuable in applications which employ partial reconfiguration or reconfiguration on the fly. configuration modes virtex-ii supports the following five configuration modes: slave-serial mode master-serial mode slave selectmap mode master selectmap mode boundary-scan mode (ieee 1532/ieee 1149) a detailed description of configuration modes is provided in the virtex-ii user guide . slave-serial mode in slave-serial mode, the fpga receives configuration data in bit-serial form from a serial prom or other serial source of configuration data. the cclk pin on the fpga is an input in this mode. the serial bitstream must be setup at the din input pin a short time before each rising edge of the externally generated cclk. multiple fpgas can be daisy-chained for configuration from a single source. after a parti cular fpga has been config- ured, the data for the next device is routed internally to the dout pin. the data on the dout pin changes on the rising edge of cclk. slave-serial mode is selected by applying <111> to the mode pins (m2, m1, m0). a weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. master-serial mode in master-serial mode, the cclk pin is an output pin. it is the virtex-ii fpga device that drives the configuration clock on the cclk pin to a xilinx serial prom which in turn feeds bit-serial data to the din input. the fpga accepts this data on each rising cclk edge. after the fpga has been loaded, the data for the next device in a daisy-chain is pre- sented on the dout pin after the rising cclk edge. the interface is identical to slave serial except that an inter- nal oscillator is used to gene rate the configuration clock (cclk). a wide range of frequencies can be selected for cclk which always starts at a slow default frequency. con- figuration bits then switch cclk to a higher frequency for the remainder of the configuration. slave selectmap mode the selectmap mode is the fastest configuration option. byte-wide data is written into the virtex-ii fpga device with a busy flag controlling the flow of data. an external data source provides a byte str eam, cclk, an active low chip select (cs_b) signal and a write signal (rdwr_b). if busy is asserted (high) by the fpga, the data must be held until busy goes low. data can also be read using the selectmap mode. if rdwr_b is asserted, configuration data is read out of the fpga as part of a readback opera- tion. after configuration, the pins of the selectmap port can be used as additional user i/o. alternatively, the port can be retained to permit high-speed 8-bit readback using the per- sist option. multiple virtex-ii fpgas can be configured using the selectmap mode, and be made to start-up simultaneously. to configure multiple devices in this way, wire the individual cclk, data, rdwr_b, and busy pins of all the devices in parallel. the individual devices are loaded separately by deasserting the cs_b pin of each device in turn and writing the appropriate data. master selectmap mode this mode is a master version of the selectmap mode. the device is configured byte-wide on a cclk supplied by the virtex-ii fpga device. timing is similar to the slave serial- map mode except that cclk is supplied by the virtex-ii fpga. boundary-scan (jtag, ieee 1532) mode in boundary-scan mode, dedicated pins are used for config- uring the virtex-ii device. the configuration is done entirely through the ieee 1149.1 test access port (tap). virtex-ii device configuration using bo undary scan is compliant with ieee 1149.1-1993 standard and the new ieee 1532 stan- dard for in-system configurable (isc) devices. the ieee 1532 standard is backward compliant with the ieee 1149.1-1993 tap and state machine. the ieee standard 1532 for in-system configurable (isc) devices is intended to be programmed, reprogrammed, or tested on the board via a physical and logical protocol. configuration through the boundary-scan port is always available, independent of the mode selection. selecting the boundary-scan mode simply turns off the other modes.
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 38 ta bl e 2 5 lists the total number of bits required to configure each device. configuration sequence the configuration of virtex-ii devices is a three-phase pro- cess after power on reset or por. por occurs when v ccint is greater than 1.2v, v ccaux is greater than 2.5v, and v cco (bank 4) is greater than 1.5v. once the por volt- ages have been reached, the three-phase process begins. first, the configuration memory is cleared. next, con- figuration data is loaded into the memory, and finally, the logic is activated by a start-up process. configuration is automatically initiated on power-up unless it is delayed by the user. the init_b pin can be held low using an open-drain driver. an open-drain is required since init_b is a bidirectional open-drain pin that is held low by a virtex-ii fpga device while the configuration memory is being cleared. extending the time that the pin is low causes the configuration sequencer to wait. thus, configuration is delayed by preventing entry into the phase where data is loaded. the configuration process can also be initiated by asserting the prog_b pin. the end of the memory-clearing phase is signaled by the init_b pin going high, and the completion of the entire process is sign aled by the done pin going high. the global set/reset (gsr) signal is pulsed after the last frame of configuration data is written but before the start-up sequence. the gsr signal resets all flip-flops on the device. the default start-up sequence is that one cclk cycle after done goes high, the global 3-state signal (gts) is released. this permits device outputs to turn on as neces- sary. one cclk cycle later, the global write enable (gwe) signal is released. this permits the internal storage ele- ments to begin changing state in response to the logic and the user clock. the relative timing of these events can be changed via con- figuration options in software. in addition, the gts and gwe events can be made dependent on the done pins of multiple devices all going high, forcing the devices to start synchronously. the sequence can also be paused at any stage, until lock has been achieved on any or all dcms, as well as the dci. readback in this mode, configuration data from the virtex-ii fpga device can be read back. readback is supported only in the selectmap (master and slave) and boundary scan mode. along with the configuration data, it is possible to read back the contents of all registers, distributed selectram, and block ram resources. this capa bility is used for real-time debugging. for more detailed configuration information, see the virtex-ii platform fpga user guide. ta bl e 2 4 : virtex-ii configuration mode pin settings configuration mode (1) m2 m1 m0 cclk direction data width serial d out (2) master serial 0 0 0 out 1 yes slave serial 1 1 1 in 1 yes master selectmap 0 1 1 out 8 no slave selectmap 1 1 0 in 8 no boundary scan 1 0 1 n/a 1 no notes: 1. the hswap_en pin controls the pullups. setting m2, m1, and m0 selects the configuration mode, while the hswap_en pin controls whether or not the pullups are used. 2. daisy chaining is possible only in modes where serial d out is used. for example, in selectmap modes, the first device does not support daisy chaining of downstream devices. ta bl e 2 5 : virtex-ii bitstream lengths device # of configuration bits xc2v40 360,096 xc2v80 635,296 xc2v250 1,697,184 xc2v500 2,761,888 xc2v1000 4,082,592 xc2v1500 5,659,296 XC2V2000 7,492,000 xc2v3000 10,494,368 xc2v4000 15,659,936 xc2v6000 21,849,504 xc2v8000 29,063,072
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 39 bitstream encryption virtex-ii devices have an on-chip decryptor using one or two sets of three keys for triple-key data encryption standard (des) operation. xilinx softwa re tools offer an optional encryption of the configuration data (bitstream) with a tri- ple-key des determined by the designer. the keys are stored in the fpga by jtag instruction and retained by a battery connected to the v batt pin, when the device is not powered. virtex-ii devices can be configured with the corresponding encrypted bitstream, using any of the configuration modes described previously. a detailed description of how to use bitstream encryption is provided in the virtex-ii user guide . your local fae can also provide specific information on this feature. partial reconfiguration partial reconfiguration of virtex-ii devices can be accom- plished in either slave selectmap mode or boundary-scan mode. instead of resetting the chip and doing a full configu- ration, new data is loaded into a specified area of the chip, while the rest of the chip remains in operation. data is loaded on a column basis, with the smallest load unit being a configuration ?frame? of the bitstream (device size depen- dent). partial reconfiguration is useful for applications that require different designs to be loaded into the same area of a chip, or that require the ability to change portions of a design without having to reset or reconfigure the entire chip. revision history this section records the change history for this module of the data sheet. date version revision 11/07/00 1.0 early access draft. 12/06/00 1.1 initial release. 01/15/01 1.2 added values to the tables in the virtex-ii performance characteristics and virtex-ii switching characteristics sections. 01/25/01 1.3 the data sheet was divided into four modules (per the current style standard). a note was added to ta b l e 1 . 04/02/01 1.5 under input/output individual options , the range of values for optional pull-up and pull-down resistors was changed to 10 - 60 k ? from 50 - 100 k ?. skipped v1.4 to sync up modules. reverted to traditional double-column format. 07/30/01 1.6 added table 6 . changed definition of multiply and divide integer ranges under digital clock manager (dcm) . made numerous minor edits throughout this module. 10/02/01 1.7 updated descriptions under digitally controlled impedance (dci) , global clock multiplexer buffers , digital clock manager (dcm) , and creating a design . 10/12/01 1.8 made clarifying edits under digital clock manager (dcm) . 11/29/01 1.9 changed bitstream lengths for each device in ta bl e 2 5 . 07/16/02 2.0 updated compatible input standards listed in table 6. 09/26/02 2.1 changed number of resources available to the xc2v40 device in ta b l e 1 2 . clarified power on reset information under configuration sequence . 12/06/02 2.1.1 cosmetic edits.
virtex?-ii platform fpgas: detailed description r ds031-2 (v3.0) august 1, 2003 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 40 virtex-ii data sheet the virtex-ii data sheet contains the following modules: virtex?-ii platform fpgas: introduction and overview (module 1) virtex?-ii platform fpgas: detailed description (module 2) virtex?-ii platform fpgas: dc and switching characteristics (module 3) virtex?-ii platform fpgas: pinout information (module 4) 05/07/03 2.1.2 added qualification note to figure 13, page 11 . corrected sentence in section input/output individual options , page 4 , to read ?the optional weak-keeper circuit is connected to each user i/o pad .? corrected typographical errors in ta bl e 3 for names of hstl_[x]_dci_18 standards. 06/19/03 2.2 removed compatible output standards and compatible input standards tables. added new ta bl e 5 , summary of voltage supply requirements for all input and output standards . this table replaces deleted i/o standards tables. added section rules for combining i/o standards in the same bank , page 6 . 08/01/03 3.0 all virtex-ii devices and speed grades now production. see table 13, module 3. date version revision
? 2001-2003 xilinx, inc. all rights reserved. all xilinx trademark s, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 1 virtex-ii electrical characteristics virtex-ii devices are provided in ? 4, ?5 , and ? 6 speed grades, with ? 6 having the highest performance. virtex-ii dc and ac characteristics are specified for both commercial and industrial grades. except the operating tem- perature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a ? 4 speed grade industrial device are the same as for a ? 4 speed grade com- mercial device). however, only selected speed grades and/or devices might be available in the industrial range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parame- ters included are common to popular designs and typical applications. contact xilinx for design considerations requiring more detailed information. all specifications are subject to change without notice. virtex-ii dc characteristics 0 38 virtex?-ii platform fpgas: dc and switching characteristics ds031-3 (v3.0) august 1, 2003 00 product specification r ta bl e 1 : absolute maximum ratings symbol description (1) units v ccint internal supply voltage relative to gnd ? 0.5 to 1.65 v v ccaux auxiliary supply voltage relative to gnd ? 0.5 to 4.0 v v cco output drivers supply voltage relative to gnd ? 0.5 to 4.0 v v batt key memory battery backup supply ? 0.5 to 4.0 v v ref input reference voltage ? 0.5 to v cco + 0.5 v v in (3) input voltage relative to gnd (user and dedicated i/os) ? 0.5 to v cco + 0.5 v v ts voltage applied to 3-state output (user and dedicated i/os) ? 0.5 to 4.0 v t stg storage temperature (ambient) ? 65 to +150 c t sol maximum soldering temp. +220 c t j operating junction temperature (2) +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. 3. inputs configured as pci are fully pci compliant. this statemen t takes precedence over any specification that would imply tha t the device is not pci compliant.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 2 ta bl e 2 : recommended operating conditions symbol description min max units v ccint internal supply voltage relative to gnd, t j =0 c to +85 c commercial 1.425 1.575 v internal supply voltage relative to gnd, t j =?40 c to +100 c industrial 1.425 1.575 v v ccaux auxiliary supply voltag e relative to gnd, t j =0 c to +85 c commercial 3.135 3.465 v auxiliary supply voltag e relative to gnd, t j = ?40 c to +100 c industrial 3.135 3.465 v v cco supply voltage relative to gnd, t j =0 c to +85 ccommercial1.23.6v supply voltage relative to gnd, t j =?40 c to +100 c industrial 1.2 3.6 v v batt battery voltage relative to gnd, t j =0 c to +85 ccommercial1.03.6v battery voltage relative to gnd, t j =?40 c to +100 c industrial 1.0 3.6 v notes: 1. if battery is not used, do not connect v batt . 2. recommended maximum voltage droop for v ccaux is 10 mv/ms. 3. the thresholds for power on reset are v ccint > 1.2v, v ccaux > 2.5v, and v cco (bank 4) > 1.5 v. 4. limit the noise at the power s upply to be within 200 mv peak-to-peak. 5. for power bypassing gui delines, see xapp623 at www.xilinx.com . ta bl e 3 : dc characteristics over re commended operating conditions symbol description device min max units v drint data retention v ccint voltage all 1.2 v v dri data retention v ccaux voltage all 2.5 v i ref v ref current per bank all ? 10 +10 a i l input leakage current all ? 10 +10 a c in input capacitance all 10 pf i rpu pad pull-up (when selected) @ v in = 0 v, v cco = 3.3 v (sample tested) all note 1 250 a i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) all note 1 250 a i batt battery supply current all 100 na notes: 1. internal pull-up and pull-down resistors guarantee valid logic le vels at unconnected input pins . these pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 3 power-on power supply requirements xilinx fpgas require a certai n amount of supply current during power-on to insure proper device operation. the actual current consumed depends on the power-on ramp rate of the power supply. the v ccint , v ccaux , and v cco power supplies shall each ramp on no faster than 200 s and no slower than 50 ms. ramp on is defined as: 0 v dc to minimum supply voltages. ta bl e 5 shows the minimum current required by virtex-ii devices for proper power on and configuration. power supplies can be turned on in any sequence. if any v cco bank powers up before v ccaux , then each bank draws up to 300 ma, worst case, until the v ccaux powers on (1) . this does not harm the device. if the current is limited to the minimum value above, or larger, the device powers on properly after all three supplies have passed through their power on reset threshold voltages. once initialized and configured, use the power calculator to estimate current drain on these supplies. notes: 1. the 300 ma is transient current (peak); it eventually disappears even if v ccaux does not power up. ta bl e 4 : quiescent supply current symbol description device min typical max units i ccintq quiescent v ccint supply current xc2v40 xc2v80 xc2v250 xc2v500 xc2v1000 xc2v1500 XC2V2000 xc2v3000 xc2v4000 xc2v6000 xc2v8000 50 50 65 80 100 125 150 200 225 250 300 tbd 125 150 200 250 350 400 500 650 800 1100 ma i ccoq quiescent v cco supply current (1,2) xc2v40 xc2v80 xc2v250 xc2v500 xc2v1000 xc2v1500 XC2V2000 xc2v3000 xc2v4000 xc2v6000 xc2v8000 1 1 1 1 1 2 2 2 2 2 2 tbd 2 2 2 2 4 4 4 4 4 4 ma i ccauxq quiescent v ccaux supply current (1,2) xc2v40 xc2v80 xc2v250 xc2v500 xc2v1000 xc2v1500 XC2V2000 xc2v3000 xc2v4000 xc2v6000 xc2v8000 10 10 10 10 10 15 15 20 20 25 25 tbd 25 25 25 25 50 50 75 75 100 100 ma notes: 1. with no output current loads, no active input pull- up resistors, all i/o pins are 3-state and floating. 2. if dci or differential signaling is used, more accurate values can be obtained by using the power estimator or xpower?. 3. data are retained even if v cco drops to 0 v. 4. values specified for quiescent supply current parameters are commercial grade. for industrial grade values, multiply commerci al grade values by 1.25.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 4 general power s upply requirements proper decoupling of all fpga power supplies is sessential. consult xilinx application note 623 for detailed information on power distribution system design. v ccaux powers critical resources in the fpga. thus, v ccaux is especially susceptible to power supply noise. changes in v ccaux voltage outside of 200 mv peak to peak should take place at a rate no faster than 10 mv per milli- second. techniques to help reduce jitter and period distor- tion are provided in xilinx an swer record 13756, available at www.support.xilinx.com . v ccaux can share a power plane with 3.3v v cco , but only if v cco does not have excessive noise. using simultaneously switching output (sso) limit s are essential for keeping power supply noise to a minimum. (more information on sso is available in xilin x answer record 11713.) dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recom- mended operating conditions at the v ol and v oh test points. only selected standards are tested. these are cho- sen to ensure that all standards meet their specifications. the selected standards are tested at minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 5 : minimum power on current required for virtex-ii devices device (ma) xc2v40, xc2v80, xc2v250, xc2v500 xc2v1000 xc2v1500 XC2V2000 xc2v3000 xc2v4000 xc2v6000 xc2v8000 i ccintmin 200 250 350 400 500 650 800 1100 i ccauxmin 100 100 100 100 100 100 100 100 i ccomin 50 50 100 100 100 100 100 100 notes: 1. values specified for power on current parameters are commercial grade. for industrial grade values, multiply commercial grade values by 1.25. 2. i ccomin values listed here apply to the entire device (all banks). ta bl e 6 : dc input and output levels input/output standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lv t t l (1) ? 0.5 0.8 2.0 3.6 0.4 2.4 24 ? 24 lvcmos33 ? 0.5 0.8 2.0 3.6 0.4 v cco ?0.4 24 ? 24 lvcmos25 ? 0.5 0.7 1.7 2.7 0.4 v cco ?0.4 24 ?24 lvcmos18 ? 0.5 35% v cco 65% v cco 1.95 0.4 v cco ?0.4 16 ?16 lvcmos15 ? 0.5 35% v cco 65% v cco 1.7 0.4 v cco ?0.4 16 ?16 pci33_3 ? 0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco note 2 note 2 pci66_3 ? 0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco note 2 note 2 pci?x ? 0.5 note 2 note 2 note 2 note 2 note 2 note 2 note 2 gtlp ? 0.5 v ref ?0.1 v ref + 0.1 v cco + 0.5 0.6 n/a 36 n/a gtl ? 0.5 v ref ?0.05 v ref + 0.05 v cco + 0.5 0.4 n/a 40 n/a hstl i ? 0.5 v ref ?0.1 v ref + 0.1 v cco + 0.5 0.4 v cco ?0.4 8 ?8 hstl ii ? 0.5 v ref ?0.1 v ref + 0.1 v cco + 0.5 0.4 v cco ?0.4 16 ?16 hstl iii ? 0.5 v ref ?0.1 v ref + 0.1 v cco + 0.5 0.4 v cco ?0.4 24 ?8 hstl iv ? 0.5 v ref ?0.1 v ref + 0.1 v cco + 0.5 0.4 v cco ?0.4 48 ?8 sstl3 i ? 0.5 v ref ?0.2 v ref + 0.2 v cco + 0.5 v ref ?0.6 v ref + 0.6 8 ? 8
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 5 ldt differential signal dc specifications (ldt_25) lvds dc specifications (lvds_33 & lvds_25) sstl3 ii ? 0.5 v ref ?0.2 v ref + 0.2 v cco + 0.5 v ref ?0.8 v ref + 0.8 16 ? 16 sstl2 i ? 0.5 v ref ?0.15 v ref + 0.15 v cco + 0.5 v ref ?0.65 v ref + 0.65 7.6 ? 7.6 sstl2 ii ? 0.5 v ref ?0.15 v ref + 0.15 v cco + 0.5 v ref ?0.80 v ref + 0.80 15.2 ? 15.2 agp ? 0.5 v ref ?0.2 v ref + 0.2 v cco + 0.5 10% v cco 90% v cco note 2 note 2 notes: 1. v ol and v oh for lower drive currents are sample tested. the done pin is always lvttl 12 ma. 2. tested according to the relevant specifications. 3. lvttl and lvcmos inputs have approximately 100 mv of hysteresis. ta bl e 6 : dc input and output levels (continued) input/output standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma ta bl e 7 : ldt dc specifications dc parameter symbol conditions min typ max units differential output voltage v od r t = 100 ? across q and q signals 500 600 700 mv change in v od magnitude ? v od ? 15 15 mv output common mode voltage v ocm r t = 100 ? across q and q signals 560 600 640 mv change in v os magnitude ? v ocm ? 15 15 mv input differential voltage v id 200 600 1000 mv change in v id magnitude ? v id ? 15 15 mv input common mode voltage v icm 500 600 700 mv change in v icm magnitude ? v icm ? 15 15 mv ta bl e 8 : lvds dc specifications dc parameter symbol conditions min typ max units supply voltage v cco 3.3 or 2.5 v output high voltage for q and q v oh r t = 100 ? across q and q signals 1.575 v output low voltage for q and q v ol r t = 100 ? across q and q signals 0.925 v differential output voltage (q ? q ), q = high (q ?q), q = high v odiff r t = 100 ? across q and q signals 250 350 400 mv output common-mode voltage v ocm r t = 100 ? across q and q signals 1.125 1.2 1.375 v differential input voltage (q ? q ), q = high (q ?q), q = high v idiff common-mode input voltage = 1.25 v 100 350 n/a mv input common-mode voltage v icm differential input voltage = 350 mv 0.2 1.25 v cco ? 0.5 v
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 6 extended lvds dc specifications (lvdsext_33 & lvdsext_25) lvpecl dc specifications these values are valid when driving a 100 ? differential load only, i.e., a 100 ? resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. ta b l e 1 0 summarizes the dc output specifications of lvpecl. fo r more information on using lvpecl , see the virtex-ii user guide . ta bl e 9 : extended lvds dc specifications dc parameter symbol conditions min typ max units supply voltage v cco 3.3 or 2.5 v output high voltage for q and q v oh r t = 100 ? across q and q signals 1.785 v output low voltage for q and q v ol r t = 100 ? across q and q signals 0.705 v differential output voltage (q ? q ), q = high (q ?q), q = high v odiff r t = 100 ? across q and q signals 440 820 mv output common-mode voltage v ocm r t = 100 ? across q and q signals 1.125 1.200 1.375 v differential input voltage (q ? q ), q = high (q ?q), q = high v idiff common-mode input voltage = 1.25 v 100 350 n/a mv input common-mode voltage v icm differential input voltage = 350 mv 0.2 1.25 v cco ? 0.5 v ta bl e 1 0 : lvpecl dc specifications dc parameter min max min max min max units v cco 3.0 3.3 3.6 v v oh 1.8 2.11 1.92 2.28 2.13 2.41 v v ol 0.96 1.27 1.06 1.43 1.30 1.57 v v ih 1.49 2.72 1.49 2.72 1.49 2.72 v v il 0.86 2.125 0.86 2.125 0.86 2.125 v differential input voltage 0.3 ? 0.3 ? 0.3 ? v
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 7 virtex-ii performance characteristics this section provides the performance characteristics of some common functions and designs implemented in virtex-ii devices. the numbers reported here are worst-case values; they have all been fully characterized. note that these values are subject to the same guidelines as virtex-ii switching characteristics , page 9 (speed files). ta b l e 1 1 provides pin-to-pin values (in nanoseconds) including iob delays; that is, delay through the device from input pin to output pin. in the case of multiple inputs and out- puts, the worst delay is reported. ta bl e 1 2 shows internal (register-to-register) performance. values are reported in mhz. ta bl e 1 1 : pin-to-pin performance description device used & speed grade pin-to-pin (with i/o delays) units basic functions 16-bit address decoder xc2v1000 ?5 6.3 ns 32-bit address decoder xc2v1000 ?5 7.7 ns 64-bit address decoder xc2v1000 ?5 9.3 ns 4:1 mux xc2v1000 ?5 5.7 ns 8:1 mux xc2v1000 ?5 6.5 ns 16:1 mux xc2v1000 ?5 6.7 ns 32:1 mux xc2v1000 ?5 8.7 ns combinatorial (pad to lut to pad) xc2v1000 ?5 5.0 ns memory block ram pad to setup 1.6 ns clock to pad 9.5 ns distributed ram pad to setup xc2v1000 ?5 2.7 ns clock to pad xc2v1000 ?5 5.1 (no clk skew) ns ta bl e 1 2 : register-to-register performance description device used & speed grade register-to-register performance units basic functions 16-bit address decoder xc2v1000 ?5 398 mhz 32-bit address decoder xc2v1000 ?5 291 mhz 64-bit address decoder xc2v1000 ?5 274 mhz 4:1 mux xc2v1000 ?5 563 mhz 8:1 mux xc2v1000 ?5 454 mhz 16:1 mux xc2v1000 ?5 414 mhz 32:1 mux xc2v1000 ?5 323 mhz register to lut to register xc2v1000 ?5 613 mhz
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 8 8-bit adder xc2v1000 ?5 292 mhz 16-bit adder xc2v1000 ?5 239 mhz 64-bit adder xc2v1000 ?5 114 mhz 64-bit counter xc2v1000 ?5 114 mhz 64-bit accumulator xc2v1000 ?5 110 mhz multiplier 18x18 (with block ram inputs) xc2v1000 ?5 88 mhz multiplier 18x18 (with register inputs) xc2v1000 ?5 105 mhz memory block ram single-port 4096 x 4 bits 278 mhz single-port 2048 x 9 bits 277 mhz single-port 1024 x 18 bits 270 mhz single-port 512 x 36 bits 253 mhz dual-port a:4096 x 4 bits & b:1024 x 18 bits 257 mhz dual-port a:1024 x 18 bits & b:1024 x 18 bits 259 mhz dual-port a:2048 x 9 bits & b: 512 x 36 bits 250 mhz distributed ram single-port 32 x 8-bit xc2v1000 ?5 387 mhz single-port 64 x 8-bit xc2v1000 ?5 335 mhz single-port 128 x 8-bit xc2v1000 ?5 266 mhz dual-port 16 x 8 xc2v1000 ?5 409 mhz dual-port 32 x 8 xc2v1000 ?5 311 mhz dual-port 64 x 8 xc2v1000 ?5 294 mhz shift registers 128-bit srl n/a mhz 256-bit srl n/a mhz fifos (async. in block ram) 1024 x 18-bit read 279 mhz 1024 x 18-bit write 172 mhz fifos (sync. in srl) 128 x 8-bit n/a mhz 128 x 16-bit n/a mhz ta bl e 1 2 : register-to-register performance (continued) description device used & speed grade register-to-register performance units
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 9 virtex-ii switching characteristics switching characteristics in this document are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. note that virtex-ii performance characteristics , page 7 are subject to these guidelines as well. each desi gnation is defined as follows: advance : these speed files are based on simulations only and are typically available soon after device design specifi- cations are frozen. although speed grades with this desig- nation are considered relatively stable and conservative, some under-reporting might still occur. preliminary : these speed files are based on complete es (engineering sample) silicon ch aracterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production : these speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typ- ically, the slowest speed grades transition to production before faster speed grades. since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. ta bl e 1 3 correlates the current status of each virtex-ii device with a corresponding speed grade designa- tion. all specifications are always representative of worst-case supply voltage and junction temperature conditions. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test pat- terns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by t he xilinx static timing analyzer and back-annotate to the simulation net list. unless other- wise noted, values apply to all virtex-ii devices. iob input switching characteristics input delays associated with the pad are specified for lvttl levels. for other standards, adjust the delays with the values shown in iob input switching characteristics standard adjustments , page 11 . table 13: virtex-ii device speed grade designations device speed grade designations advance preliminary production xc2v40 ?6, ?5, ?4 xc2v80 ?6, ?5, ?4 xc2v250 ?6, ?5, ?4 xc2v500 ?6, ?5, ?4 xc2v1000 ?6, ?5, ?4 xc2v1500 ?6, ?5, ?4 XC2V2000 ?6, ?5, ?4 xc2v3000 ?6, ?5, ?4 xc2v4000 ?6, ?5, ?4 xc2v6000 ?6, ?5, ?4 xc2v8000 ?6, ?5, ?4 ta bl e 1 4 : iob input switching characteristics speed grade units description symbol device ?6 ?5 ?4 propagation delays pad to i output, no delay t iopi all 0.69 0.76 0.88 ns, max pad to i output, with delay t iopid xc2v40 1.92 2.11 2.43 ns, max xc2v80 1.92 2.11 2.43 ns, max xc2v250 1.92 2.11 2.43 ns, max xc2v500 1.92 2.11 2.43 ns, max xc2v1000 1.92 2.11 2.43 ns, max xc2v1500 1.92 2.11 2.43 ns, max XC2V2000 1.92 2.11 2.43 ns, max xc2v3000 1.97 2.16 2.49 ns, max xc2v4000 1.97 2.16 2.49 ns, max xc2v6000 2.10 2.31 2.66 ns, max xc2v8000 2.10 2.31 2.66 ns, max
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 10 propagation delays pad to output iq via transparent latch, no delay t iopli all 0.83 0.91 1.05 ns, max pad to output iq via transparent latch, with delay t ioplid xc2v40 3.23 3.55 4.09 ns, max xc2v80 3.23 3.55 4.09 ns, max xc2v250 3.23 3.55 4.09 ns, max xc2v500 3.23 3.55 4.09 ns, max xc2v1000 3.23 3.55 4.09 ns, max xc2v1500 3.23 3.55 4.09 ns, max XC2V2000 3.23 3.55 4.09 ns, max xc2v3000 3.32 3.65 4.20 ns, max xc2v4000 3.32 3.65 4.20 ns, max xc2v6000 3.60 3.95 4.55 ns, max xc2v8000 3.60 3.95 4.55 ns, max clock clk to output iq t iockiq all 0.61 0.67 0.77 ns, max setup and hold times with respect to clock at iob input register pad, no delay t iopick /t ioickp all 0.84/?0.36 0.92/? 0.39 1.06/?0.45 ns, min pad, with delay t iopickd /t ioickpd xc2v40 3.24/?2.04 3.57/? 2.24 4.10/?2.58 ns, min xc2v80 3.24/?2.04 3.57/? 2.24 4.10/?2.58 ns, min xc2v250 3.24/?2.04 3.57/? 2.24 4.10/?2.58 ns, min xc2v500 3.24/?2.04 3.57/? 2.24 4.10/?2.58 ns, min xc2v1000 3.24/?2.04 3.57/? 2.24 4.10/?2.58 ns, min xc2v1500 3.24/?2.04 3.57/? 2.24 4.10/?2.58 ns, min XC2V2000 3.24/?2.04 3.57/? 2.24 4.10/?2.58 ns, min xc2v3000 3.33/?2.10 3.67/? 2.31 4.22/?2.66 ns, min xc2v4000 3.33/?2.10 3.67/? 2.31 4.22/?2.66 ns, min xc2v6000 3.61/?2.29 3.97/? 2.52 4.56/?2.90 ns, min xc2v8000 3.61/?2.29 3.97/? 2.52 4.56/?2.90 ns, min ice input t ioiceck /t iockice all 0.19/ 0.03 0.21/ 0. 04 0.24/ 0.04 ns, min sr input (iff, synchronous) t iosrcki all 0.27 0.30 0.34 ns, min set/reset delays sr input to iq (asynchronous) t iosriq all 1.11 1.22 1.40 ns, max gsr to output iq t gsrq all 5.44 5.98 6.88 ns, max notes: 1. input timing for lvttl is measured at 1.4 v. for other i/o standards, see ta bl e 1 8 . ta bl e 1 4 : iob input switching characteristics (continued) speed grade units description symbol device ?6 ?5 ?4
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 11 iob input switching character istics standard adjustments ta bl e 1 5 : iob input switching characteristics standard adjustments speed grade description symbol standard ? 6 ? 5 ? 4units data input delay adjustments standard-specific data input delay adjustments t ilvttl lv t t l 0.00 0.00 0.00 ns t ilvcmos33 lv c m o s 3 3 0.00 0.00 0.00 ns t ilvcmos25 lv c m o s 2 5 0.11 0.11 0.12 ns t ilvcmos18 lv c m o s 1 8 0.42 0.43 0.49 ns t ilvcmos15 lv c m o s 1 5 0.98 1.00 1.15 ns t ilvds_25 lvds_25 0.60 0.60 0.69 ns t ilvds_33 lvds_33 0.60 0.60 0.69 ns t ilvpecl_33 lvpecl 0.60 0.60 0.69 ns t ipci33_3 pci, 33 mhz, 3.3 v 0.00 0.00 0.00 ns t ipci66_3 pci, 66 mhz, 3.3 v 0.00 0.00 0.00 ns t ipcix pci ? x, 133 mhz, 3.3 v 0.00 0.00 0.00 ns t igtl gtl 0.42 0.42 0.48 ns t igtlp gtlp 0.42 0.42 0.48 ns t ihstl_i hstl i 0.42 0.42 0.48 ns t ihstl_ii hstl ii 0.42 0.42 0.48 ns t ihstl_iii hstl iii 0.42 0.42 0.48 ns t ihstl_iv hstl iv 0.42 0.42 0.48 ns t ihstl_i_18 hstl i_18 0.42 0.42 0.48 ns t ihstl_ii_18 hstl ii_18 0.42 0.42 0.48 ns t ihstl_iii_18 hstl iii_18 0.42 0.42 0.48 ns t ihstl_iv_18 hstl iv_18 0.42 0.42 0.48 ns t isstl2_i sstl2 i 0.42 0.42 0.48 ns t isstl2_ii sstl2 ii 0.42 0.42 0.48 ns t isstl3_i sstl3 i 0.35 0.35 0.40 ns t isstl3_ii sstl3 ii 0.35 0.35 0.40 ns t iagp agp 0.35 0.35 0.40 ns t ilvdci_33 lv d c i _ 3 3 0.00 0.00 0.00 ns t ilvdci_25 lv d c i _ 2 5 0.11 0.11 0.12 ns t ilvdci_18 lv d c i _ 1 8 0.42 0.43 0.49 ns
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 12 t ilvdci_15 lv d c i _ 1 5 0.98 1.00 1.14 ns t ilvdci_dv2_33 lvdci_dv2_33 0.00 0.00 0.00 ns t ilvdci_dv2_25 lvdci_dv2_25 0.11 0.11 0.12 ns t ilvdci_dv2_18 lvdci_dv2_18 0.42 0.43 0.49 ns t ilvdci_dv2_15 lvdci_dv2_15 0.98 1.00 1.14 ns t igtl_dci gtl_dci 0.42 0.42 0.48 ns t igtlp_dci gtlp_dci 0.42 0.42 0.48 ns t ihstl_i_dci hstl_i_dci 0.42 0.42 0.48 ns t ihstl_ii_dci hstl_ii_dci 0.42 0.42 0.48 ns t ihstl_iii_dci hstl_iii_dci 0.42 0.42 0.48 ns t ihstl_iv_dci hstl_iv_dci 0.42 0.42 0.48 ns t ihstl_i_dci_18 hstl_i_dci_18 0.42 0.42 0.48 ns t ihstl_ii_dci_18 hstl_ii_dci_18 0.42 0.42 0.48 ns t ihstl_iii_dci_18 hstl_iii_dci_18 0.42 0.42 0.48 ns t ihstl_iv_dci_18 hstl_iv_dci_18 0.42 0.42 0.48 ns t isstl2_i_dci sstl2_i_dci 0.42 0.42 0.48 ns t isstl2_ii_dci sstl2_ii_dci 0.42 0.42 0.48 ns t isstl3_i_dci sstl3_i_dci 0.35 0.35 0.40 ns t isstl3_ii_dci sstl3_ii_dci 0.35 0.35 0.40 ns t ildt_25 ldt_25 0.48 0.49 0.56 ns t iulvds_25 ulvds_25 0.48 0.49 0.56 ns notes: 1. input timing for lvttl is measured at 1.4 v. for other i/o standards, see ta bl e 1 8 . ta bl e 1 5 : iob input switching characteristics standard adjustments (continued) speed grade description symbol standard ? 6 ? 5 ? 4units
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 13 iob output switchin g characteristics output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays with the values shown in iob output switching characteristics standard adjustments , page 14 . ta bl e 1 6 : iob output switching characteristics speed grade description symbol ? 6 ? 5 ? 4units propagation delays o input to pad t ioop 1.43 1.51 1.74 ns, max o input to pad via transparent latch t ioolp 1.72 1.83 2.11 ns, max 3-state delays t input to pad high-impedance (1) t iothz 0.51 0.56 0.64 ns, max t input to valid data on pad t iotp 1.38 1.45 1.67 ns, max t input to pad high-impedance via transparent latch (1) t iotlphz 0.80 0.88 1.01 ns, max t input to valid data on pad via transparent latch t iotlpon 1.67 1.77 2.04 ns, max gts to pad high impedance (1) t gts 4.73 5.20 5.98 ns, max sequential delays clock clk to pad t iockp 1.76 1.87 2.15 ns, max clock clk to pad high-impedance (synchronous) (1) t iockhz 0.95 1.04 1.20 ns, max clock clk to valid data on pad (synchronous) t iockon 1.82 1.94 2.22 ns, max setup and hold times before/after clock clk o input t ioock /t iocko 0.31/?0.08 0.34/? 0.09 0.39/?0.11 ns, min oce input t iooceck /t iockoce 0.19/?0.06 0.21/? 0.07 0.24/?0.08 ns, min sr input (off) t iosrcko /t iockosr 0.27/?0.05 0.30/? 0.06 0.34/?0.07 ns, min 3 ? state setup times, t input t iotck /t iockt 0.28/?0.06 0.31/? 0.07 0.35/?0.08 ns, min 3 ? state setup times, tce input t iotceck /t iocktce 0.19/?0.06 0.21/? 0.07 0.24/?0.08 ns, min 3 ? state setup times, sr input (tff) t iosrckt /t iocktsr 0.27/?0.05 0.30/? 0.06 0.34/?0.07 ns, min set/reset delays sr input to pad (asynchronous) t iosrp 2.41 2.59 2.98 ns, max sr input to pad high-impedance (asynchronous) (1) t iosrhz 1.52 1.67 1.92 ns, max sr input to valid data on pad (asynchronous) t iosron 2.39 2.56 2.95 ns, max gsr to pad t iogsrq 5.44 5.98 6.88 ns, max notes: 1. the 3-state turn-off delays should not be adjusted.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 14 iob output switching charac teristics standard adjustments output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays by the values shown. ta bl e 1 7 : iob output switching characteristics standard adjustments speed grade description symbol standard ?6 ?5 ?4 units output delay adjustments standard-specific adj ustments for output delays terminating at pads (based on standard capacitive load, csl) t olvttl_s2 lvttl, slow, 2 ma 9.42 9.71 10.68 ns t olvttl_s4 4 ma 5.77 5.95 6.55 ns t olvttl_s6 6 ma 4.11 4.24 4.66 ns t olvttl_s8 8 ma 2.87 2.96 3.26 ns t olvttl_s12 12 ma 2.32 2.39 2.63 ns t olvttl_s16 16 ma 1.70 1.75 1.93 ns t olvttl_s24 24 ma 1.26 1.30 1.43 ns t olvttl_f2 lvttl, fast, 2 ma 6.52 6.72 7.39 ns t olvttl_f4 4 ma 2.80 2.88 3.17 ns t olvttl_f6 6 ma 1.57 1.62 1.78 ns t olvttl_f8 8 ma 0.46 0.48 0.52 ns t olvttl_f12 12 ma 0.00 0.00 0.00 ns t olvttl_f16 16 ma ?0.13 ?0.14 ?0.15 ns t olvttl_f24 24 ma ?0.22 ?0.23 ?0.26 ns t olvds_25 lvds ?0.31 ?0.32 ?0.36 ns t olvds_33 lvds ?0.25 ?0.26 ?0.29 ns t olvdsext_25 lvds ?0.18 ?0.19 ?0.21 ns t olvdsext_33 lvds ?0.17 ?0.18 ?0.19 ns t oldt_25 ldt ?0.20 ?0.21 ?0.23 ns t oblvds_25 blvds 0.67 0.69 0.76 ns t oulvds_25 ulvds ?0.20 ?0.21 ?0.23 ns t olvpecl_33 lvpecl 0.29 0.30 0.33 ns t opci33_3 pci, 33 mhz, 3.3 v 1.15 1.19 1.31 ns t opci66_3 pci, 66 mhz, 3.3 v ?0.01 ?0.01 ?0.01 ns t opcix pci?x, 133 mhz, 3.3 v ?0.01 ?0.01 ?0.01 ns t ogtl gtl ?0.31 ?0.32 ?0.36 ns t ogtlp gtlp ?0.17 ?0.18 ?0.20 ns t ohstl_i hstl i 0.26 0.27 0.29 ns t ohstl_ii hstl ii ?0.15 ?0.16 ?0.17 ns t ohstl_iii hstl iii ?0.17 ?0.17 ?0.19 ns t ohstl_iv hstl iv ?0.40 ?0.41 ?0.45 ns t ohstl_i_18 hstl i_18 0.03 0.03 0.04 ns t ohstl_ii_18 hstl ii_18 ?0.17 ?0.18 ?0.20 ns t ohstl_iii_18 hstl iii_18 ?0.16 ?0.16 ?0.18 ns t ohstl_iv_18 hstl iv_18 ?0.39 ?0.40 ?0.44 ns
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 15 t osstl2_i sstl2 i 0.21 0.22 0.24 ns t osstl2_ii sstl2 ii ?0.15 ?0.16 ?0.18 ns t osstl3_i sstl3 i 0.29 0.30 0.33 ns t osstl3_ii sstl3 ii ?0.05 ?0.05 ?0.05 ns t oagp agp ?0.27 ?0.28 ?0.31 ns t olvcmos33_s2 lvcmos33, slow, 2 ma 7.67 7.91 8.70 ns t olvcmos33_s4 4 ma 4.37 4.50 4.95 ns t olvcmos33_s6 6 ma 3.34 3.44 3.78 ns t olvcmos33_s8 8 ma 2.29 2.36 2.60 ns t olvcmos33_s12 12 ma 1.91 1.97 2.16 ns t olvcmos33_s16 16 ma 1.24 1.27 1.40 ns t olvcmos33_s24 24 ma 1.18 1.22 1.34 ns t olvcmos33_f2 lvcmos33, fast, 2 ma 5.82 6.00 6.60 ns t olvcmos33_f4 4 ma 2.48 2.55 2.81 ns t olvcmos33_f6 6 ma 1.28 1.31 1.45 ns t olvcmos33_f8 8 ma 0.48 0.49 0.54 ns t olvcmos33_f12 12 ma 0.27 0.28 0.31 ns t olvcmos33_f16 16 ma ?0.14 ?0.14 ?0.15 ns t olvcmos33_f24 24 ma ?0.21 ?0.21 ?0.23 ns t olvcmos25_s2 lvcmos25, slow, 2 ma 9.11 9.39 10.33 ns t olvcmos25_s4 4 ma 5.00 5.16 5.67 ns t olvcmos25_s6 6 ma 4.53 4.67 5.13 ns t olvcmos25_s8 8 ma 3.86 3.98 4.38 ns t olvcmos25_s12 12 ma 2.84 2.93 3.22 ns t olvcmos25_s16 16 ma 2.36 2.43 2.67 ns t olvcmos25_s24 24 ma 2.00 2.06 2.27 ns t olvcmos25_f2 lvcmos25, fast, 2 ma 4.06 4.18 4.60 ns t olvcmos25_f4 4 ma 1.15 1.18 1.30 ns t olvcmos25_f6 6 ma 0.72 0.74 0.81 ns t olvcmos25_f8 8 ma 0.33 0.34 0.37 ns t olvcmos25_f12 12 ma 0.02 0.02 0.03 ns t olvcmos25_f16 16 ma ?0.18 ?0.19 ?0.21 ns t olvcmos25_f24 24 ma ?0.35 ?0.36 ?0.40 ns t olvcmos18_s2 lvcmos18, slow, 2 ma 15.62 16.10 17.71 ns t olvcmos18_s4 4 ma 10.20 10.51 11.57 ns t olvcmos18_s6 6 ma 7.52 7.75 8.53 ns t olvcmos18_s8 8 ma 6.87 7.08 7.78 ns t olvcmos18_s12 12 ma 5.54 5.71 6.28 ns t olvcmos18_s16 16 ma 5.31 5.47 6.02 ns t olvcmos18_f2 lvcmos18, fast, 2 ma 5.55 5.72 6.30 ns ta bl e 1 7 : iob output switching characteristics standard adjustments (continued) speed grade description symbol standard ?6 ?5 ?4 units
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 16 t olvcmos18_f4 4 ma 1.89 1.95 2.15 ns t olvcmos18_f6 6 ma 0.83 0.85 0.94 ns t olvcmos18_f8 8 ma 0.70 0.72 0.80 ns t olvcmos18_f12 12 ma 0.26 0.27 0.30 ns t olvcmos18_f16 16 ma 0.23 0.23 0.26 ns t olvcmos15_s2 lvcmos15, slow, 2 ma 18.96 19.55 21.50 ns t olvcmos15_s4 4 ma 12.77 13.17 14.48 ns t olvcmos15_s6 6 ma 12.05 12.42 13.66 ns t olvcmos15_s8 8 ma 9.75 10.06 11.06 ns t olvcmos15_s12 12 ma 9.04 9.32 10.25 ns t olvcmos15_s16 16 ma 8.21 8.46 9.31 ns t olvcmos15_f2 lvcmos15, fast, 2 ma 5.09 5.25 5.78 ns t olvcmos15_f4 4 ma 2.01 2.07 2.27 ns t olvcmos15_f6 6 ma 1.46 1.51 1.66 ns t olvcmos15_f8 8 ma 0.93 0.96 1.05 ns t olvcmos15_f12 12 ma 0.74 0.77 0.84 ns t olvcmos15_f16 16 ma 0.67 0.69 0.75 ns t olvdci_33 lvdci_33 0.74 0.77 0.84 ns t olvdci_25 lvdci_25 0.78 0.80 0.88 ns t olvdci_18 lvdci_18 0.84 0.87 0.95 ns t olvdci_15 lvdci_15 1.82 1.88 2.06 ns t olvdci_dv2_33 lvdci_dv2_33 0.12 0.12 0.13 ns t olvdci_dv2_25 lvdci_dv2_25 0.03 0.03 0.03 ns t olvdci_dv2_18 lvdci_dv2_18 0.42 0.43 0.48 ns t olvdci_dv2_15 lvdci_dv2_15 1.20 1.23 1.36 ns t ogtl_dci gtl_dci ?0.31 ?0.32 ?0.35 ns t ogtlp_dci gtlp_dci ?0.15 ?0.16 ?0.17 ns t ohstl_i_dci hstl_i_dci 0.23 0.23 0.26 ns t ohstl_ii_dci hstl_ii_dci 0.06 0.06 0.07 ns t ohstl_iii_dci hstl_iii_dci ?0.17 ?0.18 ?0.20 ns t ohstl_iv_dci hstl_iv_dci ?0.46 ?0.47 ?0.52 ns t ohstl_i_dci_18 hstl_i_dci_18 0.05 0.05 0.06 ns t ohstl_ii_dci_18 hstl_ii_dci_18 ?0.03 ?0.03 ?0.03 ns t ohstl_iii_dci_18 hstl_iii_dci_18 ?0.14 ?0.14 ?0.16 ns t ohstl_iv_dci_18 hstl_iv_dci_18 ?0.41 ?0.42 ?0.47 ns t osstl2_i_dci sstl2_i_dci 0.12 0.13 0.14 ns t osstl2_ii_dci sstl2_ii_dci ?0.10 ?0.10 ?0.11 ns t osstl3_i_dci sstl3_i_dci 0.15 0.16 0.17 ns t osstl3_ii_dci sstl3_ii_dci 0.08 0.08 0.09 ns ta bl e 1 7 : iob output switching characteristics standard adjustments (continued) speed grade description symbol standard ?6 ?5 ?4 units
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 17 ta bl e 1 8 : delay measurement methodology standard v l (1) v h (1) meas. point v ref (typ) (2) lv t t l 0 3 1 . 4 ? lvcmos33 0 3.3 1.65 ? lvcmos25 0 2.5 1.25 ? lv c m o s 1 8 0 1 . 8 0 . 9 ? lvcmos15 0 1.5 0.75 ? pci33_3 per pci specification ? pci66_3 per pci specification ? pcix33_3 per pci?x specification ? gtl v ref ?0.2 v ref +0.2 v ref 0.80 gtlp v ref ?0.2 v ref +0.2 v ref 1.0 hstl class i v ref ?0.5 v ref +0.5 v ref 0.75 hstl class ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl class iii v ref ?0.5 v ref +0.5 v ref 0.90 hstl class iv v ref ?0.5 v ref +0.5 v ref 0.90 sstl3 i & ii v ref ?1.0 v ref +1.0 v ref 1.5 sstl2 i & ii v ref ?0.75 v ref +0.75 v ref 1.25 agp v ref ? (0.2xv cco )v ref + (0.2xv cco )v ref per agp spec lvds_25 1.2 ? 0.125 1.2 + 0.125 1.2 lvds_33 1.2 ? 0.125 1.2 + 0.125 1.2 lvdsext_25 1.2 ? 0.125 1.2 + 0.125 1.2 lvdsext_33 1.2 ? 0.125 1.2 + 0.125 1.2 ulvds_25 0.6 ? 0.125 0.6 + 0.125 0.6 ldt_25 0.6 ? 0.125 0.6 + 0.125 0.6 lvpecl 1.6 ?0.3 1.6 + 0.3 1.6 notes: 1. input waveform switches between v l and v h . 2. measurements are made at v ref (typ), maximum, and minimum. worst-case values are reported.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 18 i/o standard adjustment me asurement methodology i/o standard adjustments are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4" of fr4 microstrip transmission line. the propogation delay for the 4" of fr4 is characterized separately and subtracted from the final measurement. i/o standard adjustment measurements are reflected in the ibis model except where the ibis format precludes it. the use of ibis models results in a more accurate prediction of the propagation delay. the following method may be used to measure propogation delay: 1. model the output in an ibis simulation using the generalized test setup shown in figure 1 . 2. record the relative time to the v oh or v ol transition of interest. this is th e baseline simulation. 3. model the actual pcb traces (transmission lines) and actual loads from the appropriate ibis models for the driven devices. 4. record the results from the new simulation 5. compare with the baseline simulation. the increase or decrease in delay from the baseline simulation should be added or subtracted to the i/o output standard adjustment value to predict the actual propogation delay. figure 1: generalized test setup fpga scope 4" 50 ? microstrip transmission line r t ** r t * ds083-3_06_072403 * terminations are on board and are configured per the user guide.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 19 clock distribution swit ching characteristics clb switching characteristics delays originating at f/g inputs vary s lightly according to the input used (see figure 16 in module 2). the values listed below are worst-case. precise values are provided by the timing analyzer. ta bl e 1 9 : clock distribution switching characteristics description symbol speed grade units ? 6 ? 5 ? 4 global clock buffer i input to o output t gio 0.47 0.52 0.59 ns, max ta bl e 2 0 : clb switching characteristics description symbol speed grade units ? 6 ? 5 ? 4 combinatorial delays 4-input function: f/g inputs to x/y outputs t ilo 0.35 0.39 0.44 ns, max 5-input function: f/g inputs to f5 output t if5 0.57 0.63 0.72 ns, max 5-input function: f/g inputs to x output t if5x 0.76 0.83 0.95 ns, max fxina or fxinb inputs to y output via muxfx t ifxy 0.36 0.39 0.45 ns, max fxina input to fx output via muxfx t inafx 0.26 0.28 0.32 ns, max fxinb input to fx output via muxfx t inbfx 0.26 0.28 0.32 ns, max sopin input to sopout output via orcy t sopsop 0.35 0.38 0.44 ns, max incremental delay routing through transparent latch to xq/yq outputs t ifnctl 0.41 0.45 0.51 ns, max sequential delays ff clock clk to xq/yq outputs t cko 0.45 0.50 0.57 ns, max latch clock clk to xq/yq outputs t cklo 0.54 0.59 0.68 ns, max setup and hold times before/after clock clk bx/by inputs t dick /t ckdi 0.30/?0.07 0.33/?0.08 0.37/?0.09 ns, min dy inputs t dyck /t ckdy 0.30/?0.07 0.33/?0.08 0.37/?0.09 ns, min dx inputs t dxck /t ckdx 0.30/?0.07 0.33/?0.08 0.37/?0.09 ns, min ce input t ceck /t ckce 0.19/?0.06 0.21/?0.07 0.24/?0.08 ns, min sr/by inputs (synchronous) t srck/ t sckr 0.21/?0.02 0.23/?0.03 0.26/?0.03 ns, min clock clk minimum pulse width, high t ch 0.61 0.67 0.77 ns, min minimum pulse width, low t cl 0.61 0.67 0.77 ns, min set/reset minimum pulse width, sr/by inputs t rpw 0.61 0.67 0.77 ns, min delay from sr/by inputs to xq/yq outputs (asynchronous) t rq 1.06 1.17 1.34 ns, max toggle frequency (mhz) (for export control) f tog 820 750 650 mhz
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 20 clb distributed ram sw itching characteristics clb shift register swit ching characteristics ta bl e 2 1 : clb distributed ram swit ching characteristics description symbol speed grade units ? 6 ? 5 ? 4 sequential delays clock clk to x/y outputs (we active) in 16 x 1 mode t shcko16 1.63 1.79 2.05 ns, max clock clk to x/y outputs (we active) in 32 x 1 mode t shcko32 1.97 2.17 2.49 ns, max clock clk to f5 output t shckof5 1.77 1.94 2.23 ns, max setup and hold times before/after clock clk bx/by data inputs (din) t ds /t dh 0.53/?0.09 0.58/ ?0.10 0.67/?0.11 ns, min f/g address inputs t as /t ah 0.40/ 0.00 0.44/ 0.00 0.50/ 0.00 ns, min sr input (ws) t wes /t weh 0.42/?0.01 0.46/ ?0.01 0.53/?0.01 ns, min clock clk minimum pulse width, high t wph 0.57 0.63 0.72 ns, min minimum pulse width, low t wpl 0.57 0.63 0.72 ns, min minimum clock period to meet address write cycle time t wc 1.14 1.25 1.44 ns, min ta bl e 2 2 : clb shift register swit ching characteristics description symbol speed grade units ? 6 ? 5 ? 4 sequential delays clock clk to x/y outputs t reg 2.31 2.54 2.92 ns, max clock clk to x/y outputs t reg32 2.65 2.92 3.35 ns, max clock clk to xb output via mc15 lut output t regxb 2.23 2.46 2.82 ns, max clock clk to yb output via mc15 lut output t regyb 2.18 2.40 2.75 ns, max clock clk to shiftout t cksh 1.92 2.11 2.43 ns, max clock clk to f5 output t regf5 2.45 2.69 3.09 ns, max setup and hold times before/after clock clk bx/by data inputs (din) t srlds /t srldh 0.53/?0.07 0.58/ ?0.08 0.67/?0.09 ns, min sr input (ws) t wss /t wsh 0.19/?0.06 0.21/ ?0.07 0.24/?0.08 ns, min clock clk minimum pulse width, high t srph 0.57 0.63 0.72 ns, min minimum pulse width, low t srpl 0.57 0.63 0.72 ns, min
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 21 multiplier switching characteristics ta bl e 2 3 : multiplier switching characteristics description symbol speed grade units ? 6 ? 5 ? 4 propagation delay to output pin input to pin 35 t mult_p35 4.66 8.50 10.36 ns, max input to pin 34 t mult_p34 4.57 8.33 10.15 ns, max input to pin 33 t mult_p33 4.47 8.16 9.95 ns, max input to pin 32 t mult_p32 4.37 7.99 9.74 ns, max input to pin 31 t mult_p31 4.28 7.82 9.53 ns, max input to pin 30 t mult_p30 4.18 7.65 9.33 ns, max input to pin 29 t mult_p29 4.08 7.48 9.12 ns, max input to pin 28 t mult_p28 3.99 7.31 8.91 ns, max input to pin 27 t mult_p27 3.89 7.14 8.70 ns, max input to pin 26 t mult_p26 3.79 6.97 8.50 ns, max input to pin 25 t mult_p25 3.69 6.80 8.29 ns, max input to pin 24 t mult_p24 3.60 6.63 8.08 ns, max input to pin 23 t mult_p23 3.50 6.46 7.88 ns, max input to pin 22 t mult_p22 3.40 6.29 7.67 ns, max input to pin 21 t mult_p21 3.31 6.12 7.46 ns, max input to pin 20 t mult_p20 3.21 5.95 7.26 ns, max input to pin 19 t mult_p19 3.11 5.78 7.05 ns, max input to pin 18 t mult_p18 3.02 5.61 6.84 ns, max input to pin 17 t mult_p17 2.92 5.44 6.63 ns, max input to pin 16 t mult_p16 2.82 5.27 6.43 ns, max input to pin 15 t mult_p15 2.72 5.10 6.22 ns, max input to pin 14 t mult_p14 2.63 4.93 6.01 ns, max input to pin 13 t mult_p13 2.53 4.76 5.81 ns, max input to pin 12 t mult_p12 2.43 4.59 5.60 ns, max input to pin 11 t mult_p11 2.34 4.42 5.39 ns, max input to pin 10 t mult_p10 2.24 4.25 5.19 ns, max input to pin 9 t mult_p9 2.14 4.08 4.98 ns, max input to pin 8 t mult_p8 2.05 3.91 4.77 ns, max input to pin 7 t mult_p7 1.95 3.74 4.56 ns, max input to pin 6 t mult_p6 1.85 3.57 4.36 ns, max input to pin 5 t mult_p5 1.75 3.40 4.15 ns, max input to pin 4 t mult_p4 1.66 3.23 3.94 ns, max input to pin 3 t mult_p3 1.56 3.06 3.74 ns, max input to pin 2 t mult_p2 1.46 2.89 3.53 ns, max input to pin 1 t mult_p1 1.37 2.72 3.32 ns, max input to pin 0 t mult_p0 1.27 2.55 3.12 ns, max
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 22 ta bl e 2 4 : pipelined multiplier switching characteristics description symbol speed grade units ?6 ?5 ?4 setup and hold times before/after clock data inputs t mulidck /t mulckid 3.00/ 0.00 3.45/ 0.00 3.89/ 0.00 ns, max clock enable t mulidck_ce /t mulckid_ce 0.72/ 0.00 0.80/ 0.00 0.86/ 0.00 ns, max reset t mulidck_rst /t mulckid_rst 0.72/ 0.00 0.80/ 0.00 0.86/ 0.00 ns, max clock to output pin clock to pin 35 t multck_p35 3.05 6.91 8.12 ns, max clock to pin 34 t multck_p34 2.95 6.75 7.93 ns, max clock to pin 33 t multck_p33 2.85 6.59 7.74 ns, max clock to pin 32 t multck_p32 2.76 6.43 7.56 ns, max clock to pin 31 t multck_p31 2.66 6.27 7.37 ns, max clock to pin 30 t multck_p30 2.56 6.11 7.19 ns, max clock to pin 29 t multck_p29 2.47 5.95 7.00 ns, max clock to pin 28 t multck_p28 2.37 5.79 6.81 ns, max clock to pin 27 t multck_p27 2.27 5.63 6.63 ns, max clock to pin 26 t multck_p26 2.17 5.47 6.44 ns, max clock to pin 25 t multck_p25 2.08 5.31 6.26 ns, max clock to pin 24 t multck_p24 1.98 5.15 6.07 ns, max clock to pin 23 t multck_p23 1.88 4.99 5.88 ns, max clock to pin 22 t multck_p22 1.79 4.83 5.70 ns, max clock to pin 21 t multck_p21 1.69 4.67 5.51 ns, max clock to pin 20 t multck_p20 1.59 4.51 5.33 ns, max clock to pin 19 t multck_p19 1.50 4.35 5.14 ns, max clock to pin 18 t multck_p18 1.40 4.19 4.95 ns, max clock to pin 17 t multck_p17 1.30 4.03 4.77 ns, max clock to pin 16 t multck_p16 1.20 3.87 4.58 ns, max clock to pin 15 t multck_p15 1.11 3.71 4.40 ns, max clock to pin 14 t multck_p14 1.01 3.55 4.21 ns, max clock to pin 13 t multck_p13 0.91 3.39 4.02 ns, max clock to pin 12 t multck_p12 0.91 3.23 3.84 ns, max clock to pin 11 t multck_p11 0.91 3.07 3.65 ns, max clock to pin 10 t multck_p10 0.91 2.91 3.47 ns, max clock to pin 9 t multck_p9 0.91 2.75 3.28 ns, max clock to pin 8 t multck_p8 0.91 2.59 3.09 ns, max clock to pin 7 t multck_p7 0.91 2.43 2.91 ns, max clock to pin 6 t multck_p6 0.91 2.27 2.72 ns, max clock to pin 5 t multck_p5 0.91 2.11 2.54 ns, max clock to pin 4 t multck_p4 0.91 1.95 2.35 ns, max clock to pin 3 t multck_p3 0.91 1.79 2.16 ns, max clock to pin 2 t multck_p2 0.91 1.63 1.98 ns, max clock to pin 1 t multck_p1 0.91 1.47 1.79 ns, max clock to pin 0 t multck_p0 0.91 1.31 1.61 ns, max
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 23 enhanced multiplier swit ching characteristics ta bl e 2 5 and ta b l e 2 6 provide timing information for enhanced virtex-ii multiplier blocks, available in stepping revisions of virtex-ii devices. for more information on stepping revisions, availability, and ordering inst ructions, see your local sales representative. ta bl e 2 5 : enhanced multiplier switching characteristics description symbol speed grade units ?6 ?5 ?4 propagation delay to output pin input to pin 35 t mult1_p35 4.66 5.14 5.91 ns, max input to pin 34 t mult1_p34 4.57 5.03 5.79 ns, max input to pin 33 t mult1_p33 4.47 4.93 5.66 ns, max input to pin 32 t mult1_p32 4.37 4.82 5.54 ns, max input to pin 31 t mult1_p31 4.28 4.71 5.42 ns, max input to pin 30 t mult1_p30 4.18 4.61 5.29 ns, max input to pin 29 t mult1_p29 4.08 4.50 5.17 ns, max input to pin 28 t mult1_p28 3.99 4.39 5.05 ns, max input to pin 27 t mult1_p27 3.89 4.28 4.92 ns, max input to pin 26 t mult1_p26 3.79 4.18 4.80 ns, max input to pin 25 t mult1_p25 3.69 4.07 4.68 ns, max input to pin 24 t mult1_p24 3.60 3.96 4.56 ns, max input to pin 23 t mult1_p23 3.50 3.86 4.43 ns, max input to pin 22 t mult1_p22 3.40 3.75 4.31 ns, max input to pin 21 t mult1_p21 3.31 3.64 4.19 ns, max input to pin 20 t mult1_p20 3.21 3.54 4.06 ns, max input to pin 19 t mult1_p19 3.11 3.43 3.94 ns, max input to pin 18 t mult1_p18 3.02 3.32 3.82 ns, max input to pin 17 t mult1_p17 2.92 3.21 3.69 ns, max input to pin 16 t mult1_p16 2.82 3.11 3.57 ns, max input to pin 15 t mult1_p15 2.72 3.00 3.45 ns, max input to pin 14 t mult1_p14 2.63 2.89 3.33 ns, max input to pin 13 t mult1_p13 2.53 2.79 3.20 ns, max input to pin 12 t mult1_p12 2.43 2.68 3.08 ns, max input to pin 11 t mult1_p11 2.34 2.57 2.96 ns, max input to pin 10 t mult1_p10 2.24 2.47 2.83 ns, max input to pin 9 t mult1_p9 2.14 2.36 2.71 ns, max input to pin 8 t mult1_p8 2.05 2.25 2.59 ns, max input to pin 7 t mult1_p7 1.95 2.14 2.46 ns, max input to pin 6 t mult1_p6 1.85 2.04 2.34 ns, max input to pin 5 t mult1_p5 1.75 1.93 2.22 ns, max input to pin 4 t mult1_p4 1.66 1.82 2.10 ns, max input to pin 3 t mult1_p3 1.56 1.72 1.97 ns, max input to pin 2 t mult1_p2 1.46 1.61 1.85 ns, max input to pin 1 t mult1_p1 1.37 1.50 1.73 ns, max input to pin 0 t mult1_p0 1.27 1.40 1.60 ns, max
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 24 ta bl e 2 6 : enhanced pipelined multiplier switching characteristics description symbol speed grade units ?6 ?5 ?4 setup and hold times before/after clock data inputs t mulidck /t mulckid 3.00/0.00 3.45/0.00 3.89/0.00 ns, max clock enable t mulidck_ce /t mulckid_ce 0.72/0.00 0.80/0.00 0.86/0.00 ns, max reset t mulidck_rst /t mulckid_rst 0.72/0.00 0.80/0.00 0.86/0.00 ns, max clock to output pin clock to pin 35 t multck1_p35 3.05 3.25 3.74 ns, max clock to pin 34 t multck1_p34 2.95 3.14 3.61 ns, max clock to pin 33 t multck1_p33 2.85 3.04 3.49 ns, max clock to pin 32 t multck1_p32 2.76 2.93 3.37 ns, max clock to pin 31 t multck1_p31 2.66 2.82 3.25 ns, max clock to pin 30 t multck1_p30 2.56 2.72 3.12 ns, max clock to pin 29 t multck1_p29 2.47 2.61 3.00 ns, max clock to pin 28 t multck1_p28 2.37 2.50 2.88 ns, max clock to pin 27 t multck1_p27 2.27 2.40 2.75 ns, max clock to pin 26 t multck1_p26 2.17 2.29 2.63 ns, max clock to pin 25 t multck1_p25 2.08 2.18 2.51 ns, max clock to pin 24 t multck1_p24 1.98 2.07 2.38 ns, max clock to pin 23 t multck1_p23 1.88 1.97 2.26 ns, max clock to pin 22 t multck1_p22 1.79 1.86 2.14 ns, max clock to pin 21 t multck1_p21 1.69 1.75 2.02 ns, max clock to pin 20 t multck1_p20 1.59 1.65 1.89 ns, max clock to pin 19 t multck1_p19 1.50 1.54 1.77 ns, max clock to pin 18 t multck1_p18 1.40 1.43 1.65 ns, max clock to pin 17 t multck1_p17 1.30 1.33 1.52 ns, max clock to pin 16 t multck1_p16 1.20 1.22 1.40 ns, max clock to pin 15 t multck1_p15 1.11 1.11 1.28 ns, max clock to pin 14 t multck1_p14 1.01 1.00 1.15 ns, max clock to pin 13 t multck1_p13 0.91 1.00 1.15 ns, max clock to pin 12 t multck1_p12 0.91 1.00 1.15 ns, max clock to pin 11 t multck1_p11 0.91 1.00 1.15 ns, max clock to pin 10 t multck1_p10 0.91 1.00 1.15 ns, max clock to pin 9 t multck1_p9 0.91 1.00 1.15 ns, max clock to pin 8 t multck1_p8 0.91 1.00 1.15 ns, max clock to pin 7 t multck1_p7 0.91 1.00 1.15 ns, max clock to pin 6 t multck1_p6 0.91 1.00 1.15 ns, max clock to pin 5 t multck1_p5 0.91 1.00 1.15 ns, max clock to pin 4 t multck1_p4 0.91 1.00 1.15 ns, max clock to pin 3 t multck1_p3 0.91 1.00 1.15 ns, max clock to pin 2 t multck1_p2 0.91 1.00 1.15 ns, max clock to pin 1 t multck1_p1 0.91 1.00 1.15 ns, max clock to pin 0 t multck1_p0 0.91 1.00 1.15 ns, max
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 25 block selectram switching characteristics tbuf switching characteristics jtag test access port sw itching characteristics ta bl e 2 7 : block selectram switching characteristics description symbol speed grade units ? 6 ? 5 ? 4 sequential delays clock clk to dout output t bcko 2.10 2.31 2.65 ns, max setup and hold times before clock clk addr inputs t back /t bcka 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, min din inputs t bdck /t bckd 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, min en input t beck /t bcke 0.95/?0.46 1.04/? 0.50 1.20/?0.58 ns, min rst input t brck /t bckr 1.31/?0.71 1.44/? 0.78 1.65/?0.90 ns, min wen input t bwck /t bckw 0.57/?0.19 0.63/? 0.21 0.72/?0.25 ns, min clock clk minimum pulse width, high t bpwh 1.17 1.29 1.48 ns, min minimum pulse width, low t bpwl 1.17 1.29 1.48 ns, min ta bl e 2 8 : tbuf switching characteristics description symbol speed grade units ? 6 ? 5 ? 4 combinatorial delays in input to out output t io 0.45 0.50 0.58 ns, max tri input to out output high-impedance t off 0.44 0.48 0.55 ns, max tri input to valid data on out output t on 0.44 0.48 0.55 ns, max ta bl e 2 9 : jtag test access port switching characteristics description symbol units tms and tdi setup times before tck t ta p t k 5.5 ns, min tms and tdi hold times after tck t tcktap 0.0 ns, min output delay from clock tck to output tdo t tcktdo 10.0 ns, max maximum tck clock frequency f tck 33 mhz, max
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 26 virtex-ii pin-to-pin output parameter guidelines all devices are 100% functionally tested. listed below are repr esentative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted. global clock input to output delay for lvttl, 12 ma, fast slew rate, with dcm ta bl e 3 0 : global clock input to output delay for lvttl, 12 ma, fast slew rate, with dcm description symbol device speed grade units ? 6 ? 5 ? 4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, with dcm. for data output with different standards, adjust the delays with the values shown in iob output switching characteristics standard adjustments , page 14 . global clock and off with dcm t ickofdcm xc2v40 1.10 1.28 1.48 ns xc2v80 1.10 1.28 1.48 ns xc2v250 1.10 1.28 1.48 ns xc2v500 1.10 1.28 1.48 ns xc2v1000 1.10 1.28 1.48 ns xc2v1500 1.10 1.28 1.48 ns XC2V2000 1.10 1.28 1.48 ns xc2v3000 1.19 1.38 1.59 ns xc2v4000 1.19 1.38 1.59 ns xc2v6000 1.64 1.88 2.17 ns xc2v8000 1.64 1.88 2.17 ns notes: 1. listed above are representative values where one global clock i nput drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with test setup shwon in figure 1 . for other i/o standards and different loads, see ta b l e 1 8 .
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 27 global clock input to output delay for lvttl, 12 ma, fast slew rate, without dcm ta bl e 3 1 : global clock input to output delay for lvttl, 12 ma, fast slew rate, without dcm description symbol device speed grade units ? 6 ? 5 ? 4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, without dcm. for data output with different standards, adjust the delays with the values shown in iob output switching characteristics standard adjustments , page 14 . global clock and off without dcm t ickof xc2v40 3.46 3.58 3.69 ns xc2v80 3.62 3.58 3.69 ns xc2v250 3.79 3.88 4.47 ns xc2v500 3.85 3.88 4.47 ns xc2v1000 4.02 4.28 4.62 ns xc2v1500 4.16 4.28 4.62 ns XC2V2000 4.30 4.43 5.10 ns xc2v3000 4.49 4.64 5.34 ns xc2v4000 4.82 4.99 5.74 ns xc2v6000 5.19 5.38 5.93 ns xc2v8000 5.47 6.09 7.00 ns notes: 1. listed above are representative values where one global clock i nput drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with test setup shwon in figure 1 . for other i/o standards and different loads, see ta b l e 1 8 .
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 28 virtex-ii pin-to-pin in put parameter guidelines all devices are 100% functionally tested. listed below are repr esentative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted. global clock setup and ho ld for lvttl standard, with dcm ta bl e 3 2 : global clock setup and hold for lvttl standard, with dcm description symbol device speed grade units ? 6 ? 5 ? 4 input setup and hold time relative to global clock input signal for lvttl standard. for data input with different standards, adjust the setup time delay by the values shown in iob input switching characteristics standard adjustments , page 11 . no delay global clock and iff with dcm t psdcm /t phdcm xc2v40 1.60/?0.90 1. 60/?0.90 1.84/?0.76 ns xc2v80 1.60/?0.90 1. 60/?0.90 1.84/?0.76 ns xc2v250 1.60/?0.90 1 .60/?0.90 1.84/?0.76 ns xc2v500 1.60/?0.90 1 .60/?0.90 1.84/?0.76 ns xc2v1000 1.60/?0.90 1 .60/?0.90 1.84/?0.76 ns xc2v1500 1.60/?0.90 1 .60/?0.90 1.84/?0.76 ns XC2V2000 1.70/?0.90 1 .70/?0.90 1.96/?0.76 ns xc2v3000 1.70/?0.90 1 .70/?0.90 1.96/?0.76 ns xc2v4000 1.70/?0.90 1 .70/?0.90 1.96/?0.76 ns xc2v6000 1.70/?0.90 1 .70/?0.90 1.96/?0.76 ns xc2v8000 1.70/?0.90 1 .70/?0.90 1.96/?0.76 ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input si gnal with the fastest route and t he lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 29 global clock setup and ho ld for lvttl standard, without dcm , ta bl e 3 3 : global clock setup and hold for lvttl standard, without dcm description symbol device speed grade units ? 6 ? 5 ? 4 input setup and hold time relative to global clock input signal for lvttl standard. (2) for data input with different standards, adjust the setup time delay by the values shown in iob input switching characteristics standard adjustments , page 11 . full delay global clock and iff (1) without dcm t psfd /t phfd xc2v40 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns xc2v80 2.10/ 0.00 2.10/ 0.00 2.21/ 0.00 ns xc2v250 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns xc2v500 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns xc2v1000 1.92/ 0.00 1. 92/ 0.00 2.21/ 0.00 ns xc2v1500 1.92/ 0.00 1. 92/ 0.00 2.21/ 0.00 ns XC2V2000 1.92/ 0.00 1. 92/ 0.00 2.21/ 0.00 ns xc2v3000 1.92/ 0.00 1. 92/ 0.00 2.21/ 0.00 ns xc2v4000 2.00/ 0.00 2. 00/ 0.00 2.30/ 0.00 ns xc2v6000 1.92/ 0.50 1. 92/ 0.50 2.21/ 0.50 ns xc2v8000 2.38/ 0.00 2. 38/ 0.00 2.60/ 0.00 ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input si gnal with the fastest route and t he lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 3. these values are parametrically measured.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 30 dcm timing parameters all devices are 100% functionally tested. because of the dif- ficulty in directly measuring many internal timing parame- ters, those parameters are derived from benchmark timing patterns. the following guidelines reflect worst-case values across the recommended operating conditions. all output jitter and phase specifications are determined through sta- tistical measurement at the package pins. operating frequency ranges e ta bl e 3 4 : operating frequency ranges description symbol constraint s speed grade unit s ?6 ?5 ?4 output clocks (low frequency mode) clk0, clk90, clk180, clk270 clkout _freq_1x_lf_min 2 4.00 24.00 24.00 mhz clkout_freq_1x_lf_max 230.00 210.00 180.00 mhz clk2x, clk2x180 clkout_freq _2x_lf_min 48.00 48.00 48.00 mhz clkout_freq_2x_lf_max 450.00 420.00 360.00 mhz clkdv clkout_freq_dv_lf_min 1.50 1.50 1.50 mhz clkout_freq_dv_lf_max 150.00 140.00 120.00 mhz clkfx, clkfx180 clkout_freq_fx_lf_min 24.00 24.00 24.00 mhz clkout_freq_fx_lf_max 260.00 240.00 210.00 mhz input clocks (low frequency mode) clkin (using dll outputs) (1,3) clkin_freq_dll_lf_min 24.00 24.00 24.00 mhz clkin_freq_dll_lf_max 230.00 210.00 180.00 mhz clkin (using clkfx outputs) (2,3) clkin_freq_fx_lf_min 1.00 1.00 1.00 mhz clkin_freq_fx_lf_max 260.00 240.00 210.00 mhz psclk psclk_freq_lf_min 0.01 0.01 0.01 mhz psclk_freq_lf_max 450.00 420.00 360.00 mhz output clocks (high frequency mode) clk0, clk180 clkout_freq_1x _hf_min 48.00 48.00 48.00 mhz clkout_freq_1x_hf_max 450.00 420.00 360.00 mhz clkdv clkout_freq_dv_hf_min 3.00 3.00 3.00 mhz clkout_freq_dv_hf_max 300.00 280.00 240.00 mhz clkfx, clkfx180 clkout_freq_fx_hf_min 210.00 210.00 210.00 mhz clkout_freq_fx_hf_max 350.00 320.00 270.00 mhz input clocks (high frequency mode) clkin (using dll outputs) (1,3) clkin_freq_dll_hf_min 48.00 48.00 48.00 mhz clkin_freq_dll_hf_max 450.00 420.00 360.00 mhz clkin (using clkfx outputs) (2,3) clkin_frq_fx_hf_min 50.00 50.00 50.00 mhz clkin_frq_fx_hf_max 350.00 320.00 270.00 mhz psclk psclk_freq_hf_min 0.01 0.01 0.01 mhz psclk_freq_hf_max 450.00 420.00 360.00 mhz notes: 1. ?dll outputs? is used here to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. if both dll and clkfx outputs are used, fo llow the more restrictive specification. 3. if the clkin_divide_by_2 attribute of th e dcm is used, then double these values.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 31 input clock tolerances ta bl e 3 5 : input clock tolerances description symbol constraints f clkin speed grade units ?6 ?5 ?4 min max min max min max input clock low/high pulse width psclk psclk_pulse < 1mhz 25.00 25.00 25.00 ns psclk and clkin (2) psclk_pulse and clkin_pulse 1 ? 10 mhz 25.00 25.00 25.00 ns 10 ? 25 mhz 10.00 10.00 10.00 ns 25 ? 50 mhz 5.00 5.00 5.00 ns 50 ? 100 mhz 3.00 3.00 3.00 ns 100 ? 150 mhz 2.40 2.40 2.40 ns 150 ? 200 mhz 2.00 2.00 2.00 ns 200 ? 250 mhz 1.80 1.80 1.80 ns 250 ? 300 mhz 1.50 1.50 1.50 ns 300 ? 350 mhz 1.30 1.30 1.30 ns 350 ? 400 mhz 1.15 1.15 1.15 ns > 400 mhz 1.05 1.05 1.05 ns input clock cycle-cycle jitter (low frequency mode) clkin (using dll outputs) (1) clkin_cyc_jitt_dll_lf 300 300 300 ps clkin (using clkfx outputs) (2) clkin_cyc_jitt_fx_lf 300 300 300 ps input clock cycle-cycle jitter (high frequency mode) clkin (using dll outputs) (1) clkin_cyc_jitt_dll_hf 150 150 150 ps clkin (using clkfx outputs) (2) clkin_cyc_jitt_fx_hf 150 150 150 ps input clock period jitter (low frequency mode) clkin (using dll outputs) (1) clkin_per_jitt_dll_lf 1 1 1 ns clkin (using clkfx outputs) (2) clkin_per_jitt_fx_lf 1 1 1 ns input clock period jitter (high frequency mode) clkin (using dll outputs) (1) clkin_per_jitt_dll_hf 1 1 1 ns clkin (using clkfx outputs) (2) clkin_per_jitt_fx_hf 1 1 1 ns feedback clock path delay variation clkfb off-chip feedback clkfb_delay_var_ext 1 1 1 ns notes: 1. ??dll outputs? is used her e to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. if both dll and clkfx outputs are used, follow the more restrictive specification.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 32 output clock jitter output clock phase alignment ta bl e 3 6 : output clock jitter description symbol constraints speed grade units ?6 ?5 ?4 clock synthesis period jitter clk0 clkout_per_jitt_0 100 100 100 ps clk90 clkout_per_jitt_90 150 150 150 ps clk180 clkout_per_jitt_180 150 150 150 ps clk270 clkout_per_jitt_270 150 150 150 ps clk2x, clk2x180 clkout_per_jitt_2x 200 200 200 ps clkdv (integer division) clkout_per_jitt_dv1 150 150 150 ps clkdv (non-integer division) clkout_per_jitt_dv2 300 300 300 ps clkfx, clkfx180 clkout_per_jitt_fx note 1 note 1 note 1 ps notes: 1. values for this parameter are available at www.xilinx.com . ta bl e 3 7 : output clock phase alignment description symbol constraints speed grade units ?6 ?5 ?4 phase offset between clkin and clkfb clkin/clkfb clkin_clkfb_phase 50 50 50 ps phase offset between any dcm outputs all clk outputs clkout_phase 140 140 140 ps duty cycle precision dll outputs (1) clkout_duty_cycle_dll (2) 150 150 150 ps clkfx outputs clkout_duty_cycle_fx 100 100 100 ps notes: 1. "dll outputs" is used here to desc ribe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. clkout_duty_cycle_dll applies to the 1x clock outputs (clk0, clk90, clk180, and clk270) only if duty_cycle_correction = true. 3. specification also applies to psclk.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 33 miscellaneous timing parameters frequency synthesis parameter cross reference ta bl e 3 8 : miscellaneous timing parameters description symbol constraints f clkin speed grade units ?6 ?5 ?4 time required to achieve lock using dll outputs (1) lock_dll lock_dll_60 > 60mhz 20.0 20.0 20.0 s lock_dll_50_60 50 - 60 mhz 25.0 25.0 25.0 s lock_dll_40_50 40 - 50 mhz 50.0 50.0 50.0 s lock_dll_30_40 30 - 40 mhz 90.0 90.0 90.0 s lock_dll_24_30 24 - 30 mhz 120.0 120.0 120.0 s using clkfx outputs loc k_fx_min 10.0 10.0 10.0 ms lock_fx_max 10. 0 10.0 10.0 ms additional lock time with fine-phase shifting lock_dll_fine_shift 50.0 50.0 50.0 s fine-phase shifting absolute shifting range fine_shift_range 10.0 10.0 10.0 ns delay lines tap delay resolution dcm_tap_min 30.0 30.0 30.0 ps dcm_tap_max 60.0 60.0 60.0 ps notes: 1. "dll outputs" is used here to desc ribe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. specification also applies to psclk. ta bl e 3 9 : frequency synthesis attribute min max clkfx_multiply 2 32 clkfx_divide 1 32 ta bl e 4 0 : parameter cross reference libraries guide data sheet dll_clkout_{min|max}_lf clkout_freq_{1x|2x|dv}_lf dfs_clkout_{min|max}_lf clkout_freq_fx_lf dll_clkin_{min|max}_lf clkin_freq_dll_lf dfs_clkin_{min|max}_lf clkin_freq_fx_lf dll_clkout_{min|max}_hf clkout_freq_{1x|dv}_hf dfs_clkout_{min|max} _hf clkout_freq_fx_hf dll_clkin_{min|max}_hf clkin_freq_dll_hf dfs_clkin_{min|max}_hf clkin_freq_fx_hf
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 34 source-synchronous switching characteristics the parameters in this section provide the necessary values for calculating timing budgets for virtex-ii source-synchronous transmitter and receiver data-valid windows. ta bl e 4 1 : duty cycle distortion and clock-tree skew description symbol device speed grade units ? 6 ? 5 ? 4 duty cycle distortion (1) t dcd_clk0 all 140 140 140 ps t dcd_clk180 all505050ps clock tree skew (2) t ckskew xc2v40 tbd 50 tbd ps xc2v80 tbd 50 tbd ps xc2v250 tbd 50 tbd ps xc2v500 tbd 50 tbd ps xc2v1000 tbd 80 tbd ps xc2v1500 tbd 80 tbd ps XC2V2000 tbd 100 tbd ps xc2v3000 tbd 100 tbd ps xc2v4000 tbd tbd tbd ps xc2v6000 tbd 500 tbd ps xc2v8000 tbd tbd tbd ps notes: 1. these parameters represent the worst-case duty cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to ca lculate any additional duty cycle distortion that might be caus ed by asymmetrical rise/fall times. t dcd_clk0 applies to cases where local (iob) inversion is used to pr ovide the negative-edge clock to the ddr element in the i/o. t dcd_clk180 applies to cases where the clk180 output of the dcm is used to provide the negative-edge clock to the ddr element in the i/o. 2. this value represents the worst-case clock-tree skew observab le between sequential i/o element s. significantly less clock-tre e skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_ editor and timing analyzer tools to evaluate cl ock skew specific to your application. ta bl e 4 2 : package skew description symbol device/package value units package skew (1) t pkgskew xc2v1000 / ff896 130 ps xc2v3000 / ff1152 115 ps xc2v3000 / bf957 130 ps xc2v4000 / ff1152 130 ps xc2v4000 / ff1517 200 ps xc2v4000 / bf957 140 ps xc2v6000 / ff1152 90 ps xc2v6000 / ff1517 105 ps xc2v6000 / bf957 105 ps notes: 1. these values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from pad to ball (7.1ps per mm). 2. package trace length information is available for these device/package combinations. this information can be used to deskew t he package.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 35 ta bl e 4 3 : sample window description symbol device speed grade units ? 6 ? 5 ? 4 sampling error at receiver pins (1) t samp xc2v40 tbd 500 tbd ps xc2v80 tbd 500 tbd ps xc2v250 tbd 500 tbd ps xc2v500 tbd 500 tbd ps xc2v1000 tbd 500 tbd ps xc2v1500 tbd 500 tbd ps XC2V2000 tbd 500 tbd ps xc2v3000 tbd 500 tbd ps xc2v4000 tbd 500 tbd ps xc2v6000 tbd 500 tbd ps xc2v8000 tbd tbd tbd ps notes: 1. this parameter indicates the total sampling error of virtex-ii ddr input registers across voltage, temperature, and process. the characterization methodology uses the dcm to capture the ddr input regist ers? edges of operation. these measurements include: - clk0 and clk180 dcm jitter - worst-case duty-cycle distortion - t dcd_clk180 - dcm accuracy (phase offset) - dcm phase shift resolution. these measurements do not include package or clock tree skew. ta bl e 4 4 : pin-to-pin setup/hold: source-synchronous configuration description symbol device speed grade units ? 6 ? 5 ? 4 data input set-up and hold times relative to a forwarded clock input pin, using dcm and global clock buffer. for situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in iob input switching characteristics stan dard adjustments , page 11 . no delay global clock and iff with dcm t psdcm / t phdcm xc2v40 tbd tbd tbd ns xc2v80 tbd tbd tbd ns xc2v250 tbd tbd tbd ns xc2v500 tbd tbd tbd ns xc2v1000 tbd 0.2/0.5 tbd ns xc2v1500 tbd tbd tbd ns XC2V2000 tbd tbd tbd ns xc2v3000 tbd 0.2/0.5 tbd ns xc2v4000 tbd tbd tbd ns xc2v6000 tbd 0.2/0.6 tbd ns xc2v8000 tbd tbd tbd ns notes: 1. iff = input flip-flop 2. the timing values were measured using t he fine-phase adjustment feature of the dcm. 3. the worst-case duty-cycle distortion and dcm jitter on clk0 and clk180 is included in these measurements.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 36 source synchronous timing budgets this section describes how to use the parameters provided in the source-synchronous switching characteristics section to develop system-specific timing budgets. the followi ng analysis provides informat ion necessary fo r determining virtex-ii contributions to an overall system timing analysis; no assumptions are made abou t the effects of inter-symbol interference or pcb skew. virtex-ii transmitter data-valid window (t x ) t x is the minimum aggregate valid data period for a source-synchronous data bus at the pins of the device and is calculated as follows: t x = data period - [jitter (1) + duty cycle distortion (2) + tckskew (3) + tpkgskew (4) ] notes: 1. jitter values and accumulation methodology to be provided in a future release of this document. the absolute period jitter values found in the dcm timing parameters section of the particular dcm output clock used to clock the iob ff can be used for a best case analysis. 2. this value depends on the clocking methodology used. see note1 for ta bl e 4 1 . 3. this value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew s pecific to your application. 4. these values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from pad to ball. virtex-ii receiver data-valid window (r x ) r x is the required minimum aggregate valid data period for a source-synchronous data bus at the pins of the device and is calculated as follows: r x = [tsamp (1) + tckskew (2) + tpkgskew (3) ] notes: 1. this parameter indicates the total sampling error of virtex-ii ddr input registers across voltage, temperature, and process. the characterization methodology uses the dcm to capture the ddr input registers? edges of operation. these measurements include: - clk0 and clk180 dcm jitter in a quiet system - worst-case duty-cycle distortion - dcm accuracy (phase offset) - dcm phase shift resolution. these measurements do not include package or clock tree skew. 2. this value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to your application. 3. these values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from pad to ball. revision history this section records the change history for this module of the data sheet. date version revision 11/07/00 1.0 early access draft. 12/06/00 1.1 initial release. 01/15/01 1.2 added values to the tables in the virtex-ii performance characteristics and virtex-ii switching characteristics sections. 01/25/01 1.3 the data sheet was divided into four modules (per the current style standard). updated values in the virtex-ii performance characteristics and virtex-ii switching characteristics tables. table 18, ?delay measurement methodology? 04/23/01 1.5 updated values in the virtex-ii performance characteristics and virtex-ii switching characteristics tables. added t reg32 symbol to ta b l e 2 2 . skipped v1.4 to sync with other modules. reverted to traditional double-column format.
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 37 07/30/01 1.6 updated values in the virtex-ii performance characteristics and virtex-ii switching characteristics tables. added values to the virtex-ii pin-to-pin output parameter guidelines and virtex-ii pin-to-pin input parameter guidelines tables. added frequency synthesis table. 10/02/01 1.7 updated values in the virtex-ii performance characteristics and virtex-ii switching characteristics tables. updated the speed grade designations used in data sheets, and added ta b l e 1 3 , which shows the current speed grade designation for each device. 10/05/01 1.8 corrected the speed grade designation for the xc2v1000 device in ta bl e 1 3 . 10/12/01 1.9 updated values in the virtex-ii performance characteristics and virtex-ii switching characteristics tables. 11/28/01 2.0 updated values in ta bl e 3 , ta bl e 4 , ta bl e 5 , virtex-ii performance characteristics , and virtex-ii switching characteristics tables. 01/03/02 2.1 updated values in virtex-ii performance characteristics and virtex-ii switching characteristics tables, based on values extracted from speedsfile version 1.96 . changed the speed grade designation for the xc2v6000 device in ta bl e 1 3 . 07/16/02 2.2 updated values in ta bl e 4 , " quiescent supply current ." updated values in virtex-ii performance characteristics and virtex-ii switching characteristics tables, based on values extracted from speedsfile version 1.111 . added enhanced multiplier switching characteristics section. added footnote to ta bl e 3 3 , " global clock setup and hold for lvttl standard, without dcm ." added source-synchronous switching characteristics section. 09/26/02 2.3 removed mention of mil-m-38510/605 specification. added footnotes to ta bl e 2 and ta bl e 6 . 12/06/02 2.4 revised sstl2 values in ta b l e 6 to match the latest jedec specification. added footnote regarding v in pci compliance to ta bl e 1 . added footnote regarding clkout_duty_cycle_dll to ta b l e 3 7 . 05/07/03 2.5 updated values in virtex-ii performance characteristics and virtex-ii switching characteristics tables, based on values extracted from speedsfile version 1.114 . ta b l e 4 , quiescent supply current , and ta b l e 5 , minimum power on current required for virtex-ii devices : added parameters for xc2v8000 device. ta b l e 1 6 , iob output switching characteristics : changed parameter designator t ioton to t iotp . ta b l e 2 5 , enhanced multiplier switching characteristics : corrected all parameter designators from t mult_p[ nn ] to t mult1_p[ nn ] in order to correspond with designators used in speedsfile. ta b l e 2 6 , enhanced pipelined multiplier switching characteristics : corrected all parameter designators from t multck_p[ nn ] to t multck1_p[ nn ] in order to correspond with designators used in speedsfile. removed old table 19, standard capacitive loads . added figure 1, page 18 , showing test configuration for measuring i/o standard adjustments. 06/19/03 2.5.1 removed footnotes in ta b l e 3 0 and ta bl e 3 2 that stated dcm jitte r was included in the measurements. date version revision
virtex?-ii platform fpgas: dc and switching characteristics r ds031-3 (v3.0) august 1, 2003 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 38 virtex-ii data sheet the virtex-ii data sheet contains the following modules: virtex?-ii platform fpgas: introduction and overview (module 1) virtex?-ii platform fpgas: detailed description (module 2) virtex?-ii platform fpgas: dc and switching characteristics (module 3) virtex?-ii platform fpgas: pinout information (module 4) 08/01/03 3.0 ta b l e 1 3 : all virtex-ii devices and speed grades now production. updated values in virtex-ii performance characteristics and virtex-ii switching characteristics tables, based on values extracted from speedsfile version 1.116 . ta b l e 3 0 and ta bl e 3 1 : revised test setup footnote to refer to figure 1 . previously specified a capacitive load parameter. figure 1 : added note to figure regarding termination resistors. date version revision
? 2001-2002 xilinx, inc. all rights reserved. all xilinx trademark s, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 1 this document provides virtex-ii device/package combi- nations and maximum i/os available and virtex-ii pin definitions , followed by pinout tables for the following pack- ages: cs144 chip-scale bga package fg256 fine-pitch bga package fg456 fine-pitch bga package fg676 fine-pitch bga package bg575 standard bga package bg728 standard bga package ff896 flip-chip fine-pitch bga package ff1152 flip-chip fine-pitch bga package ff1517 flip-chip fine-pitch bga package bf957 flip-chip bga package for device pinout diagrams and layout guidelines, refer to the virtex-ii platform fpga user guide . ascii package pinout files are also availabl e for download from the xilinx website ( www.xilinx.com ). virtex-ii device/package combinations and maximum i/os available wire-bond and flip-chip packages are available. ta b l e 1 and ta bl e 2 show the maximum number of user i/os possible in wire-bond and flip-chip packages, respectively. ta bl e 3 shows the number of user i/os available for all device/package combinations. cs denotes wire-bond chip-scale ball grid array (bga) (0.80 mm pitch). fg denotes wire-bond fine-pitch bga (1.00 mm pitch). ff denotes flip-chip fine-pitch bga (1.00 mm pitch). bg denotes standard bga (1.27 mm pitch). bf denotes flip-chip bga (1.27 mm pitch). the number of i/os per package include all user i/os except the 15 control pins (cclk, done, m0, m1, m2, prog_b, pwrdwn_b, tck, tdi, tdo, tms, hswap_en, dxn, dxp, and rsvd). 0 225 virtex?-ii platform fpgas: pinout information ds031-4 (v2.0) august 1, 2003 00 product specification r ta bl e 1 : wire-bond packages information package cs144 fg256 fg456 fg676 bg575 bg728 pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27 size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35 i/os 92 172 324 484 408 516 ta bl e 2 : flip-chip packages information package ff896 ff1152 ff1517 bf957 pitch (mm) 1.00 1.00 1.00 1.27 size (mm) 31 x 31 35 x 35 40 x 40 40 x 40 i/os 624 824 1,108 684
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 2 virtex-ii pin definitions this section describes the pinouts for virtex-ii devices in the following packages: cs144: wire-bond chip-scale ball grid array (bga) of 0.80 mm pitch fg256, fg456, and fg676: wire-bond fine-pitch bga of 1.00 mm pitch ff896, ff1152, ff1517: flip-chip fine-pitch bga of 1.00 mm pitch bg575 and bg728: wire-bond bga of 1.27 mm pitch bf957: flip-chip bga of 1.27 mm pitch all of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). in addition, the fg456 and fg676 packages are compatible, as are the ff896 and ff1152 packages. pins that are not available for the smallest devices are listed in right-hand columns. each device is split into eight i/o banks to allow for flexibility in the choice of i/o standards (see the virtex-ii data sheet ). global pins, including jtag, configuration, and power/ground pins, are listed at the end of each table. ta b l e 4 provides definitions for all pin types. the fg256 pinouts ( ta bl e 6 ) is included as an example. all virtex-ii pinout tables are available on the distribution cd-rom, or on the web (at http://www.xilinx.com ). ta bl e 3 : virtex-ii device/package combinations and maximum number of available i/os package available i/os xc2v 40 xc2v 80 xc2v 250 xc2v 500 xc2v 1000 xc2v 1500 xc2v 2000 xc2v 3000 xc2v 4000 xc2v 6000 xc2v 8000 cs144 88 92 92 - - - - - - - - fg256 88 120 172 172 172 - - - - - - fg456 - - 200 264 324 - - - - - - fg676 - - - - - 392 456 484 - - - ff896 - - - - 432 528 624 - - - - ff1152 - - - - - - - 720 824 824 824 ff1517 - - - - - - - - 912 1,104 1,108 bg575 - - - - 328 392 408 - - - - bg728 - - - - - - - 516 - - - bf957 - - - - - - 624 684 684 684 -
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 3 pin definitions ta bl e 4 provides a description of each pin type listed in virtex-ii pinout tables. ta bl e 4 : virtex-ii pin definitions pin name direct ion description user i/o pins io_lxxy_# input/output all user i/o pins are capable of differential signalling and can implement lvds, ulvds, blvds, lvpecl, or ldt pairs. each user i/o is labeled ? io_lxxy_# ?, where: io indicates a user i/o pin. lxxy indicates a differential pair, with xx a unique pair in the bank and y = p/n for the positive and negative sides of the differential pair. # indicates the bank number (0 through 7) dual-function pins io_lxxy_#/zzz the dual-function pins are labelled ? io_lxxy_#/zzz ?, where zzz can be one of the following pins: per bank - vrp, vrn, or vref globally - gclkx(s/p), busy/dout, init_b, d0/din ? d7, rdwr_b, or cs_b with /zzz: d0/din, d1, d2, d3, d4, d5, d6, d7 input/output in selectmap mode, d0 through d7 are configuration data pins. these pins become user i/os after configuration, unless the selectmap port is retained. in bit-serial modes, din (d0) is the single-data input. this pin becomes a user i/o after configuration. cs_b input in selectmap mode, this is the active-low chip select signal. the pin becomes a user i/o after configuration, unless the selectmap port is retained. rdwr_b input in selectmap mode, this is the active-low write enable signal. the pin becomes a user i/o after configuration, unless the selectmap port is retained. busy/dout output in selectmap mode, busy controls the rate at which configuration data is loaded. the pin becomes a user i/o after configuration, unless the selectmap port is retained. in bit-serial modes, dout provides preamble and configuration data to downstream devices in a daisy-chain. the pin becomes a user i/o after configuration. init_b bidirectional (open-drain) when low, this pin indicates that the configuration memory is being cleared. when held low, the start of configuration is delayed. during configuration, a low on this output indicates that a configuration data error has occurred. the pin becomes a user i/o after configuration. gclkx (s/p) input/output these are clock input pins that connect to global clock buffers. these pins become regular user i/os when not needed for clocks. vrp input this pin is for the dci voltage reference resistor of p transistor (per bank). vrn input this pin is for the dci voltage reference resistor of n transistor (per bank). alt_vrp input this is the alternative pin for the dci voltage reference resistor of p transistor. alt_vrn input this is the alternative pin for the dci voltage reference resistor of n transistor. v ref input these are input threshold voltage pins. they become user i/os when an external threshold voltage is not needed (per bank). dedicated pins (1)
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 4 cclk input/output configuration clock. output in master mode or input in slave mode. prog_b input active low asynchronous reset to configuration logic. this pin has a permanent weak pull-up resistor. done input/output done is a bidirectional signal with an optional internal pull-up resistor. as an output, this pin indicates completion of the configuration process. as an input, a low level on done can be configured to delay the start-up sequence. m2, m1, m0 input configuration mode selection. hswap_en input enable i/o pullups during configuration. tck input boundary scan clock. tdi input boundary scan data input. tdo output boundary scan data output. tms input boundary scan mode select. pwrdwn_b input (unsupported) active low power-down pin (unsupported). driving this pin low can adversely affect device operation and configuration. pwrdwn_b is internally pulled high, which is its default state. it does not require an external pull-up. other pins dxn, dxp n/a temperature-sensing diode pins (anode: dxp, cathode: dxn). v batt input decryptor key memory backup supply. (do not connect if battery is not used.) rsvd n/a reserved pin - do not connect. v cco input power-supply pins for the output drivers (per bank). v ccaux input power-supply pins for auxiliary circuits. v ccint input power-supply pins for the internal core logic. gnd input ground. notes: 1. all dedicated pins (jtag and configuration) are powered by v ccaux (independent of the bank v cco voltage). ta bl e 4 : virtex-ii pin definitions (continued) pin name direct ion description
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 5 cs144 chip-scale bga package as shown in ta bl e 5 , xc2v40, xc2v80, and xc2v250 virtex-ii devices are available in the cs144 package. pins in the xc2v40, xc2v80, and xc2v250 devices are the same except fo r pin differences in the xc2v40 device, shown in the no connect column. following this table are the cs144 chip-scale bga package specifications (0.80mm pitch) . ta bl e 5 : cs144 ? xc2v40, xc2v80, and xc2v250 bank pin description pin number no connect in the xc2v40 0 io_l01n_0 b3 0 io_l01p_0 a3 0 io_l02n_0 c4 0 io_l02p_0 b4 0 io_l03n_0/vrp_0 a4 0 io_l03p_0/vrn_0 d5 0 io_l94n_0/vref_0 a5 0 io_l94p_0 d6 0 io_l95n_0/gclk7p c6 0 io_l95p_0/gclk6s b6 0 io_l96n_0/gclk5p a6 0 io_l96p_0/gclk4s d7 1 io_l96n_1/gclk3p a7 1 io_l96p_1/gclk2s b7 1 io_l95n_1/gclk1p a8 1 io_l95p_1/gclk0s b8 1 io_l94n_1 c8 1 io_l94p_1/vref_1 d8 1 io_l03n_1/vrp_1 c9 1 io_l03p_1/vrn_1 d9 1 io_l02n_1 a10 1 io_l02p_1 b10 1 io_l01n_1 c10 1 io_l01p_1 d10 2 io_l01n_2 c13 2 io_l01p_2 d11 2 io_l02n_2/vrp_2 d12 2 io_l02p_2/vrn_2 d13 2 io_l03n_2 e10 2 io_l03p_2/vref_2 e11 2 io_l93n_2 e13 nc 2 io_l93p_2/vref_2 f11 nc 2 io_l94n_2 f12 2 io_l94p_2 g10
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 6 2 io_l96n_2 g11 2 io_l96p_2 g13 3 io_l96n_3 g12 3 io_l96p_3 h12 3 io_l94n_3 h11 3 io_l94p_3 j13 3 io_l03n_3/vref_3 j10 3 io_l03p_3 k13 3 io_l02n_3/vrp_3 k12 3 io_l02p_3/vrn_3 k11 3 io_l01n_3 k10 3 io_l01p_3 l13 4 io_l01n_4/busy/dout (1) m11 4 io_l01p_4/init_b n11 4 io_l02n_4/d0/din (1) l10 4 io_l02p_4/d1 m10 4 io_l03n_4/d2/alt_vrp_4 n10 4 io_l03p_4/d3/alt_vrn_4 k9 4 io_l94n_4/vref_4 n9 4 io_l94p_4 k8 4 io_l95n_4/gclk3s l8 4 io_l95p_4/gclk2p m8 4 io_l96n_4/gclk1s n8 4 io_l96p_4/gclk0p k7 5 io_l96n_5/gclk7s n7 5 io_l96p_5/gclk6p m7 5 io_l95n_5/gclk5s n6 5 io_l95p_5/gclk4p m6 5 io_l94n_5 l6 5 io_l94p_5/vref_5 k6 5 io_l03n_5/d4/alt_vrp_5 l5 5 io_l03p_5/d5/alt_vrn_5 k5 5 io_l02n_5/d6 n4 5 io_l02p_5/d7 m4 5 io_l01n_5/rdwr_b l4 5 io_l01p_5/cs_b k4 ta bl e 5 : cs144 ? xc2v40, xc2v80, and xc2v250 bank pin description pin number no connect in the xc2v40
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 7 6 io_l01p_6 l3 6 io_l01n_6 l2 6 io_l02p_6/vrn_6 l1 6 io_l02n_6/vrp_6 k3 6 io_l03p_6 k2 6 io_l03n_6/vref_6 k1 6 io_l94p_6 j2 6 io_l94n_6 h4 6 io_l96p_6 h3 6 io_l96n_6 h1 7 io_l96p_7 g4 7 io_l96n_7 g3 7 io_l94p_7 g1 7 io_l94n_7 f1 7 io_l93p_7/vref_7 f2 nc 7 io_l93n_7 f4 nc 7 io_l03p_7/vref_7 e2 7 io_l03n_7 e3 7 io_l02p_7/vrn_7 e4 7 io_l02n_7/vrp_7 d1 7 io_l01p_7 d2 7 io_l01n_7 d3 0 vcco_0 b5 0 vcco_0 c3 1 vcco_1 a11 1 vcco_1 a9 2 vcco_2 f10 2 vcco_2 c12 3 vcco_3 l12 3 vcco_3 j12 4 vcco_4 m9 4 vcco_4 l11 5 vcco_5 n3 5 vcco_5 n5 6 vcco_6 j3 6 vcco_6 m1 7 vcco_7 d4 7 vcco_7 f3 ta bl e 5 : cs144 ? xc2v40, xc2v80, and xc2v250 bank pin description pin number no connect in the xc2v40
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 8 na cclk m13 na prog_b b1 na done n12 na m0 n2 na m1 m2 na m2 m3 na tck b12 na tdi c1 na tdo c11 na tms a13 na pwrdwn_b m12 na hswap_en a1 na rsvd a2 na rsvd b2 na vbatt a12 na rsvd b11 na vccaux c2 na vccaux n1 na vccaux n13 na vccaux b13 na vccint h2 na vccint l7 na vccint h13 na vccint c7 na gnd e1 na gnd g2 na gnd j1 na gnd j4 na gnd m5 na gnd l9 na gnd j11 na gnd h10 na gnd f13 na gnd e12 na gnd b9 na gnd c5 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 5 : cs144 ? xc2v40, xc2v80, and xc2v250 bank pin description pin number no connect in the xc2v40
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 9 cs144 chip-scale bga package specifications (0.80mm pitch) figure 1: cs144 chip-scale bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 10 fg256 fine-pitch bga package as shown in ta b l e 6 , xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1 000 virtex-ii devices are available in the fg256 fine-pitch bga package. the pins in the xc2v250, xc2v50 0, and xc2v1000 devices are same. the no connect columns show pin differences for the xc2v40 and xc2v80 devices. following this table are the fg256 fine-pitch bga package specifications (1.00mm pitch) . ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80 0 io_l01n_0 c4 0 io_l01p_0 b4 0 io_l02n_0 d5 0 io_l02p_0 c5 0 io_l03n_0/vrp_0 b5 0 io_l03p_0/vrn_0 a5 0 io_l04n_0/vref_0 d6 nc nc 0 io_l04p_0 c6 nc nc 0 io_l05n_0 b6 nc nc 0 io_l05p_0 a6 nc nc 0 io_l92n_0 e6 nc nc 0 io_l92p_0 e7 nc nc 0 io_l93n_0 d7 nc nc 0 io_l93p_0 c7 nc nc 0 io_l94n_0/vref_0 b7 0 io_l94p_0 a7 0 io_l95n_0/gclk7p d8 0 io_l95p_0/gclk6s c8 0 io_l96n_0/gclk5p b8 0 io_l96p_0/gclk4s a8 1 io_l96n_1/gclk3p a9 1 io_l96p_1/gclk2s b9 1 io_l95n_1/gclk1p c9 1 io_l95p_1/gclk0s d9 1 io_l94n_1 a10 1 io_l94p_1/vref_1 b10 1 io_l93n_1 c10 nc nc 1 io_l93p_1 d10 nc nc 1 io_l92n_1 e10 nc nc
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 11 1 io_l92p_1 e11 nc nc 1 io_l05n_1 a11 nc nc 1 io_l05p_1 b11 nc nc 1 io_l04n_1 c11 nc nc 1 io_l04p_1/vref_1 d11 nc nc 1 io_l03n_1/vrp_1 a12 1 io_l03p_1/vrn_1 b12 1 io_l02n_1 c12 1 io_l02p_1 d12 1 io_l01n_1 b13 1 io_l01p_1 c13 2 io_l01n_2 c16 2 io_l01p_2 d16 2 io_l02n_2/vrp_2 d14 2 io_l02p_2/vrn_2 d15 2 io_l03n_2 e13 2 io_l03p_2/vref_2 e14 2 io_l04n_2 e15 nc 2 io_l04p_2 e16 nc 2 io_l06n_2 f13 nc 2 io_l06p_2 f14 nc 2 io_l43n_2 f15 nc nc 2 io_l43p_2 f16 nc nc 2 io_l45n_2 f12 nc nc 2 io_l45p_2/vref_2 g12 nc nc 2 io_l91n_2 g13 nc 2 io_l91p_2 g14 nc 2 io_l93n_2 g15 nc 2 io_l93p_2/vref_2 g16 nc 2 io_l94n_2 h13 2 io_l94p_2 h14 2 io_l96n_2 h15 2 io_l96p_2 h16 ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 12 3 io_l96n_3 j16 3 io_l96p_3 j15 3 io_l94n_3 j14 3 io_l94p_3 j13 3 io_l93n_3/vref_3 k16 nc 3 io_l93p_3 k15 nc 3 io_l91n_3 k14 nc 3 io_l91p_3 k13 nc 3 io_l45n_3/vref_3 k12 nc nc 3 io_l45p_3 l12 nc nc 3 io_l43n_3 l16 nc nc 3 io_l43p_3 l15 nc nc 3 io_l06n_3 l14 nc 3 io_l06p_3 l13 nc 3 io_l04n_3 m16 nc 3 io_l04p_3 m15 nc 3 io_l03n_3/vref_3 m14 3 io_l03p_3 m13 3 io_l02n_3/vrp_3 n15 3 io_l02p_3/vrn_3 n14 3 io_l01n_3 n16 3 io_l01p_3 p16 4 io_l01n_4/busy/dout (1) t14 4 io_l01p_4/init_b t13 4 io_l02n_4/d0/din (1) p13 4 io_l02p_4/d1 r13 4 io_l03n_4/d2/alt_vrp_4 n12 4 io_l03p_4/d3/alt_vrn_4 p12 4 io_l04n_4/vref_4 r12 nc nc 4 io_l04p_4 t12 nc nc 4 io_l05n_4/vrp_4 n11 nc nc 4 io_l05p_4/vrn_4 p11 nc nc ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 13 4 io_l91n_4/vref_4 r11 nc nc 4 io_l91p_4 t11 nc nc 4 io_l92n_4 m11 nc nc 4 io_l92p_4 m10 nc nc 4 io_l93n_4 n10 nc nc 4 io_l93p_4 p10 nc nc 4 io_l94n_4/vref_4 r10 4 io_l94p_4 t10 4 io_l95n_4/gclk3s n9 4 io_l95p_4/gclk2p p9 4 io_l96n_4/gclk1s r9 4 io_l96p_4/gclk0p t9 5 io_l96n_5/gclk7s t8 5 io_l96p_5/gclk6p r8 5 io_l95n_5/gclk5s p8 5 io_l95p_5/gclk4p n8 5 io_l94n_5 t7 5 io_l94p_5/vref_5 r7 5 io_l93n_5 p7 nc nc 5 io_l93p_5 n7 nc nc 5 io_l92n_5 m7 nc nc 5 io_l92p_5 m6 nc nc 5 io_l91n_5 t6 nc nc 5 io_l91p_5/vref_5 r6 nc nc 5 io_l05n_5/vrp_5 p6 nc nc 5 io_l05p_5/vrn_5 n6 nc nc 5 io_l04n_5 t5 nc nc 5 io_l04p_5/vref_5 r5 nc nc 5 io_l03n_5/d4/alt_vrp_5 p5 5 io_l03p_5/d5/alt_vrn_5 n5 5 io_l02n_5/d6 r4 5 io_l02p_5/d7 p4 5 io_l01n_5/rdwr_b t4 ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 14 5 io_l01p_5/cs_b t3 6 io_l01p_6 p1 6 io_l01n_6 n1 6 io_l02p_6/vrn_6 n3 6 io_l02n_6/vrp_6 n2 6 io_l03p_6 m4 6 io_l03n_6/vref_6 m3 6 io_l04p_6 m2 nc 6 io_l04n_6 m1 nc 6 io_l06p_6 l4 nc 6 io_l06n_6 l3 nc 6 io_l43p_6 l2 nc nc 6 io_l43n_6 l1 nc nc 6 io_l45p_6 l5 nc nc 6 io_l45n_6/vref_6 k5 nc nc 6 io_l91p_6 k4 nc 6 io_l91n_6 k3 nc 6 io_l93p_6 k2 nc 6 io_l93n_6/vref_6 k1 nc 6 io_l94p_6 j4 6 io_l94n_6 j3 6 io_l96p_6 j2 6 io_l96n_6 j1 7 io_l96p_7 h1 7 io_l96n_7 h2 7 io_l94p_7 h3 7 io_l94n_7 h4 7 io_l93p_7/vref_7 g1 nc 7 io_l93n_7 g2 nc 7 io_l91p_7 g3 nc 7 io_l91n_7 g4 nc 7 io_l45p_7/vref_7 g5 nc nc ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 15 7 io_l45n_7 f5 nc nc 7 io_l43p_7 f1 nc nc 7 io_l43n_7 f2 nc nc 7 io_l06p_7 f3 nc 7 io_l06n_7 f4 nc 7 io_l04p_7 e1 nc 7 io_l04n_7 e2 nc 7 io_l03p_7/vref_7 e3 7 io_l03n_7 e4 7 io_l02p_7/vrn_7 d2 7 io_l02n_7/vrp_7 d3 7 io_l01p_7 d1 7 io_l01n_7 c1 0 vcco_0 f8 0 vcco_0 f7 0 vcco_0 e8 1 vcco_1 f10 1 vcco_1 f9 1 vcco_1 e9 2 vcco_2 h12 2 vcco_2 h11 2 vcco_2 g11 3 vcco_3 k11 3 vcco_3 j12 3 vcco_3 j11 4 vcco_4 m9 4 vcco_4 l10 4 vcco_4 l9 5 vcco_5 m8 5 vcco_5 l8 5 vcco_5 l7 6 vcco_6 k6 6 vcco_6 j6 ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 16 6 vcco_6 j5 7 vcco_7 h6 7 vcco_7 h5 7 vcco_7 g6 na cclk p15 na prog_b a2 na done r14 na m0 t2 na m1 p2 na m2 r3 na hswap_en b3 na tck a15 na tdi c2 na tdo c15 na tms b14 na pwrdwn_b t15 na rsvd a4 na rsvd a3 na vbatt a14 na rsvd a13 na vccaux r16 na vccaux r1 na vccaux b16 na vccaux b1 na vccint n13 na vccint n4 na vccint m12 na vccint m5 na vccint e12 na vccint e5 na vccint d13 na vccint d4 ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 17 na gnd t16 na gnd t1 na gnd r15 na gnd r2 na gnd p14 na gnd p3 na gnd l11 na gnd l6 na gnd k10 na gnd k9 na gnd k8 na gnd k7 na gnd j10 na gnd j9 na gnd j8 na gnd j7 na gnd h10 na gnd h9 na gnd h8 na gnd h7 na gnd g10 na gnd g9 na gnd g8 na gnd g7 na gnd f11 na gnd f6 na gnd c14 na gnd c3 na gnd b15 na gnd b2 na gnd a16 na gnd a1 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 6 : fg256 bga ? xc2v40, xc2v80, xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v40 no connect in xc2v80
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 18 fg256 fine-pitch bga package specifications (1.00mm pitch) figure 2: fg256 fine-pitch bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 19 fg456 fine-pitch bga package as shown in ta bl e 7 , xc2v250, xc2v500, and xc2v1000 virtex-ii devices are available in the fg456 fine-pitch bga package. pins in the xc2v250, xc2v500, and xc2v1000 devi ces are the same, except for the pin differences in the xc2v250 and xc2v500 devices shown in the no connect columns. following this table are the fg456 fine-pitch bga package specifications (1.00mm pitch) . ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500 0 io_l01n_0 b4 0 io_l01p_0 a4 0 io_l02n_0 c4 0 io_l02p_0 c5 0 io_l03n_0/vrp_0 b5 0 io_l03p_0/vrn_0 a5 0 io_l04n_0/vref_0 d6 0 io_l04p_0 c6 0 io_l05n_0 b6 0 io_l05p_0 a6 0 io_l06n_0 e7 0 io_l06p_0 e8 0 io_l21n_0 d7 nc nc 0 io_l21p_0/vref_0 c7 nc nc 0 io_l22n_0 b7 nc nc 0 io_l22p_0 a7 nc nc 0 io_l24n_0 d8 nc nc 0 io_l24p_0 c8 nc nc 0 io_l49n_0 b8 nc 0 io_l49p_0 a8 nc 0 io_l51n_0 e9 nc 0 io_l51p_0/vref_0 f9 nc 0 io_l52n_0 d9 nc 0 io_l52p_0 c9 nc 0 io_l54n_0 b9 nc 0 io_l54p_0 a9 nc 0 io_l91n_0/vref_0 e10 0 io_l91p_0 f10 0 io_l92n_0 d10 0 io_l92p_0 c10
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 20 0 io_l93n_0 b10 0 io_l93p_0 a10 0 io_l94n_0/vref_0 e11 0 io_l94p_0 f11 0 io_l95n_0/gclk7p d11 0 io_l95p_0/gclk6s c11 0 io_l96n_0/gclk5p b11 0 io_l96p_0/gclk4s a11 1 io_l96n_1/gclk3p f12 1 io_l96p_1/gclk2s f13 1 io_l95n_1/gclk1p e12 1 io_l95p_1/gclk0s d12 1 io_l94n_1 c12 1 io_l94p_1/vref_1 b12 1 io_l93n_1 a13 1 io_l93p_1 b13 1 io_l92n_1 c13 1 io_l92p_1 d13 1 io_l91n_1 e13 1 io_l91p_1/vref_1 e14 1 io_l54n_1 a14 nc 1 io_l54p_1 b14 nc 1 io_l52n_1 c14 nc 1 io_l52p_1 d14 nc 1 io_l51n_1/vref_1 a15 nc 1 io_l51p_1 b15 nc 1 io_l49n_1 c15 nc 1 io_l49p_1 d15 nc 1 io_l24n_1 f14 nc nc 1 io_l24p_1 e15 nc nc 1 io_l22n_1 a16 nc nc 1 io_l22p_1 b16 nc nc 1 io_l21n_1/vref_1 c16 nc nc ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 21 1 io_l21p_1 d16 nc nc 1 io_l06n_1 e16 1 io_l06p_1 e17 1 io_l05n_1 a17 1 io_l05p_1 b17 1 io_l04n_1 c17 1 io_l04p_1/vref_1 d17 1 io_l03n_1/vrp_1 a18 1 io_l03p_1/vrn_1 b18 1 io_l02n_1 c18 1 io_l02p_1 d18 1 io_l01n_1 a19 1 io_l01p_1 b19 2 io_l01n_2 c21 2 io_l01p_2 c22 2 io_l02n_2/vrp_2 e18 2 io_l02p_2/vrn_2 f18 2 io_l03n_2 d21 2 io_l03p_2/vref_2 d22 2 io_l04n_2 e19 2 io_l04p_2 e20 2 io_l06n_2 e21 2 io_l06p_2 e22 2 io_l19n_2 f19 nc nc 2 io_l19p_2 f20 nc nc 2 io_l21n_2 f21 nc nc 2 io_l21p_2/vref_2 f22 nc nc 2 io_l22n_2 g18 nc nc 2 io_l22p_2 h18 nc nc 2 io_l24n_2 g19 nc nc 2 io_l24p_2 g20 nc nc 2 io_l43n_2 g21 2 io_l43p_2 g22 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 22 2 io_l45n_2 h19 2 io_l45p_2/vref_2 h20 2 io_l46n_2 h21 2 io_l46p_2 h22 2 io_l48n_2 j17 2 io_l48p_2 j18 2 io_l49n_2 j19 nc 2 io_l49p_2 j20 nc 2 io_l51n_2 j21 nc 2 io_l51p_2/vref_2 j22 nc 2 io_l52n_2 k17 nc 2 io_l52p_2 k18 nc 2 io_l54n_2 k19 nc 2 io_l54p_2 k20 nc 2 io_l91n_2 k21 2 io_l91p_2 k22 2 io_l93n_2 l17 2 io_l93p_2/vref_2 l18 2 io_l94n_2 l19 2 io_l94p_2 l20 2 io_l96n_2 l21 2 io_l96p_2 l22 3 io_l96n_3 m21 3 io_l96p_3 m20 3 io_l94n_3 m19 3 io_l94p_3 m18 3 io_l93n_3/vref_3 m17 3 io_l93p_3 n17 3 io_l91n_3 n22 3 io_l91p_3 n21 3 io_l54n_3 n20 nc 3 io_l54p_3 n19 nc 3 io_l52n_3 n18 nc ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 23 3 io_l52p_3 p18 nc 3 io_l51n_3/vref_3 p22 nc 3 io_l51p_3 p21 nc 3 io_l49n_3 p20 nc 3 io_l49p_3 p19 nc 3 io_l48n_3 r22 3 io_l48p_3 r21 3 io_l46n_3 r20 3 io_l46p_3 r19 3 io_l45n_3/vref_3 r18 3 io_l45p_3 p17 3 io_l43n_3 t22 3 io_l43p_3 t21 3 io_l24n_3 t20 nc nc 3 io_l24p_3 t19 nc nc 3 io_l22n_3 u22 nc nc 3 io_l22p_3 u21 nc nc 3 io_l21n_3/vref_3 u20 nc nc 3 io_l21p_3 u19 nc nc 3 io_l19n_3 t18 nc nc 3 io_l19p_3 u18 nc nc 3 io_l06n_3 v22 3 io_l06p_3 v21 3 io_l04n_3 v20 3 io_l04p_3 v19 3 io_l03n_3/vref_3 w22 3 io_l03p_3 w21 3 io_l02n_3/vrp_3 y22 3 io_l02p_3/vrn_3 y21 3 io_l01n_3 w20 3 io_l01p_3 aa20 4 io_l01n_4/busy/dout (1) ab19 4 io_l01p_4/init_b aa19 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 24 4 io_l02n_4/d0/din (1) v18 4 io_l02p_4/d1 v17 4 io_l03n_4/d2/alt_vrp_4 w18 4 io_l03p_4/d3/alt_vrn_4 y18 4 io_l04n_4/vref_4 aa18 4 io_l04p_4 ab18 4 io_l05n_4/vrp_4 w17 4 io_l05p_4/vrn_4 y17 4 io_l06n_4 aa17 4 io_l06p_4 ab17 4 io_l19n_4 v16 nc nc 4 io_l19p_4 v15 nc nc 4 io_l21n_4 w16 nc nc 4 io_l21p_4/vref_4 y16 nc nc 4 io_l22n_4 aa16 nc nc 4 io_l22p_4 ab16 nc nc 4 io_l24n_4 w15 nc nc 4 io_l24p_4 y15 nc nc 4 io_l49n_4 aa15 nc 4 io_l49p_4 ab15 nc 4 io_l51n_4 u14 nc 4 io_l51p_4/vref_4 v14 nc 4 io_l52n_4 w14 nc 4 io_l52p_4 y14 nc 4 io_l54n_4 aa14 nc 4 io_l54p_4 ab14 nc 4 io_l91n_4/vref_4 u13 4 io_l91p_4 v13 4 io_l92n_4 w13 4 io_l92p_4 y13 4 io_l93n_4 aa13 4 io_l93p_4 ab13 4 io_l94n_4/vref_4 u12 4 io_l94p_4 v12 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 25 4 io_l95n_4/gclk3s w12 4 io_l95p_4/gclk2p y12 4 io_l96n_4/gclk1s aa12 4 io_l96p_4/gclk0p ab12 5 io_l96n_5/gclk7s aa11 5 io_l96p_5/gclk6p y11 5 io_l95n_5/gclk5s w11 5 io_l95p_5/gclk4p v11 5 io_l94n_5 u11 5 io_l94p_5/vref_5 u10 5 io_l93n_5 ab10 5 io_l93p_5 aa10 5 io_l92n_5 y10 5 io_l92p_5 w10 5 io_l91n_5 v10 5 io_l91p_5/vref_5 v9 5 io_l54n_5 ab9 nc 5 io_l54p_5 aa9 nc 5 io_l52n_5 y9 nc 5 io_l52p_5 w9 nc 5 io_l51n_5/vref_5 ab8 nc 5 io_l51p_5 aa8 nc 5 io_l49n_5 y8 nc 5 io_l49p_5 w8 nc 5 io_l24n_5 u9 nc nc 5 io_l24p_5 v8 nc nc 5 io_l22n_5 ab7 nc nc 5 io_l22p_5 aa7 nc nc 5 io_l21n_5/vref_5 y7 nc nc 5 io_l21p_5 w7 nc nc 5 io_l19n_5 ab6 nc nc 5 io_l19p_5 aa6 nc nc 5 io_l06n_5 y6 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 26 5 io_l06p_5 w6 5 io_l05n_5/vrp_5 v7 5 io_l05p_5/vrn_5 v6 5 io_l04n_5 ab5 5 io_l04p_5/vref_5 aa5 5 io_l03n_5/d4/alt_vrp_5 y5 5 io_l03p_5/d5/alt_vrn_5 w5 5 io_l02n_5/d6 ab4 5 io_l02p_5/d7 aa4 5 io_l01n_5/rdwr_b y4 5 io_l01p_5/cs_b aa3 6 io_l01p_6 v5 6 io_l01n_6 u5 6 io_l02p_6/vrn_6 y2 6 io_l02n_6/vrp_6 y1 6 io_l03p_6 v4 6 io_l03n_6/vref_6 v3 6 io_l04p_6 w2 6 io_l04n_6 w1 6 io_l06p_6 u4 6 io_l06n_6 u3 6 io_l19p_6 v2 nc nc 6 io_l19n_6 v1 nc nc 6 io_l21p_6 u2 nc nc 6 io_l21n_6/vref_6 u1 nc nc 6 io_l22p_6 t5 nc nc 6 io_l22n_6 r5 nc nc 6 io_l24p_6 t4 nc nc 6 io_l24n_6 t3 nc nc 6 io_l43p_6 t2 6 io_l43n_6 t1 6 io_l45p_6 r4 6 io_l45n_6/vref_6 r3 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 27 6 io_l46p_6 r2 6 io_l46n_6 r1 6 io_l48p_6 p6 6 io_l48n_6 p5 6 io_l49p_6 p4 nc 6 io_l49n_6 p3 nc 6 io_l51p_6 p2 nc 6 io_l51n_6/vref_6 p1 nc 6 io_l52p_6 n6 nc 6 io_l52n_6 n5 nc 6 io_l54p_6 n4 nc 6 io_l54n_6 n3 nc 6 io_l91p_6 n2 6 io_l91n_6 n1 6 io_l93p_6 m6 6 io_l93n_6/vref_6 m5 6 io_l94p_6 m4 6 io_l94n_6 m3 6 io_l96p_6 m2 6 io_l96n_6 m1 7 io_l96p_7 l2 7 io_l96n_7 l3 7 io_l94p_7 l4 7 io_l94n_7 l5 7 io_l93p_7/vref_7 k1 7 io_l93n_7 k2 7 io_l91p_7 k3 7 io_l91n_7 k4 7 io_l54p_7 l6 nc 7 io_l54n_7 k6 nc 7 io_l52p_7 k5 nc 7 io_l52n_7 j5 nc 7 io_l51p_7/vref_7 j1 nc ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 28 7 io_l51n_7 j2 nc 7 io_l49p_7 j3 nc 7 io_l49n_7 j4 nc 7 io_l48p_7 h1 7 io_l48n_7 h2 7 io_l46p_7 h3 7 io_l46n_7 h4 7 io_l45p_7/vref_7 j6 7 io_l45n_7 h5 7 io_l43p_7 g1 7 io_l43n_7 g2 7 io_l24p_7 g3 nc nc 7 io_l24n_7 g4 nc nc 7 io_l22p_7 f1 nc nc 7 io_l22n_7 f2 nc nc 7 io_l21p_7/vref_7 f3 nc nc 7 io_l21n_7 f4 nc nc 7 io_l19p_7 g5 nc nc 7 io_l19n_7 f5 nc nc 7 io_l06p_7 e1 7 io_l06n_7 e2 7 io_l04p_7 e3 7 io_l04n_7 e4 7 io_l03p_7/vref_7 d1 7 io_l03n_7 d2 7 io_l02p_7/vrn_7 c1 7 io_l02n_7/vrp_7 c2 7 io_l01p_7 e5 7 io_l01n_7 e6 0 vcco_0 g11 0 vcco_0 g10 0 vcco_0 g9 0 vcco_0 f8 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 29 0 vcco_0 f7 1 vcco_1 g14 1 vcco_1 g13 1 vcco_1 g12 1 vcco_1 f16 1 vcco_1 f15 2 vcco_2 l16 2 vcco_2 k16 2 vcco_2 j16 2 vcco_2 h17 2 vcco_2 g17 3 vcco_3 t17 3 vcco_3 r17 3 vcco_3 p16 3 vcco_3 n16 3 vcco_3 m16 4 vcco_4 u16 4 vcco_4 u15 4 vcco_4 t14 4 vcco_4 t13 4 vcco_4 t12 5 vcco_5 u8 5 vcco_5 u7 5 vcco_5 t11 5 vcco_5 t10 5 vcco_5 t9 6 vcco_6 t6 6 vcco_6 r6 6 vcco_6 p7 6 vcco_6 n7 6 vcco_6 m7 7 vcco_7 l7 7 vcco_7 k7 7 vcco_7 j7 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 30 7 vcco_7 h6 7 vcco_7 g6 na cclk y19 na prog_b a2 na done ab20 na m0 ab2 na m1 w3 na m2 ab3 na hswap_en b3 na tck c19 na tdi d3 na tdo d20 na tms b20 na pwrdwn_b ab21 na dxn d5 na dxp a3 na vbatt a21 na rsvd a20 na vccaux ab11 na vccaux aa22 na vccaux aa1 na vccaux m22 na vccaux l1 na vccaux b22 na vccaux b1 na vccaux a12 na vccint u17 na vccint u6 na vccint t16 na vccint t15 na vccint t8 na vccint t7 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 31 na vccint r16 na vccint r7 na vccint h16 na vccint h7 na vccint g16 na vccint g15 na vccint g8 na vccint g7 na vccint f17 na vccint f6 na gnd ab22 na gnd ab1 na gnd aa21 na gnd aa2 na gnd y20 na gnd y3 na gnd w19 na gnd w4 na gnd p14 na gnd p13 na gnd p12 na gnd p11 na gnd p10 na gnd p9 na gnd n14 na gnd n13 na gnd n12 na gnd n11 na gnd n10 na gnd n9 na gnd m14 na gnd m13 na gnd m12 na gnd m11 ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 32 na gnd m10 na gnd m9 na gnd l14 na gnd l13 na gnd l12 na gnd l11 na gnd l10 na gnd l9 na gnd k14 na gnd k13 na gnd k12 na gnd k11 na gnd k10 na gnd k9 na gnd j14 na gnd j13 na gnd j12 na gnd j11 na gnd j10 na gnd j9 na gnd d19 na gnd d4 na gnd c20 na gnd c3 na gnd b21 na gnd b2 na gnd a22 na gnd a1 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 7 : fg456 bga ? xc2v250, xc2v500, and xc2v1000 bank pin description pin number no connect in xc2v250 no connect in xc2v500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 33 fg456 fine-pitch bga package specifications (1.00mm pitch) figure 3: fg456 fine-pitch bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 34 fg676 fine-pitch bga package as shown in ta b l e 8 , xc2v1500, XC2V2000, and xc2v3000 virtex-ii devices are available in the fg676 fine-pitch bga package. pins in the xc2v1500, XC2V2000, and xc2v3000 devices are the same, except for the pin differences in the xc2v1500 and XC2V2000 devices shown in the no connect columns. following this table are the fg676 fine-pitch bga package specifications (1.00mm pitch) . ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000 0 io_l01n_0 d6 0 io_l01p_0 c6 0 io_l02n_0 b1 0 io_l02p_0 a2 0 io_l03n_0/vrp_0 d7 0 io_l03p_0/vrn_0 c7 0 io_l04n_0/vref_0 b3 0 io_l04p_0 a3 0 io_l05n_0 g6 0 io_l05p_0 g7 0 io_l06n_0 e6 0 io_l06p_0 e7 0 io_l19n_0 b4 0 io_l19p_0 a4 0 io_l21n_0 b5 0 io_l21p_0/vref_0 a5 0 io_l22n_0 b6 0 io_l22p_0 a6 0 io_l24n_0 a7 0 io_l24p_0 a8 0 io_l25n_0 e8 nc nc 0 io_l25p_0 d8 nc nc 0 io_l27n_0 g8 nc nc 0 io_l27p_0/vref_0 f8 nc nc 0 io_l49n_0 c8 0 io_l49p_0 b8 0 io_l51n_0 d9 0 io_l51p_0/vref_0 e9 0 io_l52n_0 f9 0 io_l52p_0 g9 0 io_l54n_0 b9 0 io_l54p_0 a9 0 io_l67n_0 c9
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 35 0 io_l67p_0 c10 0 io_l69n_0 f10 0 io_l69p_0/vref_0 g10 0 io_l70n_0 e10 0 io_l70p_0 d10 0 io_l72n_0 a10 0 io_l72p_0 a11 0 io_l73n_0 f11 nc 0 io_l73p_0 e11 nc 0 io_l75n_0 g11 nc 0 io_l75p_0/vref_0 h11 nc 0 io_l76n_0 d11 nc 0 io_l76p_0 c11 nc 0 io_l78n_0 b11 nc 0 io_l78p_0 b12 nc 0 io_l91n_0/vref_0 g12 0 io_l91p_0 h12 0 io_l92n_0 f12 0 io_l92p_0 e12 0 io_l93n_0 d12 0 io_l93p_0 c12 0 io_l94n_0/vref_0 g13 0 io_l94p_0 h13 0 io_l95n_0/gclk7p f13 0 io_l95p_0/gclk6s e13 0 io_l96n_0/gclk5p d13 0 io_l96p_0/gclk4s c13 1 io_l96n_1/gclk3p h14 1 io_l96p_1/gclk2s h15 1 io_l95n_1/gclk1p g14 1 io_l95p_1/gclk0s f14 1 io_l94n_1 e14 1 io_l94p_1/vref_1 d14 1 io_l93n_1 a12 1 io_l93p_1 a13 1 io_l92n_1 a14 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 36 1 io_l92p_1 a15 1 io_l91n_1 b15 1 io_l91p_1/vref_1 c15 1 io_l78n_1 d15 nc 1 io_l78p_1 e15 nc 1 io_l76n_1 f15 nc 1 io_l76p_1 g15 nc 1 io_l75n_1/vref_1 g16 nc 1 io_l75p_1 f16 nc 1 io_l73n_1 a16 nc 1 io_l73p_1 a17 nc 1 io_l72n_1 b16 1 io_l72p_1 c16 1 io_l70n_1 d16 1 io_l70p_1 e16 1 io_l69n_1/vref_1 c17 1 io_l69p_1 d17 1 io_l67n_1 h16 1 io_l67p_1 g17 1 io_l54n_1 e17 1 io_l54p_1 f17 1 io_l52n_1 a18 1 io_l52p_1 a19 1 io_l51n_1/vref_1 e18 1 io_l51p_1 d18 1 io_l49n_1 b18 1 io_l49p_1 c18 1 io_l27n_1/vref_1 f19 nc nc 1 io_l27p_1 f18 nc nc 1 io_l25n_1 g18 nc nc 1 io_l25p_1 g19 nc nc 1 io_l24n_1 b19 1 io_l24p_1 c19 1 io_l22n_1 d19 1 io_l22p_1 e19 1 io_l21n_1/vref_1 a20 1 io_l21p_1 a21 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 37 1 io_l19n_1 e20 1 io_l19p_1 f20 1 io_l06n_1 b21 1 io_l06p_1 b22 1 io_l05n_1 a22 1 io_l05p_1 a23 1 io_l04n_1 c21 1 io_l04p_1/vref_1 d21 1 io_l03n_1/vrp_1 c20 1 io_l03p_1/vrn_1 d20 1 io_l02n_1 a24 1 io_l02p_1 a25 1 io_l01n_1 b23 1 io_l01p_1 b24 2 io_l01n_2 b26 2 io_l01p_2 c26 2 io_l02n_2/vrp_2 g20 2 io_l02p_2/vrn_2 h20 2 io_l03n_2 c25 2 io_l03p_2/vref_2 d25 2 io_l04n_2 e23 2 io_l04p_2 e24 2 io_l06n_2 g21 2 io_l06p_2 g22 2 io_l19n_2 d26 2 io_l19p_2 e26 2 io_l21n_2 f23 2 io_l21p_2/vref_2 f24 2 io_l22n_2 e25 2 io_l22p_2 f25 2 io_l24n_2 h22 2 io_l24p_2 h21 2 io_l25n_2 g23 nc nc 2 io_l25p_2 g24 nc nc 2 io_l43n_2 f26 2 io_l43p_2 g26 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 38 2 io_l45n_2 h23 2 io_l45p_2/vref_2 h24 2 io_l46n_2 j21 2 io_l46p_2 j20 2 io_l48n_2 h25 2 io_l48p_2 h26 2 io_l49n_2 j22 2 io_l49p_2 j23 2 io_l51n_2 k21 2 io_l51p_2/vref_2 k22 2 io_l52n_2 k20 2 io_l52p_2 l20 2 io_l54n_2 j24 2 io_l54p_2 j25 2 io_l67n_2 k23 2 io_l67p_2 k24 2 io_l69n_2 j26 2 io_l69p_2/vref_2 k26 2 io_l70n_2 l22 2 io_l70p_2 l21 2 io_l72n_2 l25 2 io_l72p_2 l26 2 io_l73n_2 l19 nc 2 io_l73p_2 m19 nc 2 io_l75n_2 l23 nc 2 io_l75p_2/vref_2 l24 nc 2 io_l76n_2 m22 nc 2 io_l76p_2 m21 nc 2 io_l78n_2 m23 nc 2 io_l78p_2 m24 nc 2 io_l91n_2 m25 2 io_l91p_2 m26 2 io_l93n_2 m20 2 io_l93p_2/vref_2 n20 2 io_l94n_2 n22 2 io_l94p_2 n21 2 io_l96n_2 n24 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 39 2 io_l96p_2 n23 3 io_l96n_3 n26 3 io_l96p_3 p26 3 io_l94n_3 p23 3 io_l94p_3 p22 3 io_l93n_3/vref_3 p19 3 io_l93p_3 n19 3 io_l91n_3 p21 3 io_l91p_3 p20 3 io_l78n_3 r26 nc 3 io_l78p_3 r25 nc 3 io_l76n_3 r20 nc 3 io_l76p_3 r19 nc 3 io_l75n_3/vref_3 r24 nc 3 io_l75p_3 r23 nc 3 io_l73n_3 r22 nc 3 io_l73p_3 r21 nc 3 io_l72n_3 t26 3 io_l72p_3 t25 3 io_l70n_3 t20 3 io_l70p_3 t19 3 io_l69n_3/vref_3 t24 3 io_l69p_3 t23 3 io_l67n_3 t22 3 io_l67p_3 t21 3 io_l54n_3 u26 3 io_l54p_3 v26 3 io_l52n_3 u24 3 io_l52p_3 u23 3 io_l51n_3/vref_3 u22 3 io_l51p_3 u21 3 io_l49n_3 v25 3 io_l49p_3 v24 3 io_l48n_3 v23 3 io_l48p_3 v22 3 io_l46n_3 w26 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 40 3 io_l46p_3 y26 3 io_l45n_3/vref_3 u20 3 io_l45p_3 v20 3 io_l43n_3 w25 3 io_l43p_3 w24 3 io_l25n_3 v21 nc nc 3 io_l25p_3 w21 nc nc 3 io_l24n_3 aa26 3 io_l24p_3 aa25 3 io_l22n_3 y24 3 io_l22p_3 y23 3 io_l21n_3/vref_3 w22 3 io_l21p_3 w23 3 io_l19n_3 ab26 3 io_l19p_3 ab25 3 io_l06n_3 ac26 3 io_l06p_3 ac25 3 io_l04n_3 ad26 3 io_l04p_3 ad25 3 io_l03n_3/vref_3 aa24 3 io_l03p_3 aa23 3 io_l02n_3/vrp_3 ab24 3 io_l02p_3/vrn_3 ab23 3 io_l01n_3 y22 3 io_l01p_3 aa22 4 io_l01n_4/busy/dout (1) ad21 4 io_l01p_4/init_b ac21 4 io_l02n_4/d0/din (1) y20 4 io_l02p_4/d1 y19 4 io_l03n_4/d2/alt_vrp_4 aa20 4 io_l03p_4/d3/alt_vrn_4 ab20 4 io_l04n_4/vref_4 ac22 4 io_l04p_4 ae21 4 io_l05n_4/vrp_4 ae26 4 io_l05p_4/vrn_4 af25 4 io_l06n_4 w20 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 41 4 io_l06p_4 y21 4 io_l19n_4 ae24 4 io_l19p_4 af24 4 io_l21n_4 ae23 4 io_l21p_4/vref_4 af23 4 io_l22n_4 ae22 4 io_l22p_4 af22 4 io_l24n_4 af21 4 io_l24p_4 af20 4 io_l25n_4 aa19 nc nc 4 io_l25p_4 ab19 nc nc 4 io_l27n_4 ad20 nc nc 4 io_l27p_4/vref_4 ac20 nc nc 4 io_l28n_4 ac19 nc nc 4 io_l28p_4 ad19 nc nc 4 io_l49n_4 ae19 4 io_l49p_4 af19 4 io_l51n_4 aa18 4 io_l51p_4/vref_4 ab18 4 io_l52n_4 y18 4 io_l52p_4 y17 4 io_l54n_4 ac18 4 io_l54p_4 ad18 4 io_l67n_4 ae18 4 io_l67p_4 af18 4 io_l69n_4 aa17 4 io_l69p_4/vref_4 ab17 4 io_l70n_4 ac17 4 io_l70p_4 ad17 4 io_l72n_4 af17 4 io_l72p_4 af16 4 io_l73n_4 ab16 nc 4 io_l73p_4 ac16 nc 4 io_l75n_4 aa16 nc 4 io_l75p_4/vref_4 y16 nc 4 io_l76n_4 ad16 nc 4 io_l76p_4 ae16 nc ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 42 4 io_l78n_4 y15 nc 4 io_l78p_4 aa15 nc 4 io_l91n_4/vref_4 w15 4 io_l91p_4 w16 4 io_l92n_4 ab15 4 io_l92p_4 ac15 4 io_l93n_4 ad15 4 io_l93p_4 ae15 4 io_l94n_4/vref_4 w14 4 io_l94p_4 y14 4 io_l95n_4/gclk3s aa14 4 io_l95p_4/gclk2p ab14 4 io_l96n_4/gclk1s ac14 4 io_l96p_4/gclk0p ad14 5 io_l96n_5/gclk7s ac13 5 io_l96p_5/gclk6p ab13 5 io_l95n_5/gclk5s aa13 5 io_l95p_5/gclk4p y13 5 io_l94n_5 w13 5 io_l94p_5/vref_5 w12 5 io_l93n_5 af15 5 io_l93p_5 af14 5 io_l92n_5 af13 5 io_l92p_5 af12 5 io_l91n_5 ae12 5 io_l91p_5/vref_5 ad12 5 io_l78n_5 ac12 nc 5 io_l78p_5 ab12 nc 5 io_l76n_5 aa12 nc 5 io_l76p_5 y12 nc 5 io_l75n_5/vref_5 af11 nc 5 io_l75p_5 af10 nc 5 io_l73n_5 ae11 nc 5 io_l73p_5 ad11 nc 5 io_l72n_5 ac11 5 io_l72p_5 ab11 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 43 5 io_l70n_5 w11 5 io_l70p_5 y10 5 io_l69n_5/vref_5 y11 5 io_l69p_5 aa11 5 io_l67n_5 af9 5 io_l67p_5 af8 5 io_l54n_5 ae9 5 io_l54p_5 ad9 5 io_l52n_5 ab10 5 io_l52p_5 aa10 5 io_l51n_5/vref_5 ad10 5 io_l51p_5 ac10 5 io_l49n_5 ae8 5 io_l49p_5 af7 5 io_l28n_5 ad8 nc nc 5 io_l28p_5 ac8 nc nc 5 io_l27n_5/vref_5 ab9 nc nc 5 io_l27p_5 ac9 nc nc 5 io_l25n_5 aa9 nc nc 5 io_l25p_5 y9 nc nc 5 io_l24n_5 af6 5 io_l24p_5 ae6 5 io_l22n_5 ab8 5 io_l22p_5 aa8 5 io_l21n_5/vref_5 ac7 5 io_l21p_5 ad7 5 io_l19n_5 af5 5 io_l19p_5 ae5 5 io_l06n_5 af4 5 io_l06p_5 ae4 5 io_l05n_5/vrp_5 af3 5 io_l05p_5/vrn_5 ae3 5 io_l04n_5 y8 5 io_l04p_5/vref_5 y7 5 io_l03n_5/d4/alt_vrp_5 ab7 5 io_l03p_5/d5/alt_vrn_5 aa7 5 io_l02n_5/d6 ad6 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 44 5 io_l02p_5/d7 ac6 5 io_l01n_5/rdwr_b ab6 5 io_l01p_5/cs_b ac5 6 io_l01p_6 af2 6 io_l01n_6 ae1 6 io_l02p_6/vrn_6 ab4 6 io_l02n_6/vrp_6 ab3 6 io_l03p_6 ad2 6 io_l03n_6/vref_6 ad1 6 io_l04p_6 ac2 6 io_l04n_6 ac1 6 io_l06p_6 ab2 6 io_l06n_6 ab1 6 io_l19p_6 aa4 6 io_l19n_6 aa3 6 io_l21p_6 y6 6 io_l21n_6/vref_6 y5 6 io_l22p_6 w6 6 io_l22n_6 w7 6 io_l24p_6 aa2 6 io_l24n_6 aa1 6 io_l25p_6 y4 nc nc 6 io_l25n_6 y3 nc nc 6 io_l43p_6 w5 6 io_l43n_6 w4 6 io_l45p_6 w2 6 io_l45n_6/vref_6 w3 6 io_l46p_6 y1 6 io_l46n_6 w1 6 io_l48p_6 v6 6 io_l48n_6 v7 6 io_l49p_6 v5 6 io_l49n_6 v4 6 io_l51p_6 v3 6 io_l51n_6/vref_6 v2 6 io_l52p_6 v1 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 45 6 io_l52n_6 u1 6 io_l54p_6 u7 6 io_l54n_6 t7 6 io_l67p_6 u4 6 io_l67n_6 u3 6 io_l69p_6 u6 6 io_l69n_6/vref_6 u5 6 io_l70p_6 t5 6 io_l70n_6 t6 6 io_l72p_6 t8 6 io_l72n_6 r8 6 io_l73p_6 t2 nc 6 io_l73n_6 t1 nc 6 io_l75p_6 t4 nc 6 io_l75n_6/vref_6 t3 nc 6 io_l76p_6 r6 nc 6 io_l76n_6 r5 nc 6 io_l78p_6 r4 nc 6 io_l78n_6 r3 nc 6 io_l91p_6 r2 6 io_l91n_6 r1 6 io_l93p_6 r7 6 io_l93n_6/vref_6 p7 6 io_l94p_6 p6 6 io_l94n_6 p5 6 io_l96p_6 p4 6 io_l96n_6 p3 7 io_l96p_7 p1 7 io_l96n_7 n1 7 io_l94p_7 n4 7 io_l94n_7 n5 7 io_l93p_7/vref_7 n6 7 io_l93n_7 n7 7 io_l91p_7 p8 7 io_l91n_7 n8 7 io_l78p_7 m1 nc ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 46 7 io_l78n_7 m2 nc 7 io_l76p_7 m5 nc 7 io_l76n_7 m6 nc 7 io_l75p_7/vref_7 m3 nc 7 io_l75n_7 m4 nc 7 io_l73p_7 m7 nc 7 io_l73n_7 m8 nc 7 io_l72p_7 l1 7 io_l72n_7 l2 7 io_l70p_7 l5 7 io_l70n_7 l6 7 io_l69p_7/vref_7 l3 7 io_l69n_7 l4 7 io_l67p_7 k1 7 io_l67n_7 j1 7 io_l54p_7 k3 7 io_l54n_7 k4 7 io_l52p_7 k5 7 io_l52n_7 k6 7 io_l51p_7/vref_7 l8 7 io_l51n_7 l7 7 io_l49p_7 j2 7 io_l49n_7 h1 7 io_l48p_7 j3 7 io_l48n_7 j4 7 io_l46p_7 j5 7 io_l46n_7 j6 7 io_l45p_7/vref_7 h5 7 io_l45n_7 h4 7 io_l43p_7 k7 7 io_l43n_7 j7 7 io_l25p_7 h2 nc nc 7 io_l25n_7 h3 nc nc 7 io_l24p_7 g1 7 io_l24n_7 f1 7 io_l22p_7 g3 7 io_l22n_7 g4 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 47 7 io_l21p_7/vref_7 f3 7 io_l21n_7 f2 7 io_l19p_7 h6 7 io_l19n_7 h7 7 io_l06p_7 e1 7 io_l06n_7 e2 7 io_l04p_7 d1 7 io_l04n_7 d2 7 io_l03p_7/vref_7 c1 7 io_l03n_7 c2 7 io_l02p_7/vrn_7 e3 7 io_l02n_7/vrp_7 e4 7 io_l01p_7 g5 7 io_l01n_7 f4 0 vcco_0 j13 0 vcco_0 j12 0 vcco_0 j11 0 vcco_0 h10 0 vcco_0 h9 0 vcco_0 b10 0 vcco_0 b7 1 vcco_1 b17 1 vcco_1 j16 1 vcco_1 j15 1 vcco_1 j14 1 vcco_1 h18 1 vcco_1 h17 1 vcco_1 b20 2 vcco_2 n18 2 vcco_2 m18 2 vcco_2 l18 2 vcco_2 k25 2 vcco_2 k19 2 vcco_2 j19 2 vcco_2 g25 3 vcco_3 y25 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 48 3 vcco_3 v19 3 vcco_3 u25 3 vcco_3 u19 3 vcco_3 t18 3 vcco_3 r18 3 vcco_3 p18 4 vcco_4 ae20 4 vcco_4 ae17 4 vcco_4 w18 4 vcco_4 w17 4 vcco_4 v16 4 vcco_4 v15 4 vcco_4 v14 5 vcco_5 ae10 5 vcco_5 ae7 5 vcco_5 w10 5 vcco_5 w9 5 vcco_5 v13 5 vcco_5 v12 5 vcco_5 v11 6 vcco_6 y2 6 vcco_6 v8 6 vcco_6 u8 6 vcco_6 u2 6 vcco_6 t9 6 vcco_6 r9 6 vcco_6 p9 7 vcco_7 n9 7 vcco_7 m9 7 vcco_7 l9 7 vcco_7 k8 7 vcco_7 k2 7 vcco_7 j8 7 vcco_7 g2 na cclk ab21 na prog_b c4 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 49 na done ad22 na m0 ad4 na m1 aa5 na m2 ad5 na hswap_en d5 na tck e21 na tdi f5 na tdo f22 na tms d22 na pwrdwn_b ad23 na dxn f7 na dxp c5 na vbatt c23 na rsvd c22 na vccaux ad13 na vccaux ac24 na vccaux ac3 na vccaux p24 na vccaux n3 na vccaux d24 na vccaux d3 na vccaux c14 na vccint w19 na vccint w8 na vccint v18 na vccint v17 na vccint v10 na vccint v9 na vccint u18 na vccint u9 na vccint k18 na vccint k9 na vccint j18 na vccint j17 na vccint j10 na vccint j9 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 50 na vccint h19 na vccint h8 na gnd af26 na gnd af1 na gnd ae25 na gnd ae14 na gnd ae13 na gnd ae2 na gnd ad24 na gnd ad3 na gnd ac23 na gnd ac4 na gnd ab22 na gnd ab5 na gnd aa21 na gnd aa6 na gnd u17 na gnd u16 na gnd u15 na gnd u14 na gnd u13 na gnd u12 na gnd u11 na gnd u10 na gnd t17 na gnd t16 na gnd t15 na gnd t14 na gnd t13 na gnd t12 na gnd t11 na gnd t10 na gnd r17 na gnd r16 na gnd r15 na gnd r14 na gnd r13 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 51 na gnd r12 na gnd r11 na gnd r10 na gnd p25 na gnd p17 na gnd p16 na gnd p15 na gnd p14 na gnd p13 na gnd p12 na gnd p11 na gnd p10 na gnd p2 na gnd n25 na gnd n17 na gnd n16 na gnd n15 na gnd n14 na gnd n13 na gnd n12 na gnd n11 na gnd n10 na gnd n2 na gnd m17 na gnd m16 na gnd m15 na gnd m14 na gnd m13 na gnd m12 na gnd m11 na gnd m10 na gnd l17 na gnd l16 na gnd l15 na gnd l14 na gnd l13 na gnd l12 ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 52 na gnd l11 na gnd l10 na gnd k17 na gnd k16 na gnd k15 na gnd k14 na gnd k13 na gnd k12 na gnd k11 na gnd k10 na gnd f21 na gnd f6 na gnd e22 na gnd e5 na gnd d23 na gnd d4 na gnd c24 na gnd c3 na gnd b25 na gnd b14 na gnd b13 na gnd b2 na gnd a26 na gnd a1 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 8 : fg676 bga ? xc2v1500, XC2V2000, and xc2v3000 bank pin description pin number no connect in xc2v1500 no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 53 fg676 fine-pitch bga package specifications (1.00mm pitch) figure 4: fg676 fine-pitch bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 54 bg575 standard bga package as shown in ta b l e 9 , xc2v1000, xc2v1500, and XC2V2000 virtex-ii devices are available in the bg575 bga package. pins in the xc2v1000, xc2v1500, and XC2V2000 devices are the same, except for the pin differences in the xc2v1000 and xc2v1500 devices shown in the no connect columns. following this table are the bg575 standard bga package specifications (1.27mm pitch) . ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500 0 io_l01n_0 a3 0 io_l01p_0 a4 0 io_l02n_0 d5 0 io_l02p_0 c5 0 io_l03n_0/vrp_0 e6 0 io_l03p_0/vrn_0 d6 0 io_l04n_0/vref_0 f7 0 io_l04p_0 e7 0 io_l05n_0 g8 0 io_l05p_0 h9 0 io_l06n_0 a5 0 io_l06p_0 a6 0 io_l19n_0 b5 0 io_l19p_0 b6 0 io_l21n_0 d7 0 io_l21p_0/vref_0 c7 0 io_l22n_0 f8 0 io_l22p_0 e8 0 io_l24n_0 g9 0 io_l24p_0 f9 0 io_l49n_0 g10 0 io_l49p_0 h10 0 io_l51n_0 b7 0 io_l51p_0/vref_0 b8 0 io_l52n_0 d8 0 io_l52p_0 c8 0 io_l54n_0 e9 0 io_l54p_0 d9 0 io_l67n_0 a8 nc 0 io_l67p_0 a9 nc 0 io_l69n_0 c9 nc
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 55 0 io_l69p_0/vref_0 b9 nc 0 io_l70n_0 f10 nc 0 io_l70p_0 e10 nc 0 io_l72n_0 a10 nc 0 io_l72p_0 a11 nc 0 io_l73n_0 c10 nc nc 0 io_l73p_0 b10 nc nc 0 io_l91n_0/vref_0 d11 0 io_l91p_0 c11 0 io_l92n_0 g11 0 io_l92p_0 e11 0 io_l93n_0 c12 0 io_l93p_0 b12 0 io_l94n_0/vref_0 e12 0 io_l94p_0 d12 0 io_l95n_0/gclk7p g12 0 io_l95p_0/gclk6s f12 0 io_l96n_0/gclk5p h11 0 io_l96p_0/gclk4s h12 1 io_l96n_1/gclk3p a13 1 io_l96p_1/gclk2s a14 1 io_l95n_1/gclk1p b13 1 io_l95p_1/gclk0s c13 1 io_l94n_1 d13 1 io_l94p_1/vref_1 e13 1 io_l93n_1 f13 1 io_l93p_1 g13 1 io_l92n_1 h13 1 io_l92p_1 h14 1 io_l91n_1 c14 1 io_l91p_1/vref_1 d14 1 io_l73n_1 e14 nc nc 1 io_l73p_1 g14 nc nc 1 io_l72n_1 a15 nc 1 io_l72p_1 a16 nc ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 56 1 io_l70n_1 b15 nc 1 io_l70p_1 c15 nc 1 io_l69n_1/vref_1 e15 nc 1 io_l69p_1 f15 nc 1 io_l67n_1 g15 nc 1 io_l67p_1 h15 nc 1 io_l54n_1 b16 1 io_l54p_1 c16 1 io_l52n_1 d16 1 io_l52p_1 e16 1 io_l51n_1/vref_1 f16 1 io_l51p_1 g16 1 io_l49n_1 a17 1 io_l49p_1 a19 1 io_l24n_1 b17 1 io_l24p_1 b18 1 io_l22n_1 c17 1 io_l22p_1 d17 1 io_l21n_1/vref_1 f17 1 io_l21p_1 e17 1 io_l19n_1 a20 1 io_l19p_1 a21 1 io_l06n_1 b19 1 io_l06p_1 b20 1 io_l05n_1 c18 1 io_l05p_1 d18 1 io_l04n_1 c20 1 io_l04p_1/vref_1 d20 1 io_l03n_1/vrp_1 d19 1 io_l03p_1/vrn_1 e19 1 io_l02n_1 e18 1 io_l02p_1 f18 1 io_l01n_1 h16 1 io_l01p_1 g17 2 io_l01n_2 d22 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 57 2 io_l01p_2 d23 2 io_l02n_2/vrp_2 e21 2 io_l02p_2/vrn_2 e22 2 io_l03n_2 f21 2 io_l03p_2/vref_2 f20 2 io_l04n_2 g20 2 io_l04p_2 g19 2 io_l06n_2 h18 2 io_l06p_2 j17 2 io_l19n_2 d24 2 io_l19p_2 e23 2 io_l21n_2 e24 2 io_l21p_2/vref_2 f24 2 io_l22n_2 f23 2 io_l22p_2 g23 2 io_l24n_2 g21 2 io_l24p_2 g22 2 io_l43n_2 h19 2 io_l43p_2 h20 2 io_l45n_2 j18 2 io_l45p_2/vref_2 j19 2 io_l46n_2 k17 2 io_l46p_2 k18 2 io_l48n_2 h23 2 io_l48p_2 h24 2 io_l49n_2 h21 2 io_l49p_2 h22 2 io_l51n_2 j24 2 io_l51p_2/vref_2 k24 2 io_l52n_2 j22 2 io_l52p_2 j23 2 io_l54n_2 j20 2 io_l54p_2 j21 2 io_l67n_2 k19 nc 2 io_l67p_2 k20 nc 2 io_l69n_2 l17 nc ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 58 2 io_l69p_2/vref_2 l18 nc 2 io_l70n_2 k23 nc 2 io_l70p_2 l24 nc 2 io_l72n_2 k22 nc 2 io_l72p_2 l22 nc 2 io_l73n_2 l21 nc nc 2 io_l73p_2 l20 nc nc 2 io_l91n_2 m23 2 io_l91p_2 n24 2 io_l93n_2 m21 2 io_l93p_2/vref_2 m22 2 io_l94n_2 m19 2 io_l94p_2 m20 2 io_l96n_2 m17 2 io_l96p_2 m18 3 io_l96n_3 n23 3 io_l96p_3 n22 3 io_l94n_3 n20 3 io_l94p_3 n21 3 io_l93n_3/vref_3 n19 3 io_l93p_3 n18 3 io_l91n_3 n17 3 io_l91p_3 p17 3 io_l73n_3 p24 nc nc 3 io_l73p_3 r24 nc nc 3 io_l72n_3 r23 nc 3 io_l72p_3 r22 nc 3 io_l70n_3 p22 nc 3 io_l70p_3 p21 nc 3 io_l69n_3/vref_3 p20 nc 3 io_l69p_3 p18 nc 3 io_l67n_3 t24 nc 3 io_l67p_3 u24 nc 3 io_l54n_3 t23 3 io_l54p_3 t22 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 59 3 io_l52n_3 t21 3 io_l52p_3 t20 3 io_l51n_3/vref_3 r20 3 io_l51p_3 r19 3 io_l49n_3 w24 3 io_l49p_3 w23 3 io_l48n_3 u23 3 io_l48p_3 v23 3 io_l46n_3 u22 3 io_l46p_3 u21 3 io_l45n_3/vref_3 v22 3 io_l45p_3 v21 3 io_l43n_3 u19 3 io_l43p_3 u20 3 io_l24n_3 t19 3 io_l24p_3 t18 3 io_l22n_3 r18 3 io_l22p_3 r17 3 io_l21n_3/vref_3 y24 3 io_l21p_3 y23 3 io_l19n_3 aa24 3 io_l19p_3 ab24 3 io_l06n_3 aa23 3 io_l06p_3 aa22 3 io_l04n_3 y22 3 io_l04p_3 y21 3 io_l03n_3/vref_3 w21 3 io_l03p_3 w20 3 io_l02n_3/vrp_3 v20 3 io_l02p_3/vrn_3 v19 3 io_l01n_3 u18 3 io_l01p_3 t17 4 io_l01n_4/busy/dout (1) ad22 4 io_l01p_4/init_b ad21 4 io_l02n_4/d0/din (1) aa20 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 60 4 io_l02p_4/d1 ab20 4 io_l03n_4/d2/alt_vrp_4 y19 4 io_l03p_4/d3/alt_vrn_4 aa19 4 io_l04n_4/vref_4 w18 4 io_l04p_4 y18 4 io_l05n_4/vrp_4 u16 4 io_l05p_4/vrn_4 v17 4 io_l06n_4 ad20 4 io_l06p_4 ad19 4 io_l19n_4 ac20 4 io_l19p_4 ac19 4 io_l21n_4 aa18 4 io_l21p_4/vref_4 ab18 4 io_l22n_4 ac18 4 io_l22p_4 ac17 4 io_l24n_4 aa17 4 io_l24p_4 ab17 4 io_l49n_4 y17 4 io_l49p_4 w17 4 io_l51n_4 v16 4 io_l51p_4/vref_4 w16 4 io_l52n_4 ad17 4 io_l52p_4 ad16 4 io_l54n_4 ab16 4 io_l54p_4 ac16 4 io_l67n_4 y16 nc 4 io_l67p_4 aa16 nc 4 io_l69n_4 w15 nc 4 io_l69p_4/vref_4 y15 nc 4 io_l70n_4 u15 nc 4 io_l70p_4 v15 nc 4 io_l72n_4 ad15 nc 4 io_l72p_4 ad14 nc 4 io_l73n_4 ab15 nc nc 4 io_l73p_4 ac15 nc nc 4 io_l91n_4/vref_4 aa14 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 61 4 io_l91p_4 ab14 4 io_l92n_4 v14 4 io_l92p_4 y14 4 io_l93n_4 ab13 4 io_l93p_4 ac13 4 io_l94n_4/vref_4 y13 4 io_l94p_4 aa13 4 io_l95n_4/gclk3s v13 4 io_l95p_4/gclk2p w13 4 io_l96n_4/gclk1s u14 4 io_l96p_4/gclk0p u13 5 io_l96n_5/gclk7s ad12 5 io_l96p_5/gclk6p ad11 5 io_l95n_5/gclk5s ac12 5 io_l95p_5/gclk4p ab12 5 io_l94n_5 aa12 5 io_l94p_5/vref_5 y12 5 io_l93n_5 w12 5 io_l93p_5 v12 5 io_l92n_5 u12 5 io_l92p_5 u11 5 io_l91n_5 ab11 5 io_l91p_5/vref_5 aa11 5 io_l73n_5 y11 nc nc 5 io_l73p_5 v11 nc nc 5 io_l72n_5 ad10 nc 5 io_l72p_5 ad9 nc 5 io_l70n_5 ac10 nc 5 io_l70p_5 ab10 nc 5 io_l69n_5/vref_5 y10 nc 5 io_l69p_5 w10 nc 5 io_l67n_5 v10 nc 5 io_l67p_5 u10 nc 5 io_l54n_5 ac9 5 io_l54p_5 ab9 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 62 5 io_l52n_5 aa9 5 io_l52p_5 y9 5 io_l51n_5/vref_5 w9 5 io_l51p_5 v9 5 io_l49n_5 ad8 5 io_l49p_5 ad6 5 io_l24n_5 ac8 5 io_l24p_5 ac7 5 io_l22n_5 ab8 5 io_l22p_5 aa8 5 io_l21n_5/vref_5 w8 5 io_l21p_5 y8 5 io_l19n_5 ad5 5 io_l19p_5 ad4 5 io_l06n_5 ac6 5 io_l06p_5 ac5 5 io_l05n_5/vrp_5 ab7 5 io_l05p_5/vrn_5 aa7 5 io_l04n_5 ab5 5 io_l04p_5/vref_5 aa5 5 io_l03n_5/d4/alt_vrp_5 aa6 5 io_l03p_5/d5/alt_vrn_5 y6 5 io_l02n_5/d6 y7 5 io_l02p_5/d7 w7 5 io_l01n_5/rdwr_b v8 5 io_l01p_5/cs_b u9 6 io_l01p_6 ab2 6 io_l01n_6 ab1 6 io_l02p_6/vrn_6 aa3 6 io_l02n_6/vrp_6 aa2 6 io_l03p_6 y4 6 io_l03n_6/vref_6 y3 6 io_l04p_6 w4 6 io_l04n_6 w5 6 io_l06p_6 v5 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 63 6 io_l06n_6 v6 6 io_l19p_6 u7 6 io_l19n_6 t8 6 io_l21p_6 aa1 6 io_l21n_6/vref_6 y2 6 io_l22p_6 y1 6 io_l22n_6 w1 6 io_l24p_6 w2 6 io_l24n_6 v2 6 io_l43p_6 v4 6 io_l43n_6 v3 6 io_l45p_6 u6 6 io_l45n_6/vref_6 u5 6 io_l46p_6 t7 6 io_l46n_6 t6 6 io_l48p_6 r8 6 io_l48n_6 r7 6 io_l49p_6 u2 6 io_l49n_6 u1 6 io_l51p_6 u4 6 io_l51n_6/vref_6 u3 6 io_l52p_6 t1 6 io_l52n_6 r1 6 io_l54p_6 t3 6 io_l54n_6 t2 6 io_l67p_6 t5 nc 6 io_l67n_6 t4 nc 6 io_l69p_6 r6 nc 6 io_l69n_6/vref_6 r5 nc 6 io_l70p_6 p8 nc 6 io_l70n_6 p7 nc 6 io_l72p_6 r2 nc 6 io_l72n_6 p1 nc 6 io_l73p_6 r3 nc nc 6 io_l73n_6 p3 nc nc 6 io_l91p_6 p5 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 64 6 io_l91n_6 p4 6 io_l93p_6 n4 6 io_l93n_6/vref_6 n3 6 io_l94p_6 n6 6 io_l94n_6 n5 6 io_l96p_6 n8 6 io_l96n_6 n7 7 io_l96p_7 n2 7 io_l96n_7 m1 7 io_l94p_7 m2 7 io_l94n_7 m3 7 io_l93p_7/vref_7 m4 7 io_l93n_7 m5 7 io_l91p_7 m6 7 io_l91n_7 m7 7 io_l73p_7 m8 nc nc 7 io_l73n_7 l8 nc nc 7 io_l72p_7 l1 nc 7 io_l72n_7 k1 nc 7 io_l70p_7 k2 nc 7 io_l70n_7 k3 nc 7 io_l69p_7/vref_7 l3 nc 7 io_l69n_7 l4 nc 7 io_l67p_7 l5 nc 7 io_l67n_7 l7 nc 7 io_l54p_7 j1 7 io_l54n_7 h1 7 io_l52p_7 j2 7 io_l52n_7 j3 7 io_l51p_7/vref_7 j4 7 io_l51n_7 j5 7 io_l49p_7 k5 7 io_l49n_7 k6 7 io_l48p_7 f1 7 io_l48n_7 f2 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 65 7 io_l46p_7 h2 7 io_l46n_7 g2 7 io_l45p_7/vref_7 h3 7 io_l45n_7 h4 7 io_l43p_7 g3 7 io_l43n_7 g4 7 io_l24p_7 h5 7 io_l24n_7 h6 7 io_l22p_7 j6 7 io_l22n_7 j7 7 io_l21p_7/vref_7 k7 7 io_l21n_7 k8 7 io_l19p_7 e1 7 io_l19n_7 e2 7 io_l06p_7 d2 7 io_l06n_7 d3 7 io_l04p_7 e3 7 io_l04n_7 e4 7 io_l03p_7/vref_7 f4 7 io_l03n_7 f5 7 io_l02p_7/vrn_7 g5 7 io_l02n_7/vrp_7 g6 7 io_l01p_7 h7 7 io_l01n_7 j8 0 vcco_0 j12 0 vcco_0 j11 0 vcco_0 j10 0 vcco_0 f11 0 vcco_0 c6 0 vcco_0 b11 1 vcco_1 j15 1 vcco_1 j14 1 vcco_1 j13 1 vcco_1 f14 1 vcco_1 c19 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 66 1 vcco_1 b14 2 vcco_2 m16 2 vcco_2 l23 2 vcco_2 l19 2 vcco_2 l16 2 vcco_2 k16 2 vcco_2 f22 3 vcco_3 w22 3 vcco_3 r16 3 vcco_3 p23 3 vcco_3 p19 3 vcco_3 p16 3 vcco_3 n16 4 vcco_4 ac14 4 vcco_4 ab19 4 vcco_4 w14 4 vcco_4 t15 4 vcco_4 t14 4 vcco_4 t13 5 vcco_5 ac11 5 vcco_5 ab6 5 vcco_5 w11 5 vcco_5 t12 5 vcco_5 t11 5 vcco_5 t10 6 vcco_6 w3 6 vcco_6 r9 6 vcco_6 p9 6 vcco_6 p6 6 vcco_6 p2 6 vcco_6 n9 7 vcco_7 m9 7 vcco_7 l9 7 vcco_7 l6 7 vcco_7 l2 7 vcco_7 k9 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 67 7 vcco_7 f3 na cclk ab23 na prog_b c1 na done ab21 na m0 ac4 na m1 ab4 na m2 ad3 na hswap_en c2 na tck c23 na tdi d1 na tdo c24 na tms c21 na pwrdwn_b ac21 na dxn b4 na dxp c4 na vbatt b21 na rsvd a22 na vccaux ad13 na vccaux ac22 na vccaux ac3 na vccaux n1 na vccaux m24 na vccaux b22 na vccaux b3 na vccaux a12 na vccint u17 na vccint u8 na vccint t16 na vccint t9 na vccint r15 na vccint r14 na vccint r13 na vccint r12 na vccint r11 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 68 na vccint r10 na vccint p15 na vccint p10 na vccint n15 na vccint n10 na vccint m15 na vccint m10 na vccint l15 na vccint l10 na vccint k15 na vccint k14 na vccint k13 na vccint k12 na vccint k11 na vccint k10 na vccint j16 na vccint j9 na vccint h17 na vccint h8 na gnd ad24 na gnd ad23 na gnd ad18 na gnd ad7 na gnd ad2 na gnd ad1 na gnd ac24 na gnd ac23 na gnd ac2 na gnd ac1 na gnd ab22 na gnd ab3 na gnd aa21 na gnd aa15 na gnd aa10 na gnd aa4 na gnd y20 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 69 na gnd y5 na gnd w19 na gnd w6 na gnd v24 na gnd v18 na gnd v7 na gnd v1 na gnd r21 na gnd r4 na gnd p14 na gnd p13 na gnd p12 na gnd p11 na gnd n14 na gnd n13 na gnd n12 na gnd n11 na gnd m14 na gnd m13 na gnd m12 na gnd m11 na gnd l14 na gnd l13 na gnd l12 na gnd l11 na gnd k21 na gnd k4 na gnd g24 na gnd g18 na gnd g7 na gnd g1 na gnd f19 na gnd f6 na gnd e20 na gnd e5 na gnd d21 ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 70 na gnd d15 na gnd d10 na gnd d4 na gnd c22 na gnd c3 na gnd b24 na gnd b23 na gnd b2 na gnd b1 na gnd a24 na gnd a23 na gnd a18 na gnd a7 na gnd a2 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 9 : bg575 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in xc2v1000 no connect in xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 71 bg575 standard bga package specifications (1.27mm pitch) figure 5: bg575 standard bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 72 bg728 standard bga package as shown in ta bl e 1 0 , xc2v3000 virtex-ii devices are available in the bg728 bga package. following this table are the bg728 standard bga package specifications (1.27mm pitch) . ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number 0 io_l01n_0 b3 0 io_l01p_0 a3 0 io_l02n_0 b4 0 io_l02p_0 a4 0 io_l03n_0/vrp_0 c5 0 io_l03p_0/vrn_0 c6 0 io_l04n_0/vref_0 b5 0 io_l04p_0 a5 0 io_l05n_0 e6 0 io_l05p_0 d6 0 io_l06n_0 b6 0 io_l06p_0 a6 0 io_l19n_0 e7 0 io_l19p_0 d8 0 io_l21n_0 f8 0 io_l21p_0/vref_0 e8 0 io_l22n_0 c7 0 io_l22p_0 c8 0 io_l24n_0 b7 0 io_l24p_0 a7 0 io_l25n_0 h9 0 io_l25p_0 j9 0 io_l27n_0 f9 0 io_l27p_0/vref_0 g9 0 io_l28n_0 e9 0 io_l28p_0 d9 0 io_l30n_0 c9 0 io_l30p_0 b9 0 io_l49n_0 a8 0 io_l49p_0 a9 0 io_l51n_0 g10 0 io_l51p_0/vref_0 h10 0 io_l52n_0 f10
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 73 0 io_l52p_0 e10 0 io_l54n_0 d10 0 io_l54p_0 c10 0 io_l67n_0 b10 0 io_l67p_0 a10 0 io_l69n_0 g11 0 io_l69p_0/vref_0 h11 0 io_l70n_0 f11 0 io_l70p_0 f12 0 io_l72n_0 d11 0 io_l72p_0 c11 0 io_l73n_0 b11 0 io_l73p_0 a11 0 io_l75n_0 h12 0 io_l75p_0/vref_0 j12 0 io_l76n_0 e12 0 io_l76p_0 d12 0 io_l78n_0 b12 0 io_l78p_0 a12 0 io_l91n_0/vref_0 j13 0 io_l91p_0 h13 0 io_l92n_0 g13 0 io_l92p_0 f13 0 io_l93n_0 e13 0 io_l93p_0 d13 0 io_l94n_0/vref_0 b13 0 io_l94p_0 a13 0 io_l95n_0/gclk7p c13 0 io_l95p_0/gclk6s c14 0 io_l96n_0/gclk5p f14 0 io_l96p_0/gclk4s e14 1 io_l96n_1/gclk3p g14 1 io_l96p_1/gclk2s h14 1 io_l95n_1/gclk1p a15 1 io_l95p_1/gclk0s b15 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 74 1 io_l94n_1 c15 1 io_l94p_1/vref_1 d15 1 io_l93n_1 e15 1 io_l93p_1 f15 1 io_l92n_1 g15 1 io_l92p_1 h15 1 io_l91n_1 j15 1 io_l91p_1/vref_1 j16 1 io_l78n_1 a16 1 io_l78p_1 b16 1 io_l76n_1 d16 1 io_l76p_1 e16 1 io_l75n_1/vref_1 f16 1 io_l75p_1 f17 1 io_l73n_1 h16 1 io_l73p_1 h17 1 io_l72n_1 a17 1 io_l72p_1 b17 1 io_l70n_1 c17 1 io_l70p_1 d17 1 io_l69n_1/vref_1 g18 1 io_l69p_1 g17 1 io_l67n_1 a18 1 io_l67p_1 b18 1 io_l54n_1 c18 1 io_l54p_1 d18 1 io_l52n_1 e18 1 io_l52p_1 f18 1 io_l51n_1/vref_1 h19 1 io_l51p_1 h18 1 io_l49n_1 a19 1 io_l49p_1 a20 1 io_l30n_1 b19 1 io_l30p_1 c19 1 io_l28n_1 d19 1 io_l28p_1 e19 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 75 1 io_l27n_1/vref_1 f19 1 io_l27p_1 g19 1 io_l25n_1 j19 1 io_l25p_1 j20 1 io_l24n_1 c20 1 io_l24p_1 c21 1 io_l22n_1 d20 1 io_l22p_1 e21 1 io_l21n_1/vref_1 e20 1 io_l21p_1 f20 1 io_l19n_1 a21 1 io_l19p_1 b21 1 io_l06n_1 a22 1 io_l06p_1 b22 1 io_l05n_1 c22 1 io_l05p_1 c23 1 io_l04n_1 d22 1 io_l04p_1/vref_1 e22 1 io_l03n_1/vrp_1 a23 1 io_l03p_1/vrn_1 b23 1 io_l02n_1 a24 1 io_l02p_1 b24 1 io_l01n_1 a25 1 io_l01p_1 b25 2 io_l01n_2 c27 2 io_l01p_2 d27 2 io_l02n_2/vrp_2 d25 2 io_l02p_2/vrn_2 d26 2 io_l03n_2 e24 2 io_l03p_2/vref_2 e25 2 io_l04n_2 e26 2 io_l04p_2 e27 2 io_l06n_2 f23 2 io_l06p_2 f24 2 io_l19n_2 f25 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 76 2 io_l19p_2 f26 2 io_l21n_2 f27 2 io_l21p_2/vref_2 g27 2 io_l22n_2 g23 2 io_l22p_2 h23 2 io_l24n_2 g25 2 io_l24p_2 g26 2 io_l25n_2 h21 2 io_l25p_2 j21 2 io_l27n_2 h22 2 io_l27p_2/vref_2 j22 2 io_l28n_2 h24 2 io_l28p_2 h25 2 io_l30n_2 h27 2 io_l30p_2 j27 2 io_l43n_2 j23 2 io_l43p_2 j24 2 io_l45n_2 j25 2 io_l45p_2/vref_2 j26 2 io_l46n_2 k20 2 io_l46p_2 k21 2 io_l48n_2 k22 2 io_l48p_2 k23 2 io_l49n_2 k24 2 io_l49p_2 k25 2 io_l51n_2 k26 2 io_l51p_2/vref_2 k27 2 io_l52n_2 l20 2 io_l52p_2 m20 2 io_l54n_2 l21 2 io_l54p_2 l22 2 io_l67n_2 l24 2 io_l67p_2 l25 2 io_l69n_2 l26 2 io_l69p_2/vref_2 l27 2 io_l70n_2 m19 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 77 2 io_l70p_2 n19 2 io_l72n_2 m22 2 io_l72p_2 m23 2 io_l73n_2 m24 2 io_l73p_2 n24 2 io_l75n_2 m26 2 io_l75p_2/vref_2 m27 2 io_l76n_2 n20 2 io_l76p_2 n21 2 io_l78n_2 n22 2 io_l78p_2 n23 2 io_l91n_2 n25 2 io_l91p_2 p25 2 io_l93n_2 n26 2 io_l93p_2/vref_2 n27 2 io_l94n_2 p20 2 io_l94p_2 p21 2 io_l96n_2 p22 2 io_l96p_2 p23 3 io_l96n_3 r27 3 io_l96p_3 r26 3 io_l94n_3 r25 3 io_l94p_3 r24 3 io_l93n_3/vref_3 r23 3 io_l93p_3 t23 3 io_l91n_3 r22 3 io_l91p_3 r21 3 io_l78n_3 r20 3 io_l78p_3 r19 3 io_l76n_3 t27 3 io_l76p_3 t26 3 io_l75n_3/vref_3 t24 3 io_l75p_3 u24 3 io_l73n_3 t22 3 io_l73p_3 u22 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 78 3 io_l72n_3 t20 3 io_l72p_3 t19 3 io_l70n_3 u27 3 io_l70p_3 u26 3 io_l69n_3/vref_3 u25 3 io_l69p_3 v25 3 io_l67n_3 u21 3 io_l67p_3 u20 3 io_l54n_3 v27 3 io_l54p_3 v26 3 io_l52n_3 v24 3 io_l52p_3 v23 3 io_l51n_3/vref_3 v22 3 io_l51p_3 w22 3 io_l49n_3 v21 3 io_l49p_3 v20 3 io_l48n_3 w27 3 io_l48p_3 y27 3 io_l46n_3 w26 3 io_l46p_3 w25 3 io_l45n_3/vref_3 w24 3 io_l45p_3 w23 3 io_l43n_3 w21 3 io_l43p_3 w20 3 io_l28n_3 w19 3 io_l28p_3 y19 3 io_l27n_3/vref_3 y25 3 io_l27p_3 y24 3 io_l25n_3 y23 3 io_l25p_3 aa23 3 io_l24n_3 y22 3 io_l24p_3 y21 3 io_l22n_3 aa27 3 io_l22p_3 ab27 3 io_l21n_3/vref_3 aa26 3 io_l21p_3 aa25 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 79 3 io_l19n_3 ab26 3 io_l19p_3 ab25 3 io_l06n_3 ab24 3 io_l06p_3 ab23 3 io_l04n_3 ac27 3 io_l04p_3 ac26 3 io_l03n_3/vref_3 ac25 3 io_l03p_3 ac24 3 io_l02n_3/vrp_3 ad27 3 io_l02p_3/vrn_3 ae27 3 io_l01n_3 ad26 3 io_l01p_3 ad25 4 io_l01n_4/busy/dout (1) af25 4 io_l01p_4/init_b ag25 4 io_l02n_4/d0/din (1) af24 4 io_l02p_4/d1 ag24 4 io_l03n_4/d2/alt_vrp_4 ad23 4 io_l03p_4/d3/alt_vrn_4 ae23 4 io_l04n_4/vref_4 af23 4 io_l04p_4 ag23 4 io_l05n_4/vrp_4 ad22 4 io_l05p_4/vrn_4 ae22 4 io_l06n_4 af22 4 io_l06p_4 ag22 4 io_l19n_4 ac21 4 io_l19p_4 ab21 4 io_l21n_4 ae21 4 io_l21p_4/vref_4 ae20 4 io_l22n_4 af21 4 io_l22p_4 ag21 4 io_l24n_4 ab20 4 io_l24p_4 aa20 4 io_l25n_4 ac20 4 io_l25p_4 ad20 4 io_l27n_4 ag20 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 80 4 io_l27p_4/vref_4 ag19 4 io_l28n_4 ab19 4 io_l28p_4 aa19 4 io_l30n_4 ac19 4 io_l30p_4 ad19 4 io_l49n_4 ae19 4 io_l49p_4 af19 4 io_l51n_4 aa18 4 io_l51p_4/vref_4 y18 4 io_l52n_4 ab18 4 io_l52p_4 ac18 4 io_l54n_4 ad18 4 io_l54p_4 ae18 4 io_l67n_4 af18 4 io_l67p_4 ag18 4 io_l69n_4 aa17 4 io_l69p_4/vref_4 y17 4 io_l70n_4 ab17 4 io_l70p_4 ab16 4 io_l72n_4 ad17 4 io_l72p_4 ae17 4 io_l73n_4 af17 4 io_l73p_4 ag17 4 io_l75n_4 y16 4 io_l75p_4/vref_4 w16 4 io_l76n_4 ac16 4 io_l76p_4 ad16 4 io_l78n_4 af16 4 io_l78p_4 ag16 4 io_l91n_4/vref_4 w15 4 io_l91p_4 y15 4 io_l92n_4 ab15 4 io_l92p_4 aa15 4 io_l93n_4 ac15 4 io_l93p_4 ad15 4 io_l94n_4/vref_4 ae15 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 81 4 io_l94p_4 ae14 4 io_l95n_4/gclk3s af15 4 io_l95p_4/gclk2p ag15 4 io_l96n_4/gclk1s y14 4 io_l96p_4/gclk0p aa14 5 io_l96n_5/gclk7s ac14 5 io_l96p_5/gclk6p ab14 5 io_l95n_5/gclk5s ag13 5 io_l95p_5/gclk4p af13 5 io_l94n_5 ae13 5 io_l94p_5/vref_5 ad13 5 io_l93n_5 ac13 5 io_l93p_5 ab13 5 io_l92n_5 aa13 5 io_l92p_5 y13 5 io_l91n_5 w13 5 io_l91p_5/vref_5 w12 5 io_l78n_5 ag12 5 io_l78p_5 af12 5 io_l76n_5 ad12 5 io_l76p_5 ac12 5 io_l75n_5/vref_5 ab12 5 io_l75p_5 ab11 5 io_l73n_5 y12 5 io_l73p_5 y11 5 io_l72n_5 ag11 5 io_l72p_5 af11 5 io_l70n_5 ae11 5 io_l70p_5 ad11 5 io_l69n_5/vref_5 aa10 5 io_l69p_5 aa11 5 io_l67n_5 ag10 5 io_l67p_5 af10 5 io_l54n_5 ae10 5 io_l54p_5 ad10 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 82 5 io_l52n_5 ac10 5 io_l52p_5 ab10 5 io_l51n_5/vref_5 y9 5 io_l51p_5 y10 5 io_l49n_5 ag9 5 io_l49p_5 ag8 5 io_l30n_5 af9 5 io_l30p_5 ae9 5 io_l28n_5 ad9 5 io_l28p_5 ac9 5 io_l27n_5/vref_5 ab9 5 io_l27p_5 aa9 5 io_l25n_5 ae8 5 io_l25p_5 ae7 5 io_l24n_5 ad8 5 io_l24p_5 ac8 5 io_l22n_5 ab8 5 io_l22p_5 aa8 5 io_l21n_5/vref_5 ag7 5 io_l21p_5 af7 5 io_l19n_5 ac7 5 io_l19p_5 ab7 5 io_l06n_5 ag6 5 io_l06p_5 af6 5 io_l05n_5/vrp_5 ae6 5 io_l05p_5/vrn_5 ad6 5 io_l04n_5 ag5 5 io_l04p_5/vref_5 af5 5 io_l03n_5/d4/alt_vrp_5 ae5 5 io_l03p_5/d5/alt_vrn_5 ad5 5 io_l02n_5/d6 ag4 5 io_l02p_5/d7 af4 5 io_l01n_5/rdwr_b ag3 5 io_l01p_5/cs_b af3 6 io_l01p_6 ae1 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 83 6 io_l01n_6 ad1 6 io_l02p_6/vrn_6 ad3 6 io_l02n_6/vrp_6 ad2 6 io_l03p_6 ac4 6 io_l03n_6/vref_6 ac3 6 io_l04p_6 ac2 6 io_l04n_6 ac1 6 io_l06p_6 ab5 6 io_l06n_6 ab4 6 io_l19p_6 ab3 6 io_l19n_6 ab2 6 io_l21p_6 ab1 6 io_l21n_6/vref_6 aa1 6 io_l22p_6 aa5 6 io_l22n_6 aa6 6 io_l24p_6 aa3 6 io_l24n_6 aa2 6 io_l25p_6 y5 6 io_l25n_6 y6 6 io_l27p_6 y4 6 io_l27n_6/vref_6 y3 6 io_l28p_6 y1 6 io_l28n_6 w1 6 io_l43p_6 w8 6 io_l43n_6 w9 6 io_l45p_6 w6 6 io_l45n_6/vref_6 w7 6 io_l46p_6 w5 6 io_l46n_6 w4 6 io_l48p_6 w3 6 io_l48n_6 w2 6 io_l49p_6 v7 6 io_l49n_6 v8 6 io_l51p_6 v5 6 io_l51n_6/vref_6 v6 6 io_l52p_6 v4 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 84 6 io_l52n_6 v3 6 io_l54p_6 v2 6 io_l54n_6 v1 6 io_l67p_6 u8 6 io_l67n_6 t8 6 io_l69p_6 u6 6 io_l69n_6/vref_6 u7 6 io_l70p_6 u4 6 io_l70n_6 u3 6 io_l72p_6 u2 6 io_l72n_6 u1 6 io_l73p_6 t9 6 io_l73n_6 r9 6 io_l75p_6 t5 6 io_l75n_6/vref_6 t6 6 io_l76p_6 t4 6 io_l76n_6 r4 6 io_l78p_6 t2 6 io_l78n_6 t1 6 io_l91p_6 r7 6 io_l91n_6 r8 6 io_l93p_6 r5 6 io_l93n_6/vref_6 r6 6 io_l94p_6 r3 6 io_l94n_6 p3 6 io_l96p_6 r2 6 io_l96n_6 r1 7 io_l96p_7 p5 7 io_l96n_7 p6 7 io_l94p_7 p7 7 io_l94n_7 p8 7 io_l93p_7/vref_7 n1 7 io_l93n_7 n2 7 io_l91p_7 n3 7 io_l91n_7 n4 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 85 7 io_l78p_7 n6 7 io_l78n_7 n7 7 io_l76p_7 n9 7 io_l76n_7 n8 7 io_l75p_7/vref_7 n5 7 io_l75n_7 m6 7 io_l73p_7 m1 7 io_l73n_7 m2 7 io_l72p_7 m4 7 io_l72n_7 m5 7 io_l70p_7 m8 7 io_l70n_7 m9 7 io_l69p_7/vref_7 l1 7 io_l69n_7 l2 7 io_l67p_7 l3 7 io_l67n_7 l4 7 io_l54p_7 k1 7 io_l54n_7 k2 7 io_l52p_7 k4 7 io_l52n_7 k5 7 io_l51p_7/vref_7 l6 7 io_l51n_7 l7 7 io_l49p_7 k6 7 io_l49n_7 k7 7 io_l48p_7 l8 7 io_l48n_7 k8 7 io_l46p_7 j1 7 io_l46n_7 h1 7 io_l45p_7/vref_7 j2 7 io_l45n_7 j3 7 io_l43p_7 k3 7 io_l43n_7 j4 7 io_l30p_7 h3 7 io_l30n_7 h4 7 io_l28p_7 j5 7 io_l28n_7 j6 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 86 7 io_l27p_7/vref_7 h5 7 io_l27n_7 h6 7 io_l25p_7 j7 7 io_l25n_7 j8 7 io_l24p_7 g1 7 io_l24n_7 f1 7 io_l22p_7 g2 7 io_l22n_7 g3 7 io_l21p_7/vref_7 f2 7 io_l21n_7 f3 7 io_l19p_7 g5 7 io_l19n_7 g6 7 io_l06p_7 f4 7 io_l06n_7 f5 7 io_l04p_7 e1 7 io_l04n_7 e2 7 io_l03p_7/vref_7 d1 7 io_l03n_7 c1 7 io_l02p_7/vrn_7 e3 7 io_l02n_7/vrp_7 e4 7 io_l01p_7 d2 7 io_l01n_7 d3 0 vcco_0 k13 0 vcco_0 k12 0 vcco_0 k11 0 vcco_0 j11 0 vcco_0 j10 0 vcco_0 g12 0 vcco_0 d7 0 vcco_0 c12 1 vcco_1 k17 1 vcco_1 k16 1 vcco_1 k15 1 vcco_1 j18 1 vcco_1 j17 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 87 1 vcco_1 g16 1 vcco_1 d21 1 vcco_1 c16 2 vcco_2 n18 2 vcco_2 m25 2 vcco_2 m21 2 vcco_2 m18 2 vcco_2 l19 2 vcco_2 l18 2 vcco_2 k19 2 vcco_2 g24 3 vcco_3 aa24 3 vcco_3 v19 3 vcco_3 u19 3 vcco_3 u18 3 vcco_3 t25 3 vcco_3 t21 3 vcco_3 t18 3 vcco_3 r18 4 vcco_4 ae16 4 vcco_4 ad21 4 vcco_4 aa16 4 vcco_4 w18 4 vcco_4 w17 4 vcco_4 v17 4 vcco_4 v16 4 vcco_4 v15 5 vcco_5 ae12 5 vcco_5 ad7 5 vcco_5 aa12 5 vcco_5 w11 5 vcco_5 w10 5 vcco_5 v13 5 vcco_5 v12 5 vcco_5 v11 6 vcco_6 aa4 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 88 6 vcco_6 v9 6 vcco_6 u10 6 vcco_6 u9 6 vcco_6 t10 6 vcco_6 t7 6 vcco_6 t3 6 vcco_6 r10 7 vcco_7 m10 7 vcco_7 m7 7 vcco_7 m3 7 vcco_7 l10 7 vcco_7 l9 7 vcco_7 k9 7 vcco_7 g4 7 vcco_7 n10 na cclk aa22 na prog_b c4 na done ac22 na m0 ac6 na m1 y7 na m2 ae4 na hswap_en d5 na tck g20 na tdi h7 na tdo g22 na tms f21 na pwrdwn_b ae24 na dxn g8 na dxp f7 na vbatt d23 na rsvd c24 na vccaux af14 na vccaux ae26 na vccaux ae2 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 89 na vccaux p26 na vccaux p2 na vccaux c26 na vccaux c2 na vccaux b14 na vccint v18 na vccint v14 na vccint v10 na vccint u17 na vccint u16 na vccint u15 na vccint u14 na vccint u13 na vccint u12 na vccint u11 na vccint t17 na vccint t11 na vccint r17 na vccint r11 na vccint p18 na vccint p17 na vccint p11 na vccint p10 na vccint n17 na vccint n11 na vccint m17 na vccint m11 na vccint l17 na vccint l16 na vccint l15 na vccint l14 na vccint l13 na vccint l12 na vccint l11 na vccint k18 na vccint k14 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 90 na vccint k10 na gnd ag27 na gnd ag26 na gnd ag14 na gnd ag2 na gnd ag1 na gnd af27 na gnd af26 na gnd af20 na gnd af8 na gnd af2 na gnd af1 na gnd ae25 na gnd ae3 na gnd ad24 na gnd ad14 na gnd ad4 na gnd ac23 na gnd ac17 na gnd ac11 na gnd ac5 na gnd ab22 na gnd ab6 na gnd aa21 na gnd aa7 na gnd y26 na gnd y20 na gnd y8 na gnd y2 na gnd w14 na gnd u23 na gnd u5 na gnd t16 na gnd t15 na gnd t14 na gnd t13 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 91 na gnd t12 na gnd r16 na gnd r15 na gnd r14 na gnd r13 na gnd r12 na gnd p27 na gnd p24 na gnd p19 na gnd p16 na gnd p15 na gnd p14 na gnd p13 na gnd p12 na gnd p9 na gnd p4 na gnd p1 na gnd n16 na gnd n15 na gnd n14 na gnd n13 na gnd n12 na gnd m16 na gnd m15 na gnd m14 na gnd m13 na gnd m12 na gnd l23 na gnd l5 na gnd j14 na gnd h26 na gnd h20 na gnd h8 na gnd h2 na gnd g21 na gnd g7 ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 92 na gnd f22 na gnd f6 na gnd e23 na gnd e17 na gnd e11 na gnd e5 na gnd d24 na gnd d14 na gnd d4 na gnd c25 na gnd c3 na gnd b27 na gnd b26 na gnd b20 na gnd b8 na gnd b2 na gnd b1 na gnd a27 na gnd a26 na gnd a14 na gnd a2 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 1 0 : bg728 bga ? xc2v3000 bank pin description pin number
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 93 bg728 standard bga package specifications (1.27mm pitch) figure 6: bg728 standard bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 94 ff896 flip-chip fine-pitch bga package as shown in ta bl e 1 1 , xc2v1000, xc2v1500, and XC2V2000 virtex-ii device s are available in the ff8 96 flip-chip fine-pitch bga package. pins in the xc2v1000, xc2v1500, and XC2V2000 de vices are the same, except for the pin differences in the xc2v1000 and xc2v1500 devices shown in the no connect columns. following this table are the ff896 flip-chip fine-pitch bga package specifications (1.00mm pitch) . table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500 0 io_l01n_0 b27 0 io_l01p_0 a27 0 io_l02n_0 f24 0 io_l02p_0 e24 0 io_l03n_0/vrp_0 c26 0 io_l03p_0/vrn_0 c25 0 io_l04n_0/vref_0 a26 0 io_l04p_0 a25 0 io_l05n_0 f23 0 io_l05p_0 f22 0 io_l06n_0 c24 0 io_l06p_0 d25 0 io_l19n_0 a24 0 io_l19p_0 b25 0 io_l20n_0 g22 0 io_l20p_0 g21 0 io_l21n_0 d24 0 io_l21p_0/vref_0 d23 0 io_l22n_0 b23 0 io_l22p_0 b24 0 io_l23n_0 h21 0 io_l23p_0 h20 0 io_l24n_0 e22 0 io_l24p_0 e23 0 io_l49n_0 a22 0 io_l49p_0 b22 0 io_l50n_0 f21 0 io_l50p_0 f20 0 io_l51n_0 c23 0 io_l51p_0/vref_0 c22 0 io_l52n_0 b20 0 io_l52p_0 b21
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 95 0 io_l53n_0 g20 0 io_l53p_0 g19 0 io_l54n_0 d21 0 io_l54p_0 d22 0 io_l67n_0 e20 nc 0 io_l67p_0 e21 nc 0 io_l68n_0 h19 nc 0 io_l68p_0 h18 nc 0 io_l69n_0 d20 nc 0 io_l69p_0/vref_0 d19 nc 0 io_l70n_0 a20 nc 0 io_l70p_0 a21 nc 0 io_l71n_0 f19 nc 0 io_l71p_0 f18 nc 0 io_l72n_0 c19 nc 0 io_l72p_0 c20 nc 0 io_l73n_0 b18 nc nc 0 io_l73p_0 b19 nc nc 0 io_l74n_0 g18 nc nc 0 io_l74p_0 h17 nc nc 0 io_l75n_0 e18 nc nc 0 io_l75p_0/vref_0 d18 nc nc 0 io_l76n_0 a18 nc nc 0 io_l76p_0 a19 nc nc 0 io_l77n_0 j17 nc nc 0 io_l77p_0 j16 nc nc 0 io_l78n_0 e16 nc nc 0 io_l78p_0 e17 nc nc 0 io_l91n_0/vref_0 b17 0 io_l91p_0 b16 0 io_l92n_0 f17 0 io_l92p_0 f16 0 io_l93n_0 d16 0 io_l93p_0 d17 0 io_l94n_0/vref_0 a17 0 io_l94p_0 a16 0 io_l95n_0/gclk7p h16 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 96 0 io_l95p_0/gclk6s g16 0 io_l96n_0/gclk5p c17 0 io_l96p_0/gclk4s c16 1 io_l96n_1/gclk3p c15 1 io_l96p_1/gclk2s c14 1 io_l95n_1/gclk1p f15 1 io_l95p_1/gclk0s f14 1 io_l94n_1 b15 1 io_l94p_1/vref_1 b14 1 io_l93n_1 d14 1 io_l93p_1 d15 1 io_l92n_1 g15 1 io_l92p_1 h15 1 io_l91n_1 a14 1 io_l91p_1/vref_1 a13 1 io_l78n_1 e14 nc nc 1 io_l78p_1 e15 nc nc 1 io_l77n_1 j15 nc nc 1 io_l77p_1 j14 nc nc 1 io_l76n_1 b12 nc nc 1 io_l76p_1 b13 nc nc 1 io_l75n_1/vref_1 d13 nc nc 1 io_l75p_1 e13 nc nc 1 io_l74n_1 h14 nc nc 1 io_l74p_1 h13 nc nc 1 io_l73n_1 a11 nc nc 1 io_l73p_1 a12 nc nc 1 io_l72n_1 c11 nc 1 io_l72p_1 c12 nc 1 io_l71n_1 f13 nc 1 io_l71p_1 f12 nc 1 io_l70n_1 b10 nc 1 io_l70p_1 b11 nc 1 io_l69n_1/vref_1 d12 nc 1 io_l69p_1 d11 nc 1 io_l68n_1 g13 nc table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 97 1 io_l68p_1 g12 nc 1 io_l67n_1 a9 nc 1 io_l67p_1 a10 nc 1 io_l54n_1 e10 1 io_l54p_1 e11 1 io_l53n_1 h12 1 io_l53p_1 h11 1 io_l52n_1 d9 1 io_l52p_1 d10 1 io_l51n_1/vref_1 c9 1 io_l51p_1 c8 1 io_l50n_1 f11 1 io_l50p_1 f10 1 io_l49n_1 b8 1 io_l49p_1 b9 1 io_l24n_1 e8 1 io_l24p_1 e9 1 io_l23n_1 g11 1 io_l23p_1 h10 1 io_l22n_1 b7 1 io_l22p_1 a7 1 io_l21n_1/vref_1 d8 1 io_l21p_1 e7 1 io_l20n_1 g10 1 io_l20p_1 g9 1 io_l19n_1 a5 1 io_l19p_1 a6 1 io_l06n_1 c6 1 io_l06p_1 c7 1 io_l05n_1 f9 1 io_l05p_1 g8 1 io_l04n_1 b6 1 io_l04p_1/vref_1 c5 1 io_l03n_1/vrp_1 d7 1 io_l03p_1/vrn_1 d6 1 io_l02n_1 f8 1 io_l02p_1 f7 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 98 1 io_l01n_1 b4 1 io_l01p_1 a4 2 io_l01n_2 c1 2 io_l01p_2 b1 2 io_l02n_2/vrp_2 h9 2 io_l02p_2/vrn_2 h8 2 io_l03n_2 d3 2 io_l03p_2/vref_2 e3 2 io_l04n_2 d2 2 io_l04p_2 c2 2 io_l05n_2 g7 2 io_l05p_2 h7 2 io_l06n_2 f4 2 io_l06p_2 e4 2 io_l19n_2 e1 2 io_l19p_2 d1 2 io_l20n_2 g6 2 io_l20p_2 h6 2 io_l21n_2 f5 2 io_l21p_2/vref_2 g5 2 io_l22n_2 g2 2 io_l22p_2 f2 2 io_l23n_2 j8 2 io_l23p_2 j7 2 io_l24n_2 g3 2 io_l24p_2 f3 2 io_l43n_2 g1 2 io_l43p_2 f1 2 io_l44n_2 k8 2 io_l44p_2 l8 2 io_l45n_2 g4 2 io_l45p_2/vref_2 h4 2 io_l46n_2 j2 2 io_l46p_2 h2 2 io_l47n_2 j6 2 io_l47p_2 k6 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 99 2 io_l48n_2 j5 2 io_l48p_2 h5 2 io_l49n_2 j3 2 io_l49p_2 h3 2 io_l50n_2 k7 2 io_l50p_2 l7 2 io_l51n_2 j4 2 io_l51p_2/vref_2 k4 2 io_l52n_2 k1 2 io_l52p_2 j1 2 io_l53n_2 l6 2 io_l53p_2 m6 2 io_l54n_2 l5 2 io_l54p_2 k5 2 io_l67n_2 l2 nc 2 io_l67p_2 k2 nc 2 io_l68n_2 m8 nc 2 io_l68p_2 n8 nc 2 io_l69n_2 l4 nc 2 io_l69p_2/vref_2 m4 nc 2 io_l70n_2 m1 nc 2 io_l70p_2 l1 nc 2 io_l71n_2 m7 nc 2 io_l71p_2 n7 nc 2 io_l72n_2 m3 nc 2 io_l72p_2 l3 nc 2 io_l73n_2 n2 nc nc 2 io_l73p_2 m2 nc nc 2 io_l74n_2 n6 nc nc 2 io_l74p_2 p6 nc nc 2 io_l75n_2 n5 nc nc 2 io_l75p_2/vref_2 n4 nc nc 2 io_l76n_2 p1 nc nc 2 io_l76p_2 n1 nc nc 2 io_l77n_2 p9 nc nc 2 io_l77p_2 r9 nc nc 2 io_l78n_2 r5 nc nc table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 100 2 io_l78p_2 p5 nc nc 2 io_l91n_2 r2 2 io_l91p_2 p2 2 io_l92n_2 p8 2 io_l92p_2 r8 2 io_l93n_2 p4 2 io_l93p_2/vref_2 r4 2 io_l94n_2 r1 2 io_l94p_2 t2 2 io_l95n_2 r7 2 io_l95p_2 r6 2 io_l96n_2 r3 2 io_l96p_2 p3 3 io_l96n_3 t7 3 io_l96p_3 t6 3 io_l95n_3 u1 3 io_l95p_3 v1 3 io_l94n_3 t3 3 io_l94p_3 u3 3 io_l93n_3/vref_3 t8 3 io_l93p_3 u8 3 io_l92n_3 u2 3 io_l92p_3 v2 3 io_l91n_3 t4 3 io_l91p_3 u4 3 io_l78n_3 u9 nc nc 3 io_l78p_3 t9 nc nc 3 io_l77n_3 w1 nc nc 3 io_l77p_3 y1 nc nc 3 io_l76n_3 t5 nc nc 3 io_l76p_3 u5 nc nc 3 io_l75n_3/vref_3 u6 nc nc 3 io_l75p_3 v6 nc nc 3 io_l74n_3 w2 nc nc 3 io_l74p_3 y2 nc nc 3 io_l73n_3 v4 nc nc table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 101 3 io_l73p_3 w4 nc nc 3 io_l72n_3 w7 nc 3 io_l72p_3 v7 nc 3 io_l71n_3 v5 nc 3 io_l71p_3 w6 nc 3 io_l70n_3 w3 nc 3 io_l70p_3 y3 nc 3 io_l69n_3/vref_3 v8 nc 3 io_l69p_3 w8 nc 3 io_l68n_3 aa1 nc 3 io_l68p_3 ab1 nc 3 io_l67n_3 y4 nc 3 io_l67p_3 aa4 nc 3 io_l54n_3 aa6 3 io_l54p_3 y6 3 io_l53n_3 aa2 3 io_l53p_3 ab2 3 io_l52n_3 y5 3 io_l52p_3 aa5 3 io_l51n_3/vref_3 y8 3 io_l51p_3 aa8 3 io_l50n_3 ac2 3 io_l50p_3 ad2 3 io_l49n_3 y7 3 io_l49p_3 aa7 3 io_l48n_3 ac6 3 io_l48p_3 ab6 3 io_l47n_3 ad1 3 io_l47p_3 ae1 3 io_l46n_3 ab3 3 io_l46p_3 ac3 3 io_l45n_3/vref_3 ab7 3 io_l45p_3 ac7 3 io_l44n_3 ab4 3 io_l44p_3 ac4 3 io_l43n_3 ab5 3 io_l43p_3 ac5 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 102 3 io_l24n_3 ac8 3 io_l24p_3 ab8 3 io_l23n_3 ae2 3 io_l23p_3 af3 3 io_l22n_3 ad3 3 io_l22p_3 ae3 3 io_l21n_3/vref_3 ad6 3 io_l21p_3 ad7 3 io_l20n_3 af1 3 io_l20p_3 ag1 3 io_l19n_3 ad4 3 io_l19p_3 ae4 3 io_l06n_3 ad8 3 io_l06p_3 ae7 3 io_l05n_3 ag2 3 io_l05p_3 ah2 3 io_l04n_3 ad5 3 io_l04p_3 ae5 3 io_l03n_3/vref_3 ac9 3 io_l03p_3 ad9 3 io_l02n_3/vrp_3 ah1 3 io_l02p_3/vrn_3 aj1 3 io_l01n_3 af4 3 io_l01p_3 ag3 4 io_l01n_4/busy/dout (1) ak2 4 io_l01p_4/init_b aj3 4 io_l02n_4/d0/din (1) ae8 4 io_l02p_4/d1 af9 4 io_l03n_4/d2/alt_vrp_4 ah5 4 io_l03p_4/d3/alt_vrn_4 ah6 4 io_l04n_4/vref_4 aj4 4 io_l04p_4 ak4 4 io_l05n_4/vrp_4 ac10 4 io_l05p_4/vrn_4 ac11 4 io_l06n_4 ah7 4 io_l06p_4 ag6 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 103 4 io_l19n_4 ak6 4 io_l19p_4 ak5 4 io_l20n_4 ae9 4 io_l20p_4 ae10 4 io_l21n_4 af7 4 io_l21p_4/vref_4 af8 4 io_l22n_4 ak7 4 io_l22p_4 aj6 4 io_l23n_4 ad10 4 io_l23p_4 ad11 4 io_l24n_4 ag8 4 io_l24p_4 ag7 4 io_l49n_4 aj8 4 io_l49p_4 aj7 4 io_l50n_4 ae11 4 io_l50p_4 ae12 4 io_l51n_4 ag9 4 io_l51p_4/vref_4 ag10 4 io_l52n_4 ak9 4 io_l52p_4 aj9 4 io_l53n_4 ah8 4 io_l53p_4 ah9 4 io_l54n_4 af11 4 io_l54p_4 af10 4 io_l67n_4 aj11 nc 4 io_l67p_4 aj10 nc 4 io_l68n_4 ac12 nc 4 io_l68p_4 ac13 nc 4 io_l69n_4 ag11 nc 4 io_l69p_4/vref_4 ag12 nc 4 io_l70n_4 ak11 nc 4 io_l70p_4 ak10 nc 4 io_l71n_4 ad12 nc 4 io_l71p_4 ad13 nc 4 io_l72n_4 ah12 nc 4 io_l72p_4 ah11 nc 4 io_l73n_4 aj13 nc nc table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 104 4 io_l73p_4 aj12 nc nc 4 io_l74n_4 ae13 nc nc 4 io_l74p_4 ae14 nc nc 4 io_l75n_4 af13 nc nc 4 io_l75p_4/vref_4 ag13 nc nc 4 io_l76n_4 ak13 nc nc 4 io_l76p_4 ak12 nc nc 4 io_l77n_4 ab14 nc nc 4 io_l77p_4 ab15 nc nc 4 io_l78n_4 af15 nc nc 4 io_l78p_4 af14 nc nc 4 io_l91n_4/vref_4 aj14 4 io_l91p_4 aj15 4 io_l92n_4 ac14 4 io_l92p_4 ac15 4 io_l93n_4 ag15 4 io_l93p_4 ag14 4 io_l94n_4/vref_4 ak14 4 io_l94p_4 ak15 4 io_l95n_4/gclk3s ad15 4 io_l95p_4/gclk2p ae15 4 io_l96n_4/gclk1s ah14 4 io_l96p_4/gclk0p ah15 5 io_l96n_5/gclk7s ah16 5 io_l96p_5/gclk6p ah17 5 io_l95n_5/gclk5s ae16 5 io_l95p_5/gclk4p ad16 5 io_l94n_5 aj16 5 io_l94p_5/vref_5 aj17 5 io_l93n_5 ag17 5 io_l93p_5 ag16 5 io_l92n_5 ac16 5 io_l92p_5 ac17 5 io_l91n_5 ak17 5 io_l91p_5/vref_5 ak18 5 io_l78n_5 af17 nc nc table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 105 5 io_l78p_5 af16 nc nc 5 io_l77n_5 ab16 nc nc 5 io_l77p_5 ab17 nc nc 5 io_l76n_5 aj19 nc nc 5 io_l76p_5 aj18 nc nc 5 io_l75n_5/vref_5 ag18 nc nc 5 io_l75p_5 af18 nc nc 5 io_l74n_5 ae17 nc nc 5 io_l74p_5 ae18 nc nc 5 io_l73n_5 ak20 nc nc 5 io_l73p_5 ak19 nc nc 5 io_l72n_5 ah20 nc 5 io_l72p_5 ah19 nc 5 io_l71n_5 ad18 nc 5 io_l71p_5 ad19 nc 5 io_l70n_5 aj21 nc 5 io_l70p_5 aj20 nc 5 io_l69n_5/vref_5 ag19 nc 5 io_l69p_5 ag20 nc 5 io_l68n_5 ac18 nc 5 io_l68p_5 ac19 nc 5 io_l67n_5 ak22 nc 5 io_l67p_5 ak21 nc 5 io_l54n_5 af21 5 io_l54p_5 af20 5 io_l53n_5 ah22 5 io_l53p_5 ah23 5 io_l52n_5 ag22 5 io_l52p_5 ag21 5 io_l51n_5/vref_5 af22 5 io_l51p_5 af23 5 io_l50n_5 ae19 5 io_l50p_5 ae20 5 io_l49n_5 aj23 5 io_l49p_5 aj22 5 io_l24n_5 af24 5 io_l24p_5 ag23 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 106 5 io_l23n_5 ad20 5 io_l23p_5 ad21 5 io_l22n_5 ak25 5 io_l22p_5 ak24 5 io_l21n_5/vref_5 ah24 5 io_l21p_5 ah25 5 io_l20n_5 ae21 5 io_l20p_5 ad22 5 io_l19n_5 aj25 5 io_l19p_5 aj24 5 io_l06n_5 ag25 5 io_l06p_5 ag24 5 io_l05n_5/vrp_5 ac20 5 io_l05p_5/vrn_5 ac21 5 io_l04n_5 ak26 5 io_l04p_5/vref_5 ak27 5 io_l03n_5/d4/alt_vrp_5 ah26 5 io_l03p_5/d5/alt_vrn_5 aj27 5 io_l02n_5/d6 ae22 5 io_l02p_5/d7 ae23 5 io_l01n_5/rdwr_b aj28 5 io_l01p_5/cs_b ak29 6 io_l01p_6 ac22 6 io_l01n_6 ab23 6 io_l02p_6/vrn_6 ag28 6 io_l02n_6/vrp_6 af28 6 io_l03p_6 aj30 6 io_l03n_6/vref_6 ah30 6 io_l04p_6 ad23 6 io_l04n_6 ac23 6 io_l05p_6 af27 6 io_l05n_6 ae27 6 io_l06p_6 ag29 6 io_l06n_6 ah29 6 io_l19p_6 ae24 6 io_l19n_6 ad24 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 107 6 io_l20p_6 ae26 6 io_l20n_6 ad26 6 io_l21p_6 ag30 6 io_l21n_6/vref_6 af30 6 io_l22p_6 ad25 6 io_l22n_6 ac25 6 io_l23p_6 ae28 6 io_l23n_6 ad28 6 io_l24p_6 ad29 6 io_l24n_6 ae29 6 io_l43p_6 ac24 6 io_l43n_6 ab24 6 io_l44p_6 ad27 6 io_l44n_6 ac27 6 io_l45p_6 ac26 6 io_l45n_6/vref_6 ab26 6 io_l46p_6 aa23 6 io_l46n_6 y23 6 io_l47p_6 ac28 6 io_l47n_6 ab28 6 io_l48p_6 ad30 6 io_l48n_6 ae30 6 io_l49p_6 ab25 6 io_l49n_6 aa25 6 io_l50p_6 aa24 6 io_l50n_6 y24 6 io_l51p_6 ac29 6 io_l51n_6/vref_6 ab30 6 io_l52p_6 y25 6 io_l52n_6 w25 6 io_l53p_6 ab27 6 io_l53n_6 aa27 6 io_l54p_6 aa29 6 io_l54n_6 ab29 6 io_l67p_6 w23 nc 6 io_l67n_6 v23 nc 6 io_l68p_6 aa26 nc table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 108 6 io_l68n_6 y26 nc 6 io_l69p_6 aa30 nc 6 io_l69n_6/vref_6 y30 nc 6 io_l70p_6 w24 nc 6 io_l70n_6 v24 nc 6 io_l71p_6 y27 nc 6 io_l71n_6 w27 nc 6 io_l72p_6 w28 nc 6 io_l72n_6 y28 nc 6 io_l73p_6 v25 nc nc 6 io_l73n_6 u25 nc nc 6 io_l74p_6 v26 nc nc 6 io_l74n_6 v27 nc nc 6 io_l75p_6 y29 nc nc 6 io_l75n_6/vref_6 w29 nc nc 6 io_l76p_6 u22 nc nc 6 io_l76n_6 t22 nc nc 6 io_l77p_6 u26 nc nc 6 io_l77n_6 t26 nc nc 6 io_l78p_6 v30 nc nc 6 io_l78n_6 w30 nc nc 6 io_l91p_6 u23 6 io_l91n_6 t23 6 io_l92p_6 u27 6 io_l92n_6 t27 6 io_l93p_6 v29 6 io_l93n_6/vref_6 u29 6 io_l94p_6 t24 6 io_l94n_6 t25 6 io_l95p_6 u28 6 io_l95n_6 t28 6 io_l96p_6 t30 6 io_l96n_6 u30 7 io_l96p_7 p28 7 io_l96n_7 r28 7 io_l95p_7 r25 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 109 7 io_l95n_7 r24 7 io_l94p_7 r29 7 io_l94n_7 t29 7 io_l93p_7/vref_7 r27 7 io_l93n_7 p27 7 io_l92p_7 r23 7 io_l92n_7 p23 7 io_l91p_7 n30 7 io_l91n_7 p30 7 io_l78p_7 p26 nc nc 7 io_l78n_7 r26 nc nc 7 io_l77p_7 r22 nc nc 7 io_l77n_7 p22 nc nc 7 io_l76p_7 n29 nc nc 7 io_l76n_7 p29 nc nc 7 io_l75p_7/vref_7 n27 nc nc 7 io_l75n_7 n26 nc nc 7 io_l74p_7 p25 nc nc 7 io_l74n_7 n25 nc nc 7 io_l73p_7 l30 nc nc 7 io_l73n_7 m30 nc nc 7 io_l72p_7 l28 nc 7 io_l72n_7 m28 nc 7 io_l71p_7 n24 nc 7 io_l71n_7 m24 nc 7 io_l70p_7 l29 nc 7 io_l70n_7 m29 nc 7 io_l69p_7/vref_7 m27 nc 7 io_l69n_7 l27 nc 7 io_l68p_7 n23 nc 7 io_l68n_7 m23 nc 7 io_l67p_7 j30 nc 7 io_l67n_7 k30 nc 7 io_l54p_7 k26 7 io_l54n_7 l26 7 io_l53p_7 m25 7 io_l53n_7 l25 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 110 7 io_l52p_7 j29 7 io_l52n_7 k29 7 io_l51p_7/vref_7 k27 7 io_l51n_7 j27 7 io_l50p_7 l24 7 io_l50n_7 k24 7 io_l49p_7 h27 7 io_l49n_7 j28 7 io_l48p_7 h26 7 io_l48n_7 j26 7 io_l47p_7 k25 7 io_l47n_7 j25 7 io_l46p_7 h28 7 io_l46n_7 h29 7 io_l45p_7/vref_7 g28 7 io_l45n_7 f28 7 io_l44p_7 l23 7 io_l44n_7 k23 7 io_l43p_7 f30 7 io_l43n_7 g30 7 io_l24p_7 f26 7 io_l24n_7 g27 7 io_l23p_7 j24 7 io_l23n_7 h24 7 io_l22p_7 f29 7 io_l22n_7 g29 7 io_l21p_7/vref_7 g26 7 io_l21n_7 g25 7 io_l20p_7 h25 7 io_l20n_7 g24 7 io_l19p_7 d30 7 io_l19n_7 e30 7 io_l06p_7 e27 7 io_l06n_7 f27 7 io_l05p_7 j23 7 io_l05n_7 h22 7 io_l04p_7 c29 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 111 7 io_l04n_7 d29 7 io_l03p_7/vref_7 e28 7 io_l03n_7 d28 7 io_l02p_7/vrn_7 h23 7 io_l02n_7/vrp_7 g23 7 io_l01p_7 b30 7 io_l01n_7 c30 0 vcco_0 k20 0 vcco_0 k19 0 vcco_0 k18 0 vcco_0 k17 0 vcco_0 k16 0 vcco_0 j21 0 vcco_0 j20 0 vcco_0 j19 0 vcco_0 j18 0 vcco_0 c18 0 vcco_0 b26 1 vcco_1 k15 1 vcco_1 k14 1 vcco_1 k13 1 vcco_1 k12 1 vcco_1 k11 1 vcco_1 j13 1 vcco_1 j12 1 vcco_1 j11 1 vcco_1 j10 1 vcco_1 c13 1 vcco_1 b5 2 vcco_2 r10 2 vcco_2 p10 2 vcco_2 n10 2 vcco_2 n9 2 vcco_2 n3 2 vcco_2 m10 2 vcco_2 m9 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 112 2 vcco_2 l10 2 vcco_2 l9 2 vcco_2 k9 2 vcco_2 e2 3 vcco_3 af2 3 vcco_3 aa9 3 vcco_3 y10 3 vcco_3 y9 3 vcco_3 w10 3 vcco_3 w9 3 vcco_3 v10 3 vcco_3 v9 3 vcco_3 v3 3 vcco_3 u10 3 vcco_3 t10 4 vcco_4 aj5 4 vcco_4 ah13 4 vcco_4 ab13 4 vcco_4 ab12 4 vcco_4 ab11 4 vcco_4 ab10 4 vcco_4 aa15 4 vcco_4 aa14 4 vcco_4 aa13 4 vcco_4 aa12 4 vcco_4 aa11 5 vcco_5 aj26 5 vcco_5 ah18 5 vcco_5 ab21 5 vcco_5 ab20 5 vcco_5 ab19 5 vcco_5 ab18 5 vcco_5 aa20 5 vcco_5 aa19 5 vcco_5 aa18 5 vcco_5 aa17 5 vcco_5 aa16 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 113 6 vcco_6 af29 6 vcco_6 aa22 6 vcco_6 y22 6 vcco_6 y21 6 vcco_6 w22 6 vcco_6 w21 6 vcco_6 v28 6 vcco_6 v22 6 vcco_6 v21 6 vcco_6 u21 6 vcco_6 t21 7 vcco_7 r21 7 vcco_7 p21 7 vcco_7 n28 7 vcco_7 n22 7 vcco_7 n21 7 vcco_7 m22 7 vcco_7 m21 7 vcco_7 l22 7 vcco_7 l21 7 vcco_7 k22 7 vcco_7 e29 na cclk af6 na prog_b b28 na done ag5 na m0 af25 na m1 ag26 na m2 ah27 na hswap_en c27 na tck d5 na tdi a29 na tdo b3 na tms c4 na pwrdwn_b ah4 na dxn d26 na dxp e25 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 114 na vbatt a2 na rsvd e6 na vccaux ak28 na vccaux ak16 na vccaux ak3 na vccaux t1 na vccaux r30 na vccaux a28 na vccaux a15 na vccaux a3 na vccint ab22 na vccint ab9 na vccint aa21 na vccint aa10 na vccint y20 na vccint y19 na vccint y18 na vccint y17 na vccint y16 na vccint y15 na vccint y14 na vccint y13 na vccint y12 na vccint y11 na vccint w20 na vccint w11 na vccint v20 na vccint v11 na vccint u20 na vccint u11 na vccint t20 na vccint t11 na vccint r20 na vccint r11 na vccint p20 na vccint p11 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 115 na vccint n20 na vccint n11 na vccint m20 na vccint m11 na vccint l20 na vccint l19 na vccint l18 na vccint l17 na vccint l16 na vccint l15 na vccint l14 na vccint l13 na vccint l12 na vccint l11 na vccint k21 na vccint k10 na vccint j22 na vccint j9 na gnd ak23 na gnd ak8 na gnd aj29 na gnd aj2 na gnd ah28 na gnd ah21 na gnd ah10 na gnd ah3 na gnd ag27 na gnd ag4 na gnd af26 na gnd af19 na gnd af12 na gnd af5 na gnd ae25 na gnd ae6 na gnd ad17 na gnd ad14 na gnd ac30 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 116 na gnd ac1 na gnd aa28 na gnd aa3 na gnd w26 na gnd w19 na gnd w18 na gnd w17 na gnd w16 na gnd w15 na gnd w14 na gnd w13 na gnd w12 na gnd w5 na gnd v19 na gnd v18 na gnd v17 na gnd v16 na gnd v15 na gnd v14 na gnd v13 na gnd v12 na gnd u24 na gnd u19 na gnd u18 na gnd u17 na gnd u16 na gnd u15 na gnd u14 na gnd u13 na gnd u12 na gnd u7 na gnd t19 na gnd t18 na gnd t17 na gnd t16 na gnd t15 na gnd t14 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 117 na gnd t13 na gnd t12 na gnd r19 na gnd r18 na gnd r17 na gnd r16 na gnd r15 na gnd r14 na gnd r13 na gnd r12 na gnd p24 na gnd p19 na gnd p18 na gnd p17 na gnd p16 na gnd p15 na gnd p14 na gnd p13 na gnd p12 na gnd p7 na gnd n19 na gnd n18 na gnd n17 na gnd n16 na gnd n15 na gnd n14 na gnd n13 na gnd n12 na gnd m26 na gnd m19 na gnd m18 na gnd m17 na gnd m16 na gnd m15 na gnd m14 na gnd m13 na gnd m12 table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 118 na gnd m5 na gnd k28 na gnd k3 na gnd h30 na gnd h1 na gnd g17 na gnd g14 na gnd f25 na gnd f6 na gnd e26 na gnd e19 na gnd e12 na gnd e5 na gnd d27 na gnd d4 na gnd c28 na gnd c21 na gnd c10 na gnd c3 na gnd b29 na gnd b2 na gnd a23 na gnd a8 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. table 11: ff896 bga ? xc2v1000, xc2v1500, and XC2V2000 bank pin description pin number no connect in the xc2v1000 no connect in the xc2v1500
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 119 ff896 flip-chip fine-pitch bga pack age specifications (1.00mm pitch) figure 7: ff896 flip-chip fine-pitch bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 120 ff1152 flip-chip fine-pitch bga package as shown in ta b l e 1 2 , xc2v3000, xc2v4000, xc2v6000, and xc2v8000 virtex-ii devices are available in the ff1152 flip-chip fine-pitch bga package. pins in each of these devices are the same, except for the pin differences in the xc2v3000 device shown in the no connect co lumn. following this table are the ff1152 flip-chip fine-pitch bga package specifications (1.00mm pitch) . ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000 0 io_l01n_0 d29 0 io_l01p_0 c29 0 io_l02n_0 h26 0 io_l02p_0 g26 0 io_l03n_0/vrp_0 e28 0 io_l03p_0/vrn_0 e27 0 io_l04n_0/vref_0 f25 0 io_l04p_0 f26 0 io_l05n_0 h25 0 io_l05p_0 h24 0 io_l06n_0 e26 0 io_l06p_0 f27 0 io_l19n_0 b32 0 io_l19p_0 c33 0 io_l20n_0 j24 0 io_l20p_0 j23 0 io_l21n_0 c27 0 io_l21p_0/vref_0 c28 0 io_l22n_0 b30 0 io_l22p_0 b31 0 io_l23n_0 k23 0 io_l23p_0 k22 0 io_l24n_0 c26 0 io_l24p_0 d27 0 io_l25n_0 a30 0 io_l25p_0 a31 0 io_l26n_0 g24 0 io_l26p_0 g25 0 io_l27n_0 e25 0 io_l27p_0/vref_0 e24 0 io_l28n_0 d25
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 121 0 io_l28p_0 d26 0 io_l29n_0 h23 0 io_l29p_0 h22 0 io_l30n_0 f23 0 io_l30p_0 f24 0 io_l49n_0 b28 0 io_l49p_0 b29 0 io_l50n_0 j22 0 io_l50p_0 j21 0 io_l51n_0 a28 0 io_l51p_0/vref_0 a29 0 io_l52n_0 a26 0 io_l52p_0 b27 0 io_l53n_0 c24 0 io_l53p_0 d24 0 io_l54n_0 d22 0 io_l54p_0 d23 0 io_l60n_0 b25 nc 0 io_l60p_0 b26 nc 0 io_l67n_0 b23 0 io_l67p_0 b24 0 io_l68n_0 g22 0 io_l68p_0 g23 0 io_l69n_0 f22 0 io_l69p_0/vref_0 f21 0 io_l70n_0 a23 0 io_l70p_0 a24 0 io_l71n_0 k21 0 io_l71p_0 k20 0 io_l72n_0 c22 0 io_l72p_0 c23 0 io_l73n_0 e21 0 io_l73p_0 e22 0 io_l74n_0 h21 0 io_l74p_0 h20 0 io_l75n_0 g20 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 122 0 io_l75p_0/vref_0 f20 0 io_l76n_0 b21 0 io_l76p_0 b22 0 io_l77n_0 j20 0 io_l77p_0 k19 0 io_l78n_0 d20 0 io_l78p_0 d21 0 io_l79n_0 a21 nc 0 io_l79p_0 a22 nc 0 io_l80n_0 l19 nc 0 io_l80p_0 l18 nc 0 io_l81n_0 b19 nc 0 io_l81p_0/vref_0 a20 nc 0 io_l82n_0 a18 nc 0 io_l82p_0 b18 nc 0 io_l83n_0 h19 nc 0 io_l83p_0 h18 nc 0 io_l84n_0 c20 nc 0 io_l84p_0 c21 nc 0 io_l91n_0/vref_0 d19 0 io_l91p_0 d18 0 io_l92n_0 g18 0 io_l92p_0 g19 0 io_l93n_0 f18 0 io_l93p_0 f19 0 io_l94n_0/vref_0 c19 0 io_l94p_0 c18 0 io_l95n_0/gclk7p k18 0 io_l95p_0/gclk6s j18 0 io_l96n_0/gclk5p e19 0 io_l96p_0/gclk4s e18 1 io_l96n_1/gclk3p e17 1 io_l96p_1/gclk2s e16 1 io_l95n_1/gclk1p h17 1 io_l95p_1/gclk0s h16 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 123 1 io_l94n_1 d17 1 io_l94p_1/vref_1 d16 1 io_l93n_1 f16 1 io_l93p_1 f17 1 io_l92n_1 g16 1 io_l92p_1 g17 1 io_l91n_1 c16 1 io_l91p_1/vref_1 c15 1 io_l84n_1 d14 nc 1 io_l84p_1 d15 nc 1 io_l83n_1 j17 nc 1 io_l83p_1 k17 nc 1 io_l82n_1 b17 nc 1 io_l82p_1 a17 nc 1 io_l81n_1/vref_1 a15 nc 1 io_l81p_1 b16 nc 1 io_l80n_1 l17 nc 1 io_l80p_1 l16 nc 1 io_l79n_1 a13 nc 1 io_l79p_1 a14 nc 1 io_l78n_1 c13 1 io_l78p_1 c14 1 io_l77n_1 k16 1 io_l77p_1 k15 1 io_l76n_1 b13 1 io_l76p_1 b14 1 io_l75n_1/vref_1 f15 1 io_l75p_1 g15 1 io_l74n_1 h15 1 io_l74p_1 h14 1 io_l73n_1 a11 1 io_l73p_1 a12 1 io_l72n_1 e13 1 io_l72p_1 e14 1 io_l71n_1 j15 1 io_l71p_1 j14 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 124 1 io_l70n_1 d12 1 io_l70p_1 d13 1 io_l69n_1/vref_1 f14 1 io_l69p_1 f13 1 io_l68n_1 c11 1 io_l68p_1 c12 1 io_l67n_1 b11 1 io_l67p_1 b12 1 io_l60n_1 f11 nc 1 io_l60p_1 f12 nc 1 io_l54n_1 d10 1 io_l54p_1 d11 1 io_l53n_1 g12 1 io_l53p_1 g13 1 io_l52n_1 b9 1 io_l52p_1 b10 1 io_l51n_1/vref_1 b8 1 io_l51p_1 a9 1 io_l50n_1 k14 1 io_l50p_1 k13 1 io_l49n_1 a6 1 io_l49p_1 a7 1 io_l30n_1 d9 1 io_l30p_1 c9 1 io_l29n_1 h13 1 io_l29p_1 h12 1 io_l28n_1 c7 1 io_l28p_1 c8 1 io_l27n_1/vref_1 e11 1 io_l27p_1 e10 1 io_l26n_1 j13 1 io_l26p_1 k12 1 io_l25n_1 b6 1 io_l25p_1 b7 1 io_l24n_1 e8 1 io_l24p_1 e9 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 125 1 io_l23n_1 g10 1 io_l23p_1 g11 1 io_l22n_1 a4 1 io_l22p_1 a5 1 io_l21n_1/vref_1 f10 1 io_l21p_1 g9 1 io_l20n_1 j12 1 io_l20p_1 j11 1 io_l19n_1 b4 1 io_l19p_1 b5 1 io_l06n_1 d6 1 io_l06p_1 c6 1 io_l05n_1 h11 1 io_l05p_1 j10 1 io_l04n_1 d8 1 io_l04p_1/vref_1 e7 1 io_l03n_1/vrp_1 f9 1 io_l03p_1/vrn_1 f8 1 io_l02n_1 h10 1 io_l02p_1 h9 1 io_l01n_1 c2 1 io_l01p_1 b3 2 io_l01n_2 e2 2 io_l01p_2 d2 2 io_l02n_2/vrp_2 k11 2 io_l02p_2/vrn_2 k10 2 io_l03n_2 f5 2 io_l03p_2/vref_2 g5 2 io_l04n_2 e3 2 io_l04p_2 d3 2 io_l05n_2 j9 2 io_l05p_2 k9 2 io_l06n_2 f4 2 io_l06p_2 e4 2 io_l19n_2 e1 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 126 2 io_l19p_2 d1 2 io_l20n_2 j8 2 io_l20p_2 k8 2 io_l21n_2 h7 2 io_l21p_2/vref_2 j7 2 io_l22n_2 h6 2 io_l22p_2 g6 2 io_l23n_2 l10 2 io_l23p_2 l9 2 io_l24n_2 g3 2 io_l24p_2 f3 2 io_l25n_2 g2 2 io_l25p_2 f2 2 io_l26n_2 m10 2 io_l26p_2 n10 2 io_l27n_2 j6 2 io_l27p_2/vref_2 k6 2 io_l28n_2 j5 2 io_l28p_2 h5 2 io_l29n_2 l7 2 io_l29p_2 k7 2 io_l30n_2 j4 2 io_l30p_2 h4 2 io_l43n_2 g1 2 io_l43p_2 f1 2 io_l44n_2 l8 2 io_l44p_2 m8 2 io_l45n_2 j1 2 io_l45p_2/vref_2 h2 2 io_l46n_2 j3 2 io_l46p_2 h3 2 io_l47n_2 m9 2 io_l47p_2 n9 2 io_l48n_2 l5 2 io_l48p_2 k5 2 io_l49n_2 k2 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 127 2 io_l49p_2 j2 2 io_l50n_2 n7 2 io_l50p_2 m7 2 io_l51n_2 l6 2 io_l51p_2/vref_2 m6 2 io_l52n_2 m3 2 io_l52p_2 l3 2 io_l53n_2 l4 2 io_l53p_2 k4 2 io_l54n_2 n4 2 io_l54p_2 m4 2 io_l67n_2 m2 2 io_l67p_2 l2 2 io_l68n_2 n8 2 io_l68p_2 p8 2 io_l69n_2 n6 2 io_l69p_2/vref_2 p6 2 io_l70n_2 p5 2 io_l70p_2 n5 2 io_l71n_2 p10 2 io_l71p_2 r10 2 io_l72n_2 p3 2 io_l72p_2 n3 2 io_l73n_2 m1 2 io_l73p_2 l1 2 io_l74n_2 p9 2 io_l74p_2 r9 2 io_l75n_2 p2 2 io_l75p_2/vref_2 n2 2 io_l76n_2 r4 2 io_l76p_2 p4 2 io_l77n_2 r8 2 io_l77p_2 t8 2 io_l78n_2 t3 2 io_l78p_2 r3 2 io_l79n_2 p1 nc ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 128 2 io_l79p_2 n1 nc 2 io_l80n_2 t11 nc 2 io_l80p_2 u11 nc 2 io_l81n_2 r7 nc 2 io_l81p_2/vref_2 r6 nc 2 io_l82n_2 u5 nc 2 io_l82p_2 t5 nc 2 io_l83n_2 t10 nc 2 io_l83p_2 u10 nc 2 io_l84n_2 u4 nc 2 io_l84p_2 t4 nc 2 io_l91n_2 t2 2 io_l91p_2 r1 2 io_l92n_2 u7 2 io_l92p_2 t7 2 io_l93n_2 t6 2 io_l93p_2/vref_2 u6 2 io_l94n_2 u1 2 io_l94p_2 u2 2 io_l95n_2 u9 2 io_l95p_2 u8 2 io_l96n_2 u3 2 io_l96p_2 v4 3 io_l96n_3 v6 3 io_l96p_3 w6 3 io_l95n_3 v5 3 io_l95p_3 w5 3 io_l94n_3 v7 3 io_l94p_3 w7 3 io_l93n_3/vref_3 v10 3 io_l93p_3 w10 3 io_l92n_3 v1 3 io_l92p_3 v2 3 io_l91n_3 w3 3 io_l91p_3 y3 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 129 3 io_l84n_3 v9 nc 3 io_l84p_3 v8 nc 3 io_l83n_3 w4 nc 3 io_l83p_3 y4 nc 3 io_l82n_3 w11 nc 3 io_l82p_3 v11 nc 3 io_l81n_3/vref_3 w8 nc 3 io_l81p_3 y8 nc 3 io_l80n_3 w2 nc 3 io_l80p_3 y1 nc 3 io_l79n_3 aa3 nc 3 io_l79p_3 ab3 nc 3 io_l78n_3 y6 3 io_l78p_3 aa6 3 io_l77n_3 aa4 3 io_l77p_3 ab4 3 io_l76n_3 y7 3 io_l76p_3 aa8 3 io_l75n_3/vref_3 y10 3 io_l75p_3 aa10 3 io_l74n_3 aa1 3 io_l74p_3 ab1 3 io_l73n_3 aa5 3 io_l73p_3 ab5 3 io_l72n_3 aa9 3 io_l72p_3 y9 3 io_l71n_3 aa2 3 io_l71p_3 ab2 3 io_l70n_3 ab6 3 io_l70p_3 ac6 3 io_l69n_3/vref_3 ad1 3 io_l69p_3 ac1 3 io_l68n_3 ac3 3 io_l68p_3 ad3 3 io_l67n_3 ac4 3 io_l67p_3 ad4 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 130 3 io_l54n_3 ab7 3 io_l54p_3 ac7 3 io_l53n_3 ac2 3 io_l53p_3 ad2 3 io_l52n_3 ac8 3 io_l52p_3 ab8 3 io_l51n_3/vref_3 ab10 3 io_l51p_3 ac10 3 io_l50n_3 ad5 3 io_l50p_3 ae5 3 io_l49n_3 ae4 3 io_l49p_3 af4 3 io_l48n_3 ab9 3 io_l48p_3 ac9 3 io_l47n_3 ae2 3 io_l47p_3 af1 3 io_l46n_3 ad6 3 io_l46p_3 ae6 3 io_l45n_3/vref_3 ad9 3 io_l45p_3 ae9 3 io_l44n_3 af2 3 io_l44p_3 ag2 3 io_l43n_3 af3 3 io_l43p_3 ag3 3 io_l30n_3 ad7 3 io_l30p_3 ae7 3 io_l29n_3 af5 3 io_l29p_3 ag5 3 io_l28n_3 ae8 3 io_l28p_3 ad8 3 io_l27n_3/vref_3 af8 3 io_l27p_3 af9 3 io_l26n_3 ah1 3 io_l26p_3 aj1 3 io_l25n_3 ag4 3 io_l25p_3 ah5 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 131 3 io_l24n_3 af6 3 io_l24p_3 ag6 3 io_l23n_3 ah3 3 io_l23p_3 aj3 3 io_l22n_3 af7 3 io_l22p_3 ag7 3 io_l21n_3/vref_3 al1 3 io_l21p_3 ak1 3 io_l20n_3 ah2 3 io_l20p_3 aj2 3 io_l19n_3 aj4 3 io_l19p_3 ak4 3 io_l06n_3 ae10 3 io_l06p_3 ad10 3 io_l05n_3 ak2 3 io_l05p_3 al2 3 io_l04n_3 ah6 3 io_l04p_3 aj5 3 io_l03n_3/vref_3 ae11 3 io_l03p_3 af11 3 io_l02n_3/vrp_3 ak3 3 io_l02p_3/vrn_3 al3 3 io_l01n_3 af10 3 io_l01p_3 ag9 4 io_l01n_4/busy/dout (1) am4 4 io_l01p_4/init_b al5 4 io_l02n_4/d0/din (1) ag10 4 io_l02p_4/d1 ah11 4 io_l03n_4/d2/alt_vrp_4 ak7 4 io_l03p_4/d3/alt_vrn_4 ak8 4 io_l04n_4/vref_4 al6 4 io_l04p_4 am6 4 io_l05n_4/vrp_4 ak9 4 io_l05p_4/vrn_4 aj8 4 io_l06n_4 am8 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 132 4 io_l06p_4 am7 4 io_l19n_4 an3 4 io_l19p_4 am2 4 io_l20n_4 aj10 4 io_l20p_4 aj9 4 io_l21n_4 ah9 4 io_l21p_4/vref_4 ah10 4 io_l22n_4 an5 4 io_l22p_4 an4 4 io_l23n_4 ae12 4 io_l23p_4 ae13 4 io_l24n_4 am9 4 io_l24p_4 al8 4 io_l25n_4 ap5 4 io_l25p_4 ap4 4 io_l26n_4 ag11 4 io_l26p_4 ag12 4 io_l27n_4 an7 4 io_l27p_4/vref_4 an6 4 io_l28n_4 al10 4 io_l28p_4 al9 4 io_l29n_4 af12 4 io_l29p_4 af13 4 io_l30n_4 ak10 4 io_l30p_4 ak11 4 io_l49n_4 ap7 4 io_l49p_4 ap6 4 io_l50n_4 ah13 4 io_l50p_4 ah12 4 io_l51n_4 aj11 4 io_l51p_4/vref_4 aj12 4 io_l52n_4 ap9 4 io_l52p_4 an8 4 io_l53n_4 ag13 4 io_l53p_4 ag14 4 io_l54n_4 am11 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 133 4 io_l54p_4 al11 4 io_l60n_4 an10 nc 4 io_l60p_4 an9 nc 4 io_l67n_4 an12 4 io_l67p_4 an11 4 io_l68n_4 ae14 4 io_l68p_4 ae15 4 io_l69n_4 aj13 4 io_l69p_4/vref_4 aj14 4 io_l70n_4 al13 4 io_l70p_4 al12 4 io_l71n_4 af14 4 io_l71p_4 af15 4 io_l72n_4 am13 4 io_l72p_4 am12 4 io_l73n_4 ap12 4 io_l73p_4 ap11 4 io_l74n_4 ag15 4 io_l74p_4 ag16 4 io_l75n_4 an14 4 io_l75p_4/vref_4 an13 4 io_l76n_4 ap14 4 io_l76p_4 ap13 4 io_l77n_4 ad16 4 io_l77p_4 ad17 4 io_l78n_4 ak14 4 io_l78p_4 ak13 4 io_l79n_4 an16 nc 4 io_l79p_4 ap15 nc 4 io_l80n_4 ae16 nc 4 io_l80p_4 ae17 nc 4 io_l81n_4 ah15 nc 4 io_l81p_4/vref_4 aj15 nc 4 io_l82n_4 ap17 nc 4 io_l82p_4 an17 nc 4 io_l83n_4 ah17 nc ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 134 4 io_l83p_4 ah16 nc 4 io_l84n_4 al15 nc 4 io_l84p_4 al14 nc 4 io_l91n_4/vref_4 al16 4 io_l91p_4 al17 4 io_l92n_4 aj17 4 io_l92p_4 aj16 4 io_l93n_4 am15 4 io_l93p_4 am14 4 io_l94n_4/vref_4 am16 4 io_l94p_4 am17 4 io_l95n_4/gclk3s af17 4 io_l95p_4/gclk2p ag17 4 io_l96n_4/gclk1s ak16 4 io_l96p_4/gclk0p ak17 5 io_l96n_5/gclk7s ak18 5 io_l96p_5/gclk6p ak19 5 io_l95n_5/gclk5s ag18 5 io_l95p_5/gclk4p af18 5 io_l94n_5 al18 5 io_l94p_5/vref_5 al19 5 io_l93n_5 aj19 5 io_l93p_5 aj18 5 io_l92n_5 ah19 5 io_l92p_5 ah18 5 io_l91n_5 am19 5 io_l91p_5/vref_5 am20 5 io_l84n_5 al21 nc 5 io_l84p_5 al20 nc 5 io_l83n_5 am22 nc 5 io_l83p_5 am21 nc 5 io_l82n_5 an18 nc 5 io_l82p_5 ap18 nc 5 io_l81n_5/vref_5 ap20 nc 5 io_l81p_5 an19 nc ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 135 5 io_l80n_5 ae18 nc 5 io_l80p_5 ae19 nc 5 io_l79n_5 ap22 nc 5 io_l79p_5 ap21 nc 5 io_l78n_5 ak22 5 io_l78p_5 ak21 5 io_l77n_5 ad18 5 io_l77p_5 ad19 5 io_l76n_5 an22 5 io_l76p_5 an21 5 io_l75n_5/vref_5 aj20 5 io_l75p_5 ah20 5 io_l74n_5 ag19 5 io_l74p_5 ag20 5 io_l73n_5 ap24 5 io_l73p_5 ap23 5 io_l72n_5 al23 5 io_l72p_5 al22 5 io_l71n_5 af20 5 io_l71p_5 af21 5 io_l70n_5 am24 5 io_l70p_5 am23 5 io_l69n_5/vref_5 aj21 5 io_l69p_5 aj22 5 io_l68n_5 aj24 5 io_l68p_5 aj23 5 io_l67n_5 an24 5 io_l67p_5 an23 5 io_l60n_5 an26 nc 5 io_l60p_5 an25 nc 5 io_l54n_5 al25 5 io_l54p_5 al24 5 io_l53n_5 ae20 5 io_l53p_5 ae21 5 io_l52n_5 an27 5 io_l52p_5 ap26 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 136 5 io_l51n_5/vref_5 ap29 5 io_l51p_5 ap28 5 io_l50n_5 ag21 5 io_l50p_5 ag22 5 io_l49n_5 an29 5 io_l49p_5 an28 5 io_l30n_5 ak24 5 io_l30p_5 ak25 5 io_l29n_5 ah23 5 io_l29p_5 ah22 5 io_l28n_5 ap31 5 io_l28p_5 ap30 5 io_l27n_5/vref_5 ah24 5 io_l27p_5 ah25 5 io_l26n_5 af22 5 io_l26p_5 af23 5 io_l25n_5 am27 5 io_l25p_5 am26 5 io_l24n_5 al27 5 io_l24p_5 al26 5 io_l23n_5 ah26 5 io_l23p_5 aj25 5 io_l22n_5 an31 5 io_l22p_5 an30 5 io_l21n_5/vref_5 ak26 5 io_l21p_5 ak27 5 io_l20n_5 ag23 5 io_l20p_5 af24 5 io_l19n_5 am33 5 io_l19p_5 an32 5 io_l06n_5 aj27 5 io_l06p_5 aj26 5 io_l05n_5/vrp_5 ae22 5 io_l05p_5/vrn_5 ae23 5 io_l04n_5 am28 5 io_l04p_5/vref_5 am29 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 137 5 io_l03n_5/d4/alt_vrp_5 ak28 5 io_l03p_5/d5/alt_vrn_5 al29 5 io_l02n_5/d6 ag24 5 io_l02p_5/d7 ag25 5 io_l01n_5/rdwr_b al30 5 io_l01p_5/cs_b am31 6 io_l01p_6 ae24 6 io_l01n_6 ad25 6 io_l02p_6/vrn_6 aj30 6 io_l02n_6/vrp_6 ah30 6 io_l03p_6 al32 6 io_l03n_6/vref_6 ak32 6 io_l04p_6 af25 6 io_l04n_6 ae25 6 io_l05p_6 aj31 6 io_l05n_6 ak31 6 io_l06p_6 ah29 6 io_l06n_6 ag29 6 io_l19p_6 ag26 6 io_l19n_6 af26 6 io_l20p_6 al33 6 io_l20n_6 ak33 6 io_l21p_6 aj32 6 io_l21n_6/vref_6 ah32 6 io_l22p_6 ag28 6 io_l22n_6 af28 6 io_l23p_6 ag30 6 io_l23n_6 af30 6 io_l24p_6 af29 6 io_l24n_6 ae29 6 io_l25p_6 af27 6 io_l25n_6 ae27 6 io_l26p_6 al34 6 io_l26n_6 ak34 6 io_l27p_6 ae28 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 138 6 io_l27n_6/vref_6 ad28 6 io_l28p_6 ae26 6 io_l28n_6 ad26 6 io_l29p_6 af31 6 io_l29n_6 ag31 6 io_l30p_6 af32 6 io_l30n_6 ag32 6 io_l43p_6 ac25 6 io_l43n_6 ab25 6 io_l44p_6 aj33 6 io_l44n_6 ah33 6 io_l45p_6 ae31 6 io_l45n_6/vref_6 ad32 6 io_l46p_6 ad27 6 io_l46n_6 ac27 6 io_l47p_6 aj34 6 io_l47n_6 ah34 6 io_l48p_6 ae30 6 io_l48n_6 ad30 6 io_l49p_6 ac26 6 io_l49n_6 ab26 6 io_l50p_6 ad29 6 io_l50n_6 ac29 6 io_l51p_6 af33 6 io_l51n_6/vref_6 ag33 6 io_l52p_6 ac28 6 io_l52n_6 ab28 6 io_l53p_6 af34 6 io_l53n_6 ae33 6 io_l54p_6 ab27 6 io_l54n_6 aa27 6 io_l67p_6 aa25 6 io_l67n_6 y25 6 io_l68p_6 ad33 6 io_l68n_6 ac33 6 io_l69p_6 ac32 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 139 6 io_l69n_6/vref_6 ab32 6 io_l70p_6 aa26 6 io_l70n_6 y26 6 io_l71p_6 ad34 6 io_l71n_6 ac34 6 io_l72p_6 ac31 6 io_l72n_6 ad31 6 io_l73p_6 y27 6 io_l73n_6 w27 6 io_l74p_6 ab29 6 io_l74n_6 aa29 6 io_l75p_6 ab31 6 io_l75n_6/vref_6 aa31 6 io_l76p_6 y28 6 io_l76n_6 y29 6 io_l77p_6 ab33 6 io_l77n_6 aa33 6 io_l78p_6 aa30 6 io_l78n_6 ab30 6 io_l79p_6 w24 nc 6 io_l79n_6 v24 nc 6 io_l80p_6 ab34 nc 6 io_l80n_6 aa34 nc 6 io_l81p_6 w33 nc 6 io_l81n_6/vref_6 y34 nc 6 io_l82p_6 w25 nc 6 io_l82n_6 v25 nc 6 io_l83p_6 y32 nc 6 io_l83n_6 aa32 nc 6 io_l84p_6 w29 nc 6 io_l84n_6 v29 nc 6 io_l91p_6 w28 6 io_l91n_6 v28 6 io_l92p_6 v33 6 io_l92n_6 v34 6 io_l93p_6 y31 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 140 6 io_l93n_6/vref_6 w31 6 io_l94p_6 v26 6 io_l94n_6 v27 6 io_l95p_6 w30 6 io_l95n_6 v30 6 io_l96p_6 v32 6 io_l96n_6 w32 7 io_l96p_7 u31 7 io_l96n_7 v31 7 io_l95p_7 t28 7 io_l95n_7 u28 7 io_l94p_7 u33 7 io_l94n_7 u34 7 io_l93p_7/vref_7 u29 7 io_l93n_7 t29 7 io_l92p_7 u27 7 io_l92n_7 u26 7 io_l91p_7 t30 7 io_l91n_7 u30 7 io_l84p_7 r32 nc 7 io_l84n_7 t32 nc 7 io_l83p_7 u25 nc 7 io_l83n_7 t25 nc 7 io_l82p_7 r34 nc 7 io_l82n_7 t33 nc 7 io_l81p_7/vref_7 n34 nc 7 io_l81n_7 p34 nc 7 io_l80p_7 u24 nc 7 io_l80n_7 t24 nc 7 io_l79p_7 r31 nc 7 io_l79n_7 t31 nc 7 io_l78p_7 n32 7 io_l78n_7 p32 7 io_l77p_7 t27 7 io_l77n_7 r27 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 141 7 io_l76p_7 n33 7 io_l76n_7 p33 7 io_l75p_7/vref_7 r29 7 io_l75n_7 r28 7 io_l74p_7 r26 7 io_l74n_7 p26 7 io_l73p_7 n31 7 io_l73n_7 p31 7 io_l72p_7 n30 7 io_l72n_7 p30 7 io_l71p_7 r25 7 io_l71n_7 p25 7 io_l70p_7 l34 7 io_l70n_7 m34 7 io_l69p_7/vref_7 p29 7 io_l69n_7 n29 7 io_l68p_7 p27 7 io_l68n_7 n27 7 io_l67p_7 l32 7 io_l67n_7 m32 7 io_l54p_7 l31 7 io_l54n_7 m31 7 io_l53p_7 k29 7 io_l53n_7 l30 7 io_l52p_7 l33 7 io_l52n_7 m33 7 io_l51p_7/vref_7 m29 7 io_l51n_7 l29 7 io_l50p_7 m28 7 io_l50n_7 n28 7 io_l49p_7 k30 7 io_l49n_7 k31 7 io_l48p_7 h32 7 io_l48n_7 j32 7 io_l47p_7 n26 7 io_l47n_7 m26 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 142 7 io_l46p_7 j33 7 io_l46n_7 k33 7 io_l45p_7/vref_7 h33 7 io_l45n_7 j34 7 io_l44p_7 m27 7 io_l44n_7 l27 7 io_l43p_7 h31 7 io_l43n_7 j31 7 io_l30p_7 f32 7 io_l30n_7 g32 7 io_l29p_7 n25 7 io_l29n_7 m25 7 io_l28p_7 f34 7 io_l28n_7 g34 7 io_l27p_7/vref_7 j30 7 io_l27n_7 h30 7 io_l26p_7 k28 7 io_l26n_7 l28 7 io_l25p_7 h28 7 io_l25n_7 j29 7 io_l24p_7 g29 7 io_l24n_7 h29 7 io_l23p_7 l26 7 io_l23n_7 k26 7 io_l22p_7 f33 7 io_l22n_7 g33 7 io_l21p_7/vref_7 j28 7 io_l21n_7 j27 7 io_l20p_7 k27 7 io_l20n_7 j26 7 io_l19p_7 e31 7 io_l19n_7 f31 7 io_l06p_7 d32 7 io_l06n_7 e32 7 io_l05p_7 l25 7 io_l05n_7 k24 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 143 7 io_l04p_7 d34 7 io_l04n_7 e34 7 io_l03p_7/vref_7 g30 7 io_l03n_7 f30 7 io_l02p_7/vrn_7 k25 7 io_l02n_7/vrp_7 j25 7 io_l01p_7 d33 7 io_l01n_7 e33 0 vcco_0 m22 0 vcco_0 m21 0 vcco_0 m20 0 vcco_0 m19 0 vcco_0 m18 0 vcco_0 l23 0 vcco_0 l22 0 vcco_0 l21 0 vcco_0 l20 0 vcco_0 e20 0 vcco_0 d28 0 vcco_0 a25 0 vcco_0 a19 1 vcco_1 m17 1 vcco_1 m16 1 vcco_1 m15 1 vcco_1 m14 1 vcco_1 m13 1 vcco_1 l15 1 vcco_1 l14 1 vcco_1 l13 1 vcco_1 l12 1 vcco_1 e15 1 vcco_1 d7 1 vcco_1 a16 1 vcco_1 a10 2 vcco_2 u12 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 144 2 vcco_2 t12 2 vcco_2 t1 2 vcco_2 r12 2 vcco_2 r11 2 vcco_2 r5 2 vcco_2 p12 2 vcco_2 p11 2 vcco_2 n12 2 vcco_2 n11 2 vcco_2 m11 2 vcco_2 k1 2 vcco_2 g4 3 vcco_3 ah4 3 vcco_3 ae1 3 vcco_3 ac11 3 vcco_3 ab12 3 vcco_3 ab11 3 vcco_3 aa12 3 vcco_3 aa11 3 vcco_3 y12 3 vcco_3 y11 3 vcco_3 y5 3 vcco_3 w12 3 vcco_3 w1 3 vcco_3 v12 4 vcco_4 ap16 4 vcco_4 ap10 4 vcco_4 al7 4 vcco_4 ak15 4 vcco_4 ad15 4 vcco_4 ad14 4 vcco_4 ad13 4 vcco_4 ad12 4 vcco_4 ac17 4 vcco_4 ac16 4 vcco_4 ac15 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 145 4 vcco_4 ac14 4 vcco_4 ac13 5 vcco_5 ap25 5 vcco_5 ap19 5 vcco_5 al28 5 vcco_5 ak20 5 vcco_5 ad23 5 vcco_5 ad22 5 vcco_5 ad21 5 vcco_5 ad20 5 vcco_5 ac22 5 vcco_5 ac21 5 vcco_5 ac20 5 vcco_5 ac19 5 vcco_5 ac18 6 vcco_6 ah31 6 vcco_6 ae34 6 vcco_6 ac24 6 vcco_6 ab24 6 vcco_6 ab23 6 vcco_6 aa24 6 vcco_6 aa23 6 vcco_6 y30 6 vcco_6 y24 6 vcco_6 y23 6 vcco_6 w34 6 vcco_6 w23 6 vcco_6 v23 7 vcco_7 u23 7 vcco_7 t34 7 vcco_7 t23 7 vcco_7 r30 7 vcco_7 r24 7 vcco_7 r23 7 vcco_7 p24 7 vcco_7 p23 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 146 7 vcco_7 n24 7 vcco_7 n23 7 vcco_7 m24 7 vcco_7 k34 7 vcco_7 g31 na cclk ah8 na prog_b d30 na done aj7 na m0 ah27 na m1 aj28 na m2 ak29 na hswap_en e29 na tck f7 na tdi c31 na tdo d5 na tms e6 na pwrdwn_b ak6 na dxn f28 na dxp g27 na vbatt c4 na rsvd g8 na vccaux am30 na vccaux am18 na vccaux am5 na vccaux v3 na vccaux u32 na vccaux c30 na vccaux c17 na vccaux c5 na vccint ad24 na vccint ad11 na vccint ac23 na vccint ac12 na vccint ab22 na vccint ab21 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 147 na vccint ab20 na vccint ab19 na vccint ab18 na vccint ab17 na vccint ab16 na vccint ab15 na vccint ab14 na vccint ab13 na vccint aa22 na vccint aa13 na vccint y22 na vccint y13 na vccint w22 na vccint w13 na vccint v22 na vccint v13 na vccint u22 na vccint u13 na vccint t22 na vccint t13 na vccint r22 na vccint r13 na vccint p22 na vccint p13 na vccint n22 na vccint n21 na vccint n20 na vccint n19 na vccint n18 na vccint n17 na vccint n16 na vccint n15 na vccint n14 na vccint n13 na vccint m23 na vccint m12 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 148 na vccint l24 na vccint l11 na gnd ap33 na gnd ap32 na gnd ap27 na gnd ap8 na gnd ap3 na gnd ap2 na gnd an34 na gnd an33 na gnd an20 na gnd an15 na gnd an2 na gnd an1 na gnd am34 na gnd am32 na gnd am25 na gnd am10 na gnd am3 na gnd am1 na gnd al31 na gnd al4 na gnd ak30 na gnd ak23 na gnd ak12 na gnd ak5 na gnd aj29 na gnd aj6 na gnd ah28 na gnd ah21 na gnd ah14 na gnd ah7 na gnd ag34 na gnd ag27 na gnd ag8 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 149 na gnd ag1 na gnd af19 na gnd af16 na gnd ae32 na gnd ae3 na gnd ac30 na gnd ac5 na gnd aa28 na gnd aa21 na gnd aa20 na gnd aa19 na gnd aa18 na gnd aa17 na gnd aa16 na gnd aa15 na gnd aa14 na gnd aa7 na gnd y33 na gnd y21 na gnd y20 na gnd y19 na gnd y18 na gnd y17 na gnd y16 na gnd y15 na gnd y14 na gnd y2 na gnd w26 na gnd w21 na gnd w20 na gnd w19 na gnd w18 na gnd w17 na gnd w16 na gnd w15 na gnd w14 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 150 na gnd w9 na gnd v21 na gnd v20 na gnd v19 na gnd v18 na gnd v17 na gnd v16 na gnd v15 na gnd v14 na gnd u21 na gnd u20 na gnd u19 na gnd u18 na gnd u17 na gnd u16 na gnd u15 na gnd u14 na gnd t26 na gnd t21 na gnd t20 na gnd t19 na gnd t18 na gnd t17 na gnd t16 na gnd t15 na gnd t14 na gnd t9 na gnd r33 na gnd r21 na gnd r20 na gnd r19 na gnd r18 na gnd r17 na gnd r16 na gnd r15 na gnd r14 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 151 na gnd r2 na gnd p28 na gnd p21 na gnd p20 na gnd p19 na gnd p18 na gnd p17 na gnd p16 na gnd p15 na gnd p14 na gnd p7 na gnd m30 na gnd m5 na gnd k32 na gnd k3 na gnd j19 na gnd j16 na gnd h34 na gnd h27 na gnd h8 na gnd h1 na gnd g28 na gnd g21 na gnd g14 na gnd g7 na gnd f29 na gnd f6 na gnd e30 na gnd e23 na gnd e12 na gnd e5 na gnd d31 na gnd d4 na gnd c34 na gnd c32 na gnd c25 ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 152 na gnd c10 na gnd c3 na gnd c1 na gnd b34 na gnd b33 na gnd b20 na gnd b15 na gnd b2 na gnd b1 na gnd a33 na gnd a32 na gnd a27 na gnd a8 na gnd a3 na gnd a2 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 1 2 : ff1152 bga ? xc2v3000, xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v3000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 153 ff1152 flip-chip fine-pitc h bga package specificat ions (1.00mm pitch) figure 8: ff1152 flip-chip fine-pitch bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 154 ff1517 flip-chip fine-pitch bga package as shown in ta bl e 1 3 , xc2v4000, xc2v6000, and xc2v8000 virtex-ii devices are available in the ff1517 flip-chip fine-pitch bga package. pins in each of these devices are the same, except for the pin differences in the xc2v4000 and xc2v6000 devices shown in the no connect columns. following this table are the ff1517 flip-chip fine-pitch bga package specifications (1.00mm pitch) . ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000 0 io_l01n_0 b36 0 io_l01p_0 c36 0 io_l02n_0 j30 0 io_l02p_0 j29 0 io_l03n_0/vrp_0 d33 0 io_l03p_0/vrn_0 d34 0 io_l04n_0/vref_0 c34 0 io_l04p_0 c35 0 io_l05n_0 h30 0 io_l05p_0 g30 0 io_l06n_0 d32 0 io_l06p_0 e33 0 io_l07n_0 a35 nc 0 io_l07p_0 a36 nc 0 io_l08n_0 k28 nc 0 io_l08p_0 j28 nc 0 io_l09n_0 e32 nc 0 io_l09p_0/vref_0 f32 nc 0 io_l10n_0 b34 nc 0 io_l10p_0 b35 nc 0 io_l11n_0 h29 nc 0 io_l11p_0 h28 nc 0 io_l12n_0 f31 nc 0 io_l12p_0 g31 nc 0 io_l19n_0 c32 0 io_l19p_0 c33 0 io_l20n_0 m26 0 io_l20p_0 m25 0 io_l21n_0 e30 0 io_l21p_0/vref_0 e31 0 io_l22n_0 a33
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 155 0 io_l22p_0 a34 0 io_l23n_0 k27 0 io_l23p_0 k26 0 io_l24n_0 f29 0 io_l24p_0 f30 0 io_l25n_0 b32 0 io_l25p_0 b33 0 io_l26n_0 l26 0 io_l26p_0 l25 0 io_l27n_0 g28 0 io_l27p_0/vref_0 g29 0 io_l28n_0 c30 0 io_l28p_0 c31 0 io_l29n_0 j27 0 io_l29p_0 j26 0 io_l30n_0 d30 0 io_l30p_0 d31 0 io_l31n_0 a31 nc 0 io_l31p_0 a32 nc 0 io_l32n_0 h27 nc 0 io_l32p_0 h26 nc 0 io_l33n_0 f27 nc 0 io_l33p_0/vref_0 f28 nc 0 io_l34n_0 b30 nc 0 io_l34p_0 b31 nc 0 io_l35n_0 m24 nc 0 io_l35p_0 m23 nc 0 io_l36n_0 d28 nc 0 io_l36p_0 d29 nc 0 io_l49n_0 c28 0 io_l49p_0 c29 0 io_l50n_0 k25 0 io_l50p_0 l24 0 io_l51n_0 e27 0 io_l51p_0/vref_0 e28 0 io_l52n_0 a29 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 156 0 io_l52p_0 a30 0 io_l53n_0 g26 0 io_l53p_0 g25 0 io_l54n_0 d26 0 io_l54p_0 d27 0 io_l55n_0 b27 0 io_l55p_0 b28 0 io_l56n_0 h25 0 io_l56p_0 h24 0 io_l57n_0 f25 0 io_l57p_0/vref_0 f26 0 io_l58n_0 a27 0 io_l58p_0 a28 0 io_l59n_0 k24 0 io_l59p_0 k23 0 io_l60n_0 e24 0 io_l60p_0 e25 0 io_l67n_0 c26 0 io_l67p_0 c27 0 io_l68n_0 j24 0 io_l68p_0 j23 0 io_l69n_0 d24 0 io_l69p_0/vref_0 d25 0 io_l70n_0 a25 0 io_l70p_0 a26 0 io_l71n_0 m22 0 io_l71p_0 m21 0 io_l72n_0 g23 0 io_l72p_0 g24 0 io_l73n_0 b25 0 io_l73p_0 c25 0 io_l74n_0 l22 0 io_l74p_0 l21 0 io_l75n_0 f23 0 io_l75p_0/vref_0 f24 0 io_l76n_0 c23 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 157 0 io_l76p_0 c24 0 io_l77n_0 k22 0 io_l77p_0 k21 0 io_l78n_0 e22 0 io_l78p_0 e23 0 io_l79n_0 b23 0 io_l79p_0 b24 0 io_l80n_0 j22 0 io_l80p_0 j21 0 io_l81n_0 g21 0 io_l81p_0/vref_0 g22 0 io_l82n_0 a23 0 io_l82p_0 a24 0 io_l83n_0 h22 0 io_l83p_0 h21 0 io_l84n_0 f21 0 io_l84p_0 f22 0 io_l91n_0/vref_0 b21 0 io_l91p_0 b22 0 io_l92n_0 l20 0 io_l92p_0 m20 0 io_l93n_0 e21 0 io_l93p_0 d22 0 io_l94n_0/vref_0 a21 0 io_l94p_0 a22 0 io_l95n_0/gclk7p h20 0 io_l95p_0/gclk6s j20 0 io_l96n_0/gclk5p c21 0 io_l96p_0/gclk4s d21 1 io_l96n_1/gclk3p f19 1 io_l96p_1/gclk2s f20 1 io_l95n_1/gclk1p h19 1 io_l95p_1/gclk0s h18 1 io_l94n_1 c19 1 io_l94p_1/vref_1 c20 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 158 1 io_l93n_1 e19 1 io_l93p_1 e20 1 io_l92n_1 j19 1 io_l92p_1 j18 1 io_l91n_1 a18 1 io_l91p_1/vref_1 a19 1 io_l84n_1 d18 1 io_l84p_1 d19 1 io_l83n_1 k19 1 io_l83p_1 k18 1 io_l82n_1 b18 1 io_l82p_1 b19 1 io_l81n_1/vref_1 g18 1 io_l81p_1 g19 1 io_l80n_1 e18 1 io_l80p_1 e17 1 io_l79n_1 a16 1 io_l79p_1 a17 1 io_l78n_1 f17 1 io_l78p_1 f18 1 io_l77n_1 l19 1 io_l77p_1 l18 1 io_l76n_1 b16 1 io_l76p_1 b17 1 io_l75n_1/vref_1 g16 1 io_l75p_1 g17 1 io_l74n_1 m19 1 io_l74p_1 m18 1 io_l73n_1 c16 1 io_l73p_1 c17 1 io_l72n_1 d15 1 io_l72p_1 d16 1 io_l71n_1 j17 1 io_l71p_1 j16 1 io_l70n_1 a14 1 io_l70p_1 a15 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 159 1 io_l69n_1/vref_1 e15 1 io_l69p_1 e16 1 io_l68n_1 k17 1 io_l68p_1 k16 1 io_l67n_1 c15 1 io_l67p_1 b15 1 io_l60n_1 f15 1 io_l60p_1 f16 1 io_l59n_1 h16 1 io_l59p_1 h15 1 io_l58n_1 c13 1 io_l58p_1 c14 1 io_l57n_1/vref_1 d13 1 io_l57p_1 d14 1 io_l56n_1 m17 1 io_l56p_1 m16 1 io_l55n_1 a12 1 io_l55p_1 a13 1 io_l54n_1 b12 1 io_l54p_1 b13 1 io_l53n_1 g15 1 io_l53p_1 g14 1 io_l52n_1 c11 1 io_l52p_1 c12 1 io_l51n_1/vref_1 f13 1 io_l51p_1 f14 1 io_l50n_1 l16 1 io_l50p_1 l15 1 io_l49n_1 a10 1 io_l49p_1 a11 1 io_l36n_1 e12 nc 1 io_l36p_1 e13 nc 1 io_l35n_1 k15 nc 1 io_l35p_1 j14 nc 1 io_l34n_1 b9 nc 1 io_l34p_1 b10 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 160 1 io_l33n_1/vref_1 d11 nc 1 io_l33p_1 d12 nc 1 io_l32n_1 h14 nc 1 io_l32p_1 h13 nc 1 io_l31n_1 a8 nc 1 io_l31p_1 a9 nc 1 io_l30n_1 f11 1 io_l30p_1 f12 1 io_l29n_1 k14 1 io_l29p_1 l14 1 io_l28n_1 c9 1 io_l28p_1 c10 1 io_l27n_1/vref_1 g11 1 io_l27p_1 g12 1 io_l26n_1 m15 1 io_l26p_1 m14 1 io_l25n_1 b7 1 io_l25p_1 b8 1 io_l24n_1 d9 1 io_l24p_1 d10 1 io_l23n_1 j13 1 io_l23p_1 j12 1 io_l22n_1 a6 1 io_l22p_1 a7 1 io_l21n_1/vref_1 e9 1 io_l21p_1 e10 1 io_l20n_1 d8 1 io_l20p_1 e7 1 io_l19n_1 c7 1 io_l19p_1 c8 1 io_l12n_1 f9 nc 1 io_l12p_1 f10 nc 1 io_l11n_1 h12 nc 1 io_l11p_1 h11 nc 1 io_l10n_1 b5 nc 1 io_l10p_1 b6 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 161 1 io_l09n_1/vref_1 g9 nc 1 io_l09p_1 g10 nc 1 io_l08n_1 k13 nc 1 io_l08p_1 k12 nc 1 io_l07n_1 a4 nc 1 io_l07p_1 a5 nc 1 io_l06n_1 f8 1 io_l06p_1 e8 1 io_l05n_1 j11 1 io_l05p_1 k11 1 io_l04n_1 c5 1 io_l04p_1/vref_1 c6 1 io_l03n_1/vrp_1 d6 1 io_l03p_1/vrn_1 d7 1 io_l02n_1 h10 1 io_l02p_1 j10 1 io_l01n_1 c4 1 io_l01p_1 b4 2 io_l01n_2 e3 2 io_l01p_2 d2 2 io_l02n_2/vrp_2 l13 2 io_l02p_2/vrn_2 m13 2 io_l03n_2 f4 2 io_l03p_2/vref_2 e4 2 io_l04n_2 e1 2 io_l04p_2 d1 2 io_l05n_2 l12 2 io_l05p_2 m11 2 io_l06n_2 g6 2 io_l06p_2 f5 2 io_l07n_2 f2 nc 2 io_l07p_2 e2 nc 2 io_l08n_2 m12 nc 2 io_l08p_2 n12 nc 2 io_l09n_2 h6 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 162 2 io_l09p_2/vref_2 h7 nc 2 io_l10n_2 g3 nc 2 io_l10p_2 f3 nc 2 io_l11n_2 j8 nc 2 io_l11p_2 k8 nc 2 io_l12n_2 h5 nc 2 io_l12p_2 g5 nc 2 io_l19n_2 g1 2 io_l19p_2 f1 2 io_l20n_2 k9 2 io_l20p_2 l10 2 io_l21n_2 k7 2 io_l21p_2/vref_2 j7 2 io_l22n_2 h2 2 io_l22p_2 g2 2 io_l23n_2 l9 2 io_l23p_2 m9 2 io_l24n_2 h4 2 io_l24p_2 g4 2 io_l25n_2 j3 2 io_l25p_2 h3 2 io_l26n_2 m10 2 io_l26p_2 n10 2 io_l27n_2 k6 2 io_l27p_2/vref_2 j6 2 io_l28n_2 k5 2 io_l28p_2 j5 2 io_l29n_2 n11 2 io_l29p_2 p11 2 io_l30n_2 m7 2 io_l30p_2 l7 2 io_l31n_2 j1 nc 2 io_l31p_2 h1 nc 2 io_l32n_2 l8 nc 2 io_l32p_2 m8 nc 2 io_l33n_2 k4 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 163 2 io_l33p_2/vref_2 j4 nc 2 io_l34n_2 k2 nc 2 io_l34p_2 j2 nc 2 io_l35n_2 p12 nc 2 io_l35p_2 r12 nc 2 io_l36n_2 m6 nc 2 io_l36p_2 l6 nc 2 io_l43n_2 l3 2 io_l43p_2 k3 2 io_l44n_2 n9 2 io_l44p_2 p9 2 io_l45n_2 m4 2 io_l45p_2/vref_2 l4 2 io_l46n_2 l1 2 io_l46p_2 k1 2 io_l47n_2 p10 2 io_l47p_2 r10 2 io_l48n_2 n5 2 io_l48p_2 m5 2 io_l49n_2 n3 2 io_l49p_2 m3 2 io_l50n_2 n8 2 io_l50p_2 p8 2 io_l51n_2 t11 2 io_l51p_2/vref_2 r11 2 io_l52n_2 n2 2 io_l52p_2 m2 2 io_l53n_2 t12 2 io_l53p_2 u12 2 io_l54n_2 p6 2 io_l54p_2 n6 2 io_l55n_2 n1 2 io_l55p_2 m1 2 io_l56n_2 r8 2 io_l56p_2 t8 2 io_l57n_2 r7 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 164 2 io_l57p_2/vref_2 p7 2 io_l58n_2 r3 2 io_l58p_2 p3 2 io_l59n_2 t10 2 io_l59p_2 u10 2 io_l60n_2 p4 2 io_l60p_2 n4 2 io_l67n_2 t6 2 io_l67p_2 r6 2 io_l68n_2 t9 2 io_l68p_2 u9 2 io_l69n_2 t5 2 io_l69p_2/vref_2 r5 2 io_l70n_2 r1 2 io_l70p_2 p1 2 io_l71n_2 v12 2 io_l71p_2 w12 2 io_l72n_2 t4 2 io_l72p_2 r4 2 io_l73n_2 t2 2 io_l73p_2 r2 2 io_l74n_2 v11 2 io_l74p_2 w11 2 io_l75n_2 u7 2 io_l75p_2/vref_2 t7 2 io_l76n_2 u3 2 io_l76p_2 t3 2 io_l77n_2 v10 2 io_l77p_2 w10 2 io_l78n_2 v6 2 io_l78p_2 u6 2 io_l79n_2 u1 2 io_l79p_2 t1 2 io_l80n_2 v9 2 io_l80p_2 w9 2 io_l81n_2 v5 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 165 2 io_l81p_2/vref_2 u5 2 io_l82n_2 v2 2 io_l82p_2 u2 2 io_l83n_2 v8 2 io_l83p_2 w8 2 io_l84n_2 w7 2 io_l84p_2 v7 2 io_l91n_2 w1 2 io_l91p_2 v1 2 io_l92n_2 y11 2 io_l92p_2 y12 2 io_l93n_2 w4 2 io_l93p_2/vref_2 v4 2 io_l94n_2 w2 2 io_l94p_2 w3 2 io_l95n_2 y8 2 io_l95p_2 y9 2 io_l96n_2 w5 2 io_l96p_2 w6 3 io_l96n_3 ab8 3 io_l96p_3 aa8 3 io_l95n_3 y3 3 io_l95p_3 aa3 3 io_l94n_3 y6 3 io_l94p_3 aa6 3 io_l93n_3/vref_3 ab9 3 io_l93p_3 aa9 3 io_l92n_3 aa1 3 io_l92p_3 ab1 3 io_l91n_3 y5 3 io_l91p_3 aa5 3 io_l84n_3 ab10 3 io_l84p_3 aa10 3 io_l83n_3 aa2 3 io_l83p_3 ab2 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 166 3 io_l82n_3 aa4 3 io_l82p_3 ab4 3 io_l81n_3/vref_3 ab11 3 io_l81p_3 aa11 3 io_l80n_3 ac1 3 io_l80p_3 ad1 3 io_l79n_3 aa7 3 io_l79p_3 ab7 3 io_l78n_3 ab12 3 io_l78p_3 aa12 3 io_l77n_3 ac2 3 io_l77p_3 ac3 3 io_l76n_3 ab5 3 io_l76p_3 ac5 3 io_l75n_3/vref_3 ad9 3 io_l75p_3 ac9 3 io_l74n_3 ad2 3 io_l74p_3 ae2 3 io_l73n_3 ab6 3 io_l73p_3 ac6 3 io_l72n_3 ad10 3 io_l72p_3 ac10 3 io_l71n_3 ad3 3 io_l71p_3 ae3 3 io_l70n_3 ac7 3 io_l70p_3 ad7 3 io_l69n_3/vref_3 ae8 3 io_l69p_3 ad8 3 io_l68n_3 ae1 3 io_l68p_3 af1 3 io_l67n_3 ad4 3 io_l67p_3 ae4 3 io_l60n_3 ad12 3 io_l60p_3 ac12 3 io_l59n_3 af3 3 io_l59p_3 ag3 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 167 3 io_l58n_3 ad5 3 io_l58p_3 ae5 3 io_l57n_3/vref_3 ae11 3 io_l57p_3 ad11 3 io_l56n_3 ag1 3 io_l56p_3 ah1 3 io_l55n_3 ad6 3 io_l55p_3 ae6 3 io_l54n_3 af10 3 io_l54p_3 ae10 3 io_l53n_3 ag2 3 io_l53p_3 ah2 3 io_l52n_3 af4 3 io_l52p_3 ag4 3 io_l51n_3/vref_3 ag8 3 io_l51p_3 af8 3 io_l50n_3 ah3 3 io_l50p_3 aj3 3 io_l49n_3 ae7 3 io_l49p_3 af7 3 io_l48n_3 ag9 3 io_l48p_3 af9 3 io_l47n_3 af6 3 io_l47p_3 ag6 3 io_l46n_3 ag5 3 io_l46p_3 ah5 3 io_l45n_3/vref_3 af12 3 io_l45p_3 ae12 3 io_l44n_3 aj1 3 io_l44p_3 ak1 3 io_l43n_3 ah4 3 io_l43p_3 aj4 3 io_l36n_3 ag11 nc 3 io_l36p_3 af11 nc 3 io_l35n_3 ak2 nc 3 io_l35p_3 al2 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 168 3 io_l34n_3 ah6 nc 3 io_l34p_3 aj6 nc 3 io_l33n_3/vref_3 aj8 nc 3 io_l33p_3 ah8 nc 3 io_l32n_3 al1 nc 3 io_l32p_3 am1 nc 3 io_l31n_3 ah7 nc 3 io_l31p_3 aj7 nc 3 io_l30n_3 ah10 3 io_l30p_3 ag10 3 io_l29n_3 ak3 3 io_l29p_3 al3 3 io_l28n_3 ak4 3 io_l28p_3 al4 3 io_l27n_3/vref_3 aj9 3 io_l27p_3 ah9 3 io_l26n_3 am2 3 io_l26p_3 an2 3 io_l25n_3 ak5 3 io_l25p_3 al5 3 io_l24n_3 ak9 3 io_l24p_3 ak8 3 io_l23n_3 an1 3 io_l23p_3 ap1 3 io_l22n_3 ak6 3 io_l22p_3 al6 3 io_l21n_3/vref_3 ah12 3 io_l21p_3 ag12 3 io_l20n_3 am3 3 io_l20p_3 an3 3 io_l19n_3 am4 3 io_l19p_3 an4 3 io_l12n_3 aj12 nc 3 io_l12p_3 ah11 nc 3 io_l11n_3 ap2 nc 3 io_l11p_3 ar2 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 169 3 io_l10n_3 ak7 nc 3 io_l10p_3 al7 nc 3 io_l09n_3/vref_3 ak11 nc 3 io_l09p_3 aj10 nc 3 io_l08n_3 ar1 nc 3 io_l08p_3 at1 nc 3 io_l07n_3 am5 nc 3 io_l07p_3 an5 nc 3 io_l06n_3 am7 3 io_l06p_3 al8 3 io_l05n_3 ap3 3 io_l05p_3 ap4 3 io_l04n_3 am6 3 io_l04p_3 an6 3 io_l03n_3/vref_3 aj13 3 io_l03p_3 ah13 3 io_l02n_3/vrp_3 ar3 3 io_l02p_3/vrn_3 at2 3 io_l01n_3 ap5 3 io_l01p_3 ar4 4 io_l01n_4/busy/dout (1) av4 4 io_l01p_4/init_b au4 4 io_l02n_4/d0/din (1) am9 4 io_l02p_4/d1 am10 4 io_l03n_4/d2/alt_vrp_4 at6 4 io_l03p_4/d3/alt_vrn_4 ar6 4 io_l04n_4/vref_4 au6 4 io_l04p_4 au5 4 io_l05n_4/vrp_4 al10 4 io_l05p_4/vrn_4 al11 4 io_l06n_4 ar8 4 io_l06p_4 ar7 4 io_l07n_4 aw5 nc 4 io_l07p_4 aw4 nc 4 io_l08n_4 ak12 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 170 4 io_l08p_4 al12 nc 4 io_l09n_4 ap9 nc 4 io_l09p_4/vref_4 ap8 nc 4 io_l10n_4 av6 nc 4 io_l10p_4 av5 nc 4 io_l11n_4 am11 nc 4 io_l11p_4 am12 nc 4 io_l12n_4 an10 nc 4 io_l12p_4 an9 nc 4 io_l19n_4 au8 4 io_l19p_4 au7 4 io_l20n_4 ah14 4 io_l20p_4 ah15 4 io_l21n_4 at8 4 io_l21p_4/vref_4 at7 4 io_l22n_4 aw7 4 io_l22p_4 aw6 4 io_l23n_4 ak13 4 io_l23p_4 ak14 4 io_l24n_4 ar10 4 io_l24p_4 ar9 4 io_l25n_4 av8 4 io_l25p_4 av7 4 io_l26n_4 aj14 4 io_l26p_4 aj15 4 io_l27n_4 ap11 4 io_l27p_4/vref_4 ap10 4 io_l28n_4 au10 4 io_l28p_4 au9 4 io_l29n_4 al13 4 io_l29p_4 al14 4 io_l30n_4 an12 4 io_l30p_4 an11 4 io_l31n_4 aw9 nc 4 io_l31p_4 aw8 nc 4 io_l32n_4 am13 nc ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 171 4 io_l32p_4 am14 nc 4 io_l33n_4 at10 nc 4 io_l33p_4/vref_4 at9 nc 4 io_l34n_4 av10 nc 4 io_l34p_4 av9 nc 4 io_l35n_4 ah16 nc 4 io_l35p_4 ah17 nc 4 io_l36n_4 ap13 nc 4 io_l36p_4 ap12 nc 4 io_l49n_4 au12 4 io_l49p_4 au11 4 io_l50n_4 ak15 4 io_l50p_4 aj16 4 io_l51n_4 at12 4 io_l51p_4/vref_4 at11 4 io_l52n_4 an15 4 io_l52p_4 an14 4 io_l53n_4 ar12 4 io_l53p_4 ar13 4 io_l54n_4 at14 4 io_l54p_4 at13 4 io_l55n_4 aw11 4 io_l55p_4 aw10 4 io_l56n_4 am15 4 io_l56p_4 am16 4 io_l57n_4 ap15 4 io_l57p_4/vref_4 ap14 4 io_l58n_4 av13 4 io_l58p_4 av12 4 io_l59n_4 ak16 4 io_l59p_4 ak17 4 io_l60n_4 ar16 4 io_l60p_4 ar15 4 io_l67n_4 aw13 4 io_l67p_4 aw12 4 io_l68n_4 al16 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 172 4 io_l68p_4 al17 4 io_l69n_4 at16 4 io_l69p_4/vref_4 at15 4 io_l70n_4 au14 4 io_l70p_4 au13 4 io_l71n_4 ah18 4 io_l71p_4 ah19 4 io_l72n_4 an17 4 io_l72p_4 an16 4 io_l73n_4 aw15 4 io_l73p_4 aw14 4 io_l74n_4 aj18 4 io_l74p_4 aj19 4 io_l75n_4 ap17 4 io_l75p_4/vref_4 ap16 4 io_l76n_4 av15 4 io_l76p_4 au15 4 io_l77n_4 ak18 4 io_l77p_4 ak19 4 io_l78n_4 ar18 4 io_l78p_4 ar17 4 io_l79n_4 au17 4 io_l79p_4 au16 4 io_l80n_4 al18 4 io_l80p_4 al19 4 io_l81n_4 an19 4 io_l81p_4/vref_4 an18 4 io_l82n_4 av17 4 io_l82p_4 av16 4 io_l83n_4 am18 4 io_l83p_4 am19 4 io_l84n_4 ap19 4 io_l84p_4 ap18 4 io_l85n_4 aw17 nc nc 4 io_l85p_4 aw16 nc nc 4 io_l91n_4/vref_4 av19 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 173 4 io_l91p_4 av18 4 io_l92n_4 ah20 4 io_l92p_4 aj20 4 io_l93n_4 ar19 4 io_l93p_4 at18 4 io_l94n_4/vref_4 aw19 4 io_l94p_4 aw18 4 io_l95n_4/gclk3s al20 4 io_l95p_4/gclk2p am20 4 io_l96n_4/gclk1s au19 4 io_l96p_4/gclk0p at19 5 io_l96n_5/gclk7s ap21 5 io_l96p_5/gclk6p ap20 5 io_l95n_5/gclk5s an21 5 io_l95p_5/gclk4p an22 5 io_l94n_5 au21 5 io_l94p_5/vref_5 au20 5 io_l93n_5 ar21 5 io_l93p_5 ar20 5 io_l92n_5 am21 5 io_l92p_5 am22 5 io_l91n_5 aw22 5 io_l91p_5/vref_5 aw21 5 io_l85n_5 av22 nc nc 5 io_l85p_5 av21 nc nc 5 io_l84n_5 at22 5 io_l84p_5 at21 5 io_l83n_5 al21 5 io_l83p_5 al22 5 io_l82n_5 aw24 5 io_l82p_5 aw23 5 io_l81n_5/vref_5 ar23 5 io_l81p_5 ar22 5 io_l80n_5 ak21 5 io_l80p_5 ak22 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 174 5 io_l79n_5 av24 5 io_l79p_5 av23 5 io_l78n_5 ap23 5 io_l78p_5 ap22 5 io_l77n_5 aj21 5 io_l77p_5 aj22 5 io_l76n_5 au24 5 io_l76p_5 au23 5 io_l75n_5/vref_5 at25 5 io_l75p_5 at24 5 io_l74n_5 ah21 5 io_l74p_5 ah22 5 io_l73n_5 aw26 5 io_l73p_5 aw25 5 io_l72n_5 ar25 5 io_l72p_5 ar24 5 io_l71n_5 an23 5 io_l71p_5 an24 5 io_l70n_5 au25 5 io_l70p_5 av25 5 io_l69n_5/vref_5 al24 5 io_l69p_5 al23 5 io_l68n_5 ak23 5 io_l68p_5 ak24 5 io_l67n_5 au27 5 io_l67p_5 au26 5 io_l60n_5 ap25 5 io_l60p_5 ap24 5 io_l59n_5 am24 5 io_l59p_5 am25 5 io_l58n_5 aw28 5 io_l58p_5 aw27 5 io_l57n_5/vref_5 at27 5 io_l57p_5 at26 5 io_l56n_5 ah23 5 io_l56p_5 ah24 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 175 5 io_l55n_5 av28 5 io_l55p_5 av27 5 io_l54n_5 ap27 5 io_l54p_5 ap26 5 io_l53n_5 an25 5 io_l53p_5 an26 5 io_l52n_5 au29 5 io_l52p_5 au28 5 io_l51n_5/vref_5 ar28 5 io_l51p_5 ar27 5 io_l50n_5 aj24 5 io_l50p_5 aj25 5 io_l49n_5 aw30 5 io_l49p_5 aw29 5 io_l36n_5 at29 nc 5 io_l36p_5 at28 nc 5 io_l35n_5 ak25 nc 5 io_l35p_5 al26 nc 5 io_l34n_5 av31 nc 5 io_l34p_5 av30 nc 5 io_l33n_5/vref_5 ap29 nc 5 io_l33p_5 ap28 nc 5 io_l32n_5 ak26 nc 5 io_l32p_5 aj26 nc 5 io_l31n_5 aw32 nc 5 io_l31p_5 aw31 nc 5 io_l30n_5 am27 5 io_l30p_5 am26 5 io_l29n_5 an28 5 io_l29p_5 an29 5 io_l28n_5 au31 5 io_l28p_5 au30 5 io_l27n_5/vref_5 at31 5 io_l27p_5 at30 5 io_l26n_5 ah25 5 io_l26p_5 ah26 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 176 5 io_l25n_5 av33 5 io_l25p_5 av32 5 io_l24n_5 ar31 5 io_l24p_5 ar30 5 io_l23n_5 al27 5 io_l23p_5 al28 5 io_l22n_5 aw34 5 io_l22p_5 aw33 5 io_l21n_5/vref_5 an30 5 io_l21p_5 ap30 5 io_l20n_5 am28 5 io_l20p_5 am29 5 io_l19n_5 au33 5 io_l19p_5 au32 5 io_l12n_5 at33 nc 5 io_l12p_5 at32 nc 5 io_l11n_5 ak27 nc 5 io_l11p_5 ak28 nc 5 io_l10n_5 av35 nc 5 io_l10p_5 av34 nc 5 io_l09n_5/vref_5 ap32 nc 5 io_l09p_5 ap31 nc 5 io_l08n_5 al29 nc 5 io_l08p_5 ak29 nc 5 io_l07n_5 aw36 nc 5 io_l07p_5 aw35 nc 5 io_l06n_5 ar33 5 io_l06p_5 ar32 5 io_l05n_5/vrp_5 am30 5 io_l05p_5/vrn_5 al30 5 io_l04n_5 au35 5 io_l04p_5/vref_5 au34 5 io_l03n_5/d4/alt_vrp_5 ar34 5 io_l03p_5/d5/alt_vrn_5 at34 5 io_l02n_5/d6 an31 5 io_l02p_5/d7 am31 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 177 5 io_l01n_5/rdwr_b au36 5 io_l01p_5/cs_b av36 6 io_l01p_6 aj27 6 io_l01n_6 ah27 6 io_l02p_6/vrn_6 at38 6 io_l02n_6/vrp_6 ar37 6 io_l03p_6 ap36 6 io_l03n_6/vref_6 ar36 6 io_l04p_6 aj28 6 io_l04n_6 ah29 6 io_l05p_6 at39 6 io_l05n_6 ar39 6 io_l06p_6 an34 6 io_l06n_6 ap35 6 io_l07p_6 ah28 nc 6 io_l07n_6 ag28 nc 6 io_l08p_6 ar38 nc 6 io_l08n_6 ap38 nc 6 io_l09p_6 am34 nc 6 io_l09n_6/vref_6 am33 nc 6 io_l10p_6 al32 nc 6 io_l10n_6 ak32 nc 6 io_l11p_6 ap37 nc 6 io_l11n_6 an37 nc 6 io_l12p_6 am35 nc 6 io_l12n_6 an35 nc 6 io_l19p_6 ak31 6 io_l19n_6 aj30 6 io_l20p_6 ap39 6 io_l20n_6 an39 6 io_l21p_6 ak33 6 io_l21n_6/vref_6 al33 6 io_l22p_6 aj31 6 io_l22n_6 ah31 6 io_l23p_6 an38 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 178 6 io_l23n_6 am38 6 io_l24p_6 am36 6 io_l24n_6 an36 6 io_l25p_6 ah30 6 io_l25n_6 ag30 6 io_l26p_6 am37 6 io_l26n_6 al37 6 io_l27p_6 ak34 6 io_l27n_6/vref_6 al34 6 io_l28p_6 ag29 6 io_l28n_6 af29 6 io_l29p_6 al35 6 io_l29n_6 ak35 6 io_l30p_6 ah33 6 io_l30n_6 aj33 6 io_l31p_6 aj32 nc 6 io_l31n_6 ah32 nc 6 io_l32p_6 am39 nc 6 io_l32n_6 al39 nc 6 io_l33p_6 ak36 nc 6 io_l33n_6/vref_6 al36 nc 6 io_l34p_6 af28 nc 6 io_l34n_6 ae28 nc 6 io_l35p_6 al38 nc 6 io_l35n_6 ak38 nc 6 io_l36p_6 ah34 nc 6 io_l36n_6 aj34 nc 6 io_l43p_6 ag31 6 io_l43n_6 af31 6 io_l44p_6 ak37 6 io_l44n_6 aj37 6 io_l45p_6 ah36 6 io_l45n_6/vref_6 aj36 6 io_l46p_6 af30 6 io_l46n_6 ae30 6 io_l47p_6 ak39 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 179 6 io_l47n_6 aj39 6 io_l48p_6 ag35 6 io_l48n_6 ah35 6 io_l49p_6 ag32 6 io_l49n_6 af32 6 io_l50p_6 ah37 6 io_l50n_6 ag37 6 io_l51p_6 ad29 6 io_l51n_6/vref_6 ae29 6 io_l52p_6 ad28 6 io_l52n_6 ac28 6 io_l53p_6 ah38 6 io_l53n_6 ag38 6 io_l54p_6 af34 6 io_l54n_6 ag34 6 io_l55p_6 ae32 6 io_l55n_6 ad32 6 io_l56p_6 ah39 6 io_l56n_6 ag39 6 io_l57p_6 ae33 6 io_l57n_6/vref_6 af33 6 io_l58p_6 ad30 6 io_l58n_6 ac30 6 io_l59p_6 af37 6 io_l59n_6 ae37 6 io_l60p_6 af36 6 io_l60n_6 ag36 6 io_l67p_6 ad31 6 io_l67n_6 ac31 6 io_l68p_6 ae34 6 io_l68n_6 ad34 6 io_l69p_6 ad35 6 io_l69n_6/vref_6 ae35 6 io_l70p_6 ab28 6 io_l70n_6 aa28 6 io_l71p_6 af39 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 180 6 io_l71n_6 ae39 6 io_l72p_6 ad36 6 io_l72n_6 ae36 6 io_l73p_6 ab29 6 io_l73n_6 aa29 6 io_l74p_6 ae38 6 io_l74n_6 ad38 6 io_l75p_6 ac33 6 io_l75n_6/vref_6 ad33 6 io_l76p_6 ab30 6 io_l76n_6 aa30 6 io_l77p_6 ad37 6 io_l77n_6 ac37 6 io_l78p_6 ab34 6 io_l78n_6 ac34 6 io_l79p_6 ab31 6 io_l79n_6 aa31 6 io_l80p_6 ad39 6 io_l80n_6 ac39 6 io_l81p_6 ab35 6 io_l81n_6/vref_6 ac35 6 io_l82p_6 ab32 6 io_l82n_6 aa32 6 io_l83p_6 ac38 6 io_l83n_6 ab38 6 io_l84p_6 aa33 6 io_l84n_6 ab33 6 io_l91p_6 y28 6 io_l91n_6 y29 6 io_l92p_6 ab39 6 io_l92n_6 aa39 6 io_l93p_6 aa36 6 io_l93n_6/vref_6 ab36 6 io_l94p_6 y31 6 io_l94n_6 y32 6 io_l95p_6 aa37 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 181 6 io_l95n_6 aa38 6 io_l96p_6 aa35 6 io_l96n_6 aa34 7 io_l96p_7 w34 7 io_l96n_7 y34 7 io_l95p_7 w32 7 io_l95n_7 v32 7 io_l94p_7 w37 7 io_l94n_7 y37 7 io_l93p_7/vref_7 w35 7 io_l93n_7 y35 7 io_l92p_7 w31 7 io_l92n_7 v31 7 io_l91p_7 v39 7 io_l91n_7 w39 7 io_l84p_7 v36 7 io_l84n_7 w36 7 io_l83p_7 w30 7 io_l83n_7 v30 7 io_l82p_7 v38 7 io_l82n_7 w38 7 io_l81p_7/vref_7 v33 7 io_l81n_7 w33 7 io_l80p_7 w29 7 io_l80n_7 v29 7 io_l79p_7 t39 7 io_l79n_7 u39 7 io_l78p_7 u35 7 io_l78n_7 v35 7 io_l77p_7 w28 7 io_l77n_7 v28 7 io_l76p_7 u37 7 io_l76n_7 u38 7 io_l75p_7/vref_7 u34 7 io_l75n_7 v34 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 182 7 io_l74p_7 u31 7 io_l74n_7 t31 7 io_l73p_7 r38 7 io_l73n_7 t38 7 io_l72p_7 t33 7 io_l72n_7 u33 7 io_l71p_7 u30 7 io_l71n_7 t30 7 io_l70p_7 r37 7 io_l70n_7 t37 7 io_l69p_7/vref_7 r36 7 io_l69n_7 t36 7 io_l68p_7 t32 7 io_l68n_7 r32 7 io_l67p_7 p39 7 io_l67n_7 r39 7 io_l60p_7 r35 7 io_l60n_7 t35 7 io_l59p_7 u28 7 io_l59n_7 t28 7 io_l58p_7 n37 7 io_l58n_7 p37 7 io_l57p_7/vref_7 r34 7 io_l57n_7 t34 7 io_l56p_7 t29 7 io_l56n_7 r29 7 io_l55p_7 m39 7 io_l55n_7 n39 7 io_l54p_7 n36 7 io_l54n_7 p36 7 io_l53p_7 r30 7 io_l53n_7 p30 7 io_l52p_7 m38 7 io_l52n_7 n38 7 io_l51p_7/vref_7 p33 7 io_l51n_7 r33 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 183 7 io_l50p_7 p32 7 io_l50n_7 n32 7 io_l49p_7 l37 7 io_l49n_7 m37 7 io_l48p_7 n34 7 io_l48n_7 p34 7 io_l47p_7 p31 7 io_l47n_7 n31 7 io_l46p_7 m35 7 io_l46n_7 n35 7 io_l45p_7/vref_7 l36 7 io_l45n_7 m36 7 io_l44p_7 r28 7 io_l44n_7 p28 7 io_l43p_7 k39 7 io_l43n_7 l39 7 io_l36p_7 l34 nc 7 io_l36n_7 m34 nc 7 io_l35p_7 p29 nc 7 io_l35n_7 n29 nc 7 io_l34p_7 j38 nc 7 io_l34n_7 k38 nc 7 io_l33p_7/vref_7 l33 nc 7 io_l33n_7 m33 nc 7 io_l32p_7 m32 nc 7 io_l32n_7 l32 nc 7 io_l31p_7 h39 nc 7 io_l31n_7 j39 nc 7 io_l30p_7 j36 7 io_l30n_7 k36 7 io_l29p_7 n30 7 io_l29n_7 m30 7 io_l28p_7 j37 7 io_l28n_7 k37 7 io_l27p_7/vref_7 j35 7 io_l27n_7 k35 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 184 7 io_l26p_7 m31 7 io_l26n_7 l31 7 io_l25p_7 g38 7 io_l25n_7 h38 7 io_l24p_7 j34 7 io_l24n_7 k34 7 io_l23p_7 k32 7 io_l23n_7 k31 7 io_l22p_7 f39 7 io_l22n_7 g39 7 io_l21p_7/vref_7 g36 7 io_l21n_7 h36 7 io_l20p_7 n28 7 io_l20n_7 m28 7 io_l19p_7 g37 7 io_l19n_7 h37 7 io_l12p_7 j33 nc 7 io_l12n_7 k33 nc 7 io_l11p_7 m29 nc 7 io_l11n_7 l28 nc 7 io_l10p_7 e38 nc 7 io_l10n_7 f38 nc 7 io_l09p_7/vref_7 g35 nc 7 io_l09n_7 h35 nc 7 io_l08p_7 l30 nc 7 io_l08n_7 k29 nc 7 io_l07p_7 d39 nc 7 io_l07n_7 e39 nc 7 io_l06p_7 g34 7 io_l06n_7 h34 7 io_l05p_7 j32 7 io_l05n_7 h33 7 io_l04p_7 f36 7 io_l04n_7 f37 7 io_l03p_7/vref_7 e36 7 io_l03n_7 f35 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 185 7 io_l02p_7/vrn_7 m27 7 io_l02n_7/vrp_7 l27 7 io_l01p_7 d38 7 io_l01n_7 e37 0 vcco_0 p25 0 vcco_0 p24 0 vcco_0 p23 0 vcco_0 p22 0 vcco_0 p21 0 vcco_0 n26 0 vcco_0 n25 0 vcco_0 n24 0 vcco_0 n23 0 vcco_0 n22 0 vcco_0 n21 0 vcco_0 l23 0 vcco_0 j25 0 vcco_0 g27 0 vcco_0 e29 0 vcco_0 c22 0 vcco_0 b26 1 vcco_1 p19 1 vcco_1 p18 1 vcco_1 p17 1 vcco_1 p16 1 vcco_1 p15 1 vcco_1 n19 1 vcco_1 n18 1 vcco_1 n17 1 vcco_1 n16 1 vcco_1 n15 1 vcco_1 n14 1 vcco_1 l17 1 vcco_1 j15 1 vcco_1 g13 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 186 1 vcco_1 e11 1 vcco_1 c18 1 vcco_1 b14 2 vcco_2 w14 2 vcco_2 w13 2 vcco_2 v14 2 vcco_2 v13 2 vcco_2 v3 2 vcco_2 u14 2 vcco_2 u13 2 vcco_2 u11 2 vcco_2 t14 2 vcco_2 t13 2 vcco_2 r14 2 vcco_2 r13 2 vcco_2 r9 2 vcco_2 p13 2 vcco_2 p2 2 vcco_2 n7 2 vcco_2 l5 3 vcco_3 aj5 3 vcco_3 ag7 3 vcco_3 af13 3 vcco_3 af2 3 vcco_3 ae14 3 vcco_3 ae13 3 vcco_3 ae9 3 vcco_3 ad14 3 vcco_3 ad13 3 vcco_3 ac14 3 vcco_3 ac13 3 vcco_3 ac11 3 vcco_3 ab14 3 vcco_3 ab13 3 vcco_3 ab3 3 vcco_3 aa14 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 187 3 vcco_3 aa13 4 vcco_4 av14 4 vcco_4 au18 4 vcco_4 ar11 4 vcco_4 an13 4 vcco_4 al15 4 vcco_4 aj17 4 vcco_4 ag19 4 vcco_4 ag18 4 vcco_4 ag17 4 vcco_4 ag16 4 vcco_4 ag15 4 vcco_4 ag14 4 vcco_4 af19 4 vcco_4 af18 4 vcco_4 af17 4 vcco_4 af16 4 vcco_4 af15 5 vcco_5 av26 5 vcco_5 au22 5 vcco_5 ar29 5 vcco_5 an27 5 vcco_5 al25 5 vcco_5 aj23 5 vcco_5 ag26 5 vcco_5 ag25 5 vcco_5 ag24 5 vcco_5 ag23 5 vcco_5 ag22 5 vcco_5 ag21 5 vcco_5 af25 5 vcco_5 af24 5 vcco_5 af23 5 vcco_5 af22 5 vcco_5 af21 6 vcco_6 aj35 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 188 6 vcco_6 ag33 6 vcco_6 af38 6 vcco_6 af27 6 vcco_6 ae31 6 vcco_6 ae27 6 vcco_6 ae26 6 vcco_6 ad27 6 vcco_6 ad26 6 vcco_6 ac29 6 vcco_6 ac27 6 vcco_6 ac26 6 vcco_6 ab37 6 vcco_6 ab27 6 vcco_6 ab26 6 vcco_6 aa27 6 vcco_6 aa26 7 vcco_7 w27 7 vcco_7 w26 7 vcco_7 v37 7 vcco_7 v27 7 vcco_7 v26 7 vcco_7 u29 7 vcco_7 u27 7 vcco_7 u26 7 vcco_7 t27 7 vcco_7 t26 7 vcco_7 r31 7 vcco_7 r27 7 vcco_7 r26 7 vcco_7 p38 7 vcco_7 p27 7 vcco_7 n33 7 vcco_7 l35 na cclk at5 na prog_b h31 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 189 na done ap7 na m0 an32 na m1 ap33 na m2 at35 na hswap_en e34 na tck g8 na tdi d35 na tdo e6 na tms f7 na pwrdwn_b an8 na dxn g32 na dxp f33 na vbatt d5 na rsvd h9 na vccaux av20 na vccaux at37 na vccaux at3 na vccaux y38 na vccaux y2 na vccaux d37 na vccaux d3 na vccaux b20 na vccint ag27 na vccint ag20 na vccint ag13 na vccint af26 na vccint af20 na vccint af14 na vccint ae25 na vccint ae24 na vccint ae23 na vccint ae22 na vccint ae21 na vccint ae20 na vccint ae19 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 190 na vccint ae18 na vccint ae17 na vccint ae16 na vccint ae15 na vccint ad25 na vccint ad24 na vccint ad16 na vccint ad15 na vccint ac25 na vccint ac15 na vccint ab25 na vccint ab15 na vccint aa25 na vccint aa15 na vccint y27 na vccint y26 na vccint y25 na vccint y15 na vccint y14 na vccint y13 na vccint w25 na vccint w15 na vccint v25 na vccint v15 na vccint u25 na vccint u15 na vccint t25 na vccint t24 na vccint t16 na vccint t15 na vccint r25 na vccint r24 na vccint r23 na vccint r22 na vccint r21 na vccint r20 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 191 na vccint r19 na vccint r18 na vccint r17 na vccint r16 na vccint r15 na vccint p26 na vccint p20 na vccint p14 na vccint n27 na vccint n20 na vccint n13 na gnd aw38 na gnd aw37 na gnd aw20 na gnd aw3 na gnd aw2 na gnd av39 na gnd av38 na gnd av37 na gnd av29 na gnd av11 na gnd av3 na gnd av2 na gnd av1 na gnd au39 na gnd au38 na gnd au37 na gnd au3 na gnd au2 na gnd au1 na gnd at36 na gnd at23 na gnd at20 na gnd at17 na gnd at4 na gnd ar35 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 192 na gnd ar26 na gnd ar14 na gnd ar5 na gnd ap34 na gnd ap6 na gnd an33 na gnd an20 na gnd an7 na gnd am32 na gnd am23 na gnd am17 na gnd am8 na gnd al31 na gnd al9 na gnd ak30 na gnd ak20 na gnd ak10 na gnd aj38 na gnd aj29 na gnd aj11 na gnd aj2 na gnd af35 na gnd af5 na gnd ad23 na gnd ad22 na gnd ad21 na gnd ad20 na gnd ad19 na gnd ad18 na gnd ad17 na gnd ac36 na gnd ac32 na gnd ac24 na gnd ac23 na gnd ac22 na gnd ac21 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 193 na gnd ac20 na gnd ac19 na gnd ac18 na gnd ac17 na gnd ac16 na gnd ac8 na gnd ac4 na gnd ab24 na gnd ab23 na gnd ab22 na gnd ab21 na gnd ab20 na gnd ab19 na gnd ab18 na gnd ab17 na gnd ab16 na gnd aa24 na gnd aa23 na gnd aa22 na gnd aa21 na gnd aa20 na gnd aa19 na gnd aa18 na gnd aa17 na gnd aa16 na gnd y39 na gnd y36 na gnd y33 na gnd y30 na gnd y24 na gnd y23 na gnd y22 na gnd y21 na gnd y20 na gnd y19 na gnd y18 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 194 na gnd y17 na gnd y16 na gnd y10 na gnd y7 na gnd y4 na gnd y1 na gnd w24 na gnd w23 na gnd w22 na gnd w21 na gnd w20 na gnd w19 na gnd w18 na gnd w17 na gnd w16 na gnd v24 na gnd v23 na gnd v22 na gnd v21 na gnd v20 na gnd v19 na gnd v18 na gnd v17 na gnd v16 na gnd u36 na gnd u32 na gnd u24 na gnd u23 na gnd u22 na gnd u21 na gnd u20 na gnd u19 na gnd u18 na gnd u17 na gnd u16 na gnd u8 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 195 na gnd u4 na gnd t23 na gnd t22 na gnd t21 na gnd t20 na gnd t19 na gnd t18 na gnd t17 na gnd p35 na gnd p5 na gnd l38 na gnd l29 na gnd l11 na gnd l2 na gnd k30 na gnd k20 na gnd k10 na gnd j31 na gnd j9 na gnd h32 na gnd h23 na gnd h17 na gnd h8 na gnd g33 na gnd g20 na gnd g7 na gnd f34 na gnd f6 na gnd e35 na gnd e26 na gnd e14 na gnd e5 na gnd d36 na gnd d23 na gnd d20 na gnd d17 ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 196 na gnd d4 na gnd c39 na gnd c38 na gnd c37 na gnd c3 na gnd c2 na gnd c1 na gnd b39 na gnd b38 na gnd b37 na gnd b29 na gnd b11 na gnd b3 na gnd b2 na gnd b1 na gnd a38 na gnd a37 na gnd a20 na gnd a3 na gnd a2 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 1 3 : ff1517 bga ? xc2v4000, xc2v6000, and xc2v8000 bank pin description pin number no connect in the xc2v4000 no connect in the xc2v6000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 197 ff1517 flip-chip fine-pitc h bga package specificat ions (1.00mm pitch) figure 9: ff1517 flip-chip fine-pitch bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 198 bf957 flip-chip bga package as shown in ta bl e 1 4 , XC2V2000, xc2v3000, xc2v4000, and xc2v6000 virtex-ii devices are available in the bf957 package. pins in each of these devices are the same, except for the pin differences in the XC2V2000 device shown in the no connect column. following this table are the bf957 flip-chip bga package specifications (1.27mm pitch) . ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000 0 io_l01n_0 h23 0 io_l01p_0 h22 0 io_l02n_0 g24 0 io_l02p_0 e25 0 io_l03n_0/vrp_0 b29 0 io_l03p_0/vrn_0 c27 0 io_l04n_0/vref_0 f24 0 io_l04p_0 f23 0 io_l05n_0 d26 0 io_l05p_0 d25 0 io_l06n_0 a28 0 io_l06p_0 a27 0 io_l19n_0 j22 0 io_l19p_0 j21 0 io_l20n_0 g23 0 io_l20p_0 g22 0 io_l21n_0 b27 0 io_l21p_0/vref_0 b26 0 io_l22n_0 k20 0 io_l22p_0 k19 0 io_l23n_0 c26 0 io_l23p_0 c24 0 io_l24n_0 d24 0 io_l24p_0 d23 0 io_l25n_0 e24 nc 0 io_l25p_0 e23 nc 0 io_l26n_0 g21 nc 0 io_l26p_0 g20 nc 0 io_l27n_0 a26 nc 0 io_l27p_0/vref_0 a25 nc 0 io_l29n_0 h21 nc 0 io_l29p_0 h20 nc 0 io_l30n_0 b25 nc 0 io_l30p_0 b23 nc
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 199 0 io_l49n_0 c23 0 io_l49p_0 c22 0 io_l50n_0 e22 0 io_l50p_0 e21 0 io_l51n_0 f21 0 io_l51p_0/vref_0 f20 0 io_l52n_0 a24 0 io_l52p_0 a23 0 io_l53n_0 e20 0 io_l53p_0 e19 0 io_l54n_0 b22 0 io_l54p_0 b21 0 io_l67n_0 d21 0 io_l67p_0 d20 0 io_l68n_0 j20 0 io_l68p_0 j19 0 io_l69n_0 f19 0 io_l69p_0/vref_0 f18 0 io_l70n_0 a22 0 io_l70p_0 a21 0 io_l71n_0 h19 0 io_l71p_0 h17 0 io_l72n_0 c21 0 io_l72p_0 c20 0 io_l73n_0 b20 0 io_l73p_0 b19 0 io_l74n_0 g18 0 io_l74p_0 g17 0 io_l75n_0 e18 0 io_l75p_0/vref_0 d17 0 io_l76n_0 a20 0 io_l76p_0 a19 0 io_l77n_0 d19 0 io_l77p_0 d18 0 io_l78n_0 c19 0 io_l78p_0 c17 0 io_l91n_0/vref_0 k18 0 io_l91p_0 j18 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 200 0 io_l92n_0 f17 0 io_l92p_0 f16 0 io_l93n_0 b18 0 io_l93p_0 b17 0 io_l94n_0/vref_0 j17 0 io_l94p_0 j16 0 io_l95n_0/gclk7p e17 0 io_l95p_0/gclk6s e16 0 io_l96n_0/gclk5p a18 0 io_l96p_0/gclk4s a17 1 io_l96n_1/gclk3p c16 1 io_l96p_1/gclk2s c15 1 io_l95n_1/gclk1p h16 1 io_l95p_1/gclk0s h15 1 io_l94n_1 a15 1 io_l94p_1/vref_1 a14 1 io_l93n_1 f15 1 io_l93p_1 f14 1 io_l92n_1 g15 1 io_l92p_1 g14 1 io_l91n_1 b15 1 io_l91p_1/vref_1 b14 1 io_l78n_1 d15 1 io_l78p_1 e15 1 io_l77n_1 j15 1 io_l77p_1 k14 1 io_l76n_1 d14 1 io_l76p_1 d13 1 io_l75n_1/vref_1 e14 1 io_l75p_1 e13 1 io_l74n_1 a13 1 io_l74p_1 a12 1 io_l73n_1 f13 1 io_l73p_1 f12 1 io_l72n_1 j14 1 io_l72p_1 j13 1 io_l71n_1 b13 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 201 1 io_l71p_1 b12 1 io_l70n_1 c13 1 io_l70p_1 c12 1 io_l69n_1/vref_1 h13 1 io_l69p_1 h12 1 io_l68n_1 d12 1 io_l68p_1 d11 1 io_l67n_1 b11 1 io_l67p_1 b10 1 io_l54n_1 e12 1 io_l54p_1 e11 1 io_l53n_1 a11 1 io_l53p_1 a10 1 io_l52n_1 g12 1 io_l52p_1 g11 1 io_l51n_1/vref_1 k13 1 io_l51p_1 k12 1 io_l50n_1 c11 1 io_l50p_1 c10 1 io_l49n_1 b9 1 io_l49p_1 b7 1 io_l30n_1 f11 nc 1 io_l30p_1 f9 nc 1 io_l29n_1 a9 nc 1 io_l29p_1 a8 nc 1 io_l27n_1/vref_1 d9 nc 1 io_l27p_1 d8 nc 1 io_l26n_1 j12 nc 1 io_l26p_1 j11 nc 1 io_l25n_1 c9 nc 1 io_l25p_1 c8 nc 1 io_l24n_1 e10 1 io_l24p_1 e9 1 io_l23n_1 h11 1 io_l23p_1 h10 1 io_l22n_1 a7 1 io_l22p_1 a6 1 io_l21n_1/vref_1 a5 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 202 1 io_l21p_1 a4 1 io_l20n_1 g10 1 io_l20p_1 g9 1 io_l19n_1 b6 1 io_l19p_1 c5 1 io_l06n_1 c6 1 io_l06p_1 d6 1 io_l05n_1 h9 1 io_l05p_1 g8 1 io_l04n_1 d7 1 io_l04p_1/vref_1 e6 1 io_l03n_1/vrp_1 e8 1 io_l03p_1/vrn_1 e7 1 io_l02n_1 f8 1 io_l02p_1 f7 1 io_l01n_1 b5 1 io_l01p_1 b3 2 io_l01n_2 f5 2 io_l01p_2 g4 2 io_l02n_2/vrp_2 g6 2 io_l02p_2/vrn_2 h6 2 io_l03n_2 d3 2 io_l03p_2/vref_2 e4 2 io_l04n_2 k10 2 io_l04p_2 k9 2 io_l05n_2 d2 2 io_l05p_2 e3 2 io_l06n_2 f4 2 io_l06p_2 f3 2 io_l19n_2 l10 2 io_l19p_2 m10 2 io_l20n_2 h7 2 io_l20p_2 j8 2 io_l21n_2 d1 2 io_l21p_2/vref_2 e1 2 io_l22n_2 g5 2 io_l22p_2 h5 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 203 2 io_l23n_2 e2 2 io_l23p_2 f2 2 io_l24n_2 h4 2 io_l24p_2 j4 2 io_l25n_2 k8 nc 2 io_l25p_2 l8 nc 2 io_l27n_2 j7 nc 2 io_l27p_2/vref_2 k7 nc 2 io_l43n_2 f1 2 io_l43p_2 g1 2 io_l44n_2 l9 2 io_l44p_2 m9 2 io_l45n_2 g2 2 io_l45p_2/vref_2 j2 2 io_l46n_2 h3 2 io_l46p_2 j3 2 io_l47n_2 j6 2 io_l47p_2 l6 2 io_l48n_2 j5 2 io_l48p_2 k5 2 io_l49n_2 h1 2 io_l49p_2 j1 2 io_l50n_2 n10 2 io_l50p_2 p10 2 io_l51n_2 l7 2 io_l51p_2/vref_2 m7 2 io_l52n_2 k3 2 io_l52p_2 l3 2 io_l53n_2 m8 2 io_l53p_2 n8 2 io_l54n_2 l5 2 io_l54p_2 m5 2 io_l67n_2 k2 2 io_l67p_2 l2 2 io_l68n_2 m6 2 io_l68p_2 n6 2 io_l69n_2 l4 2 io_l69p_2/vref_2 m4 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 204 2 io_l70n_2 k1 2 io_l70p_2 l1 2 io_l71n_2 n9 2 io_l71p_2 p9 2 io_l72n_2 n5 2 io_l72p_2 p5 2 io_l73n_2 m3 2 io_l73p_2 n3 2 io_l74n_2 r8 2 io_l74p_2 r9 2 io_l75n_2 m2 2 io_l75p_2/vref_2 n2 2 io_l76n_2 m1 2 io_l76p_2 n1 2 io_l77n_2 p7 2 io_l77p_2 r7 2 io_l78n_2 n4 2 io_l78p_2 p4 2 io_l91n_2 t8 2 io_l91p_2 t9 2 io_l92n_2 p6 2 io_l92p_2 r6 2 io_l93n_2 p2 2 io_l93p_2/vref_2 r2 2 io_l94n_2 r5 2 io_l94p_2 t5 2 io_l95n_2 p1 2 io_l95p_2 r1 2 io_l96n_2 r4 2 io_l96p_2 r3 3 io_l96n_3 t6 3 io_l96p_3 u5 3 io_l95n_3 u6 3 io_l95p_3 v6 3 io_l94n_3 t3 3 io_l94p_3 u3 3 io_l93n_3/vref_3 u1 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 205 3 io_l93p_3 v1 3 io_l92n_3 u8 3 io_l92p_3 w8 3 io_l91n_3 u2 3 io_l91p_3 v2 3 io_l78n_3 u7 3 io_l78p_3 v7 3 io_l77n_3 u4 3 io_l77p_3 v4 3 io_l76n_3 w1 3 io_l76p_3 y1 3 io_l75n_3/vref_3 v5 3 io_l75p_3 w5 3 io_l74n_3 w2 3 io_l74p_3 y2 3 io_l73n_3 w6 3 io_l73p_3 y6 3 io_l72n_3 y5 3 io_l72p_3 aa5 3 io_l71n_3 w3 3 io_l71p_3 y3 3 io_l70n_3 w4 3 io_l70p_3 y4 3 io_l69n_3/vref_3 u9 3 io_l69p_3 v9 3 io_l68n_3 aa1 3 io_l68p_3 ab1 3 io_l67n_3 y7 3 io_l67p_3 aa7 3 io_l54n_3 aa6 3 io_l54p_3 ac6 3 io_l53n_3 aa2 3 io_l53p_3 ab2 3 io_l52n_3 aa4 3 io_l52p_3 ac4 3 io_l51n_3/vref_3 v10 3 io_l51p_3 w10 3 io_l50n_3 aa3 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 206 3 io_l50p_3 ab3 3 io_l49n_3 ab5 3 io_l49p_3 ac5 3 io_l48n_3 w9 3 io_l48p_3 y9 3 io_l47n_3 ac1 3 io_l47p_3 ad1 3 io_l46n_3 ac3 3 io_l46p_3 ad3 3 io_l45n_3/vref_3 y8 3 io_l45p_3 aa8 3 io_l44n_3 ac2 3 io_l44p_3 ae2 3 io_l43n_3 ab7 3 io_l43p_3 ac7 3 io_l27n_3/vref_3 y10 nc 3 io_l27p_3 aa10 nc 3 io_l25n_3 ae1 nc 3 io_l25p_3 af1 nc 3 io_l24n_3 af2 3 io_l24p_3 ag2 3 io_l23n_3 aa9 3 io_l23p_3 ab9 3 io_l22n_3 ad4 3 io_l22p_3 ae4 3 io_l21n_3/vref_3 ad5 3 io_l21p_3 ae5 3 io_l20n_3 ab8 3 io_l20p_3 ac8 3 io_l19n_3 ag1 3 io_l19p_3 ah1 3 io_l06n_3 af4 3 io_l06p_3 ag4 3 io_l05n_3 ab10 3 io_l05p_3 ab11 3 io_l04n_3 af3 3 io_l04p_3 ag3 3 io_l03n_3/vref_3 ad6 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 207 3 io_l03p_3 ad7 3 io_l02n_3/vrp_3 ae6 3 io_l02p_3/vrn_3 af5 3 io_l01n_3 ah2 3 io_l01p_3 ah3 4 io_l01n_4/busy/dout (1) ad9 4 io_l01p_4/init_b ad10 4 io_l02n_4/d0/din (1) af7 4 io_l02p_4/d1 ag7 4 io_l03n_4/d2/alt_vrp_4 ak3 4 io_l03p_4/d3/alt_vrn_4 aj5 4 io_l04n_4/vref_4 ae8 4 io_l04p_4 af8 4 io_l05n_4/vrp_4 ak4 4 io_l05p_4/vrn_4 ak5 4 io_l06n_4 ah6 4 io_l06p_4 ah7 4 io_l19n_4 ac10 4 io_l19p_4 ac11 4 io_l20n_4 ae9 4 io_l20p_4 ae10 4 io_l21n_4 al4 4 io_l21p_4/vref_4 al5 4 io_l22n_4 ab12 4 io_l22p_4 ab13 4 io_l23n_4 aj6 4 io_l23p_4 aj8 4 io_l24n_4 ak6 4 io_l24p_4 ak7 4 io_l25n_4 ag8 nc 4 io_l25p_4 ag9 nc 4 io_l26n_4 af9 nc 4 io_l26p_4 af11 nc 4 io_l27n_4 ah8 nc 4 io_l27p_4/vref_4 ah9 nc 4 io_l28n_4 ad11 nc 4 io_l28p_4 ad12 nc ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 208 4 io_l29n_4 al6 nc 4 io_l29p_4 al7 nc 4 io_l30n_4 aj9 nc 4 io_l30p_4 aj10 nc 4 io_l49n_4 ae11 4 io_l49p_4 ae12 4 io_l50n_4 ag10 4 io_l50p_4 ag11 4 io_l51n_4 al8 4 io_l51p_4/vref_4 al9 4 io_l52n_4 af12 4 io_l52p_4 af13 4 io_l53n_4 ak9 4 io_l53p_4 ak10 4 io_l54n_4 ah11 4 io_l54p_4 ah12 4 io_l67n_4 ac12 4 io_l67p_4 ac13 4 io_l68n_4 ag12 4 io_l68p_4 ag13 4 io_l69n_4 al10 4 io_l69p_4/vref_4 al11 4 io_l70n_4 ad13 4 io_l70p_4 ad15 4 io_l71n_4 aj11 4 io_l71p_4 aj12 4 io_l72n_4 ak11 4 io_l72p_4 ak12 4 io_l73n_4 ae14 4 io_l73p_4 ae15 4 io_l74n_4 af14 4 io_l74p_4 af15 4 io_l75n_4 al12 4 io_l75p_4/vref_4 al13 4 io_l76n_4 ab14 4 io_l76p_4 ac14 4 io_l77n_4 ah13 4 io_l77p_4 ah14 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 209 4 io_l78n_4 aj13 4 io_l78p_4 ak13 4 io_l91n_4/vref_4 ac15 4 io_l91p_4 ac16 4 io_l92n_4 ag14 4 io_l92p_4 ag15 4 io_l93n_4 ak14 4 io_l93p_4 ak15 4 io_l94n_4/vref_4 af16 4 io_l94p_4 ag16 4 io_l95n_4/gclk3s al14 4 io_l95p_4/gclk2p al15 4 io_l96n_4/gclk1s ah15 4 io_l96p_4/gclk0p aj15 5 io_l96n_5/gclk7s aj16 5 io_l96p_5/gclk6p ah17 5 io_l95n_5/gclk5s ad16 5 io_l95p_5/gclk4p ad17 5 io_l94n_5 al17 5 io_l94p_5/vref_5 al18 5 io_l93n_5 ag17 5 io_l93p_5 af17 5 io_l92n_5 ae17 5 io_l92p_5 ae18 5 io_l91n_5 ak17 5 io_l91p_5/vref_5 aj17 5 io_l78n_5 ak18 5 io_l78p_5 ak19 5 io_l77n_5 ac17 5 io_l77p_5 ab18 5 io_l76n_5 ah18 5 io_l76p_5 ah19 5 io_l75n_5/vref_5 al19 5 io_l75p_5 al20 5 io_l74n_5 ac18 5 io_l74p_5 ac19 5 io_l73n_5 aj19 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 210 5 io_l73p_5 aj20 5 io_l72n_5 ag18 5 io_l72p_5 ag19 5 io_l71n_5 af18 5 io_l71p_5 af19 5 io_l70n_5 ak20 5 io_l70p_5 ak21 5 io_l69n_5/vref_5 ah20 5 io_l69p_5 ah21 5 io_l68n_5 ad19 5 io_l68p_5 ad20 5 io_l67n_5 al21 5 io_l67p_5 al22 5 io_l54n_5 ag20 5 io_l54p_5 ag21 5 io_l53n_5 ab19 5 io_l53p_5 ab20 5 io_l52n_5 aj21 5 io_l52p_5 aj22 5 io_l51n_5/vref_5 af20 5 io_l51p_5 af21 5 io_l50n_5 ae20 5 io_l50p_5 ae21 5 io_l49n_5 ak22 5 io_l49p_5 ak23 5 io_l30n_5 aj23 nc 5 io_l30p_5 aj24 nc 5 io_l29n_5 ac20 nc 5 io_l29p_5 ac21 nc 5 io_l28n_5 al23 nc 5 io_l28p_5 al24 nc 5 io_l27n_5/vref_5 al25 nc 5 io_l27p_5 al26 nc 5 io_l26n_5 ad21 nc 5 io_l26p_5 ad22 nc 5 io_l25n_5 ah23 nc 5 io_l25p_5 ah24 nc 5 io_l24n_5 ag22 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 211 5 io_l24p_5 ag23 5 io_l23n_5 ae22 5 io_l23p_5 ae23 5 io_l22n_5 ak25 5 io_l22p_5 ak26 5 io_l21n_5/vref_5 ah25 5 io_l21p_5 ag25 5 io_l20n_5 ab21 5 io_l20p_5 ac22 5 io_l19n_5 al27 5 io_l19p_5 al28 5 io_l06n_5 ak27 5 io_l06p_5 aj27 5 io_l05n_5/vrp_5 ad23 5 io_l05p_5/vrn_5 ae24 5 io_l04n_5 aj26 5 io_l04p_5/vref_5 ah26 5 io_l03n_5/d4/alt_vrp_5 af23 5 io_l03p_5/d5/alt_vrn_5 af24 5 io_l02n_5/d6 ag24 5 io_l02p_5/d7 af25 5 io_l01n_5/rdwr_b ak28 5 io_l01p_5/cs_b ak29 6 io_l01p_6 af27 6 io_l01n_6 af28 6 io_l02p_6/vrn_6 ae26 6 io_l02n_6/vrp_6 ae27 6 io_l03p_6 ah29 6 io_l03n_6/vref_6 ah30 6 io_l04p_6 ab22 6 io_l04n_6 ab23 6 io_l05p_6 ag28 6 io_l05n_6 ag29 6 io_l06p_6 ah31 6 io_l06n_6 ag31 6 io_l19p_6 aa22 6 io_l19n_6 y22 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 212 6 io_l20p_6 ad25 6 io_l20n_6 ac24 6 io_l21p_6 ag30 6 io_l21n_6/vref_6 af30 6 io_l22p_6 ad26 6 io_l22n_6 ac26 6 io_l23p_6 af29 6 io_l23n_6 ad29 6 io_l24p_6 ae28 6 io_l24n_6 ad28 6 io_l25p_6 ab24 nc 6 io_l25n_6 aa24 nc 6 io_l27p_6 ac25 nc 6 io_l27n_6/vref_6 ab25 nc 6 io_l43p_6 af31 6 io_l43n_6 ae31 6 io_l44p_6 aa23 6 io_l44n_6 y23 6 io_l45p_6 ae30 6 io_l45n_6/vref_6 ac30 6 io_l46p_6 ac28 6 io_l46n_6 aa28 6 io_l47p_6 ad27 6 io_l47n_6 ac27 6 io_l48p_6 aa25 6 io_l48n_6 y25 6 io_l49p_6 ac29 6 io_l49n_6 ab29 6 io_l50p_6 ab27 6 io_l50n_6 aa27 6 io_l51p_6 aa26 6 io_l51n_6/vref_6 y26 6 io_l52p_6 ad31 6 io_l52n_6 ac31 6 io_l53p_6 w22 6 io_l53n_6 v22 6 io_l54p_6 y27 6 io_l54n_6 w27 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 213 6 io_l67p_6 ab30 6 io_l67n_6 aa30 6 io_l68p_6 w26 6 io_l68n_6 v26 6 io_l69p_6 ab31 6 io_l69n_6/vref_6 aa31 6 io_l70p_6 aa29 6 io_l70n_6 y29 6 io_l71p_6 y24 6 io_l71n_6 w24 6 io_l72p_6 v25 6 io_l72n_6 u25 6 io_l73p_6 y28 6 io_l73n_6 w28 6 io_l74p_6 w23 6 io_l74n_6 v23 6 io_l75p_6 y30 6 io_l75n_6/vref_6 w30 6 io_l76p_6 y31 6 io_l76n_6 w31 6 io_l77p_6 v27 6 io_l77n_6 u27 6 io_l78p_6 w29 6 io_l78n_6 u29 6 io_l91p_6 u23 6 io_l91n_6 t23 6 io_l92p_6 u26 6 io_l92n_6 t26 6 io_l93p_6 v28 6 io_l93n_6/vref_6 u28 6 io_l94p_6 u24 6 io_l94n_6 t24 6 io_l95p_6 v30 6 io_l95n_6 u30 6 io_l96p_6 v31 6 io_l96n_6 u31 7 io_l96p_7 t27 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 214 7 io_l96n_7 r27 7 io_l95p_7 r24 7 io_l95n_7 n24 7 io_l94p_7 t29 7 io_l94n_7 r29 7 io_l93p_7/vref_7 r31 7 io_l93n_7 p31 7 io_l92p_7 r26 7 io_l92n_7 p26 7 io_l91p_7 r30 7 io_l91n_7 p30 7 io_l78p_7 r25 7 io_l78n_7 p25 7 io_l77p_7 r28 7 io_l77n_7 p28 7 io_l76p_7 n31 7 io_l76n_7 m31 7 io_l75p_7/vref_7 r23 7 io_l75n_7 p23 7 io_l74p_7 n30 7 io_l74n_7 m30 7 io_l73p_7 p27 7 io_l73n_7 n27 7 io_l72p_7 p22 7 io_l72n_7 n22 7 io_l71p_7 n29 7 io_l71n_7 m29 7 io_l70p_7 n28 7 io_l70n_7 m28 7 io_l69p_7/vref_7 n26 7 io_l69n_7 m26 7 io_l68p_7 l31 7 io_l68n_7 k31 7 io_l67p_7 m27 7 io_l67n_7 l27 7 io_l54p_7 n23 7 io_l54n_7 m23 7 io_l53p_7 l30 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 215 7 io_l53n_7 k30 7 io_l52p_7 l28 7 io_l52n_7 j28 7 io_l51p_7/vref_7 m24 7 io_l51n_7 l24 7 io_l50p_7 l29 7 io_l50n_7 k29 7 io_l49p_7 m25 7 io_l49n_7 l25 7 io_l48p_7 l26 7 io_l48n_7 j26 7 io_l47p_7 j31 7 io_l47n_7 h31 7 io_l46p_7 j29 7 io_l46n_7 h29 7 io_l45p_7/vref_7 m22 7 io_l45n_7 l22 7 io_l44p_7 j30 7 io_l44n_7 g30 7 io_l43p_7 k27 7 io_l43n_7 j27 7 io_l27p_7/vref_7 l23 nc 7 io_l27n_7 k23 nc 7 io_l25p_7 g31 nc 7 io_l25n_7 f31 nc 7 io_l24p_7 f30 7 io_l24n_7 e30 7 io_l23p_7 k25 7 io_l23n_7 j25 7 io_l22p_7 h28 7 io_l22n_7 g28 7 io_l21p_7/vref_7 h27 7 io_l21n_7 g27 7 io_l20p_7 k24 7 io_l20n_7 j24 7 io_l19p_7 e31 7 io_l19n_7 d31 7 io_l06p_7 f28 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 216 7 io_l06n_7 e28 7 io_l05p_7 k22 7 io_l05n_7 k21 7 io_l04p_7 f29 7 io_l04n_7 e29 7 io_l03p_7/vref_7 h26 7 io_l03n_7 h25 7 io_l02p_7/vrn_7 g26 7 io_l02n_7/vrp_7 f27 7 io_l01p_7 d30 7 io_l01n_7 d29 0 vcco_0 c18 0 vcco_0 c25 0 vcco_0 f22 0 vcco_0 h18 0 vcco_0 l17 0 vcco_0 l18 0 vcco_0 l19 0 vcco_0 l20 0 vcco_0 m17 0 vcco_0 m18 0 vcco_0 m19 1 vcco_1 c7 1 vcco_1 c14 1 vcco_1 f10 1 vcco_1 h14 1 vcco_1 l12 1 vcco_1 l13 1 vcco_1 l14 1 vcco_1 l15 1 vcco_1 m13 1 vcco_1 m14 1 vcco_1 m15 2 vcco_2 g3 2 vcco_2 k6 2 vcco_2 m11 2 vcco_2 n11 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 217 2 vcco_2 n12 2 vcco_2 p3 2 vcco_2 p8 2 vcco_2 p11 2 vcco_2 p12 2 vcco_2 r11 2 vcco_2 r12 3 vcco_3 u11 3 vcco_3 u12 3 vcco_3 v3 3 vcco_3 v8 3 vcco_3 v11 3 vcco_3 v12 3 vcco_3 w11 3 vcco_3 w12 3 vcco_3 y11 3 vcco_3 ab6 3 vcco_3 ae3 4 vcco_4 y13 4 vcco_4 y14 4 vcco_4 y15 4 vcco_4 aa12 4 vcco_4 aa13 4 vcco_4 aa14 4 vcco_4 aa15 4 vcco_4 ad14 4 vcco_4 af10 4 vcco_4 aj7 4 vcco_4 aj14 5 vcco_5 y17 5 vcco_5 y18 5 vcco_5 y19 5 vcco_5 aa17 5 vcco_5 aa18 5 vcco_5 aa19 5 vcco_5 aa20 5 vcco_5 ad18 5 vcco_5 af22 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 218 5 vcco_5 aj18 5 vcco_5 aj25 6 vcco_6 u20 6 vcco_6 u21 6 vcco_6 v20 6 vcco_6 v21 6 vcco_6 v24 6 vcco_6 v29 6 vcco_6 w20 6 vcco_6 w21 6 vcco_6 y21 6 vcco_6 ab26 6 vcco_6 ae29 7 vcco_7 g29 7 vcco_7 k26 7 vcco_7 m21 7 vcco_7 n20 7 vcco_7 n21 7 vcco_7 p20 7 vcco_7 p21 7 vcco_7 p24 7 vcco_7 p29 7 vcco_7 r20 7 vcco_7 r21 na cclk aj4 na prog_b d27 na done ag6 na m0 ah27 na m1 aj28 na m2 ag26 na hswap_en e26 na tck k11 na tdi c28 na tdo c4 na tms j10 na pwrdwn_b ah5 na dxn f25 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 219 na dxp b28 na vbatt d5 na rsvd b4 na vccaux b16 na vccaux c2 na vccaux c30 na vccaux t2 na vccaux t30 na vccaux aj2 na vccaux aj30 na vccaux ak16 na vccint k15 na vccint k17 na vccint l11 na vccint l16 na vccint l21 na vccint m12 na vccint m16 na vccint m20 na vccint n13 na vccint n14 na vccint n15 na vccint n16 na vccint n17 na vccint n18 na vccint n19 na vccint p13 na vccint p19 na vccint r10 na vccint r13 na vccint r19 na vccint r22 na vccint t11 na vccint t12 na vccint t13 na vccint t19 na vccint t20 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 220 na vccint t21 na vccint u10 na vccint u13 na vccint u19 na vccint u22 na vccint v13 na vccint v19 na vccint w13 na vccint w14 na vccint w15 na vccint w16 na vccint w17 na vccint w18 na vccint w19 na vccint y12 na vccint y16 na vccint y20 na vccint aa11 na vccint aa16 na vccint aa21 na vccint ab15 na vccint ab17 na gnd a2 na gnd a3 na gnd a16 na gnd a29 na gnd a30 na gnd b1 na gnd b2 na gnd b8 na gnd b24 na gnd b30 na gnd b31 na gnd c1 na gnd c3 na gnd c29 na gnd c31 na gnd d4 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 221 na gnd d10 na gnd d16 na gnd d22 na gnd d28 na gnd e5 na gnd e27 na gnd f6 na gnd f26 na gnd g7 na gnd g13 na gnd g16 na gnd g19 na gnd g25 na gnd h2 na gnd h8 na gnd h24 na gnd h30 na gnd j9 na gnd j23 na gnd k4 na gnd k16 na gnd k28 na gnd n7 na gnd n25 na gnd p14 na gnd p15 na gnd p16 na gnd p17 na gnd p18 na gnd r14 na gnd r15 na gnd r16 na gnd r17 na gnd r18 na gnd t1 na gnd t4 na gnd t7 na gnd t10 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 222 na gnd t14 na gnd t15 na gnd t16 na gnd t17 na gnd t18 na gnd t22 na gnd t25 na gnd t28 na gnd t31 na gnd u14 na gnd u15 na gnd u16 na gnd u17 na gnd u18 na gnd v14 na gnd v15 na gnd v16 na gnd v17 na gnd v18 na gnd w7 na gnd w25 na gnd ab4 na gnd ab16 na gnd ab28 na gnd ac9 na gnd ac23 na gnd ad2 na gnd ad8 na gnd ad24 na gnd ad30 na gnd ae7 na gnd ae13 na gnd ae16 na gnd ae19 na gnd ae25 na gnd af6 na gnd af26 na gnd ag5 ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 223 na gnd ag27 na gnd ah4 na gnd ah10 na gnd ah16 na gnd ah22 na gnd ah28 na gnd aj1 na gnd aj3 na gnd aj29 na gnd aj31 na gnd ak1 na gnd ak2 na gnd ak8 na gnd ak24 na gnd ak30 na gnd ak31 na gnd al2 na gnd al3 na gnd al16 na gnd al29 na gnd al30 notes: 1. see ta b l e 4 for an explanation of the signals available on this pin. ta bl e 1 4 : bf957 ? XC2V2000, xc2v3000, xc2v4000, and xc2v6000 bank pin description pin number no connect in XC2V2000
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 224 bf957 flip-chip bga package specifications (1 .27mm pitch) figure 10: bf957 flip-chip bga package specifications
virtex?-ii platform fp gas: pinout information r ds031-4 (v2.0) august 1, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 225 revision history this section records the change history for this module of the data sheet. virtex-ii data sheet the virtex-ii data sheet contains the following modules: virtex?-ii platform fpgas: introduction and overview (module 1) virtex?-ii platform fpgas: detailed description (module 2) virtex?-ii platform fpgas: dc and switching characteristics (module 3) virtex?-ii platform fpgas: pinout information (module 4) date version revision 11/07/00 1.0 early access draft. 11/22/00 1.1 initial xilin x release. made the following corrections: cs144 package - table 5, page 5 : added missing pin d10 in bank 1. changed dedicated pins a2 and b2 to rsvd (from dxn and dxp). fg256 package - table 6, page 10 : changed dedicated pins a3 and a4 to rsvd (from dxn and dxp). fg896 package - table 11, page 94 : corrected pin ag1 in bank 4 to be ag12. ff1152 package - table 12, page 120 : corrected pin y3 in bank 6 to be y32. 12/19/00 1.2 reverse designations were fixed for pins in every package. 01/25/01 1.3 the data sheet was divided into four modules (per the current style standard). dxn and dxp pin information was added for the cs144 package ( ta b l e 5 ) and the fg256 package ( ta bl e 6 ). 02/07/01 1.4 dxn and dxp pin information was changed back to rsvd for the cs144 package ( ta b l e 5 ) and the fg256 package ( ta b l e 6 ). 04/02/01 1.5 alt_vrn and alt_vrp pin information was added for each package. table 8, page 34 ? added no connect designations for the xc2v1500 device in the fg676 package. reverted to traditional double-column format. 11/07/01 1.6 updated list of devices supported in the ff1152, ff1517, and bf957 packages. 09/26/02 1.7 updated ta b l e 3 to reflect devices supported in the bg728 and bf957 packages. added mention of lvpecl to pin definition in ta bl e 4 . 10/07/02 1.8 corrected ta b l e 1 0 heading to reflect supported devices in the bg728 package. 12/06/02 1.8.1 enhanced the description of the pwrdwn_b pin in ta b l e 4 . 05/07/03 1.8.2 added clarification to ta b l e 4 and all device pinout tables regarding the dual-use nature of pins d0/din and busy/dout during configuration. 06/19/03 1.8.3 the final gnd pin in each of five pinout tables was inadvertently deleted in v1.8.2. this revision restores the deleted gnd pins as follows: - pin c5, table5, page5 (cs144) - pin a1, table 6, page 10 (fg256) - pin a2, table 10, page 72 (bg728) - pin a2, table 12, page 120 (ff1152) - pin al30, table 14, page 198 (bf957) 08/01/03 2.0 all virtex-ii devices and speed grades now production. see table 13, module 3.

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