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duslic dual channel subscriber line interface concept peb 3264/-2 version 1.3 peb 4264/-2 version 1.1 peb 3265 version 1.3 peb 4265/-2 version 1.1 peb 4266 version 1.1 never stop thinking. product overview, ds2, nov. 2000 wired communications
edition 2000-11-09 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 11/8/00. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
p r e l i m i nar y wired communications duslic dual channel subscriber line interface concept peb 3264/-2 version 1.3 peb 4264/-2 version 1.1 peb 3265 version 1.3 peb 4265/-2 version 1.1 peb 4266 version 1.1 product overview, ds2, nov. 2000 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com duslic preliminary revision history: 2000-11-09 ds2 previous version: product overview ds1 page subjects (major changes since last revision) all peb 3265 version changed from 1.2 to 1.3 all new codecs slicofi-2s/-2s2 (peb 3264/-2) and new slics slic-s/-s2 (peb 4264/-2) and slic-e2 (peb4265-2) added. all major changes throughout the whole document
duslic table of contents page product overview 2000-11-09 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 basic functions available for all duslic chip sets . . . . . . . . . . . . . . . . 9 2.1.2 additional functions available for duslic-e/-e2/-p chip sets . . . . . . . 12 2.2 dc feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 dc characteristic feeding zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 constant current zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.3 resistive zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 constant voltage zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 programmable voltage and current range of dc characteristic . . . . . 19 2.2.6 slic power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 necessary voltage reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.8 extended battery feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 ac transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.1 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.2 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.3 impedance matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.4 transhybrid balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.1 ringer load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.2 ring trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.3 ringing methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.4 duslic ringing options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.5 internal balanced ringing via slics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.6 internal unbalanced ringing with slic-p . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.7 external unbalanced ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5 signaling (supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6 metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.1 metering by 12/16 khz sinusoidal bursts . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.2 metering by polarity reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.2.1 soft reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.7 duslic enhanced signal processing capabilities . . . . . . . . . . . . . . . . . . 40 2.7.1 dtmf generation and detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.7.2 caller id generation (only duslic-e/-e2/-p) . . . . . . . . . . . . . . . . . . . . 43 2.7.3 line echo cancelling (lec) (only duslic-e/-e2/-p) . . . . . . . . . . . . . . 45 2.7.4 universal tone detection (utd) (only duslic-e/-e2/-p) . . . . . . . . . . . 46 2.8 message waiting indication (only duslic-e/-e2/-p) . . . . . . . . . . . . . . . . 47 2.9 three-party conferencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
duslic table of contents page product overview 2000-11-09 2.9.1 conferencing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.10 16 khz modes on pcm highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.1 operating modes for the duslic chip set . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2 operating modes for the duslic-s/-s2 chip set . . . . . . . . . . . . . . . . . . . 54 3.3 operating modes for the duslic-e/-e2 chip set . . . . . . . . . . . . . . . . . . . 56 3.4 operating modes for the duslic-p chip set . . . . . . . . . . . . . . . . . . . . . . 58 3.5 operating modes and power management . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5.2 power dissipation of the slicofi-2x . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5.3 power dissipation of the slic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.3.1 power down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.3.2 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.3.3 slic power consumption calculation in active mode . . . . . . . . . . . 64 3.5.3.4 ringing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.5.3.5 slic power consumption calculation in ringing mode . . . . . . . . . . 71 3.6 integrated test and diagnosis functions (itdf) . . . . . . . . . . . . . . . . . . . . 75 3.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.6.2 conventional line testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.6.3 duslic line testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.6.4 diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.6.4.1 line test capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.6.4.2 integrated signal sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.6.4.3 dc levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.6.4.4 ac levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.6.5 signal path and test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.6.5.1 test loops slicofi-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.6.5.2 test loops slicofi-2s/-2s2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1 pcm interface with a serial microcontroller interface . . . . . . . . . . . . . . . . 83 4.1.1 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1.2 serial microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.2 the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.3 tip/ring interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.4 slicofi-2s/-2s2 and slic-s/-s2 interface . . . . . . . . . . . . . . . . . . . . . . . 92 4.5 slicofi-2 and slic-e/-e2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.6 slicofi-2 and slic-p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
duslic product overview 2000-11-09 preliminary 5 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1 internal ringing (balanced/unbalanced) . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.1 circuit diagram internal ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.1.2 protection circuit for slic-e/-e2 and slic-s . . . . . . . . . . . . . . . . . . . . 97 5.1.3 protection circuit for slic-p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.1.4 bill of materials (including protection) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2 external unbalanced ringing with duslic-e/-e2/-s/-s2/-p . . . . . . . . . . 100 6 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
duslic list of figures page product overview 2000-11-09 figure 1 duslic chip set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2 logic symbol slic-s / slic-s2 / slic-e / slic-e2 . . . . . . . . . . . . . . . 7 figure 3 logic symbol slic-p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4 logic symbol slicofi-2/-2s/-2s2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5 line circuit functions included in the duslic-s/-s2 . . . . . . . . . . . . . 13 figure 6 line circuit functions included in the duslic-e/-e2/-p . . . . . . . . . . . 13 figure 7 signal paths - dc feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8 dc feeding characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9 constant current zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10 resistive zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11 constant voltage zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12 dc characteristic (detailed description) . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14 ttx voltage reserve schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15 dc feeding characteristics (acth, actr) . . . . . . . . . . . . . . . . . . . . 22 figure 16 signal paths - ac transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17 signal flow in voice channel (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18 nyquist diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19 2/4-wire conversion in the hybrid circuit. . . . . . . . . . . . . . . . . . . . . . . 26 figure 20 typical ringer loads of 1 and 5 ren used in us . . . . . . . . . . . . . . . . 27 figure 21 balanced ringing via slic-e/-e2, slic-s and slic-p . . . . . . . . . . . . 33 figure 22 unbalanced ringing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 23 teletax injection and metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 24 soft reversal (example for open loop) . . . . . . . . . . . . . . . . . . . . . . . 39 figure 25 duslic ac signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 26 bellcore on-hook caller id physical layer transmission . . . . . . . . . . 44 figure 27 line echo cancellation unit - block diagram . . . . . . . . . . . . . . . . . . . 45 figure 28 utd functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 29 mwi circuitry with glow lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 30 conference block for one duslic channel . . . . . . . . . . . . . . . . . . . . 48 figure 31 circuit diagram for power consumption . . . . . . . . . . . . . . . . . . . . . . . 64 figure 32 slic-e/-e2 power dissipation with switched battery voltage . . . . . . . 66 figure 33 slic-p power dissipation (switched battery voltage, long loops) . . 67 figure 34 slic-p power dissipation (switched battery voltage, short loops). . 69 figure 35 circuit diagram for ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 36 ac test loops slicofi-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 37 dc test loops slicofi-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 38 ac test loops slicofi-2s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 39 ac test loops slicofi-2s2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 40 dc test loops slicofi-2s/-2s2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 41 general pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 42 serial microcontroller interface write access . . . . . . . . . . . . . . . . . . . 87
duslic list of figures page product overview 2000-11-09 figure 43 serial microcontroller interface read access . . . . . . . . . . . . . . . . . . . 87 figure 44 iom-2 int. timing for up to 16 voice channels (per 8 khz frame) . . . 89 figure 45 iom-2 interface timing (dcl = 4096 khz, per 8 khz frame) . . . . . . . 90 figure 46 iom-2 interface timing (dcl = 2048 khz, per 8-khz frame) . . . . . . . 91 figure 47 interface slicofi-2s/-2s2 and slic-s/-s2 . . . . . . . . . . . . . . . . . . . . 92 figure 48 interface slicofi-2 and slic-e/-e2. . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 49 interface slicofi-2 and slic-p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 50 application circuit, internal ringing (balanced & unbalanced) . . . . . . 96 figure 51 typical overvoltage protection for slic-e/-e2 and slic-s . . . . . . . . 97 figure 52 typical overvoltage protection for slic-p . . . . . . . . . . . . . . . . . . . . . 98 figure 53 application circuit, external unbalanced ringing . . . . . . . . . . . . . . . 100 figure 54 application circuit, external unbalanced ringing for long loops. . . 101
duslic product overview 1 2000-11-09 preliminary preface this document describes the duslic chip set comprising a programmable dual channel slicofi-2x codec and two single channel high-voltage slic chips. for more duslic related documents please see our webpage at http://www.infineon.com/duslic. synonyms to simplify matters, the following synonyms are used: slicofi-2x: synonym used for all codec versions slicofi-2/-2s/-2s2 slic: synonym used for all slic versions slic-s/-s2, slic-e/-e2 and slic-p organization of this document this product overview is divided into six chapters. it is organized as follows: chapter 1, overview a general description of the product, list of its key features and some typical applications. chapter 2, functional description the main functions are presented following a functional block diagram. chapter 3, operational description a brief description of the three operating modes: power down, active and ringing (plus signal monitoring techniques). chapter 4, interfaces connection information including standard iom ? -2 and pcm interface timing frames and pins. chapter 5, application circuits illustrations of balanced ringing, unbalanced ringing and protection circuits. chapter 6, index
duslic overview product overview 2 2000-11-09 preliminary 1 overview duslic is a chip set, comprising one dual channel slicofi-2x codec and two single- channel slic chips. it is a highly flexible codec/slic solution for an analog line circuit and is widely programmable. users can now access different markets with a single hardware design that meets all different standards worldwide. the interconnections between the single channel high-voltage slic (170 v process) and the dual channel slicofi-2x codec (advanced cmos process) are a seamless fit. this guarantees maximum transmission performance with a minimum of necessary components. duslic family chip sets: the duslic family comprises five different chip sets (see table 1 ): ? three basic duslic chip sets optimized for different applications: duslic-s (standard), duslic-e (enhanced), duslic-p (power management). table 1 duslic chip sets chip set duslic-s duslic-s2 duslic-e duslic-e2 duslic-p marketing name slicofi-2s/ slic-s slicofi-2s2/ slic-s2 slicofi-2/ slic-e slicofi-2/ slic-e2 slicofi-2/ slic-p product id peb 3264/ peb 4264 peb 3264-2/ peb 4264-2 1) 1) nevertheless marked on the chip as peb 4264 peb 3265/ peb 4265 peb 3265/ peb 4265-2 2) 2) nevertheless marked on the chip as peb 4265 peb 3265/ peb 4266 longitudinal balance 53 db 60 db 53 db 60 db 53 db maximum dc feeding 32 ma 50 ma 32 ma 50 ma 32 ma neg. battery voltages 22222/3 add. positive voltages 11110 internal ringing 45 vrms balanced no 85 vrms balanced 85 vrms balanced 85 vrms bal., 50 vrms unbal. itdf 3) 3) integrated test and diagnosis functions (board or line testing) no no yes yes yes ttx 1.2 vrms no 2.5 vrms 2.5 vrms 2.5 vrms add-ons 4) 4) the add-on functions are dtmf detection, caller id generation, message waiting lamp support, three-party conferencing, universal tone detection (utd), line echo cancellation (lec) and sleep mode. no no yes yes yes
duslic overview product overview 3 2000-11-09 preliminary ? two different performance versions of the basic duslic-e and duslic-s chip sets (mainly regarding longitudinal balance and maximum dc feeding): duslic-e2 (using slic-e2 peb 4265-2 compared to duslic-e) duslic-s2 (using slic-s2 peb 4264-2 and codec peb 3264-2) the codec devices slicofi-2, slicofi-2s and slicofi-2s2 are manufactured in an advanced 0.35 m 3.3 v cmos process. the slic-e, slic-e2 and slic-p devices are manufactured in infineon technologies robust and well proven 170 v smart power technology. the slic-s and slic-s2 devices are manufactured in infineon technologies 90 v smart power technology. all line circuit functions are implemented on the duslic chip set: borscht functions internal balanced/unbalanced ringing capability up to 85 vrms metering by polarity reversal and by 12/16 khz sinusoidal bursts dual-tone multifrequency (dtmf) detection and generation caller id generation three-party conferencing universal tone detection (utd) unit for fax-/modemtone detection line echo cancellation unit (lec) integrated battery switches guarantee minimum power consumption during the off-hook, on-hook and ringing modes. test and diagnosis functions have been integrated to simplify testing (itdf). no external test equipment is needed for either subscriber line testing in the field or board testing during production or in the field. usage of codecs and slics: duslic-e, duslic-e2 and duslic-p comprise the same slicofi-2 codec with full edsp (enhanced digital signal processor) features like dtmf detection, caller id generation, universal tone detection (utd) and line echo cancellation. duslic-s comprises the slicofi-2s codec without edsp features. duslic-s2 comprises the slicofi-2s2 codec based on the slicofi-2s but without teletax metering (ttx) and internal ringing capability. the respective slic variant for each chip set featured in table 1 has been selected according to performance and application requirements: slic-s/-s2 (peb 4264 / peb 4264-2) and slic-e/-e2 (peb 4265 / peb 4265-2) are optimized for access network requirements, while the power management slic-p (peb 4266) is an enhanced version for extremely power-sensitive applications or for applications where internal unbalanced ringing is required.
duslic overview product overview 4 2000-11-09 preliminary duslic architecture unlike traditional designs, duslic splits the slic function into high-voltage slic functions and low-voltage slic functions. the low-voltage functions are handled in the slicofi-2x device. the partitioning of the functions is shown in figure 1 . figure 1 duslic chip set slicofi-2x hv slic functions lv slic functions codec filter functions voltage feeding programmable dc feeding filtering transversal current ring generation pcm compression/expansion sensing supervision programmable gain longitudinal current teletax generation programmable frequency sensing teletax notch filter impedance matching overload protection ring trip detection hybrid balance battery switching ground key detection dtmf generation ring amplification hook switch detection dtmf detection on-hook transmission fsk generation (caller id) polarity reversal linear mode support (16-bit uncompressed voice data) iom-2 and pcm/c interface integrated test and diagnosis functions (idtf) line echo cancelling (lec) universal tone detection (utd) three-party conferencing message waiting lamp support slic slic iom ? -2 pcm c ezm14034.wmf
p-mqfp-64-1,-2 p-dso-20-5 dual channel subscriber line interface concept duslic peb 3264/-2 peb 3265 peb 4264/-2 peb 4265/-2 peb 4266 product overview 5 2000-11-09 version 1.3 type package peb 3264/-2 p-mqfp-64-1 peb 4264/-2 p-dso-20-5 peb 3265 p-mqfp-64-1 peb 4265/-2 p-dso-20-5 peb 4266 p-dso-20-5 1.1 features internal balanced/unbalanced ringing capability up to 85 vrms programmable teletax (ttx) generation programmable battery feeding with capability for driving longer loops fully programmable dual-channel codec ground/loop start signaling polarity reversal integrated test and diagnosis functions (idtf) on-hook transmission integrated dtmf generator integrated dtmf decoder integrated caller id (fsk) generator integrated fax/modem detection (universal tone detection (utd)) integrated line echo cancellation unit (lec) optimized filter structure for modem transmission three-party conferencing (in pcm/ c mode) message waiting lamp support (pbx) power optimized architecture power management capability (integrated battery switches) 8 and 16 khz pcm transmission iom-2 or pcm/c-interface selectable specification in accordance with itu-t recommendation g.712, itu-t recommendation q.552 for interface z and applicable lssgr
duslic overview product overview 6 2000-11-09 preliminary 1.2 typical applications the infineon technologies duslic family is particularily designed for all access network applications and customer premises equipment but adresses all major telephone applications including: digital loop carrier (dlc) wireless local loop fiber in the loop private branch exchange intelligent nt (network termination) for isdn isdn terminal adapter central office cable modem xdsl nt router integrated access device (iad) voice over packet network application pcm-x systems
duslic overview product overview 7 2000-11-09 preliminary 1.3 logic symbols figure 2 logic symbol slic-s / slic-s2 / slic-e / slic-e2 figure 3 logic symbol slic-p tip ring vdd agnd vhr bgnd vbatl vbath vcms cext it il acp acn dcp dcn c1 c2 peb 4264 peb 4264-2 peb 4265 peb 4265-2 tip/ring interface power supply logic control ac & dc feeding line current ezm14094.emf tip ring vcms cext it il acp acn dcp dcn c1 c2 c3 peb 4266 tip/ring interface logic control ac & dc feeding line current vdd agnd bgnd vbatl vbath vbatr power supply ezm14095.emf
duslic overview product overview 8 2000-11-09 preliminary figure 4 logic symbol slicofi-2/-2s/-2s2 ita itb itaca itacb ila ilb vcmita vcmitb dcpa dcpb dcna dcnb cdcpa cdcna cdcpb cdcnb vcm vcms acpa acpb acna acnb c1a c1b c2a c2b io1a io2a io3a io4a io1b io2b io3b io4b peb 3265 peb 3264 peb 3264-2 pcm/iom-2 fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs int mclk sel24/dra dxa dxb tca tcb rsync reset test cref selclk vdda vddb gnda gndb vddr gndr vddd gndd vddpll gndpll power supply logic control iom-2 interface c-interface pcm interface line current dc loop ac loop i/o feeding ezm14096.emf
duslic functional description product overview 9 2000-11-09 preliminary 2 functional description 2.1 functional overview 2.1.1 basic functions available for all duslic chip sets the duslic chip set is a cost-effective, high-performance solution that provides the borscht functions of an analog line circuit. duslic has the advantage of offering all the functions integrated in a single channel high-voltage slic and in a dual channel dsp-based codec. the functions described in this chapter are integrated in all duslic chip sets (see figure 5 for duslic-s/-s2 and figure 6 for duslic-e/-e2/-p). borscht functions all borscht functions are integrated: battery feed overvoltage protection (realized by the robust high-voltage slic technology and additional circuitry) ringing 1) signaling (supervision) coding hybrid for 2/4-wire conversion testing the following paragraphs explain the advantages of using duslic to implement the borscht functions. battery feed an analog line circuit provides the voltage and current for subscriber equipment. in conventional line circuits, extra hardware is needed to adapt the battery feed characteristics to the requirements for different applications and countries. with the duslic chip set, the battery feed (dc) characteristics can be programmed in the slicofi-2x (low-voltage slic function, see figure 1 ) and applied to the line via the slic. overvoltage protection overvoltage protection is indispensable to prevent damage to the line circuit if the system is exposed to high voltages that can result from power lines crossing or lightning strikes. 1) for duslic-s2 chip set only external ringing is supported
duslic functional description product overview 10 2000-11-09 preliminary the robust 170 v slic technology together with the external low cost protection circuit, consisting of varistors, resistors and thyristor diodes, form a reliable overvoltage protection solution. if an overvoltage occurs, the protection circuit separates the duslic from the tip and ring lines. ringing the ringing signal is a low-frequency, high-voltage signal to the subscriber equipment. in conventional line circuits, the ringing voltage (e.g. 40 v rms to 85 v rms ) is generated in an external ringing generator and applied to the tip and ring lines by a relay. with the duslic chip set, the ringing generator is integrated and this relay is not needed. this saves space and costs in the line circuit design. the ringing signal is generated in the low-voltage slicofi-2x and amplified in the high-voltage slic. duslic supports balanced and unbalanced ringing. with balanced ringing, the ringing voltage is applied differentially to the tip and ring lines. with unbalanced ringing, the ringing voltage is applied single-ended to either the tip or ring line against a potential which is near ground (for details see ? ringing modes ? on page 69 ). balanced ringing is generated by slic-e/-e2 and slic-s, while slic-p can generate both balanced and unbalanced ringing. signaling (supervision) duslic must detect when a subscriber changes from on-hook mode to off-hook mode in both non-ringing (hook switch detection) and ringing modes (ring trip detection). with this chip set, the thresholds for ring trip detection can be programmed in slicofi-2x to suit applications without using external components. coding slicofi-2x encodes an analog input signal to a digital pcm signal and decodes a pcm signal to an analog signal. both a-law and -law coding is supported and can be selected via software. hybrid for 2/4-wire conversion the subscriber equipment is connected to a 2-wire interface (tip and ring) where information is transmitted bidirectionally. for digital transmission through the switching network, the information must be split into separate transmit and receive paths (4 wires). to avoid generating echoes, the hybrid function requires a balanced network matched to the line impedance. hybrid balancing can be programmed in the duslic device without using any external components. testing access to the analog loop is necessary to perform the regular measurements involved in monitoring the local loop. line circuit functions must also be tested. in conventional line circuit solutions, test units have to be switched to perform loop and line circuit tests. a remote testing unit and relays are normally necessary to perform a full range of tests. duslic already offers a number of internal test features to check both the local loop and the line circuit.
duslic functional description product overview 11 2000-11-09 preliminary programmability an important feature of the duslic design is the fact that all the slic and codec functions are programmable via the dual-channel codec device. conventional designs need a number of external components to adapt the circuit for use in different countries and applications. in contrast, the configuration software duslicos can be used to program the following functions of the duslic chip set: dc (battery) feed characteristics ac impedance matching transmit gain receive gain hybrid balance frequency response in transmit and receive direction ring frequency and amplitude 1) hook thresholds ttx modes 1) one of the main challenges of linecard development is to adapt the above-mentioned functions to country-specific requirements. these adaptations used to be handled by hardware, an approach that required a different linecard board for every modification to a specification. because signal processing within the slicofi-2x is completely digital, it is possible to adapt to the requirements listed above by simply updating the coefficients that control dsp processing of all data. this means, for example, that changing impedance matching or hybrid balance requires no hardware modifications. a single hardware is now capable of meeting the requirements for different markets. the digital nature of the filters and gain stages also assures high reliability, no drifts (over temperature or time) and minimal variations between different lines. the characteristics for the two voice channels within slicofi-2x can be programmed independently of each other. the duslicos software is provided to automate calculation of coefficients to match different requirements. duslicos also verifies the calculated coefficients. 1) not available with duslic-s2 chip set
duslic functional description product overview 12 2000-11-09 preliminary 2.1.2 additional functions available for duslic-e/-e2/-p chip sets the following line circuit functions are integrated only in the duslic-e/-e2/-p chip sets (see figure 6 ): teletax metering in many countries, teletax metering signals (ttx signals) are sent to the subscriber for billing purposes. a 12/16 khz sinusoidal metering burst has to be transmitted. as soon as metering pulses are applied to the subscriber line, they also divert to the transmit signal path which means that a notch filter has to block the 12/16 khz signal to prevent overloading the transmit a/d converter. in contrast to conventional line circuits, the duslic chip set generates the metering signal internally. the fact that the notch filter is integrated is one of the big advantages of duslic. dtmf a dtmf signal is used for touchtone signaling from a subscriber to the central office. each digit is represented by a pair of tones. duslic has an integrated dtmf decoder. the decoder is able to monitor the transmit and receive path for valid tone pairs and outputs the corresponding digital code for each dtmf tone pair. duslic also has an integrated dtmf generator comprising two tone generators. caller id frequency shift keying (fsk) modulator caller id is used to provide caller information to the subscriber during on-hook transmission. duslic has an integrated fsk modulator capable of sending caller id information. the caller id modulator complies with all requirements of itu-t recommendation v.23 and bell 202. lec (line echo cancellation) duslic contains an adaptive line echo cancellation unit for the cancellation of near end echos (up to 8 ms cancelable echo delay time). utd (universal tone detection) duslic has an integrated universal tone detection unit to detect special tones in the receive or transmit path (e.g. fax or modem tones). this is e.g. useful for activating the optimized filter coefficient set for modem transmission.
duslic functional description product overview 13 2000-11-09 preliminary figure 5 line circuit functions included in the duslic-s/-s2 figure 6 line circuit functions included in the duslic-e/-e2/-p ezm22020.emf v bat /v h switch control logic tip ring current sensor & offhook detection gain slic-s/-s2 v bat /v h switch control logic tip ring current sensor & offhook detection gain adc dac hardware filters programmable filters and gain a-law or -law pcm / iom-2 interface adc dac hardware filters programmable filters and gain a-law or -law prefilter postfilter prefilter postfilter controller pcm interface iom-2 interface serial c interface slicofi-2s/-2s2 channel a channel b slic-s/-s2 interface control both slicofi-2s/-2s2 channels one slicofi-2s/-2s2 channel ringing* ttx metering* supervision digital signal processing (dsp) compander dcctl * not available with slicofi-2s2 slic-s/-s2 ezm22007.emf v bat /v h switch control logic tip ring current sensor & offhook detection gain slic-e/-e2/-p v bat /v h switch control logic tip ring current sensor & offhook detection gain adc dac hardware filters programmable filters and gain a-law or -law pcm / iom-2 interface adc dac hardware filters programmable filters and gain a-law or -law prefilter postfilter prefilter postfilter controller pcm interface iom-2 interface serial c interface slicofi-2 channel a channel b slic-e/-e2/-p interface control both slicofi-2 channels one slicofi-2 channel ringing level metering ttx metering cid generation dtmf supervision digital signal processing (dsp) compander dcctl utd lec slic-e/-e2/-p
duslic functional description product overview 14 2000-11-09 preliminary 2.2 dc feeding analog telephones need a dc current in the off-hook state. ac speech signals in the receive and transmit directions are superimposed on this dc current. once the off-hook state has been detected, the slic must supply a dc current to the subscriber line. the current is typically in the range of 14 to 40 ma (for duslic programming capabilities see table 2 ), depending on local country specifications. conventional linecard solutions require additional hardware to adjust the dc feed current to meet different country specifications. by contrast, dc feeding with the slicofi-2x is fully programmable by using the software coefficients depicted in table 2 . special digital filter technology offers an extremely cost- effective solution that is far more flexible than analog dc feeding circuits. the dc feeding characteristic in slicofi-2 is programmed using software coefficients. figure 7 shows the signal paths for dc feeding between the slics and slicofi-2x : figure 7 signal paths - dc feeding acp dcpb dcnb dcp dcn slic channel a slicofi-2x pcm out (data upstream) pcm in (data downstream) dcpa it il itaca ila ita vcm vcmita dcna dcp dcn slic channel b it il itacb ilb itb vcm vcmitb ring tip ring tip acpb acnb acn acpa acna acp acn pcm or iom-2 interface r ilb r it1b r it2b c itb r ila r it1a r it2a c ita transmit path receive path c vcmita c vcmitb transmit receive ezm140374.emf
duslic functional description product overview 15 2000-11-09 preliminary 2.2.1 dc characteristic feeding zones the duslic dc feeding characteristic has three different zones: the constant current zone, the resistive zone and the constant voltage zone. a voltage reserve v res (see chapter 2.2.7 ) can be selected to avoid clipping the high level ac signals (e.g. ttx) and to take into account the voltage drop of the slic. the dc feeding characteristic is shown in figure 8 . figure 8 dc feeding characteristic the simplified diagram shows the constant current zone as an ideal current source with an infinite internal resistance, while the constant voltage zone is shown as an ideal voltage source with an internal resistance of 0 ? . for the specification of the internal resistances see chapter 2.2.5 ezm14017.emf i tip/ring i 0 constant voltage zone necessary voltage reserve v res |v bat | v tip/ring resistive zone constant current zone
duslic functional description product overview 16 2000-11-09 preliminary 2.2.2 constant current zone in the off-hook state, the feed current must usually be kept at a constant value independent of load (see figure 9 ). the slic senses the dc current and supplies this information to slicofi-2x via the it pin (input pin for dc control). slicofi-2x compares the actual current with the programmed value and adjusts the slic drivers as necessary. i tip/ring in the constant current zone is programmable from 0 to 32 ma or 0 to 50 ma depending on the used slic version. figure 9 constant current zone depending on the load, the operating point is determined by v tip/ring between the tip and ring pins. the operating point is calculated from: v tip/ring = r load i tip/ring where r load = r pre + r line + r phone,off-hook r pre = r prot + r stab (see figure 52 , page 98 ). the lower the load resistance r load , the lower the voltage between the tip and ring pins. a typical value for the programmable feeding resistance in the constant current zone is about r i =10k ? (see table 2 ). ezm14016.emf i tip/ring i 0 v res |v bat | v tip/ring r load r k12 r i
duslic functional description product overview 17 2000-11-09 preliminary 2.2.3 resistive zone the programmable resistive zone r k12 of duslic provides extra flexibility over a wide range of applications. the resistive zone is used for very long lines where the battery is incapable of feeding a constant current into the line. the operating point in this case crosses from the constant current zone for low and medium impedance loops to the resistive zone for high impedance loops (see figure 10 ). the resistance of the zone r k12 is programmable from r v to 1000 ? . figure 10 resistive zone ezm14035.emf i tip/ring i 0 v res |v bat | v tip/ring r load r k12 r i
duslic functional description product overview 18 2000-11-09 preliminary 2.2.4 constant voltage zone the constant voltage zone (see figure 11 ) is used in some applications to supply a constant voltage to the line. in this case v tip/ring = v lim is constant and the current depends on the load between the tip and ring pin. v lim is set by the duslicos software. in the constant voltage zone the external resistors r pre = r prot + r stab necessary for stability and protection define the resistance r v seen at the ring and tip wires of the application. figure 11 constant voltage zone ezm14036.emf i tip/ring i 0 v res |v bat | v tip/ring r load r k12 v lim
duslic functional description product overview 19 2000-11-09 preliminary 2.2.5 programmable voltage and current range of dc characteristic in the above chapters the idealized dc characteristics were shown. a detailed description is given in figure 12 . figure 12 dc characteristic (detailed description) the programmable range of the parameters r i , i 0 , i k1 , v k1 , r k12 and v lim is given in table 2 : table 2 dc characteristic symbol programmable range condition r i 1.8 k ? ? 40 k ? ? i 0 0 ? 32 ma only for duslic-s, duslic-e, duslic-p 0 ? 50 ma only for duslic-s2, duslic-e2 i k1 0 ? 32 ma only for duslic-s, duslic-e, duslic-p 0 ? 50 ma only for duslic-s2, duslic-e2 v k1 0 ? 50 v ? v k1 < v lim ? i k1 r k12 only ( v k1 , i k1 ) v k1 < v lim ? i k1 r v v k1 > v lim ? i k1 r k12 ( v k1 , i k1 ) and ( v k2 , i k2 ) r k12 r v ? 1000 ? ? v lim 0 ? 50 v ? v lim > v k1 + i k1 r k12 only ( v k1 , i k1 ) ezm22009.wmf i tip/ring i 0 v lim v tip/ring v k2 v k1 i k1 i k2 r i r k12 r v = r pre = r prot + r stab 1 2
duslic functional description product overview 20 2000-11-09 preliminary 2.2.6 slic power dissipation the power dissipation in the slic can be estimated by the power dissipation in the output stages (see chapter 3.5.3 ). the power dissipation can be calculated from: p slic ( v bat ? v tip/ring ) i tip/ring figure 13 power dissipation i tip/ring i lim v bat v tip/ring slic output stage power dissipation constant current zone slic output stage power dissipation constant voltage zone ezm14021.wmf
duslic functional description product overview 21 2000-11-09 preliminary 2.2.7 necessary voltage reserve to avoid clipping ac speech signals as well as ac metering pulses, a voltage reserve v res (see figure 8 ) has to be provided. v res =| v bat | ? v lim (see page 18 ) v bat is the selected battery voltage, which can be depending on the mode either v bath , v batl , ( v hr ? v bath ) for slic-s/-s2/-e/-e2 or v bath , v batl , ? v batr for slic-p. v res consists of: voltage reserve of the slic output buffers: this voltage drop depends on the output current through the tip and ring pins. for a standard output current of 25 ma, this voltage reserve is a few volts (see table 14 ). voltage reserve for ac speech signals: max. signal amplitude (example 2 v) voltage reserve for ac metering pulses: the ttx signal amplitude v ttx depends on local specifications and varies from 0.1 vrms to several vrms at a load of 200 ? . to obtain v ttx = 2 vrms at a load of 200 ? and r pre =50 ? ( r pre = r prot + r stab , see figure 51 , page 97 ), 3 vrms = 4.24 vpeak are needed at the slic output. therefore a v res value of 10.24 v must be selected (= 4 v (slic drop for peak current of dc and speech and ttx) + 2 v (ac speech signals) + 4.24 v (ttx-signal)). figure 14 ttx voltage reserve schematic r pre slic r pre 200 ? v ttx ezm14032.wmf
duslic functional description product overview 22 2000-11-09 preliminary 2.2.8 extended battery feeding if the battery voltage is not sufficient to supply the minimum required current through the line even in the resistive zone, the auxiliary positive battery voltage can be used to expand the voltage swing between tip and ring. with this extended supply voltage v hr (duslic-s/-s2/e/-e2) respectively v batr (duslic-p), it is possible to supply the constant current for long lines. figure 15 shows the dc feeding impedances r max,acth in acth mode and r max,actr in actr mode (for acth and actr modes see chapter 3.1 ). figure 15 dc feeding characteristics (acth, actr) ezm23019.emf |v hr ? v bath | 1) |v bath | v tip/ring r max i k1 i tip/ring acth normal mode actr extended battery feeding mode r max, actr v k1, actr v k1 r k12, actr r k12 |v batr | 2) 1) duslic-s/-s2/-e/-e2, 2) duslic-p v lim v lim, actr
duslic functional description product overview 23 2000-11-09 preliminary 2.3 ac transmission characteristics slicofi-2x uses either an iom-2 or a pcm digital interface. in receive direction, slicofi-2x converts pcm data from the network and outputs a differential analog signal (acp and acn) to the slic, that amplifies the signal and applies it to the subscriber line. in transmit direction, the transversal (it) and longitudinal (il) currents on the line are sensed by the slic and fed to the slicofi-2x . a capacitor separates the transversal line current into dc (it) and ac (itac) components. as itac is the sensed transversal (also called metallic) current on the line, it includes both the receive and transmit components. slicofi-2x separates the receive and transmit components digitally, via a transhybrid circuit. figure 16 shows the signal paths for ac transmission between the slics and slicofi-2x : figure 16 signal paths - ac transmission the signal flow within the slicofi-2x for one voice channel is shown in figure 17 by the following schematic circuitry. with the exception of a few analog filter functions, signal processing is performed digitally in the slicofi-2x . ezm140373.emf acp dcpb dcnb dcp dcn slic channel a slicofi-2x dcpa it il itaca ila ita vcm vcmita dcna dcp dcn slic channel b it il itacb ilb itb vcm vcmitb ring tip ring tip acpb acnb acn acpa acna acp acn pcm or iom-2 interface r ilb r it1b r it2b c itb r ila r it1a r it2a c ita transmit path receive path c vcmita c vcmitb pcm out (data upstream) pcm in (data downstream) transmit receive
duslic functional description product overview 24 2000-11-09 preliminary figure 17 signal flow in voice channel (a) 2.3.1 transmit path the current sense signal (itac) is converted to a voltage by an external resistor. this voltage is first filtered by an anti-aliasing filter (pre-filter), that stops producing noise in the voiceband from signals near the a/d sampling frequency. a/d conversion is done by a 1-bit sigma-delta converter. the digital signal is down-sampled further and routed through programmable gain and filter stages. the coefficients for the filter and gain stages can be programmed to meet specific requirements. the processed digital signal goes through a compander (cmp) that converts the voice data into a-law or -law codes. a time slot assignment unit outputs the voice data to the programmed time slot. slicofi-2x can also operate in 16-bit linear mode for processing uncompressed voice data. in this case, two time slots are used for one voice channel. 2.3.2 receive path the digital input signal is received via the iom-2 or pcm interface. expansion (exp), pcm low-pass filtering, frequency response correction and gain correction are performed by the dsp. the digital data stream is up-sampled and converted to a corresponding analog signal. after smoothing by post-filters in the slicofi-2x , the ac signal is fed to the slic, where it is superimposed on the dc signal. the dc signal has been processed in a separate dc path. a ttx signal, generated digitally within slicofi-2x , can also be added. ezm14026.emf pre- filter post- filter + teletax generator itac acp acn + amplify receive frequency response receive d/a ttx filter a/d amplify transmit + frequency response transmit cmp impedance matching transhybrid filter exp pcm out pcm in channel a channel b tg 1 tg 2 impedance matching slicofi-2x + cid generation dtmf detection transmit receive
duslic functional description product overview 25 2000-11-09 preliminary 2.3.3 impedance matching the slic outputs the voice signal to the line (receive direction) and also senses the voice signal coming from the subscriber. the ac impedance of the slic and the load impedance need to be matched in order to maximize power transfer and minimize two- wire return loss. the two-wire return loss is a measure of the impedance matching between a transmission line and the ac termination of duslic. the actual line impedance however can vary considerably, depending on loop length, loaded/unloaded lines, cable type, etc. reference networks have therefore been defined to represent the average characteristics of a country's local loop. these reference networks differ from country to country and need to be reflected by the linecard being used in that country. impedance matching is done digitally within slicofi-2x by providing three impedance matching feedback loops. the loops feed the transmit signal back to the receive signal simulating the programmed impedance through the slic. when calculating the feedback filter coefficients, the external resistors between the protection circuit and slic ( r pre = r prot + r stab , see figure 51 , page 97 ) have to be taken into account. the impedance can be programmed to any appropriate real and complex values shown in the nyquist diagram figure 18 . this means that the device can be adapted to requirements anywhere in the world without requiring the hardware changes that are necessary with conventional line card designs. figure 18 nyquist diagram ezm22019.emf 0 -200 -400 -600 200 400 600 800 1000 1200 1400 re z l im z l possible values for line impedance
duslic functional description product overview 26 2000-11-09 preliminary 2.3.4 transhybrid balance digital switching systems can handle voice data only if receive and transmit data are separated on distinctive channels. the analog voice signal on the local loop is 2-wire full duplex, so it needs to be converted from 2-wire to 4-wire (2 wires each for receive and transmit). the circuitry, that performs this task, is commonly referred to as a hybrid circuit (see figure 19 ) . figure 19 2/4-wire conversion in the hybrid circuit to prevent the receive voice signal being looped back (echoed) directly into the transmit voice path, the hybrid circuit has to separate the receive path signal from the transmit path signal. in contrast with conventional line card designs, echo cancellation is implemented digitally within slicofi-2x . figure 19 shows the transhybrid loop that subtracts the receive signal from the transmit signal. the hybrid function is also dependent on loop condition. it has to be adapted to country-specific requirements. in conventional line card designs, this is done by external hardware adaptation. with slicofi-2x , adaptation is simply a matter of updating coefficients. no hardware changes are necessary. hybrid circuit 2-wire transmit 2-wire receive 2-wire subscriber line transmit signal receive signal unwanted echo path ezm14012.wmf
duslic functional description product overview 27 2000-11-09 preliminary 2.4 ringing with the 170 v technology used for the slic, a ringing voltage of up to 85 vrms can be generated on-chip without the need for an external ringing generator. the slicofi-2x generates a sinusoidal ringing signal that causes less noise and cross-talk in neighboring lines than a trapezoidal ringing signal. the ringing frequency is programmable from 3 to 300 hz. the advantage over traditional applications with a central ringing generator and decoupling resistors (approx. r = 400 ?) is the very low source impedance of duslic (approx. 60 ? without r prot ). thus it is possible to supply the subscriber line with a lower ringing voltage from the slic. slic-e/-e2, slic-s/-s2 and slic-p support different ringing methods (see chapter 2.4.3 ). 2.4.1 ringer load a typical ringer load can be thought of as a resistor in series with a capacitor. ringer loads are usually described as a ren (ringer equivalence number) value. ren is used to describe the on-hook impedance of the terminal equipment, and is actually a dimensionless ratio that reflects a certain load. ren definitions vary from country to country. a commonly used ren is described in fcc part 68 that defines a single ren as either 5 k ? , 7 k ? or 8 k ? of ac impedance at 20 hz. the impedance of an n-multiple ren is equivalent to parallel connection of n single rens. in this manual, all references to ren assume the 7 k ? model. for example, a 1 ren and 5 ren load would be: figure 20 typical ringer loads of 1 and 5 ren used in us 1 ren 5 ren 8 f 40 f 1386 ? 6930 ? ezm14024.wmf
duslic functional description product overview 28 2000-11-09 preliminary 2.4.2 ring trip once the subscriber has gone off-hook, the ringing signal must be removed within a specified time, and power must start feeding to the subscriber's phone. there are two ring trip methods: dc ring trip detection most applications with duslic are using dc ring trip detection. by applying a dc offset together with the ringing signal, a transversal dc loop current starts to flow when the subscriber goes off-hook. this dc current is sensed by the slic and in this way used as an off-hook criterion. the slic supplies this information to the slicofi-2x at the it pin. the slicofi-2x continuously integrates the sensed line current i trans over one ringer period. this causes the integration result to represent the dc component of the ring current. if the dc current exceeds the programmed ring trip threshold, slicofi-2x generates an interrupt. ring trip is reliably detected and reported within two ring signal periods. the ringing signal is switched off automatically at zero crossing by the slicofi-2x . the threshold for the ring trip dc current is set internally in slicofi-2x , programmed via the digital interface. the dc offset for ring trip detection can be generated by the duslic chip set and the internal ring trip function can be used, even if an external ringing generator is used. ac ring trip detection: for short lines (< 1 k ? loop length) and for low-power applications, the dc offset can be avoided to reduce the battery voltage for a given ring amplitude. ring trip detection is done by rectifying the ring current i trans , integrating it over one ringer period and comparing it to a programmable ac ring trip threshold. most applications with duslic are using dc ring trip detection, which is more reliable than ac ring trip detection.
duslic functional description product overview 29 2000-11-09 preliminary 2.4.3 ringing methods there are two methods of ringing: balanced ringing (bridged ringing) unbalanced ringing (divided ringing) the resulting ringing amplitude in balanced mode is twice the amplitude of v t or v r . this is an advantage over the unbalanced mode because the ringing generator circuit in balanced mode has to handle voltages of only half the amplitude to generate the same amplitude of ringing signal. the slic process technology used is capable of generating balanced ringing signals with amplitudes of up to 85 v rms . table 3 unbalanced versus balanced ringing unbalanced ringing: balanced ringing: the ringing signal is applied to only either the tip or ring line, whereas gnd is applied to the other line. an opposite-phase ringing signal is applied to both tip and ring lines. the resulting ringing signal is the differential signal between tip and ring line. v ring = v t ? v r v t = v ac(t) + v dc,ring /2 v r = ? v ac(t) ? v dc,ring /2 if v t = ? v r then v ring =2* v ac(t) + v dc,ring slic ezm140311.wmf slic ezm140312.wmf gnd v dc,ring v ring ezm140313.wmf v dc,ring v r v t bgnd v tp v rp ezm140317.wmf
duslic functional description product overview 30 2000-11-09 preliminary internal balanced ringing generally offers more benefits compared to unbalanced ringing: balanced ringing produces much less longitudinal voltage, which results in a lower amount of noise coupled into adjacent cable pairs by using a differential ringing signal, lower supply voltages become possible the phone itself cannot distinguish between balanced and unbalanced ringing. where unbalanced ringing is still used, it is often simply a historical leftover. for a comparison between balanced and unbalanced ringing see also ansi document t1.401-1993. additionally, integrated ringing with the duslic offers the following advantages: internal ringing (no need for external ringing generator and relays) reduction of board space because of much higher integration and fewer external components programmable ringing amplitude, frequency and ringing dc offset without hardware changes programmable ring trip thresholds switching off the ringing signal at zero-crossing
duslic functional description product overview 31 2000-11-09 preliminary 2.4.4 duslic ringing options application requirements differ with regard to ringing amplitudes, power requirements, loop length and loads. the duslic options include three different slics to select the most appropriate ringing methods (see table 4 ): slic-s allows balanced ringing up to 45 vrms and is dedicated for short loop or pbx applications. for slic-s2 only external ringing is provided. slic-e/-e2 allows balanced ringing up to 85 vrms and can therefore be used in systems with higher loop impedance. the low-power slic-p is optimized for power-critical applications (e.g. intelligent isdn network termination). internal ringing can be used up to 85 vrms balanced or 50 vrms unbalanced. table 4 ringing options with slic-s, slic-e/-e2 and slic-p slic version/ ringing facility, battery voltages slic-s peb 4264 slic-e/-e2 peb 4265 peb 4265-2 slic-p peb 4266 internal balanced ringing max. voltage in vrms (sinusoidal) with 20 v dc used for ring trip detection 45 vrms 85 vrms 85 vrms dc voltage for balanced ringing 1) 1) in most applications 20 v dc are sufficient for reliable ring trip detection. a higher dc voltage will reduce the achievable maximum ringing voltage. for short loops 10 v dc may be sufficient. programmable typ. 0 ? 50 v programmable typ. 0 ? 50 v programmable typ. 0 ? 50 v internal unbalanced ringing max. voltage in vrms (sinusoidal) no no 50 vrms dc voltage for unbalanced ringing no no v batr /2 required slic supply voltages for maximum ringing amplitude (typically) v dd =5v, v bath = ? 54 v, v hr =36v v dd =5v, v bath = ? 70 v, v hr =80v v dd =5v or 3.3 v, v bath = ? 70 v, v batr = ? 150 v number of battery voltages for power saving 2 ( v batl & v bath ) 2 ( v batl & v bath ) 2 (when internal ringing is used) 3 (when external ringing is used)
duslic functional description product overview 32 2000-11-09 preliminary for lowest power applications where external ringing is preferred, three different battery voltages ( v batr , v bath , v batl ) can be used for optimizing the power consumption of the application. 1) slic-e/-e2 and slic-p differ in supply voltage configuration and the ring voltages at tip and ring v t and v r . external ringing is supported by both slic ? s. external ringing support by duslic external ringing requires an external ring signal generator and a ttl compatible zero crossing signal which has to be applied to the rsync pin of the slicofi-2x . the ring relay is controlled by the io1 pin. due to the high current drive capability of the io1 ouput, no additional relay driver is necessary. the relay can be switched: synchronous: the ring relay is switched at the zero crossing of the external ringing frequency. asynchronous : the ring relay is switched immediately with the ring command. 1) in this case v batr is typically used for the on-hook state, while v bath and v batl are used for optimized feeding of different loop length in the off-hook state.
duslic functional description product overview 33 2000-11-09 preliminary 2.4.5 internal balanced ringing via slics slic-e/-e2 and slic-p support internal balanced ringing up to v ring,rms =85vrms, slic-s support balanced ringing up to v ring,rms =45vrms. the ringing signal is generated digitally within slicofi-2x 1) . figure 21 balanced ringing via slic-e/-e2, slic-s and slic-p in ringing mode, the dc feeding regulation loop is not active. a programmable ring offset voltage is applied to the line instead. during ring bursts, the ringing dc offset and the ringing signal are summed digitally within slicofi-2x in accordance with the programmed values. this signal is then converted to an analog signal and applied to the slic. the slic amplifies the signal and supplies the line with ringing voltages up to 85 vrms. in balanced ringing mode, the slic uses an additional supply voltage v hr for slic-e/-e2/-s and v batr for slic-p. the total supply span is now v hr ? v bath for slic-e/-e2/-s and v batr for slic-p. the maximum ringing voltage that can be achieved is: for slic-e/-e2/-s: v ring,rms =( v hr ? v bath ? v drop, rt ? v dc,ring )/1.41 for slic-p: v ring,rms =( ? v batr ? v drop,rt ? v dc,ring )/1.41 where: v drop,rt = v drop,t + v drop,r 1) slicofi-2s2 supports only external ringing ezm140315.emf v dc,ring v r v t v drop,t v drop,r v ring,pp = v tp - v rp v batr bgnd slic-e slic-e2 slic-s slic-p v bath v hr v tp v rp
duslic functional description product overview 34 2000-11-09 preliminary with the duslic ringing voltages up to 85 vrms sinusoidal can be applied, but also trapezoidal ringing can be programmed. the slic senses the transversal current on the line and supplies this information to the slicofi-2x at the it pin. the it current is monitored by slicofi-2x . if the dc current exceeds the programmed ring trip threshold, slicofi-2x generates an interrupt. ring trip is reliably detected and reported within two ring signal periods. the ringing signal is switched off during zero crossing by the slicofi-2x . for a detailed application diagram of internal balanced ringing refer to the chapter on "application circuits" (see figure 50 , page 96 ). 2.4.6 internal unbalanced ringing with slic-p the internal unbalanced ringing together with slic-p can be used for ringing voltages up to 50 vrms. the slicofi-2 integrated ringing generator is used and the ringing signal is applied to either the tip or ring line. ringing signal generation is the same as described above for balanced ringing. since only one line is used for ringing, technology limits the ringing amplitude to about half the value of balanced ringing, to maximum 50 vrms. figure 22 unbalanced ringing signal the above diagram shows an example with the ring line used for ringing and the tip line fixed at ? v drop,t which is the drop in the output buffer of the tip line of slic-p (typ. < 1 v). the ring line has a fixed dc voltage of v batr /2 used for ring trip detection. the maximum ringing voltage is: v ring,rms =( ? v batr ? v drop,r,vbatr ? v drop,t )/2.82 when the called subscriber goes off-hook, a dc path is established from the ring to the tip line. the dc current is recognized by the slicofi-2 because it monitors the it pin. an interrupt indicates ring trip if the line current exceeds the programmed threshold. v batr / 2 v t v r v ring,p v dc,ring v drop,r,vbatr v drop,r,bgnd v drop,t v drop,t v batr bgnd v ring = v r ezm140316.wmf
duslic functional description product overview 35 2000-11-09 preliminary the same hardware can be used for integrated balanced or unbalanced ringing. the balanced or unbalanced modes are configured by software. the maximum achievable amplitudes depend on the values selected for v batr . in both balanced and unbalanced ringing modes, slicofi-2 automatically applies and removes the ringing signal during zero-crossing. this reduces noise and cross-talk to adjacent lines. 2.4.7 external unbalanced ringing slicofi-2x supports external ringing for higher ringing voltage requirements with all slics. in this case duslics integrated ring trip functionality is used. for a detailed application diagram of unbalanced ringing see figure 53 ( page 100 ) and figure 54 ( page 101 ). since high voltages are involved, an external relay should be used to switch the ring line off and to switch the external ringing signal together with a dc voltage to the line. the dc voltage has to be applied for the internal ring trip detection mechanism which operates for external ringing in the same way as for internal ringing. the slicofi-2x has to be set to the external ringing mode. a synchronization signal of the external ringer is applied to the slicofi-2x via the rsync pin. the external relay is switched on or off synchronously to this signal via the io1 pin of the slicofi-2x according to the actual mode of the duslic. an interrupt is generated if the dc current exceeds the programmed ring trip threshold.
duslic functional description product overview 36 2000-11-09 preliminary 2.5 signaling (supervision) signaling in the subscriber loop is monitored internally by the duslic chip set. supervision is performed by sensing the longitudinal and transversal line currents on the ring and tip wires. the scaled values of these currents are generated in the slic and fed to the slicofi-2x via the it and il pins. transversal line current: i trans =( i r + i t )/2 longitudinal line current: i long =( i r ? i t )/2 where i r , i t are the loop currents on the ring and tip wires. off-hook detection loop start signaling is the most common type of signaling. the subscriber loop is closed by the hook switch inside the subscriber equipment. in active mode, the resulting transversal loop current is sensed by the internal current sensor in the slic. the it pin of the slic indicates the subscriber loop current to the slicofi-2x . external resistors ( r it1 , r it2, see figure 50 ) convert the current information to a voltage on the ita (or itb) pin. the analog information is first converted to a digital value. it is then filtered and processed further which effectively suppresses line disturbances. if the result exceeds a programmable threshold, an interrupt is generated to indicate off-hook detection. in sleep/power down mode (pdrx) a similar mechanism is used. in this mode, the internal current sensor of the slic is switched off to minimize power consumption. the loop current is therefore fed and sensed through 5 k ? resistors integrated in the slic. the information is made available on the it pin and interpreted by the slicofi-2x . ? in sleep mode, the analog information is fed to an analog comparator integrated in the slicofi-2x who directly indicates off-hook. ? in power down mode, the slicofi-2x converts the analog information to a digital value. it is then filtered and processed further which effectively suppresses line disturbances. if the result exceeds a programmable threshold, an interrupt is generated to indicate off-hook detection. in applications using ground start signaling, duslic can be set in the ground start mode. in this mode, the tip wire is switched to high impedance mode. ring ground detection is performed by the internal current sensor in the slic and transferred to the slicofi-2x via the it pin.
duslic functional description product overview 37 2000-11-09 preliminary ground key detection the scaled longitudinal current information is transferred from the slic via the il pin and the external resistor r il to slicofi-2x . this voltage is compared with a fixed threshold value. for the specified r il (1.6 k ? , see application circuit figure 50 ) this threshold corresponds to 17 ma (positive and negative). after further post-processing, this information generates an interrupt and ground key detection is indicated. the post-processing is performed to guarantee ground key detection, even if longitudinal ac currents with frequencies of 16 2 / 3 , 50 or 60 hz are superimposed. the time delay between triggering the ground key function and registering the ground key interrupt will in most cases ( f = 50 hz, 60 hz) be less than 40 ms. in power down mode, the slic's internal current sensors are switched off and ground key detection is disabled. 2.6 metering there are two different metering methods: metering by sinusoidal bursts with either 12 or 16 khz or polarity reversal of tip and ring. 2.6.1 metering by 12/16 khz sinusoidal bursts the required amplitude of the sinusoidal 12 or 16 khz metering signals varies from a few hundred millivolts to several v rms , depending on the country specifications and the application (long loop or short loop application). these signals are superimposed onto the speech signal. as soon as metering pulses are applied to the subscriber line, they also divert to the transmit signal path which means that a notch filter has to block the 12/ 16 khz signal, to prevent overloading the transmit a/d converter. in contrast to conventional line circuits, the duslic chip set generates the metering signal internally. the fact that the adaptive notch filter is integrated is one of the big advantages of duslic. teletax metering and filtering to satisfy worldwide application requirements, slicofi-2/-2s 1) offers integrated metering injection of either 12 or 16 khz signals with programmable amplitudes. slicofi-2/-2s also has an integrated adaptive ttx notch filter and can switch the ttx signal to the line in a smooth way. when switching the signal to the line, the switching noise is less than 1 mv. figure 23 shows ttx bursts at certain points of the signal flow within slicofi-2/-2s. 1) metering is not available with slicofi-2s2
duslic functional description product overview 38 2000-11-09 preliminary figure 23 teletax injection and metering the integrated, adaptive ttx notch filter guarantees an attenuation of > 40 db. no external components for filtering ttx bursts are required. ezm14027.emf slicofi-2/-2s a/d d/a d / a ttx adaptive filter ttx gen. im filter + slic-e/-e2 slic-s slic-p x1 - y receive path transmit path z l /2 z l /2 + +
duslic functional description product overview 39 2000-11-09 preliminary 2.6.2 metering by polarity reversal slicofi-2/-2s also supports metering by changing the actual polarity of the voltages on the tip/ring lines. metering with polarity reversal is usually used for pay phones (coin lines). every time the polarity changes, a magnet in the pay phone releases a coin. 2.6.2.1 soft reversal some applications require a smooth polarity reversal (soft reversal), as shown in figure 24 . soft reversal helps to prevent negative effects like non-required ringing. soft reversal is deactivated by the soft-dis bit in register bcr2. figure 24 soft reversal (example for open loop) start: the soft ramp starts by setting the revpol bit in register bcr1 to 1. the dc characteristic is switched off. sr-end1: at the soft reversal end one point, the dc characteristic is switched on again. programmable by the duslicos software, e.g. ? u/8. sr-end2: at the soft reversal end two point, the soft ramp is switched off. programmable by the duslicos software, e.g. 1/16*sr-end1. soft-dis = 1 immediate reversal is performed (hard reversal) soft-dis = 0 soft reversal is performed. transition time (time from start to sr-end1, see figure 24 ) is programmable by cram-coefficients, default value 80 ms. 0 50 100 150 200 250 -25 -20 -15 -10 -5 0 5 10 15 20 25 t [ms] v tip/ring [v] sr-end1 ? u ? u/8 sr-end2 = 1/16*sr-end1 start ezm14038.wmf
duslic functional description product overview 40 2000-11-09 preliminary 2.7 duslic enhanced signal processing capabilities the signal processing capabilities described in this chapter are realized by an enhanced digital signal processor (edsp) except for dtmf generation. each function can be individually enabled or disabled for each duslic channel. therefore power consumption can be reduced according to the needs of the application. figure 25 shows the ac signal path for duslic with the adcs and dacs, impedance matching loop, thranshybrid filter, gain stages and the connection to the edsp. figure 25 duslic ac signal path 2.7.1 dtmf generation and detection 1) dual tone multi-frequency (dtmf) is a signaling scheme using voice frequency tones to signal dialing information. a dtmf signal is the sum of two tones, one from a low group (697 - 941 hz) and one from a high group (1209 - 1633 hz), with each group containing four individual tones. this scheme allows 16 unique combinations. ten of these codes represent the numbers from zero through nine on the telephone keypad, the remaining six codes (*, #, a, b, c, d) are reserved for special signaling. the buttons are arranged in a matrix, with the rows determining the low group tones, and the columns determining the high group tone for each button. in all slicofi-2x codec versions the 16 standard dtmf tone pairs can be generated independently in each channel via two integrated tone generators. alternatively the frequency and the amplitude of the tone generators can be programmed individually via the digital interface. each tone generator can be switched on and off. the generated dtmf tone signals meet the frequency variation tolerances specified in the itu-t q.23 recommendation. 1) dtmf detection only available for duslic-e/-e2/-p edsp cmp exp dtmf lec ax1 hpx1 cid + ar1 hpr1 tg lpx frx lpr frr th ax2 hpx2 ar2 hpr2 im3 ttxa + dac dac adc im2 + + im1 + xout rin vin vout ttxg utd utd switch duslic_0005_acsignal_path.emf
duslic functional description product overview 41 2000-11-09 preliminary both channels (a and b) of slicofi-2 1) have a powerful built-in dtmf decoder that will meet most national requirements. the receiver algorithm performance meets the quality criteria for central office/exchange applications. it complies among others with the requirements of itu-t q.24, bellcore gr-30-core (tr-nwt-000506) and deutsche telekom network (bapt 223 zv 5, approval specification of the federal office for post and telecommunications, germany). the performance of the algorithm can be adapted according to the needs of the application via the digital interface (detection level, twist, bandwidth and center frequency of the notch filter). table 5 shows the performance characteristics of the dtmf decoder algorithm: 1) dtmf detection only available for duslic-e/-e2/-p table 5 performance characteristics of the dtmf decoder algorithm characteristic value notes 1 valid input signal detection level ? 48 to 0 dbm0 programmable 2 input signal rejection level ? 5 db of valid signal detection level ? 3 positive twist accept < 8 db programmable 4 negative twist accept < 8 db programmable 5 frequency deviation accept < (1.5% + 4 hz) and <1.8% related to center frequency 6 frequency deviation reject > 3% related to center frequency 7 dtmf noise tolerance (could be the same as 14) ? 12 db db referenced to lowest amplitude tone 8 minimum tone accept duration 40 ms ? 9 maximum tone reject duration 25 ms ? 10 signaling velocity 93 ms/digit ? 11 minimum inter-digit pause duration 40 ms ? 12 maximum tone drop-out duration 20 ms ? 13 interference rejection 30 hz to 480 hz for valid dtmf recognition level in frequency range 30 hz ? 480 hz level of dtmf frequency + 22 db db referenced to lowest amplitude tone
duslic functional description product overview 42 2000-11-09 preliminary in the event of pauses < 20 ms: if the pause is followed by a tone pair with the same frequencies as before, this is interpreted as drop-out. if the pause is followed by a tone pair with different frequencies and if all other conditions are valid, this is interpreted as two different numbers. dtmf decoders can be switched on or off individually to reduce power consumption. in normal operation, the decoder monitors the tip and ring wires via the itac pins (transmit path). alternatively the decoder can be switched also in the receive path. on detecting a valid dtmf tone pair, slicofi-2 generates an interrupt via the appropriate int pin and indicates a change of status. the dtmf code information is provided by a register which is read via the digital interface. the dtmf decoder also has excellent speech-rejection capabilities and complies with bellcore tr-tsy-000763. the algorithm has been fully tested with the speech sample sequences in the series-1 digit simulation test tapes for dtmf decoders from bellcore. 14 gaussian noise influence signal level ? 22 dbm0, snr = 23 db error rate better than 1 in 10000 ? 15 pulse noise influence impulse noise tape 201 according to bellcore tr-tsy-000762 error rate better than 14 in 10000 measured with dtmf level ? 22 dbm0 impulse noise ? 10 dbm0 and ? 12 dbm0 table 5 performance characteristics of the dtmf decoder algorithm (cont ? d) characteristic value notes
duslic functional description product overview 43 2000-11-09 preliminary 2.7.2 caller id generation (only duslic-e/-e2/-p) a generator to send calling line identification (caller id, cid) is integrated in the duslic chip set. caller id is a generic name for the service provided by telephone utilities that supply information like the telephone number or the name of the calling party to the called subscriber at the start of a call. in call waiting, the caller id service supplies information about a second incoming caller to a subscriber already busy with a phone call. in typical caller id (cid) systems, the coded calling number information is sent from the central exchange to the called phone. this information can be shown on a display on the subscriber telephone set. in this case, the caller id information is usually displayed before the subscriber decides to answer the incoming call. if the line is connected to a computer, caller information can be used to search in databases and additional services can be offered. there are two methods used for sending cid information depending on the application and country-specific requirements: caller id generation using dtmf signaling (see chapter 2.7.1 ) caller id generation using fsk duslic contains dtmf generation units and fsk generation units which can be used for both channels simultaneously. duslic fsk generation different countries use different standards to send caller id information. the duslic chip set is compatible with the widely used standards bellcore gr-30-core, british telecom (bt) sin227, sin242 or the uk cable communications association (cca) specification tw/p&e/312. continuous phase binary frequency shift keying (fsk) modulation is used for coding which is compatible with bell 202 (see table 6 ) and itu-t v.23, the most common standards. slicofi-2 can be easily adapted to these requirements by programming via the microcontroller interface. coefficient sets are provided for the most common standards. table 6 fsk modulation characteristics characteristic itu-t v.23 bell 202 mark (logic 1) 1300 3 hz 1200 3 hz space (logic 0) 2100 3 hz 2200 3 hz modulation fsk transmission rate 1200 6 baud data format serial binary asynchronous
duslic functional description product overview 44 2000-11-09 preliminary the caller id data of the calling party can be transferred via the microcontroller interface into a slicofi-2 buffer register. the slicofi-2 will start sending the fsk signal when the cis-en bit is set and the cid-data buffer is filled up to cis-brs plus 1 byte. the data transfer into the buffer register is handled by a slicofi-2 interrupt signal. caller data is transferred from the buffer via the interface pins to the slic-e/-e2/-p and fed to the tip and ring wires. the caller id data bytes from cid-data buffer are sent lsb first. duslic offers two different levels of framing: a basic low-level framing mode all the data necessary to implement the fsk data stream ? including channel seizure, mark sequence and framing for the data packet or checksum ? has to be configured by firmware. slicofi-2 transmits the data stream in the same order in which the data is written to the buffer register. a high level framing mode the number of channel seizure and mark bits can be programmed and are automatically sent by the duslic. only the data packet information has to be written into the cid buffer. start and stop bits are automatically inserted by the slicofi-2. the example below shows signaling of cid on-hook data transmission in accordance with bellcore specifications. the caller id information applied on tip and ring is sent during the period between the first and second ring burst. figure 26 bellcore on-hook caller id physical layer transmission bellcore on-hook caller id physical layer transmission first ring burst channel seizure mark data packet second ring burst abc d efg more parameter messages more parameter bytes message type message lenght 1 parameter type parameter length parameter byte checksum parameter message parameter header parameter body message header message body message 1 message length equals the number of bytes to follow in the message body, excluding the checksum. a: 0.2-3 second ring burst. b: 0.5-1.5 seconds between first ring burst and start of data transmission. c: 300 alternating mark and space bits. d: 180 mark bits. c + d + e = 2.9 to 3.7 seconds. f: 200ms g: 1.8-3 second ring burst ezm14014.wmf
duslic functional description product overview 45 2000-11-09 preliminary 2.7.3 line echo cancelling (lec) (only duslic-e/-e2/-p) the duslic contains an adaptive line echo cancellation unit for the cancellation of near end echoes. with the adaptive balancing of the lec unit the transhybrid loss can be improved up to a value of about 50 db. the maximum echo cancellation time selectable is 8 ms. the line echo cancellation unit is especially useful in combination with the dtmf detection unit. in critical situations the performance of the dtmf detection can be improved. the duslic line echo canceller is compatible with applicable standards itu-t g.165 and g.168. an echo cancellation delay time of up to 8 ms can be programmed. the lec unit consists basically of an fir filter, a shadow fir filter, and a coefficient adaption mechanism between these two filters as shown in figure 27 . figure 27 line echo cancellation unit - block diagram the adaption process is controlled by the three parameters pow lecr (power detection level receive), deltap lec (delta power) and deltaq (delta quality). adaptation takes place only if both of the following conditions hold: 1. s lec,r >pow lecr 2. s lec,r ? s lec,tin >deltap lec with the first condition, adaptation to small signals can be avoided. the second condition avoids adaptation during double talk. the parameter deltap lec represents the echo loss provided by external circuitry. if the adaptation of the shadow filter is performed better than the adaption of the actual filter by a value of more than deltaq then the shadow filter coefficients will be copied to the actual filter. at the start of an adaption process the coefficients of the lec unit can be reset to default initial values or set to the old coefficient values. the coefficients may also be frozen. shadow fir filter copy coeff. fir filter adapt coeff. s lec,r s lec, tin s lec, tout duslic_0004_lecunit.emf
duslic functional description product overview 46 2000-11-09 preliminary 2.7.4 universal tone detection (utd) (only duslic-e/-e2/-p) each channel of the duslic has two universal tone detection units which can be used to detect special tones in the receive and transmit paths, especially fax or modem tones (e.g., see the modem startup sequence described in recommendation itu-t v.8). this allows the use of modem-optimized filter for v.34 and v.90 connections. if the duslic utd detects that a modem connection is about to be established, the optimized filter coefficients for the modem connection can be downloaded before the modem connection is set up. with this mechanism implemented in the duslic chip set, the optimum modem transmission rate can always be achieved. figure 28 shows the functional block diagram of the utd unit: figure 28 utd functional block diagram initially, the input signal is filtered by a programmable band-pass (center frequency f c and bandwidth f bw ). both the in-band signal (upper path) and the out-of-band signal (lower path) are determined, and the absolute value is calculated. both signals are furthermore filtered by a limiter and a low-pass. all signal samples (absolute values) below a programmable limit lev n (noise level) are set to zero and all other signal samples are diminished by lev n . the purpose of this limiter is to increase noise robustness. after the limiter stages both signals are filtered by a fixed low-pass. the evaluation logic block determines whether a tone interval or silence interval is detected and an interrupt is generated for the receive or transmit path. if the bandwidth parameter is programmed to a negative value, the utd unit can be used for the detection of silence intervals in the whole frequency range. the duslic utd unit is compatible with itu-t g.164. the utd is resistant to a modulation with 15 hz sinusoidal signals and a phase reversal but is not able to detect the 15 hz modulation and the phase reversal. ezm14061 s utd programmable band-pass |x| |x| + + limit limit lp lp evaluation logic
duslic functional description product overview 47 2000-11-09 preliminary 2.8 message waiting indication (only duslic-e/-e2/-p) message waiting is a function that can be required by pbx applications. a message waiting indication (mwi) lamp is activated indicating to the subscriber that a message has arrived. the duslic message waiting function uses a glow lamp at the subscriber phone. current does not flow through a glow lamp until the voltage reaches a threshold value of approximately 80 v. at this threshold, the neon gas in the lamp will start to glow. when the voltage is reduced, the current falls under a certain threshold and the lamp is extinguished. duslic has high-voltage slic technology (170 v) which is able to activate the glow lamp without any external components. the hardware circuitry is shown in figure 29 below. the figure shows a typical telephone circuit with the hook switch in the on-hook mode, together with the impedances for the on-hook (z r ) and off-hook (z l ) modes. figure 29 mwi circuitry with glow lamp the glow lamp circuit also requires a resistor (r mw ) and a lamp (mw lamp) built into the phone. when activated, the lamp must be able to either blink or remain on constantly . in non-duslic solutions the telephone ringer may respond briefly if the signal slope is too steep, which is not desirable. duslic ? s integrated ramp generator can be programmed to increase the voltage slowly, to ensure activating the lamp and not the ringer. z l r mw z r z l ac impedance z r ringer impedance r mw pre resistor message waiting mw lamp ezm14066.wmf
duslic functional description product overview 48 2000-11-09 preliminary 2.9 three-party conferencing each duslic channel has a three-party conferencing facility consisting of four pcm registers, adders and gain stages in the microprogram and the corresponding control registers (see figure 30 ). cascading duslic channels allows even multi-party conferencing. three-party conferencing is available in pcm/c-mode only. figure 30 conference block for one duslic channel note: g...gain stage (gain factor), x1-x4...pcm transmit channels, r1-r4...pcm receive channels, a, b, c, d, s...examples for voice data on pcm channels x1-x4, r1-r4 table 7 shows all possible three-party conferencing modes and the corresponding selection of the pcm transmit and receive channels x1 to x4 and r1 to r4 (see also figure 30 ). the timeslot assignment, the pcm-highway selection, the pcm line drivers and the behaviour of the conferencing facility itself are controled by various registers 1) . a programmable gain stage g is able to adjust the gain of the conferencing voice data (b, c, d, s) in a range of ? 6 db to + 3 db to prevent overload of the sum signals. 1) not to be explained in this document. + + + subscriber s pcm highways g g g conf_en = 0 1 0 conf_en = 0 0 1 subscribers pcm channel x4 x1 x3 x2 a r1 b r2 c r3 d r4 - - - ezm14069.emf x2 = (r3 ? r4)*g x3 = (r2 ? r4)*g x4 = (r2 ? r3)*g
duslic functional description product overview 49 2000-11-09 preliminary 2.9.1 conferencing modes pcm off after a reset, or in power down there is no communication via the pcm highways. also when selecting new timeslots it is recommended to switch off the pcm line drivers by setting the control bits to zero. pcm active this is the normal operating mode without conferencing. only the channels r1 and x1 are in use, and voice data are transferred from subscriber a to analog subscriber s and vice versa. external conference in this mode the slicofi-2 acts as a server for a three-party conference of subscribers b, c and d which may be controlled by any device connected to the pcm highways. the slicofi-2 channel itself can remain in power down mode to lower power consumption. external conference + pcm active like in external conference mode any external three-party conference is supported. at the same time an internal phone call is active using the channels r1 and x1. internal conference if the analog subscriber s is one of the conference partners, the internal conference mode will be selected. the partners (b, c) do not need any conference facility, since the slicofi-2 performs all required functions for them as well. table 7 conference modes receive pcm channels transmit pcm channels mode r1 r2 r3 r4 x1 x2 x3 x4 subscriber s pcm off off off off off off pcm active asoffoffoffa external conference bcdoffg (b+d) g (c+d) g (b+c) off external conference + pcm active abcdsg (b+d) g (c+d) g (b+c) a internal conference bc offg (b+s) g (c+s) off g (b+c)
duslic functional description product overview 50 2000-11-09 preliminary 2.10 16 khz modes on pcm highway in addition to the standard 8-khz transmission pcm-interface modes, there are also two 16-khz modes for high data transmission performance. table 8 shows the configuration of the pcm channels for the different pcm interface modes. the configuration bits pcm16k and lin (in the bcr3 register) are used to select the following pcm interface modes: pcm mode normal mode used for voice transmission via channels r1 and x1 (receive and transmit). the pcm input channels r2, r3 and r4 are always available for use in different conference configurations. the status of the pcm output channels depends on the conference mode configuration. table 8 possible modes in pcm/ c interface mode config. bits receive pcm channels transmit pcm channels pcm16k lin r1 r1l 1) 1) time slot r1 + 1 r2 r3 r4 x1 x1l 2) 2) time slot x1 + 1 x2 x3 x4 pcm mode 00a 3) 3) empty cells in the table mark unused data in the pcm receive channels and switched-off line drivers in the pcm transmit channels bcds ? depends on conference mode lin mode 0 1 a-hb a-lb b c d s-hb s-lb depends on conference mode pcm16 mode 10ds1 ?? ds2 ? ds1 ?? ds2 ? lin16 mode 11ds1- hb ? ds1- lb ds2- hb ds2- lb ds1- hb ? ds1- lb ds2- hb ds2- lb
duslic functional description product overview 51 2000-11-09 preliminary lin mode similar to the pcm mode, but for 16 bit linear data at 8 khz sample rate via the pcm channels r1, r1l (receive) and x1, x1l (transmit). pcm16 mode mode for higher data transmission rate of pcm encoded data using a 16 khz sample rate (only in pcm/ c interface mode with specific register setting). in this mode the channels r1, r3 (x1, x3) are used to receive (transmit) two samples of data (ds1, ds2) in each 8 khz frame. lin16 mode like the pcm16 mode for 16 khz sample rate but for linear data. channels r1 to r4 (x1 to x4) are used for receiving (transmitting) the high and low bytes of the two linear data samples ds1 and ds2. lin16 mode: like the pcm16 mode for the 16-khz sample rate but for linear data. the channels r1 to r4 (x1 to x4) are used for receiving (transmitting) the high and low bytes of the two linear data samples ds1 and ds2.
duslic operational description product overview 52 2000-11-09 preliminary 3 operational description 3.1 operating modes for the duslic chip set sleep (sl) the slicofi-2 is able to go into a sleep mode with minimal power dissipation. in this mode off-hook detection is performed without any checks on spikes or glitches. off-hook is detected by an analog comparator in slicofi-2 and transferred via the int or the du- pin. the sleep mode can be used for either channel, but for the most effective power saving, both channels should be set to this mode. power down resistive (pdrh for slic-e/-e2/-s/-s2 and pdrr for slic-p) the power down resistive mode is the standard mode for none-active lines. off-hook is detected by a current value fed to the dsp, compared with a programmable threshold, and filtered by a data upstream persistence checker. the power management slic-p can be switched to a power down resistive high (pdrh) or a power down resistive ring (pdrr) mode. hirt the line drivers in the slic-e/-e2/-p are shut down and no resistors are switched to the line. off-hook detection is not possible. in hirt mode the slicofi-2 is able to measure the input offset of the current sensors. power down high impedance (pdh) in power down high impedance mode, the slic is totally powered down. no off-hook sensing can be performed. this mode can be used for emergency shutdown of a line. active high (acth) a regular call can be performed, voice and metering pulses can be transferred via the telephone line and the dc loop is operational in the active high mode. active low (actl) the active low mode is similar to the active high mode. the only difference is that the slic uses a lower battery voltage, v batl (bit actl = 1). active ring (actr) the active ring mode is different for the slic-e/-e2 and the slic-p. the slic-e/-e2 uses the additional positive voltage v hr for extended feeding and the slic-p will switch to the negative battery voltage v batr .
duslic operational description product overview 53 2000-11-09 preliminary ringing if the slicofi-2x is switched to ringing mode, the slic is switched to actr mode. with the slic-p connected to the slicofi-2, the ring on ring (ror) mode allows unbalanced internal ringing on the ring wire. the tip wire is set to battery ground. the ring signal will be superimposed by v batr /2. the ring on tip (rot) mode is the equivalent to the ror mode. active with hit this is a testing mode where the tip wire is set to a high impedance mode. it is used for special line testing. it is only available in an active mode of the slicofi-2x to enable all necessary test features. active with hir hir is similar to hit but with the ring wire set to high impedance. active with metering any available active mode can be used for metering either with reverse polarity or with ttx signals. ground start the tip wire is set to high impedance in ground start mode. any current drawn on the ring wire leads to a signal on it, indicating off-hook. ring pause the ring burst is switched off in ring pause, but the slic remains in the specified mode and the off-hook recognition behaves like in ringing mode (ring trip).
duslic operational description product overview 54 2000-11-09 preliminary 3.2 operating modes for the duslic-s/-s2 chip set table 9 duslic-s/-s2 operating modes slicofi-2s / slicofi-2s2 mode slic-s / slic-s2 mode slic-s/-s2 internal supply voltages (+/ ? )[ v hi / v bi ] system functionality active circuits tip/ring output voltage pdh pdh open/ v bath none none high impedance power down resistive pdrh open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ? pdrhl 1) open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) active low (actl) actl v bgnd / v batl voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batl + v ac + v dc )/2 ring: ( v batl ? v ac ? v dc )/2 active high (acth) acth v bgnd / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v bath + v ac + v dc )/2 ring: ( v bath ? v ac ? v dc )/2 active ring (actr) actr v hr / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx- generator (optional) tip: (+ v bath + v hr + v ac + v dc )/2 ring: (+ v bath + v hr ? v ac ? v dc )/2 ringing (ring) actr v hr / v bath balanced ring signal feed (incl. dc offset) buffer, sensor, dc loop, ring generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2
duslic operational description product overview 55 2000-11-09 preliminary ring pause actr v hr / v bath dc offset feed buffer, sensor, dc loop, ramp generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2 active with hir hir v hr / v bath e.g. line test (tip) tip buffer, sensor, dc + ac loop tip: ( v bath + v hr + v ac + v dc )/2 ring: high impedance active with hit hit v hr / v bath e.g. line test (ring) ring buffer, sensor, dc + ac loop ring: ( v bath + v hr ? v ac ? v dc )/2 tip: high impedance 1) load ext. c for switching from pdrh to acth in on-hook mode v ac ? tip/ring ac voltage v dc ? tip/ring dc voltage table 9 duslic-s/-s2 operating modes (cont ? d) slicofi-2s / slicofi-2s2 mode slic-s / slic-s2 mode slic-s/-s2 internal supply voltages (+/ ? )[ v hi / v bi ] system functionality active circuits tip/ring output voltage
duslic operational description product overview 56 2000-11-09 preliminary 3.3 operating modes for the duslic-e/-e2 chip set table 10 duslic-e/-e2 operating modes slicofi-2 mode slic-e / slic-e2 mode slic-e/-e2 internal supply voltages (+/ ? )[ v hi / v bi ] system functionality active circuits tip/ring output voltage pdh pdh open/ v bath none none high impedance sleep pdrh open/ v bath off-hook detect via off- hook comparator off-hook, analog comparator v bgnd / v bath (via 5 k ? ) power down resistive pdrh open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ? pdrhl 1) open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) active low (actl) actl v bgnd / v batl voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batl + v ac + v dc )/2 ring: ( v batl ? v ac ? v dc )/2 active high (acth) acth v bgnd / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v bath + v ac + v dc )/2 ring: ( v bath ? v ac ? v dc )/2 active ring (actr) actr v hr / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: (+ v bath + v hr + v ac + v dc )/2 ring: (+ v bath + v hr ? v ac ? v dc )/2
duslic operational description product overview 57 2000-11-09 preliminary ringing (ring) actr v hr / v bath balanced ring signal feed (incl. dc offset) buffer, sensor, dc loop, ring generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2 ring pause actr v hr / v bath dc offset feed buffer, sensor, dc loop, ramp generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2 hirt hirt v hr / v bath e.g. sensor offset calibration sensor, dc transmit path high impedance active with hir hir v hr / v bath e.g. line test (tip) tip-buffer, sensor, dc + ac loop tip: ( v bath + v hr + v ac + v dc )/2 ring: high impedance active with hit hit v hr / v bath e.g. line test (ring) ring-buffer, sensor, dc + ac loop ring: ( v bath + v hr ? v ac ? v dc )/2 tip: high impedance 1) load ext. c for switching from pdrh to acth in on-hook mode v ac ? tip/ring ac voltage v dc ? tip/ring dc voltage table 10 duslic-e/-e2 operating modes (cont ? d) slicofi-2 mode slic-e / slic-e2 mode slic-e/-e2 internal supply voltages (+/ ? )[ v hi / v bi ] system functionality active circuits tip/ring output voltage
duslic operational description product overview 58 2000-11-09 preliminary 3.4 operating modes for the duslic-p chip set table 11 duslic p operating modes slicofi-2 mode slic-p mode slic-p internal supply voltages [ v bi ] system functionality active circuits tip/ring output voltage pdh pdh v batr none none high impedance sleep pdrh v bath off-hook detect via off-hook comparator off-hook, analog comparator v bgnd / v bath (via 5 k ? ) sleep pdrr v batr off-hook detect via off-hook comparator off-hook, analog comparator v bgnd / v batr (via 5 k ? ) power down resistive pdrh v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ? pdrhl 1) v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ? pdrr v batr off-hook detect as in active mode (dsp) off-hook, analog comparator v bgnd / v batr (via 5 k ? ) ? pdrrl 2) v batr off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v batr (via 5 k ? ) active low (actl) actl v batl voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batl + v ac + v dc )/2 ring: ( v batl ? v ac ? v dc )/2 active high (acth) acth v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v bath + v ac + v dc )/2 ring: ( v bath ? v ac ? v dc )/2
duslic operational description product overview 59 2000-11-09 preliminary active ring (actr) actr v batr voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batr + v ac + v dc )/2 ring: ( v batr ? v ac ? v dc )/2 ringing (ring) actr v batr balanced ring signal feed (incl. dc offset) buffer, sensor, dc loop, ring generator tip: ( v batr + v dc )/2 ring: ( v batr ? v dc )/2 ringing (ring) ror v batr ring signal on ring, tip on bgnd buffer, sensor, dc loop, ring generator ring: ( v batr ? v dc )/2 tip: 0 v ringing (ring) rot v batr ring signal on ring, tip on bgnd buffer, sensor, dc loop, ring generator tip: ( v batr + v dc )/2 ring: 0 v ring pause actr, ror, rot v batr dc offset feed buffer, sensor, dc loop, ramp generator tip: ( v batr + v dc )/2 ring: ( v batr ? v dc )/2 hirt hirt v batr e.g. sensor offset calibration sensor, dc transmit path high impedance active with hir hir v batr e.g. line test (tip) tip-buffer, sensor, dc + ac loop tip: ( v batr + v ac + v dc )/2 ring: high impedance active with hit hit v batr e.g. line test (ring) ring-buffer, sensor, dc + ac loop ring: ( v batr ? v ac ? v dc )/2 tip: high impedance 1) load ext. c for switching from pdrh to acth in on-hook mode 2) load ext. c for switching from pdrr to actr in on-hook mode table 11 duslic p operating modes (cont ? d) slicofi-2 mode slic-p mode slic-p internal supply voltages [ v bi ] system functionality active circuits tip/ring output voltage
duslic operational description product overview 60 2000-11-09 preliminary 3.5 operating modes and power management in many applications, the power dissipated on the line card is a critical parameter. in larger systems, the mean power value (taking into account traffic statistics and line length distribution) determines cooling requirements. particularly in remotely fed systems, the maximum power for a line must not exceed a given limit. 3.5.1 introduction generally, system power dissipation is determined mainly by the high-voltage part. the most effective power-saving method is to limit slic functionality and reduce supply voltage in line with requirements. this is achieved using different operating modes. the three main modes ? power down, active and ringing ? correspond to the main system states: on-hook, signal transmission (voice and/or ttx) and ring signal feed. for power critical applications the sleep mode can be used for even lower power consumption than in power down mode. ? power down off-hook detection is the only function available. it is realized by 5 k ? resistors applied by the slic from tip to v bgnd and ring to v bat , respectively. a simple sensing circuit supervises the dc current through these resistors (zero in on-hook and non-zero in off- hook state). this scaled transversal line current is transferred to the it pin and compared with a programmable current threshold in the slicofi-2x . only the dc loop in the slicofi-2x is active. in sleep mode, all functions of the slicofi-2x are switched off except for off-hook detection which is still available via an analog comparator. both ac and dc loops are inactive. to achieve the lowest power consumption of the duslic chip set, the clock cycles fed to the mclk and pclk pins have to be shut off. for changing into another state the duslic has to be waked up. ? active both ac and dc loops are operative. the slic provides low-impedance voltage feed to the line. the slic senses, scales and separates transversal (metallic) and longitudinal line currents. the voltages at tip and ring are always symmetrical with reference to half the battery voltage (no ground reference!). an integrated switch makes it possible to choose between two (slic-s/-s2, slic-e/-e2) or even three (slic-p) different battery voltages. with these voltages selected according to certain loop lengths, power optimized solutions can be achieved.
duslic operational description product overview 61 2000-11-09 preliminary ? ringing for slic-e/-e2 and slic-s, an auxiliary positive supply voltage v hr is used to give a total supply range of up to 150 v. for slic-p the whole supply range is provided by v batr . the low-impedance line feed ( r stab (2x30 ?) + r fuse (2x20 ?) + appr. 1 ? 101 ? output impedance) with a balanced sinusoidal ring signal of up to 85 vrms, plus a dc offset of 20 v, is sufficient to supply very long lines at any kind of ringer load and to reliable detect ring trip. unbalanced ringing is supported by applying the ring signal to only one line, while ground is applied to the other line. for an overview of all duslic operating modes see table 9 for peb 4264/-2, table 10 for peb 4265/-2 and table 11 for peb 4266. 3.5.2 power dissipation of the slicofi-2x table 12 and table 13 show typical power dissipation values for different operating modes of the slicofi-2 and slicofi-2s/-2s2 1) . for an optimized power consumption of the slicofi-2 ( table 12 ) unused edsp functions have to be switched off. conditions (all codecs): t a = ? 40 c to 85 c, unless otherwise stated. v ddd = v dda = v ddb = v ddr = v ddpll =3.3v 5%; v gnda = v gndb = v gndr = v gndd = v gndpll =0v 1) for more detailed characteristics see the duslic data sheet. table 12 power dissipation peb 3265 (slicofi-2) parameter symbol limit values unit test condition min. typ. max. power dissipation sleep both channels p ddsleep ? 17 25 mw (mclk, pclk = 2 mhz) power down both channels p ddpdown ? 79 104 mw ? active one channel p ddact1 ? ? ? 129 142 155 160 174 191 mw mw mw without edsp with 8 mips 1) (dtmf detection) with 16 mips 1) mips = million instructions per second (performed by the edsp) active both channels p ddact2 ? ? 182 231 243 315 mw mw without edsp with 32 mips
duslic operational description product overview 62 2000-11-09 preliminary 3.5.3 power dissipation of the slic the slic power dissipation mainly comes from internal bias currents and the buffers output stage (to a less extent from the sensor) where additional power is dissipated whenever current is fed to the line. 3.5.3.1 power down modes in power down modes, the internal bias currents are reduced to a minimum value and no current is fed to the line (see table 16 , table 18 and table 20 ). even with active off- hook detection the power dissipation of 5 mw (6 mw for slic-p) is negligible. note that this is the dominant factor for low mean power value in large systems, as a large percentage of lines are always inactive. 3.5.3.2 active mode in active mode, the selected battery voltage v batx 1) has the strongest influence on power dissipation. the power dissipation in the output stage p o is determined by the difference between v batx and the tip-ring voltage v tip/ring . at constant dc line current i trans , the shortest lines (lowest r l ) cause lowest v tip/ring , and accordingly exhibit the highest on-chip power dissipation. however, the minimum battery voltage required is determined by the longest line and therefore the maximum line resistance r l,max and in addition r prot and r stab . v batx,min = i trans ( r l,max + r prot + r stab )+ v ac,p + v drop v ac,p ..................... peak value of ac signal v drop ................... sum of voltage drop in the slic buffers ( table 14 ) table 13 power dissipation peb 3264, peb 3264-2 (slicofi-2s/-2s2) parameter symbol limit values unit test condition min. typ. max. power dissipation power down both channels p ddpdown ? 79 104 mw ? active one channel p ddact1 ? 129 160 mw ? active both channels p ddact2 ? 182 243 mw ? 1) v batx = v batl , v bath or v batr
duslic operational description product overview 63 2000-11-09 preliminary the most efficient way to reduce short-loop power dissipation is to use a lower battery supply voltage ( v batl ) whenever line resistance is small enough. this method is supported on the slic-e/-e2 by integrating a battery switch. with a standard battery voltage of ? 48 v, long lines up to 2 k ? can be driven at 20 ma line current. the slic-p peb 4266 ? low-power ? version even allows three battery voltages (typically the most negative one, e.g. ? 48 v, is used in active mode (on-hook) and power down mode). duslic contains two mechanism which can be used as indication for the battery switching: 1. a threshold for the voltage at tip/ring can be set for generating an interrupt 2. the change between constant current and resistive feeding will generate an interrupt table 14 typical buffer voltage drops (sum) for i trans ( i t or i r ) mode total voltage drop v drop [v] slic-e/-e2/-s/-s2 slic-p actl i trans 96 ? i trans 88 ? acth i trans 100 ? i trans 100 ? actr ( i trans 100 ? ) + 1 v i trans 92 ? ror, rot ? i trans 92 ? hir, hit ( i torr 48 ? ) + 1 v i torr 52 ?
duslic operational description product overview 64 2000-11-09 preliminary 3.5.3.3 slic power consumption calculation in active mode a scheme of a typical calulation is shown in figure 31 . figure 31 circuit diagram for power consumption r prot =40 ? , r stab =60 ? , r phone =150 ? , v phone =7v, i line =20ma conditions: v voice peak =2v, i voice peak =2ma, v ttx,rms (see example below) typical power consumption calculation with slic-e/-e2 assuming a typical application where the following battery voltages are used: v dd =5v, v batl = ? 27 v, v bath = ? 48 v, v hr = 45 v and line feeding is guaranteed up to r lmax =800 ? . for longer lines ( r l > 800 ? ) the extended battery feeding option can be used (mode actr). requirement for ttx: v ttx =0.6vrms at a load of 200 ? . slic off-hook r prot + r stab r line r phone v phone i line v subscriber v tr circuit diagram ezm14049.emf
duslic operational description product overview 65 2000-11-09 preliminary table 15 shows line currents and output voltages for different operating modes. with the line feed conditions given in the above table the total power consumption p tot and its shares at different operating modes are shown in table 16 . the output voltage at tip and ring is calculated for a typical line length ( r l =3/4* r lmax in acth, r l =1/4* r lmax in actl). figure 32 shows the total power dissipation p tot of the slic-e/-e2 in active mode (acth and actl) with switched battery voltage ( v bath , v batl ) as a function of r line . the power dissipation in the slic is strongly reduced for short lines. table 15 line feed conditions for power calculation of slic-e/-e2 operating mode line currents output voltages pdrh, pdrhl i trans =0ma ? actl i trans =20ma v tip/ring =16v acth i trans =20ma v tip/ring =24v table 16 slic-e/-e2 typical total power dissipation p q 1) 1) the formulas for the calculation of the power shares p q , p i , p g and p o can be found in the duslic data sheet. p i p g p o p tot operating mode [mw] [mw] [mw] [mw] [mw] pdh3.7000 3.7 pdrh 4.4 0 0 0 4.4 actl 81.8 33.7 3.3 220 339 acth 173 56.8 0 480 710
duslic operational description product overview 66 2000-11-09 preliminary figure 32 slic-e/-e2 power dissipation with switched battery voltage typical power consumption calculation with slic-p (internal ringing) assuming a typical application where the following battery voltages are used: v dd =3.3v, v batl = ? 22 v, v bath = ? 48 v, v batr = ? 80 v and a maximum line length of up to r lmax =400 ? is used. requirement for ttx: v ttx = 0.4 vrms at a load of 200 ? . table 17 shows line currents and output voltages for different operating modes. with the line feed conditions given in the above table, the total power consumption p tot and its shares at different operating modes are shown in table 18 . the output voltage at tip and ring is calculated for typical line length ( r l =3/4* r lmax in acth, r l =1/4* r lmax in actl). table 17 line feed conditions for power calculation for slic-p operating mode line currents output voltages pdrh, pdrhl i trans =0ma ? actl i trans =20ma v tip/ring =14v acth i trans =20ma v tip/ring =18v duslic_0002_powerdiss.emf 0 200 400 600 800 1000 1200 1400 100 200 300 400 500 600 700 800 r line [ ? ? ? ? ] p tot [mw] slic power dissipation power consumption output power
duslic operational description product overview 67 2000-11-09 preliminary . figure 34 shows the total power dissipation ptot of the slic-p in active mode (acth and actl) with switched battery voltage ( v bath , v batl ) as a function of r line . figure 33 slic-p power dissipation (switched battery voltage, long loops) table 18 slic-p peb 4266 power dissipation p q 1) 1) the formulas for the calculation of the power shares p q , p i , p g and p o can be found in the duslic data sheet. p i p g p o p tot operating mode [mw] [mw] [mw] [mw] [mw] pdh 6.4 0 0 0 6.4 pdrh 6.4 0 0 0 6.4 pdrr 7.7 0 0 0 7.7 actl 50.5 26.8 ? 2160 235 acth 133.4 55.4 0 600 789 ror, rot (ring pause) 194.6 0 ? 20 0 175 duslic_0001_powerdiss.emf 0 200 400 600 800 1000 1200 1400 100 200 300 400 r line [ ? ? ? ? ] p tot [mw] slic power dissipation power consumption output power
duslic operational description product overview 68 2000-11-09 preliminary typical power consumption calculation with slic-p (external ringing) assuming a typical application where the following battery voltages are used: v dd =3.3v, v batl = ? 22 v, v bath = ? 26 v, v batr = ? 48 v and line feeding is guaran-teed up to r l =400 ? . requirement for ttx: v ttx,rms =0.4vrms. this is a typical lowest-power application, where v batr is used just in the on-hook state and v bath and v batl is used in the active modes with battery switching. table 19 shows line currents and output voltages for different operating modes. with the line feed conditions given in the above table, the total power consumption p tot and its shares at different operating modes are shown in table 20 . the output voltage at tip and ring is calculated for a typical line length ( r l =3/4* r lmax in acth, r l =1/4* r lmax in actl). . figure 34 shows the total power dissipation p tot of the slic-p in active mode (acth and actl) with switched battery voltage ( v bath , v batl ) as a function of r line (lowest power applications). table 19 line feed conditions for power calculation for slic-p operating mode line currents output voltages pdrh, pdrhl i trans =0ma ? actl i trans =20ma v tip/ring =14v acth i trans =20ma v tip/ring =18v table 20 slic-p peb 4266 power dissipation p q 1) 1) the formulas for the calculation of the power shares p q , p i , p g and p o can be found in the duslic data sheet. p i p g p o p tot operating mode [mw] [mw] [mw] [mw] [mw] pdh 4.0 0 0 0 4.0 pdrh 3.9 0 0 0 3.9 pdrr 4.8 0 0 0 4.8 actl 49.9 26.8 ? 2160 235 acth 73.7 31.2 ? 34.7 160 230
duslic operational description product overview 69 2000-11-09 preliminary figure 34 slic-p power dissipation (switched battery voltage, short loops) 3.5.3.4 ringing modes internal balanced ringing (slic-e and slic-p) the slic-e/-e2/-p internal balanced ringing facility requires a higher supply voltage (auxiliary voltage v hr ). the highest share of the total power is dissipated in the output stage of the slic-e/-e2/-p. the output stage power dissipation p o (see table 21 , table 22 ) depends on the ring amplitude ( v rng,peak ), the equivalent ringer load ( r rng and c rng ), the ring frequency (via cos l ) and the line length ( r l ). the minimum auxiliary voltage v hr necessary for a required ring amplitude can be calculated using: v hr ? v bath = v rng,peak + v rng,dc + v drop = v rng,rms crest factor + v rng,dc + v drop the crest factor is defined as peak value divided by rms value (here always 1.41 because sinusoidal ringing is assumed). v rng,dc superimposed dc voltage for ring trip detection (10 to 20 v) v drop sum of voltage drops in slic buffers ( table 14 ) v rng,peak peak ring voltage at tip/ring duslic_0003_powerdiss.emf 0 100 200 300 400 500 600 700 100 200 300 400 r line [ ? ? ? ? ] p tot [mw] slic power dissipation power consumption output power
duslic operational description product overview 70 2000-11-09 preliminary the strong influence of the ringer load impedance z ld and the number of ringers is demonstrated by the formula for the current sensor power dissipation ( p i + p o ) in table 21 and table 22 . the ringer load impedance z ld can be calculated as follows: z ld =| z ld | e j ld = r l + r rng +1/j c rng with z ld load impedance r rng ringer resistance c rng ringer capacitance r l line resistance internal unbalanced ringing with slic-p the ring signal is present just on one line (modes ror, rot), while the other line is connected to a potential of gnd. the minimum battery voltage v batr necessary for a required ring amplitude can be calculated using: ? v batr ? v drop =2 v rng, peak =2 v rng,rms crest factor external ringing (slic-e/-e2 and slic-p) when an external ring generator and ring relays are used, the slic can be switched to power down mode. the ? low-power ? slic-p is optimized for extremely power-sensitive applications (see table 20 ). slic-p has three different battery voltages. v batr can be used for on-hook, while v bath and v batl are normally used for off-hook mode.
duslic operational description product overview 71 2000-11-09 preliminary 3.5.3.5 slic power consumption calculation in ringing mode the average power consumption for a ringing cadence of 1 second on and 4 seconds off is given by p tot, average =k p tot, ringing +(1 ? k) p tot, ringpause with k = 0.20 the typical circuit for ringing is shown in figure 35 . figure 35 circuit diagram for ringing ezm35004.emf z rng r rng c rng r line v rng r prot + r stab slic v tr i circuit diagram for ringing on hook
duslic operational description product overview 72 2000-11-09 preliminary ? power consumption calculation for slic-e/-e2 in balanced ringing mode with the example of the above calculation for slic-e/-e2 (see chapter 3.5.3.3 ) and a typical ringer load. typical ringer load: r rng =450 ?, c rng =3.4 f required ringing voltage v rng =45vrms and ringing frequency f rng =20hz dc offset voltage for ring trip detection v dc =16v. table 21 shows the power calculation for the total power dissipation p tot of the slic-e/ slic-e2 in balanced ringing mode consisting of the quiescent power dissipation p q , the current sensor power dissipation p i , the gain stage power dissipation p g and the output stage power dissipation p o . table 21 slic-e/-e2 balanced ringing power dissipation (typical) p tot, ringpause = p q + p i + p g + p o ( i trans =0ma) 458mw p tot, ringing = p q + p i + p g + p o 1526 mw 1) 1) values for v dd =5v, v batl = ? 27 v, v bath = ? 48 v, v hr =45v, t j =25 c p q = v dd i dd +i v bath i i bath +i v batl i i batl + v hr i hr 254 mw p i =0.015 i trans,rms v hr +0.055 i trans,rms | v bath | +0.04 i trans,rms v dd with i trans,rms = v tip/ring, rms /| z ld | 67 mw p g =( v hr +| v bath |) ( sqrt( ( v hr + v bath + v dc-offset ) 2 +( v tip/ ring 2 )/2) ? i v hr + v bath i)/60k + ( v hr2 ? 322 + v bath 2 ? 48 2 ) (1/60k + 1/216k) 99 mw p o = ( v hr +i v bath i) i trans,rms 2 sqrt(2)/ ? v tip/ring, rms i trans,rms cos( load ) 1105 mw
duslic operational description product overview 73 2000-11-09 preliminary ? power consumption calculation for slic-p in balanced ringing mode with the example of the above calculation with r l =400 ? line length for slic-p (see chapter 3.5.3.3 ) when the internal ringing feature will be used. typical ringer load: r rng = 1000 ?, c rng =3.7 f. required ringing voltage v rng = 40 vrms and ringing frequency f rng =20hz. dc offset voltage for ring trip detection v dc =14v. table 22 shows the power calculation for the total power dissipation p tot of the slic-p in balanced ringing mode consisting of the quiescent power dissipation p q , the current sensor power dissipation p i , the gain stage power dissipation p g and the output stage power dissipation p o . table 22 slic-p balanced ringing power dissipation (typical) p tot, ringpause = p q + p i + p g + p o ( i trans = 0 ma) 283 mw p tot, ringing = p q + p i + p g + p o 1137 mw 1) 1) values for v dd =3.3v, v batl = ? 22 v, v bath = ? 48 v, v batr = ? 80 v, t j =25 c p q = v dd i dd +i v batr i i batr +i v bath i i bath +i v batl i i batl 281 mw p i =0.055 i trans,rms i v batr i + 0.04 i trans,rms v dd with i trans,rms = v tip/ring, rms /i z ld i 76 mw p g =( v batr 2 ? 80 2 ) (1/60k + 1/216k) ? 1.6 mw p o =i v batr i i trans,rms 2 sqrt(2)/ ? v tip/ring, rms i trans,rms cos( load ) 781 mw
duslic operational description product overview 74 2000-11-09 preliminary ? power consumption calculation for slic-p in unbalanced ringing mode a similar power calculation is valid for internal unbalanced ringing mode, which is only available for the slic-p. example: v dd =3.3v, v batl = ? 22 v, v bath = ? 48 v, v batr = ? 128 v and line feeding is guaranteed up to 400 ? . typical ringer load: r rng =1000 ?, c rng =3.7 f required ringing voltage v rng = 40 vrms and ringing frequency f rng =20hz. table 23 shows the power calculation for the total power dissipation p tot of the slic-p in unbalanced ringing mode. note: for further power reduction in unbalanced ringing mode see the application note ?duslic ringing modes? (chapter 5: ?integrated unbalanced ringing with reduced power dissipation using slic-p?) table 23 slic-p unbalanced ringing power dissipation (typical) p tot, ringpause = p q + p i + p g + p o ( i trans = 0 ma) 530 mw p tot, ringing = p q + p i + p g + p o 2125 mw 1) 1) values for v dd =3.3v, v batl = ? 22 v, v bath = ? 48 v, v batr = ? 128 v, t j =25 c p q = v dd i dd +i v batr i i batr +i v bath i i bath +i v batl i i batl 310 mw p i =0.055 i trans,rms i v batr i + 0.04 i trans,rms v dd with i trans,rms = v tip/ring, rms /i z ld i 121 mw p g =(0.5 v tip/ring 2 ? ( v batr /2) 2 )/60k + ( v batr 2 ? 80 2 ) (1/60k + 1/216k) 177 mw p o =i v batr i i trans,rms 2 sqrt(2)/ ? v tip/ring, rms i trans,rms cos( load ) 1518 mw
duslic operational description product overview 75 2000-11-09 preliminary 3.6 integrated test and diagnosis functions (itdf) 1) 3.6.1 introduction subscriber loops are affected by a variety of failures which have to be monitored. monitoring the loop supposes the access to the subscriber loop and to have test equipment in place which are capable to perform certain measurements. the measurements or tests involve resistance, capacitance, leakage, and measurements of interfering currents and voltages. 3.6.2 conventional line testing conventional linecards in central office (co) applications usually need two test relays per channel to access the subscriber loop with the appropriate test equipment. one relay (test-out) connects the actual test unit to the local loop. all required line tests can be accomplished that way. the second relay (test-in) separates the local loop from the slic-e/-e2/-p and connects a termination impedance to it. hence, by sending a tone signal the entire loop can be checked, including the slicofi-2 and slic-e/-e2/-p. with an external test unit, every line has to be connected separately to the test unit and the tests have to be performed one line at a time. testing thousands of lines takes several hours. because of the time factor, these tests are typically carried out once a week or once a month. the test cycle for a specific subscriber line is therefore very long and any failures are usually detected at a very late stage. this reduces the network quality. 3.6.3 duslic line testing the duslic with its integrated test and diagnosis functions (itdf) is capable to perform all tests necessary to monitor the local loop without an external test unit and test relays. the fact, that measurements can be accomplished much faster as with conventional test capabilities makes it even more a compelling argument for the duslic. with the duslic both channels are able to perform line tests concurrently, which also has a tremendous impact on the test time. all in all, the duslic increases the quality of service and reduces the costs in various applications. 1) only available with duslic-e/-e2/-p
duslic operational description product overview 76 2000-11-09 preliminary 3.6.4 diagnostics the two-channel chip set has a set of signal generators and features implemented to accomplish a variety of diagnostic functions. the slicofi-2 device generates all test signals, processes the information that comes back from the slic-e/-e2/-p and provides the data to a higher level master device, e.g. a microprocessor. all the tests can be initiated by the micropocessor and the results can be read back very easily. the integrated test and diagnosis functions (itdf) might prevent any problem which affects service caused by the subscriber line or line equipment before the customer complains. idtf has been integrated to facilitate the monitoring of the subscriber loop. 3.6.4.1 line test capabilities the line test comprises the following functions: loop resistance measurement: the dc loop resistance can be determined by supplying a constant dc voltage v tr,dc to the ring- and tip line and measuring the dc loop current via the it pin. leakage current: ? leakage current tip/ring ? leakage current tip/gnd ? leakage current ring/gnd ringer / line capacitance: capacitance measurements can be performed by using the integrated ramp generator function. loading a capacitor c measure with a constant voltage ramp results in a constant current which is proportional to c measure. ? line capacitance tip/gnd ? line capacitance ring/gnd foreign voltage measurement: two analog input pins (io3, io4) can be used for direct and differential measurement of two external voltages. ? foreign voltage measurement tip/gnd ? foreign voltage measurement ring/gnd ? foreign voltage measurement tip/ring measurement of ringing voltage measurement of line feed current measurement of supply voltage v dd of the slicofi-2 measurement of transversal- and longitudinal current
duslic operational description product overview 77 2000-11-09 preliminary 3.6.4.2 integrated signal sources the signal sources available on the duslic chip set are: constant dc voltage (three programmable ringing dc offset voltages) 2 independent tone generators tg1 and tg2: ttx metering signal generator (12/16 khz) ramp generator (used for capacitance measurements) ring generator (5 hz - 300 hz) 3.6.4.3 dc levelmeter the dc levelmeter results will be determined and prepared depending on certain configuration settings. the selected input signal becomes digitized after pre-filtering and analog-to-digital conversion. the following values can be measured: 3.6.4.4 ac levelmeter the ac levelmeter allows access to the voice signal while the active voice signal is being processed. the input signal for the ac levelmeter might get processed with a programmable filter characteristic, i.e. bandpass- or notch filter. the following values can be measured: dc levelmeter measurement values: dc out voltage on dcp-dcn dc current on it dc current on il voltage on io3 voltage on io4 v dd offset of dc-pre-filter (short circuit on dc-pre-filter input) voltage on io4 ? io3 ac levelmeter measurement values: ac level in transmit ac level in receive ac level receive + transmit
duslic operational description product overview 78 2000-11-09 preliminary 3.6.5 signal path and test loops the following figures show the main ac and dc signal path and the integrated analog and digital loops of slicofi-2, slicofi-2s and slicofi-2s2. please note the interconnections between the ac and dc pictures of the respective chip set. for further information on the shown registers and bits/switches please see the duslic data sheet. 3.6.5.1 test loops slicofi-2 figure 36 ac test loops slicofi-2 tg mu-law lin hpx1 ax1 frx lpx exp + ar1 tg hpr frr lpr th hpx2 ax2 ar2 cor8 pcm16k cox16 ac-dlb-32k cor-64 ac-dlb-128k dac adc im2 opim_4m pofi prefi opim_an ac-dlb-4m pcm16k 16k ax-dis ar-dis th-dis lprx-cr ax-dis frx-dis hpx-dis pd-ac-gn pd-ac-ad him-an pd-ac-po pd-ac-da im-dis ptg, tg1-en, tg2-en ar-dis hpr-dis frr-dis lpx-cr mu-law lin lm-ac ac-dlb-8k lm-val* cmp lm-dc lm2pcm lm -s el[3:0] lm-notch lm-filt lm-en pcm2dc hpx-dis ttx gen. ttx-12k ttx-dis + im3 + ttx adapt. ttx-12k ttx-dis pd-ttx-a + + pd-ac-pr ac-xgain itac acn/acp a b a b c programmable via cram not programmable switch switch always available available only when bit test-en = 1 *lm-val-h[7:0] lm -val-l[7:0] d im1 pcm in: receive data from pcm or iom-2 interface pcm out: transmit data to pcm or iom-2 interface duslic_0022_intstru_slicofi2_a.wmf
duslic operational description product overview 79 2000-11-09 preliminary figure 37 dc test loops slicofi-2 duslic_0022_intstru_slicofi2_b.wmf pd-dc-ad dc prefi dc adc pd-dc-pr it il io3 io4 io4 ? io3 vdd offset lp dc-hold ramp-en ramp + hook lm-dc ro1 ro1 dc char. rg ro1 + + lm-en lm-rect rtr-sel rng-offset[1:0] pcm2dc dcn/dcp c programmable via cram not programmable pd-dc-da pd-dcbuf pc-pofi-hi dc pofi dc buf dc dac lm-sel[3:0] switch switch always available available only when bit test-en = 1 it pd-ofhk offhook comp il pd-gnkc gnk comp c1 pd-hvi hv-int. c2 overt. comp pd-ovtc d *o ffset-h[7:0] o ffset-l[7:0] offset*
duslic operational description product overview 80 2000-11-09 preliminary 3.6.5.2 test loops slicofi-2s/-2s2 the ac test loops for slicofi-2s ( figure 38 ) and slicofi-2s2 ( figure 39 ) are different since teletax (ttx) is not available with slicofi-2s2. the dc test loops are identical. figure 38 ac test loops slicofi-2s duslic_0023_intstru_slicofi2s_c.wmf tg mu-law lin hpx1 ax1 frx lpx exp + ar1 tg hpr frr lpr th hpx2 ax2 ar2 cor8 cox16 ac-dlb-32k cor-64 16k ax-dis ar-dis th-dis lprx-cr ax-dis frx-dis hpx-dis ptg, tg1-en, tg2-en ar-dis hpr-dis frr-dis lpx-cr mu-law lin ac-dlb-8k cmp pcm2dc hpx-dis a b c pcm in: receive data from pcm or iom-2 interface pcm out: transmit data to pcm or iom-2 interface ac-dlb-128k dac adc im2 opim_4m pofi prefi opim_an ac-dlb-4m pd-ac-gn pd-ac-ad him-an pd-ac-po pd-ac-da im-dis ttx gen. ttx-12k ttx-dis + im3 + ttx adapt. ttx-12k ttx-dis pd-ttx-a + + pd-ac-pr ac-xgain itac acn/acp a b programmable via cram not programmable switch switch always available available only when bit test-en = 1 im1
duslic operational description product overview 81 2000-11-09 preliminary figure 39 ac test loops slicofi-2s2 duslic_0023_intstru_slicofi2s_a.wmf tg mu-law lin hpx1 ax1 frx lpx exp + ar1 tg hpr frr lpr th hpx2 ax2 ar2 cor8 cox16 ac-dlb-32k cor-64 ac-dlb-128k dac adc im2 opim_4m pofi prefi opim_an ac-dlb-4m 16k ax-dis ar-dis th-dis lprx-cr ax-dis frx-dis hpx-dis pd-ac-gn pd-ac-ad him-an pd-ac-po pd-ac-da im-dis ptg, tg1-en, tg2-en ar-dis hpr-dis frr-dis lpx-cr mu-law lin ac-dlb-8k cmp pcm2dc hpx-dis im3 + + pd-ac-pr ac-xgain itac acn/acp a b a b im1 c programmable via cram not programmable switch switch always available available only when bit test-en = 1 pcm in: receive data from pcm or iom-2 interface pcm out: transmit data to pcm or iom-2 interface
duslic operational description product overview 82 2000-11-09 preliminary figure 40 dc test loops slicofi-2s/-2s2 duslic_0023_intstru_slicofi2s_b.wmf pd-dc-ad dc prefi dc adc pd-dc-pr lp + hook ro1 ro1 dc char. rg ro1 + + rtr-sel rng-offset[1:0] pcm2dc dcn/dcp c programmable via cram not programmable pd-dc-da pd-dcbuf pc-pofi-hi dc pofi dc buf dc dac switch switch always available available only when bit test-en = 1 it pd-ofhk offhook comp il pd-gnkc gnk comp c1 pd-hvi hv-int. c2 overt. comp pd-ovtc offset* *o ffset-h [7:0] o ffset-l[7:0] it
duslic interfaces product overview 83 2000-11-09 preliminary 4 interfaces the duslic connects the analog subscriber to the digital switching network by two different types of digital interfaces to allow for the highest degree of flexibility in different applications: pcm interface combined with a serial microcontroller interface iom-2 interface. the pcm/iom-2 pin selects the interface mode. pcm/iom-2 = 0: the iom-2 interface is selected. pcm/iom-2 =1: the pcm/ c interface is selected. the analog tip/ring interface connects the duslic to the subscriber. 4.1 pcm interface with a serial microcontroller interface in pcm/ c interface mode, voice and control data are separated and handled by different pins of the slicofi-2x . voice data are transferred via the pcm highways while control data are using the microcontroller interface. 4.1.1 pcm interface the serial pcm interface is used to transfer a-law or -law-compressed voice data. in test mode, the pcm interface can also transfer linear data. the eight pins of the pcm interface are used as follows (two pcm highways): the fsc pulse identifies the beginning of a receive and transmit frame for both channels. the pclk clock signal synchronizes the data transfer on the dxa (dxb) and dra (drb) lines. on all channels, bytes are serialized with msb first. as a default setting, the rising edge indicates the start of the bit, while the falling edge is used to buffer the contents of the received data on dra (drb). pclk: pcm clock, 128 khz to 8192 khz fsc: frame synchronization clock, 8 khz dra: receive data input for pcm highway a drb: receive data input for pcm highway b dxa: transmit data output for pcm highway a dxb: transmit data output for pcm highway b tca : transmit control output for pcm highway a, active low during transmission tcb : transmit control output for pcm highway b, active low during transmission
duslic interfaces product overview 84 2000-11-09 preliminary if double clock rate is selected (pclk clock rate is twice the data rate), the first rising edge indicates the start of a bit, while, by default, the second falling edge is used to buffer the contents of the data line dra (drb). figure 41 general pcm interface timing fsc pclk dra dxa 125 s tca detail a 0 12 31 3 high 'z' high 'z' fsc pclk dra dxa tca high 'z' high 'z' voice data voice data 0 1 72 3 4 5 6 01 7 23456 bit clock time slot time slot detail a: ezm14046.wmf
duslic interfaces product overview 85 2000-11-09 preliminary the data rate of the interface can vary from 2 128 kbit/s to 2 8192 kbit/s (two highways). a frame may consist of up to 128 time slots of 8 bits each. the time slot and pcm highway assignment for each duslic channel can be programmed. receive and transmit time slots can also be programmed individually. when duslic is transmitting data on dxa (dxb), pin tca (tcb ) is activated to control an external driving device. the dra/b and dxa/b pins may be connected to form a bidirectional data pin for special purposes, e.g., for the serial interface port (sip) with the subscriber line data (sld) bus. the sld approach provides a common interface for analog or digital per-line components. for more details, please see the ? ics for communications ? 1) user ? s manual available from infineon technologies on request. table 24 shows pcm interface examples; other frequencies (e.g., 1536 khz) are also possible. 1) ordering no. b115-h6377-x-x-7600, published by infineon technologies. table 24 slicofi-2x pcm interface configuration clock rate pclk [khz] single/double clock [1/2] time slots [per highway] data rate [kbit/s per highway] 1281 2128 2562 2128 2561 4256 5122 4256 5121 8512 7682 6384 768 1 12 768 1024 2 8 512 1024 1 16 1024 2048 2 16 1024 2048 1 32 2048 4096 2 32 2048 4096 1 64 4096 8192 2 64 4096 8192 1 128 8192 f 1f/64f
duslic interfaces product overview 86 2000-11-09 preliminary 4.1.2 serial microcontroller interface the microcontroller interface consists of four lines: cs , dclk, din and dout. there are two different command types. reset commands have just one byte. read/write commands have two command bytes with the address offset information located in the second byte. a write command consists of two command bytes and the following data bytes. the first command byte determines whether the command is read or write, how the command field is to be used, and which duslic channel (a or b) is written. the second command byte contains the address offset. a read command consists of two command bytes written to din. after the second command byte is applied to din, a dump-byte consisting of ? 1 ? s is written to dout. data transfer starts with the first byte following the ? dump-byte ? . f 2 f/128 f/2 valid pclk clock rates are: f =n 64 khz (2 n 128) cs a synchronization signal starting a read or write access to slicofi-2x . dclk a clock signal (up to 8.192 mhz) supplied to slicofi-2x . din data input carries data from the master device to the slicofi-2x . dout data output carries data from slicofi-2x to a master device. table 24 slicofi-2x pcm interface configuration
duslic interfaces product overview 87 2000-11-09 preliminary figure 42 serial microcontroller interface write access 1) figure 43 serial microcontroller interface read access 1) for n data bytes and single byte command comm 1st dclk din cs comm 2nd data data data data byte 1 data byte n comm 1st din cs ezm14057.wmf comm 1st dclk din dout cs comm 2nd 'dump byte' data data data data byte 1 data byte n * high impedance * * ezm14058.wmf
duslic interfaces product overview 88 2000-11-09 preliminary programming the microcontroller interface without clocks at fsc, mclk, pclk the slicofi-2x can also be programmed via the c interface without any clocks connected to the fsc, mclk, pclk pins. this can be useful in power down modes when further power saving on system level is necessary. in this case a data clock of up to 1.024 mhz can be used on pin dclk. since the slicofi-2x will leave the basic reset routine only if clocks at the fsc, mclk and pclk pins are applied, it is not possible to program the slicofi-2x without any clocks at these pins directly after the hardware reset or power on reset.
duslic interfaces product overview 89 2000-11-09 preliminary 4.2 the iom-2 interface iom-2 defines an industry-standard serial bus for interconnecting telecommunication ics for a broad range of applications - typically isdn-based applications. the iom-2 bus provides a symmetrical full-duplex communication link containing data, control/programming and status channels. providing data, control and status information via a serial channel reduces pin count and cost by simplifying the line card layout. the iom-2 interface consists of two data lines and two clock lines as follows: slicofi-2x handles data as described in the iom-2 specification 1) for analog devices. figure 44 iom-2 int. timing for up to 16 voice channels (per 8 khz frame) du: data upstream carries data from the slicofi-2x to a master device. dd: data downstream carries data from the master device to the slicofi-2x . fsc: a frame synchronization signal (8 khz) supplied to slicofi-2x . dcl: a data clock signal (2048 khz or 4096 khz) supplied to slicofi-2x . 1) available on request from infineon technologies. 125 s voice channel a voice channel a voice channel b voice channel b fsc dcl dd du detail a ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 detail a dd du monitor channel monitor channel c/i channel c/i channel mr mx mr mx ezm04104.emf
duslic interfaces product overview 90 2000-11-09 preliminary the information is multiplexed into frames, which are transmitted at an 8-khz rate. the frames are subdivided into 8 sub-frames, with one sub-frame dedicated to each transceiver or pair of codecs (in this case, two slicofi-2x channels). the sub-frames provide channels for data, programming and status information for a single transceiver or codec pair. figure 45 iom-2 interface timing (dcl = 4096 khz, per 8 khz frame) fsc dcl dd du 4096 khz detail b detail b fsc dcl bit n bit 0 bit 1 dd/du 125 s ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ezm04105.emf
duslic interfaces product overview 91 2000-11-09 preliminary figure 46 iom-2 interface timing (dcl = 2048 khz, per 8-khz frame) both duslic channels (see figure 44 ) can be assigned to one of the eight time slots. set the iom-2 time slot selection as shown in table 25 below by pin-strapping. in this way, up to 16 channels can be handled with one iom-2 interface on the line card. 2 mhz or 4 mhz dcl is selected by the sel24 pin: sel24 = 0: dcl = 2048 khz sel24 = 1: dcl = 4096 khz table 25 iom-2 time slot assignment ts2 ts1 ts0 iom-2 operating mode 0 0 0 0 0 0 1 1 0 1 0 1 time slot 0; dcl = 2048, 4096 khz time slot 1; dcl = 2048, 4096 khz time slot 2; dcl = 2048, 4096 khz time slot 3; dcl = 2048, 4096 khz 1 1 1 1 0 0 1 1 0 1 0 1 time slot 4; dcl = 2048, 4096 khz time slot 5; dcl = 2048, 4096 khz time slot 6; dcl = 2048, 4096 khz time slot 7; dcl = 2048, 4096 khz fsc dcl dd du 2048 khz detail c detail c fsc dcl bit n bit 0 bit 1 dd/du 125 s ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ezm04106.emf
duslic interfaces product overview 92 2000-11-09 preliminary 4.3 tip/ring interface the tip/ring interface is the interface that connects the subscriber to the duslic. it meets the itu-t recommendation q.552 for a z-interface and applicable lssgr. 4.4 slicofi-2s/-2s2 and slic-s/-s2 interface the slic-s/-s2 peb 4264/-2 operates in the following modes controlled by a ternary logic signal at the c1 and c2 input: figure 47 interface slicofi-2s/-2s2 and slic-s/-s2 table 26 slic-s/-s2 interface code c2 (pin 17) lmh c1 (pin 18) l 1) 1) no ? overtemp ? signaling possible via pin c1 if c1 is low. pdh pdrhl pdrh m actl acth actr h unused hit hir ezm29204.emf acna dcna acpa dcpa agnd vdd(3.3 v) c1a c ext acp c1 vhr peb 4264/-2 dcp dcn acn peb 3264/-2 c2a c2 bgnd vcms tip ring vbath (sub) agnd vdd (+5 v) vbatl vcms vcmita itaca ita ila it il vcm i t i r bias logik current sensor (i r + i t ) / 100 60k 60k (i r - i t ) / 200 vhi vhi vhi off-hook vh switch + + - - symfi vbi vbat switch vbi 10k 2k 2k 10k 2k 2k 2k (i ro + i to ) / 10 5k bgnd pdrhl pdrh pdrhl pdrh 5k i to i ro r ila r it1a r it2a s1, s2 closed: actr, hit, hir s1 s1 s2 c ita c vcmita
duslic interfaces product overview 93 2000-11-09 preliminary 4.5 slicofi-2 and slic-e/-e2 interface the slic-e/-e2 peb 4265/-2 operates in the following modes controlled by a ternary logic signal at the c1 and c2 input: figure 48 interface slicofi-2 and slic-e/-e2 table 27 slic-e/-e2 interface code c2 lmh c1 l 1) 1) no ? overtemp ? signaling possible via pin c1 if c1 is low. pdh pdrhl pdrh m actl acth actr h hirt hit hir ezm20204.emf acna dcna acpa dcpa agnd vdd(3.3 v) c1a c ext acp c1 vhr peb 4265/-2 dcp dcn acn peb 3265 c2a c2 bgnd vcms tip ring vbath (sub) agnd vdd (+5 v) vbatl vcms vcmita itaca ita ila it il vcm i t i r bias logik current sensor (i r + i t ) / 100 60k 60k (i r - i t ) / 200 vhi vhi vhi off-hook vh switch + + - - symfi vbi vbat switch vbi 10k 2k 2k 10k 2k 2k 2k (i ro + i to ) / 10 5k bgnd pdrhl pdrh pdrhl pdrh 5k i to i ro r ila r it1a r it2a s1, s2 closed: actr, hit, hir, hirt s1 s2 c ita c vcmita
duslic interfaces product overview 94 2000-11-09 preliminary 4.6 slicofi-2 and slic-p interface the slic-p peb 4266 operates in the following modes controlled by a ternary logic signal at the c1, c2 inputs and a binary logic signal at c3 input: figure 49 interface slicofi-2 and slic-p table 28 slic-p interface code c2 lmh l 1) 1) no ? overtemp ? signaling possible via pin c1 if c1 is low. pdh pdrr pdrrl pdrhl pdrh c1 m actl acth actr h hirt hit hir rot ror c3 = h or l c3 = h 2) c3 = l 2) 2) c3 pin of slic-p is typically connected to io2 pin of slicofi-2. for extremely power-sensitive applications using external ringing the c3 pin can be connected to gnd. ezm14041.emf acna dcna acpa dcpa agnd vdd(+3.3 v) c1a c ext acp c1 dcp dcn acn peb3265 io2a c3 vcms c2a c2 ring agnd vdd(+5 v) tip vbatr (sub) vbath vbatl peb 4266 bgnd vcms c vcmita c ita ita ila it il vcm i t i r bias current sensor (i r + i t ) / 100 60k 60k (i r - i t ) / 200 off-hook + + - - symfi battery switch vbi vbi bgnd 10k 2k 2k 10k 2k 2k 2k 5k bgnd pdrr pdrrl pdrh pdrhl pdrr pdrrl 5k (i r0 + i t0 ) / 10 logic pdrh pdrhl i t0 i r0 r it1a r ila r it2a s1, s2 closed: actr, rot, ror, hit, hir, hirt s1 s2 vcmita itaca
duslic application circuits product overview 95 2000-11-09 preliminary 5 application circuits application circuits are shown for internal ringing with duslic-e/-e2/-s/-p (balanced and unbalanced) and for external unbalanced ringing with duslic-e/-e2/-s/-s2/-p for one line. channel a and the slic have to be duplicated in the circuit diagrams to show all components for 2 channels. 5.1 internal ringing (balanced/unbalanced) internal balanced ringing is supported up to 85 vrms for duslic-e/-e2/-p and up to 45 vrms for duslic-s. internal unbalanced ringing is supported for slic-p with ringing amplitudes up to 50 vrms without any additional external components. off-hook detection and ring trip detection are also fully internal in the duslic chip set.
duslic application circuits product overview 96 2000-11-09 preliminary 5.1.1 circuit diagram internal ringing figure 50 application circuit, internal ringing (balanced & unbalanced) as shown in figure 50 both balanced and unbalanced internal ringing uses the same line circuit. note: only the codec/slic combinations shown in table 1 "duslic chip sets" on page 2 are possible. ezm14042.emf fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs mclk sel24/dra dxa dxb rsync acpa acna dcpa dcna c1a c2a cdcna cdcpa itaca ita vcmita ila vcm vcms cref gndr test c dc slicofi-2 slicofi-2s (channel a, b) c itaca c vcmita r it1a slic-e/-e2 slic-s slic-p r it2a r ila acp acn dcp dcn c1 c2 v dda v ddr v ddd v ddpll c 1 agnd c 1 agnd c 1 agnd c 1 agnd gnda gndd gndpll agnd agnd agnd c ref vcms agnd il it v hr v dd v bath v batl c 1 agnd c 1 bgnd c 1 bgnd bgnd agnd cext bgnd agnd agnd c ext ring tip r stab r stab c stab c stab bgnd protection channel a v cca v cca v cca v cca v bath v batl c 1 bgnd v h peb 3265 peb 3264 peb 4265/-2 peb 4264 peb 4266 reset tcb tca pcm/iom-2 io1a io3a io4a io1b io2b io3b io4b io2a v ccs c3 * optional for slic -p * agnd agnd selclk agnd in t connected to io2a
duslic application circuits product overview 97 2000-11-09 preliminary 5.1.2 protection circuit for slic-e/-e2 and slic-s a typical overvoltage protection circuit for slic-e/s is shown in figure 51 . other proved application schemes are available on request. . figure 51 typical overvoltage protection for slic-e/-e2 and slic-s the lcp02 (from stm) protects against overvoltage strikes exceeding v hr and v bath . protection resistors must be rated for lightning pulses. in case of power contact, protection resistors must become high impedance or additional fuses are needed. slic-e/-e2 peb 4265/-2 slic-s peb 4264 r stab 30 ? r stab 30 ? tip ring vhr vbath lcp02 r prot 20 ? fuseable resistor tip ring gp gn gnd c p c p c stab c stab r prot 20 ? fuseable resistor ezm14070.emf
duslic application circuits product overview 98 2000-11-09 preliminary 5.1.3 protection circuit for slic-p a typical protection circuit for slic-p is shown in figure 52 . other proved application schemes are available on request. figure 52 typical overvoltage protection for slic-p the gate trigger voltage of the battrax b1160cc (teccor) can be set down to the battery voltage of v batr ( ? 150 v). protection resistors must be rated for lightning pulses. in case of power contact, protection resistors must become high impedance or additional fuses are needed. ezm14048.emf slic-p peb 4266 tip ring c stab 15nf c stab 15nf r stab 30 ? r stab 30 ? r prot 20 ? fusable resistor r prot 20 ? fusable resistor bgnd bgnd protection b1160cc vbatr mb2s
duslic application circuits product overview 99 2000-11-09 preliminary for handling higher electromagnetic compatibility (emc) requirements, additional effort in the circuit design may be necessary, e.g., a current-compensated choke of 470 h in the ring/tip lines. additionally to the capacitors c 1 a 22 f capacitor per 8 ring/tip lines is recommended for buffering the supply voltages. 5.1.4 bill of materials (including protection) table 29 shows the external passive components needed for a dual channel solution consisting of one slicofi-2/-2s and two slic-e/-e2/-s/-p. table 29 external components in application circuit for duslic-e/-e2/-s/-p no. symbol value unit tolerance rating duslic -e/-e2/-s duslic -p 2 r it1 470 ? 1% x x 2 r it2 680 ? 1% x x 2 r il 1.6 k ? 1% x x 4 r stab 30 ? 1% 1) xx 4 r prot 20 ? 1% 1) xx 4 c stab 15 nf 10 % see 2) xx 2 c dc 120 nf 10 % 10 v x x 2 c itac 680 nf 10 % 10 v x x 2 c vcmit 680 nf 10 % 10 v x x 1 c ref 68 nf 20 % 10 v x x 2 c ext 470 nf 20 % 10 v x x 12 c 1 100 nf 10 % x x 2 battrax b1160cc ?? according to supply voltage v batr x 2 diode- bridge mb2s x 2 stm lcp-02 x 4 c p 220 nf 20 % according to supply voltage v bath and v hr x 1) matching tolerance is dependent on longitudinal balance requirement 2) according to the highest used battery voltage i v batr i for slic-p and i v hr i or i v bath i for slic-e/-e2/-s
duslic application circuits product overview 100 2000-11-09 preliminary 5.2 external unbalanced ringing with duslic-e/-e2/-s/-s2/-p external unbalanced ringing applications are shown for a standard solution (see figure 53 ) and for a solution dedicated to higher loop lengths (see figure 54 ). note: only the codec/slic combinations shown in table 1 "duslic chip sets" on page 2 are possible. figure 53 application circuit, external unbalanced ringing this circuit senses the ring current on only one line (tip line). it is therefore restricted to applications with low longitudinal influence (short lines). ezm14044.emf r s t a b r s t a b c s t a b c s t a b b g n d p r o t e c t i o n e x t e r n a l r i n g g e n e r a t o r r s y n c / s l i c o f i - 2 + 5 v fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs mclk sel24/dra dxa dxb rsync acpa acna dcpa dcna c1a c2a cdcna cdcpa itac a ita vcmita ila vcm vcms cref gndr test c dc slicofi-2 slicofi-2s/-2s2 (channel a, b) c itaca c vcmita r it1a slic-e/-e2 slic-s/-s2 slic-p r it2a r ila acp acn dcp dcn c1 c2 v dda v ddr v ddd v ddpll c 1 agnd c 1 agnd c 1 agnd c 1 agnd gnda gndd gndpll agnd agnd agnd c ref vcms agnd il it v hr v dd v bath v batl c 1 agnd c 2 bgnd c 2 bgnd bgnd agnd cext bgnd agnd agnd c ext ring tip channel a v cca v cca v cca v cca v bath v batl peb 4265/-2 peb 4264/-2 peb 4266 peb 3265 peb 3264/-2 io 1a io 3a io 4a io 1b io 2b io 3b io 4b io 2a reset tcb tca int pc m /io m -2 v ccs c3 * optional for slic-p * agnd selclk agnd 1 n 4 1 4 8 1 n 4 1 4 8 connected to io2a
duslic application circuits product overview 101 2000-11-09 preliminary figure 54 application circuit, external unbalanced ringing for long loops for handling higher electromagnetic compatibility (emc) requirements, additional effort in the circuit design may be necessary, e.g., a current-compensated choke of 470 h in the ring/tip lines. this circuit senses the ring current in both tip and ring lines. longitudinal influence is cancelled out. this circuit therefore is recommended for long line applications. pcm /io m -2 fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs in t mclk sel24/dra dxa dxb tca tcb rsync acpa acna dcpa dcna c1a c2a cdcna cdcpa itac a ita vcmita ila vcm vcms cref gndr reset test c dc slicofi-2 slicofi-2s/-2s2 (channel a, b) c itaca c vcmita r it1a slic-e/-e2 slic-s/-s2 slic-p r it2a r ila acp acn dcp dcn c1 c2 v dda v ddr v ddd v ddpll c 1 agnd c 1 agnd c 1 agnd c 1 agnd gnda gndd gndpll agnd agnd agnd c ref vcms agnd il it v hr v dd v bath v batl c 1 agnd c 2 bgnd c 2 bgnd bgnd agnd cext bgnd agnd agnd c ext ring tip r stab r stab c stab c stab bgnd protection channel a v cca v cca v cca v cca 5v v bath v batl peb 3265 peb 3264/-2 peb 4265/-2 peb 4264/-2 peb 4266 + 68k 68k vc m s/slico fi-2/-2s/-2s2 io 3a or io 4a of slic o fi-2/-2s/-2s2 ring generator ? 48vdc 80v rms zero crossing signal (ttl level) r syn c/slic ofi-2/-2s/-2s2 + 5v ring tip io 1a io 3a io 4a io 1b io 2b io 3b io 4b - 150 ? 2m 150 ? 2m 2m 2m r prot r prot lm358 relay c3 * * optional for slic-p agnd selclk agnd 1 n 4 1 4 8 1 n 4 1 4 8 connected to io2a ezm35003.emf
duslic index preliminary product overview 102 2000-11-09 6 index numerics 170v technology 27 a active 60 active high 52, 54, 56, 58 active low 52, 54, 56, 58 active ring 52, 54, 56, 59 active state 36, 62 active with hir 53, 55, 57, 59 active with hit 53, 55, 57, 59 active with metering 53 b balanced ringing 95 battery feed 9 c caller id 5, 12 central office 6 coding 9 d digital loop carrier 6 dtmf 12 dtmf decoder 5 dtmf generator 5 duslicos 11 e enhanced digital signal processor 40 external components duslic-p 99 external conference 49 external ringing 32, 75 f fiber in the loop 6 frequency response 11 fsk 12 g ground start 53 h hybrid 9 hybrid balance 11 i impedance matching 11 intelligent nt 6 internal conference 49 iom-2 interface 83, 89 isdn terminal adapters 6 l levelmeter ac 77 dc 77 lin mode 51 lin16 mode 51 line echo cancellation 12 line resistance 70 m message waiting 5 metering 5 microcontroller interface 83, 86 o operating modes duslic-e/-e2 56 duslic-p 58 duslic-s/-s2 54 overvoltage protection 9 p pcm interface 24, 83 pcm mode 50 pcm/c interface 50, 83 pcm16 mode 51 pcm-active 49 pcm-off 49
duslic index preliminary product overview 103 2000-11-09 polarity reversal 5 power dissipation operating modes 60 power down 60 power down high impedance 52 power down resistive 54, 56, 58 power down state 36, 49, 62 power management 2, 5, 52, 60 private branch exchange 6 r ramp generator 47, 55, 57, 59 read command 86 receive gain 11 ring on ring 53 ring on tip 53 ring pause 53, 55, 57, 59 ring trip 53 ringing 9, 53, 54, 57, 59, 61 s second command byte 86 signaling 9, 41 sleep 56, 58 slic interface 92, 93 supervision 9 t teletax metering 12 testing 75 time slot assignment 24 tip/ring interface 83 transmit gain 11 ttx 11, 37, 53 u unbalanced ringing 61 universal tone detection 12 v voice over packet network 6 voltage reserve 15 w wireless local loop 6 write command 86
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