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application note R01AN1504EJ0100 rev. 1.00 p age 1 of 47 feb. 14, 2014 rl78/g14 using the dtc to perform continuous clock synchronous serial communication abstract this document describes how to perform continuous clock synchronous serial communication using the serial arra y unit (3 - wire serial i/o) and dtc in the rl78/g14 . products rl78/g14 when using this application note with other renesas mcus, careful evaluation is re commended after making modifications to comply with the alternate mcu. R01AN1504EJ0100 rev. 1.00 feb. 14, 2014
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 2 of 47 feb. 14, 2014 contents 1. specifications ................................ ................................ ................................ ................................ ..... 3 2. operation conf irmation conditions ................................ ................................ ................................ .... 4 3. hardware ................................ ................................ ................................ ................................ ............ 5 3.1 hardware configuration ................................ ................................ ................................ ............... 5 3.2 pins used ................................ ................................ ................................ ................................ ..... 5 4. software ................................ ................................ ................................ ................................ ............. 6 4.1 operation overview ................................ ................................ ................................ ..................... 7 4.2 sect ion composition ................................ ................................ ................................ .................. 10 4.3 option byte settings ................................ ................................ ................................ .................. 10 4.4 constant ................................ ................................ ................................ ................................ ..... 10 4 .5 variables ................................ ................................ ................................ ................................ .... 10 4.6 functions ................................ ................................ ................................ ................................ .... 11 4.7 function specifications ................................ ................................ ................................ .............. 11 4.8 flowcharts ................................ ................................ ................................ ................................ .. 15 4.8.1 overall flow ................................ ................................ ................................ ........................ 15 4.8.2 initialization ................................ ................................ ................................ ......................... 15 4.8.3 peripheral function initialization ................................ ................................ ......................... 16 4.8.4 cpu clock initialization ................................ ................................ ................................ ...... 16 4.8.5 sau0 initialization ................................ ................................ ................................ ............... 17 4.8.6 csi00 initialization ................................ ................................ ................................ .............. 19 4.8.7 csi00 operation start ................................ ................................ ................................ ........ 28 4.8.8 csi00 transmission /reception start ................................ ................................ ................. 31 4.8.9 csi00 transfer end interrupt ................................ ................................ ............................. 33 4.8.10 csi00 receive end callback function ................................ ................................ ............. 35 4.8.11 csi00 error callback function ................................ ................................ .......................... 35 4.8.12 dtc initialization ................................ ................................ ................................ ............... 36 4.8.13 dtcd0 operat ion start ................................ ................................ ................................ ..... 43 4.8.14 dtcd0 operation stop ................................ ................................ ................................ ..... 44 4.8.15 main processing ................................ ................................ ................................ ................ 45 4.8.16 main initialization ................................ ................................ ................................ ............... 46 4.8.17 transmit data setting ................................ ................................ ................................ ........ 46 5. sample code ................................ ................................ ................................ ................................ .... 47 6. reference documents ................................ ................................ ................................ ...................... 47
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 3 of 47 feb. 14, 2014 1. specifications in this application note, the s erial a rray u nit (sau) and dtc are used to successively transmit and receive 8 - bit data. the sau is used as a 3 - wire serial i/o interface to output a transfer clock from the sck00 pin, output transmit data from the so00 pin, and input receive data to the si00 pin. the dtc transfers transmit data and receive data from the transmission source address to the destination address. the d tc is activated by the 3 - wire serial i/o interface transfer end . table 1 . 1 lists the peripherals functions and their applications. figure 1 . 1 shows the timing and communication format. table 1 . 1 peripheral functions and their applications peripheral function application sau (unit 0, channel 0) performs clock synchronous serial communication dtc transfers transmit data and receive data sck00 pin dtc is activated (transfers the transmit and receive data) transmit/receive first byte d7 d6 d5 d4 d3 d2 d1 d0 so00 pin d7 d6 d5 d4 d3 d2 d1 d0 si00 pin 104 s (9600 bps) second byte third byte fourth byte fifth byte sixth byte seventh byte eighth byte figure 1 . 1 timing and communication format
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 4 of 47 feb. 14, 2014 2. operation confirmation conditions the sample code accompanying this application note has been run and confirmed under the conditions below. table 2 . 1 operation confirmation conditions item contents mcu used rl78/g14 (r5f104pja) operating frequencies ? high - speed on - chip oscillator clock (f hoco ): 32 mhz (typical) ? cpu/peripheral hardware clock (f clk ): 32 mhz operating voltage 5.0 v (operation enabled from 2.9 to 5.5 v) lvd operation (v lvi ): 2.81 v at the rising edge or 2.75 v at the falling edge in reset mode integrated development environment r enesas electronics corporation cubesuite+ v1.03.00 c compiler renesas electronics corporation ca78k0r v1.60 rl78/g14 code library renesas electronics corporation codegenerator for rl78/g14 v1.01.03.06
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 5 of 47 feb. 14, 2014 3. hardware 3.1 hardware config u ration figure 3 . 1 shows a connection example . rl78/g14 ev dd0 v dd regc ev ss0 v ss v dd v dd p50/si00 p51/so00 p30/sck00 notes: 1. the above figure is simplified to show an overview of the hardware connection. when designing circuits, make sure to handle unused pins appropriately to satisfy the electrical characteristics. connect input-only ports independently to either v dd or v ss via resistors. 2. connect pins with names that begin with ev ss to v ss , and pins with names that begin with ev dd to v dd . 3. make sure to set vdd greater than the detection voltage (v lvi ) specified by the lvd. serial data input serial data output serial clock output p40/tool0 on-chip debugging reset figure 3 . 1 connection example 3.2 pins used table 3 . 1 lists the pins used and their functions. table 3 . 1 pins used and their functions pin name i/o function p50/si00 input serial data input p51/so00 output serial data output p30/sck output serial clock o utput
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 6 of 47 feb. 14, 2014 4. software as the sample code is created by editing the functions generated by the rl78/g14 code library, the code generator property has been modified. figure 4 . 1 shows the code generator property setting. 2 . select ?g do nothing if file exists ?h from the drop - down menu . 1 . open code generator ( design tool ). figure 4 . 1 c o de generator property setting
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 7 of 47 feb. 14, 2014 4.1 operation overview rl78/g14 transfers the receive data using the dtc control data 0 (dtcd0), and transfers the transmit data using the dtc control data 1 (dtcd1), and thus successively transmits and receives 8 - byte data. note that the program transfers the first byte of transmit data and the eighth byte of receive data. settings for the peripheral functions are listed below . sau ? use single transfer mode ? set the data length to 8 bit s ? set the data transfer sequence to msb first ? set the data transmit/receive timing to type 1 ? set the baud rate to 9600 bps ? set the interrupt priority to low dtcd0 ? set the activation source to csi00 transfer end ? enable the chain transfer ? set the transfer mode to normal mode ? set the data length to 8 bit s ? set the transfer source to fff10h (sio00 register address), fixed ? set the transfer destination to fe900h, incremented ? set the number of transfers to seven ? set the transfer block size to 1 byte dtcd1 ? set the activation source to dtc0 transfer end ? disable the chain transfer ? set the t ransfer mode to normal mode ? set the data length to 8 bit s ? set the transfer source to fe911h, incremented ? set the transfer destination to fff10h (sio00 register address), fixed ? set the transfer block size to 1 byte
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 8 of 47 feb. 14, 2014 figure 4 . 2 sho ws transmit and receive timing, and dtc activation. figure 4 . 3 shows the operation of dtcd0. figure 4 . 4 shows the operation of dtcd1. transmit/receive first byte (1) (2) (4) (3) dtcct0 second byte third byte fourth byte fifth byte sixth byte seventh byte eight byte 7 6 5 4 3 2 1 0 dtc is activated csi00 transfer end intcsi00 interrupt figure 4 . 2 timing of transmission/reception and dtc activation (1) t ransmission/reception start rl78/g14 starts transmission and reception a fter the dtc is configured. transmission is performed by the program writing the first byte of transmit data to the sio00 register. (2) dtc activation after the first byte of data has been transmitted and received, dtc0 is activated. the first byte of rece ive data is transferred from the sio00 register to the transfer destination address. when transfer of the receive data is completed, dtc1 is activated. the second byte of transmit data from the transmit source address is transferred to the sio00 register. when the transmit data is written to the sio00 register, the next transmission and reception start. the dtc is activate d every time when the transmission and reception are completed and the same procedure is repeated until the transmission and reception o f the eighth byte data is started . the dtcct0 register value decrement s each time the dtc transfer is activated. (3) intcsi00 interrupt generated by the dtc transfer end when the dtcct0 register becomes 0, the intcsi00 interrupt occurs. preparations to com plete transmission and reception are performed in the program. (4) intcsi00 interrupt generated by transmission/reception end when the transmission and reception of the eighth byte of data is completed, the intcsi00 interrupt occurs. the p rogram reads and copies the eighth byte of receive data.
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 9 of 47 feb. 14, 2014 sio00 (receive data) fff10h rcv_data[0] rcv_data[1] rcv_data[2] rcv_data[3] rcv_data[4] rcv_data[5] rcv_data[6] rcv_data[7] dtc transfer fe900h fe901h fe902h fe903h fe904h fe905h fe906h fe907h transfer by a program figure 4 . 3 dtcd0 operation sio00 (transmit data) dtc transfer fff10h???n snd_data[0] snd_data[1] snd_data[2] snd_data[3] snd_data[4] snd_data[5] snd_data[6] snd_data[7] fe910h fe911h fe912h fe913h fe914h fe915h fe916h fe917h transfer by a program figure 4 . 4 dtcd1 operation
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 10 of 47 feb. 14, 2014 4.2 section composition table 4 . 1 lis ts the sections used in the sample code . table 4 . 1 sections used in the sample code section nam e address reference variable description dtc0dst 0fe900h rcv_data[] dtcd0 transfer destination address dtc1sr c 0fe910h snd_data[] dtcd1 transfer source address 4.3 option byte setting s table 4 . 2 lists the option byte settings . table 4 . 2 option byte setting s address setting value contents 0 00c0h/010c0h 11101111b stops the watchdog time r (counting is stopped when a reset is canceled) 000c1h/010c1h 01111111b sets the lvd in reset mode detection voltage: 2.81 v at the rising edge, 2.75 v at the falling edge 000c2h/010c2h 11101000b sets the ho co clock as 32 mhz in high - speed main (hs) mode 000c3h/010c3h 10000100b e nables on - chip debugging 4.4 constant table 4 . 3 lists the constant used in the sample code . table 4 . 3 consta nt used in the sample code constant name setting value contents tx_rx_data_size 8 bytes transmit/ receive data size 4.5 variables table 4 . 4 lists the global variables, and table 4 . 5 lists the static variabl e . table 4 . 4 global variables type variable name contents function used uint8_t rcv_data[] receive data r_main_userinit r_csi00_interrupt r_csi00_callback_receiveend uint8_t snd_data[] transmit data r_csi 00_send_receive transmit_data_set uint8_t set_rcv_data[] store the receive data r_csi00_callback_receiveend uint8_t csi_status transmission/reception end status main r_main_userinit r_csi00_callback_receiveend
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 11 of 47 feb. 14, 2014 table 4 . 5 s tatic variable type variable name contents function used md_status md_status status flag main 4.6 function s table 4 . 6 lists the functions . table 4 . 6 functions fu nction name outline hdwinit initialization r_systeminit peripheral function initialization r_cgc_create cpu clock initialization r_sau0_create sau0 initialization r_csi00_create csi00 initialization r_csi00_start csi00 operation start r_csi00_send_r eceive csi00 transmission/reception start r_csi00_interrupt csi00 transfer end interrupt r_csi00_callback_receiveend csi00 receive end callback function r_csi00_callback_error csi00 error callback function r_dtc_create dtc initialization r_dtcd0_start dtcd0 operation start r_dtcd0_stop dtcd0 operation stop main m ain processing r_main_userinit m ain initialization transmit_data_set transmit data setting 4.7 function specifications the following tables list the sample code function specifications. hdw init outline initialization header none declaration void hdwinit(void) description initializes the peripheral functions . argument s none return v alue none
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 12 of 47 feb. 14, 2014 r_systeminit outline peripheral function initialization header none declaration void r_ systeminit(void) description initializes the peripheral function s used in this application note. argument s none return v alue none r_cgc_create outline cpu clock initialization header r_cg_cgc.h declaration void r_cgc_create(void) description ini tializes the cpu clock. argument s none return v alue none r_sau0_create outline sau0 initialization header r_cg_serial.h declaration void r_sau0_create(void) description initializes sau0. arguments none return value none r_csi00_create outl ine csi00 initialization header r_cg_serial.h declaration void r_csi00_create(void) description initializes csi00. arguments none return value none r_csi00_ start outline csi00 operation start header r_c g _serial.h declaration void r_csi00_start( void) description starts csi00 operation. arguments none return value none
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 13 of 47 feb. 14, 2014 r_csi00_ send_receive outline csi00 transmit/receive start header r_cg_serial.h declaration md_status r_csi00_send_receive(uint8_t * const tx_buf, uint16_t tx_num, uint8_ t * const rx_buf) description prepares the data buffer for csi00 communication (transmission/reception) and sets the first byte of the transmit data. arguments uint8_t * const tx_buf : transmit data buffer pointer uint16_t tx_num : transmit data size uint8_t * const rx_buf : receive data buffer pointer return value md_ok : setting is completed, operation started md_argerror : argument is incorrect r_csi00_interrupt outline csi00 transfer end interrupt header none declaration __ interrupt stati c void r_csi00_interrupt(void) description performs csi00 transfer end interrupt handling . arguments none return value none r_csi00_ callback_receiveend outline csi00 receive end callback function header r_cg_serial.h declaration static void r_csi 00_callback_receiveend(void) description this function is called when receiving the specified number of bytes of data is completed. 8 bytes of receive data are copied to set_rcv_data[tx_rx_data_size] . arguments none return value none r_csi00_callba ck_error outline csi00 error callback function header r_cg_serial.h declaration static void r_csi00_callback_error(uint8_t err_type) description this function is called when the csi00 error occurs. arguments uint8_t err_type : error type return value none remarks the s ample code does not include the error processing. add processing to the user program as needed.
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 14 of 47 feb. 14, 2014 r_dtc_create outline dtc initialization header r_cg_dtc.h declaration void r_dtc_create(void) description initializes the dtc . argu ments none return value none dtcd0_start outline dtcd0 operation start header r_cg_dtc.h declaration void r_dtcd0_start(void) description starts the dtcd0 operation. arguments none return value none r_dtcd0_stop outline dtcd0 operation stop header r_cg_dtc.h declaration void r_dtcd0_stop(void) description stops the dtcd0 operation. arguments none return value none main outline main processing header none declaration void main(void) description performs the main processing. argu ments none return value none r_main_userinit outline main initialization header none declaration void r_main_userinit(void) description performs processing required to initialize the main processing. arguments none return value none
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 15 of 47 feb. 14, 2014 transm it_data_set outline transmit data setting header none declaration static void transmit_data_set(void) description sets the transmit data. arguments none return value none 4.8 flowchart s 4.8.1 overall flow figure 4 . 5 shows the over all flow . _@cstart initialization function hdwinit () _@cend main() figure 4 . 5 o verall flow 4.8.2 initialization fi gure 4 . 6 shows the initialization. hdwinit disable maskable interrupts initialize the peripheral functions r_systeminit() return ie 0 cpu clock initialization sau0 initialization dtc initialization figure 4 . 6 initialization
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 16 of 47 feb. 14, 2014 4.8.3 peripheral f unction initialization figure 4 . 7 shows the peripheral function initialization. r _ systeminit disable the peripheral i / o redirect function pior 0 register 00 h pior 1 register 00 h return initialize the cpu r _ cgc _ create () cpu clock initialization r _ cgc _ create () sau 0 initialization r _ sau 0 _ create () dtc initialization r _ dtc _ create () figure 4 . 7 peripheral function initialization 4.8.4 cpu clock initialization figure 4 . 8 shows the cpu clock initialization r _ cgc _ create set the x 1 and xt 1 oscillators not to be used return stop the high - speed system clock csc register mstop bit 1 : x 1 oscillator stopped set the main system clock ckc register mcm 0 bit 0 : selects the high - speed on - chip oscillator clock as the main system clock set the subsystem clock to stopped csc register xtstop bit 1 : xt 1 oscillator stopped ckc register css bit 0 : main system clock set the cpu / peripheral hardware clock set the high - speed on - chip oscillator to operate csc register hiostop bit 0 cmc register 00 h exclk bit = 0 , oscsel bit = 0 : high - speed system clock pin operation mode : input port mode exclks bit = 0 , oscsels bit = 0 subsystem clock pin operation mode : input port mode set the operating clock of the real - time clock and interval timer osmc register 10 h wutmmck 0 bit 1 : selects the low - speed on - chip oscillator clock figure 4 . 8 cpu clock initialization
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 17 of 47 feb. 14, 2014 4.8.5 sau0 initialization figure 4 . 9 shows the sau0 initialization. r _ sau 0 _ create enable input clock supply to sau 0 wait for 4 clocks of f clk per 0 register sau 0 en bit 1 : enables input clock supply set the sau 0 operating clock csi 00 initialization r _ csi 00 _ create () sps 0 register 0004 h bits prs 003 to prs 000 = 0100 b : f clk / 2 4 return figure 4 . 9 sau0 initialization enabling input clock supply to sau0 ? peripheral enable regis ter 0 (per0) symbol 7 6 5 4 3 2 1 0 per0 rtcen iica1en adcen iica0en sau1en sau0en tau1en tau0en value 1 ? bit 2 sau0en bit control of serial array unit 0 input clock supply 0 stops supply of input clock ? sfr used by serial array unit 0 ca nnot be written. ? serial array unit 0 is in the reset status. 1 enables input clock supply ? sfr used by serial array unit 0 can be read/written. for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 18 of 47 feb. 14, 2014 setting the sau0 operating clock ? serial clock select register 0 (sps0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sps0 0 0 0 0 0 0 0 0 prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 value ? ? ? ? ? ? ? ? 0 1 0 0 ? bits 3 to 0 prs 003 prs 002 prs 001 prs 000 select the operating clock (ck00) f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz f clk = 32 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 32 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mh z 1 6 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 8 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 4 mhz 0 1 0 0 f clk /2 4 125 khz 313 khz 625 k hz 1.25 mhz 2 mhz 0 1 0 1 f clk /2 5 62.5 khz 156 khz 31 3 k hz 625 k hz 1 m hz 0 1 1 0 f clk /2 6 31.3 khz 78.1 khz 156 k hz 313 k hz 500 k hz 0 1 1 1 f clk /2 7 15.6 khz 39.1 khz 78.1 k hz 156 k hz 250 k hz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 k hz 78.1 k hz 125 k hz 1 0 0 1 f clk /2 9 3.91 khz 9.7 7 khz 19.5 k hz 39.1 k hz 62.5 k hz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.77 k hz 19.5 k hz 31.3 k hz 1 0 1 1 f clk /2 11 97 7 hz 2.44 khz 4.88 k hz 9.7 7 k hz 1 5 . 6 k hz 1 1 0 0 f clk /2 12 488 hz 1.22 khz 2.44 k hz 4.88 k hz 7.8 k hz 1 1 0 1 f clk /2 13 244 hz 610 hz 1.22 k hz 2.44 k hz 3.9 k hz 1 1 1 0 f clk /2 14 122 hz 305 hz 610 hz 1.22 khz 1.95 khz 1 1 1 1 f clk /2 15 61 hz 153 hz 305 hz 610 hz 977 hz for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserv ed bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 19 of 47 feb. 14, 2014 4.8.6 csi00 initialization figure 4 . 10 shows the csi00 initialization. r _ csi 00 _ create stop csi 00 communication operation disable the csi 00 interrupt set the csi 00 interrupt priority level clear the csi 00 error flag set the csi 00 operating mode set the csi 00 communication format set the baud rate set the output values of pins sck 00 and so 00 enable the csi 00 output set the pin used by csi 00 return st 0 register st 00 bit 1 sir 00 register 0007 h fect 00 bit = 1 : framing error flag clear pect 00 bit = 1 : parity error flag clear ovct 00 bit = 1 : overrun error flag clear pr 10 h register csipr 100 bit 1 pr 00 h register csipr 000 bit 1 : interrupt priority level 3 ( low priority ) pm 5 register pm 50 bit 1 : si 00 pin : input mode p 5 register p 51 1 : so 00 pin : output 1 pm 5 register pm 51 bit 0 : so 00 pin : output mode p 3 register ?@ p 30 1 : sck 00 pin : output 1 pm 3 register pm 30 bit 0 : sck 00 pin : output mode mk 0 h register csimk 00 bit 1 : interrupt servicing disabled if 0 h register csiif 00 bit 0 : no interrupt request signal is generated smr 00 register 0020 h cks 00 bit = 0 : operation clock : ck 00 ( 2 mhz = 32 mhz / 2 4 ) ccs 00 bit = 0 : operation clock : divided clock frequency of the operating clock bits md 002 and md 001 = 00 b : csi mode md 000 bit = 0 : interrupt source : transfer end interrupt scr 00 register c 007 h bits txe 00 and rxe 00 = 11 b : transmission / reception bits dap 00 and ckp 00 = 00 b : data and clock phase : type 1 dir 00 bit = 0 : msb first bits dls 001 and dls 000 = 11 b : 8 - bit data length sdr 00 register ce 00 h : transfer clock set by dividing the operating clock : f mck / 208 9615 bps = 2 mhz 208 so 0 register cko 00 1 : serial clock output value : 1 so 00 bit 0 : serial data output value : 0 soe 0 register soe 00 bit 1 figure 4 . 10 csi00 initialization
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 20 of 47 feb. 14, 2014 stopping the csi00 communication operation ? serial channel stop register 0 (st0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st0 0 0 0 0 0 0 0 0 0 0 0 0 st03 st02 st01 s t00 value ? ? ? ? ? ? ? ? ? ? ? ? 1 ? bit 0 st00 bit operation stop trigger of channel 0 0 no trigger operation 1 clears the se00 bit to 0 and stops the communication operation disabling the csi00 interrupt ? interrupt mask flag register (mk0h) s ymbol 7 6 5 4 3 2 1 0 mk0h sremk0 tmmk01h sr mk0 csimk01 iicmk01 stmk0 csimk00 iicmk00 1 1 sremk2 tmmk11h srmk2 csimk21 iicmk21 stmk2 csimk20 iicmk20 value 1 ? ? ? bit 5 csi mk00 bit interrupt servicing control 0 interrupt servicing enabled 1 i nterrupt servicing disabled ? interrupt request flag register (if0h) symbol 7 6 5 4 3 2 1 0 if0h sreif0 tmif01h srif0 csiif 0 1 iicif01 stif0 csiif00 iicif00 0 0 sreif2 tmif11h srif2 csiif21 iicif21 stif2 csiif20 iicif20 value 0 ? ? ? bit 5 csi if00 bit interrupt request flag 0 no interrupt request signal is generated 1 interrupt request signal is generated , interrupt request status for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 21 of 47 feb. 14, 2014 setting the csi00 interrupt priority level ? priority specification flag registers (pr10h, pr00h) symbol 7 6 5 4 3 2 1 0 pr00h srepr00 tmpr001h srpr00 csipr001 iicpr001 stpr00 csipr000 iicpr000 1 1 srepr02 tmpr011h srpr0 2 csipr021 iicpr021 stpr02 csipr020 iicpr020 value 1 ? ? symbol 7 6 5 4 3 2 1 0 pr10h srepr 1 0 tmpr 1 01h srpr 1 0 csipr 1 01 iicpr 1 01 stpr 1 0 csipr 1 00 iicpr 1 00 1 1 srepr 1 2 tmpr 1 11h srpr 1 2 csipr 1 21 iicpr 1 21 stpr 1 2 csipr 1 20 iicpr 1 20 value 1 ? ? ? bit 5 csipr100 bit csipr000 bit priority level selection 0 0 specify level 0 (high priority) 0 1 specify level 1 1 0 specify level 2 1 1 specify level 3 (low priority) for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 22 of 47 feb. 14, 2014 clearing the csi00 error flag ? serial flag clear trigger register (sir00) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sir00 0 0 0 0 0 0 0 0 0 0 0 0 0 fect00 pect00 ovct00 value ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 ? bit 2 fect00 bit clear trigger of framing error of channel 0 0 no t cleared 1 clears the fef00 bit of the ssr00 register to 0 ? bit 1 pect00 bit clear trigger of parity error of channel 0 0 no t cleared 1 clears the pef00 bit of the ssr00 register to 0 ? bit 0 ovct00 bit clear trigger of overrun error of channel 0 0 no t cleared 1 clears the ovf00 bit of the ssr00 register to 0 for details on register setting, refer to the rl78/g14 user s manual: hardware. l egend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 23 of 47 feb. 14, 2014 setting the csi00 operating mode ? serial mode register 00 (smr00) operating clock (f mck ): ck00 transfer clock (f tclk ): divid ed f mck operating mode: csi mode symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr00 cks 00 ccs 0 0 0 0 0 0 0 sts 0 0 0 sis 000 1 0 0 md 00 2 md 00 1 md 0 0 0 value 0 0 ? ? ? ? ? 0 ? 0 1 ? ? 0 0 0 ? bit 15 cks00 bit selection of operati ng clock (f mck ) of channel 0 0 operati ng clock ck 0 0 set by the sps0 reg ister 1 operati ng clock ck 0 1 set by the sps0 register operati ng clock (f mck ) is used by the edge detector. in addition, depending on the setting of the ccs00 bit and the higher 7 bits of the sdr00 register, a transfer clock (f tclk ) is generated. ? bit 14 ccs00 bit selection of transfer clock (f tclk ) of channel 0 0 divided operati ng clock f mck specified by the cks00 bit 1 clock input f sck from the sck00 ___________ pin (slave transfer in csi mode) tra nsfer clock f tclk is used for the shift register, communication controller, output controller, interrupt controller, and error controller. when ccs00 = 0, the division ratio of operati ng clock (f mck ) is set by the higher 7 bits of the sdr00 register. ? bit s 2 and 1 md002 bit md001 bit setting of operati ng mode of channel 0 0 0 csi mode 0 1 uart mode 1 0 simplified i 2 c mode 1 1 setting prohibited ? bit 0 md000 bit selection of interrupt source of channel 0 0 transfer end interrupt 1 buffer empty interr upt (occurs when data is transferred from the sdr00 register to the shift register) for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cel l: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 24 of 47 feb. 14, 2014 setting the csi00 communication format ? serial communication operation setting register 00 (scr00) operating mode: enable transmission/reception clock phase: type 1 data transfer sequence: msb first data length: 8 - bit dat a length symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr00 txe 00 rxe 00 dap 00 ckp 00 0 eoc 0 0 ptc 0 0 1 ptc 0 00 dir 00 0 slc 001 slc 000 0 1 dls 0 01 dls 000 value 1 1 0 0 ? 0 ? ? ? 1 1 ? bits 15 and 14 txe00 bit rxe00 bit selection of operati ng mode of c hannel n 0 0 disable communication 0 1 reception only 1 0 transmission only 1 1 transmission/reception ? bits 13 and 12 dap00 bit ckp00 bit selection of data and clock phase in csi mode 0 0 type 1 0 1 type 2 1 0 type 3 1 1 type 4 ? bit 7 dir00 bit selection of data transfer sequence in csi and uart modes 0 inputs/outputs data with msb first 1 inputs/outputs data with lsb first ? bits 1 and 0 dls001 bit dls000 bit setting of data length in csi and uart modes 0 0 9 - bit data length (stored in bits 0 to 8 of the sdr00 register) (settable in uart mode only) 1 0 7 - bit data length (stored in bits 0 to 6 of the sdr00 register) 1 1 8 - bit data length (stored in bits 0 to 7 of the sdr00 register) other than above setting prohibited for details on regist er setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 25 of 47 feb. 14, 2014 setting the baud rate ? serial data register 00 (sdr00) sets the transfer clock to 9600 bps (9600 bps = f mck 208 = 2 mhz 208) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? value 1 1 0 0 1 1 1 ? ? bits 15 to 9 sdr00[15:9] transfer clock set by dividing the operating clock (fmck) 0 0 0 0 0 0 0 f mck /2 0 0 0 0 0 0 1 f mck / 4 1 1 0 0 1 1 1 f mck / 208 (=f mck /[(103+1) 2]) setting the output values from pins sc k00 and so00 ? serial output register 0 (so0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 cko03 cko02 cko01 cko00 0 0 0 0 so03 so02 so01 so00 value ? ? ? ? 1 ? ? ? ? ? bit 8 cko00 bit serial clock output of channel 0 0 serial cl ock output value is 0 1 serial clock output value is 1 ? serial output register 0 (so0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 cko03 cko02 cko01 cko00 0 0 0 0 so03 so02 so01 so00 value ? ? ? ? ? ? ? ? 0 ? bit 0 so00 b it serial data output of channel 0 0 serial clock output value is 0 1 serial clock output value is 1 for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 26 of 47 feb. 14, 2014 enabling the csi00 output ? serial output enable register 0 (soe0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 soe03 soe02 soe01 so e 00 value ? ? ? ? ? ? ? ? ? ? ? ? 1 ? bit 0 soe00 bi t serial output enable/stop of channel 0 0 stops output by serial communication operation 1 enables output by serial communication operation setting the pin used by csi00 ? port mode register 5 (pm5) symbol 7 6 5 4 3 2 1 0 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 value 1 ? bit 0 pm50 bit p50 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output buffer off) ? port register 5 (p5) symbol 7 6 5 4 3 2 1 0 p5 p57 p56 p55 p54 p53 p52 p51 p50 value 1 ? bit 0 p5 1 bit output data control (in output mode) 0 output 0 1 output 1 for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchan ged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 27 of 47 feb. 14, 2014 ? port mode register 5 (pm5) symbol 7 6 5 4 3 2 1 0 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 value 0 ? bit 1 pm5 1 bit p5 1 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output bu ffer off) ? port register 3 (p3) symbol 7 6 5 4 3 2 1 0 p3 0 0 0 0 0 0 p31 p30 value ? ? ? ? ? ? 1 ? bit 0 p 30 bit output data control (in output mode) 0 output 0 1 output 1 ? port mode register 3 (pm3) symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 1 1 pm31 pm30 value 0 ? bit 0 pm 30 bit p 30 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output buffer off) for details on register setting, refer to the rl78/g14 user s m anual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 28 of 47 feb. 14, 2014 4.8.7 csi00 operation start figure 4 . 11 shows the csi00 operation start. r _ csi 00 _ start enable the csi 00 interrupt set the output values of pins sck 00 and so 00 enable to output from csi 00 enable to start the csi 00 communication operation return ss 0 register ss 00 bit 1 if 0 h register csiif 00 bit 0 : no interrupt request signal is generated mk 0 h register csimk 00 bit 0 : interrupt servicing enabled so 0 register cko 00 bit 1 : serial clock output value is " 1 " so 00 bit 0 : serial data output value is " 0 " soe 0 register soe 0 0 0 bit 1 figure 4 . 11 csi00 operation start enabling the csi00 interrupt ? interrupt request flag register (if0h) symbol 7 6 5 4 3 2 1 0 if0h sreif0 tmif01h srif0 csiif 0 1 iicif01 stif0 csiif00 iicif00 0 0 sreif2 tmif11h srif2 csiif21 iicif21 stif2 csiif20 iicif20 value 0 ? ? ? bit 5 csiif00 bit interrupt request flag 0 no interrupt request signal is generated 1 interrupt request signal is generated , interrupt request status for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 29 of 47 feb. 14, 2014 ? interrupt mask flag register (mk0h) symbol 7 6 5 4 3 2 1 0 mk0h sremk0 tmmk01h sr mk0 csimk01 iicmk01 stmk0 csimk00 iicmk 00 1 1 sremk2 tmmk11h srmk2 csimk21 iicmk21 stmk2 csimk20 iicmk20 value 0 ? ? ? bit 5 csimk00 bit interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled setting the output values from pins sck00 and so00 ? ser ial output register 0 (so0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 cko03 cko02 cko01 cko00 0 0 0 0 so03 so02 so01 so00 value ? ? ? ? 1 ? ? ? ? ? bit 8 cko00 bit serial clock output of channel 0 0 serial clock output value is 0 1 serial clock output value is 1 ? serial output register 0 (so0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 cko03 cko02 cko01 cko00 0 0 0 0 so03 so02 so01 so00 value ? ? ? ? ? ? ? ? 0 ? bit 0 so00 bit serial data o utput of channel 0 0 serial clock output value is 0 1 serial clock output value is 1 for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; bl ank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 30 of 47 feb. 14, 2014 enabling the csi00 output ? serial output enable register 0 (soe0) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 soe03 soe02 soe01 so e 00 value ? ? ? ? ? ? ? ? ? ? ? ? 1 ? bit 0 soe00 bi t serial output enable/stop of channel 0 0 stops output by serial communication operation 1 enables output by serial communication operation enabling to start the csi00 communication operation ? serial channel start register 0 (ss0) symbol 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 ss01 s s 00 value ? ? ? ? ? ? ? ? ? ? ? ? 1 ? bit 0 ss00 bit operation start trigger of channel 0 0 no trigger operation 1 sets the se00 bit to 1 and enters the communication wait status for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 31 of 47 feb. 14, 2014 4.8.8 csi00 t ransmission/ r eception s tart figure 4 . 12 shows the csi00 transmission/recepti on start. r _ csi 00 _ send _ receive set md _ ok to the ?g status ?h number of bytes to transmit is less than 1 ? set the transmit data size to the transmit data counter set the transmit buffer address set the receive buffer address disable the csi 00 interrupt set the transmit data to the sio 00 register update the transmit buffer address update the transmit data counter enable the csi 00 interrupt return ( status ) yes no set md _ argerror to the ?g status ?h arguments uint 8 _ t * const tx _ buf : transmit data buffer pointer uint 16 _ t tx _ num : transmit data size uint 8 _ t * const rx _ buf : receive data buffer pointer mk 0 h register csimk 00 bit 1 : interrupt servicing disabled sio 00 register * gp _ csi 00 _ tx _ address mk 0 h register csimk 00 bit 0 : interrupt servicing enabled figure 4 . 12 csi00 transmission/reception start
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 32 of 47 feb. 14, 2014 disa bling the csi00 interrupt ? interrupt mask flag register (mk0h) symbol 7 6 5 4 3 2 1 0 mk0h sremk0 tmmk01h sr mk0 csimk01 iicmk01 stmk0 csimk00 iicmk00 1 1 sremk2 tmmk11h srmk2 csimk21 iicmk21 stmk2 csimk20 iicmk20 value 1 ? ? ? bit 5 csimk00 bit interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled setting the transmit data ? csi00 data register (sio00) symbol 7 6 5 4 3 2 1 0 sio00 ? ? ? ? ? ? ? ? value 00h to ffh enabling the csi00 interrupt ? interrupt mask flag register (mk0h) symbol 7 6 5 4 3 2 1 0 mk0h sremk0 tmmk01h sr mk0 csimk01 iicmk01 stmk0 csimk00 iicmk00 1 1 sremk2 tmmk11h srmk2 csimk21 iicmk21 stmk2 csimk20 iicmk20 value 0 ? ? ? bit 5 csimk00 bit interrup t servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell : unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 33 of 47 feb. 14, 2014 4.8.9 csi00 transfer end interrupt figure 4 . 13 shows the csi00 transfer end interrupt. r_csi00_interrupt retrieve the overrun error detection flag set the clear trigger of the overrun error flag overrun error occurs? csi00 error callback function r_csi00_callback_error() transmit data counter is less than 0? clear the transmit data counter return (status) transmit data counter is equal to 0? store the receive data csi00 receive end callback function r_csi00_callback_receiveend() err_type (ssr00 & 0001h) sir00 register err_typ ovct00 bit = 1: clears the ovf00 bit of the ssr00 register to 0 yes no yes no yes no *(gp_csi00_rx_address+tx_rx_data_size?1) sio00 register figure 4 . 13 csi00 transfer end interrupt
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 34 of 47 feb. 14, 2014 retrieving the overrun error detection flag status ? serial status register 00 (ssr00) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssr0 0 0 0 0 0 0 0 0 0 0 tsf 00 bff 00 0 0 fec 00 pec 00 ovc 00 ? bit 0 ovc00 bit overrun error detection flag of channel 0 0 no error occurs 1 an error occurs setting the clear trigger of the overrun error flag ? serial flag clear trigger register (sir00) clears an overrun error flag when an overrun error occurs. symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sir00 0 0 0 0 0 0 0 0 0 0 0 0 0 fect00 pect00 ovct 00 value ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? bit 0 ovct00 bit clear trigger of overrun error flag of channel 0 0 not cleared 1 clears the ovf00 bit of the ssr00 register to 0 storing the receive data ? csi00 data register 00 (sio00) reads the receive data symbol 7 6 5 4 3 2 1 0 sio00 ? ? ? ? ? ? ? ? for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 35 of 47 feb. 14, 2014 4.8.10 csi00 receive end callback function figure 4 . 14 shows the csi0 0 receive end callback function. r_csi00_callback_receiveend copy the receive data (8 bytes) set the transmit/receive status to transmit/receive end return figure 4 . 14 csi00 rece ive end callback function 4.8.11 csi00 error callback function figure 4 . 15 shows the csi00 error callback function. r _ csi 00 _ callback _ error error processing ( note 1 ) return argument uint 8 _ t err _ type : error type note 1 . the sample code does not include the error processing . add processing to the user program as needed . figure 4 . 15 csi00 error callback function
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 36 of 47 feb. 14, 2014 4.8.12 dtc initialization figure 4 . 16 shows the dtc initialization. r _ dtc _ create supply an input clock to the dtc disable to active the dtc dtcen 0 register 00 h dtcen 1 register 00 h dtcen 2 register 00 h dtcen 3 register 00 h dtcen 4 register 00 h per 1 register dtcen bit 1 : enables input clock supply set the dtc base address dtcbar register fdh set the start address of the dtc control data to the dtc vector table set dtcd 0 dtccr 0 register 18 h sz bit = 0 : transfer byte size : 8 - bit chne bit = 1 : chain transfers enabled damod bit = 1 : transfer destination address incremented samod bit = 0 : transfer source address fixed mode bit = 0 : normal mode dtbls 0 register 01 h : b lock size of the data to be transferred by one activation : 1 byte dtcct 0 register 07 h : number of dtc data transfers : 7 dtrld 0 register 07 h : transfer count in repeat mode : 7 dtsar 0 register ff 10 h : specify the transfer source address to ff 10 h dtdar 0 register e 900 h : specify the transfer destination address to e 900 h set dtcd 1 dtccr 1 register 04 h sz bit = 0 : transfer byte size : 8 - bit chne bit = 0 : chain transfers disabled damod bit = 0 : transfer destination address fixed samod bit = 1 : transfer source address incremented mode bit = 0 : normal mode dtbls 1 register 01 h : block size of the data to be transferred by one activation : 1 byte dtcct 1 register 07 h : number of dtc data transfers : 7 dtsar 1 register e 911 h : specify the transfer source address to e 911 h dtdar 1 register ff 10 h : specify the transfer destination address to ff 10 h return figure 4 . 16 dtc initialization
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 37 of 47 feb. 14, 2014 supplying an input clock to the dtc ? peripheral enable register 1 (per1) symbol 7 6 5 4 3 2 1 0 per1 dacen trgen cmpen trd0en dtcen 0 0 trj0en value 1 ? ? ? bit 3 dtcen bit control of dtc input clock supply 0 stops input clock supply ? dtc cannot run. 1 enables input clock supply ? dtc can run. disabling to activate dtc 0 ? dtc activ ation enable register i (dtceni, i = 0 to 4) symbol 7 6 5 4 3 2 1 0 dtceni dtceni7 dtceni6 dtceni5 dtceni4 dtceni3 dtceni2 dtceni1 dtceni0 value 0 0 0 0 0 0 0 0 ? bit 7 dtceni7 bit dtc activation enable i7 0 activation disabled 1 activation enabled ? bit 6 dtceni6 bit dtc activation enable i6 0 activation disabled 1 activation enabled ? bit 5 dtceni5 bit dtc activation enable i5 0 activation disabled 1 activation enabled for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 38 of 47 feb. 14, 2014 ? bit 4 dtceni4 bit dtc activation enable i4 0 activation disabled 1 activation enabled ? bit 3 dtceni3 bit dtc activation enable i3 0 activation disabled 1 activation enabled ? bit 2 dtceni2 bit dtc activation enable i2 0 activation disabled 1 activation enabled ? bit 1 dtceni1 bit dtc activation enable i1 0 activation disabled 1 activation enabled ? bit 0 dtceni0 bit dtc activation enable i0 0 activation disabled 1 activation enabled setting the dtc base address ? dtc base address register (dtcbar) sets the start address of the dtc control data area. symbol 7 6 5 4 3 2 1 0 dtcbar dtc bar 7 dtc bar 6 dtc ba r 5 dtc bar 4 dtc bar 3 dtc bar 2 dtc bar 1 dtc bar 0 value fdh for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 39 of 47 feb. 14, 2014 setting the dtcd0 ? dtc control register 0 (dtccr0) data size: 8 bit s chain transfer: enabled transfer destination address: incremented transfer source address: fixed transfer mode: normal mode symbol 7 6 5 4 3 2 1 0 dtccr0 0 sz rpt int chne damod samod rptsel mode value ? 0 1 1 0 0 ? bit 6 sz bit data size selection 0 8 bits 1 16 bits ? bit 4 chne bit enabling/disabling chain transfers 0 chain transfers disabled 1 chain transfers enabled ? bit 3 damod bit transfer destination address control 0 fixed 1 incremente d ? bit 2 samod bit transfer source address control 0 fixed 1 incremented ? bit 0 mode bit transfer mode selection 0 normal mode 1 repeat mode for details on register setting, refer to the rl78/g14 u ser s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 40 of 47 feb. 14, 2014 ? dtc block size register 0 (dtbls0) set the dtc0 block size to 1 byte. symbol 7 6 5 4 3 2 1 0 dtbls0 dt bls0 7 dt bls0 6 dt bls0 5 dt bls0 4 dt bls0 3 dt bls0 2 dt bls0 1 dt bls0 0 value 01h ? dtc transfer count register 0 (dtcct0) se t the number of transfers by dtc0 to 7. symbol 7 6 5 4 3 2 1 0 dt cct 0 dt cct 0 7 dt cct 0 6 dt cct 0 5 dt cct 0 4 dt cct 0 3 dt cct 0 2 dt cct 0 1 dt cct 0 0 value 0 7 h ? dtc transfer count reload register 0 (dtrld0) set the number of transfers in repeat mode to 7 (this registe r can be used in repeat mode) . symbol 7 6 5 4 3 2 1 0 dtrld0 dt rld0 7 dt rld0 6 dt rld0 5 dt rld0 4 dt rld0 3 dt rld0 2 dt rld0 1 dt rld0 0 value 07h ? dtc source address register 0 (dtsar0) specify the transfer source address for data transfer to ff10h . symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dtsar 0 dtsa r 0 15 dtsa r 0 1 4 dtsa r 0 1 3 dtsa r 0 1 2 dtsa r 0 1 1 dtsa r 0 1 0 dtsa r 09 dtsa r 08 dtsa r 07 dtsa r 06 dtsa r 0 5 dtsa r 04 dtsa r 03 dtsa r 02 dtsa r 0 1 dtsa r 00 value ff10h ? dtc destination address register 0 (dtdar0) spec ify the transfer destination address for data transfer to e900h. symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dt d ar 0 dt d a r 0 15 dt d a r 0 1 4 dt d a r 0 1 3 dt d a r 0 1 2 dt d a r 0 1 1 dt d a r 0 1 0 dt d a r 09 dt d a r 08 dt d a r 07 dt d a r 06 dt d a r 0 5 dt d a r 04 dt d a r 03 dt d a r 02 d t d a r 0 1 dt d a r 00 value e900 h for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 41 of 47 feb. 14, 2014 se tting the dtcd1 ? dtc control register 1 (dtccr1) data size: 8 bits chain transfer: disabled transfer destination address: fixed transfer source address: incremented transfer mode: normal mode symbol 7 6 5 4 3 2 1 0 dtccr1 0 sz rptint chne damod samod rpts el mode value ? 0 0 0 1 0 ? bit 6 sz bit data size selection 0 8 bits 1 16 bits ? bit 4 chne bit enabling/disabling chain transfers 0 chain transfers disabled 1 chain transfers enabled ? bit 3 damod bit transfer destination address control 0 fixed 1 incremente d ? bit 2 samod bit transfer source address control 0 fixed 1 incremented ? bit 0 mode bit transfer mode selection 0 normal mode 1 repeat mode for details on register setting, refer to the rl78/g14 u ser s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 42 of 47 feb. 14, 2014 ? dtc block size register 1 (dtbls1) sets the dtc1 block size to 1 byte. symbol 7 6 5 4 3 2 1 0 dtbls1 dt bls1 7 dt bls1 6 dt bls1 5 dt bls1 4 dt bls1 3 dt bls1 2 dt bls1 1 dt bls1 0 value 01h ? dtc transfer count register 1 (dtcct1) s et the number of transfers by dtc1 to 7. symbol 7 6 5 4 3 2 1 0 dtcct1 dt cct1 7 dt cct1 6 dt cct1 5 dt cct1 4 dt cct1 3 dt cct1 2 dt cct1 1 dt cct1 0 value 07h ? dtc source address register 1 (dtsar1) specify the transfer source address for data transfer to e911h. sy mbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dtsar 1 dtsa r 1 15 dtsa r 1 1 4 dtsa r 1 1 3 dtsa r 1 1 2 dtsa r 1 1 1 dtsa r 1 1 0 dtsa r 1 9 dtsa r 1 8 dtsa r 1 7 dtsa r 1 6 dtsa r 1 5 dtsa r 1 4 dtsa r 1 3 dtsa r 1 2 dtsa r 1 1 dtsa r 1 0 value e911 h ? dtc destination address register 1 (dt dar 1 ) specify the transfer destination address for data transfer to ff10 h. symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dt d ar 1 dt d a r 1 15 dt d a r 1 1 4 dt d a r 1 1 3 dt d a r 1 1 2 dt d a r 1 1 1 dt d a r 1 1 0 dt d a r 1 9 dt d a r 1 8 dt d a r 1 7 dt d a r 1 6 dt d a r 1 5 dt d a r 1 4 dt d a r 1 3 dt d a r 1 2 dt d a r 1 1 dt d a r 1 0 value ff10 h for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 43 of 47 feb. 14, 2014 4.8.13 dtcd0 operation start figure 4 . 17 shows the dtcd0 operation start. r _ dtcd 0 _ start enable to activate the dtc by csi 00 transfer end return dtcen 1 register dtcen 13 bit 1 : activation enabled figure 4 . 17 dtcd0 operation start enabling to activate the dtc by csi00 transfer end ? dtc activation enable register 1 (dtcen 1 ) symbol 7 6 5 4 3 2 1 0 dtcen 1 dtcen 1 7 dtcen 1 6 dtcen 1 5 dtcen 1 4 dtce n 1 3 dtcen 1 2 dtcen 1 1 dtcen 1 0 value 1 ? bit 3 dtcen 13 bit dtc activation enable 13 0 activation disabled 1 activation enabled for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 44 of 47 feb. 14, 2014 4.8.14 dtcd0 operation stop figure 4 . 18 shows dtcd0 operation stop. r _ dtcd 0 _ stop disable to activate the dtc by csi 00 transfer end return dtcen 1 register dtcen 13 bit 0 : activation disabled figure 4 . 18 dtcd0 operation stop disabling to activate the dtc by csi00 transfer end ? dtc activation enable register 1 (dtcen1) symbol 7 6 5 4 3 2 1 0 dtcen1 dtcen17 dtcen16 dtcen15 dtcen14 dtcen 1 3 dtcen12 dtcen11 dtcen10 value 0 ? bit 3 dtcen13 bit dtc activation enable 13 0 activation disabled 1 activation enabled for details on register setting, refer to the rl78/g14 user s manual: hardware. legend symbol: : unused bit; blank cell: unchanged bit; ? : reserved bit or unallocated bit
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 45 of 47 feb. 14, 2014 4.8.15 main processing figure 4 . 19 shows the main processi ng. main main initialization r_main_userinit() transmission/reception completed? dtcd0 operation stop r_dtcd0_stop() dtc initialization r_dtc_create() dtcd0 operation start r_dtcd0_start() csi00 transmission/reception start r_csi00_send_receive() set the transmit/receive status to during transmission/reception csi_status = 0: during transmission/reception csi_status = 1: transmission/reception completed yes no figure 4 . 19 main processing
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 46 of 47 feb. 14, 2014 4.8.16 main initialization figure 4 . 20 shows the main initialization. r _ main _ userinit initialize the receive data set the transmit data transmit _ data _ set () set the transmit / receive status to transmission / reception end csi 00 operation start r _ csi 00 _ start () enable maskable interrupts return ie 1 figure 4 . 20 main initia lization 4.8.17 transmit data setting figure 4 . 21 shows the transmit data setting. transmit _ data _ set set the transmit data return figure 4 . 21 transmit data setting
using the dtc to perform continuous clock rl78/g14 synchronous serial commu nication R01AN1504EJ0100 rev. 1.00 p age 47 of 47 feb. 14, 2014 5. sample code sample code can be downloaded from the renesas electronics website. 6. reference documents rl78/g 14 user s manual: hardware rev. 2 .00 (r01uh0186ej) rl78 family user s manual: software rev.1.00 (r01us0015ej) the latest version s can be downloaded from the renesas electronics website. technical update /technical news the latest information can be downloa ded from the renesas electronics website. website and support renesas electronics w ebsite http://www.renesas.com inquiries http://www.renesas.com/contact/
a - 1 r evision h istory rl78/g14 using the dtc to perform continuous clock synchronous serial communication rev. date description page summary 1.00 feb . 14 , 201 4 first edition issued all trademarks and registered trademarks are the property of their respective owners.
general p recautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any t echnical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pin s of cmos products are generally in the high - impedance state. in operation with an unused pin in the open - circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot - through current flows internally, and malfunctions o ccur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power - on the state of the product is undefined at the moment whe n power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on - chip power - on reset function are not guaranteed from the momen t when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansi on of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between p roducts before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system - evaluation test for the given product.
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