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asahi kasei [ak4183] ms0500-e-00 2006/04 1 ak4183 i 2 c touch screen controller sda scl pen interrupt penirqn gnd 12bit adc (sar type) vref+ ain+ vref- control logic ain- vcc cad0 yp xn yn xp block diagram features: ? 12-bit sar type a/d converter with s/h circuit ? low voltage operation (2.5v 3.6v) ? i 2 c bus i/f supports (standard mode 100 khz, fast mode 400 khz) ? 4-wire resistive touch screen interface ? pen pressure measurement ? auto power down ? continuous read operation ? low power consumption (91 a @fast mode) ? package 10pin tmsop general description: the ak4183 is a 4-wire resistive touch screen controller that incorporates sar type a/d converter. the ak4183 operates down to 2.5v supply voltage in order to connect a low voltage drive processor. the ak4183 can detect the pressed screen location by performing two a/d conversions. in addition to location, the ak4183 also measures touch pressure. as the package size of 10 pin tmsop is 4.0mm x 2.9mm this is much smaller th an qfn and bga package. ak4183 is the best fit for cellular phone, pda, or other portable devices. asahi kasei [ak4183] ms0500-e-00 2006/04 2 ? ordering guide AK4183VT -40 c +85 c 10pin tmsop (0.5mm pitch) ? pin layout top view 10 9 6 7 8 scl sda penirqn gnd cad0 5 4 3 2 1 vcc xp xn yp yn pin/function no. signal name i/o description 1 vcc - power supply 2 xp i/o touch screen x+ plate voltage supply ? x axis measurement: supplies the voltage to x+ posit ion input of the touch panel. ? y axis measurement: this pin is used as the input for the a/d converter ? pen pressure measurement: this pin is the input for the a/d converter at z1 measurement. ? pen waiting state: pulled up by an internal resistor (typ.10k ohm). 3 yp i/o touch screen y+ plate voltage supply ? x axis measurement: this pin is used as the input for the a/d converter ? y axis measurement: supplies the voltage to y+ position input of the touch panel ? pen pressure measurement: s upplies the voltage to y+ positio n input of the touch panel. ? pen waiting state: open state 4 xn i/o touch screen x- plate voltage supply ? x axis measurement: supplies the voltage to x- position input of the touch panel ? y axis measurement: open state ? pen pressure measurement: supplies the volt age to x- position input of the touch panel ? pen waiting state: open state 5 yn i/o touch screen y- plate voltage supply ? x axis measurement: open state ? y axis measurement: supplies the voltage to y- position input of the touch panel ? pen pressure measurement: this pin is the input for the a/d converter at z2 measurement. ? pen waiting state: connected to gnd. 6 gnd - ground 7 penirqn o pen interrupt output this pin is ?l? during the pen down on pen interr upt enabled state otherwise this pin is ?h?. this pin is ?l? during pen interrupt disabled state regardless pen touch. 8 cad0 i i 2 c bus slave address bit 0 9 sda i/o i 2 c serial data 10 scl i i 2 c serial clock asahi kasei [ak4183] ms0500-e-00 2006/04 3 absolute maximum ratings gnd = 0v (note 1) parameter symbol min max units power supplies vcc -0.3 6.0 v input current (any pins except for supplies) iin - 10 ma input voltage vin -0.3 6.0(vcc+0.3) v touch panel drive current ioutdrv 50 ma ambient temperature (power supplied) ta -40 85 c storage temperature tstg -65 150 c note 1.all voltages with respect to ground. warning: operation at or beyond these limits may result in perm anent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions gnd = 0v (note 1) parameter symbol min typ max units power supplies vcc 2.5 2.7 3.6 v note 1. all voltages with respect to ground. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet. asahi kasei [ak4183] ms0500-e-00 2006/04 4 analog characteristics ta = -40 c to 85 c, vcc = 2.7v, i 2 c bus scl=400 khz, 12 bit mode parameter min. typ. max. units adc for touch screen resolution 12 bits no missing codes 11 12 bits integral nonlinearity (inl) error 2 lsb differential nonlinea rity (dnl) error 1 lsb offset error 6 lsb gain error 4 lsb throughput rate 8.2 ksps touch panel driver on-resistance xp, yp xn, yn 5 5 ? ? xp pull up register (when pen interrupt enable) 10 k ? power supply current fast mode: scl=400khz 91 200 a normal mode pd0=?0? addressed standard mode: scl=100khz 68 150 a fast mode: scl=400khz 23 a power down pd0=?0? not addressed standard mode: scl=100khz 6 a full power down (control command pd0= ?0? sda=scl= vcc) 0 3 a asahi kasei [ak4183] ms0500-e-00 2006/04 5 dc characteristics (logic i/o) ta = -40 to 85 c, vcc = 2.5v to 3.6v parameter symbol min. typ. max. units ?h? level input voltage vih 0.7xvcc - v ?l? level input voltage vil - 0.3xvcc v input leakage current iilk -10 10 a ?h? level output voltage (penirqn pin@ iout = -250 a) voh vcc-0.4 v ?l? level output voltage (penirqn pin @ iout = 250 a) (sda pin @ iout = 3ma) vol 0.4 v tri-state leakage current all pins except for xp, yp, xn, yn pins xp, yp, xn, yn pins iolk -10 -50 10 50 a a switching characteristics ta = -40 to 85 c, vcc = 2.5v to 3.6v parameter (i 2 c timing) symbol min typ max units scl clock frequency fscl 30 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated st art condition tsu:sta 1.3 s sda hold time from scl falling (note 2) thd:dat 0 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 2: data must be held for sufficient time to bridge the 300 ns transition time of scl. thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 1 ak4183 timing diagram asahi kasei [ak4183] ms0500-e-00 2006/04 6 ? a/d converter for touch screen the ak4183 incorporates a 12-bit successive approximation resi stor (sar) a/d converter fo r position measurement. the architecture is based on a capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (s /h) circuit. the sar a/d converter output is a strai ght binary format as shown below: input voltage output code ( ? vref-1.5lsb)~ ? vref fffh ( ? vref-2.5lsb) ~ ( ? vref-1.5lsb) ffeh --------- --------- 0.5lsb ~ 1.5lsb 001h 0 ~ 0.5lsb 000h ? vref: (vref+) ? (vref-) table 1 output code ? the position detection of touch screen a position detecting (x, y position) on the touc h panel is selected by the control command via the a2, a1, a0 bits in the contr ol register. the mode of the position detecting is differential mode, the full scale ( ? vref) is the differential voltage between the non- inverting terminal and the inverting terminal of the measured axis (e.g. x-axis measurement: ? vref = v xp ? v xn ). the voltage difference on the a/d converter ( ? ain) is the voltage between non- inverting terminals of the non-m easured axis and the inverting terminal of the measured axis. (e.g. ? ain= (ain+) - (ain-) = v yp -v xn ) the voltage difference ( ? ain) is charged to the internal capacitor array during the sampling period. no current flows into the internal capacitor after the capacitor has been charged completely. the required settling time to charge the internal capacitor a rray depends on the source impedanc e (rin). if the source impedan ce is 600 ohm, the settling time needs at least 2.5 s (1 clock cycle period of scl 400 khz) the position on the touch screen is detect ed by taking the voltage of one axis when the voltage is supplied between the two terminals of another axis. at least two a/d conversions are needed to get the two-dimensional (x/y axis) position. the x-plate and y-plate are connected on the dotted line when the panel is touched. xp xn x-plate (top side) y-plate (bottom side) c) 4-wire touch screen construction x-plate y-p l ate x-plate yp yn yn xn yp xn-driver sw on vref+ vref- adc ain+ ain- xp xp-driver sw on a) x-position measurement differential mode b) y-position measurement differential mode yn xn yp yn-driver sw on vref+ vref- adc ain+ ain- xp yp-driver sw on vcc vcc touch screen y-p l ate figure 2 axis measurements asahi kasei [ak4183] ms0500-e-00 2006/04 7 the differential mode position detection is ty pically more accurate than the single-ended mode. as the full scale of single-en ded mode is fixed to the vcc, input voltage may exceed the full-sc ale reference voltage. this probl em does not occur in differenti al mode. in addition to this, the differential mode is less influenced by power supply voltage variation due to the ratio-metric measurement. ? the pen pressure measurement the touch screen pen pressure can be deri ved from the measurement of the contact resistor between two plates. the contact resistance depends on the size of the depre ssed area and the pressure. the area of the spot is proportional to the contact res istance. this resistance (rtouch) can be calc ulated using two different methods. the first method is that when the total resistance of the x-pl ate sheet is already known. the resistance, rtouch, is calculated from the results of three conversions, x-pos ition, z1-position, and z2-position, and then using the following formula: rtouch = (rxplate) * (xposition/4096) * [(z2/z1) ? 1] the second method is that when both the resi stances of the x-plate and y-plate are know n. the resistance, rtouch, is calculated from the results of three conversions, x- position, y-position, and z1-position, and then using the following formula: rtouch = (rxplatexposition/4096)[(4096/z1) ? 1] ? ryplate*[1 ? (yposition/4096)] xn-driver swon yn vref+ vref- adc a in+ a in- xp yp xn yp-driver sw on a) z1-position measurement rtouch xn-driver sw on yn vref+ vref- adc a in+ a in- xp yp xn yp-driver sw on b) z2-position measurement rtouch vcc vcc figure 3 pen pressure measurements asahi kasei [ak4183] ms0500-e-00 2006/04 8 ? digital i/f the ak4183 operates with up via i 2 c bus and supports the standard mode (100 khz) and the fast mode (400khz). note that the ak4183 operates in those two modes and do es not support a high speed mode i 2 c-bus system (3.4mhz). the ak4183 can operate as the slave device on the i 2 c bus network. vcc ak4183 micro- processor i 2 c bus controller scl sda vcc=2.5v ? 3.6v cad0 penirqn rp rp ?l? or ?h? figure 4 digital i/f [start condition a nd stop condition] a high to low transition on the sda line while scl is high indicates a start condition. all sequences start by the start condition or repeated start condition. repeated start condition is the same signal tradition as start condition. a low to high transition on the sda line while scl is high defines a stop condition. all sequences are terminated by the stop or repeated start condition. repeated start is also the start condition of next transfer so that i2c bus cannot be idle. scl sda p : stop condition s : start condition s/sr sr : repeated start condition figure 5 start and stop conditions [data transfer] all commands are preceded by a start condition. after the start condition, a slave address is sent. after the ak4183 recognizes the start condition, the device interfaced to the bus waits for the slave address to be transmitted over the sda lin e. if the transmitted slave address matches an address for one of the de vices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminated by a stop condition generated by the master device. asahi kasei [ak4183] ms0500-e-00 2006/04 9 [data validity] the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable; data valid change of data allowed figure 6 bit transfer on the i2c-bus [acknowledge] acknowledge is a software convention used to indicate successful data transfers. the transmit ting device will release the sda line (high) after transmitting eight bits. the receiver must pull down the sda line during the acknowledge clock pulse so that that it remains stable ?l? during ?h? period of this clock pulse. the ak4183 will generates an acknowledge after each byte has been received. in the read mode, the slave, ak4183 will transmit eight bits of data, release the sda line and monitor the line for an acknowle dge. if an acknowledge is detected and no stop c ondition is generated by the master, the slav e will continue to transmit data. if an acknowledge is not detected, the slave will terminate fu rther data transmissions and await the stop condition. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 7 acknowledge [address byte] the sequence of writing data is shown figure 10. the address byte , which includes seven bits of slave address and one bit of r/ w bit, is sent after the start condition. if the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls dow n the sda line (acknowledge). the most significant six bits of the slave address are fixed as ?100100?. the next one bit is cad0 (device address bit). this b it identifies the specific device on the bus. the hard-wired input pi n (cad0 pin) sets cad0 bit. the eighth bit (lsb) of the addre ss byte (r/w bit) defines whether the master requests a write or read operation. a ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. 1 0 0 1 0 0 cad0 r/w (cad0 should match with cad0 pins) figure 8 address byte asahi kasei [ak4183] ms0500-e-00 2006/04 10 [write operations] the second byte that followed by address byte consists of the control command byte of the ak4183. the operational mode is determined by control command. the bit form at is msb first and 8 bits width. contro l command is described in the table 3. the ak4183 generates an acknowledge after each byte has been received. a control command transfer is terminated by a stop condition or repeated start condition generated by the master. refer to the table 3 in detail. d7 d6 d5 d4 d3 d2 d1 d0 s a2 a1 a0 x1 pd0 mode x2 figure 9 control command byte start r/w=?0? address command s ak4183 ack ack ak4183 stop p sda figure 10 single write transmission sequence [read operation] the operation mode is determined by the wr ite command just before read operation. ak4183 features two methods of read operation, single read op eration and continuous read ope ration. the continuous read operation is a series of single read opera tion. each single read operation in conti nuous read operation make ak4183 updated a/d conversion on each read operation. write operation does not need to issue before each read operations are executed. the channel selection of ak4183 defines by the control command ju st before read operation. when the address byte with r/w = ?1? read operations are executed. a/d readout format is msb first, 1byte or 2byt es width. upper 8bits are valid on 8-bit mo de and upper 12 bits are valid, and lower 4 bi ts are filled with zero on 12-bit mode. [single read mode] read operation begins with start condition followed by the ad dress byte with r/w= ?1?.the address matches ak4183 generates ack. and after transmission of the address byte, the master receives upper 8bit a/d data first, an d generates ack. the ak4183 transmits the remaining 4-bit a/d data and followed by 4-bit zero data (12bit mode). master devi ce receives 8bit a/d data (8bi t mode). the master then generates nack and stop condition or repeated start condition. start a/d data ack ack stop nack a/d data sda d11 d4 d3 s p ak4183 master master d0 address r/w=?1? figure 11 single a/d data r ead sequence (12-bit mode) asahi kasei [ak4183] ms0500-e-00 2006/04 11 [continuous read mode] this continuous read operation enables the higher sampling rate and lower processor load than a single read operation. because once control command is sent, it does not need to update control command on each read operation until another control command would like to be rewritten. start a/d data a/d data sda d11 d4 s ack ak4183 ack master nack master d0 d3 stop p n n d11 d4 d0 d3 a/d data n+x n+x a/d data nack master ack ak4183 ack master sr repeat restart address address r/w=?1? r/w=?1? figure 12 continuous a/d data read sequence ? power on sequence it is recommended that the control command must be sent to fix th e internal register when power up. this initiates all register s such as a2-0 bit, pd0 bit, and mode bit. once sending command to fix the internal regist er after first power up, the state of ak4183 is held on the known-condition of state to ensure that ak4183 is go ing into desire mode to realize lowest mode. a command with pd0= ?0? should be sent so that ak4183 w ill be set in the lowest power down mode. ? sleep mode ak4183 supports the sleep mode that enables touch panel interface to put open state and disables pen interrupt function. ak4183 goes into the sleep mode when control comma nd is sent to ak4183 as shown table 2. the selection of the sleep mode is set by ?mode? bit of the control command. the st ate of both the output of penirqn pin and the connection with touch panel interface (xp, yp, xn, and yn) are the following table 2. ak4183 k eeps the sleep mode until next control command is sent. command mode bit penirqn touch panel 0111xx1x 1 hi-z open 0111xx0x 0 ?h? output open table 2 sleep command setting the timing of going into the sleep mode is the rising edge of the 16 th scl of the write operation. a/d conversion does not execute when the sleep command is sent. sda pin is ?h? since sda is pull up. in order for going to normal mode from sleep mode the command (s= ?1?) is sent. the timing of going back to normal mode is the rising edge of the 16 th scl. when the sleep command is sent again under the sleep mode the mode continues the same as before. the initial state after power up is in normal mode. asahi kasei [ak4183] ms0500-e-00 2006/04 12 ? control command the control command, 8 bits, provided to the ak4183 via sda, is shown in the following table. this command includes start bit, channel selection bit, power-down bit and re solution bit. the ak4183 latches the serial command at the rising edge of scl. ref er to the detailed information regarding the bi t order, function, the status of driver switch, adc input as shown in table 3. bit name function 7 s start bit. ?1? accelerate and axis command, ?0?: sleep mode command 6-4 a2-a0 channel selection bits. analog inputs to th e a/d converter and the activated driver switches are selected. please see the following table for the detail. 3 x1 don?t care 2 pd0 power down bit (refer to power-down control) 1 mode resolution of a/d converter. ?0?: 12 bit output ?1?: 8 bit output 0 x2 don?t care input status of driver switch adc input ( ? ain) reference voltage ( ? vref) s a2 a1 a0 xp xn yp yn ain+ ain- vref+ vref- note 0 1 1 1 sleep 1 0 0 0 on on off off yp xn xp xn accelerate x-driver 1 0 0 1 off off on on xp yn yp yn accelerate y-driver 1 0 1 0 off on on off xp xn yp xn 1 0 1 1 off on on off yn xn yp xn accelerate y+, x- driver 1 1 0 0 on on off off yp xn xp xn x-axis 1 1 0 1 off off on on xp yn yp yn y-axis 1 1 1 0 off on on off xp (z1) xn yp xn z1 (pen pressure) 1 1 1 1 off on on off yn (z2) xn yp xn z2 (pen pressure) table 3 control command list ? power-down control a/d converter and power-down cont rol of touch driver switch are determined by pd0 bit. pd0 penirqn function 0 enabled auto power-down mode a/d converter is automatically powered up at th e start of the conversion, and goes to power- down state automatically at the e nd of the conversion. all touch screen driver switches except for yn switch are turned off and relative pins are open state. only yn driver switch is turned on and yn pin is forced to the ground in this case. pen interrupt function is enabled except for the sampling time and conversion time. 1 disabled adc on mode when x-axis or y-axis are selected on the wr ite operation with pd0 = ?1? a/d converter and touch panel driver are always powered up until ne xt conversion. this mode is effective if more settling time is required to suppress the electrical bouncing of touch plate. pen interrupt function is disabled and penirqn is forced to ?l? state table 4 powers ?down control asahi kasei [ak4183] ms0500-e-00 2006/04 13 ? write operation sequence (figure 13) the selection of channel input of ak4183 is determined by a command byte. the timing of the driver switch on is 18 th falling edge of scl regardless pd0 bit when accelerate command (a2= ?0?) is sent. the accelerate command is to accelerate the timing of desired driver sw on to ensure that ak4183 needs more settling tim e. as for actually sampling is on the time of read operation, it becomes possible to take settling time long even when the impedance of the touch screen is large. ak4183 ack 0 touch driver sw ak4183 ack s x1 a2=0, pd0=0 or 1 a2=1 , pd0=0 a2 pd0 stop a2=1, pd0=1 mode a1 a0 x2 cad0 0 19 i ii iii iv command byte scl sda start 1 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 0 0 r/ w address byte figure 13 write operation and driver sw timing ? read operation sequence (figure. 14) a/d conversion is synchronized with scl. samp ling time is the one scl clock period (scl7 scl8 ) on the end of writing address byte and then hold. a/d conversion is held on the next 12 scl period (except master ack) .the readout sequence is that after command byte has been sent, ak4183 respond with acknowle dge if the address matches. the msb data byte will follow (d11 d4) then issued acknowledge by master. the lsb data byte (d3 d0, followed four ?0?) will be follo wed by not acknowledge bit (nack) from master in order to terminate the read transfer. the master will then issued stop that ends read operation or repeated start condition that keeps write or read ope ration. the master will issue repeated start condition or st art condition followed by read operation again. ak4183 repeats a/d data updated [continuous read operation]. master must issue stop condition after terminating the last read out of a/d data. address byte data byte (msb) data byte (lsb) master ack master nack 0 ?h? a2=?0? or a2=?1? , pd0=?1? a2=?1?, pd0=?0? sampling ad conversion 0 a2=?0?, pd0=?0? 28 v vi scl sda start 1 0 0 1 0 cad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 0 0 ak4183 ack d11 d10 d9 d8 d7 d6 d4 d5 r/ w 19 20 21 22 23 24 25 26 27 d3 d2 d1 d0 0 0 0 1 0 to uc h d r iv e r sw stop or repeated star t iv figure 14 read data sequence asahi kasei [ak4183] ms0500-e-00 2006/04 14 ? pen interrupt the ak4183 has a pen-interrupt function to detect the pen touch on the touch panel. this function will use as the interrupt of the microprocessor. pen interrupt function is enabled at power-down st ate. yn driver is on and this pin is connected to gnd at the power down state. and xp pin is pulled up vi a an internal resister (ri), typically 10k ? . if the touch plate is touched by pen or stylus, the current flow s via ---	--. the resistance of the plate is generally 1k ? or less, peniqrn pin is force to ?l? level. if the pen is released, peni rqn returns ?h? level because two plates are disconnected, and t he current does not flow via two plates. the transition of penirqn is related to pd0 bit. pd0 bit is upd ated as shown below. (please see ?power-down control? for the detail. once the control command with pd0= ?1? is sent the pen-interrupt function is disabled. the clock number under the write and the read operation refer to figure 13 and figure 14. i. the period from start condition to scl7 the level transition of penirqn pin is determined by pd0 bit of the previous command. when the previous command with pd0= ?0? the pen-interrupt function w ill be enabled. penirqn pin is low wh en the panel is touch, penirqn pin is ?h? when the panel is untouched. when the previous command with pd0= ?1? is sent penirqn pin is low regardless of pen-touch ii. the period scl7 to scl8 on the write operation the level of penirqn pin is always low regardless of pd0 bit and the state of pa nel (touched/untouched) iii. the period from scl8 to scl18 on the write operation the level transition of penirqn pin is determined by pd0 bit of the previous command. when the previous command with pd0= ?0? the pen-interrupt function w ill be enabled. penirqn pin is low wh en the panel is touch, penirqn pin is ?h? when the panel is untouched. when the previous command with pd0= ?1? is sent penirqn pin is low regardless of pen-touch iv. the period from scl18 on the write operation to scl7 on the read operation the level of penirqn pin is determined by the a2 bit and pd0 bit of the present command. penirqn pin is always low regardless pen-touch when command with a2 = ?1? or pd0 = ?1? is set. penirqn is determined by the pen-touch (touched/untouched) when command with a2= ?1? and pd0= ?1? is sent. v. the period from scl7 to scl21 on the write operation the ad input will sample the hold and the conversion will be done during this period. penirqn is always low. vi. the period after scl21 on the read operation the level transition of penirqn pin is determined by pd0 bit of the present command. when the present command with pd0= ?0? is sent the pen-interrupt func tion will be enabled. penirqn pin is low when the panel is touched. penirqn pin is ?h? when the panel is untouched. when the pr esent command with pd0= ?1? are sent penirqn pin is low regardless of pen-touch. it is recommended that the processor will mask the pseudo interrupt while the control command is issued or ad data is sent to processor. xp penirqn driver on yn en2 ri = 10k ? driver off en1 vcc vcc vcc pen interrupt to u p figure 15 pen interrupt function block asahi kasei [ak4183] ms0500-e-00 2006/04 15 package 10pin tmsop 0.5mm pitch (unit : mm) 4.00.2 2.90.2 0.5 2.80.2 1 5 6 10 1.0 max. 0.10 +0.1 -0.05 0.20.1 0.127 +0.1 -0.05 0.550.2 0~10 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: sn ? bi (pb free) asahi kasei [ak4183] ms0500-e-00 2006/04 16 marking yma (1) #1pinindicator (2) chip no. (ak4183=183) (3) year 1 digit (4) month 1digit (5) manage code (internal) (1) 10pin 6pin 1pin 5pin 183 (2) (3) (4) (5) asahi kasei [ak4183] ms0500-e-00 2006/04 17 ? these products and their specificat ions are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or system s containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the re presentative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in lo ss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet ve ry high standards of performance and reliability. ? it is the responsibility of the buy er or distributor of an akm produc t who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. important notice

asahi kasei [ak4183] ms0500-e-00 2006/04 1 ak4183 i 2 c touch screen controller sda scl pen interrupt penirqn gnd 12bit adc (sar type) vref+ ain+ vref- control logic ain- vcc cad0 yp xn yn xp block diagram features: ? 12-bit sar type a/d converter with s/h circuit ? low voltage operation (2.5v 3.6v) ? i 2 c bus i/f supports (standard mode 100 khz, fast mode 400 khz) ? 4-wire resistive touch screen interface ? pen pressure measurement ? auto power down ? continuous read operation ? low power consumption (91 a @fast mode) ? package 10pin tmsop general description: the ak4183 is a 4-wire resistive touch screen controller that incorporates sar type a/d converter. the ak4183 operates down to 2.5v supply voltage in order to connect a low voltage drive processor. the ak4183 can detect the pressed screen location by performing two a/d conversions. in addition to location, the ak4183 also measures touch pressure. as the package size of 10 pin tmsop is 4.0mm x 2.9mm this is much smaller th an qfn and bga package. ak4183 is the best fit for cellular phone, pda, or other portable devices.
asahi kasei [ak4183] ms0500-e-00 2006/04 2 ? ordering guide AK4183VT -40 c +85 c 10pin tmsop (0.5mm pitch) ? pin layout top view 10 9 6 7 8 scl sda penirqn gnd cad0 5 4 3 2 1 vcc xp xn yp yn pin/function no. signal name i/o description 1 vcc - power supply 2 xp i/o touch screen x+ plate voltage supply ? x axis measurement: supplies the voltage to x+ posit ion input of the touch panel. ? y axis measurement: this pin is used as the input for the a/d converter ? pen pressure measurement: this pin is the input for the a/d converter at z1 measurement. ? pen waiting state: pulled up by an internal resistor (typ.10k ohm). 3 yp i/o touch screen y+ plate voltage supply ? x axis measurement: this pin is used as the input for the a/d converter ? y axis measurement: supplies the voltage to y+ position input of the touch panel ? pen pressure measurement: s upplies the voltage to y+ positio n input of the touch panel. ? pen waiting state: open state 4 xn i/o touch screen x- plate voltage supply ? x axis measurement: supplies the voltage to x- position input of the touch panel ? y axis measurement: open state ? pen pressure measurement: supplies the volt age to x- position input of the touch panel ? pen waiting state: open state 5 yn i/o touch screen y- plate voltage supply ? x axis measurement: open state ? y axis measurement: supplies the voltage to y- position input of the touch panel ? pen pressure measurement: this pin is the input for the a/d converter at z2 measurement. ? pen waiting state: connected to gnd. 6 gnd - ground 7 penirqn o pen interrupt output this pin is ?l? during the pen down on pen interr upt enabled state otherwise this pin is ?h?. this pin is ?l? during pen interrupt disabled state regardless pen touch. 8 cad0 i i 2 c bus slave address bit 0 9 sda i/o i 2 c serial data 10 scl i i 2 c serial clock
asahi kasei [ak4183] ms0500-e-00 2006/04 3 absolute maximum ratings gnd = 0v (note 1) parameter symbol min max units power supplies vcc -0.3 6.0 v input current (any pins except for supplies) iin - 10 ma input voltage vin -0.3 6.0(vcc+0.3) v touch panel drive current ioutdrv 50 ma ambient temperature (power supplied) ta -40 85 c storage temperature tstg -65 150 c note 1.all voltages with respect to ground. warning: operation at or beyond these limits may result in perm anent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions gnd = 0v (note 1) parameter symbol min typ max units power supplies vcc 2.5 2.7 3.6 v note 1. all voltages with respect to ground. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet.
asahi kasei [ak4183] ms0500-e-00 2006/04 4 analog characteristics ta = -40 c to 85 c, vcc = 2.7v, i 2 c bus scl=400 khz, 12 bit mode parameter min. typ. max. units adc for touch screen resolution 12 bits no missing codes 11 12 bits integral nonlinearity (inl) error 2 lsb differential nonlinea rity (dnl) error 1 lsb offset error 6 lsb gain error 4 lsb throughput rate 8.2 ksps touch panel driver on-resistance xp, yp xn, yn 5 5 ? ? xp pull up register (when pen interrupt enable) 10 k ? power supply current fast mode: scl=400khz 91 200 a normal mode pd0=?0? addressed standard mode: scl=100khz 68 150 a fast mode: scl=400khz 23 a power down pd0=?0? not addressed standard mode: scl=100khz 6 a full power down (control command pd0= ?0? sda=scl= vcc) 0 3 a
asahi kasei [ak4183] ms0500-e-00 2006/04 5 dc characteristics (logic i/o) ta = -40 to 85 c, vcc = 2.5v to 3.6v parameter symbol min. typ. max. units ?h? level input voltage vih 0.7xvcc - v ?l? level input voltage vil - 0.3xvcc v input leakage current iilk -10 10 a ?h? level output voltage (penirqn pin@ iout = -250 a) voh vcc-0.4 v ?l? level output voltage (penirqn pin @ iout = 250 a) (sda pin @ iout = 3ma) vol 0.4 v tri-state leakage current all pins except for xp, yp, xn, yn pins xp, yp, xn, yn pins iolk -10 -50 10 50 a a switching characteristics ta = -40 to 85 c, vcc = 2.5v to 3.6v parameter (i 2 c timing) symbol min typ max units scl clock frequency fscl 30 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated st art condition tsu:sta 1.3 s sda hold time from scl falling (note 2) thd:dat 0 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 2: data must be held for sufficient time to bridge the 300 ns transition time of scl. thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 1 ak4183 timing diagram
asahi kasei [ak4183] ms0500-e-00 2006/04 6 ? a/d converter for touch screen the ak4183 incorporates a 12-bit successive approximation resi stor (sar) a/d converter fo r position measurement. the architecture is based on a capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (s /h) circuit. the sar a/d converter output is a strai ght binary format as shown below: input voltage output code ( ? vref-1.5lsb)~ ? vref fffh ( ? vref-2.5lsb) ~ ( ? vref-1.5lsb) ffeh --------- --------- 0.5lsb ~ 1.5lsb 001h 0 ~ 0.5lsb 000h ? vref: (vref+) ? (vref-) table 1 output code ? the position detection of touch screen a position detecting (x, y position) on the touc h panel is selected by the control command via the a2, a1, a0 bits in the contr ol register. the mode of the position detecting is differential mode, the full scale ( ? vref) is the differential voltage between the non- inverting terminal and the inverting terminal of the measured axis (e.g. x-axis measurement: ? vref = v xp ? v xn ). the voltage difference on the a/d converter ( ? ain) is the voltage between non- inverting terminals of the non-m easured axis and the inverting terminal of the measured axis. (e.g. ? ain= (ain+) - (ain-) = v yp -v xn ) the voltage difference ( ? ain) is charged to the internal capacitor array during the sampling period. no current flows into the internal capacitor after the capacitor has been charged completely. the required settling time to charge the internal capacitor a rray depends on the source impedanc e (rin). if the source impedan ce is 600 ohm, the settling time needs at least 2.5 s (1 clock cycle period of scl 400 khz) the position on the touch screen is detect ed by taking the voltage of one axis when the voltage is supplied between the two terminals of another axis. at least two a/d conversions are needed to get the two-dimensional (x/y axis) position. the x-plate and y-plate are connected on the dotted line when the panel is touched. xp xn x-plate (top side) y-plate (bottom side) c) 4-wire touch screen construction x-plate y-p l ate x-plate yp yn yn xn yp xn-driver sw on vref+ vref- adc ain+ ain- xp xp-driver sw on a) x-position measurement differential mode b) y-position measurement differential mode yn xn yp yn-driver sw on vref+ vref- adc ain+ ain- xp yp-driver sw on vcc vcc touch screen y-p l ate figure 2 axis measurements
asahi kasei [ak4183] ms0500-e-00 2006/04 7 the differential mode position detection is ty pically more accurate than the single-ended mode. as the full scale of single-en ded mode is fixed to the vcc, input voltage may exceed the full-sc ale reference voltage. this probl em does not occur in differenti al mode. in addition to this, the differential mode is less influenced by power supply voltage variation due to the ratio-metric measurement. ? the pen pressure measurement the touch screen pen pressure can be deri ved from the measurement of the contact resistor between two plates. the contact resistance depends on the size of the depre ssed area and the pressure. the area of the spot is proportional to the contact res istance. this resistance (rtouch) can be calc ulated using two different methods. the first method is that when the total resistance of the x-pl ate sheet is already known. the resistance, rtouch, is calculated from the results of three conversions, x-pos ition, z1-position, and z2-position, and then using the following formula: rtouch = (rxplate) * (xposition/4096) * [(z2/z1) ? 1] the second method is that when both the resi stances of the x-plate and y-plate are know n. the resistance, rtouch, is calculated from the results of three conversions, x- position, y-position, and z1-position, and then using the following formula: rtouch = (rxplate*xposition/4096)*[(4096/z1) ? 1] ? ryplate*[1 ? (yposition/4096)] xn-driver swon yn vref+ vref- adc a in+ a in- xp yp xn yp-driver sw on a) z1-position measurement rtouch xn-driver sw on yn vref+ vref- adc a in+ a in- xp yp xn yp-driver sw on b) z2-position measurement rtouch vcc vcc figure 3 pen pressure measurements
asahi kasei [ak4183] ms0500-e-00 2006/04 8 ? digital i/f the ak4183 operates with up via i 2 c bus and supports the standard mode (100 khz) and the fast mode (400khz). note that the ak4183 operates in those two modes and do es not support a high speed mode i 2 c-bus system (3.4mhz). the ak4183 can operate as the slave device on the i 2 c bus network. vcc ak4183 micro- processor i 2 c bus controller scl sda vcc=2.5v ? 3.6v cad0 penirqn rp rp ?l? or ?h? figure 4 digital i/f [start condition a nd stop condition] a high to low transition on the sda line while scl is high indicates a start condition. all sequences start by the start condition or repeated start condition. repeated start condition is the same signal tradition as start condition. a low to high transition on the sda line while scl is high defines a stop condition. all sequences are terminated by the stop or repeated start condition. repeated start is also the start condition of next transfer so that i2c bus cannot be idle. scl sda p : stop condition s : start condition s/sr sr : repeated start condition figure 5 start and stop conditions [data transfer] all commands are preceded by a start condition. after the start condition, a slave address is sent. after the ak4183 recognizes the start condition, the device interfaced to the bus waits for the slave address to be transmitted over the sda lin e. if the transmitted slave address matches an address for one of the de vices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminated by a stop condition generated by the master device.
asahi kasei [ak4183] ms0500-e-00 2006/04 9 [data validity] the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable; data valid change of data allowed figure 6 bit transfer on the i2c-bus [acknowledge] acknowledge is a software convention used to indicate successful data transfers. the transmit ting device will release the sda line (high) after transmitting eight bits. the receiver must pull down the sda line during the acknowledge clock pulse so that that it remains stable ?l? during ?h? period of this clock pulse. the ak4183 will generates an acknowledge after each byte has been received. in the read mode, the slave, ak4183 will transmit eight bits of data, release the sda line and monitor the line for an acknowle dge. if an acknowledge is detected and no stop c ondition is generated by the master, the slav e will continue to transmit data. if an acknowledge is not detected, the slave will terminate fu rther data transmissions and await the stop condition. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 7 acknowledge [address byte] the sequence of writing data is shown figure 10. the address byte , which includes seven bits of slave address and one bit of r/ w bit, is sent after the start condition. if the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls dow n the sda line (acknowledge). the most significant six bits of the slave address are fixed as ?100100?. the next one bit is cad0 (device address bit). this b it identifies the specific device on the bus. the hard-wired input pi n (cad0 pin) sets cad0 bit. the eighth bit (lsb) of the addre ss byte (r/w bit) defines whether the master requests a write or read operation. a ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. 1 0 0 1 0 0 cad0 r/w (cad0 should match with cad0 pins) figure 8 address byte
asahi kasei [ak4183] ms0500-e-00 2006/04 10 [write operations] the second byte that followed by address byte consists of the control command byte of the ak4183. the operational mode is determined by control command. the bit form at is msb first and 8 bits width. contro l command is described in the table 3. the ak4183 generates an acknowledge after each byte has been received. a control command transfer is terminated by a stop condition or repeated start condition generated by the master. refer to the table 3 in detail. d7 d6 d5 d4 d3 d2 d1 d0 s a2 a1 a0 x1 pd0 mode x2 figure 9 control command byte start r/w=?0? address command s ak4183 ack ack ak4183 stop p sda figure 10 single write transmission sequence [read operation] the operation mode is determined by the wr ite command just before read operation. ak4183 features two methods of read operation, single read op eration and continuous read ope ration. the continuous read operation is a series of single read opera tion. each single read operation in conti nuous read operation make ak4183 updated a/d conversion on each read operation. write operation does not need to issue before each read operations are executed. the channel selection of ak4183 defines by the control command ju st before read operation. when the address byte with r/w = ?1? read operations are executed. a/d readout format is msb first, 1byte or 2byt es width. upper 8bits are valid on 8-bit mo de and upper 12 bits are valid, and lower 4 bi ts are filled with zero on 12-bit mode. [single read mode] read operation begins with start condition followed by the ad dress byte with r/w= ?1?.the address matches ak4183 generates ack. and after transmission of the address byte, the master receives upper 8bit a/d data first, an d generates ack. the ak4183 transmits the remaining 4-bit a/d data and followed by 4-bit zero data (12bit mode). master devi ce receives 8bit a/d data (8bi t mode). the master then generates nack and stop condition or repeated start condition. start a/d data ack ack stop nack a/d data sda d11 d4 d3 s p ak4183 master master d0 address r/w=?1? figure 11 single a/d data r ead sequence (12-bit mode)
asahi kasei [ak4183] ms0500-e-00 2006/04 11 [continuous read mode] this continuous read operation enables the higher sampling rate and lower processor load than a single read operation. because once control command is sent, it does not need to update control command on each read operation until another control command would like to be rewritten. start a/d data a/d data sda d11 d4 s ack ak4183 ack master nack master d0 d3 stop p n n d11 d4 d0 d3 a/d data n+x n+x a/d data nack master ack ak4183 ack master sr repeat restart address address r/w=?1? r/w=?1? figure 12 continuous a/d data read sequence ? power on sequence it is recommended that the control command must be sent to fix th e internal register when power up. this initiates all register s such as a2-0 bit, pd0 bit, and mode bit. once sending command to fix the internal regist er after first power up, the state of ak4183 is held on the known-condition of state to ensure that ak4183 is go ing into desire mode to realize lowest mode. a command with pd0= ?0? should be sent so that ak4183 w ill be set in the lowest power down mode. ? sleep mode ak4183 supports the sleep mode that enables touch panel interface to put open state and disables pen interrupt function. ak4183 goes into the sleep mode when control comma nd is sent to ak4183 as shown table 2. the selection of the sleep mode is set by ?mode? bit of the control command. the st ate of both the output of penirqn pin and the connection with touch panel interface (xp, yp, xn, and yn) are the following table 2. ak4183 k eeps the sleep mode until next control command is sent. command mode bit penirqn touch panel 0111xx1x 1 hi-z open 0111xx0x 0 ?h? output open table 2 sleep command setting the timing of going into the sleep mode is the rising edge of the 16 th scl of the write operation. a/d conversion does not execute when the sleep command is sent. sda pin is ?h? since sda is pull up. in order for going to normal mode from sleep mode the command (s= ?1?) is sent. the timing of going back to normal mode is the rising edge of the 16 th scl. when the sleep command is sent again under the sleep mode the mode continues the same as before. the initial state after power up is in normal mode.
asahi kasei [ak4183] ms0500-e-00 2006/04 12 ? control command the control command, 8 bits, provided to the ak4183 via sda, is shown in the following table. this command includes start bit, channel selection bit, power-down bit and re solution bit. the ak4183 latches the serial command at the rising edge of scl. ref er to the detailed information regarding the bi t order, function, the status of driver switch, adc input as shown in table 3. bit name function 7 s start bit. ?1? accelerate and axis command, ?0?: sleep mode command 6-4 a2-a0 channel selection bits. analog inputs to th e a/d converter and the activated driver switches are selected. please see the following table for the detail. 3 x1 don?t care 2 pd0 power down bit (refer to power-down control) 1 mode resolution of a/d converter. ?0?: 12 bit output ?1?: 8 bit output 0 x2 don?t care input status of driver switch adc input ( ? ain) reference voltage ( ? vref) s a2 a1 a0 xp xn yp yn ain+ ain- vref+ vref- note 0 1 1 1 sleep 1 0 0 0 on on off off yp xn xp xn accelerate x-driver 1 0 0 1 off off on on xp yn yp yn accelerate y-driver 1 0 1 0 off on on off xp xn yp xn 1 0 1 1 off on on off yn xn yp xn accelerate y+, x- driver 1 1 0 0 on on off off yp xn xp xn x-axis 1 1 0 1 off off on on xp yn yp yn y-axis 1 1 1 0 off on on off xp (z1) xn yp xn z1 (pen pressure) 1 1 1 1 off on on off yn (z2) xn yp xn z2 (pen pressure) table 3 control command list ? power-down control a/d converter and power-down cont rol of touch driver switch are determined by pd0 bit. pd0 penirqn function 0 enabled auto power-down mode a/d converter is automatically powered up at th e start of the conversion, and goes to power- down state automatically at the e nd of the conversion. all touch screen driver switches except for yn switch are turned off and relative pins are open state. only yn driver switch is turned on and yn pin is forced to the ground in this case. pen interrupt function is enabled except for the sampling time and conversion time. 1 disabled adc on mode when x-axis or y-axis are selected on the wr ite operation with pd0 = ?1? a/d converter and touch panel driver are always powered up until ne xt conversion. this mode is effective if more settling time is required to suppress the electrical bouncing of touch plate. pen interrupt function is disabled and penirqn is forced to ?l? state table 4 powers ?down control
asahi kasei [ak4183] ms0500-e-00 2006/04 13 ? write operation sequence (figure 13) the selection of channel input of ak4183 is determined by a command byte. the timing of the driver switch on is 18 th falling edge of scl regardless pd0 bit when accelerate command (a2= ?0?) is sent. the accelerate command is to accelerate the timing of desired driver sw on to ensure that ak4183 needs more settling tim e. as for actually sampling is on the time of read operation, it becomes possible to take settling time long even when the impedance of the touch screen is large. ak4183 ack 0 touch driver sw ak4183 ack s x1 a2=0, pd0=0 or 1 a2=1 , pd0=0 a2 pd0 stop a2=1, pd0=1 mode a1 a0 x2 cad0 0 19 i ii iii iv command byte scl sda start 1 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 0 0 r/ w address byte figure 13 write operation and driver sw timing ? read operation sequence (figure. 14) a/d conversion is synchronized with scl. samp ling time is the one scl clock period (scl7 scl8 ) on the end of writing address byte and then hold. a/d conversion is held on the next 12 scl period (except master ack) .the readout sequence is that after command byte has been sent, ak4183 respond with acknowle dge if the address matches. the msb data byte will follow (d11 d4) then issued acknowledge by master. the lsb data byte (d3 d0, followed four ?0?) will be follo wed by not acknowledge bit (nack) from master in order to terminate the read transfer. the master will then issued stop that ends read operation or repeated start condition that keeps write or read ope ration. the master will issue repeated start condition or st art condition followed by read operation again. ak4183 repeats a/d data updated [continuous read operation]. master must issue stop condition after terminating the last read out of a/d data. address byte data byte (msb) data byte (lsb) master ack master nack 0 ?h? a2=?0? or a2=?1? , pd0=?1? a2=?1?, pd0=?0? sampling ad conversion 0 a2=?0?, pd0=?0? 28 v vi scl sda start 1 0 0 1 0 cad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 0 0 ak4183 ack d11 d10 d9 d8 d7 d6 d4 d5 r/ w 19 20 21 22 23 24 25 26 27 d3 d2 d1 d0 0 0 0 1 0 to uc h d r iv e r sw stop or repeated star t iv figure 14 read data sequence
asahi kasei [ak4183] ms0500-e-00 2006/04 14 ? pen interrupt the ak4183 has a pen-interrupt function to detect the pen touch on the touch panel. this function will use as the interrupt of the microprocessor. pen interrupt function is enabled at power-down st ate. yn driver is on and this pin is connected to gnd at the power down state. and xp pin is pulled up vi a an internal resister (ri), typically 10k ? . if the touch plate is touched by pen or stylus, the current flow s via ---

--. the resistance of the plate is generally 1k ? or less, peniqrn pin is force to ?l? level. if the pen is released, peni rqn returns ?h? level because two plates are disconnected, and t he current does not flow via two plates. the transition of penirqn is related to pd0 bit. pd0 bit is upd ated as shown below. (please see ?power-down control? for the detail. once the control command with pd0= ?1? is sent the pen-interrupt function is disabled. the clock number under the write and the read operation refer to figure 13 and figure 14. i. the period from start condition to scl7 the level transition of penirqn pin is determined by pd0 bit of the previous command. when the previous command with pd0= ?0? the pen-interrupt function w ill be enabled. penirqn pin is low wh en the panel is touch, penirqn pin is ?h? when the panel is untouched. when the previous command with pd0= ?1? is sent penirqn pin is low regardless of pen-touch ii. the period scl7 to scl8 on the write operation the level of penirqn pin is always low regardless of pd0 bit and the state of pa nel (touched/untouched) iii. the period from scl8 to scl18 on the write operation the level transition of penirqn pin is determined by pd0 bit of the previous command. when the previous command with pd0= ?0? the pen-interrupt function w ill be enabled. penirqn pin is low wh en the panel is touch, penirqn pin is ?h? when the panel is untouched. when the previous command with pd0= ?1? is sent penirqn pin is low regardless of pen-touch iv. the period from scl18 on the write operation to scl7 on the read operation the level of penirqn pin is determined by the a2 bit and pd0 bit of the present command. penirqn pin is always low regardless pen-touch when command with a2 = ?1? or pd0 = ?1? is set. penirqn is determined by the pen-touch (touched/untouched) when command with a2= ?1? and pd0= ?1? is sent. v. the period from scl7 to scl21 on the write operation the ad input will sample the hold and the conversion will be done during this period. penirqn is always low. vi. the period after scl21 on the read operation the level transition of penirqn pin is determined by pd0 bit of the present command. when the present command with pd0= ?0? is sent the pen-interrupt func tion will be enabled. penirqn pin is low when the panel is touched. penirqn pin is ?h? when the panel is untouched. when the pr esent command with pd0= ?1? are sent penirqn pin is low regardless of pen-touch. it is recommended that the processor will mask the pseudo interrupt while the control command is issued or ad data is sent to processor. xp penirqn driver on yn en2 ri = 10k ? driver off en1 vcc vcc vcc pen interrupt to u p figure 15 pen interrupt function block
asahi kasei [ak4183] ms0500-e-00 2006/04 15 package 10pin tmsop 0.5mm pitch (unit : mm) 4.00.2 2.90.2 0.5 2.80.2 1 5 6 10 1.0 max. 0.10 +0.1 -0.05 0.20.1 0.127 +0.1 -0.05 0.550.2 0~10 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: sn ? bi (pb free)
asahi kasei [ak4183] ms0500-e-00 2006/04 16 marking yma (1) #1pinindicator (2) chip no. (ak4183=183) (3) year 1 digit (4) month 1digit (5) manage code (internal) (1) 10pin 6pin 1pin 5pin 183 (2) (3) (4) (5)
asahi kasei [ak4183] ms0500-e-00 2006/04 17 ? these products and their specificat ions are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or system s containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the re presentative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in lo ss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet ve ry high standards of performance and reliability. ? it is the responsibility of the buy er or distributor of an akm produc t who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. important notice

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