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ds07-12528-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89143a/144a series mb89143a/144a n description the mb89143a/144a has been developed as a general-purpose version of the f 2 mc-8l* family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain peripheral functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, an a/d converter, buzzer output, high voltage driver, watch prescaler, and an external interrupt. the mb89143a/144a is applicable to a wide range of applications from welfare products to industrial equipment. * f 2 mc stands for fujitsu flexible microcontroller. n features ? minimum execution time: 0.50 m s/8.0-mhz oscillation ? interrupt servicing time: 4.50 m s/8.0-mhz oscillation ?f 2 mc-8l family cpu core multiplication and division instructions instruction set optimized for controllers 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. ? dual-clock control system ? high-voltage ports: 24 channel (continued) n package (dip-64p-m01) 64-pin plastic sh-dip
2 mb89143a/144a (continued) ? two types of timers 8/16-bit timer/counter (also usable as two 8-bit timers) 21-bit time-base timer ? one 8-bit serial interface switchable transfer direction allows comunication with various equipment. ? 8-bit a/d converter: 8 channels successive approximation type ? external interrupt: 2 channels two channels are independent and capable of wake-up from low-power consumption modes. (rising edge/ falling edge/both edges selectability) C0.3 v to +7.0 v can be applied to int1 (n-ch open-drain) ? low-power consumption modes subclock mode (the main clock stops, and the device operates at the subclock.) watch mode (only the watch prescaler is operating.) stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) ? watch prescaler ? buzzer output ? watchdog reset, reset output, and power-on reset functions
3 mb89143a/144a part number n product lineup (continued) MB89144A mb89144/5/6 mb89p147 mb89pv140 classification mass production products (mask rom products) one-time prom product piggyback/evaluation product (for evaluation and development) rom size 8 k 8 bits 12 k 12 bits 12/16/24 k 8 bits 32 k 8 bits internal prom 32 k 8 bits external rom (piggyback) ram size 256 8 bits 256/512/768 8 bits 1 k 8 bits internal cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.5 m s/8 mhz to 8.0 m s/8 mhz, 61 m s/32.768 khz interrupt processing time: 4.5 m s/8 mhz to 72.0 m s/8 mhz, 562.5 m s/32.768 khz note: the above times change according to the gear function. ports high-voltage output ports (p-ch open-drain): 24 (p40 to p47, p50 to p57, and p60 to p67) buzzer output (p-ch open-drain, high-voltage): 1 output ports (cmos): 4 (p20 to p23) input ports (cmos): 2 (p70 and p71, function as x0a and x1a pins when dual-clock system is used.) i/o ports (cmos): 23 (p00 to p07, p10 to p17, p30, and p32 to p37) i/o port (n-channel open-drain): 1 (p31) to t a l : 5 5 time-base timer capable of generating four different intervals (at 8.0-mhz oscillation): 0.26 ms, 0.51 ms, 1.02 ms, and 0.524 s 8/16-bit timer counter 8/16-bit timer operation (operating clock, internal clock, external trigger) 8/16-bit event counter operation (rising edge/falling edge/both edges selectability) 8-bit serial i/o 8 bits lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles) a/d converter 8-bit resolution 8 channels a/d conversion mode (with conversion time of 22 m s/8 mhz, and highest gear speed) continuous activation by external activation cabable 10-bit resolution 12 channels a/d conversion mode (with conversion time of 16.5 ms/ 8 mhz, and highest gear speed) sense mode (with conversion time of 9.0 m s/8 mhz, and highest gear speed) continuous activation enabled by external activation capable external interrupt 2 independent channels (edge selection, interrupt vector, source flag) rising edge/falling edge/both edges selectability built-in analog noise canceller used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) buzzer output 1.95 or 3.91 khz selectable (at 8-mhz oscillation) output to a high-voltage pin mb89143a parameter
4 mb89143a/144a part number (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) n package and corresponding products : available : not available * : under examination for development note: for more information about each package, see section n package dimensions. MB89144A mb89144/5/6 mb89p147 mb89pv140 watchdog reset internal reset in 524 to 1049 ms (at 8 mhz oscillation) when the program runway occurs 8-bit pwm timer none 8-bit timer operation/8-bit resolution pwm operation 12-bit mpg timer none 12-bit resolution pwm operation/reload timer operation/ ppg operation standby mode sleep mode, stop mode, and watch mode process cmos package dip-64p-m01 dip-64p-m01 fpt-64p-m06 mdp-64c-p02 mqp-64c-p01 eprom for use mbm27c256a-20 operating voltage* 4.0 v to 6.0 v 2.7 v to 6.0 v package mb89143a MB89144A mb89p147 mb89pv140 dip-64p-m01 fpt-64p-m06 mdp-64c-p02 mqp-64c-p01 mb89143a parameter
5 mb89143a/144a n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? on the mb89143a/144a, the upper half of the register bank cannot be used. ? the stack area, etc., is set at the upper limit of the ram. 2. functions before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following point: ? the a/d converter in the mb89143a/144a is an 8-bit resolution type. the mb89143a/144a contains neither the 8-bit pwm timer nor the 12-bit mpg timer. 3. current consumption ? in the case of the mb89pv140, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see section n electrical characteristics.) 4. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following point: ? a pull-up resistor option is not provided for the mb89pv140.
6 mb89143a/144a n pin assignment (dip-64p-m01) (top view) 1 bz 2 p67 3 p66 4 p65 5 p64 6 p63 7 p62 8 p61 9 p60 10 n.c. 11 p57 12 p56 13 p55 14 p53 15 p50 16 p47 17 p46 18 p45 19 p44 20 p43 21 p42 22 p41 23 p40 24 p23 25 rst 26 moda 27 x0 28 x1 29 v ss v cc 64 avr 63 av ss 62 p00/an0 61 p01/an1 60 p02/an2 59 p03/an3 58 p04/an4 57 p05/an5 56 p06/an6 55 p07/an7 54 p10 53 p11 52 p12 51 p13 50 p14 49 p15 48 p16 47 p17/adst 46 p30/int0 45 p31/int1 44 p32/sck 43 p33/so 42 p34/si 41 p35/ec 40 p36 39 p37 38 p20 37 p21 36 30 31 32 p22 35 p70/x0a 34 p71/x1a 33 p54 p52 p51 when used as general-purpose ports, the p70/x0a and p71/x1a functions as input-only ports.
7 mb89143a/144a n pin description (continued) pin no. pin name circuit type function sdip* 30 x0 a main clock oscillator pins use a crystal oscillator. 31 x1 29 moda b operating mode selection pin connect directly to v ss in normal operation. 28 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. this pin is with a noise canceller. 54 to 61 p07/an7 to p00/an0 f general-purpose i/o ports these ports are a hysteresis input type. also serve as an analog input. 46 p17/adst h general-purpose i/o port this port is a hysteresis input type. also serves as an a/d converter external activation. 47 to 53 p16 to p10 h general-purpose i/o ports these ports are a hysteresis input type. 34, 33 p70/x0a, p71/x1a j selectable either general-purpose input ports or the subclock oscillator pins by the mask option. these ports are a hysteresis input type when used as general-purpose input ports. 27, 35 to 37 p23 to p20 d general-purpose output ports 38, 39 p37, p36 h general-purpose i/o ports these ports are a hysteresis input type. 40 p35/ec general-purpose i/o port this port is a hysteresis input type. also serves as the external clock input for the 8/16-bit timer/counter. 41 p34/si general-purpose i/o port this port is a hysteresis input type. also serves as the serial data input for the 8-bit serial interface. 42 p33/so general-purpose i/o port this port is a hysteresis input type. also serves as the serial data output for the 8-bit serial interface. 43 p32/sck general-purpose i/o port this port is a hysteresis input type. also serves as the serial transfer clock for the 8-bit serial interface. * : dip-64p-m01
8 mb89143a/144a (continued) * : dip-64p-m01 pin no. pin name circuit type function sdip* 44 p31/int1 e general-purpose i/o port this port is an n-ch open-drain outupt and hysteresis input type. also serves as an external interrupt. the interrupt input is a hysteresis input type and with a built-in noise canceller. 45 p30/int0 i general-purpose i/o port this port is a hysteresis input type. also serves as an external interrupt. the interrupt input is a hysteresis input type and with a built-in noise canceller. 1 bz g buzzer output-only pin p-ch high-voltage open-drain output port 19 to 26, 11 to 18, 2 to 9 p47 to p40, p57 to p50, p67 to p60 g p-ch high-voltage open-drain output port 10 n.c. be sure to leave them open. 64 v cc power supply pin also serves as an a/d converter power supply. 32 v ss power supply (gnd) pin 63 avr a/d converter reference voltage input pin 62 av ss a/d converter power supply pin use this pin at the same voltage as v ss .
9 mb89143a/144a n i/o circuit type (continued) type circuit remarks a ? at an oscillation feedback resistor of approximately 1 m w /5.0 v b c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? cmos hysteresis input d ? cmos output e ? n-ch open-drain output ? cmos hysteresis input ? the interrupt input is with a noise canceller. f ? cmos output ? cmos hysteresis input x1 x0 standby control signal r p-ch n-ch hysteresis input p-ch n-ch n-ch hysteresis input port interrupt input with noise canceller p-ch n-ch hysteresis input port analog input
10 mb89143a/144a (continued) type circuit remarks g ? p-ch high-voltage open-drain output h ? cmos output ? cmos hysteresis input ? pull-up resistor optional (only for p14 to p17 and p32 to p37) i ? cmos output ? cmos hysteresis input ? the interrupt input is with a noise canceller. j ? the oscillation feedback resistor is not provided. ? cmos hysteresis input when subclock is not used p-ch hysteresis input port p-ch n-ch p-ch p-ch n-ch hysteresis input with noise canceller port interrupt input x1a x0a hysteresis input hysteresis input port port standby control signal
11 mb89143a/144a n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . (however, up to 7.0 v can be applied to p31/int1 pin, regardless of v cc .) when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency(50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode.
12 mb89143a/144a n block diagram x0 x1 p70/x0a clock controller subclock oscillator (32.768 khz) cmos input port port 7 ram (256 8 bits) f 2 mc-8l cpu rom v cc , v ss , moda, rst other pins buzzer output 8-bit serial interface p35/ec p32/sck p60 to p67 bz time-base timer 8-bit a/d converter cmos i/o port 1 p17/adst p10 to p16 avr av ss high-voltage port 6 8/16-bit timer/ counter p30/int0 p31/int1 p71/x1a cmos output port port 2 p20 to p23 7 cmos i/o port 0 p07/an7 to p00/an0 8 p50 to p57 p40 to p47 external interrupt p33/so p34/si cmos i/o port n-ch open-drain port note: the a/d converter is an 8-bit, 8-channel type. main clock oscillator (max. 8 mhz) internal bus high-voltage port 5 high-voltage port 4 port 3 port 3 4 8 8 8
13 mb89143a/144a n cpu core 1. memory space the microcontrollers of the mb89143a/144a series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89143a/144a series is structured as illustrated below. ffff h mb89143a 0000 h 0080 h 0100 h i/o ram 256 register not available rom 8 kb 0180 h e000 h MB89144A 0000 h 0080 h 0100 h i/o ram 256 register rom 12 kb 0180 h d000 h not available ffff h
14 mb89143a/144a 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
15 mb89143a/144a the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
16 mb89143a/144a the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 16 banks can be used on the mb89143a/144a. the bank currently in use is indicated by the register bank pointer (rp). register bank configuraiton this address = 0100 h + 8 (rp) memory area 16 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
17 mb89143a/144a n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h vacancy 06 h vacancy 07 h (r/w) sycc system clock control register 08 h (r/w) stbc standby control register 09 h (r/w) wdte watchdog timer control register 0a h (r/w) tbcr time-base timer control register 0b h (r/w) wpcr watch prescaler control register 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) buzr buzzer register 0f h (r/w) eic external interrupt control register 10 h (r/w) pdr4 port 4 data register 11 h (r/w) pdr5 port 5 data register 12 h (r/w) pdr6 port 6 data register 13 h (r) pdr7 port 7 data register 14 h vacancy 15 h vacancy 16 h vacancy 17 h vacancy 18 h (r/w) t3cr timer 3 control register 19 h (r/w) t2cr timer 2 control register 1a h (r/w) t3dr timer 3 data register 1b h (r/w) t2dr timer 2 data register 1c h (r/w) smr serial mode register 1d h (r/w) sdr serial data register 1e h (r/w) adc1 a/d converter control register 1 1f h (r/w) adc2 a/d converter control register 2
18 mb89143a/144a (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) addh a/d data register (h) 21 h (r/w) addl a/d data register (l) 22 h (w) pcr0 port input control register 0 23 h (w) pcr1 port input control register 1 24 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
19 mb89143a/144a n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: take care so that avr does not exceed v cc + 0.3 v and v cc , such as when power is turned on. *2: v i and v o must not exceed v cc + 0.3 v. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc avr v ss C 0.3 v ss + 7.0 v avr v cc +0.3 *1 input voltage v i1 v ss C 0.3 v cc + 0.3 v p00 to p07, p10 to p17, p30, p32 to p37, p70, p71 v i2 v ss C 0.3 7 v p31 v i3 v cc C 40 v cc + 0.3 v p40 to p47, p50 to p57, p60 to p67, bz *2 output voltage v o1 v ss C 0.3 v cc + 0.3 v p00 to p07, p10 to p17, p20 to p23, p30 to p37 v o2 v cc + 0.3 v p40 to p47, p50 to p57, p60 to p67, bz *2 h level total maximum output current s i oh C100 ma h level total average output current s i ohav C75ma averge value (operating current operation rate) h level maximum output current i oh C12 ma p00 to p07, p30, p32 to p37, p10 to p17, p20 to p23 average value (operating current operation rate) h level average output current i ohav C6 h level maximum output current i oh C20 ma p40 to p47, p50 to p57, p60 to p67, bz average value (operating current operation rate) h level average output current i ohav C10 l level total maximum output current s i ol 50ma l level total average output current s i olav 30ma average value (operating current operation rate) l level maximum output current i ol 12 ma p00 to p07, p10 to p17, p20 to p23, p30 to p37 l level average output current i olav 6 power consumption p d 470 mw sdip64 : dip-64p-m01 operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
20 mb89143a/144a 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency, instruction cycle, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. figure 1 operating voltage vs. main clock operating frequency figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. parameter symbol value unit remarks min. max. power supply voltage v cc 4.0* 6.0* v normal operation assurance range* at highest gear speed 3.5* 6.0* v normal operation assurance range* at highest gear speed 2.5 6.0 v when in watch mode or subclock operation mode 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 v cc v operating temperature t a C40 +85 c 1 2 3 4 5 6 2 operation assurance range 6 main clock operating frequency (at an instruction cycle of 4/f ch ) (mhz) 345 78 2.0 1.3 minimum execution time (instruction cycle) ( m s) 0.8 0.5 0.57 910 0.4 0.44 0.66 1.0 operating voltage (v)
21 mb89143a/144a 3. dc characteristics (avr = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage v ihs p00 to p07, p10 to p17, p30 to p37, p70, p71, x0, rst , x1, moda 0.8 v cc v cc + 0.3 v l level input voltage v ils p00 to p07, p10 to p17, p30 to p37, p70, p71, x0, rst , x1, moda v ss C 0.3 0.2 v cc v open-drain output pin application voltage v d1 p31 v ss C 0.3 7.0v h level output voltage v oh1 p00 to p07, p10 to p17, p20 to p23, p30 to p37 i oh = C2.0 ma 2.4 v except p31 v oh2 p40 to p47, p50 to p57, p60 to p67 i oh = C10 ma 3.0 v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p23, p30 to p37 i ol = 1.8 ma 0.4 v v ol2 rst i ol = 4.0 ma 0.6 v input leakage current i li1 p00 to p07, p10 to p17, p30 to p37, p70, p71 0 v < v 1 < v cc 5 m a except pins with pull-up resistor i li2 p14 to p17, p32 to p37 v i = 0.0 v C200 C100 C50 m a only for pins with pull-up resistor output leakage current i lo1 p40 to p47, p50 to p57, p60 to p67 v i = v cc C 35 v C10 m a pull-up resistance r pull rst , p14 to p17, p32 to p37 v i = 0.0 v 25 50 100 k w power supply current i cc1 v cc f ch = 8 mhz, v cc = 5.0 v, t inst = 0.5 m s, when a/d conversion is stopped 915ma
22 mb89143a/144a (continued) (avr = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: the power supply current is measured at the external clock. parameter symbol pin condition value unit remarks min. typ. max. power supply current i cc2 v cc f ch = 8 mhz, v cc = 3.5 v, t inst = 8.0 m s, when a/d conversion is stopped 1.5 2ma i ccs1 f ch = 8 mhz v cc = 5.0 v t inst = 0.5 m s 3 7ma i ccs2 f ch = 8 mhz v cc = 3.5 v t inst = 8.0 m s 11.5ma i ccl f cl = 32.768 khz v cc = 3.0 v subclock mode 50 150 m a i ccls f cl = 32.768 khz v cc = 3.0 v subclock mode 2550 m a i cct f cl = 32.768 khz v cc = 3.0 v ? watch mode ? main clock stop mode at dual-clock system 315 m a i cch f cl = 32.768 khz t a = +25 c ? subclock stop mode ? main clock stop mode at single-clock system 10 m a i cca f ch = 8 mhz, v cc = 5.0 v, t a = +25 c, t inst = 0.5 m s, when a/d conversion is activated 11.5 19.5 ma when the gear function is used, the power supply current varies with the measurement point. i r avr f ch = 8 mhz, t a = +25 c, when a/d conversion is activated 200 m a i rh f ch = 8 mhz, t a = +25 c, when a/d conversion is stopped 10 m a input capacitance c in other than av ss , avr, v cc , and v ss f = 1 mhz 10 pf sleep mode
23 mb89143a/144a 4. ac characteristics (1) reset timing (avr = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: t xcyl is the oscillation cycle (1/f ch ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. typ. max. rst l pulse width t zlzh 16 t xcyl ns rst noise limit width t zlnc 204060 ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50ms power-on reset function only power supply cut-off time t off 1ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh t zlnc 0.2 v 0.2 v 2.0 v 0.2 v t r v cc t off
24 mb89143a/144a (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. typ. max. clock frequency f ch x0, x1 2 8 mhz f cl x0a, x1a 32.768 khz clock cycle time t xcyl x0, x1 125 500 ns t lxcyl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 30 ns external clock p whl p wll x0a 15.2 ns input clock rising/ falling time t cr t cf x0, x0a 10 ns external clock 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open c0 c1 t xcyl p wh p wl x0 and x1 timings and conditions main clock conditions
25 mb89143a/144a (4) instruction cycle note: when operating at 8 mhz, the cycle varies with the set execution time. parameter symbol value (typical) unit remarks instruction cycle time t inst 4/f ch , 8/f ch , 16/f ch , 32/f ch m s (4/f ch ) t inst = 0.5 m s when operating at f ch = 8 mhz 2/f cl m s t inst = 61.036 m s when operating at f cl = 32.768 khz 0.2 v cc 0.8 v cc x0a 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0a x1a when a crystal or ceramic resonator is used c0 c1 r d rf x0a x1a when an external clock is used open p whl p wll t lxcyl note: the subclock oscillator feedback resistor is connected externally in dual-clock products. x0a and x1a timings and conditions subclock conditions
26 mb89143a/144a (5) serial i/o timing (avr = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s t scyc t slov t shix t ivsh sck 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc so si t slsh t slov t shix t ivsh sck 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc so si 0.2 v cc t shsl 0.8 v cc internal shift clock mode external shift clock mode
27 mb89143a/144a (6) peripheral input timing (avr = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (7) peripheral input noise limit width (avr = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: the minimum values is always canceled, while values over the maximum value are not canceled. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width 1 t ilih1 ec, adst, int0 to int1 2 t inst m s peripheral input l pulse width 1 t ihil1 ec, adst, int0 to int1 2 t inst m s parameter symbol pin value unit remarks min. typ. max. peripheral input h level noise limit width 1 t ihnc1 int1, int0 50 100 250 ns peripheral input l level noise limit width 1 t ilnc1 int1, int0 50 100 250 ns 0.2 v cc 0.8 v cc t ihil1 int0 to int1, ec, adst 0.2 v cc t ilih1 0.8 v cc int0, int1 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc t ilnc1 t ihnc1
28 mb89143a/144a 5. a/d converter electrical characteristics (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, f ch = 8 mhz, t a = C40 c to +85 c) notes: the smaller the | avr C av ss |, the greater the error would become relatively. the output impedance of the external circuit for the analog input must satisfy the following conditions: output impedance of the external circuit < approx. 10 k w if the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 22 m s at 8 mhz oscillation). parameter symbol pin condition value unit remarks min. typ. max. resolution 8 bit total error 3.0 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot an0 to an7 av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst an0 to an7 avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 1.0lsb a/d conversion time 44 t inst m s sense mode conversion time 12 t inst m s analog port input current i ain an0 to an7 avr = v cc = 5.0 v 10 m a analog input voltage an0 to an7 0 avr v reference voltage avr 4.5 v cc v reference-voltage supply current i r avr avr = 5.0 v 200 m a analog input pin sample hold circuit c = 33 pf if the analog input impedance is 10 k w or more, it is recommended to connect an external capacitor of approx. 0.1 m f. comparator r = 6 k w analog channel selector close for 8 instruction cycles after activating a/d conversion. . . . . analog input equivalent circuit
29 mb89143a/144a 6. a/d glossary ? resolution analog changes that are identifiable with the a/d converter ? linearity error the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error the difference between actual and theoretical value this error is caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. 1111 1111 1111 1110 0000 0010 0000 0001 0000 0000 theoretical i/o characteristics analog input 1 lsb = 256 digital output 1 lsb linearity error = avr (1 lsb n + v ot ) actual conversion value theoretical conversion value linearity error v fst v ot v (n+1)t v nt v (n+1)t - v nt 1 lsb differential linearity error = 1 lsb total error = - 1 v nt - (1 lsb n + 0.5 lsb) v nt - (1 lsb n + v ot )
30 mb89143a/144a n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
31 mb89143a/144a (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
32 mb89143a/144a table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
33 mb89143a/144a table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 todf d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 ? ? c c ? a ? a
34 mb89143a/144a (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) +off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
35 mb89143a/144a n instruction map 0123456789 abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
36 mb89143a/144a n mask options n ordering information no. mb89pv140 mb89p147v1 specification method specify when ordering masking 101 102 set in eprom 1 clock mode selection single-clock mode dual-clock mode can be set single clock dual clock can be set 2 pull-up resistors p14 to p17, p32 to p37 specify by pin without pull- up resistor without pull- up resistor can be set per pin 3 power-on reset with without with power-on rest with power- on reset with power- on reset can be set 4 reset output with without can be set with reset output with reset output can be set 5 pull-down resistors p40 to p47 p50 to p57 p60 to p67 without pull-down resistor without pull- down resistor without pull- down resistor without pull-down resistor part number package remarks mb89143ap MB89144Ap 64-pin plastic sh-dip (dip-64p-m01) mb89143a/144a part number parameter
37 mb89143a/144a n package dimensions +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c 64-pin plastic sh-dip (dip-64p-m01) dimensions in mm (inches)
38 mb89143a/144a fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited no. 51 bras basah road, plaza by the park, #06-04 to #06-07 singapore 189554 tel: 336-1600 fax: 336-1609 f9606 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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