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general description the hi-3598 and hi-3599 from holt integrated circuits are silicon gate cmos ics for interfacing eight arinc 429 receive buses to a high-speed serial peripheral interface (spi) enabled microcontroller. each receiver has user- programmable label recognition for up to 16 labels, a four- word data buffer (fifo), and an on-chip analog line receiver. receive fifo status can be monitored using the programmable external interrupt pins, or by polling the status register. other features include the ability to switch the bit-signifiance of the arinc 429 label, and to recog- nize the 32nd received arinc bit as data or a parity flag. versions are available with different input resistance values to provide flexibility when using external lightning protection circuitry. the serial peripheral interface minimizes the number of host interface signals, providing a small footprint device which can be interfaced to a wide variety of industry- standard microcontrollers supporting spi. alternatively, the spi interface may be controlled using four general purpose i/o port pins from a microcontroller or custom fpga. the spi and all control signals are cmos and ttl compatible and support 3.3v or 5v operation. the hi-3599 is identical to the hi-3598 except not all pins are available. this allows a minimum package footprint to be achieved with only slightly less hardware flexibility. features arinc 429 compliant 8 independent receive channels 3.3v or 5.0v logic supply operation on-chip analog line receivers connect independent data rate selection for each receiver directly to arinc 429 bus programmable label recognition for 16 labels per channel four-wire spi interface label bit-order control 32nd bit can be data or parity reduced pin-count version (hi-3599) for minimum footprint low power industrial & extended temperature ranges pin configurations (top view) octal arinc 429 receivers with label recognition and spi interface (ds3598 rev. a) 05/09 may 2009 hi-3598 full function, full pin-out version 52 - pin plastic quad flat pack (pqfp) (see ordering information for additional pin configurations) hi-3598 full function, full pin-out version 52 - pin plastic quad flat pack (pqfp) hi-3599 minimum footprint, reduced pin-out version 24 - pin plastic small outline package (soic) (see ordering information for additional pin configurations) hi-3598pqi & hi-3598pqt 52 - flag1 51 - flag2 50 - flag3 49 - flag4 48 - flag5 47 - flag6 46 - flag7 45 - flag8 44 - vdd 43 - flag 42 - rin8b 41 - rin8b-40 40 - rin8a-40 39 - rin8a 38 - rin7b 37 - rin7b-40 36 - rin7a-40 35 - rin7a 34 - rin6b 33 - rin6b-40 32 - rin6a-40 31 - rin6a 30 - rin5b 29 - rin5b-40 28 - rin5a-40 27 - rin5a rin2a - 14 rin2a-40 - 15 rin2b-40 - 16 rin2b - 17 rin3a - 18 rin3a-40 - 19 rin3b-40 - 20 rin3b - 21 gnd-22 rin4a - 23 rin4a-40 - 24 rin4b-40 - 25 rin4b - 26 aclk - 1 sck - 2 -3 si - 4 so - 5 mr - 6 tx1 - 7 tx0 - 8 rin1a - 9 rin1a-40 - 10 rin1b-40 - 11 rin1b - 12 n/c-13 cs aclk - 1 sck - 2 -3 si - 4 so - 5 rin1a - 6 rin1b - 7 rin2a - 8 rin2b - 9 rin3a - 10 rin3b - 11 gnd-12 cs 24 - vdd 23 - flag 22 - rin8b 21 - rin8a 20 - rin7b 19 - rin7a 18 - rin6b 17 - rin6a 16 - rin5b 15 - rin5a 14 - rin4b 13 - rin4a hi-3599 psi & hi-3599 pst hi-3598, hi-3599 holt integrated circuits www.holtic.com
block diagrams vdd spi interface control register status register arinc 429 received data fifo (4 words) label filter arinc 429 valid word checker arinc 429 line receiver 16 label filter memory rin1a rin1b sck cs si so aclk gnd 40 kohm 40 kohm channel 1 ch 8 ch 7 ch 6 ch 4 ch 3 ch 2 rin1a-40 rin1b-40 ch 5 arinc 429 bus 1 flag1 flag2 flag3 flag4 flag5 flag6 flag8 flag { hi-3598 (52-pin version) bus 6 bus 5 bus 4 bus 2 mr test register flag7 bus 7 bus 3 bus 8 tx1, tx0 vdd spi interface status register arinc 429 received data fifo (4 words) label filter arinc 429 valid word checker arinc 429 line receiver 16 label filter memory rin1a rin1b sck cs si so aclk gnd 40 kohm 40 kohm channel 1 ch 8 ch 7 ch 6 ch 4 ch 3 ch 2 ch 5 arinc 429 bus 1 flag { hi-3599 (24-pin version) bus 8 bus 6 bus 4 bus 2 control register test register bus 7 bus 3 bus 5 hi-3598, hi-3599 the 40 kohm resistors are shorted on the hi-3599-40 holt integrated circuits 2
example: one spi instruction op code 14 hex data field 0232 hex msb lsb msb lsb cs sck si ie: load channel 1 control register with 0232 hex hi-3598, hi-3599 instructions instruction op codes are used to read, write and configure the hi-3598 & hi-3599. when goes low, the next 8 clocks at the sck pin shift an instruction op code into the decoder, starting with the first rising edge. the op code is fed into the si pin, most significant bit first. for write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising sck edge. data word length varies depending on word type written: 16-bit control register writes, 32- bit self-test register writes or 128-bit writes to a channel?s label- matching enable/disable memory. cs for read instructions, the most significant bit of the requested data word appears at the so pin after the last op code bit is clocked into the decoder, at the next falling sck edge. as in write instructions, the data field bit-length varies with read instruction type. channel-specific instructions use the upper four bits to specify an arinc 429 receiver channel, 1-8 hex . the lower four bits specify the op code, described in table 1. the four channel assignment bits are ?don?t care? for instructions that are not channel-specific, such as master reset. table 1. defined instructions pin descriptions spi instruction format 76543210 msb lsb arinc 429 channel op code description instruction not implemented. no operation. load label values to label memory. the data field consists of 16, 8-bit labels. if fewer than 16 labels are needed for the application, the memory must be padded with redundant (duplicate) label values. read the contents of the label memory for this channel read an arinc word from the receive fifo for this channel. if the fifo is empty all zeros will be read load the specified channel?s control register and clear that channel?s fifo read read the status register. the specified channel?s control register master reset (all channels) load the self test register and send the test word to all receivers (high-speed data rate) load the self test register and send the test word to all receivers (low-speed data rate) instruction not implemented. no operation. data field none 128 bits 128 bits 32 bits 16 bits 16 bits 16 bits none 32 bits 32 bits none op code hex 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah-fh arinc channel x 1h-8h x x x x x 1h-8h 1h-8h 1h-8h 1h-8h signal function description 3598 3599 vdd power 3.3v or 5.0v power supply x x gnd power chip 0v supply x x input chip select. data is shifted into si and out of so when is low x x sck input spi clock. data is shifted into or out of the spi interface using sck x x si input spi interface serial data input x x so output spi interface serial data output x x aclk input master 1 mhz timing reference for the arinc 429 receiver and transmitter x x rina1 - rina8 arinc input arinc receiver positive input. direct connection to arinc 429 bus x std rinb1 - rinb8 arinc input arinc receiver negative input. direct connection to arinc 429 bus x std rina1-40 - rina8-40 arinc input alternate arinc receiver positive input. requires external 40k ohm resistor x -40 rinb1-40 - rinb8-40 arinc input alternate arinc receiver negative input. requires external 40k ohm resistor x -40 flag1 - flag8 output goes high when arinc 429 receiver fifo is not empty (cr1=0), or full (cr1=1) x flag output logical or of flag1 through flag8 x x tx1 output arinc 429 test word one state serial output pin x tx0 output arinc 429 test word zero state serial output pin x mr input hardware active high master reset. clears all receivers and fifos. x does not affect control register contents. cs cs holt integrated circuits 3
functional description control word register each hi-3598 and hi-3599 receive channel is assigned a 16-bit control register which configures that receiver. control register bits cr15 - cr0 are loaded from a 16-bit data value appended to spi instruction n4 hex, where ?n? is the channel number 1-8 hex. writing to the control register also clears the data fifo for that channel. the control register contents may be read using spi instruction n5 hex. the control register bits have the following functions: status register the hi-3598 and hi-3599 have a single 16-bit status register which is read to determine status for the eight received data fifos. the status register is read using spi instruction n6 hex. the following table defines the status register bits: hi-3598, hi-3599 cr bit function state description cr0 receiver 0 data rate = aclk/10 1 data rate = aclk/80 (arinc 429 high-speed) (lsb) data rate select (arinc 429 low-speed) cr1 rflag 0 flag goes high when receive fifo is not empty definition (contains at least one word) 1 flag goes high when receive fifo is full cr2 enable label 0 label recognition disabled recognition 1 label recognition enabled cr3 reset 0 normal operation receiver 1 reset this receiver (clear receiver logic and fifo) the receive channel is disabled if cr3 is left high cr4 receiver 0 receiver parity check disabled parity check enable 1 receiver odd parity check enabled cr5 self test 0 receiver?s inputs are connected to the self test register serial data output 1 normal operation cr6 receiver 0 receiver decoder disabled decoder 1 arinc bits 10 and 9 must match cr7 and cr8 cr7 - - if receiver decoder is enabled, the arinc bit 10 must match this bit cr8 - - if receiver decoder is enabled, the arinc bit 9 must match this bit cr9 arinc label 0 label bit order reversed (see table 2) bit order 1 label bit order same as received (see table 2) cr10 not used x control register read returns ?0? for this bit cr11 not used x control register read returns ?0? for this bit cr12 not used x control register read returns ?0? for this bit cr13 not used x control register read returns ?0? for this bit cr14 not used x control register read returns ?0? for this bit cr15 not used x control register read returns ?0? for this bit (msb) sr bit function state description sr0 receiver 1 0 receiver 1 fifo contains valid data. (lsb) fifo empty resets to zero when all data has been read. flag pin reflects the state of this bit when cr1=?0? 1 receiver 1 fifo is empty sr1 receiver 2 0 receiver 2 fifo contains valid data fifo empty 1 receiver 2 fifo is empty sr2 receiver 3 0 receiver 3 fifo contains valid data fifo empty 1 receiver 3 fifo is empty sr3 receiver 4 0 receiver 4 fifo contains valid data fifo empty 1 receiver 4 fifo is empty sr4 receiver 5 0 receiver 5 fifo contains valid data fifo empty 1 receiver 5 fifo is empty sr5 receiver 6 0 receiver 6 fifo contains valid data fifo empty 1 receiver 6 fifo is empty sr6 receiver 7 0 receiver 7 fifo contains valid data fifo empty 1 receiver 7 fifo is empty sr7 receiver 8 0 receiver 8 fifo contains valid data fifo empty 1 receiver 8 fifo is empty sr8 receiver 1 fifo 0 receiver 1 fifo not full. flag pin full reflects the state of this bit when cr1=?1? 1 receiver 1 fifo full. to avoid data loss, the fifo must be read within one arinc word period sr9 receiver 2 fifo 0 receiver 2 fifo not full. full 1 receiver 2 fifo full. sr10 receiver 3 fifo 0 receiver 3 fifo not full. full 1 receiver 3 fifo full. sr11 receiver 4 fifo 0 receiver 4 fifo not full. full 1 receiver 4 fifo full. sr12 receiver 5 fifo 0 receiver 5 fifo not full. full 1 receiver 5 fifo full. sr13 receiver 6 fifo 0 receiver 6 fifo not full. full 1 receiver 6 fifo full. sr14 receiver 7 fifo 0 receiver 7 fifo not full. full 1 receiver 7 fifo full. sr15 receiver 8 fifo 0 receiver 8 fifo not full. (msb) full 1 receiver 8 fifo full. holt integrated circuits 4
functional description (cont.) arinc 429 receiver arinc bus interface figure 1 shows the input circuit for each on-chip arinc 429 line receiver. the arinc 429 specification requires the following detection levels: one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts state differential voltage hi-3598, hi-3599 differential amplifiers comparators figure 1. arinc receiver input rina-40 rina rinb rinb-40 vdd gnd vdd gnd one null zero the hi-3598 and hi-3599 guarantee recognition of these levels with a common mode voltage with respect to gnd less than 30v for the worst case condition (3.15v supply and 13v signal level). the tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. 1. an accurate 1mhz clock source is required to validate the receive signal timing. less than 0.1% error is recommended. 2. the receiver uses three separate 10-bit sampling shift reg- isters for ones detection, zeros detection and null detection. when the input signal is within the differential voltage range for any shift register?s state (one zero or null) sampling clocks a high bit into that register. when the receive signal is outside the differential voltage range defined for any shift reg- ister, a low bit is clocked. only one shift register can clock a high bit for any given sample. all three registers clock low bits if the differential input voltage is between defined state volt- age bands. valid data bits require at least three consecutive one or zero samples (three high bits) in the upper half of the ones or ze- ros sampling shift register, and at least three consecutive null samples (three high bits) in the lower half of the null sampling shift register within the data bit interval. a word gap null requires at least three consecutive null sam- ples (three high bits) in the upper half of the null sampling shift register and at least three consecutive null samples (three high bits) in the lower half of the null sampling shift reg- ister. this guarantees the minimum pulse width. receiver logic operation bit timing bit rate pulse rise time pulse fall time pulse width figure 2 is a block diagram showing the logic for each receiver. the arinc 429 specification defines the following timing toler- ances for received data: 100k bps 1% 12k -14.5k bps 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 to 41.7 sec the hi-3598 and hi-3599 accept signals within these tolerances and rejects signals outside these tolerances. receiver logic achieves this as described below: high speed low speed 3. to validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. with exactly 1mhz input clock frequency, the acceptable data bit rates are: 83k bps 10.4k bps 125k bps 15.6k bps 4. following the last data bit of a valid reception, the word gap timer samples the null shift register every 10 input clocks (every 80 clocks for low speed). if a null is present, the word gap counter is incremented. a word gap count of 3 enables the next reception. high speed low speed data bit rate min data bit rate max parity sdi label label (lsb) label (msb) label label label label label sdi parity sdi label label (msb) label (lsb) label label label label label sdi arinc 429 data format control register bit cr9 controls how individual bits in the received arinc word are mapped to the hi-3598 and hi-3599 spi data word bits during data read or write operations. the following table describes this mapping: table 2. spi / arinc bit-mapping spi 1 2-22 23242526272829303132 order . arinc bit 32 31 - 11 10 912345678 cr11=0 data arinc bit 32 31 - 11 10 987654321 cr11=1 data holt integrated circuits 5
0 x 0 x load fifo 1 no 0 x ignore data 1 yes 0 x load fifo 0 x 1 no ignore data 0 x 1 yes load fifo 1 yes 1 no ignore data 1 no 1 yes ignore data 1 no 1 no ignore data 1 yes 1 yes load fifo cr2 arinc word cr6 arinc word fifo matches bits 10, 9 enabled match cr7, 8 label functional description (cont.) receiver parity if enabled by setting control register cr4 bit to ?1?, the receiver parity circuit counts ones received, including the parity bit. if the result is odd, then a "0" appears in the 32nd bit. setting control register cr4 bit to ?0? disables parity checking and all 32 bits are treated as data. once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). depending on the state of control register bits cr2, cr6, cr7 and cr8, the received 32-bit arinc word is then checked for correct decoding and label match before it is loaded into the 4 x 32 receive fifo. arinc words that do not match required 9th and 10th arinc bit and do not have a label match are ignored and are not loaded into the receive fifo. the adjacent table describes this operation. retrieving data hi-3598, hi-3599 fifo load control control bits cr2, cr6-8 / spi interface 32 bit shift register aclk bit counter and end of sequence parity check 32nd bit data bit clock word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos figure 2. receiver block diagram label / decode compare 16-label memory 4 words x 32 bit fifo flag sck cs si so table 3. fifo loading control holt integrated circuits 6
functional description (cont.) once a valid arinc word is loaded into the fifo, the eos signal clocks the data ready flip-flop to a "1", and the corresponding channel?s status register fifo empty bit (sr0- sr7) goes to a ?0?. the channel?s empty bit remains low until the corresponding receive fifo is empty. each received arinc word is retrieved via the spi interface using spi instruction n3 hex where ?n? is the channel number 1-8 hex. up to 4 arinc words may be held in each channel?s receive fifo. the status register fifo full bit (sr8 - sr15) goes high when the corresponding channel?s receive fifo is full. failure to offload a full receive fifo causes additional received valid arinc words to overwrite the last received word. label recognition self test the user loads the 16 byte label look-up table to specify which 8- bit incoming arinc labels are captured by the receiver, and which are discarded. if fewer than 16 labels are required, spare label memory locations must be filled with duplicate copies of any valid label. after the look-up table is initialized, set channel control register bit cr2 to enable label recognition for that channel. the hi-3598 and hi-3599 contain an on-chip arinc 429 format self-test register which may be used to execute user-defined self- test sequences for each receiver. a 32-bit test word is loaded to the test register using spi instructions n8 hex (for arinc 429 high-speed data rate) or n9 hex (for arinc 429 low speed). upon completion of the instruction, the word is shifted out of the register and routed to all receivers. the serial test word may be observed at the hi-3598?s tx1 and tx0 pins, as shown in table 4. each channel will respond to the test word if self-test mode is enabled for that channel (control register cr5 bit equals ?0?) and the receive channel is set to the correct speed. if a channel?s cr5 bit equals ?1? the channel ignores the self-test word and continues to respond to the external arinc 429 bus. the first bit shifted into the self test register will be the first bit sent to the receivers and the tx1 and tx0 pins. in arinc 429 protocol, this bit is the lsb. therefore the self test word is unique in that it is loaded lsb first with respect to the arinc word. if label recognition is enabled, the receiver compares the label in each new arinc word against the channel?s stored label look-up table. if a label match is found, the received word is processed. if no match occurs, the new arinc word is discarded and no indicators of received arinc data are presented. note that 00 hex is treated in the same way as any other label value. label memory bit significance is not changed by the status of control register bit cr9. the most significant label bit is always compared to the first (msb) bit of each spi 8-bit data field from spi instruction n1 hex, where ?n? is the channel number 1-8 hex. if a channel control register cr2 bit equals ?0,? the corresponding receiver recognizes all label values as valid, as shown in table 3. the contents of each channel?s label memory may be read via the spi interface using instruction n2 hex where ?n? equals the channel number 1-8 hex, as described in table 1. reading the label memory hi-3598, hi-3599 tx1 tx0 arinc 429 state 0 0 null 1 0 one 0 1 zero table 4. test outputs transmit function line receiver input pins the self test register can be used as a transmitter by connecting the tx1 and tx0 pins to an external arinc 429 line driver (such as the hi-8570 or hi-8571). please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. the hi-3598 has two sets of line receiver input pins, rina/b and rina/b-40. only one pair may be used to connect to the arinc 429 bus. the rina/b pins may be connected directly to the arinc 429 bus. the rina/b-40 pins require an external 40kohm resistor to be added in series with each arinc input without affecting the arinc input thresholds. this option is espe- cially useful in applications where lightning protection circuitry is also required. when using the rina/b-40 pins, each side of the arinc bus must be connected through a 40k ohm series resistor in order for the chip to detect the correct arinc levels. the typical 10 volt differential signal is translated and input to a window com- parator and latch. the comparator levels are set so that with the external 40k ohm resistors, they are just below the standard 6.5 volt minimum arinc data threshold and just above the standard 2.5 volt maximum arinc null threshold. when using the reduced pin-count hi-3599 option of this prod- uct, only one set of arinc 429 receive inputs are provided for each channel. the standard hi-3599 device uses the direct- connection rina / rinb pins. the hi-3599-40 device uses the rina-40 / rinb-40 pins and requires external 40k ohm series resistors. see the ordering information table for complete part number options. master reset (mr) assertion of master reset (mr) causes immediate termination of data reception. the eight receive fifos are cleared. status register fifo flags and fifo status output signals are also cleared. master reset does not affect the eight channel control registers. master reset may be asserted using the mr input pin (hi-3598 only) or by executing spi instruction n7 hex. an individual receive channel can be reset by setting its corresponding control register cr3 bit to ?1?. this clears the channel?s receiver logic and receive fifo and disables the receiver until cr3 is reset to ?0?. for applications requiring less than eight channels, unused receivers should be held in reset by setting the corresponding control register cr3 bits. holt integrated circuits 7
hi-3598, hi-3599 timing diagrams receiver operation flag arinc data cs bit 31 bit 32 rflg t spif t rxr t serial input timing diagram cs sck si chh t ceh t msb ces t ds tt dh lsb cph t sckr t sckf t sck arinc word so si spi instruction n3 hex serial output timing diagram cs sck so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance holt integrated circuits 8
logic outputs operating voltage range operating supply current output voltage: logic "1" output voltage v i = -100 a v logic "0" output voltage v i = 1.0ma v output current: output sink i v = 0.4v 1.6 ma (all outputs & bi-directional pins) output source i v = v - 0.4v -1.0 ma output capacitance: c 15 pf v 3.15 5.25 v vdd i 2.5 7 ma oh oh ol ol ol out oh out dd o dd 90%vdd 10% vdd dd limits parameter conditions unit symbol differential input voltage: one v common mode voltages 6.5 10.0 13.0 v (rin1a to rin1b, rin2a to rin2b, etc.) zero v less than 30v with -13.0 -10.0 -6.5 v null v respect to gnd -2.5 0 2.5 v input resistance: differential r - 140 - k to gnd r - 140 - k to v r - 100 - k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf (guaranteed but not tested) to gnd c 20 pf to v c 20 pf input voltage: input voltage hi v v input voltage lo v v input current: input sink i 1.5 a input source i -1.5 a min typ max arinc inputs - pins rina, rinb, rina-40 (with external 40kohms), rinb-40 (with external 40kohms) logic inputs ih il nul i g dd h ih il i g dd h ih il ih il (rina to rinb) pull-down current (mr, si, sck, aclk pins) i 250 600 a pull-up current ( pin) i -600 -250 a 70% vdd 30% vdd pd pu cs hi-3598, hi-3599 absolute maximum ratings supply voltages v ......................................... -0.3v to +7.0v voltage at pins rin1a, rin1b, rin2a, rin2b ..... -29v to +29v voltage at any other pin ............................... -0.3v to v +0.3v solder temperature (leads) .................... 280 for 10 seconds (package) .......................................... 220 dd dd c c power dissipation at 25c plastic quad flat pack ..................1.5 w, derate 10mw/ c dc current drain per pin .............................................. 10ma operating temperature range (industrial): .... -40c to +85c (extended temp.): .....-55c to +125c storage temperature range ........................ -65c to +150c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics v = 3.3v or 5.0v, gnd = 0v, ta = operating temperature range (unless otherwise specified). dd holt integrated circuits 9
ac electrical characteristics vdd = 3.3v or 5.0v, gnd = 0v, ta = operating temperature range and fclk=1mhz 0.1% with 60/40 duty cycle + hi-3598, hi-3599 limits parameter symbol units min typ max spi interface timing receiver timing sck clock period active after last sck rising edge t 25 ns setup time to first sck rising edge t 10 ns hold time after last sck falling edge t 10 ns inactive between spi instructions t delay - last bit of received arinc word to flag(full or empty) - hi speed t 16 s received data available to spi interface. flag to active spi receiver read t t 130 ns 30 ns spi si data set-up time to sck rising edge t 10 ns spi si data hold time after sck rising edge t 30 ns sck rise time t 10 ns sck fall ime t 10 ns sck high time t 45 ns sck low time t 25 ns so valid after sck falling edge t 65 ns so high-impedance after sck falling edge t 65 ns delay - last bit of received arinc word to flag(full or empty) - lo speed t 126 s t0 ns 85 ns cyc cph ds dh sckr sckf sckh sckl dv chz rflg rxr cs cs cs cs cs chh ces ceh rflg spif the hi-3598pci, hi-3598pct, hi-3599pci and hi3599pct use 44-pin or 64-pin plastic chip-scale packages. these packages have a metal heat sink pad on the bottom surface that is electrically connected to the die. for these receivers, small size is the primary advantage of this package style. heat sinking provides little benefit because power dissipation is low. if connected, the bottom heat sink pad should be connected to vdd. do not connect heat sink pad to gnd. heat sink - chip-scale package only holt integrated circuits 10
hi-3598, hi-3599 additional pin / package configurations 64 - pin plastic 9mm x 9mm chip-scale package (qfn) 44 - pin plastic 7mm x 7mm chip-scale package (qfn) 44 - pin plastic 7mm x 7mm chip-scale package (qfn) hi-3599 psi-40 & hi-3599 pst-40 aclk - 1 sck - 2 -3 si - 4 so - 5 rin1a-40 - 6 rin1b - 7 rin2a - 8 rin2b - 9 rin3a - 10 rin3b - 11 gnd-12 cs -40 -40 -40 -40 -40 24 - vdd 23 - flag 22 - rin8b 21 - rin8a 20 - rin7b 19 - rin7a 18 - rin6b 17 - rin6a 16 - rin5b 15 - rin5a 14 - rin4b 13 - rin4a -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 hi-3599pci hi-3599pct 44 - 43 - 42 - sck 41 - aclk 40 - 39 - vdd 38 - flag 37 - 36 - rin8b-40 35 - rin8a-40 34 - cs 33 - 32 - 31 - 30 - rin7b-40 29 - rin7a-40 28 - rin6b-40 27 - rin6a-40 26 - rin5b-40 25 - rin5a-40 24 - 23 - -12 -13 rin2a-40 - 14 rin2b-40 - 15 rin3a-40 - 16 rin3b-40 - 17 gnd - 18 rin4a-40 - 19 rin4b-40 - 20 -21 -22 -1 -2 -3 si - 4 so - 5 -6 -7 rin1a-40 - 8 rin1b-40 - 9 -10 -11 HI-3599PCI-40 hi-3599pct-40 64 - 63 - flag1 62 - flag2 61 - flag3 60 - flag4 59 - flag5 58 - flag6 57 - flag7 56 - flag8 55 - 54 - vdd 53 - 52 - flag 51 - rin8b 50 - rin8b-40 49 - hi-3598pci hi-3598pct 48 - rin8a-40 47 - rin8a 46 - rin7b 45 - rin7b-40 44 - rin7a-40 43 - rin7a 42 - 41 - rin6b 40 - rin6b-40 39 - 38 - rin6a-40 37 - rin6a 36 - rin5b 35 - rin5b-40 34 - rin5a-40 33 - rin5a -17 -18 rin2a -19 rin2a-40 - 20 rin2b-40 - 21 rin2b - 22 rin3a -23 rin3a-40 - 24 rin3b-40 - 25 rin3b - 26 gnd - 27 rin4a -28 rin4a-40 - 29 rin4b-40 - 30 rin4b - 31 -32 -1 -2 aclk - 3 sck - 4 -5 si - 6 so - 7 mr - 8 tx1 - 9 tx0 - 10 rin1a - 11 rin1a-40 - 12 rin1b-40 - 13 rin1b - 14 -15 -16 cs hi-3598pcx hi-3599pcx hi-3599pcx-40 hi-3599psx-40 24 - pin plastic small outilne package (soic) 44 - 43 - 42 - sck 41 - aclk 40 - 39 - vdd 38 - flag 37 - 36 - rin8b 35 - rin8a 34 - cs 33 - 32 - 31 - 30 - rin7b 29 - rin7a 28 - rin6b 27 - rin6a 26 - rin5b 25 - rin5a 24 - 23 - -12 -13 rin2a -14 rin2b - 15 rin3a -16 rin3b - 17 gnd - 18 rin4a -19 rin4b - 20 -21 -22 -1 -2 -3 si - 4 so - 5 -6 -7 rin1a - 8 rin1b - 9 -10 -11 holt integrated circuits 11
hi-3598, hi-3599 ordering information (hi-3598 all pins) hi - 3598 xx x x temperature range burn in -40c to +85c no -55c to +125c no t part number t i package description 64 pin plastic chip-scale pkg, qfn (64pcs) part number pc 52 pin plastic quad flat pack, pqfp (52ptqs) pq flow lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank i ordering information (hi-3599 minimum pin-count version) hi - 3599 - xxxx xx package description 44 pin plastic chip-scale pkg, qfn (44pcs) part number pc 24 pin plastic wide soic (24hw) ps lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank temperature range burn in -40c to +85c no -55c to +125c no t part number t i flow i input resistance part number 100 kohm.requires external 40 kohm resistors -40 140 kohm. direct connection to arinc 429 bus blank holt integrated circuits 12
hi-3598, hi-3599 revision history revision date description of change ds3598, rev. new 06/12/08 initial release rev. a 05/22/09 clarified relationship between spi bit order and arinc 429 bit order holt integrated circuits 13
hi-3598 package dimensions 52-pin plastic quad flat pack (pqfp) inches (millimeters) package type: 52ptqs d etail a see detail a 0 7 .520 (13.2) bsc sq .394 (10.0) bsc sq .063 (1.6) typ .008 (.20) min .005 (.13) r min r min .005 (.13) .0256 (.65) bsc .015 .003 (.375 .075) .035 .006 (.88 .15) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .055 .002 (1.4 .05) .063 (1.6) max. bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .354 (9.00) bsc .039 (1.00) max .008 (0.20) typ .0197 (0.50) bsc .010 (0.25) typ .016 .004 (0.40 ) .10 .281 .006 (7.15 ) .15 .281 .006 (7.15 ) .15 bottom view top view .354 (9.00) bsc package type: 64pcs inches (millimeters) 64-pin plastic chip-scale package (qfn) heat sink pad on bottom of package. heat sink must be left floating or connected to vdd. do not connect to gnd. holt integrated circuits 14
hi-3599 package dimensions 24-pin plastic small outline (soic) - wb (wide body) 24-pin plastic small outline (soic) - wb (wide body) inches (millimeters) package type: 24hw bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .407 .013 (10.325 .32) .294 .002 (7.468 .051) 0 to 8 .0075 .0035 (.191 .089) .606 .004 (15.392 .102) .033 .017 (.838 .43) .095 .005 (2.413 .127) .0105 .0015 (.2667 .038) see detail a detail a .050 (1.27) bsc .0165 .0035 (.419 .089) 44-pin plastic chip-scale package (qfn) inches (millimeters) package type: 44pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .203 .006 (5.15 .15) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .203 .006 (5.15 .15) typ typ bottom view top view bsc .276 (7.00) bsc max heat sink pad on bottom of package. heat sink must be left floating or connected to vdd. do not connect to gnd. holt integrated circuits 15

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