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3 mhz, 600 ma, low quiescent current buck with 300 ma ldo regulator adp2140 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features input voltage range: 2.3 v to 5.5 v ldo input (vin2) 1.65 v to 5.5 v buck output voltage range: 1.0 v to 3.3 v ldo output voltage range: 0.8 v to 3.3 v buck output current: 600 ma ldo output current: 300 ma ldo quiescent current: 22 a with zero load buck quiescent current: 20 a in psm mode low shutdown current: <0.3 a low ldo dropout 110 mv @ 300 ma load high ldo psrr 65 db @ 10 khz at v out2 = 1.2 v 55 db @ 100 khz at v out2 = 1.2 v low noise ldo: 40 v rms at v out2 = 1.2 v initial accuracy: 1% current-limit and thermal overload protection power-good indicator optional enable sequencing 10-lead 0.75 mm 3 mm 3 mm lfcsp package applications mobile phones personal media players digital camera and audio devices portable and battery-powered equipment general description t he adp2140 includes a high efficiency, low quiescent 600 ma stepdown dc-to-dc converter and a 300 ma ldo packaged in a small 10-lead 3 mm 3 mm lfcsp. the total solution requires only four tiny external components. the buck regulator uses a proprietary high speed current-mode, constant frequency, pulse-width modulation (pwm) control scheme for excellent stability and transient response. to ensure the longest battery life in portable applications, the adp2140 has a power saving variable frequency mode to reduce switching fre- quency under light loads. the ldo is a low quiescent current, low dropout linear regulator designed to operate in a split supply mode with v in2 as low as 1.65 v. the low input voltage minimum allows the ldo to be powered from the output of the buck regulator increasing effi- ciency and reducing power dissipation. the adp2140 runs from input voltages of 2.3 v to 5.5 v allowing single li+/li? polymer typical application circuits vin1 pgnd pg sw en1 agnd en2 pg en1 en2 fb vout2 10 9 8 7 6 vin2 1 2 3 4 5 adp2140 100k ? + c in 10f + c out2 1f + c out 10f v in1 = 3.6 v v out2 = 1.8v 1h v out = 1.2v 07932-001 figure 1. adp2140 with ldo connected to v in1 vin1 pgnd pg sw en1 agnd en2 pg en1 en2 fb vout2 10 9 8 7 6 vin2 1 2 3 4 5 adp2140 100k ? + c in 10f + c out2 1f + c out 10f v in1 = 3.3 v v out2 = 1.2v 1h v out = 1.8v 07932-002 figure 2. adp2140 with ldo connected to buck output cell, multiple alkaline/nimh cell, pcmcia, and other standard power sources. adp2140 includes a power-good pin, soft start, and internal compensation. numerous power sequencing options are user- selectable through two enable inputs. in autosequencing mode, the highest voltage output enables on the rising edge of en1. during logic controlled shutdown, the input disconnects from the output and draws less than 300 na from the input source. other key features include: undervoltage lockout to prevent deep battery discharge, soft start to prevent input current overshoot at startup, and both short-circuit protection and thermal overload protection circuits to prevent damage in adverse conditions. when the adp2140 is used with two 0603 capacitors, one 0402 capacitor, one 0402 resistor, and one 0805 chip inductor, the total solution size is approximately 90 mm 2 resulting in the smallest foot- print solution to meet a variety of portable applications.
adp2140 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuits ............................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 recommended specifications: capacitors and inductor ........ 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 buck output .................................................................................. 7 ldo output ................................................................................ 14 theory of operation ...................................................................... 19 buck section ................................................................................ 19 control scheme .......................................................................... 19 pwm operation ......................................................................... 19 psm operation ........................................................................... 19 pulse skipping threshold .......................................................... 19 selected features ............................................................................. 20 short-circuit protection ............................................................ 20 undervoltage lockout ............................................................... 20 thermal protection .................................................................... 20 soft start ...................................................................................... 20 current limit .............................................................................. 20 power-good pin ......................................................................... 20 ldo section ............................................................................... 20 applications information .............................................................. 21 power sequencing ...................................................................... 21 power-good function ............................................................... 24 external component selection ................................................ 24 selecting the inductor ................................................................ 24 output capacitor ........................................................................ 24 input capacitor ........................................................................... 24 efficiency ..................................................................................... 25 recommended buck external components .......................... 25 ldo capacitor selection .......................................................... 26 ldo as a postregulator to reduce buck output noise ........ 26 thermal considerations ................................................................ 28 pcb layout considerations ...................................................... 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 6/10revision 0: initial version
adp2140 rev. 0 | page 3 of 32 specifications v in1 = 3.6 v, v in2 = v out2 + 0.3 v or 1.65 v, whichever is greater; 5 v en1 = en2 = v in1 ; i out = 200 ma, i out2 = 10 ma, c in = 10 f, c out = 10 f, c out2 = 1 f, l out = 1 h; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit buck section input voltage range v in1 2.3 5.5 v buck output accuracy v out i out = 10 ma ?1.5 +1.5 % v in1 = 2.3 v or (v out + 0.5 v) to 5.5 v, i out = 1 ma to 600 ma ?2.5 +2.5 % transient load regulation v tr-load v out = 1.8 v load = 50 ma to 250 ma, rise/fall time = 200 ns 75 mv load = 200 ma to 600 ma, rise/fall time = 200 ns 75 mv transient line regulation v tr-line line transient = 4 v to 5 v, 4 s rise time v out = 1.0 v 40 mv v out = 1.8 v 25 mv v out = 3.3 v 25 mv pwm to psm threshold v in1 = 2.3 v or (v out + 0.5 v) to 5.5 v 100 ma output current i out 600 ma current limit i lim v in1 = 2.3 v or (v out + 0.5 v) to 5.5 v 1100 1300 ma switch on resistance pfet r pfet v in1 = 2.3 v to 5.5 v 250 m nfet r nfet v in1 = 2.3 v to 5.5 v 250 m switch leakage current i leak-sw en1 = gnd, vin1 = 5.5 v, and sw = 0 v ?1 a quiescent current i q no load, device not switching 20 30 a minimum on time on-time min 70 ns oscillator frequency freq 2.55 3.0 3.15 mhz frequency foldback threshold v fold output voltage where f sw 50% of nominal frequency 50 % start-up time 1 t start-up v out = 1.8 v, 600 ma load 70 s soft start time 2 ss time v out = 1.8 v, 600 ma load 150 s ldo section input voltage range v in2 1.65 5.5 v ldo output accuracy v out2 i out2 = 10 ma, t j = 25c ?1 +1 % 1 ma < i out2 < 300 ma, v in2 = (v out2 + 0.3 v) to 5.5 v, t j = 25c ?1.5 +1.5 % 1 ma < i out2 < 300 ma, v in2 = (v out2 + 0.3 v) to 5.5 v ?3 +3 % line regulation ?v out2 /?v in2 v in2 = (v out2 + 0.3 v) to 5.5 v, i out2 = 10 ma ?0.05 +0.05 %/v load regulation 3 ?v out2 /?i out2 i out2 = 1 ma to 300 ma 0.001 0.005 %/ma dropout voltage 4 v dropout i out2 = 10 ma, v out2 = 1.8 v 4 7 mv i out2 = 300 ma, v out2 = 1.8 v 110 200 mv ground current i agnd no load, buck disabled 22 35 a i out2 = 10 ma 65 90 a i out2 = 300 ma 150 220 a power supply rejection ratio psrr v in2 = v out2 + 1 v, v in1 = 5 v, i out2 = 10 ma psrr on v in2 10 khz, v out2 = 1.2 v, 1.8 v, 3.3 v 65 db 100 khz, v out2 = 3.3 v 53 db 100 khz, v out2 = 1.8 v 54 db 100 khz, v out2 = 1.2 v 55 db
adp2140 rev. 0 | page 4 of 32 parameter symbol test conditions/comments min typ max unit output noise out noise v in2 = v in1 = 5 v, i out2 = 10 ma 10 hz to 100 khz, v out2 = 0.8 v 29 v rms 10 hz to 100 khz, v out2 = 1.2 v 40 v rms 10 hz to 100 khz, v out2 = 1.8 v 50 v rms 10 hz to 100 khz, v out2 = 2.5 v 66 v rms 10 hz to 100 khz, v out2 = 3.3 v 88 v rms current limit i lim t j = 25c 360 500 760 ma input leakage current i leak-ldo en2 = gnd, v in2 = 5.5 v and v out2 = 0 v 1 a start-up time 1 t start-up v out2 = 3.3 v, 300 ma load 70 s soft start time 2 ss time v out2 = 3.3 v, 300 ma load 130 s additional functions undervoltage lockout uvlo input voltage rising uvlo rise 2.23 2.3 v input voltage falling uvlo fall 2.05 2.16 v en input en1, en2 input logic high v ih 2.3 v v in1 5.5 v 1.0 v en1, en2 input logic low v il 2.3 v v in1 5.5 v 0.27 v en1, en2 input leakage i en-lkg en1, en2 = v in1 or gnd 0.05 a en1, en2 = v in1 or gnd 1 a shutdown current i shut v in1 = 5.5 v, en1, en2 = gnd, t j = ?40c to +85c 0.3 1.2 a thermal shutdown threshold ts sd t j rising 150 c hysteresis ts sd-hys 20 c power good rising threshold pg rise 92 %v out falling threshold pg fall 86 %v out power-good hysteresis pg hys 6 %v out output low v ol i sink = 4 ma 0.2 v leakage current i oh power-good pin pull-up voltage = 5.5 v 1 a buck to ldo delay t delay pwm mode only 5 ms power-good delay t reset pwm mode only 5 ms 1 start-up time is defined as the time between the rising edge of enx to v outx being at 10% of the v outx nominal value. 2 soft start time is defined as the time between v outx being at 10% to v outx being at 90% of the v outx nominal value. 3 based on an en dpoint calculation using 1 ma and 300 ma loads. 4 dropout voltage is defined as the input-to-output voltage differe ntial when the input voltage is set to the nominal output vol tage. this applies only for output voltages above 2.3 v. recommended specifications: capacitors and inductor table 2. parameter symbol test conditions/comments min typ max unit minimum input and output capacitance 1 t a = ?40c to +125c buck c min 7.5 10 f ldo c min 0.7 1.0 f capacitor esr t a = ?40c to +125c buck r esr 0.001 0.01 ldo r esr 0.001 1 minimum inductor ind min 0.7 1 h 1 the minimum input and output capacitance should be greater than 0.70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during devi ce selection to ensure that the minimum capa citance specification is met. x7r- and x5 r-type capacitors are recommended, y5v and z5u capacitors are not recommended for use with any ldo.
adp2140 rev. 0 | page 5 of 32 absolute maximum ratings table 3. parameter rating vin1, vin2 to pgnd, agnd ?0.3 v to +6.5 v vout2 to pgnd, agnd ?0.3 v to v in2 sw to pgnd, agnd ?0.3 v to v in1 fb to pgnd, agnd ?0.3 v to +6.5 v pg to pgnd, agnd ?0.3 v to +6.5 v en1, en2 to pgnd, agnd ?0.3 v to +6.5 v storage temperature range ?65c to +150c operating ambient temperature range ?40c to +85c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in com- bination. the adp2140 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and low printed circuit board (pcb) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in. 3 in. circuit board. refer to jesd 51-7 for detailed information on the board construction. for more information, see an-772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) . jb is the junction-to-board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a 4-layer board. the jesd51-12, guidelines for reporting and using package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path, as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real-world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) refer to jesd51-8 and jesd51-12 for more detailed information about jb . thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jb unit 10-lead 3 mm 3 mm lfcsp 35.3 16.9 c/w esd caution
adp2140 rev. 0 | page 6 of 32 pin configuration and fu nction descriptions vin1 pg en1 en2 vout2 10 9 8 7 6 pgnd sw agnd fb vin2 1 2 3 4 5 adp2140 top view (not to scale) notes 1. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to ground inside the package. it is recommended that the exposed pad be connected to the ground plane on the circuit board. 07932-003 figure 3. pin configuration table 5. pin function descriptions pin mnemonic description 1 pgnd power ground. 2 sw connection from power mosfets to inductor. 3 agnd analog ground. 4 fb feedback from buck output. 5 vin2 ldo input voltage. 6 vout2 ldo output voltage. 7 en2 logic 1 to enable ldo or no connect for autosequencing. 8 en1 logic 1 to enable buck or initiate sequencing. this is a dual function pin and th e state of en2 determines which function is operational. 9 pg power good. open-drain output. pg is held low unti l both output voltages (which includes the external inductor and capacitor sensed by the fb pin) rise a bove 92% of nominal value. pg is held high until both outputs fall below 85% of nominal value. 10 vin1 analog power input. ep exposed pad. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to ground inside the package. it is recommended that the exposed pad be connected to the ground plane on the circuit board.
adp2140 rev. 0 | page 7 of 32 typical performance characteristics buck output v in1 = 4 v, v out = 1.8 v, i out = 10 ma, c in = c out = 10 f, t a = 25c, unless otherwise noted. 30 0 5 10 15 20 25 2.3 2.8 3.3 3.8 4.3 4.8 5.3 quiescent current (a) input voltage (v) ?40c ?5c +25c +85c +125c 07932-004 figure 4. quiescent supply current vs. input voltage, different temperatures 3.1 2.5 2.6 2.7 2.8 2.9 3.0 2.3 2.8 3.3 3.8 4.3 4.8 5.3 frequency (mhz) input voltage (v) ?40c ?5c +25c +85c +125c 07932-005 figure 5. switching frequency vs. input voltage, different temperatures 3.10 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 ?60 ?40 ?20 0 20 40 60 80 100 120 140 frequency (mhz) temperature (c) 5.5v 4.6v 3.1v 2.3v 07932-006 figure 6. switching frequency vs. temperature, different input voltages 1.82 1.76 1.77 1.78 1.79 1.80 1.81 ?40 125 85 25 ?5 output voltage (v) junction temperature (c) load current = 1ma load current = 10ma load current = 50ma load current = 100ma load current = 300ma load current = 600ma 07932-007 figure 7. output volt age vs. temperature, v in1 = 2.3 v, different loads 1200 700 750 800 850 900 950 1000 1050 1100 1150 ?60 ?40 ?20 0 20 40 60 80 100 120 140 current limit (ma) junction temperature (c) 2.3v 3.0v 4.0v 5.0v 5.5v 07932-008 figure 8. current limit vs. temperature, different input voltages 140 0 20 40 60 80 100 120 3.50 5.50 5.25 5.00 4.75 4.50 4.25 4.00 3.75 current (ma) input voltage (v) ?40c ?5c +25c +85c +125c 07932-009 figure 9. psm to pwm mode transition vs. input voltage, different temperatures
adp2140 rev. 0 | page 8 of 32 v in1 = 4 v, v out = 1.8 v, i out = 10 ma, c in = c out = 10 f, t a = 25c, unless otherwise noted. 1.82 1.81 1.80 1.79 1.78 1.77 1.76 2.3 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 output voltage (v) input voltage (v) load current = 1ma load current = 10ma load current = 50ma load current = 100ma load current = 300ma load current = 600ma 07932-010 figure 10. line regulation, v out = 1.8 v, different loads 1.82 1.81 1.80 1.79 1.78 1.77 1.76 1 10 100 1000 output voltage (v) load current (ma) 07932-011 figure 11. load regulation, v out = 1.8 v, v in1 = 2.3 v 1.22 1.21 1.20 1.19 1.18 1.17 1 10 100 1000 output voltage (v) load current (ma) 07932-012 figure 12. load regulation, v out = 1.2 v, v in1 = 2.3 v 3.350 3.325 3.300 3.275 3.250 1 10 100 1000 output voltage (v) load current (ma) 07932-013 figure 13. load regulation, v out = 3.3 v 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 efficiency (%) load current (ma) 2.5v 3.0v 4.0v 5.0v 5.5v 07932-014 figure 14. efficiency vs. load current, v out = 1.8 v, different input voltages 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 efficiency (%) load current (ma) ?40c ?5c +25c +85c +125c 07932-015 figure 15. efficiency vs. load current, v out = 1.8 v, different temperatures
adp2140 rev. 0 | page 9 of 32 v in1 = 4 v, v out = 1.8 v, i out = 10 ma, c in = c out = 10 f, t a = 25c, unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 efficiency (%) load current (ma) 2.5v 3.0v 4.0v 5.0v 5.5v 07932-016 figure 16. efficiency vs. load current, v out = 1.2 v, different input voltages 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 efficiency (%) load current (ma) ?40c ?5c +25c +85c +125c 07932-017 figure 17. efficiency vs. load current, v out = 1.2 v, different temperatures ch1 1.00v ch2 50.0mv m20.0s a ch1 4.68v t 11.60% ch3 5.00v 1 2 3 t input voltage output voltage switch node 07932-020 figure 18. line transient, v out = 1.8 v, power save mode, 50 ma, v in1 = 4 v to 5 v, 4 s rise time 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 efficiency (%) load current (ma) ?40c ?5c +25c +85c +125c 07932-019 figure 19. efficiency vs. load current, v out = 3.3 v, different temperatures 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 efficiency (%) load current (ma) 4.0v 5.0v 5.5v 07932-018 figure 20. efficiency vs. load current, v out = 3.3 v, different input voltages ch1 1.00v ch2 20.0mv m20.0s a ch1 4.68v t 11.60% ch3 5.00v 1 2 3 t input voltage output voltage switch node 07932-021 figure 21. line transient, v out = 1.8 v, pwm mode, 600 ma, v in1 = 4 v to 5 v, 4 s rise time
adp2140 rev. 0 | page 10 of 32 v in1 = 4 v, v out = 1.8 v, i out = 10 ma, c in = c out = 10 f, t a = 25c, unless otherwise noted. ch1 1.00v ch2 50.0mv m20.0s a ch1 4.68v t 11.60% ch3 5.00v 1 2 3 t input voltage output voltage switch node 07932-022 figure 22. line transient, v out = 1.2 v, psm mode, 50 ma, v in1 = 4 v to 5 v, 4 s rise time ch1 1.00v ch2 20.0mv m20.0s a ch1 4.32v t 10.80% ch3 5.00v 1 2 3 t input voltage output voltage switch node 07932-023 figure 23. line transient, v out = 1.2 v, pwm mode, 600 ma, v in1 = 4 v to 5 v, 4 s rise time ch1 1.00v ch2 50.0mv m20.0s a ch1 4.68v t 11.60% ch3 5.00v 1 2 3 t input voltage output voltage switch node 07932-024 figure 24. line transient, v out = 3.3 v, psm mode, 50 ma, v in1 = 4 v to 5 v, 4 s rise time ch1 1.00v ch2 20.0mv m20.0s a ch1 4.68v t 11.60% ch3 5.00v 1 2 3 t input voltage output voltage switch node 07932-025 figure 25. line transient, v out = 3.3 v, pwm mode, 600 ma, v in1 = 4 v to 5 v, 4 s rise time ch1 200ma ch2 50.0mv m20.0s a ch1 288ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-026 figure 26. load transient, v out = 1.8 v, 200 ma to 600 ma, load current rise time = 200 ns ch1 100ma ch2 50.0mv m20.0s a ch1 136ma t 10.40% ch3 5.00v 1 2 3 t load output output voltage switch node 07932-027 figure 27. load transient, v out = 1.8 v, 50 ma to 250 ma, load current rise time = 200 ns
adp2140 rev. 0 | page 11 of 32 v in1 = 4 v, v out = 1.8 v, i out = 10 ma, c in = c out = 10 f, t a = 25c, unless otherwise noted. ch1 50.0ma ch2 50.0mv m20.0s a ch1 51.0ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-028 figure 28. load transient, v out = 1.8 v,10 ma to 110 ma, load current rise time = 200 ns ch1 200ma ch2 100.0mv m20.0s a ch1 292ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-029 figure 29. load transient, v out = 3.3 v, 200 ma to 600 ma, load current rise time = 200 ns ch1 100ma ch2 100.0mv m20.0s a ch1 80.0ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-030 figure 30. load transient, v out = 3.3 v, 50 ma to 250 ma, load current rise time = 200 ns ch1 50.0ma ch2 100.0mv m20.0s a ch1 50.0ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-031 figure 31. load transient, v out = 3.3 v,10 ma to 110 ma, load current rise time = 200 ns ch1 200.0ma ch2 50.0mv m20.0s a ch1 376ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-032 figure 32. load transient, v out = 1.2 v, 200 ma to 600 ma, load current rise time = 200 ns ch1 100.0ma ch2 50.0mv m20.0s a ch1 154ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-033 figure 33. load transient, v out = 1.2 v, 50 ma to 250 ma, load current rise time = 200 ns
adp2140 rev. 0 | page 12 of 32 v in1 = 4 v, v out = 1.8 v, i out = 10 ma, c in = c out = 10 f, t a = 25c, unless otherwise noted. ch1 50.0ma ch2 50.0mv m20.0s a ch1 48.0ma t 10.40% ch3 5.00v 1 2 3 t load current output voltage switch node 07932-034 figure 34. load transient, v out = 1.2 v,10 ma to 110 ma, load current rise time = 200 ns ch1 500ma ch2 1.00v ch4 5.00v m100s a ch4 2.70v t 10.40% ch3 5.00v 1 2 3 4 t inductor current output voltage switch node enable 1 07932-035 figure 35. startup, v out = 1.8 v, 10 ma ch1 500ma ch2 1.00v ch4 5.00v m40.0s a ch4 2.70v t 10.40% ch3 5.00v 1 2 3 4 t inductor current output voltage switch node enable 1 07932-036 figure 36. startup, v out = 1.8 v, 600 ma ch1 500ma ch2 2.00v ch4 5.00v m40.0s a ch4 2.70v t 10.40% ch3 5.00v 1 2 3 4 t inductor current output voltage switch node enable 1 07932-037 figure 37. startup, v out = 3.3 v, 10 ma ch1 500ma ch2 2.00v ch4 5.00v m40.0s a ch4 2.70v t 10.40% ch3 5.00v 1 2 3 4 t inductor current output voltage switch node enable 1 07932-100 figure 38. startup, v out = 3.3 v, 600 ma ch1 200ma ch2 1.00v ch4 5.00v m100s a ch4 2.30v t 10.40% ch3 5.00v 1 2 3 4 t inductor current output voltage switch node enable 1 07932-039 figure 39. startup, v out = 1.2 v, 10 ma
adp2140 rev. 0 | page 13 of 32 v in1 = 4 v, v out = 1.8 v, i out = 10 ma, c in = c out = 10 f, t a = 25c, unless otherwise noted. ch1 500ma ch2 1.00v ch4 5.00v m40.0s a ch4 2.30v t 10.00% ch3 5.00v 1 2 3 4 t output voltage switch node inductor current enable 1 07932-040 figure 40. startup, v out = 1.2 v, 600 ma ch1 1.00v ch2 1.00v ch4 5.00v m2.00ms a ch4 2.30v t 10.00% ch3 5.00v 1 2 3 4 t ldo output pg signal buck output enable 1 07932-041 figure 41. startup, autosequence mode, v out = 1.8 v, v out2 = 1.2 v
adp2140 rev. 0 | page 14 of 32 ldo output v in1 = 5 v, v in2 = 2.3 v, v out2 = 1.8 v, i out2 = 10 ma, c in2 = c out2 = 1 f, t a = 25c, unless otherwise noted. 1.83 1.77 1.78 1.79 1.80 1.81 1.82 ?40 125 85 25 ?5 output voltage (v) junction temperature (c) load current = 1ma load current = 5ma load current = 10ma load current = 50ma load current = 100ma load current = 300ma 07932-242 figure 42. output voltage vs. junction temperature, different loads 1.820 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 1 10 100 1000 output voltage (v) load current (ma) 07932-243 figure 43. output voltage vs. load current 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 output voltage (v) input voltage (v) load current = 1ma load current = 5ma load current = 10ma load current = 50ma load current = 100ma load current = 300ma 1.820 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 07932-244 figure 44. output voltage vs. input voltage, different loads 180 160 140 120 100 80 60 40 20 0 ?40 125 85 25 ?5 ground current (a) junction temperature (c) load current = 1ma load current = 5ma load current = 10ma load current = 50ma load current = 100ma load current = 300ma 07932-245 figure 45. ground current vs. junction temperature, different loads 160 140 120 100 80 60 40 20 0 1 10 100 1000 ground current (a) load current (ma) 07932-246 figure 46. ground current vs. load current 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 input voltage (v) load current = 1ma load current = 5ma load current = 10ma load current = 50ma load current = 100ma load current = 300ma 160 140 120 100 80 60 40 20 0 ground current (a) 07932-247 figure 47. ground current vs. input voltage, different loads
adp2140 rev. 0 | page 15 of 32 v in1 = 5 v, v in2 = 2.3 v, v out2 = 1.8 v, i out2 = 10 ma, c in2 = c out2 = 1 f, t a = 25c, unless otherwise noted. 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?50 ?25 0 25 50 75 100 125 shutdown current (a) temperature (c) 2.2v 2.6v 3.4v 3.8v 4.6v 5.5v 07932-048 figure 48. shutdown current vs. temperature at various input voltages 150 125 100 75 50 25 0 1 10 100 1000 dropout voltage (mv) load current (ma) 07932-249 figure 49. dropout voltage vs. load current 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.60 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 output voltage (v) input voltage (v) v drop = 1ma v drop = 5ma v drop = 10ma v drop = 50ma v drop = 100ma v drop = 300ma 07932-250 figure 50. output voltage vs. input voltage (in dropout) 200 180 160 140 120 100 80 60 40 20 0 1.6 1.7 1.8 1.9 2.0 ground current (a) input voltage (v) i gnd = 1ma i gnd = 5ma i gnd = 10ma i gnd = 50ma i gnd = 100ma i gnd = 300ma 07932-251 figure 51. ground current vs. input voltage (in dropout) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 300ma 100ma 10ma 1ma 07932-252 figure 52. power supply reje ction ratio vs. frequency v out2 = 1.2 v, v in1 = 5 v, v in2 = 2.2 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 300ma 200ma 100ma 10ma 1ma 07932-253 figure 53. power supply reje ction ratio vs. frequency v out2 = 1.2 v, v in1 = 5 v, v in2 = 1.7 v
adp2140 rev. 0 | page 16 of 32 v in1 = 5 v, v in2 = 2.3 v, v out2 = 1.8 v, i out2 = 10 ma, c in2 = c out2 = 1 f, t a = 25c, unless otherwise noted. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 300ma 100ma 10ma 1ma 07932-254 figure 54. power supply reject ion ratio vs. frequency, v out2 = 3.3 v, v in1 = 5 v, v in2 = 4.3 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 300ma 100ma 10ma 1ma 07932-255 figure 55. power supply reject ion ratio vs. frequency, v out2 = 1.8 v, v in1 = 5 v, v in2 = 2.8 v 10 0.01 0.1 1 10 100 1k 10k 100k (v/ hz) frequency (hz) 1.2v 1.8v 2.5v 3.3v 07932-055 figure 56. output noise spectrum, v in2 = 5 v, load current = 10 ma 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 300ma 200ma 100ma 10ma 1ma 07932-256 figure 57. power supply reject ion ratio vs. frequency, v out2 = 3.3 v, v in1 = 5 v, v in2 = 3.8 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 300ma 200ma 100ma 10ma 1ma 07932-257 figure 58. power supply reje ction ratio vs. frequency v out2 = 1.8 v, v in1 = 5 v, v in2 = 2.3 v 100 90 80 70 60 50 40 30 20 10 0 100n 1 10 100 1m 10m 1 100m noise (v rms) load current (a) 1.2v 1.8v 2.5v 3.3v 07932-261 figure 59. output noise vs. lo ad current and output voltage v in2 = 5 v
adp2140 rev. 0 | page 17 of 32 v in1 = 5 v, v in2 = 2.3 v, v out2 = 1.8 v, i out2 = 10 ma, c in2 = c out2 = 1 f, t a = 25c, unless otherwise noted. ch1 100ma ch2 100mv m40.0s a ch1 68ma t 10.40% 1 2 t 07932-259 load current v out2 figure 60. load transient response, v in2 = 4 v, v out2 = 1.2 v, 1 ma to 300 ma, load current rise time = 200 ns ch1 100ma ch2 100mv m40.0s a ch1 68ma t 10.40% 1 2 t 07932-260 load current v out2 figure 61. load transient response, v in2 = 4 v, v out2 = 1.8 v, 1 ma to 300 ma, load current rise time = 200 ns ch1 100ma ch2 100mv m40.0s a ch1 68ma t 10.40% 1 2 t 07932-262 load current v out2 figure 62. load transient response, v in2 = 4 v, v out2 = 3.3 v, 1 ma to 300 ma, load current rise time = 200 ns ch1 1.00v ch2 5.00mv m2.00s a ch4 12mv t 10.20% 1 2 t 07932-263 v in2 v out2 figure 63. line transient response, v out2 = 1.8 v, load current = 1 ma, v in2 = 4 v to 5 v, 1 s rise time ch1 1.00v ch2 5.00mv m2.00s a ch4 12mv t 10.20% 1 2 t 07932-264 v out2 v in2 figure 64. line transient response, v out2 = 1.2 v, load current = 1 ma, v in2 = 4 v to 5 v, 1 s rise time ch1 1.00v ch2 5.00mv m2.00s a ch4 12mv t 10.20% 1 2 t 07932-265 v out2 v in2 figure 65. line transient response, v out2 = 3.3 v, load current = 1 ma, v in2 = 4 v to 5 v, 1 s rise time
adp2140 rev. 0 | page 18 of 32 v in1 = 5 v, v in2 = 2.3 v, v out2 = 1.8 v, i out2 = 10 ma, c in2 = c out2 = 1 f, t a = 25c, unless otherwise noted. ch1 1.00v ch2 5.00mv m2.00s a ch4 12mv t 10.20% 1 2 t 07932-266 v out2 v in2 figure 66. line transient response, v out2 = 1.8 v, load current = 300 ma, v in2 = 4 v to 5 v, 1 s rise time ch1 1.00v ch2 5.00mv m2.00s a ch4 12mv t 10.20% 1 2 t 07932-267 v out2 v in2 figure 67. line transient response, v out2 = 1.2 v, load current = 300 ma, v in2 = 4 v to 5 v, 1 s rise time ch1 1.00v ch2 5.00mv m2.00s a ch4 12mv t 10.20% 1 2 t 07932-268 v out2 v in2 figure 68. line transient response, v out2 = 3.3 v, load current = 300 ma, v in2 = 4 v to 5 v, 1 s rise time
adp2140 rev. 0 | page 19 of 32 theory of operation pwm/ psm control enable/ sequencing gm error amp soft start reference 0.5v 3mhz oscillator current limit power good thermal shutdown r1 r2 fb vin2 a gnd en1 en2 uvlo vin1 sw pgnd pg epad current sense amp zero-cross comparator fb driver and antishoot through 0 7932-068 figure 69. internal block diagram buck section the adp2140 contains a step-down dc-to-dc converter that uses a fixed frequency, high speed current-mode architecture. the high 3 mhz switching frequency and tiny 10-lead, 3 mm 3 mm lfcsp package allow for a small step-down dc-to-dc converter solution. the adp2140 operates with an input voltage from 2.3 v to 5.5 v. output voltage options are 1.0 v, 1.1 v, 1.2 v, 1.5 v, 1.8 v, 1.875 v, 2.5 v, and 3.3 v. control scheme the adp2140 operates with a fixed frequency, current-mode pwm control architecture at medium to high loads for high efficiency, but shifts to a variable frequency control scheme at light loads for lower quiescent current. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches adjust to regulate the output voltage, but when operating in power saving mode (psm) at light loads, the switching frequency adjusts to regulate the output voltage. the adp2140 operates in the pwm mode only when the load current is greater than the pulse skipping threshold current. at load currents below this value, the converter smoothly transitions to the psm mode of operation. pwm operation in pwm mode, the adp2140 operates at a fixed frequency of 3 mhz set by an internal oscillator. at the start of each oscillator cycle, the p-channel mosfet switch is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current level that turns off the p-channel mosfet switch and turns on the n-channel mosfet synchronous rectifier. this puts a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the remainder of the cycle, unless the inductor current reaches zero, which causes the zero-crossing comparator to turn off the n-channel mosfet. psm operation the adp2140 has a smooth transition to the variable frequency psm mode of operation when the load current decreases below the pulse skipping threshold current, switching only as necessary to maintain the output voltage within regulation. when the output voltage dips below regulation, the adp2140 enters pwm mode for a few oscillator cycles to increase the output voltage back to regulation. during the wait time between bursts, both power switches are off, and the output capacitor supplies the entire load current. because the output voltage occasionally dips and recovers, the output voltage ripple in this mode is larger than the ripple in the pwm mode of operation. pulse skipping threshold the output current at which the adp2140 transitions from variable frequency psm control to fixed frequency pwm control is called the pulse skipping threshold. the pulse skipping threshold has been optimized for excellent efficiency over all load currents.
adp2140 rev. 0 | page 20 of 32 selected features short-circuit protection the adp2140 includes frequency foldback to prevent output current runaway on a hard short. when the voltage at the feed- back pin falls below 50% of the nominal output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to 1/2 of the internal oscillator frequency. the reduc- tion in the switching frequency gives more time for the inductor to discharge, preventing a runaway of output current. undervoltage lockout to protect against battery discharge, undervoltage lockout circuitry is integrated on the adp2140. if the input voltage drops below the 2.15 v uvlo threshold, the adp2140 shuts down and both the power switch and synchronous rectifier turn off. when the voltage rises again above the uvlo threshold, the soft start period initiates and the part is enabled. thermal protection in the event that the adp2140 junction temperatures rises above 150c, the thermal shutdown circuit turns off the converter. extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient tem- perature. a 20c hysteresis is included; thus, when thermal shutdown occurs, the adp2140 does not return to operation until the on-chip temperature drops below 130c. when emerging from a thermal shutdown, soft start initiates. soft start the adp2140 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is con- nected to the input of the converter. current limit the adp2140 has protection circuitry to limit the direction and amount of current to 1000 ma flowing through the power switch and synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output, and the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load. the adp2140 also provides a negative current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced continuous conduction mode. under negative current limit conditions, both the high- side and low-side switches are disabled. power-good pin the adp2140 has a dedicated pin (pg) to signal the state of the monitored output voltages. the voltage monitor circuit has an active high, open-drain output requiring an external pull-up resistor typically supplied from the i/o supply rail, as shown in figure 1 . the voltage monitor circuit has a small amount of hysteresis and is deglitched to ensure that noise or external perturbations do not trigger the pg line. ldo section the adp2140 low dropout linear regulator uses an advanced proprietary architecture to achieve low quiescent current, and high efficiency regulation. it also provides high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response with just a small 1 f ceramic output capa- citor. the wide input voltage range of 1.65 v to 5.5 v allows it to operate from either the input or output of the buck. supply current in shutdown mode is typically 0.3 a. internally, the ldo consists of a reference, an error amplifier, a feedback voltage divider, and a pass device. the output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system ideally driving the feedback voltage to be equal to the reference voltage. if the feedback voltage is lower than the reference voltage, the negative feedback drives more current, increasing the output voltage. if the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. the positive supply for all circuitry, except the pass device, is the vin1 pin. the ldo has an internal soft start that limits the output voltage ramp period to approximately 130 s. the ldo is available in 0.8 v, 1.0 v, 1.1 v, 1.2 v, 1.3 v, 1.5 v, 2.5 v, 2.8 v, 3.0 v, and 3.3 v output voltage options.
adp2140 rev. 0 | page 21 of 32 applications information power sequencing the adp2140 has a flexible power sequencing system supporting two distinct activation modes: ? individual activation control is where en1 controls only the buck regulator and en2 controls only the ldo. a high level on pin en1 turns on the buck and a high level on pin en2 turns on the ldo. a logic low level turns off the respective regulator. ? autosequencing is where the two regulators turn on in a specified order and delay after a low-to-high transition on the en1 pin. select the activation mode (individual or autosequence) by decoding the state of pin en2. the individual activation mode is selected when the en2 pin is driven externally or hardwired to a voltage level (vin1 or pgnd). the autosequencing mode is selected when the en2 pin remains unconnected (floating). to minimize quiescent current consumption, the mode selection executes one time only during the rising edge of vin1. the detection circuit then activates for the time needed to assess the en2 state, after which time the circuit is disabled until vin1 falls below 0.5 v. when en2 is unconnected, the internal control circuit provides a termination resistance to ground. the 100 k termination resistance is low enough to guarantee insensitivity to noise and transients. the termination resistor is disabled in the event that the en2 pin is driven externally to a logic level high (individual activation mode assumed) to reduce the quiescent current con- sumption. when the autosequencing mode is selected, the en1 pin is used to start the on/off sequence of the regulators. a logic high sequences the regulators on whereas a logic low sequences the regulators off. the regulator activation order is associated with the voltage selected for the buck regulator and the ldo. when the turn on or turn off autosequence starts, the start-up delay between the first and the second regulator is fixed to 5 ms in pwm mode (t reg12 , as shown in figure 71 and figure 72 ). when the application requires activating and deactivating the regulators at the same time, use the individual activation mode, which connects the en1 and en2 pins together, as shown in figure 75 . table 6. power sequencing modes en2 1 en1 description 0 0 individual mode: both regulators are off. 0 1 individual mode: buck regulator is on. 1 0 individual mode: ldo regulator is on. 1 1 individual mode: both regulators are on. nc rising edge autosequence: buck regulator turns on, then the ldo regulator turns on. the ldo voltage is less than the buck voltage. nc rising edge autosequence: ldo regulator turns on, then the buck regulator turns on. the ldo voltage is greater than the buck voltage. nc rising edge autosequence: if the buck voltage is 1.875 v, then the ldo regulator always turns on first. nc falling edge autosequence: the ldo and buck regula- tors turn off at the same time. 1 nc means not connected. figure 70 to figure 75 use the following symbols, as described in table 7 . table 7. timing symbols symbol description typical value t start time needed for the internal circuitry to activate the first regulator 60 s t ss regulator soft start time 330 s t reset time delay from power-good condition to the release of pg 5 ms t reg12 delay time between buck and ldo activation 5 ms en1 v buck en2 v ldo pg 92% v buck 92% v ldo 85% v ldo t ss t reset t ss time v 0 7932-069 figure 70. individual activation mode
adp2140 rev. 0 | page 22 of 32 en1 v buck en2 = unconnected v ldo pg 92% v buck 85% v ldo 92% v ldo t ss t ss t start t reset t reg12 time v 07932-111 figure 71. autosequencing mode, buck first then ldo 0 7932-112 en1 v buck v ldo pg 85% v buck t ss t reg12 time v en2 = unconnected t start 92% v ldo 92% v buck t ss t reset figure 72. autosequencing mode, ldo first then buck the pg responds to the last activated regulator. as described in the power sequencing section, the regulator order in the auto- sequencing mode is defined by the voltage option combination. therefore, if the sequence is buck first, the ldo and the pg signal are active low for t reset after v ldo reaches 92% of the rated output voltage, at which time pg goes high and remains high for as long as v ldo is above 86% of the rated output voltage. when the sequencing is ldo first then buck, v buck controls pg. this control scheme also applies when the individual activation mode is selected. as soon as either regulator output voltage drops below 86% of the respective nominal level, the pg pin is forced low. en2 en1 v buck v ldo pg 92% v ldo t reset t reset 92% v buck 85% v buck 95% v buck 85% v buck 85% v ldo 0 7932-072 figure 73. individual activation mode, both regulators sensed en2 en1 v buck v ldo pg 92% v ldo t reset 92% v buck 85% v buck 85% v ldo 07932-073 figure 74. individual activation mode , one regulator only (buck) sensed t reset 92% v buck 92% v ldo 85% v buck 85% v ldo en1 en2 pg v ldo v buck 0 7932-075 figure 75. individual activation mo de, no activation/deactivation delay between regulators, en1 and en2 pins tied together ch1 500mv ch2 500mv m1.00ms a ch3 1.16v t 10.00% ch3 2.00v 1 2 3 t ldo output buck output en1 07932-101 figure 76. autosequence mode turn on behavior, buck voltage = 1.8 v, ldo voltage = 1.2 v, buck load = 500 ma, ldo load = 100 ma ch1 500mv ch2 500mv m40.0s a ch3 1.16v t 10.00% ch3 2.00v 1 2 3 t ldo output buck output en1 07932-102 figure 77. autosequence mode turn on behavior, buck voltage = 1.8 v, ldo voltage = 1.2 v, buck load = 500 ma, ldo load = 100 ma
adp2140 rev. 0 | page 23 of 32 ch1 500mv ch2 500mv m40.0s a ch3 1.16v t 10.00% ch3 2.00v 1 2 3 t ldo output buck output en1 07932-103 figure 78. autosequence mode turn on behavior, buck voltage = 1.8 v, ldo voltage = 1.2 v, buck load = 500 ma, ldo load = 100 ma ch1 1.00v ch2 1.00v m100ms a ch3 3.04v ch3 2.00v 1 2 3 ldo output buck output en1 07932-104 figure 79. autosequence mode turn on behavior, buck voltage =1.8 v, ldo voltage = 1.2 v, buck load = 1 ma, ldo load = 100 ma ch1 500mv ch2 1.00v m2.00ms a ch3 2.04v t 10.00% ch3 2.00v 1 2 3 t ldo output buck output en1 07932-105 figure 80. autosequence mode turn on behavior, buck voltage = 1.0 v, ldo voltage = 3.3 v, buck load = 500 ma, ldo load = 100 ma ch1 500mv ch2 1.00v m40.0s a ch3 2.04v t 10.00% ch3 2.00v 1 2 3 t buck output en1 07932-106 ldo output figure 81. autosequence mode turn on behavior, buck voltage = 1.0 v, ldo voltage = 3.3 v, buck load = 500 ma, ldo load = 100 ma (expanded version of figure 80 ) ch1 500mv ch2 1.00v m40.0s a ch3 2.04v t 10.00% ch3 2.00v 1 2 3 t buck output en1 07932-107 ldo output figure 82. autosequence mode turn off behavior, buck voltage = 1.0 v, ldo voltage = 3.3 v, buck load = 500 ma, ldo load = 100 ma ch1 500mv ch2 1.00v m2.00ms a ch3 3.04v t 10.00% ch3 2.00v 1 2 3 t buck output en1 07932-108 ldo output figure 83. autosequence mode turn on behavior, buck voltage = 1.0 v, ldo voltage = 3.3 v, buck load = 1 ma, ldo load = 100 ma
adp2140 rev. 0 | page 24 of 32 ch1 500mv ch2 500mv m40.0s a ch3 1.16v t 10.00% ch3 2.00v 1 2 3 t ldo output buck output en1 07932-109 figure 84. individual activation mode, en1 and en2 pins tied together power-good function the adp2140 power-good (pg) pin indicates the state of the monitored output voltages. the pg function is the logical and of the state of both outputs. the pg function is an active high, open-drain output, requiring an external pull-up resistor typically supplied from the i/o supply rail, as shown in figure 1 . when the sensed output voltages are below 92% of their nominal value, the pg pin is held low. when the sensed output voltages rise above 92% of the nominal levels, the pg line is pulled high after t reset . the pg pin remains high as long as the sensed output voltages are above 86% of the nominal output voltage levels. the typical pg delay when the buck is in pwm mode is 5 ms. when the part is in psm mode, the pg delay is load dependent because the internal clock is disabled to reduce quiescent current during the sleep stage. pg delay varies from hundreds of micro- seconds at 10 ma, up to seconds at current loads of less than 10 a. ch1 2.00v ch2 2.00v ch4 2.00v m2.00ms a ch1 2.20v t 10.20% ch3 2.00v 1 2 3 4 t en1 buck ldo pg 07932-285 figure 85. typical pg timing external component selection the external component selection for the adp2140 application circuit that is shown in table 8 , table 9 , and figure 86 is dependent on input voltage, output voltage, and load current requirements. additionally, trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components. selecting the inductor the high frequency switching of the adp2140 allows the selection of small chip inductors. the inductor value affects the transi- tion between cfm to psm, efficiency, output ripple, and current limit values. use the following equation to calculate the inductor ripple current: lfv vvv i sw in out in out l ? = ) ( where: f sw is the switching frequency (3 mhz typical). l is the inductor value. the dc resistance (dcr) value of the selected inductor affects efficiency, but a decrease in this value typically means an increase in root mean square (rms) losses in the core and skin. as a minimum requirement, the dc current rating of the inductor should be equal to the maximum load current plus half of the inductor current ripple, as shown by the following equation: ) 2 ( )( l max load pk i ii + = output capacitor output capacitance is required to minimize the voltage over- shoot and ripple present on the output. capacitors with low equivalent series resistance (esr) values produce the lowest output ripple; therefore, use capacitors such as the x5r dielectric. do not use the y5v and z5u capacitors; they are not suitable for this application because of their large variation in capacitance over temperature and dc bias voltage. because esr is important, select the capacitor using the following equation: l ripple cout i v esr where: esr cout is the esr of the chosen capacitor. v ripple is the peak-to-peak output voltage ripple. use the following equations to determine the output capacitance: ripple sw in out vlf v c 2)2( out sw l out vf i c 8 increasing the output capacitor has no effect on stability and increasing the output capacitance may further reduce output ripple and enhance load transient response. when choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. input capacitor input capacitance is required to reduce input voltage ripple; there- fore, place the input capacitor as close as possible to the vinx pins. as with the output capacitor, a low esr x7r- or x5r-type
adp2140 rev. 0 | page 25 of 32 switching losses capacitor is recommended to help minimize the input voltage ripple. use the following equation to determine the minimum input capacitance: switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. each time a power device gate is turned on and turned off, the driver transfers a charge, q, from the input supply to the gate, and then from the gate to ground. in out in out max load cin v vvv ii ) ( )( ? efficiency estimate switching losses using the following equation: efficiency is defined as the ratio of output power to input power. the high efficiency of the adp2140 has two distinct advantages. first, only a small amount of power is lost in the dc-to-dc con- verter package, which in turn, reduces thermal constraints. in addition, high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. p sw = (c gate_p + c gate_n ) v in 2 f sw where: c gate_p is the gate capacitance of the internal high-side switch. c gate_n is the gate capacitance of the internal low-side switch. f sw is the switching frequency. transition losses transition losses occur because the p-channel switch cannot turn on or turn off instantaneously. in the middle of an sw node transition, the power switch provides all of the inductor current. the source-to-drain voltage of the power switch is half the input voltage, resulting in power loss. transition losses increase with both load current and input voltage and occur twice for each switching cycle. power switch conduction losses power switch dc conduction losses are caused by the flow of output current through the p-channel power switch and the n-channel synchronous rectifier, which have internal resis- tances ( r ds(on) ) associated with them. the amount of power loss can be approximated by 2 _)( _)( _ ))1( ( out nonds p onds condsw id rd r p ? + = use the following equation to estimate transition losses: where in out v v d = p tran = v in /2 i out (t r + t f ) f sw where: t r is the rise time of the sw node. the internal resistance of the power switches increases with temperature but decreases with higher input voltage. t f is the fall time of the sw node. recommended buck ex ternal components inductor losses inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (dcr) associated with it. larger size inductors have smaller dcr, which can decrease inductor conduction losses. inductor core losses relate to the magnetic permeability of the core material. because the adp2140 is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low emi. the recommended buck external components for use with the adp2140 are listed in table 8 (inductors) and table 9 (capacitors). vin1 pgnd pg sw en1 agnd en2 pg en1 en2 fb vout2 10 9 8 7 6 vin2 1 2 3 4 5 adp2140 100k ? + cin 10f + cout2 1f + cout 10f v in1 = 3.6 v v out2 = 1.8v 1h v out = 1.2 v 07932-076 to estimate the total amount of power lost in the inductor, use the following equation: p l = dcr i out 2 + core losses figure 86. typical application circuit with ldo connected to input voltage table 8. 1.0 h inductors vendor model case size dimensions isat (ma) dcr (m) murata lqm21pn1r0mc0d 0805 2.0 mm 1.25 mm 0.5 mm 800 190 murata lqm31pn1r0m00l 1206 3.2 mm 1.6 mm 0.95 mm 1200 120 murata lqm2hpn1r0mj0 1008 2.5 mm 2.0 mm 0.95 mm 1500 90 fdk mipsa2520d1r0 2.5 mm 2.0 mm 1.0 mm 1200 90 table 9. 10 f capacitors vendor type model case size voltage rating murata x5r grm219r60j106 0805 6.3 v taiyo yuden x5r jmk212bj106 0805 6.3 v tdk x5r c1608x5r0j106 0603 6.3 v
adp2140 rev. 0 | page 26 of 32 ldo capacitor selection output capacitor the adp2140 ldo is designed for operation with small, space- saving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken about the effective series resistance (esr) value. the esr of the output capacitor affects stability of the ldo control loop. a minimum of 0.70 f capa- citance with an esr of 1 or less is recommended to ensure stability of the adp2140. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adp2140 to large changes in load current. figure 87 shows the transient response for an output capacitance value of 1 f. ch1 100ma ch2 100mv m40.0s a ch1 68ma t 10.40% 1 2 t 07932-286 load current v out2 figure 87. output transient response, v out2 = 1.8 v, c out = 1 f, 1 ma to 300 ma, load current rise time = 200 ns input bypass capacitor connecting a 1 f capacitor from vin to gnd reduces the cir- cuit sensitivity to the pcb layout, especially when long input traces or high source impedance are encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it. input and output capacitor properties use any good quality ceramic capacitors with the adp2140, as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 88 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera- ture range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 02 4681 voltage (v) capacitance (f) 0 murata part number: grm155r61a105ke15 07932-077 figure 88. capacitance vs. voltage characteristic use equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 0.94 f at 1.8 v as shown in figure 88 . substituting these values in equation 1 yields c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temper- ature and tolerance at the chosen output voltage. to guarantee the performance of the adp2140, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. ldo as a postregulator to reduce buck output noise the output of the buck regulator may not be suitable for many noise sensitive applications because of its inherent switching noise. this is particularly true when the buck is operating in psm mode because the switching noise may be in the audio range. the adp2140 ldo can greatly reduce the noise at the output of the buck at high efficiency because of the load dropout voltage of the ldo and the high psrr of the ldo. figure 89 and figure 90 show the noise reduction that is possible when the ldo is used as a post regulator.
adp2140 rev. 0 | page 27 of 32 ch1 50.0mv ch2 10.0mv m40.0s a ch1 ?27.0mv t 48.00% 1 2 t buck output voltage ldo output voltage 07932-066 figure 89. ldo as a postregulator (see figure 2 ), v out = 1.8 v, load current = 50 ma, v out2 = 1.2 v, load current = 50 ma ch1 10.0mv ch2 10.0mv m2.00s a ch1 800v t 48.00% 1 2 t buck output voltage ldo output voltage 07932-067 figure 90. ldo as a postregulator (see figure 2 ), v out = 1.8 v, load current = 500 ma, v out2 = 1.2 v, load current = 50 ma
adp2140 rev. 0 | page 28 of 32 thermal considerations in most applications, the adp2140 does not dissipate much heat due to its high efficiency. however, in applications with high ambient temperature and high supply voltage-to-output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125c. where: i load is the ldo load current. i agnd is the analog ground current. v in and v out are the ldo input and output voltages, respectively. p sw , p tran , and p sw_cond are defined in the efficiency section. when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the junction temperature has decreased below 130c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera- ture rise of the package due to the power dissipation, as shown in equation 2. for a given ambient temperature and total power dissipation, there exists a minimum copper size requirement for the pcb to ensure the junction temperature does not rise above 125c. the following figures show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of pcb copper. 145 135 125 115 105 95 85 75 65 55 45 35 25 0 0.250.500.751.001.251.501.752.002.252.502.753.00 junction temperature (c) total power dissipation (w) 500mm 2 50mm 2 0mm 2 t j max 07932-078 to guarantee reliable operation, the junction temperature of the adp2140 must not exceed 125c. to ensure the junction temper- ature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipa- tion in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pins to the pcb. table 10 shows typical ja values of the 10-lead, 3 mm 3 mm lfcsp for various pcb copper sizes. figure 91. junction temperature vs. power dissipation, t a = 25c table 10. typical ja values copper sie mm 2 ja (c/w) 0 1 42.5 50 40.0 100 38.8 300 37.2 500 36.2 1 the device is soldered to minimum size pin traces. the junction temperature of the adp2140 can be calculated from the following equation: t j = t a + (p d ja ) (2) 140 130 120 110 100 90 80 70 60 50 0 0.250.500.751.001.251.501.752.002.252.50 junction temperature (c) total power dissipation (w) 500mm 2 50mm 2 0mm 2 t j max 07932-079 where: t a is the ambient temperature. p d is the total power dissipation in the die, given by figure 92. junction temperature vs. power dissipation, t a = 50c p d = p ldo + p buck where: p ldo = [( v in ? v out ) i load ] + ( v in i agnd ) (3) p buck = p sw + p tran + p sw_cond (4)
adp2140 rev. 0 | page 29 of 32 145 135 125 115 105 95 85 75 65 0 0.20.40.60.81.01.21.41.61.82.0 junction temperature (c) total power dissipation (w) 500mm 2 50mm 2 0mm 2 t j max 07932-080 figure 93. junction temperature vs. power dissipation, t a = 65c 135 125 115 105 95 85 01 1.41.31.2 1.11.00.90.80.70.6 0.50.40.30.20.1 junction temperature (c) total power dissipation (w) . 5 500mm 2 50mm 2 0mm 2 t j max 07932-081 figure 94. junction temperature vs. power dissipation, t a = 85c in cases where the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction temper- ature rise. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + (p d jb ) (5) the typical jb value for the 10-lead, 3 mm 3 mm lfcsp is 16.9c/w. 140 100 120 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 junction temperature (c) total power dissipation (w) t b = 25c t b = 50c t b = 65c t b = 85c t j max 07932-082 figure 95. junction temperature vs. power dissipation pcb layout considerations improve heat dissipation from the package by increasing the amount of copper attached to the pins of the adp2140. however, as listed in table 10 , a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. poor layout can affect the adp2140 buck performance causing electromagnetic interference (emi) and electromagnetic compa- tibility (emc) performance, ground bounce, and voltage losses; thus, regulation and stability can be affected. implement a good layout using the following rules: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies and long, large tracks act like antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? use a ground plane with several vias connected to the component-side ground to reduce noise interference on sensitive circuit nodes. ? use of 0402- or 0603-size capacitors achieves the smallest possible footprint solution on boards where area is limited. 07932-083 figure 96. pcb layout, top 07932-084 figure 97. pcb layout, bottom
adp2140 rev. 0 | page 30 of 32 031208-b outline dimensions top view 10 1 6 5 0.30 0.23 0.18 * exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 bsc p i n 1 i n d i c a t o r ( r 0 . 2 0 ) 0.50 0.40 0.30 * for proper connection of the exposed pad please refer to the pin configuration and function descriptions section of this data sheet. figure 98. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model 1 buck output voltage (v) ldo output voltage (v) temperature range package description package option branding adp2140acpz1218r7 1.2 1.8 ?40c to +125c 10-lead lfcsp_wd cp-10-9 let adp2140acpz1228r7 1.2 2.8 ?40c to +125c 10-lead lfcsp_wd cp-10-9 leq ADP2140ACPZ1233R7 1.2 3.3 ?40c to +125c 10-lead lfcsp_wd cp-10-9 ler adp2140acpz1528r7 1.5 2.8 ?40c to +125c 10-lead lfcsp_wd cp-10-9 les adp2140acpz1533r7 1.5 3.3 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lex adp2140acpz1812r7 1.8 1.2 ?40c to +125c 10-lead lfcsp_wd cp-10-9 leu adp2140acpz1815r7 1.8 1.5 ?40c to +125c 10-lead lfcsp_wd cp-10-9 ley adp2140acpz1833r7 1.8 3.3 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lez adp2140acpz18812r7 1.875 1.2 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lh8 adp2140acpz2518r7 2.5 1.8 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lge adp2140acpz3312r7 3.3 1.2 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lf0 adp2140acpz3315r7 3.3 1.5 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lf1 adp2140acpz3318r7 3.3 1.8 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lf2 adp2140acpz3325r7 3.3 2.5 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lf4 adp2140acpz3328r7 3.3 2.8 ?40c to +125c 10-lead lfcsp_wd cp-10-9 lf3 adp2140cp-evalz evaluation board adp2140cpz-redykit evaluation board 1 z = rohs compliant part.
adp2140 rev. 0 | page 31 of 32 notes
adp2140 rev. 0 | page 32 of 32 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07932-0-6/10(0)

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