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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1994 copyright ? intel corporation, 1995 order number: 272430-002 80186/80188 high-integration 16-bit microprocessors y integrated feature set e enhanced 8086-2 cpu e clock generator e 2 independent dma channels e programmable interrupt controller e 3 programmable 16-bit timers e programmable memory and peripheral chip-select logic e programmable wait state generator e local bus controller y available in 10 mhz and 8 mhz versions y high-performance processor e 4 mbyte/sec bus bandwidth interface @ 8 mhz (80186) e 5 mbyte/sec bus bandwidth interface @ 10 mhz (80186) y direct addressing capability to 1 mbyte of memory and 64 kbyte i/o y completely object code compatible with all existing 8086, 8088 software e 10 new instruction types y numerics coprocessing capability through 8087 interface y available in 68 pin: e plastic leaded chip carrier (plcc) e ceramic pin grid array (pga) e ceramic leadless chip carrier (lcc) y available in express e standard temperature with burn-in e extended temperature range ( b 40 cto a 85 c) 272430 1 figure 1. block diagram 1
80186/80188 high-integration 16-bit microprocessors contents page functional description 9 introduction 9 clock generator 9 oscillator 9 clock generator 9 ready synchronization 9 reset logic 9 local bus controller 9 memory/peripheral control 10 local bus arbitration 10 local bus controller and reset 10 peripheral architecture 10 chip-select/ready generation logic 10 dma channels 11 timers 11 interrupt controller 12 contents page absolute maximum ratings 15 d.c. characteristics 15 a.c. characteristics 16 explanation of the ac symbols 18 waveforms 19 express 25 execution timings 26 instruction set summary 27 footnotes 32 revision history 33 2 2
80186/80188 contacts facing up contacts facing down 272430 2 figure 2. ceramic leadless chip carrier (jedec type a) pins facing up pins facing down 272430 3 figure 3. ceramic pin grid array note: pin names in parentheses apply to the 80188. 3 3
80186/80188 leads facing up leads facing down 272430 4 figure 4. plastic leaded chip carrier note: pin names in parentheses apply to the 80188. 4 4
80186/80188 table 1. pin descriptions symbol pin type name and function no. v cc 9i system power: a 5 volt power supply. 43 v ss 26 i system ground. 60 reset 57 o reset output indicates that the cpu is being reset, and can be used as a system reset. it is active high, synchronized with the processor clock, and lasts an integer number of clock periods corresponding to the length of the res signal. x1 59 i crystal inputs x1 and x2 provide external connections for a fundamental mode parallel resonant crystal for the internal oscillator. instead of using a crystal, an x2 58 o external clock may be applied to x1 while minimizing stray capacitance on x2. the input or oscillator frequency is internally divided by two to generate the clock signal (clkout). clkout 56 o clock output provides the system with a 50% duty cycle waveform. all device pin timings are specified relative to clkout. res 24 i an active res causes the processor to immediately terminate its present activity, clear the internal logic, and enter a dormant state. this signal may be asynchronous to the processor clock. the processor begins fetching instructions approximately 6 (/2 clock cycles after res is returned high. for proper initialization, v cc must be within specifications and the clock signal must be stable for more than 4 clocks with res held low. res is internally synchronized. this input is provided with a schmitt-trigger to facilitate power-on res generation via an rc network. test 47 i/o test is examined by the wait instruction. if the test input is high when ``wait'' execution begins, instruction execution will suspend. test will be resampled until it goes low, at which time execution will resume. if interrupts are enabled while the processor is waiting for test , interrupts will be serviced. during power-up, active res is required to configure test as an input. this pin is synchronized internally. tmr in 0 20 i timer inputs are used either as clock or control signals, depending upon the programmed timer mode. these inputs are active high (or low-to-high tmr in 1 21 i transitions are counted) and internally synchronized. tmr out 0 22 o timer outputs are used to provide single pulse or continous waveform generation, depending upon the timer mode selected. tmr out 1 23 o drq0 18 i dma request is asserted high by an external device when it is ready for dma channel 0 or 1 to perform a transfer. these signals are level-triggered and drq1 19 i internally synchronized. nmi 46 i the non-maskable interrupt input causes a type 2 interrupt. an nmi transition from low to high is latched and synchronized internally, and initiates the interrupt at the next instruction boundary. nmi must be asserted for at least one clock. the non-maskable interrupt cannot be avoided by programming. int0 45 i maskable interrupt requests can be requested by activating one of these pins. when configured as inputs, these pins are active high. interrupt requests are int1/select 44 i synchronized internally. int2 and int3 may be configured to provide active- int2/inta0 42 i/o low interrupt-acknowledge output signals. all interrupt inputs may be int3/inta1 /irq 41 i/o configured to be either edge- or level-triggered. to ensure recognition, all interrupt requests must remain active until the interrupt is acknowledged. when slave mode is selected, the function of these pins changes (see interrupt controller section of this data sheet). note: pin names in parentheses apply to the 80188. 5 5
80186/80188 table 1. pin descriptions (continued) symbol pin type name and function no. a19/s6 65 o address bus outputs (1619) and bus cycle status (36) indicate the four most significant address bits during t 1 . these signals are active high. during t 2 ,t 3 ,t w , a18/s5 66 o and t 4 , the s6 pin is low to indicate a cpu-initiated bus cycle or high to indicate a a17/s4 67 o dma-initiated bus cycle. during the same t-states, s3, s4, and s5 are always low. a16/s3 68 o the status pins float during bus hold or reset. ad15 (a15) 1 i/o address/data bus signals constitute the time multiplexed memory or i/o address (t 1 ) and data (t 2 ,t 3 ,t w , and t 4 ) bus. the bus is active high. a 0 is analogous to bhe for ad14 (a14) 3 i/o the lower byte of the data bus, pins d 7 through d 0 . it is low during t 1 when a byte is ad13 (a13) 5 i/o to be transferred onto the lower portion of the bus in memory or i/o operations. bhe ad12 (a12) 7 i/o does not exist on the 80188, as the data bus is only 8 bits wide. ad11 (a11) 10 i/o ad10 (a10) 12 i/o ad9 (a9) 14 i/o ad8 (a8) 16 i/o ad7 2 i/o ad6 4 i/o ad5 6 i/o ad4 8 i/o ad3 11 i/o ad2 13 i/o ad1 15 i/o ad0 17 i/o bhe /s7 64 o during t 1 the bus high enable signal should be used to determine if data is to be enabled onto the most significant half of the data bus; pins d 15 d 8 . bhe is low (s7) during t 1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the higher half of the bus. the s 7 status information is available during t 2 ,t 3 , and t 4 .s 7 is logically equivalent to bhe . bhe /s7 floats during hold. on the 80188, s7 is high during normal operation. bhe and a0 encodings (80186 only) bhe a0 function value value 0 0 word transfer 0 1 byte transfer on upper half of data bus (d15d8) 1 0 byte transfer on lower half of data bus (d 7 d 0 ) 1 1 reserved ale/qs0 61 o address latch enable/queue status 0 is provided by the processor to latch the address. ale is active high. addresses are guaranteed to be valid on the trailing edge of ale. the ale rising edge is generated off the rising edge of the clkout immediately preceding t 1 of the associated bus cycle, effectively one-half clock cycle earlier than in the 8086. the trailing edge is generated off the clkout rising edge in t 1 as in the 8086. note that ale is never floated. wr /qs1 63 o write strobe/queue status 1 indicates that the data on the bus is to be written into a memory or an i/o device. wr is active for t 2 ,t 3 , and t w of any write cycle. it is active low, and floats during hold. when the processor is in queue status mode, the ale/ qs0 and wr /qs1 pins provide information about processor/instruction queue interaction. qs1 qs0 queue operation 0 0 no queue operation 0 1 first opcode byte fetched from the queue 1 1 subsequent byte fetched from the queue 1 0 empty the queue note: pin names in parentheses apply to the 80188. 6 6
80186/80188 table 1. pin descriptions (continued) symbol pin type name and function no. rd /qsmd 62 i/o read strobe is an active low signal which indicates that the processor is performing a memory or i/o read cycle. it is guaranteed not to go low before the a/d bus is floated. an internal pull-up ensures that rd is high during reset. following reset the pin is sampled to determine whether the processor is to provide ale, rd , and wr , or queue status information. to enable queue status mode, rd must be connected to gnd. rd will float during bus hold. ardy 55 i asynchronous ready informs the processor that the addressed memory space or i/o device will complete a data transfer. the ardy pin accepts a rising edge that is asynchronous to clkout, and is active high. the falling edge of ardy must be synchronized to the processor clock. connecting ardy high will always assert the ready condition to the cpu. if this line is unused, it should be tied low to yield control to the srdy pin. srdy 49 i synchronous ready informs the processor that the addressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active-high input synchronized to clkout. the use of srdy allows a relaxed system timing over ardy. this is accomplished by elimination of the one-half clock cycle required to internally synchronize the ardy input signal. connecting srdy high will always assert the ready condition to the cpu. if this line is unused, it should be tied low to yield control to the ardy pin. lock 48 o lock output indicates that other system bus masters are not to gain control of the system bus while lock is active low. the lock signal is requested by the lock prefix instruction and is activated at the beginning of the first data cycle associated with the instruction following the lock prefix. it remains active until the completion of that instruction. no instruction prefetching will occur while lock is asserted. when executing more than one lock instruction, always make sure there are 6 bytes of code between the end of the first lock instruction and the start of the second lock instruction. lock is driven high for one clock during reset and then floated. s0 52 o bus cycle status s0 s2 are encoded to provide bus-transaction information: s1 53 o s2 54 o bus cycle status information s2 s1 s0 bus cycle initiated 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 passive (no bus cycle) the status pins float during hold. s2 may be used as a logical m/io indicator, and s1 as a dt/r indicator. note: pin names in parentheses apply to the 80188. 7 7
80186/80188 table 1. pin descriptions (continued) symbol pin type name and function no. hold 50 i hold indicates that another bus master is requesting the local bus. the hold input is active high. hold may be asynchronous with respect to the hlda 51 o processor clock. the processor will issue a hlda (high) in response to a hold request at the end of t 4 or t i . simultaneous with the issuance of hlda, the processor will float the local bus and control lines. after hold is detected as being low, the processor will lower hlda. when the processor needs to run another bus cycle, it will again drive the local bus and control lines. ucs 34 o upper memory chip select is an active low output whenever a memory reference is made to the defined upper portion (1k 256k block) of memory. this line is not floated during bus hold. the address range activating ucs is software programmable. lcs 33 o lower memory chip select is active low whenever a memory reference is made to the defined lower portion (1k 256k) of memory. this line is not floated during bus hold. the address range activating lcs is software programmable. mcs0 38 o mid-range memory chip select signals are active low when a memory reference is made to the defined mid-range portion of memory (8k 512k). mcs1 37 o these lines are not floated during bus hold. the address ranges activating mcs2 36 o mcs0 3 are software programmable. mcs3 35 o pcs0 25 o peripheral chip select signals 0 4 are active low when a reference is made to the defined peripheral area (64 kbyte i/o space). these lines are not pcs1 27 o floated during bus hold. the address ranges activating pcs0 4 are pcs2 28 o software programmable. pcs3 29 o pcs4 30 o pcs5 /a1 31 o peripheral chip select 5 or latched a1 may be programmed to provide a sixth peripheral chip select, or to provide an internally latched a1 signal. the address range activating pcs5 is software-programmable. pcs5 /a1 does not float during bus hold. when programmed to provide latched a1, this pin will retain the previously latched value during hold. pcs6 /a2 32 o peripheral chip select 6 or latched a2 may be programmed to provide a seventh peripheral chip select, or to provide an internally latched a2 signal. the address range activating pcs6 is software programmable. pcs6 /a2 does not float during bus hold. when programmed to provide latched a2, this pin will retain the previously latched value during hold. dt/r 40 o data transmit/receive controls the direction of data flow through an external data bus transceiver. when low, data is transferred to the processsor. when high, the processor places write data on the data bus. den 39 o data enable is provided as a data bus transceiver output enable. den is active low during each memory and i/o access. den is high whenever dt/r changes state. during reset, den is driven high for one clock, then floated. den also floats during hold. note: pin names in parentheses apply to the 80188. 8 8
80186/80188 functional description introduction the following functional description describes the base architecture of the 80186. the 80186 is a very high integration 16-bit microprocessor. it combines 15 20 of the most common microprocessor system components onto one chip while providing twice the performance of the standard 8086. the 80186 is ob- ject code compatible with the 8086/8088 microproc- essors and adds 10 new instruction types to the 8086/8088 instruction set. for more detailed information on the architecture, please refer to the 80c186xl/80c188xl user's manual. the 80186 and the 80186xl devices are functionally and register compatible. clock generator the processor provides an on-chip clock generator for both internal and external clock generation. the clock generator features a crystal oscillator, a divide- by-two counter, synchronous and asynchronous ready inputs, and reset circuitry. oscillator the oscillator circuit is designed to be used with a parallel resonant fundamental mode crystal. this is used as the time base for the processor. the crystal frequency selected will be double the cpu clock fre- quency. use of an lc or rc circuit is not recom- mended with this oscillator. if an external oscillator is used, it can be connected directly to the input pin x1 in lieu of a crystal. the output of the oscillator is not directly available outside the processor. the recom- mended crystal configuration is shown in figure 5. x 80186-10 (10 mhz) 20 272430 5 80186 (8 mhz) 16 figure 5. recommended crystal configuration intel recommends the following values for crystal se- lection parameters: temperature range: 0 to 70 c esr (equivalent series resistance): 30 x max c 0 (shunt capacitance of crystal): 7.0 pf max c 1 (load capacitance): 20 pf g 2pf drive level: 1 mw max clock generator the clock generator provides the 50% duty cycle processor clock for the processor. it does this by dividing the oscillator output by 2 forming the sym- metrical clock. if an external oscillator is used, the state of the clock generator will change on the fall- ing edge of the oscillator signal. the clkout pin provides the processor clock signal for use outside the device. this may be used to drive other system components. all timings are referenced to the output clock. ready synchronization the processor provides both synchronous and asyn- chronous ready inputs. in addition, the processor, as part of the integrated chip-select logic, has the capa- bility to program wait states for memory and peripheral blocks. reset logic the processor provides both a res input pin and a synchronized reset output pin for use with other system components. the res input pin is provided with hysteresis in order to facilitate power-on reset generation via an rc network. reset output is guaranteed to remain active for at least five clocks given a res input of at least six clocks. local bus controller the processor provides a local bus controller to generate the local bus control signals. in addition, it employs a hold/hlda protocol for relinquishing the local bus to other bus masters. it also provides outputs that can be used to enable external buffers and to direct the flow of data on and off the local bus. 9 9
80186/80188 memory/peripheral control the processor provides ale, rd , and wr bus con- trol signals. the rd and wr signals are used to strobe data from memory or i/o to the processor or to strobe data from the processor to memory or i/o. the ale line provides a strobe to latch the address when it is valid. the local bus controller does not provide a memory/i/o signal. if this is required, use the s2 signal (which will require external latching), make the memory and i/o spaces nonoverlapping, or use only the integrated chip-select circuitry. local bus arbitration the processor uses a hold/hlda system of local bus exchange. this provides an asynchronous bus exchange mechanism. this means multiple masters utilizing the same bus can operate at separate clock frequencies. the processor provides a single hold/hlda pair through which all other bus mas- ters may gain control of the local bus. external cir- cuitry must arbitrate which external device will gain control of the bus when there is more than one alter- nate local bus master. when the processor relin- quishes control of the local bus, it floats den ,rd , wr ,s0 s2 , lock , ad0 ad15 (ad0 ad7), a16 a19 (a8 a19), bhe (s7), and dt/r to allow another master to drive these lines directly. local bus controller and reset during reset the local bus controller will perform the following action: # drive den ,rd , and wr high for one clock cy- cle, then float. note: rd is also provided with an internal pull-up de- vice to prevent the processor from inadvertently entering queue status mode during reset. # drive s0 s2 to the inactive state (all high) and then float. # drive lock high and then float. # float ad0 15 (ad0 ad7), a16 19 (a8a19), bhe (s7), dt/r . # drive ale low (ale is never floated). # drive hlda low. peripheral architecture all of the integrated peripherals are controlled by 16-bit registers contained within an internal 256-byte control block. the control block may be mapped into either memory or i/o space. internal logic will recog- nize control block addresses and respond to bus cy- cles. during bus cycles to internal registers, the bus controller will signal the operation externally (i.e., the rd ,wr , status, address, data, etc., lines will be driv- en as in a normal bus cycle), but d 150 (d 70 ), srdy, and ardy will be ignored. the base address of the control block must be on an even 256-byte boundary (i.e., the lower 8 bits of the base address are all zeros). the control block base address is programmed by a 16-bit relocation register contained within the control block at offset feh from the base address of the control block. it provides the upper 12 bits of the base address of the control block. in addition to providing relocation information for the control block, the relocation register contains bits which place the interrupt controller into slave mode, and cause the cpu to interrupt upon encountering esc instructions. chip-select/ready generation logic the processor contains logic which provides programmable chip-select generation for both mem- ories and peripherals. in addition, it can be pro- grammed to provide ready (or wait state) genera- tion. it can also provide latched address bits a1 and a2. the chip-select lines are active for all memory and i/o cycles in their programmed areas, whether they be generated by the cpu or by the integrated dma unit. memory chip selects the processor provides 6 memory chip select out- puts for 3 address areas; upper memory, lower memory, and midrange memory. one each is provid- ed for upper memory and lower memory, while four are provided for midrange memory. upper memory cs the processor provides a chip select, called ucs , for the top of memory. the top of memory is usually used as the system memory because after reset the processor begins executing at memory location ffff0h. lower memory cs the processor provides a chip select for low memo- ry called lcs . the bottom of memory contains the interrupt vector table, starting at location 00000h. 10 10
80186/80188 the lower limit of memory defined by this chip select is always 0h, while the upper limit is programmable. by programming the upper limit, the size of the memory block is defined. mid-range memory cs the processor provides four mcs lines which are active within a user-locatable memory block. this block can be located within the 1-mbyte memory ad- dress space exclusive of the areas defined by ucs and lcs . both the base address and size of this memory block are programmable. peripheral chip selects the processor can generate chip selects for up to seven peripheral devices. these chip selects are ac- tive for seven contiguous blocks of 128 bytes above a programmable base address. the base address may be located in either memory or i/o space. sev- en cs lines called pcs0 6 are generated by the processor. pcs5 and pcs6 can also be pro- grammed to provide latched address bits a1 and a2. if so programmed, they cannot be used as peripher- al selects. these outputs can be connected directly to the a0 and a1 pins used for selecting internal registers of 8-bit peripheral chips. ready generation logic the processor can generate a ready signal inter- nally for each of the memory or peripheral cs lines. the number of wait states to be inserted for each peripheral or memory is programmable to provide 0 3 wait states for all accesses to the area for which the chip select is active. in addition, the proc- essor may be programmed to either ignore external ready for each chip-select range individually or to factor external ready with the integrated ready generator. chip select/ready logic and reset upon reset, the chip-select/ready logic will per- form the following actions: # all chip-select outputs will be driven high. # upon leaving reset, the ucs line will be pro- grammed to provide chip selects to a 1k block with the accompanying ready control bits set at 011 to insert 3 wait states in conjunction with ex- ternal ready (i.e., umcs resets to fffbh). # no other chip select or ready control registers have any predefined values after reset. they will not become active until the cpu accesses their control registers. both the pacs and mpcs registers must be accessed before the pcs lines will become active. dma channels the dma controller provides two independent dma channels. data transfers can occur between memo- ry and i/o spaces (e.g., memory to i/o) or within the same space (e.g., memory to memory or i/o to i/o). data can be transferred either in bytes or in words (80186 only) to or from even or odd addresses. each dma channel maintains both a 20-bit source and destination pointer which can be optionally in- cremented or decremented after each data transfer (by one or two depending on byte or word transfers). each data transfer consumes 2 bus cycles (a mini- mum of 8 clocks), one cycle to fetch data and the other to store data. this provides a maximum data transfer rate of 1.25 mword/sec or 2.5 mbytes/sec at 10 mhz (half of this rate for the 80188). dma channels and reset upon reset, the dma channels will perform the following actions: # the start/stop bit for each channel will be reset to stop. # any transfer in progress is aborted. timers the processor provides three internal 16-bit pro- grammable timers. two of these are highly flexible and are connected to four external pins (2 per timer). they can be used to count external events, time ex- ternal events, generate nonrepetitive waveforms, etc. the third timer is not connected to any external pins, and is useful for real-time coding and time de- lay applications. in addition, the third timer can be used as a prescaler to the other two, or as a dma request source. 11 11
80186/80188 timers and reset upon reset, the timers will perform the following actions: # all en (enable) bits are reset preventing timer counting. # for timers 0 and 1, the riu bits are reset to zero and the alt bits are set to one. this results in the timer out pins going high. interrupt controller the processor can receive interrupts from a number of sources, both internal and external. the internal interrupt controller serves to merge these requests on a priority basis, for individual service by the cpu. internal interrupt sources (timers and dma chan- nels) can be disabled by their own control registers or by mask bits within the interrupt controller. the interrupt controller has its own control register that sets the mode of operation for the controller. interrupt controller and reset upon reset, the interrupt controller will perform the following actions: # all sfnm bits reset to 0, implying fully nested mode. # all pr bits in the various control registers set to 1. this places all sources at lowest priority (level 111). # all ltm bits reset to 0, resulting in edge-sense mode. # all interrupt service bits reset to 0. # all interrupt request bits reset to 0. # all msk (interrupt mask) bits set to 1 (mask). # all c (cascade) bits reset to 0 (non-cascade). # all prm (priority mask) bits set to 1, implying no levels masked. # initialized to master mode. 12 12
80186/80188 272430 6 note: pin names in parenthesis apply to 80188. (1) bhe does not exist on the 80188, this is only required for a 16-bit data bus. figure 6. typical 80186/80188 computer 13 13
80186/80188 272430 7 note: pin names in parentheses apply to 80188. (1) bhe does not exist on the 80188, this is only required for a 16-bit data bus. figure 7. typical 80186/80188 multi-master bus interface 14 14
80186/80188 absolute maximum ratings * ambient temperature under bias 0 cto70 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 1.0v to a 7v power dissipation 3w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. d.c. characteristics (t a e 0 cto a 70 c, v cc e 5v g 10%) applicable to 8 mhz and 10 mhz devices. symbol parameter min max units test conditions v il input low voltage b 0.5 a 0.8 v v ih input high voltage 2.0 v cc a 0.5 v (all except x1 and (res ) v ih1 input high voltage (res ) 3.0 v cc a 0.5 v v ol output low voltage 0.45 v i a e 2.5 ma for s0 s2 i a e 2.0 ma for all other outputs v oh output high voltage 2.4 v i oa eb 400 m a i cc power supply current 600 * ma t a eb 40 c 550 ma t a e 0 c 415 ma t a ea 70 c i li input leakage current g 10 m a0v k v in k v cc i lo output leakage current g 10 m a 0.45v k v out k v cc v clo clock output low 0.6 v i a e 4.0 ma v cho clock output high 4.0 v i oa eb 200 m a v cli clock input low voltage b 0.5 0.6 v v chi clock input high voltage 3.9 v cc a 1.0 v c in input capacitance 10 pf c io i/o capacitance 20 pf * for extended temperature parts only. 15 15
80186/80188 a.c. characteristics (t a e 0 cto a 70 c, v cc e 5v g 10%) timing requirements all timings measured at 1.5v unless otherwise noted. symbol parameter 8 mhz 10 mhz units conditions test min max min max t dvcl data in setup (a/d) 20 15 ns t cldx data in hold (a/d) 10 8 ns t aryhch asynchronous ready 20 15 ns (ardy) active setup time (1) t arylcl ardy inactive setup time 35 25 ns t clarx ardy hold time 15 15 ns t arychl asynchronous ready 15 15 ns inactive hold time t srycl synchronous ready (srdy) 20 20 ns transition setup time (2) t clsry srdy transition hold 15 15 ns time (2) t hvcl hold setup (1) 25 20 ns t invch intr, nmi, test , tim in, 25 25 ns setup (1) t invcl drq0, drq1, setup (1) 25 20 ns master interface timing responses t clav address valid delay 5 55 5 44 ns c l e 20 pf200 pf all outputs t clax address hold 10 10 ns (except t cltmv ) @ 8 mhz and 10 mhz t claz address float delay t clax 35 t clax 30 ns t chcz command lines float delay 45 40 ns t chcv command lines valid delay 55 45 ns (after float) t lhll ale width t clcl b 35 t clcl b 30 ns t chlh ale active delay 35 30 ns t chll ale inactive delay 35 30 ns t llax address hold from ale t chcl b 25 t chcl b 20 ns inactive t cldv data valid delay 10 44 10 40 ns t cldox data hold time 10 10 ns t whdx data hold after wr t clcl b 40 t clcl b 34 ns t cvctv control active delay 1 5 50 5 40 ns t chctv control active delay 2 10 55 10 44 ns t cvctx control inactive delay 5 55 5 44 ns t cvdex den inactive delay 10 70 10 56 ns (non-write cycle) 1. to guarantee recognition at next clock. 2. to guarantee proper operation. 16 16
80186/80188 a.c. characteristics (t a e 0 cto a 70 c, v cc e 5v g 10%) (continued) master interface timing responses (continued) symbol parameter 8 mhz 10 mhz units conditions test min max min max t azrl address float to rd active 0 0 ns t clrl rd active delay 10 70 10 56 ns t clrh rd inactive delay 10 55 10 44 ns t rhav rd inactive to address t clcl b 40 t clcl b 40 ns active t clhav hlda valid delay 5 50 5 40 ns t rlrh rd width 2t clcl b 50 2t clcl b 46 ns t wlwh wr width 2t clcl b 40 2t clcl b 34 ns t avll address valid to ale low t clch b 25 t clch b 19 ns t chsv status active delay 10 55 10 45 ns t clsh status inactive delay 10 65 10 50 ns t cltmv timer output delay 60 48 ns 100 pf max @ 8&10mhz t clro reset delay 60 48 ns t chqsv queue status delay 35 28 ns t chdx status hold time 10 10 ns t avch address valid to clock high 10 10 ns t cllv lock valid/invalid delay 5 65 5 60 ns chip-select timing responses t clcsv chip-select active delay 66 45 ns t cxcsx chip-select hold from 35 35 ns command inactive t chcsx chip-select inactive delay 5 35 5 32 ns clkin requirements t ckin clkin period 62.5 250 50 250 ns t ckhl clkin fall time 10 10 ns 3.5 to 1.0v t cklh clkin rise time 10 10 ns 1.0 to 3.5v t clck clkin low time 25 20 ns 1.5v t chck clkin high time 25 20 ns 1.5v clkout timing (200 pf load) t cico clkin to clkout skew 50 25 ns t clcl clkout period 125 500 100 500 ns t clch clkout low time (/2 t clcl b 7.5 (/2 t clcl b 6.0 ns 1.5v t chcl clkout high time (/2 t clcl b 7.5 (/2 t clcl b 6.0 ns 1.5v t ch1ch2 clkout rise time 15 12 ns 1.0 to 3.5v t cl2cl1 clkout fall time 15 12 ns 3.5 to 1.0v 17 17
80186/80188 explanation of the ac symbols each timing symbol has from 5 to 7 characters. the first character is always a ``t'' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the charac- ters and what they stand for. a: address ary: asynchronous ready input c: clock output ck: clock input cs: chip select ct: control (dt/r , den ,...) d: data input de: den h: logic level high in: input (drq0, tim0, . . . ) l: logic level low or ale o: output qs: queue status (qs1, qs2) r: rd signal, reset signal s: status (s0 ,s1 ,s2 ) sry: synchronous ready input v: valid w: wr signal x: no longer a valid logic level z: float examples: t clav e time from clock low to address valid t chlh e time from clock high to ale high t clcsv e time from clock low to chip select valid 18 18
80186/80188 waveforms major cycle timing 272430 8 note: pin names in parentheses apply to the 80188. 19 19
80186/80188 waveforms (continued) major cycle timing (continued) notes: 272430 9 1. inta occurs one clock later in slave mode. 2. status inactive just prior to t 4 . 3. if latched a1 and a2 are selected instead of pcs5 and pcs6 , only t clcsv is applicable. 4. pin names in parentheses apply to the 80188. 20 20
80186/80188 waveforms (continued) 272430 10 272430 11 272430 12 21 21
80186/80188 waveforms (continued) 272430 13 272430 14 22 22
80186/80188 waveforms (continued) ready timing 272430 15 23 23
80186/80188 272430 16 note: pin names in parentheses apply to the 80188. 24 24
80186/80188 waveforms (continued) 272430 17 express the intel express system offers enhancements to the operational specifications of the microprocessor. express products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. the express program includes the commercial standard temperature range with burn-in and an ex- tended temperature range without burn-in. with the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 cto a 70 c. with the ex- tended temperature range option, operational char- acteristics are guaranteed over the range of b 40 c to a 85 c. the optional burn-in is dynamic, for a minimum time of 160 hours at a 125 c with v cc e 5.5v g 0.25v, following guidelines in mil-std-883, method 1015. package types and express versions are identified by a one- or two-letter prefix to the part number. the prefixes are listed in table 2. all a.c. and d.c. speci- fications not mentioned in this section are the same for both commercial and express parts. table 2. prefix identification prefix package temperature burn-in type range a pga commercial no n plcc commercial no r lcc commercial no ta pga extended no qa pga commercial yes qr lcc commercial yes note: not all package/temperature range/speed combinations are available. 25 25
80186/80188 execution timings a determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. the fol- lowing instruction timings represent the minimum ex- ecution time in clock cycles for each instruction. the timings given are based on the following assump- tions: # the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # no wait states or bus holds occur. # all word-data is located on even-address bound- aries. all instructions which involve memory accesses can also require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (biu) and execution unit. all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. the 80186 has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. therefore, actual program execution time will not be substantially greater than that derived from adding the instruction timings shown. the 80188 is noticeably limited in its performance relative to the execution unit. a sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. therefore, actual program execution time may be substantially greater than that derived from adding the instruction timings shown. 26 26
80186/80188 instruction set summary 80186 80188 function format clock clock comments cycles cycles data transfer mov e move: register to register/memory 1000100w modreg r/m 2/12 2/12 * register/memory to register 1000101w modreg r/m 2/9 2/9 * immediate to register/memory 1100011w mod000 r/m data data if w e 1 12/13 12/13 8/16-bit immediate to register 1011w reg data data if w e 1 3/4 3/4 8/16-bit memory to accumulator 1010000w addr-low addr-high 8 8 * accumulator to memory 1010001w addr-low addr-high 9 9 * register/memory to segment register 10001110 mod0reg r/m 2/9 2/13 segment register to register/memory 10001100 mod0reg r/m 2/11 2/15 push e push: memory 11111111 mod110 r/m 16 20 register 01010 reg 10 14 segment register 000reg110 9 13 immediate 011010s0 data data if s e 01014 pusha e push all 01100000 36 68 pop e pop: memory 10001111 mod000 r/m 20 24 register 01011 reg 10 14 segment register 000reg111 (reg i 01) 8 12 popa e popall 01100001 51 83 xchg e exchange: register/memory with register 1000011w modreg r/m 4/17 4/17 * register with accumulator 10010 reg 3 3 in e input from: fixed port 1110010w port 10 10 * variable port 1110110w 8 8 * out e output to: fixed port 1110011w port 9 9 * variable port 1110111w 7 7 * xlat e translate byte to al 11010111 11 15 lea e load ea to register 10001101 modreg r/m 6 6 lds e load pointer to ds 11000101 modreg r/m (mod i 11) 18 26 les e load pointer to es 11000100 modreg r/m (mod i 11) 18 26 lahf e load ah with flags 10011111 2 2 sahf e store ah into flags 10011110 3 3 pushf e push flags 10011100 9 13 popf e pop flags 10011101 8 12 shaded areas indicate instructions not available in 8086, 8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 27 27
80186/80188 instruction set summary (continued) 80186 80188 function format clock clock comments cycles cycles data transfer (continued) segment e segment override: cs 00101110 2 2 ss 00110110 2 2 ds 00111110 2 2 es 00100110 2 2 arithmetic add e add: reg/memory with register to either 000000dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod000 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0000010w data data if w e 1 3/4 3/4 8/16-bit adc e add with carry: reg/memory with register to either 000100dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod010 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0001010w data data if w e 1 3/4 3/4 8/16-bit inc e increment: register/memory 1111111w mod000 r/m 3/15 3/15 * register 01000 reg 3 3 sub e subtract: reg/memory and register to either 001010dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod101 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0010110w data data if w e 1 3/4 3/4 8/16-bit sbb e subtract with borrow: reg/memory and register to either 000110dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod011 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0001110w data data if w e 1 3/4 3/4 8/16-bit dec e decrement register/memory 1111111w mod001 r/m 3/15 3/15 * register 01001 reg 3 3 cmp e compare: register/memory with register 0011101w modreg r/m 3/10 3/10 * register with register/memory 0011100w modreg r/m 3/10 3/10 * immediate with register/memory 100000sw mod111 r/m data data if s w e 01 3/10 3/10 * immediate with accumulator 0011110w data data if w e 1 3/4 3/4 8/16-bit neg e change sign register/memory 1111011w mod011 r/m 3/10 3/10 * aaa e ascii adjust for add 00110111 8 8 daa e decimal adjust for add 00100111 4 4 aas e ascii adjust for subtract 00111111 7 7 das e decimal adjust for subtract 00101111 4 4 mul e multiply (unsigned): 1111011w mod100 r/m register-byte 2628 2628 register-word 3537 3537 memory-byte 3234 3234 memory-word 4143 4143 * shaded areas indicate instructions not available in 8086, 8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 28 28
80186/80188 instruction set summary (continued) 80186 80188 function format clock clock comments cycles cycles arithmetic (continued) imul e integer multiply (signed): 1111011w mod101 r/m register-byte 2528 2528 register-word 3437 3437 memory-byte 3134 3134 memory-word 4043 4043 * imul e integer immediate multiply 011010s1 modreg r/m data data if s e 0 2225/ 2225/ (signed) 2932 2932 div e divide (unsigned): 1111011w mod110 r/m register-byte 29 29 register-word 38 38 memory-byte 35 35 memory-word 44 44 * idiv e integer divide (signed): 1111011w mod111 r/m register-byte 4452 4452 register-word 5361 5361 memory-byte 5058 5058 memory-word 5967 5967 * aam e ascii adjust for multiply 11010100 00001010 19 19 aad e ascii adjust for divide 11010101 00001010 15 15 cbw e convert byte to word 10011000 2 2 cwd e convert word to double word 10011001 4 4 logic shift/rotate instructions: register/memory by 1 1101000w modtttr/m 2/15 2/15 register/memory by cl 1101001w modtttr/m 5 a n/17 a n5 a n/17 a n register/memory by count 1100000w modtttr/m count 5 a n/17 a n5 a n/17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shl/sal 101 shr 111 sar and e and: reg/memory and register to either 001000dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod100 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0010010w data data if w e 1 3/4 3/4 8/16-bit test e and function to flags, no result: register/memory and register 1000010w modreg r/m 3/10 3/10 * immediate data and register/memory 1111011w mod000 r/m data data if w e 1 4/10 4/10 * immediate data and accumulator 1010100w data data if w e 1 3/4 3/4 8/16-bit or e or: reg/memory and register to either 000010dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod001 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0000110w data data if w e 1 3/4 3/4 8/16-bit shaded areas indicate instructions not available in 8086, 8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 29 29
80186/80188 instruction set summary (continued) 80186 80188 function format clock clock comments cycles cycles logic (continued) xor e exclusive or: reg/memory and register to either 001100dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod110 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0011010w data data if w e 1 3/4 3/4 8/16-bit not e invert register/memory 1111011w mod010 r/m 3/10 3/10 * string manipulation movs e move byte/word 1010010w 14 14 * cmps e compare byte/word 1010011w 22 22 * scas e scan byte/word 1010111w 15 15 * lods e load byte/wd to al/ax 1010110w 12 12 * stos e store byte/wd from al/ax 1010101w 10 10 * ins e input byte/wd from dx port 0110110w 14 14 outs e output byte/wd to dx port 0110111w 14 14 repeated by count in cx (rep/repe/repz/repne/repnz) movs e move string 11110010 1010010w 8 a 8n 8 a 8n * cmps e compare string 1111001z 1010011w 5 a 22n 5 a 22n * scas e scan string 1111001z 1010111w 5 a 15n 5 a 15n * lods e load string 11110010 1010110w 6 a 11n 6 a 11n * stos e store string 11110010 1010101w 6 a 9n 6 a 9n * ins e input string 11110010 0110110w 8 a 8n 8 a 8n * outs e output string 11110010 0110111w 8 a 8n 8 a 8n * control transfer call e call: direct within segment 11101000 disp-low disp-high 15 19 register/memory 11111111 mod010 r/m 13/19 17/27 indirect within segment direct intersegment 10011010 segment offset 23 31 segment selector indirect intersegment 11111111 mod011 r/m (mod i 11) 38 54 jmp e unconditional jump: short/long 11101011 disp-low 14 14 direct within segment 11101001 disp-low disp-high 14 14 register/memory 11111111 mod100 r/m 11/17 11/21 indirect within segment direct intersegment 11101010 segment offset 14 14 segment selector indirect intersegment 11111111 mod101 r/m (mod i 11) 26 34 shaded areas indicate instructions not available in 8086, 8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 30 30
80186/80188 instruction set summary (continued) 80186 80188 function format clock clock comments cycles cycles control transfer (continued) ret e return from call: within segment 11000011 16 20 within seg adding immed to sp 11000010 data-low data-high 18 22 intersegment 11001011 22 30 intersegment adding immediate to sp 11001010 data-low data-high 25 33 je/jz e jump on equal/zero 01110100 disp 4/13 4/13 jmp not jl/jnge e jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/jmp jle/jng e jump on less or equal/not greater 01111110 disp 4/13 4/13 taken jb/jnae e jump on below/not above or equal 01110010 disp 4/13 4/13 jbe/jna e jump on below or equal/not above 01110110 disp 4/13 4/13 jp/jpe e jump on parity/parity even 01111010 disp 4/13 4/13 jo e jump on overflow 01110 000 disp 4/13 4/13 js e jump on sign 01111000 disp 4/13 4/13 jne/jnz e jump on not equal/not zero 01110101 disp 4/13 4/13 jnl/jge e jump on not less/greater or equal 01111101 disp 4/13 4/13 jnle/jg e jump on not less or equal/greater 01111111 disp 4/13 4/13 jnb/jae e jump on not below/above or equal 01110011 disp 4/13 4/13 jnbe/ja e jump on not below or equal/above 01110111 disp 4/13 4/13 jnp/jpo e jump on not par/par odd 01111011 disp 4/13 4/13 jno e jump on not overflow 01110001 disp 4/13 4/13 jns e jump on not sign 01111001 disp 4/13 4/13 jcxz e jump on cx zero 11100011 disp 5/15 5/15 loop e loop cx times 11100010 disp 6/16 6/16 loop not loopz/loope e loop while zero/equal 11100001 disp 6/16 6/16 taken/loop loopnz/loopne e loop while not zero/equal 11100000 disp 6/16 6/16 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 19 l e 1 25 29 l l 1 22 a 16(n b 1) 26 a 20(n b 1) leave e leave procedure 11001001 8 8 int e interrupt: type specified 11001101 type 47 47 type 3 11001100 45 45 if int. taken/ into e interrupt on overflow 11001110 48/4 48/4 if int. not taken iret e interrupt return 11001111 28 28 bound e detect value out of range 01100010 modreg r/m 3335 3335 shaded areas indicate instructions not available in 8086, 8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 31 31
80186/80188 instruction set summary (continued) 80186 80188 function format clock clock comments cycles cycles processor control clc e clear carry 11111000 2 2 cmc e complement carry 11110101 2 2 stc e set carry 11111001 2 2 cld e clear direction 11111100 2 2 std e set direction 11111101 2 2 cli e clear interrupt 11111010 2 2 sti e set interrupt 11111011 2 2 hlt e halt 11110100 2 2 wait e wait 10011011 6 6 if test e 0 lock e bus lock prefix 11110000 2 3 esc e processor extension escape 11011ttt modlll r/m 6 6 (ttt lll are opcode to processor extension) nop e no operation 10010000 3 3 shaded areas indicate instructions not available in 8086, 8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. footnotes the effective address (ea) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as reg field if mod e 00 then disp e 0 * , disp-low and disp-high are absent if mod e 01 then disp e disp-low sign-extended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high: disp-low if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp * if r/m e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) * except if mod e 00 and r/m e 110 then ea e disp-high: disp-low. ea calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: reg segment register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table: 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register. the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment, which may not be overridden. 32 32
80186/80188 revision history this data sheet replaces the following data sheets: 210706-011 80188 210451-011 80186 33 33

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