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101 innovation drive san jose, ca 95134 www.altera.com stratix ii gx device handbook, volume 1 siigx5v1-4.4
copyright ? 2009 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time with out notice. altera assumes no responsibility or liabil- ity arising out of the application or use of any information, produc t, or service described herein except as expressly agreed to in writing by al tera corporation. altera customers are advised to obtain the latest ver- sion of device specifications before relying on an y published information and before placing orders for products or services . ii altera corporation
altera corporation iii contents section i. stratix ii gx device data sheet chapter 1. introduction features ....................................................................................................................... ............................ 1?1 referenced document ............................................................................................................ ............... 1?5 document revision history ...................................................................................................... ........... 1?5 chapter 2. stratix ii gx architecture transceivers ................................................................................................................... ......................... 2?1 transmitter path ............................................................................................................... ................ 2?4 receiver path .................................................................................................................. ................. 2?14 loopback modes ................................................................................................................. ........... 2?30 transceiver clocking ........................................................................................................... .......... 2?35 other transceiver features ..................................................................................................... ...... 2?41 logic array blocks ............................................................................................................. ........... ...... 2?44 lab interconnects .............................................................................................................. ............ 2?45 lab control signals ............................................................................................................ ........... 2?46 adaptive logic modules ......................................................................................................... ........... 2?48 alm operating modes ............................................................................................................ ..... 2?50 arithmetic mode ................................................................................................................ ............ 2?55 shared arithmetic mode ......................................................................................................... ...... 2?58 shared arithmetic chain ........................................................................................................ ....... 2?60 register chain ................................................................................................................. ................ 2?61 clear and preset logic control ................................................................................................. ... 2?63 multitrack interconnect ........................................................................................................ ............. 2?63 trimatrix memory ............................................................................................................... ................ 2?69 m512 ram block ................................................................................................................. ........... 2?70 m4k ram blocks ................................................................................................................. .......... 2?73 m-ram block .................................................................................................................... ............. 2?75 digital signal processing (dsp) block .......................................................................................... .... 2?81 modes of operation ............................................................................................................. .......... 2?85 dsp block interface ............................................................................................................ ............ 2?85 plls and clock networks ........................................................................................................ .......... 2?89 global and hierarchical clocking ............................................................................................... .2?89 enhanced and fast plls ......................................................................................................... ...... 2?97 enhanced plls .................................................................................................................. ........... 2?109 fast plls ...................................................................................................................... ............ ...... 2?109 i/o structure .................................................................................................................. ........... ......... 2?110 double data rate i/o pins .................................... .................................................................. ... 2?118 external ram interfacing ....................................................................................................... .... 2?122
iv altera corporation contents stratix ii gx device handbook, volume 1 programmable drive strength ................................................................................................... 2 ?124 open-drain output .............................................................................................................. ........ 2?125 bus hold ....................................................................................................................... ........... ...... 2?125 programmable pull-up resistor ................................................................................................ 2? 126 advanced i/o standard support .............................................................................................. 2?12 6 on-chip termination ............................................................................................................ ...... 2?130 multivolt i/o interface ........................................................................................................ ....... 2?133 high-speed differential i/o with dpa su pport ................ ........... ............ ........... ........... ............. 2?136 dedicated circuitry with dpa support ........ ............ ........... ........... ........... ......... ......... ............. 2?138 fast pll and channel layout .................................................................................................... 2?141 referenced documents ............................................ ............................................................... .......... 2?142 document revision history ...................................................................................................... ....... 2?143 chapter 3. configuration & testing ieee std. 1149.1 jtag boundary -scan support ...... ........... ........... ............ ........... ........... ........... ...... 3?1 signaltap ii embedded logic analyzer ........................................................................................... . 3?3 configuration .................................................................................................................. ....................... 3?3 operating modes ................................................................................................................ .............. 3?4 configuration schemes .......................................................................................................... ......... 3?6 device security using configuration bitstream encryp tion ..................................................... 3?7 device configuration data decompression ................... .............................................................. 3?7 remote system upgrades ......................................................................................................... ...... 3?8 configuring stratix ii gx fpgas with jrunner .......................................................................... 3?8 programming serial configuration de vices with srunner ....................................................... 3?9 configuring stratix ii fpgas with the microblaster driver ..................................................... 3?9 pll reconfiguration ............................................................................................................ ............ 3?9 temperature sensing diode (tsd) ................................................................................................ ... 3?10 automated single event upset (seu) dete ction ............ ........... ........... ........... ........... ............ ........ 3?12 custom-built circuitry ......................................................................................................... ......... 3?12 software interface ............................................................................................................. .............. 3?12 referenced documents ............................................ ............................................................... ............ 3?13 document revision history ...................................................................................................... ......... 3?13 chapter 4. dc and switching characteristics operating conditions ........................................................................................................... ................ 4?1 absolute maximum ratings ....................................................................................................... .... 4?1 recommended operating conditions ........ .................................................................................. 4?2 transceiver block characteristics .............................................................................................. .... 4?3 dc electrical characteristics .................................................................................................. ...... 4?42 i/o standard specifications .................................................................................................... ..... 4?43 bus hold specifications ........................................................................................................ ......... 4?56 on-chip termination specifications ............................. .............................................................. 4? 56 pin capacitance ................................................................................................................ .............. 4?58 power consumption .............................................................................................................. ............. 4?59 timing model ................................................................................................................... ............ ........ 4?59 preliminary and final timing ................................................................................................... ... 4?59 i/o timing measurement methodology .................................................................................... 4?60
altera corporation v stratix ii gx device handbook, volume 1 contents internal timing parameters ..................................................................................................... ..... 4?69 stratix ii gx clock timing parameters ....................................................................................... 4?76 clock network skew adders ...................................................................................................... .4?81 ioe programmable delay ......................................................................................................... .... 4?82 default capacitive loading of different i/o standards . ......................................................... 4?83 i/o delays ..................................................................................................................... .................. 4?84 maximum input and output clock toggle rate ....................................................................... 4?98 duty cycle distortion .......................................................................................................... ............. 4?118 dcd measurement techniques ................................................................................................. 4?11 8 high-speed i/o specifications .................................................................................................. ...... 4?126 pll timing specifications ...................................................................................................... .......... 4?130 external memory interfac e specifications ..................................................................................... 4? 132 jtag timing specifications ..................................................................................................... ........ 4?134 referenced documents ............................................ ............................................................... .......... 4?136 document revision history ...................................................................................................... ....... 4?137 chapter 5. reference and ordering information device pin-outs ................................................................................................................ ..................... 5?1 ordering information ........................................................................................................... ................ 5?1 referenced documents ............................................ ............................................................... .............. 5?2 document revision history ...................................................................................................... ........... 5?2
vi altera corporation contents stratix ii gx device handbook, volume 1
altera corporation vii chapter revision dates the chapters in this book, stratix ii gx device handbook, volume 1 , were revised on the following dates. where chapters or groups of chapters ar e available separately, part numbers are listed. chapter 1. introduction revised: october 2007 part number: siigx51001-1.6 chapter 2. stratix ii gx architecture revised: october 2007 part number: siigx51003-2.2 chapter 3. configuration & testing revised: october 2007 part number: siigx51005-1.4 chapter 4. dc and switching characteristics revised: june 2009 part number: siigx51006-4.6 chapter 5. reference and ordering information revised: august 2007 part number: siigx51007-1.3
viii altera corporation chapter revision dates stratix ii gx device handbook, volume 1
altera corporation ix preliminary about this handbook this handbook provides comprehe nsive information about the altera ? stratix ii gx family of devices. how to contact altera for the most up-to-date information about altera products, refer to the following table. typographic conventions this document uses the typogr aphic conventions shown below. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature email www.altera.com/literature altera literature services website literature@altera.com non-technical support (general) (software licensing) email nacomp@altera.com email authorization@altera.com note to table: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board design.
x altera corporation preliminary typographic conventions stratix ii gx device handbook, volume 1 italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: , .pof file. initial capital letters keyboard keys and menu names ar e shown with initial capital letters. examples: delete key, the options menu. ?subheading title? references to sections within a document and titles of on-line help topics are shown in quotation marks. example: ?typographic conventions.? courier type signal and port names are shown in lowercase courier type. examples: data1 , tdi , input. active-low signals are denoted by suffix n , e.g., resetn . anything that must be typed exactly as it appears is shown in courier type. for example: c:\qdesigns\tutorial\chiptrip.gdf . also, sections of an actual file, such as a report file, refere nces to parts of files (e.g., the ahdl keyword subdesign ), as well as logic function names (e.g., tri ) are shown in courier. 1., 2., 3., and a., b., c., etc. numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ? bullets are used in a list of items when the sequence of the items is not important. v the checkmark indicates a procedur e that consists of one step only. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or the user?s work. w a warning calls attention to a condition or possible situation that can cause injury to the user. r the angled arrow indicates you should press the enter key. f the feet direct you to more information on a particular topic. visual cue meaning
altera corporation section i?1 section i. stratix ii gx device data sheet this section provides designers with the data sheet specifications for stratix ? ii gx devices. they contai n feature definitions of the transceivers, internal architecture, configuration, and jtag boundary-scan testing information, dc operating conditions, ac timing parameters, a reference to power co nsumption, and ordering information for stratix ii gx devices. this section includes the following chapters: chapter 1, introduction chapter 2, stratix ii gx architecture chapter 3, configuration & testing chapter 4, dc and switching characteristics chapter 5, reference and ordering information revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section i?2 altera corporation stratix ii gx device data sheet stratix ii gx device handbook, volume 1
altera corporation 1?1 october 2007 1. introduction the stratix ? ii gx family of devices is altera?s third generation of fpgas to combine high-speed serial transceivers with a scalable, high-performance logic array. stratix ii gx devices include 4 to 20 high-speed transceiver channels, each incorporating clock and data recovery unit (cru) technology and embedded serdes capability at data rates of up to 6.375 gigabits per second (gbps). the transceivers are grouped into four-channel transceiver blocks and are designed for low power consumption and small die size. the stratix ii gx fpga technology is built upon the stratix ii architecture and offers a 1.2-v logic array with unmatched performance, flexibility, and time-to-market capabilities. this scalable, high -performance architecture makes stratix ii gx devices ideal for hi gh-speed backpl ane interface, chip-to-chip, and communications protocol-bridging applications. features this section lists the stratix ii gx device features. main device features: trimatrix memory consisting of three ram block sizes to implement true dual-port memory and first-in first-out (fifo) buffers with performance up to 550 mhz up to 16 global clock networks with up to 32 regional clock networks per device region high-speed dsp blocks provide dedicated implementation of multipliers (at up to 450 mhz), mul tiply-accumulate functions, and finite impulse response (fir) filters up to four enhanced plls per de vice provide spread spectrum, programmable bandwidth, clock switch-over, real-time pll reconfiguration, and advanced multiplication and phase shifting support for numerous single-ended and differential i/o standards high-speed source-synchronous differential i/o support on up to 71 channels support for source-synchronous bus standards, including spi-4 phase 2 (pos-phy level 4), sfi- 4.1, xsbi, utopia iv, npsi, and csix-l1 support for high-speed external memory, including quad data rate (qdr and qdrii) sram, double data rate (ddr and ddr2) sdram, and single data rate (sdr) sdram siigx51001-1.6
1?2 altera corporation stratix ii gx device handbook, volume 1 october 2007 features support for multiple intellectual property megafunctions from altera ? megacore ? functions and altera megafunction partners program (ampp sm ) megafunctions support for design security using configuration bitstream encryption support for remote configuration updates transceiver block features: high-speed serial transceiver channels with clock data recovery (cdr) provide 600-megabits pe r second (mbps) to 6.375-gbps full-duplex transceiver operation per channel devices available with 4, 8, 12, 16, or 20 high-speed serial transceiver channels providing up to 255 gbps of serial bandwidth (full duplex) dynamically programmable voltage output differential (v od ) and pre-emphasis settings for improved signal integrity support for cdr-based serial pr otocols, includin g pci express, gigabit ethernet, sdi, altera?s seriallite ii, xaui, cei-6g, cpri, serial rapidio, sonet/sdh dynamic reconfiguration of tran sceiver channels to switch between multiple protocols and data rates individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation adaptive equalization (aeq) capability at the receiver to compensate for changing link characteristics selectable on-chip termination resistors (100, 120, or 150 ) for improved signal integrity on a variety of transmission media programmable transceiver-to-fpga interface with support for 8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer 1.2- and 1.5-v pseudo current mode logic (pcml) for 600 mbps to 6.375 gbps (ac coupling) receiver indicator for loss of signal (available only in pipe mode) built-in self test (bist) hot socketing for hot plug-in or hot swap and power sequencing support without th e use of external devices rate matcher, byte-reordering, bit-reordering, pattern detector, and word aligner support programmable patterns dedicated circuitry that is co mpliant with pipe, xaui, and gige built-in byte ordering so that a frame or packet always starts in a known byte lane transmitters with two pll inpu ts for each transceiver block with independent cloc k dividers to provide varying clock rates on each of its transmitters
altera corporation 1?3 october 2007 stratix ii gx device handbook, volume 1 introduction 8b/10b encoder and decoder perf orm 8-bit to 10-bit encoding and 10-bit to 8-bit decoding phase compensation fifo buff er performs clock domain translation between the transcei ver block and the logic array receiver fifo resynchronizes the received data with the local reference clock channel aligner compliant with xaui f certain transceiver blocks ca n be bypassed. refer to the stratix ii gx architecture chapter in volume 1 of the stratix ii gx de vice handbook for more details. table 1?1 lists the stratix ii gx device features. table 1?1. stratix ii gx devi ce features (part 1 of 2) feature ep2sgx30c/d ep2s gx60c/d/e ep2sgx90e/f ep2sgx130/g cd cd e e f g alms 13,552 24,176 36,384 53,016 equivalent les 33,880 60,440 90,960 132,540 transceiver channels 48 4 812 12 16 20 transceiver data rate 600 mbps to 6.375 gbps 600 mbps to 6.375 gbps 600 mbps to 6.375 gbps 600 mbps to 6.375 gbps source-synchronous receive channels (1) 31 31 31 42 47 59 73 source-synchronous transmit channels 29 29 29 42 45 59 71 m512 ram blocks (32 18 bits) 202 329 488 699 m4k ram blocks (128 36 bits) 144 255 408 609 m-ram blocks (4k 144 bits) 12 46 total ram bits 1,369,728 2,544,192 4,520,448 6,747,840 embedded multipliers (18 18) 64 144 192 252 dsp blocks 16 36 48 63 plls 4 4 4 8 8 8 maximum user i/o pins 361 364 364 534 558 650 734
1?4 altera corporation stratix ii gx device handbook, volume 1 october 2007 features stratix ii gx devices are availabl e in space-saving fineline bga packages (refer to table 1?2 ). all stratix ii gx devices support vertical migration within the same package. vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given pa ckage across device densities. for i/o pin migration across densities, you must cross-reference the available i/o pins using the device pin-outs for all planned dens ities of a given package type to identify wh ich i/o pins are migratable. table 1?3 lists the stratix ii gx device package sizes. package 780-pin fineline bga 780-pin fineline bga 1,152-pin fineline bga 1,152-pin fineline bga 1,508-pin fineline bga 1,508-pin fineline bga note to ta b l e 1 ? 1 : (1) includes two sets of dual-purpose differential pins that can be used as two additional channels for the differential receiver or differen tial clock inputs. table 1?1. stratix ii gx devi ce features (part 2 of 2) feature ep2sgx30c/d ep2s gx60c/d/e ep2sgx90e/f ep2sgx130/g cd cd e e f g table 1?2. stratix ii gx package options (pin counts and transceiver channels) device transceiver channels source-synchronous channels maximum user i/o pin count receive (1) transmit 780-pin fineline bga (29 mm) 1,152-pin fineline bga (35 mm) 1,508-pin fineline bga (40 mm) ep2sgx30c 4 31 29 361 ? ? ep2sgx60c 4 31 29 364 ? ? ep2sgx30d 8 31 29 361 ? ? ep2sgx60d 8 31 29 364 ? ? ep2sgx60e 12 42 42 ? 534 ? ep2sgx90e 12 47 45 ? 558 ? ep2sgx90f 16 59 59 ? ? 650 ep2sgx130g 20 73 71 ? ? 734 note to ta b l e 1 ? 2 : (1) includes two differential clock inputs that can also be us ed as two additional channels for the differential receiver.
altera corporation 1?5 october 2007 stratix ii gx device handbook, volume 1 introduction referenced document this chapter references the following document: stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook document revision history table 1?4 shows the revision history for this chapter. table 1?3. stratix ii gx fineline bga package sizes dimension 780 pins 1,152 pins 1,508 pins pitch (mm) 1.00 1.00 1.00 area (mm 2 ) 841 1,225 1,600 length width (mm mm) 29 29 35 35 40 40 table 1?4. document revision history date and document version changes made summary of changes october 2007, v1.6 updated ?features? section. minor text edits. august 2007, v1.5 added ?referenced documents? section. minor text edits. february 2007, v1.4 changed 622 mbps to 600 mbps on page 1-2 and table 1?1. deleted ?dc coupling? from the transceiver block features list. changed 4 to 6 in the plls row (columns 3 and 4) of table 1?1. added the ?document revision history? section to this chapter. added support information for the stratix ii gx device. june 2006, v1.3 updated table 1?2. april 2006, v1.2 updated table 1?1. updated table 1?2. updated numbers for receiver channels and user i/o pin counts in table 1?2. february 2006, v1.1 updated table 1?1. october 2005 v1.0 added chapter to the stratix ii gx device handbook .
1?6 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history
altera corporation 2?1 october 2007 2. stratix ii gx architecture transceivers stratix ? ii gx devices incorporate dedicated embedded circuitry on the right side of the device, which contai ns up to 20 high-speed 6.375-gbps serial transceiver channels. each st ratix ii gx transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. the transceivers deliver bidirectional point-to-point data transmissions, with up to 51 gbps (6.375 gbps per channel) of full-duplex data tran smission per transceiver block. figure 2?1 shows the function blocks that make up a transceiver channel within the stratix ii gx device. figure 2?1. stratix ii gx tr ansceiver block diagram notes to figure 2?1 : (1) n represents the number of bits in each word that need to be serialized by the transmitter portion of the pma or have been deserialized by the re ceiver portion of the pma. n = 8, 10, 16, or 20. (2) m represents the number of bits in the word that pass be tween the fpga logic and the pcs portion of the transceiver. m = 8, 10, 16, 20, 32, or 40. transceivers within each block are in dependent and have their own set of dividers. therefore, each transceiver can operate at different frequencies. each block can select from two refe rence clocks to provide two clock domains that each transceiver can select from. deserializer serializer word aligner 8b/10b decoder xaui lane deskew byte deserializer 8b/10b encoder phase compensation fifo buffer reference clock reference clock byte serializer phase compensation fifo buffer rate matcher pcs digital section fpga fabric pma analog section byte ordering receiver pll transmitter pll clock recovery unit m n n m (1) (2) (2) (1) siigx51003-2.2
2?2 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers there are up to 20 transceiver channels available on a single stratix ii gx device. table 2?1 shows the number of tran sceiver channels and their serial bandwidth for ea ch stratix ii gx device. figure 2?2 shows the elements of the transc eiver block, including the four transceiver channels, supporting logic, and i/o buffers. each transceiver channel consists of a receiver and transmitter. the supporting logic contains two transmitter plls to genera te the high-speed clock(s) used by the four transmitters wi thin that block. each of the four transmitter channels has its own individual clock divider. the four receiver plls within each transceiver block generate four recovered clocks. the transceiver channels can be configured in one of the following functional modes: pci express (pipe) oif cei phy interface sonet/sdh gigabit ethernet (gige) xaui basic (600 mbps to 3.125 gbps sing le-width mode and 1 gbps to 6.375 gbps double-width mode) sdi (hd, 3g) cpri (614 mbps, 1228 mbps, 2456 mbps) serial rapidio (1.25 gbps, 2.5 gbps, 3.125 gbps) table 2?1. stratix ii gx transceiver channels device number of transceiver channels serial bandwidth (full duplex) ep2sgx30c 4 51 gbps ep2sgx60c 4 51 gbps ep2sgx30d 8 102 gbps ep2sgx60d 8 102 gbps ep2sgx60e 12 153 gbps ep2sgx90e 12 153 gbps ep2sgx90f 16 204 gbps ep2sgx130g 20 255 gbps
altera corporation 2?3 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?2. elements of t he transceiver block each stratix ii gx transceiver channe l consists of a transmitter and receiver. the transceivers are grouped in four and share pll resources. each transmitter has access to one of two plls. the transmitter contains the following: transmitter phase compensation fi rst-in first-out (fifo) buffer byte serializer (optional) 8b/10b encoder (optional) serializer (parallel-to-serial converter) transmitter differential output buffer the receiver contains the following: receiver differential input buffer receiver lock detector and run length checker clock recovery unit (cru) deserializer pattern detector word aligner lane deskew rate matcher (optional) 8b/10b decoder (optional) byte deserializer (optional) byte ordering receiver phase compensation fifo buffer designers can preset stratix ii gx transceiver functions using the quartus ? ii software. in addition, pre-emphasis, equalization, and differential output voltage (v od ) are dynamically programmable. each stratix ii gx transceiver channel supports various loopback modes and is channel 1 channel 0 channel 2 supporting blocks (plls, state machines, programming) channel 3 rx1 tx1 rx0 tx0 rx2 tx2 rx3 tx3 refclk_1 refclk_0 transceiver block stratix ii gx logic array
2?4 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers capable of built-in self test (bis t) generation and verification. the alt2gxb megafunction in the quartus ii software provides a step-by-step menu selection to configure the transceiver. figure 2?1 shows the block diagram for the stratix ii gx transceiver channel. stratix ii gx transceivers provide pcs and pma implementations for all supported protocols. th e pcs portion of the transceiver consists of th e word aligner, lane deskew fifo buffer, rate matcher fifo buffer, 8b/10b encoder and decoder, byte serializer and deserializer, byte ordering, and phase compensation fifo buffers. each stratix ii gx transceiver channel is also capable of bist generation and verification in addition to vari ous loopback modes. the pma portion of the transceiver consists of the seri alizer and deserializer, the cru, and the high-speed differential transceive r buffers that contain pre-emphasis, programmable on-chip termination (oct), programmable voltage output differential (v od ), and equalization. transmitter path this section describes the data path th rough the stratix ii gx transmitter. the stratix ii gx transmitter contains the following modules: transmitter plls access to one of two plls transmitter logic array interface transmitter phase compensation fifo buffer byte serializer 8b/10b encoder serializer (parallel-to-serial converter) transmitter differential output buffer transmitter plls each transceiver block has two tr ansmitter plls which receive two reference clocks to generate ti ming and the following clocks: high-speed clock used by the seri alizer to transmit the high-speed differential transmitter data low-speed clock to load the parallel transmitter data of the serializer the serializer uses high-speed clocks to transmit data. the serializer is also referred to as parallel in serial out (piso). the high -speed clock is fed to the local clock generation buffer . the local clock generation buffers divide the high-speed clock on the transmitter to a desired frequency on a per-channel basis. figure 2?3 is a block diagram of the transmitter clocks.
altera corporation 2?5 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?3. clock distributio n for the transmitters note (1) note to figure 2?3 : (1) the global clock line must be driven by an input pin. the transmitter plls in each tran sceiver block clock the pma and pcs circuitry in the transmit path. the quartus ii softwa re automatically powers down the transmitter plls that are not used in the design. figure 2?4 is a block diagram of the transmitter pll. the transmitter phase/freq uency detector references the clock from one of the following sources: reference clocks reference clock from the adjacent transceiver block inter-transceiver block clock lines global clock line driven by input pin two reference clocks, refclk0 and refclk1 , are available per transceiver block. the inter-transc eiver block bus allows multiple transceivers to use the same referenc e clocks. each transceiver block has one outgoing reference clock whic h connects to one inter-transceiver block line. the incoming reference clock can be selected from five inter-transceiver block lines iq[4..0] or from the global clock line that is driven by an input pin. transmitter pll block central clock divider block tx clock gen block tx clock gen block transmitter channel [3..2] transmitter channel [1..0] transmitter high-speed & low-speed clocks transmitter high-speed & low-speed clocks transmitter local clock divider block transmitter local clock divider block reference clocks (refclks, global clock (1) , inter-transceiver lines) central block
2?6 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?4. transmitter pll block note (1) note to figure 2?4 : (1) the global clock line must be driven by an input pin. the transmitter plls support data rate s up to 6.375 gbps. the input clock frequency is limited to 622.08 mhz. an optional pll_locked port is available to indicate whether the tr ansmitter pll is locked to the reference clock. both transmitter plls have a programmable loop bandwidth parameter that can be set to low, medium, or high. the loop bandwidth parameter can be statically set in the quartus ii software. table 2?2 lists the adjustable parameters in the transmitter pll. pfd dedicated local refclk 0 cp+lf up dn vco from pld inter-transceiver block routing (iq[4:0]) from pld inter-transceiver block routing (iq[4:0]) l pfd dedicated local refclk 1 cp+lf up dn vco m 2 inclk l transmitter pll 1 transmitter pll 0 high-speed transmitter pll0 clock high-speed transmitter pll1 clock high-speed transmitter pll cloc k to inter-transceiver block line /2 2 m inclk table 2?2. transmitter pll specifications parameter specifications input reference frequency range 50 mhz to 622.08 mhz data rate support 600 mbps to 6.375 gbps multiplication factor (w) 1, 4, 5, 8, 10, 16, 20, 25 bandwidth low, medium, or high
altera corporation 2?7 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture transmitter phase compensation fifo buffer the transmitter phase compensation fifo buffer resides in the transceiver block at the pcs/fpga boundary and cannot be bypassed. this fifo buffer compensates fo r phase differences between the transmitter pll clock and the clock fr om the pld. after the transmitter pll has locked to the frequency and phase of the reference clock, the transmitter fifo buffer must be re set to initialize the read and write pointers. after fifo pointer initialization, the pll must remain phase locked to the reference clock. byte serializer the fpga and transceiver block must maintain the same throughput. if the fpga interface cannot meet th e timing margin to support the throughput of the transceiver, the byte serializer is used on the transmitter and the byte deserial izer is used on the receiver. the byte serializer takes words from the fpga interface and converts them into smaller words for use in the transceiver. the transmit data path after the byte serializer is 8, 10, 16, or 20 bits. refer to table 2?3 for the transmitter data with the byte serializ er enabled. the byte serializer can be bypassed when the data width is 8, 10, 16, or 20 bits at the fpga interface. if the byte serializer is disabled, th e fpga transmit data is passed without data width conversion. table 2?3. transmitter data with the byte serializer enabled input data width output data width 16 bits 8 bits 20 bits 10 bits 32 bits 16 bits 40 bits 20 bits
2?8 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers table 2?4 shows the data path configurations for the stratix ii gx device in single-width and double-width modes. 1 refer to the section ?8b/10b encoder? on page 2?8 for a description of the single- and double-width modes. 8b/10b encoder there are two different modes of operation for 8b/10b encoding. single-width (8-bit) mode supports natural data rates from 622 mbps to 3.125 gbps. double-width (16-bit cascaded) mode supports data rates above 3.125 gbps. the encoded data has a maximum run length of five. the 8b/10b encoder can be bypassed. figure 2?5 diagrams the 10-bit encoding process. table 2?4. data path configurations note (1) parameter single-width mode double-width mode without byte serialization/ deserialization with byte serialization/ deserialization without byte serialization/ deserialization with byte serialization/ deserialization fabric to pcs data path width (bits) 8 or 10 16 or 20 16 or 20 32 or 40 data rate range (gbps) 0.6 to 2.5 0.6 to 3.125 1 to 5.0 1 to 6.375 pcs to pma data path width (bits) 8 or 10 8 or 10 16 or 20 16 or 20 byte ordering (1) vv data symbol a (msb) v data symbol b vv data symbol c vv data symbol d (lsb) vvvv note to ta b l e 2 ? 4 : (1) designs can use byte ordering when byte serialization and deserialization are used.
altera corporation 2?9 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?5. 8b/10b encoding process in single-width mode, the 8b/10b en coder generates a 10-bit code group from the 8-bit data and 1-bit contro l identifier. in double-width mode, there are two 8b/10b encoders that are cascaded together and generate a 20-bit (2 10-bit) code group from the 16-bit (2 8-bit) data + 2-bit (2 1-bit) control identifier. figure 2?6 shows the 20-bit encoding process. the 8b/10b encoder conforms to the ieee 802.3 1998 edition standards. figure 2?6. 16-bit to 20-bit encoding process upon power on or reset, the 8b/10b encoder has a negative disparity which chooses the 10-bit code fr om the rd-column. however, the running disparity can be changed via the tx_forcedisp and tx_dispval ports. 9876543210 8b/10b conversion 76543210 hgfed cb a + ctrl jhgfiedcba msb sent last lsb sent firs t cascaded 8b/10b conversion g' f' e' d' c' b' a' h' g f e d c b a h parallel data ctrl[1..0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb msb g' f' i' e' d' c' b' a' j' h' g f i edcba jh 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2?10 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers transmit state machine the transmit state machine operates in either pci express mode, xaui mode, or gige mode, depending on th e protocol used. the state machine is not utilized for certai n protocols, such as sonet. gige mode in gige mode, the transmit state mach ine converts all idle ordered sets (/k28.5/, /dx.y/) to either /i1/ or /i 2/ ordered sets. /i1/ consists of a negative-ending disparity /k28.5/ (d enoted by /k28.5/-) followed by a neutral /d5.6/. /i2/ consists of a positive-ending disparity /k28.5/ (denoted by /k28.5/+) and a nega tive-ending disparity /d16.2/ (denoted by /d16.2/-). the transmit state machines do not convert any of the ordered sets to match /c1/ or /c2/, which are the configuration ordered sets. (/c1/ and /c2/ are defined by [/k28.5/, /d21.5/] and [/k28.5/, /d2.2/], respectively). bo th the /i1/ and /i2/ ordered sets guarantee a negative-ending disparity after each ordered set. xaui mode the transmit state machine translates the xaui xgmii code group to the xaui pcs code group. table 2?5 shows the code conversion. the xaui pcs idle code groups, /k2 8.0/ (/r/) and /k28.5/ (/k/), are automatically randomiz ed based on a prbs7 pattern with an x 7 + x 6 + 1 polynomial. the /k28.3/ (/a/) code group is automatically generated between 16 and 31 idle code groups. th e idle randomization on the /a/, /k/, and /r/ code groups is done automatically by the transmit state machine. table 2?5. code conversion xgmii txc xgmii txd pcs code-group description 0 00 through ff dxx.y normal data 1 07 k28.0 or k28.3 or k28.5 idle in || i || 1 07 k28.5 idle in || t || 1 9c k28.4 sequence 1 fb k27.7 start 1 fd k29.7 terminate 1 fe k30.7 error 1 see ieee 802.3 reserved code groups see ieee 802.3 reserved code groups reserved code groups 1 other value k30.7 invalid xgmii character
altera corporation 2?11 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture serializer (parallel-to-serial converter) the serializer converts the parallel 8, 10 , 16, or 20-bit data into a serial data bit stream, transmitting th e least significant bit (lsb ) first. the serialized data stream is then fed to the high-s peed differential transmit buffer. figure 2?7 is a diagram of the serializer. figure 2?7. serializer note (1) note to figure 2?7 : (1) this is a 10-bit serializer. the serializer can also convert 8, 16, and 20 bits of data. transmit buffer the stratix ii gx transceiver buffers support the 1.2- and 1.5-v pcml i/o standard at rates up to 6.375 gbps. the common mode voltage (v cm ) of the output driver is pr ogrammable. the following v cm values are available when the buffer is in 1.2- and 1.5-v pcml. v cm = 0.6 v v cm = 0.7 v d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 low-speed parallel clock high-speed serial clock serial data out (to output buffer) d8 d9 d8 d9 10
2?12 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers f refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx handbook . the output buffer, as shown in figure 2?8 , is directly driven by the high-speed data serializer and consis ts of a programmable output driver, a programmable pre-emphasis circuit, a programmable termination, and a programmable v cm . figure 2?8. output buffer programmable output driver the programmable output driver can be set to drive out differentially 200 to 1,400 mv. the differential output voltage (v od ) can be changed dynamically, or statically set by using the alt2gxb megafunction or through i/o pins. the output driver may be programmed with four different differential termination values: 100 120 150 external termination serializer programmable termination programmable pre-emphasis output buffer output pins programmable output driver
altera corporation 2?13 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture differential signaling conventions are shown in figure 2?9 . the differential amplitude represents the value of the voltage between the true and complement signals. peak-to- peak differential voltage is defined as 2 (v high ? v low ) = 2 single-ended voltage swing. the common mode voltage is the average of v high and v low . figure 2?9. differential signaling programmable pre-emphasis the programmable pre-emphasis module controls the output driver to boost the high frequency components, and compensate for losses in the transmission medium, as shown in figure 2?10 . the pre-emphasis is set statically using the alt2gxb megafu nction or dynamically through the dynamic reconfiguration controller. figure 2?10. pre-emphasis signaling single-ended waveform differential waveform +v od +v od -v od 2 * v od 0-v differential +400 ? 400 - v od (differential) = v hi g h v low v low v hi g h complement tr u e ? v max v max v min v min pre-emphasis % = ( ? 1) 100
2?14 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers pre-emphasis percentage is defined as (v max /v min ? 1) 100, where v max is the differential emphasized voltage (peak-to-peak) and v min is the differential steady-state voltage (peak-to-peak). programmable termination the programmable termination can be statically set in the quartus ii software. the values are 100 , 120 , 150 , and external termination. figure 2?11 shows the setup for programmable termination. figure 2?11. programmable transmitter terminations pci express re ceiver detect the stratix ii gx transmitter buffer ha s a built-in receiver detection circuit for use in pipe mode. this circuit prov ides the ability to detect if there is a receiver downstream by sendin g out a pulse on the channel and monitoring the refl ection. this mode requires the transmitter buffer to be tri-stated (in electrical idle mode). pci express electric idles (or individual transmitter tri-state) the stratix ii gx transmitter buffer supports pci express electrical idles. this feature is only active in pipe mode. the tx_forceelecidle port puts the transmitter buffer in electrical idle mode. this port is available in all pci express power-down modes and has specific usage in each mode. receiver path this section describes the data path th rough the stratix ii gx receiver. the stratix ii gx receiver consists of the following blocks: receiver differential input buffer receiver pll lock detector, signal detector, and run length checker clock/data recovery (cru) unit deserializer pattern detector word aligner programmable output driver 50, 60, or 75 v cm
altera corporation 2?15 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture lane deskew rate matcher 8b/10b decoder byte deserializer byte ordering receiver phase compensation fifo buffer receiver input buffer the stratix ii gx receiver input buffer supports the 1.2-v and 1.5-v pcml i/o standard at rates up to 6.375 gbps. the common mode voltage of the receiver input buffer is pr ogrammable between 0.85 v and 1.2 v. you must select the 0.85 v common mode voltage for ac- and dc-coupled pcml links and the 1.2 v common mode voltage for dc-coupled lvds links. the receiver has programmable on-chip 100-, 120-, or 150- differential termination for different protocols, as shown in figure 2?12 . the receiver?s internal termination can be disabled if external terminations and biasing are provided. the receiv er and transmitter differential termination resistances can be set independently of each other. figure 2?12. receiver input buffer programmable termination the programmable termination can be statically set in the quartus ii software. figure 2?13 shows the setup for programmable receiver termination. the termination can be disabled if external termination is provided. pro g rammable termination input pins differential input buffer pro g rammable equalizer
2?16 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?13. programmable receiver termination if a design uses external termination, the receiver must be externally terminated and biased to 0.85 v or 1.2 v. figure 2?14 shows an example of an external terminat ion and biasing circuit. figure 2?14. external termi nation and bias ing circuit programmable equalizer the stratix ii gx receivers provide a programmable receive equalization feature to compensate the effects of channel attenuation for high-speed signaling. pcb traces carrying these high-speed signals have low-pass filter characteristics. the impedance mismatch boundaries can also cause signal degradation. the equalization in the receiver diminishes the lossy attenuation effects of the pcb at high frequencies. differential input buffer 50, 60, or 75 50, 60, or 75 v cm transmission line c1 r1/r2 = 1k v dd {r2/(r1 + r 2)} = 0.85/1.2 v 50/60/75- termination resistance r1 r2 v dd receiver external termination and biasing stratix ii gx device receiver external termination and biasing rxip rxin receiver
altera corporation 2?17 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture 1 the stratix ii gx receivers also have adaptive equalization capability that adjusts the equalization levels to compensate for changing link characteristics. th e adaptive equalization can be powered down dynamically after it selects the appropriate equalization levels. the receiver equalization circuit is comprised of a programmable amplifier. each stage is a peaking equalizer with a different center frequency and programmable gain. this allows varying amounts of gain to be applied, depending on the over all frequency response of the channel loss. channel loss is defined as the summation of all losses through the pcb traces, vias, connectors, and cables present in the physical link. figure 2?15 shows the frequency response for the 16 programmable settings allowed by the quartus ii software for stratix ii gx devices. figure 2?15. frequency response receiver pll and cru each transceiver block has four receiver plls, lock detectors, signal detectors, run length checkers, and cr u units, each of which is dedicated to a receive channel. if the receive channel associated with a particular receiver pll or cru is not used, the receiver pll and cru are powered down for the channel. figure 2?16 shows the receiver pll and cru circuits. high medium low bypass eq
2?18 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?16. receiver pll and cru the receiver plls and crus can su pport frequencies up to 6.375 gbps. the input clock frequency is limited to the full clock range of 50 to 622 mhz but only when using refclk0 or refclk1 . an optional rx_pll_locked port is available to indicate whether the pll is locked to the reference clock. the receiv er pll has a programmable loop bandwidth which can be set to low, medium, or high. the quartus ii software can statically set the loop bandwidth parameter. all the parameters listed are progra mmable in the quartus ii software. the receiver pll has the following features: operates from 600 mbps to 6.375 gbps. uses a reference clock between 50 mhz and 622.08 mhz. programmable bandwidth settings: low, medium, and high. programmable rx_locktorefclk (forces the receiver pll to lock to the reference clock) and rx_locktodata (forces the receiver pll to lock to the data). the voltage-controlled oscillator (vco) operates at half rate and has two modes. these modes are for low or high frequency operation and provide optimized phase-noise performance. programmable frequency multiplication w of 1, 4, 5, 8, 10, 16, 20, and 25. not all settings are supported for any particular frequency. two lock indication signals are provided. they are found in pfd mode (lock-to-reference cl ock), and pd (lock-to-data). rx_cruclk cp+lf up down vco m 1, 4, 5, 8, 10, 16, 20, or 25 rx_datain hi g h speed rcvd_clk low speed rcvd_clk down up rx_locktorefclk rx_rlv[ ] rx_locktodata rx_freqlocked clock recovery unit (cru) pfd l 2 n 1, 2, 4 1, 2, 4 rx_pll_locked
altera corporation 2?19 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture the cru has a built-in switchover ci rcuit to select whether the pll vco is aligned by the reference clock or the data. the optional port rx_freqlocked monitors when the cru is in locked-to-data mode. in the automatic mode, the cru pll mu st be within the prescribed ppm frequency threshold setting of the cru reference clock for the cru to switch from locked-to-refere nce to locked-to-data mode. the automatic switchover circuit can be overridden by using the optional ports rx_locktorefclk and rx_locktodata . table 2?6 shows the possible combinations of these two signals. if the rx_locktorefclk and rx_locktodata ports are not used, the default is auto mode. deserializer (serial-to-parallel converter) the deserializer converts a serial bi tstream into 8, 10, 16, or 20 bits of parallel data. the deserializer receives the lsb first. figure 2?17 shows the deserializer. table 2?6. receiver lock combinations rx_locktodata rx_locktoref clk vco (lock to mode) 00 auto 0 1 reference clock 1x data
2?20 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?17. deserializer note (1) note to figure 2?17 : (1) this is a 10-bit deserializer. the deserializer can also convert 8, 16, or 20 bits of data. word aligner the deserializer block cr eates 8-, 10-, 16-, or 20-bit parallel data. the deserializer ignores protocol symbol boundaries when converting this data. therefore, the boundaries of the transferred words are arbitrary. the word aligner aligns the incoming data based on specific byte or word boundaries. the word alignment module is clocked by the local receiver recovered clock during normal oper ation. all the data and programmed patterns are defined as big-endian (most significant word followed by least significant word). most-signi ficant-bit-first protocols such as sonet/sdh should reverse the bit order of word align patterns programmed. high-speed serial clock d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 low-speed parallel clock d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 10
altera corporation 2?21 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture this module detects word boundari es for the 8b/10b-based protocols, sonet, 16-bit, and 20-bit proprietary pr otocols. this module is also used to align to specific programmable patterns in prbs7/23 test mode. pattern detection the programmable pattern detection logic can be programmed to align word boundaries using a single 7-, 8-, 10-, 16-, 20, or 32-bit pattern. the pattern detector can either do an ex act match, or match the exact pattern and the complement of a given pattern . once the programmed pattern is found, the data stream is aligned to have the pattern on the lsb portion of the data output bus. xaui, gige, pci express, and serial rapidio standards have embedded state machines for symbol boundary synchronization. these standards use k28.5 as their 10-bit programmed comma pattern. each of these standards uses different algorithms before signaling symbol boundary acquisition to the fpga. the pattern detection logic searches from the lsb to the most significant bit (msb). if multiple patterns are found within the search window, the pattern in the lower portion of the data stream (corresponding to the pattern received earlier) is aligned and the rest of the matching patterns are ignored. once a pattern is detected and the data bus is aligned, the word boundary is locked. the two detection status signals ( rx_syncstatus and rx_patterndetect ) indicate that an alignment is complete. figure 2?18 is a block diagram of the word aligner. figure 2?18. word aligner word aligner datain dataout bitslip enapatternalign syncstatus patterndetect clock
2?22 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers control and status signals the rx_enapatternalign signal is the fpga control signal that enables word alignment in non-automatic modes. the rx_enapatternalign signal is not used in automatic modes (pci express, xaui, gige, cpri, and serial rapidio). in manual alignment mode, after the rx_enapatternalign signal is activated, the rx_syncstatus signal goes high for one parallel clock cycle to indicate that the alignment pattern has been detected and the word boundary has been locked. if the rx _ enapatternalign is deactivated, the rx_syncstatus signal acts as a re-synchronization signal to signify that the alignment pattern has been detected but not locked on a different word boundary. when using the synchroni zation state machine, the rx_syncstatus signal indicates the link status. if the rx_syncstatus signal is high, link synchronization is achieved. if the rx_syncstatus signal is low, synchronization has not yet been achi eved, or there were enough code group errors to lose synchronization. in some modes, the rx_enapatternalign signal can be configured to operate as a rising edge signal. f for more information on manual alignment modes, refer to the stratix ii gx device handbook , volume 2. when the rx_enapatternalign signal is sensitive to the rising edge, each rising edge triggers a new boun dary alignment search, clearing the rx_syncstatus signal. the rx_patterndetect signal pulses high du ring a new alignment, and also whenever the alignment pa ttern occurs on the current word boundary. sonet/sdh in all the sonet/sdh modes, you can configure the word aligner to either align to a1a2 or a1a1a2a2 patterns. once the pattern is found, the word boundary is aligned and the word aligner asserts the rx_patterndetect signal for one clock cycle.
altera corporation 2?23 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture programmable run length violation the word aligner supports a programmable run length violation counter. whenever the number of the contin uous ?0? (or ?1?) exceeds a user programmable value, the rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles . the maximum run values supported are shown in table 2?7 . running disparity check the running disparity error rx_disperr and running disparity value rx_runningdisp are sent along with alig ned data from the 8b/10b decoder to the fpga. you can ignore or act on the reported running disparity value and running disparity error signals. bit-slip mode the word aligner can operate in either pattern detection mode or in bit-slip mode. the bit-slip mode provides the op tion to manually shift the word boundary through the fpga. this feature is useful for: longer synchronization patterns than the pattern detector can accommodate scrambled data stream input stream consisting of over-sampled data this feature can be applied at 10-bit and 16-bit data widths. the word aligner outputs a word boundary as it is received from the analog receiver after reset. you can examine the word and search its boundary in the fpga. to do so, assert the rx_bitslip signal. the rx_bitslip signal should be toggled and held constant for at least two fpga clock cycles. for every rising edge of the rx_bitslip signal, the current word boundary is slipped by one bit. every time a bit is slipped, the bit received earliest is lost. if bit slipping shifts a complete round of bus width, the word boundary is back to the original boundary. table 2?7. maximum run length (ui) mode pma serialization 8 bit 10 bit 16 bit 20 bit single-width 128 160 ? ? double-width ? ? 512 640
2?24 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers the rx_syncstatus signal is not available in bit-slipping mode. channel aligner the channel aligner is available only in xaui mode and aligns the signals of all four channels within a transc eiver. the channel aligner follows the ieee 802.3ae, clause 48 specif ication for channel bonding. the channel aligner is a 16-word fifo buffer with a state machine controlling the channel bonding proce ss. the state machine looks for an /a/ (/k28.3/) in each channel, and al igns all the /a/ code groups in the transceiver. when four columns of /a/ (denoted by //a//) are detected, the rx_channelaligned signal goes high, signifying that all the channels in the transceiver have been aligned. the reception of four consecutive misaligned /a/ code groups restarts the channel alignment sequence and sends the rx_channelaligned signal low. figure 2?19 shows misaligned channels before the channel aligner and the aligned channels after the channel aligner. figure 2?19. before and af ter the channel aligner kr kkk r r rkk r a lane 3 kr kkk r r rkk r a lane 2 kr kkk r r rkk r a lane 1 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 3 kr kkk r r rkk r a lane 2 kr kkk r r rkk r a lane 1 kr kkk r r rkk r a lane 0 before after
altera corporation 2?25 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture rate matcher rate matcher is availabl e in basic, pci express, xaui, and gige modes and consists of a 20-word deep fifo buffer and a fifo controller. figure 2?20 shows the implementation of the rate matcher in the stratix ii gx device. figure 2?20. rate matcher in a multi-crystal environment, the rate matcher compensates for up to a 300-ppm difference between the source and receiver clocks. table 2?8 shows the standards supported and the ppm for the rate matcher tolerance. basic mode in basic mode, you can program the skip and control pattern for rate matching. in single-width basic mode, there is no restriction on the deletion of a skip character in a clus ter. the rate matcher deletes the skip characters as long as th ey are available. for insertion, the rate matcher inserts skip characters such that the number of skip characters at the output of rate matcher does not exce ed five. in double-width mode, the rate matcher deletes skip character when they appear as pairs in the upper and lower bytes. there are no restrictions on the number of skip characters that are deleted. the rate matcher inserts skip characters as pairs. table 2?8. rate matcher ppm support note (1) standard ppm xaui 100 pci express (pipe) 300 gige 100 basic double-width 300 note to table 2?8 : (1) refer to the stratix ii gx transceiver user guide for the altera ? -defined scheme. rate matcher dataout datain wrclock rdclock
2?26 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers gige mode in gige mode, the rate matcher adhe res to the specifications in clause 36 of the ieee 802.3 documentation for id le additions or removals. the rate matcher performs clock compensati on only on /i2/ ordered sets, composed of a /k28.5/+ followed by a /d16.2/-. the rate matcher does not perform clock compensation on any other ordered set combinations. an /i2/ is added or deleted automatically based on the number of words in the fifo buffer. a k28.4 is given at the control and data ports when the fifo buffer is in an overflow or underflow condition. xaui mode in xaui mode, the rate matcher adhe res to clause 48 of the ieee 802.3ae specification for clock rate compensation. the rate matcher performs clock compensation on columns of /r/ (/k28.0/), denoted by //r//. an //r// is added or deleted automatically based on the number of words in the fifo buffer. pci express mode pci express mode operates at a data rate of 2.5 gbps, and supports lane widths of 1, 2, 4, and 8. the rate matcher can support up to 300-ppm differences between the upstream transmitter and the receiver. the rate matcher looks for the skip ordered sets (sos), which usually consist of a /k28.5/ comma followed by three /k28.0/ skip characters. the rate matcher deletes or inserts skip characters when necessary to prevent the rate matching fifo buffer from overflowing or underflowing. the stratix ii gx rate matcher in pci express mode has fifo overflow and underflow protection. in the event of a fifo overflow, the rate matcher deletes any data after the overflow condition to prevent fifo pointer corruption until the rate ma tcher is not full. in an underflow condition, the rate matcher inserts 9' h1fe (/k30.7/) until the fifo is not empty. these measures ensure that the fifo can gracefully exit the overflow and underflow condition without requiring a fifo reset. 8b/10b decoder the 8b/10b decoder ( figure 2?21 ) is part of the stra tix ii gx transceiver digital blocks (pcs) and lies in the re ceiver path between the rate matcher and the byte deserializer blocks. the 8b/10b decoder operates in single-width and double-width mode s, and can be bypassed if the 8b/10b decoding is not necessary. in single-width mode, the 8b/10b decoder restores the 8-bit data + 1-bi t control identifier from the 10-bit code. in double-width mode, there are two 8b/10b decoders in parallel, which restores the 16-bit (2 8-bit) data + 2-bit (2 1-bit) control identifier from the 20-bit (2 10-bit) code. this 8b/10b decoder conforms to the ieee 802.3 1998 edition standards.
altera corporation 2?27 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?21. 8b/10b decoder the 8b/10b decoder in single-width mode translates the 10-bit encoded data into the 8-bit equivalent data or control code. the 10-bit code received must be from the supported dx.y or kx.y list with the proper disparity or error flags asserted. al l 8b/10b control si gnals, such as disparity error or control detect, are pipelined with the data and edge-aligned with the data. figure 2?22 shows how the 10-bit symbol is decoded in the 8-bit data + 1-bit control indicator. figure 2?22. 8b/10b decoder conversion the 8b/10b decoder in double-width mode translates the 20-bit (2 10-bits) encoded code into the 16-bit (2 8-bits) equivalent data or control code. the 20-bit upper and lowe r symbols received must be from the supported dx.y or kx.y list with the proper disparity or error flags 8b/10b decoder msbyte datain[19..10] to byte deserializer dataout[15..8] status si g nals[1] (1) 8b/10b decoder lsbyte datain[9..0] dataout[7..0] status si g nals[0] from rate matcher (1) 9876543210 8b/10b conversion jhgfiedcba msb received last lsb received first 76543210 hgfed cb a + ctrl parallel data
2?28 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers asserted. all 8b/10b cont rol signals, such as disparity error or control detect, are pipelined with the data in the stratix ii gx receiver block and are edge aligned with the data. figure 2?23 shows how the 20-bit code is decoded to the 16-bit data + 2-bit control indicator. figure 2?23. 20-bit to 16-bit decoding process there are two optional error status po rts available in the 8b/10b decoder, rx_errdetect and rx_disperr . these status signals are aligned with the code group in which the error occurred. receiver state machine the receiver state machine operates in basic, gige, pci express, and xaui modes. in gige mode, the rece iver state machine replaces invalid code groups with k30.7. in xaui mode, the receiver state machine translates the xaui pcs code grou p to the xaui xgmii code group. byte deserializer the byte deserializer widens the tran sceiver data path before the fpga interface. this reduces the rate at which the received data needs to be clocked at in the fpga logic. the byte deserializer block is available in both single- and double-width modes. the byte deserializer converts the one- or two-byte interface into a two- or four-byte-wide data path from the transceiver to the fpga logic (see table 2?9 ). the fpga interface has a li mit of 250 mhz, so the byte deserializer is needed to widen the bus width at the fpga interface and 19 18 17 16 15 14 13 12 11 10 cascaded 8b/10b conversion j 1 h 1 g 1 f 1 i 1 e 1 d 1 c 1 b 1 a 1 msb lsb 15 14 13 13 11 10 9 8 h 1 g 1 f 1 e 1 d 1 c 1 b 1 a 1 ctrl[1..0] 9876543210 jh g fiedcba 7 6543 21 0 hgfed cb a parallel data
altera corporation 2?29 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture reduce the interface speed. for exam ple, at 6.375 gbps, the transceiver logic has a double-byte-wide data path that runs at 318.75 mhz in a 20 deserializer factor, which is above the maximum fpga interface speed. when using the byte deserializer, th e fpga interface width doubles to 40-bits (36-bits when using the 8b/ 10b encoder) and the interface speed reduces to 159.375 mhz. byte ordering block the byte ordering block shifts the byte order. a pre-programmed byte in the input data stream is detected and placed in the leas t significant byte of the output stream. subsequent bytes start appearing in the byte positions following the lsb. the byte ordering block inserts the programmed pad characters to shift the byte order pattern to the lsb. based on the setting in the megawizard ? plug-in manager, the byte ordering block can be enabled either by the rx_syncstatus signal or by the rx_enabyteord signal from the pld. when the rx_syncstatus signal is used as enable, the byte ordering block reorders the data only for the first occurrence of the byte order pattern that is received after word alignment is completed. you must assert rx_digitalreset to perform byte ordering again. however, when th e byte ordering block is controlled by rx_enabyteord , the byte ordering block can be controlled by the pld logic dynamically. when you crea te your functional mode in the megawizard, you can select byte ordering block only if rate matcher is not selected. receiver phase compensation fifo buffer the receiver phase compensation fifo buffer resides in the transceiver block at the fpga boundary and cann ot be bypassed. this fifo buffer compensates for phase differences an d clock tree timing skew between the receiver clock domain within th e transceiver and the receiver fpga clock after it has transferred to the fpga. table 2?9. byte deserializer input and output widths input data width (bits) deserialized output data width to the fpga (bits) 20 40 16 32 10 20 816
2?30 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers when the fifo pointers initialize, the receiver domain clock must remain phase locked to receiver fpga clock. after resetting the receiver fifo buffer, writing to the receiver fifo buffer begins and continues on each parallel clock. the phase compensation fifo buffer is eight words deep for pipe mode and four words deep for all other modes. loopback modes the stratix ii gx transceiver has built-in loopback modes for debugging and testing. the loopback modes are configured in the stratix ii gx alt2gxb megafunction in the quartus ii software. the available loopback modes are: serial loopback parallel loopback reverse serial loopback reverse serial loopback (pre-cdr) pci express pipe reverse parallel loopback (available only in pipe mode) serial loopback the serial loopback mode exercises all the transceiver logic, except for the input buffer. serial loopback is available for all non-pipe modes. the loopback function is dyna mically enabled through the rx_seriallpbken port on a channel-by-channel basis. in serial loopback mode, the data on th e transmit side is sent by the pld. a separate mode is available in the alt2gxb megafunction under basic protocol mode, in which prbs data is generated and verified internally in the transceiver. the prbs patterns av ailable in this mode are shown in table 2?10 . table 2?10 shows the bist data output and verifier alignment pattern. table 2?10. bist data output and verifier alignment pattern pattern polynomial parallel data width 8-bit 10-bit 16-bit 20-bit prbs-7 7 + 6 + 1 v prbs-10 10 + 7 + 1 v
altera corporation 2?31 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?24 shows the data path in serial loopback mode. figure 2?24. stratix ii gx block in se rial loopback mode with bist and prbs parallel loopback the parallel loopback mode exercises the digital logic portion of the transceiver data path. the analog port ions are not used in this loopback path, and the received high-speed serial data is not retimed. this protocol is available as one of the sub-protoco ls under basic mode and can be used only for basic double-width mode. in this loopback mode, the data fr om the internally available bist generator is transmitted. the data is looped back after the end of pcs and before the pma. on the receive side, an internal bist verifier checks for errors. this loopback enables you to verify the pcs block. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer serial loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20
2?32 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?25 shows the data path in parallel loopback mode. figure 2?25. stratix ii gx bloc k in parallel loopback mode reverse serial loopback the reverse serial loopback mode uses the analog portion of the transceiver. an external source (p attern generator or transceiver) generates the source data. the high-speed serial source data arrives at the high-speed differential receiver in put buffer, passes through the cru unit, and the retimed serial data is looped back and transmitted though the high-speed differential transmitter output buffer. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer parallel loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20
altera corporation 2?33 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?26 shows the data path in reverse serial loopback mode. figure 2?26. stratix ii gx block in reverse serial loopback mode reverse serial pre-cdr loopback the reverse serial pre-cdr loopback mo de uses the analog portion of the transceiver. an external source (p attern generator or transceiver) generates the source data. the high-speed serial source data arrives at the high-speed differential receiver inpu t buffer, loops back before the cru unit, and is transmitted though the high-speed differential transmitter output buffer. it is for test or veri fication use only to verify the signal being received after the gain and eq ualization improvements of the input buffer. the signal at the output is n ot exactly what is received since the signal goes through the output bu ffer and the vod is changed to the vod setting level. the pre-emphas is settings have no effect. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer reverse serial loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20
2?34 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?27 show the stratix ii gx block in reverse serial pre-cdr loopback mode. figure 2?27. stratix ii gx block in re verse serial pre-cdr loopback mode pci express pipe reverse parallel loopback this loopback mode, available only in pipe mode, can be dynamically enabled by the tx_detectrxloopback port of the pipe interface. figure 2?28 shows the datapath for this mode. figure 2?28. stratix ii gx block in pci ex press pipe reverse parallel loopback mode transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer reverse serial pre-cdr loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 pci express pipe reverse parallel loopback
altera corporation 2?35 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture transceiver clocking each stratix ii gx device transceive r block contains tw o transmitter plls and four receiver plls. these plls can be driven by either of the two reference clocks per transceiver block. these refclk signals can drive all global clocks, transmi tter pll inputs, and all receiver pll inputs. subsequently, the transmitter pll ou tput can only drive global clock lines and the receiver pll referenc e clock port. only one of the two reference clocks in a quad can drive the inter quad (i/q ) lines to clock the plls in the other quads. figure 2?29 shows the inter-transceiver line connections as well as the global clock connections for the ep2sgx130 device.
2?36 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?29. ep2sgx130 device inter-trans ceiver and global clock connections notes to figure 2?29 : (1) there are two transmitter p lls in each transceiver block. (2) there are four receiver pl ls in each tr ansceiver block. (3) the global clock line must be driven by an input pin. transmitter pll 0 transceiver block 0 refclk0 4 receiver plls transmitter pll 1 refclk1 iq[4..0] iq[4..0] iq[4..0] global clk line to iq0 transmitter pll 0 transceiver block 1 4 receiver plls transmitter pll 1 iq[4..0] iq[4..0] iq[4..0] to iq1 transmitter pll 0 transceiver block 2 4 receiver plls transmitter pll 1 iq[4..0] iq[4..0] iq[4..0] to iq4 transmitter pll 0 transceiver block 3 4 receiver plls transmitter pll 1 iq[4..0] iq[4..0] iq[4..0] to iq2 transmitter pll 0 transceiver block 4 4 receiver plls transmitter pll 1 from global clock line (3) iq[4..0] iq[4..0] iq[4..0] to iq3 iq[4..0] to pld global clocks 16 interface clocks from global clock line (3) 2 refclk0 2 refclk0 2 refclk0 2 refclk0 2 2 refclk1 2 refclk1 2 refclk1 2 refclk1 2 global clk line global clk line global clk line global clk line global clk line global clk line global clk line global clk line global clk line from global clock line (3) from global clock line (3) from global clock line (3) from global clock line (3) transceiver clock generator block transceiver clock generator block transceiver clock generator block transceiver clock generator block transceiver clock generator block
altera corporation 2?37 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture the receiver pll can also drive the regional clocks and regional routing adjacent to the associated transceiver block. figure 2?30 shows which global clock resource can be used by the recovered clock. figure 2?31 shows which regional clock resource can be used by the recovered clock. figure 2?30. stratix ii gx re ceiver pll recovered clock to global clock connection notes (1) , (2) notes to figure 2?30 : (1) clk# pins are clock pins and their associated number. these are pins for global and regional clocks. (2) gclk# pins are global clock pins. gclk[15..12] gclk[4..7] gclk[11..8] gclk[3..0] stratix ii gx transceiver block stratix ii gx transceiver block 12 6 11 5 clk[7..4] clk[15..12] clk[3..0] 1 7 2 8
2?38 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?31. stratix ii gx re ceiver pll recovered clock to regional clock connection notes (1) , (2) notes to figure 2?31 : (1) clk# pins are clock pins and their associated number. these are pins for global and local clocks. (2) r clk# pins are regional clock pins. rclk [3..0] rclk [7..4] rclk [23..20] rclk [19..16] rclk [11..8] rclk [15..12] rclk [31..28] rclk [27..24] stratix ii gx transceiver block stratix ii gx transceiver block 12 6 11 5 clk[7..4] clk[15..12] clk[3..0] 1 7 2 8
altera corporation 2?39 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?11 summarizes the possible clocking connections for the transceivers. clock resource for pld-transceiver interface for the regional or global clock netw ork to route into the transceiver, a local route input output (lrio) channel is required. each lrio clock region has up to eight clock paths and each transceiver block has a maximum of eight clock paths for co nnecting with lrio clocks. these resources are limited and determine the number of clocks that can be used between the pld and transceiver blocks. table 2?12 shows the number of lrio resources available for stratix ii gx devices with different numbers of transceiver blocks. tables 2?12 through 2?15 show the connection of the lrio clock resource to the transceiver block. table 2?11. available clocking connections for transceivers source destination transmitter pll receiver pll global clock regional clock inter-transceiver lines refclk[1..0] vvvv v transmitter pll vv receiver pll vv global clock (driven from an input pin) vv inter-transceiver lines vv table 2?12. available clocking connectio ns for transceivers in 2sgx30d region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 12-19 v
2?40 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers . . table 2?13. available clocking connecti ons for transceivers in 2sgx60e region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o bank 15 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 vv region2 8 lrio clock v rclk 12-19 vv region3 8 lrio clock v rclk 12-19 v table 2?14. available clocking connecti ons for transceivers in 2sgx90f region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o bank 15 8 clock i/o bank 16 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 v region2 8 lrio clock v rclk 12-19 v region3 8 lrio clock v rclk 12-19 v
altera corporation 2?41 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture . other transceiver features other important features of the strati x ii gx transceivers are the power down and reset capabilities, external voltage reference and bias circuitry, and hot swapping. calibration block the stratix ii gx device uses the ca libration block to calibrate the on-chip termination for the plls and their associated output buffers and the terminating resistors on the transcei vers. the calibration block counters the effects of process, voltage, an d temperature (pvt). the calibration block references a derived voltage across an external reference resistor to calibrate the on-chip termination resist ors on the stratix ii gx device. the calibration block can be powered down. however, powering down the calibration block during operations may yield transmit and receive data errors. dynamic reconfiguration this feature allows you to dynamically reconfigure the pma portion and the channel parameters, such as data rate and functional mode, of the stratix ii gx transceiver. the pma reconfiguration allows you to quickly optimize the settings for the transc eiver?s pma to achieve the intended bit error rate (ber). table 2?15. available clocking connecti ons for transceivers in 2sgx130g region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o bank 15 8 clock i/o bank 16 8 clock i/o bank 17 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 v region2 8 lrio clock v rclk 12-19 vv region3 8 lrio clock v rclk 12-19 vv
2?42 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers the dynamic reconfiguration block can dynamically reconfigure the following pma settings: pre-emphasis settings equalizer and dc gain settings voltage output differential (v od ) settings the channel reconfiguration allows you to dynamically modify the data rate, local dividers, and the function al mode of the transceiver channel. f refer to the stratix ii gx de vice handbook , volume 2 , for more information. the dynamic reconfiguration block requires an input clock between 2.5 mhz and 50 mhz. the clock for th e dynamic reconfiguration block is derived from a high-speed clock and divided down using a counter. individual power down and reset for the transmitter and receiver stratix ii gx transceivers offer a power saving advantage with their ability to shut off functions that are not needed. the device can individually reset the receiver and transmitter blocks and the plls. the stratix ii gx device can either globally or individually power down and reset the transceiver. table 2?16 shows the connectivity between the reset signals and the stratix ii gx transceiver blocks. these reset signals can be controlled from the fpga or pins.
altera corporation 2?43 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture voltage reference capabilities stratix ii gx transceivers provide voltage reference and bias circuitry. to set up internal bias for controlling the transmitter output driver voltage swings, as well as to provide voltag e and current biasin g for other analog circuitry, the device uses an internal bandgap voltage reference of 0.7 v. an external 2-k resistor connected to ground generates a constant bias current (independent of power supply drift, process changes, or temperature variation). an on-chip resistor generates a tracking current that tracks on-chip resi stor variation. these cu rrents are mirrored and distributed to the analog circuitry in each channel. f for more information, refer to the dc and switching characteristics chapter in volume 1 of the stratix ii gx handbook . table 2?16. reset signal map to stratix ii gx blocks reset signal transmitter phase com pensation fifo module/ byte serializer transmitter 8b/10b encoder transmitter serializer transmitter analog circuits transmitter pll transmitter xaui state machine bist generators receiver deserializer receiver word aligner receiver deskew fifo module receiver rate matcher receiver 8b/10b decoder receiver phase comp fifo module/ byte deserializer receiver pll / cru receiver xaui state machine bist verifiers receiver analog circuits rx_digitalreset vvvvv vv rx_analogreset vvv tx_digitalreset vv vv gxb_powerdown vvvvvvvvvvvvvvvvv gxb_enable vvvvvvvvvvvvvvvvv
2?44 altera corporation stratix ii gx device handbook, volume 1 october 2007 logic array blocks applications and protocols supported with stratix ii gx devices each stratix ii gx transceiver block is designed to operate at any serial bit rate from 600 mbps to 6.375 gbps per channel. the wide data rate range allows stratix ii gx transceivers to su pport a wide variety of standards and protocols, such as pci express, gige, sone t/sdh, sdi, oif-cei, and xaui. stratix ii gx devices are ideal for many high-speed communication applications, such as high-speed backplanes, chip-to-chip bridges, and high-speed serial communications links. example applications support for stratix ii gx stratix ii gx devices can be used for many applications, including: traffic management with various le vels of quality of service (qos) and integrated serial backplane interconnect multi-port single-protocol switch ing (for example, pci express, gige, xaui switch, or sonet/sdh) logic array blocks each logic array block (lab) consists of eight adaptive logic modules (alms), carry chains, shared arithmetic chains, lab control signals, local interconnects, and register chain conn ection lines. the local interconnect transfers signals between alms in the same lab. register chain connections transfer the output of an alm register to the adjacent alm register in a lab. the quartus ii co mpiler places asso ciated logic in a lab or adjacent labs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. table 2?17 shows stratix ii gx device resources. figure 2?32 shows the stratix ii gx lab structure. table 2?17. stratix ii gx device resources device m512 ram columns/blocks m4k ram columns/blocks m-ram blocks dsp block columns/blocks lab columns lab rows ep2sgx30 6/202 4/144 1 2/16 49 36 ep2sgx60 7/329 5/255 2 3/36 62 51 ep2sgx90 8/488 6/408 4 3/48 71 68 ep2sgx130 9/699 7/609 6 3/63 81 87
altera corporation 2?45 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?32. stratix ii gx lab structure lab interconnects the lab local interconnect can drive all eight alms in the same lab. it is driven by column and row interc onnects and alm outputs in the same lab. neighboring labs, m512 ra m blocks, m4k ram blocks, m-ram blocks, or digital signal processing (dsp) blocks from the left and right can also drive a lab?s local interconnect through the direct link connection. the direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. each alm can drive 24 alms through fast local and direct link interconnects. direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block alms
2?46 altera corporation stratix ii gx device handbook, volume 1 october 2007 logic array blocks figure 2?33 shows the direct link connection. figure 2?33. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its alms. the control signals include three clocks, three clock enables, two asynchronous clears, synchronous clea r, asynchronous preset/load, and synchronous load control signals, providing a maximum of 11 control signals at a time. although synchr onous load and clear signals are generally used when implementing coun ters, they can also be used with other functions. each lab can use three clocks and th ree clock enable signals. however, there can only be up to two unique cl ocks per lab, as shown in the lab control signal generation circuit in figure 2?34 . each lab?s clock and clock enable signals are linked. for example, any alm in a particular lab using the labclk1 signal also uses labclkena1 . if the lab uses both the rising and falling edges of a clock, it also uses two lab-wide clock signals. de-asserting the clock enable signal turns off the corresponding lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous lo ad/preset signal. the asynchronous lab alms direct link interconnect to ri g ht direct link interconnect from ri g ht lab, trimatrix memory block, dsp block, or ioe output direct link interconnect from left lab, trimatrix tm memory block, dsp block, or input/output element (ioe) local interconnect direct link interconnect to left
altera corporation 2?47 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture load acts as a preset when the asynch ronous load data input is tied high. when the asynchronous load/p reset signal is used, the labclkena0 signal is no longer available. the lab row clocks [5..0] and lab local interconnect generate the lab-wide control signals. the multitrack? interconnects have inherently low skew. this low skew allows the multitrack interconnects to distribute clock and control signals in addition to data. figure 2?34 shows the lab control signal generation circuit. figure 2?34. lab-wide control signals dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclk2 syncload labclkena0 or asyncload or labpreset labclk0 labclk1 labclr1 labclkena1 labclkena2 labclr0 synclr 6 6 6 there are two unique clock signals per lab.
2?48 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules adaptive logic modules the basic building block of logic in th e stratix ii gx architecture is the alm. the alm provides advanced features with efficient logic utilization. each alm contains a variety of look-up table (lut)-based resources that can be divided between two adaptive luts (aluts). with up to eight inputs to the two al uts, one alm can implement various combinations of two functions. this adaptability allo ws the alm to be completely backward-compatible with four-input lut architectures. one alm can also implement any function of up to six inputs and certain seven-input functions. in addition to the adaptive lut-base d resources, each alm contains two programmable registers, two dedicate d full adders, a carry chain, a shared arithmetic chain, and a regi ster chain. through these dedicated resources, the alm can efficientl y implement various arithmetic functions and shift registers. each al m drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. figure 2?35 shows a high-level block diagram of the stratix ii gx alm while figure 2?36 shows a detailed view of all the connections in the alm. figure 2?35. high-level block diagram of the stratix ii gx alm dq to general or local routing reg0 to general or local routing datae0 dataf0 shared_arith_in shared_arith_out reg_chain_in reg_chain_out adder0 dataa datab datac datad combinational logic datae1 dataf1 dq to general or local routing reg1 to general or local routing adder1 carry_in carry_out
altera corporation 2?49 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?36. stratix ii gx alm details prn/ald clrn d a data ena q prn/ald clrn d a data ena q 4-input lut 3-input lut 3-input lut 4-input lut 3-input lut 3-input lut dataa datac datae0 dataf0 dataf1 datae1 datab datad v cc reg_chain_in sclr asyncload syncload ena[2..0] shared_arith_in carry_in carry_out clk[2..0] local interconnect row, column & direct link routing row, column & direct link routing local interconnect row, column & direct link routing row, column & direct link routing reg_chain_out shared_arith_out aclr[1..0] local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect
2?50 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules one alm contains two programmable registers. each register has data, clock, clock enable, synchronous and asynchronous clear, asynchronous load data, and synchronous and as ynchronous load/preset inputs. global signals, general-purpose i/o pi ns, or any internal logic can drive the register?s clock and clear control signals. either ge neral-purpose i/o pins or internal logic can drive th e clock enable, preset, asynchronous load, and asynchronous load data. the asynchronous load data input comes from the datae or dataf input of the alm, which are the same inputs that can be used for register packing. for combinational functions, the register is bypassed and the output of the lut drives directly to the outputs of the alm. each alm has two sets of outputs that drive the local, row, and column routing resources. the lut, adder, or register output can drive these output drivers independently (see figure 2?36 ). for each set of output drivers, two alm outputs can drive co lumn, row, or direct link routing connections, and one of these al m outputs can also drive local interconnect resources. this allows the lut or adder to drive one output while the register drives another outp ut. this feature, called register packing, improves device utilization because the device can use the register and the combinational logi c for unrelated functions. another special packing mode allows the regist er output to feed back into the lut of the same alm so that the register is packed with its own fan-out lut. this feature provides another mech anism for improved fitting. the alm can also drive out registered and unregistered versions of the lut or adder output. f see the stratix ii performance and logic efficiency analysis white paper for more information on the efficienci es of the stratix ii gx alm and comparisons with previous architectures. alm operating modes the stratix ii gx alm can operate in one of the following modes: normal mode extended lut mode arithmetic mode shared arithmetic mode each mode uses alm resources differently. each mode has 11 available inputs to the alm (see figure 2?35 )?the eight data inputs from the lab local interconnect; carry-in from the previous alm or lab; the shared arithmetic chain connection from th e previous alm or lab; and the register chain connection?are directed to different destinations to implement the desired logic function. lab-wide signals provide clock,
altera corporation 2?51 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. these lab wide signals are available in all alm modes. refer to ?lab control signals? on page 2?46 for more information on the lab-wide control signals. the quartus ii software and supported third-party synthesis tools, in conjunction with parameterized functions such as library of parameterized modules (lpm) func tions, automatic ally choose the appropriate mode for common func tions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that spec ify which alm operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinational functions. in this mode , up to eight data inputs from the lab local interconnect are inputs to the combinational logic. the normal mode allows two functions to be impl emented in one stratix ii gx alm, or an alm to implement a single func tion of up to six inputs. the alm can support certain combinations of completely independent functions and various combinations of func tions which have common inputs. figure 2?37 shows the supported lut combinations in normal mode.
2?52 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?37. alm in normal mode note (1) note to figure 2?37 : (1) combinations of functions with less inputs than those shown are also suppo rted. for exam ple, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc. the normal mode provides complete backward compatibility with four-input lut architectures. two in dependent functions of four inputs or less can be implemented in one stratix ii gx alm. in addition, a five-input function and an indepe ndent three-input function can be implemented withou t sharing inputs. 6-input lut dataf0 datae0 dataf0 datae0 dataa datab dataa datab datab datac datac dataf0 datae0 dataa datac 6-input lut datad datad datae1 combout0 combout1 combout0 combout1 combout0 combout1 dataf1 datae1 dataf1 datad datae1 dataf1 4-input lut 4-input lut 4-input lut 6-input lut dataf0 datae0 dataa datab datac datad combout0 5-input lut 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut 3-input lut
altera corporation 2?53 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture to pack two five-input functions in to one alm, the functions must have at least two common inputs. the common inputs are dataa and datab . the combination of a four-input func tion with a five -input function requires one common input (either dataa or datab ). to implement two six-input functions in one alm, four inputs must be shared and the combinational function must be the same. for example, a 4 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one alm, as shown in figure 2?38 . the shared inputs are dataa , datab , datac , and datad , while the unique select lines are datae0 and dataf0 for function0 , and datae1 and dataf1 for function1 . this crossbar switch consumes four luts in a four-input lut-based architecture. figure 2?38. 4 2 crossbar switch example in a sparsely used device, function s that could be placed into one alm can be implemented in separate alms. the quartus ii compiler spreads a design out to achieve the best possible performance. as a device begins to fill up, the quartus ii software au tomatically utilizes the full potential of the stratix ii gx alm. the quartu s ii compiler automatically searches for functions of common inputs or completely independent functions to be placed into one alm and to make effi cient use of the device resources. in addition, you can manually control resource usage by setting location assignments. any six-input function can be implemented utilizing inputs dataa , datab , datac , datad , and either datae0 and dataf0 or datae1 and dataf1 . if datae0 and dataf0 are utilized, the output is driven to register0 , and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (see figure 2?39 ). if datae1 and dataf1 are utilized, the output drives to register1 and/or bypasses register1 and drives to the interconnect six-input lut (function0) dataf0 datae0 dataa datab datac six-input lut (function1) datad datae1 combout0 combout1 dataf1 inputa sel0[1..0] sel1[1..0] inputb inputc inputd out0 out1 4 2 crossbar switch implementation in 1 alm
2?54 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules using the bottom set of output dr ivers. the quartu s ii compiler automatically selects the inputs to th e lut. asynchronous load data for the register comes from the datae or dataf input of the alm. alms in normal mode support register packing. figure 2?39. 6-input function in normal mode notes (1) , (2) notes to figure 2?39 : (1) if datae1 and dataf1 are used as inputs to the six-input function, datae0 and dataf0 are available for register packing. (2) the dataf1 input is available for register packing only if the six-input function is un-registered. extended lut mode the extended lut mode is used to implement a specific set of seven-input functions. the set must be a 2-to-1 multiplexer fed by two arbitrary five-inp ut functions sharing four inputs. figure 2?40 shows the template of supported seven-input functions utilizing extended lut mode. in this mode, if the seven-in put function is unregistered, the unused eighth input is available for register packing. functions that fit into the template shown in figure 2?40 occur naturally in designs. these functions often appear in designs as ?if-else? statements in verilog hdl or vhdl code. 6-input lut dataf0 datae0 dataa datab datac datad datae1 dataf1 dq dq to general or local routing to general or local routing to general or local routing reg0 reg1 these inputs are available for register packing. (2)
altera corporation 2?55 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?40. template for supported sev en-input functions in extended lut mode note to figure 2?40 : (1) if the seven-input function is un-registered, the unused eighth input is available for register packing. the second register, reg1 , is not available. arithmetic mode the arithmetic mode is ideal for implementing adders, counters, accumulators, wide pari ty functions, and comp arators. an alm in arithmetic mode uses two sets of two four-input luts along with two dedicated full adders. the dedicated adders allow the luts to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. the four luts share the dataa and datab inputs. as shown in figure 2?41 , the carry-in signal feeds to adder0 , and the carry-out from adder0 feeds to carry-in of adder1 . the carry-out from adder1 drives to adder0 of the next alm in the lab. alms in arithmetic mode can drive out registered and/or un-registered versions of the adder outputs. datae0 combout0 5-input lut 5-input lut datac dataa datab datad dataf0 datae1 dataf1 dq to general or local routing to general or local routing reg0 this input is available for register packing. (1)
2?56 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?41. alm in arithmetic mode while operating in arithmetic mode, the alm can support simultaneous use of the adder?s carry output along with combinational logic outputs. in this operation, the ad der output is ignored. this usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. an example of such functionality is a conditional operation, such as the one shown in figure 2?42 . the equation for this example is: r = (x < y) ? y : x to implement this function, the adder is used to subtract ?y? from ?x?. if ?x? is less than ?y?, the carry_out signal will be ?1?. the carry_out signal is fed to an adder where it drives out to the lab local interconnect. it then feeds to the lab-wide syncload signal. when asserted, syncload selects the syncdata input. in this case , the data ?y? drives the syncdata inputs to the registers. if ?x? is greater than or equal to ?y?, the syncload signal is de-asserted and ?x? drives the data port of the registers. dataf0 datae0 carry_in carry_out dataa datab datac datad datae1 dataf1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut adder1 adder0
altera corporation 2?57 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?42. conditional operation example the arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, synchronous clear, sync hronous load. the lab local interconnect data inputs generate the clock enable, counter enable, synchronous up and down and add and subtract control si gnals. these control signals may be used for the inputs that are shared between the four luts in the alm. the synchronous clear and synchron ous load options are lab-wide signals that affect all registers in the lab. the quartus ii software automatically places any registers that are not used by the counter into other labs. y[1] y[0] x[0] x[0] carry_out x[2] x[2] x[1] x[1] y[2] dq to general or local routing reg0 comb & adder logic comb & adder logic comb & adder logic comb & adder logic dq to general or local routing reg1 dq to general or local routing to local routing & then to lab-wide syncload reg0 syncload syncload syncload alm 1 alm 2 r[0] r[1] r[2] carry chain adder output is not used. syncdata
2?58 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules carry chain the carry chain provides a fast ca rry function between the dedicated adders in arithmetic or shared arithmetic mode. carry chains can begin in either the first alm or the fifth alm in a lab. the final carry-out signal is routed to an alm, where it is fed to local, row, or column interconnects. the quartus ii compiler automatically creates carry chain logic during compilation, or you can create it manually during design entry. parameterized functions, such as lpm functions, au tomatically take advantage of carry chains for the a ppropriate functions. the quartus ii compiler creates carry chains longer than 16 (8 alms in arithmetic or shared arithmetic mode) by linking labs together automatically. for enhanced fitting, a long carry chai n runs vertically, allowing fast horizontal connections to trimatrix memory an d dsp blocks. a carry chain can continue as far as a full co lumn. to avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the lab can support carry chains that only utilize either the top half or the bottom half of the lab before connecting to the next lab. the other half of the alms in the lab is available for implementing narrower fan-in functions in normal mode. carry chains that use the top four alms in the first lab will carry into the top half of the alms in the next lab within the column. carry ch ains that use the bottom four alms in the first lab will carry into the b ottom half of the alms in the next lab within the column. every other column of the labs are top-half bypassable, while the other lab co lumns are bottom-half bypassable. refer to ?multitrack interconnect? on page 2?63 for more information on carry chain interconnect. shared arithmetic mode in shared arithmetic mode, the alm can implement a three-input add. in this mode, the alm is configured with four 4-input luts. each lut either computes the sum of three inpu ts or the carry of three inputs. the output of the carry computation is fed to the next adder (either to adder1 in the same alm or to adder0 of the next alm in the lab) using a dedicated connection called the shared arithmetic chain. this shared arithmetic chain can significantly im prove the performance of an adder tree by reducing the number of summ ation stages required to implement an adder tree. figure 2?43 shows the alm in shared arithmetic mode.
altera corporation 2?59 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?43. alm in shared arithmetic mode note to figure 2?43 : (1) inputs dataf0 and dataf1 are available for register pack ing in shared arithmetic mode. adder trees are used in many different applications. for example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. another example is a corr elator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data which was transmitted utilizing spread spectrum technology. an ex ample of a three-bit add operation utilizing the shared arithmetic mode is shown in figure 2?44 . the partial sum ( s[2..0] ) and the partial carry ( c[2..0] ) is obtained using the luts, while the result ( r[2..0] ) is computed using the dedicated adders. datae0 carry_in shared_arith_in shared_arith_out carry_out dataa datab datac datad datae1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut
2?60 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?44. example of a 3-bit add utilizing shared arithmetic mode shared arithmetic chain in addition to the dedicated carry chai n routing, the shared arithmetic chain available in shared arithmetic mode allows the alm to implement a three-input add, which significantl y reduces the resources necessary to implement large adder trees or co rrelator functions. the shared arithmetic chains can begi n in either the first or fifth alm in a lab. the quartus ii compiler automatically links labs to create shared arithmetic chains longer than 16 (8 alms in arit hmetic or shared arithmetic mode). for enhanced fitting, a long shared arithmetic chain runs vertically carry_in = '0' shared_arith_in = '0' z0 y0 x0 binary add decimal equivalents + z1 x1 r0 c0 s0 s1 s2 c1 c2 '0' r1 y1 3-input lut 3-input lut 3-input lut 3-input lut z2 y2 x2 r2 r3 3-input lut 3-input lut 3-input lut 3-input lut alm 1 3-bit add example alm implementation alm 2 x2 x1 x0 y2 y1 y0 z2 z1 z0 s2 s1 s0 c2 c1 c0 r3 r2 r1 r0 + + 1 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 0 1 + + 6 5 2 1 2 x 6 13 + 2nd stage add is implemented in adders. 1st stage add is implemented in luts.
altera corporation 2?61 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture allowing fast horizontal connec tions to trimatrix memory and dsp blocks. a shared arithmet ic chain can continue as far as a full column. similar to the carry chains, the shared arithmetic chains are also top- or bottom-half bypassable. th is capability allows the shared arithmetic chain to cascade through half of the alms in a lab while leaving the other half available for narrower fan-in functionality. every other lab column is top-half bypassable, while the other lab columns are bottom-half bypassable. refer to ?multitrack interconnect? on page 2?63 for more information on shared arithmetic chain interconnect. register chain in addition to the general routing ou tputs, the alms in a lab have register chain outputs. the register chain routing allows registers in the same lab to be cascaded together. th e register chain interconnect allows a lab to use luts for a single combin ational function and the registers to be used for an unrelated shift re gister implementation. these resources speed up connections between alms while saving local interconnect resources (see figure 2?45 ). the quartus ii comp iler automatically takes advantage of these resources to improve utilization and performance. see ?multitrack interconnect? on page 2?63 for more information about register chain interconnect.
2?62 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?45. register c hain within a lab note (1) note to figure 2?45 : (1) the combinational or adder logic can be utilized to implement an unrelated, un-registered function. dq to general or local routing reg0 to general or local routing reg_chain_in adder0 dq to general or local routing reg1 to general or local routing adder1 dq to general or local routing reg0 to general or local routing reg_chain_out adder0 dq to general or local routing reg1 to general or local routing adder1 from previous alm within the lab to next alm within the lab combinational logic combinational logic
altera corporation 2?63 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture clear and preset logic control lab-wide signals control the logic for the register?s clear and load/preset signals. the alm directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynchro nous preset does not require a not gate push-back technique. stratix ii gx devices support simultaneous asynchronous load/preset and clear signals. an asynchronous clear signal takes precedence if both signals are asserted simultaneously. each lab supports up to two clears and one load/preset signal. in addition to the clear and load/preset ports, stratix ii gx devices provide a device-wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the quartus ii software controls this pin. this device-wide reset overrides all other control signals. multitrack interconnect in the stratix ii gx architecture, th e multitrack interconnect structure with directdrive technology prov ides connections between alms, trimatrix memory, dsp blocks, and device i/o pins. the multitrack interconnect consists of continuous , performance-optimi zed routing lines of different lengths and speeds used for inter- and intra-design block connectivity. the quartus ii compiler automatically places critical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. the multitrack interconnect and directdrive technology simplify the integration stage of bloc k-based designing by eliminating the re-optimization cycles that typi cally follow desi gn changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. dedicated row interconnects route signals to and from labs, dsp blocks, and trimatrix memory in the same row. these row resources include: direct link interconnects between labs and adjacent blocks r4 interconnects traversing fo ur blocks to the right or left r24 row interconnects for high-speed access across the length of the device
2?64 altera corporation stratix ii gx device handbook, volume 1 october 2007 multitrack interconnect the direct link interconnect allows a lab, dsp block, or trimatrix memory block to drive into the local in terconnect of its left and right neighbors and then back into itself, providing fast communication between adjacent labs and/or bloc ks without using row interconnect resources. the r4 interconnects span four labs, three labs and one m512 ram block, two labs and one m4k ram block, or two labs and one dsp block to the right or left of a source lab. these resources are used for fast row connections in a four-lab region . every lab has its own set of r4 interconnects to drive either left or right. figure 2?46 shows r4 interconnect connections from a lab. r4 interconnects can drive and be driven by dsp blocks and ram blocks and row ioes. for lab interfacing, a primary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects that drive to the right, the primary lab and right neighbor can drive onto the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive onto the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 an d c16 interconnects for connections from one row to another. additional ly, r4 interconnects can drive r24 interconnects. figure 2?46. r4 interconnect connections notes (1) , (2) , (3) notes to figure 2?46 : (1) c4 and c16 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. (3) the labs in figure 2?46 show the 16 possible logical outputs per lab. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 and c16 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
altera corporation 2?65 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture r24 row interconnects span 24 labs and provide the fastest resource for long row connections between labs, trimatrix memory, dsp blocks, and row ioes. the r24 row interconnects can cross m-ram blocks. r24 row interconnects drive to other row or column interconnects at every fourth lab and do not drive directly to lab local interconnects. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects. r24 interconnects can drive r24, r4 , c16, and c4 interconnects. the column interconnect operates simi larly to the row interconnect and vertically routes signals to and from labs, trimatrix memory, dsp blocks, and ioes. each column of labs is served by a dedicated column interconnect. these column resources include: shared arithmetic chain interconnects in a lab carry chain interconnects in a lab and from lab to lab register chain interconnects in a lab c4 interconnects traversing a distan ce of four blocks in an up and down direction c16 column interconnects for high -speed vertical routing through the device stratix ii gx devices include an enha nced interconnect structure in labs for routing shared arithmetic chai ns and carry chains for efficient arithmetic functions. the register chain connection allows the register output of one alm to connect directly to the register input of the next alm in the lab for fast shift regi sters. these alm-to-alm connections bypass the local interconnect. the quartus ii compil er automatically takes advantage of these resources to improve utilization and performance. figure 2?47 shows the shared arithmet ic chain, carry chain, and register chain interconnects.
2?66 altera corporation stratix ii gx device handbook, volume 1 october 2007 multitrack interconnect figure 2?47. shared arithmetic chain, carry chain and r egister chai n interconnects the c4 interconnects span four labs , m512, or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?48 shows the c4 interc onnect connections from a lab in a column. the c4 interconnects can drive and be driven by all types of architecture blocks, including dsp bl ocks, trimatrix memory blocks, and column and row ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for colu mn-to-column connections. alm 1 alm 2 alm 3 alm 4 alm 5 alm 6 alm 8 alm 7 carry chain & shared arithmetic chain routing to adjacent alm local interconnect register chain routing to adjacent alm's register input local interconnect routing among alms in the lab
altera corporation 2?67 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?48. c4 inte rconnect connections note (1) note to figure 2?48 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect
2?68 altera corporation stratix ii gx device handbook, volume 1 october 2007 multitrack interconnect c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, trimatrix memory blocks, dsp blocks, and ioes. c16 interconnects can cross m-ram blocks and also drive to row and column interconnects at every fourth lab. c16 interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. all embedded blocks communicate with the logic array similar to lab-to-lab interfaces. each block (that is, trimatrix memory and dsp blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these blocks also have direct link intercon nects for fast connections to and from a neighboring lab. all blocks are fed by the row lab clocks, labclk[5..0] . table 2?18 shows the stratix ii gx device?s routing scheme. table 2?18. stratix ii gx device routing scheme (part 1 of 2) source destination shared arithmetic chain carry chain register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect alm m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe shared arithmetic chain v carry chain v register chain v local interconnect vvvvvvv direct link interconnect v r4 interconnect v vvvv r24 interconnect vvvv c4 interconnect vvv c16 interconnect vvvv alm vvvvvv v m512 ram block vvv v m4k ram block vvv v m-ram block vvvv dsp blocks vv v
altera corporation 2?69 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture trimatrix memory trimatrix memory consists of three types of ram blocks: m512, m4k, and m-ram. although thes e memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port ram, rom, and fifo buffers. table 2?19 shows the size and features of the different ram blocks. column ioe vvv row ioe vvvv table 2?18. stratix ii gx device routing scheme (part 2 of 2) source destination shared arithmetic chain carry chain register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect alm m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe table 2?19. trimatrix memory features (part 1 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (128 36 bits) m-ram block (4k 144 bits) maximum performance 500 mhz 550 mhz 420 mhz true dual-port memory vv simple dual-port memory vvv single-port memory vvv shift register vv rom vv (1) fifo buffer vvv pack mode vv byte enable vvv address clock enable vv parity bits vvv mixed clock mode vvv memory initialization ( .mif ) vv
2?70 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory trimatrix memory provides three different memory sizes for efficient application support. the quartus ii software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. you can also manually assign the memory to a specific block size or a mixture of block sizes. m512 ram block the m512 ram block is a simple dual-port memory block and is useful for implementing small fifo buffers, dsp, and clock domain transfer applications. each block contains 576 ram bits (includin g parity bits). m512 ram blocks can be configured in the following modes: simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. simple dual-port memory mixed width support vvv true dual-port memory mixed width support vv power-up conditions outputs cleare d outputs cleared outputs unknown register clears output registers output registers output registers mixed-port read-during-write unknown output/old data unknown output/old data unknown output configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 note to table 2?19 : (1) violating the setup or hold time on the memory bl ock address registers could corrupt memory contents. this applies to both read and write operations. table 2?19. trimatrix memory features (part 2 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (128 36 bits) m-ram block (4k 144 bits)
altera corporation 2?71 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture m512 ram blocks can have different cl ocks on its inputs and outputs. the wren , datain , and write address registers are all clocked together from one of the two cl ocks feeding the block. the read address, rden , and output registers can be clocked by ei ther of the two cl ocks driving the block, allowing the ram block to oper ate in read and write or input and output clock modes. only the output register can be bypassed. the six labclk signals or local interconnect can drive the inclock , outclock , wren , rden , and outclr signals. because of the advanced interconnect between the lab and m512 ram bloc ks, alms can also control the wren and rden signals and the ram clock, clock enable, and asynchronous clear signals. figure 2?49 shows the m512 ram block control signal generation logic. figure 2?49. m512 ram block control signals inclocken outclock inclock outclocken rden wren dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect outclr 6 local interconnect local interconnect
2?72 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory the ram blocks in stratix ii gx devi ces have local interconnects to allow alms and interconnects to drive into ram blocks. the m512 ram block local interconnect is driven by the r4, c4, and direct link interconnects from adjacent labs. the m512 ram bl ocks can communicate with labs on either the left or right side through these row interconnects or with lab columns on the left or right side with the column interconnects. the m512 ram block has up to 16 direct li nk input connections from the left adjacent labs and another 16 from the right adjacent lab. m512 ram outputs can also connect to left an d right labs through direct link interconnect. the m512 ram block has equal opportunity for access and performance to and from labs on either its left or right side. figure 2?50 shows the m512 ram block to logic array interface. figure 2?50. m512 ram block lab row interface dataout m4k ram block datain address 16 36 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnect r4 interconnect lab row clocks clocks byte enable control signals 6
altera corporation 2?73 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture m4k ram blocks the m4k ram block includes support for true dual-port ram. the m4k ram block is used to implement buffer s for a wide variety of applications such as storing processor code, im plementing lookup schemes, and implementing larger memory applications. each block contains 4,608 ram bits (including parity bits). m4k ram blocks can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. the m4k ram blocks allow for differ ent clocks on their inputs and outputs. either of the two clocks feeding the block can clock m4k ram block registers ( renwe , address , byte enable , datain , and output registers). only the output register can be bypassed. the six labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k ram block. alms can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?51 .
2?74 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory figure 2?51. m4k ram bl ock control signals the r4, c4, and direct link interconnects from adjacent labs drive the m4k ram block local interconnect. the m4k ram blocks can communicate with labs on either the left or righ t side through these row resources or with lab columns on either the right or left with the column resources. up to 16 direct link inpu t connections to the m4k ram block are possible from the left adjacent labs and another 16 possible from the right adjacent lab. m4k ram block outputs can also connect to left and right labs through direct link interconnect. figure 2?52 shows the m4k ram block to logic array interface. clock_b clocken_a clock_a clocken_b aclr_b aclr_a dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect renwe_b renwe_a 6
altera corporation 2?75 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?52. m4k ram block lab row interface m-ram block the largest trimatrix memory block, the m-ram block, is useful for applications where a large volume of data must be stored on-chip. each block contains 589,824 ram bits (inc luding parity bits). the m-ram block can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo you cannot use an initialization file to initialize the contents of a m-ram block. all m-ram block contents powe r up to an undefined value. only synchronous operation is supported in the m-ram block, so all inputs are registered. output registers can be bypassed. dataout m4k ram block datain address 16 36 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnect r4 interconnect lab row clocks clocks byte enable control signals 6
2?76 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory similar to all ram blocks, m-ram bloc ks can have different clocks on their inputs and outputs. either of the two clocks feeding the block can clock m-ram block registers ( renwe , address , byte enable, datain , and output registers). the output register can be bypassed. the six labclk signals or local interconnect can drive the control signals for the a and b ports of the m-ram block. alms can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?53 . figure 2?53. m-ram block control signals the r4, r24, c4, and direct link interconnects from adjacent labs on either the right or left side drive the m-ram block local interconnect. up to 16 direct link input connections to the m-ram block are possible from the left adjacent labs and another 16 possible from the right adjacent lab. m-ram block outputs can also connect to left and right labs through direct link interconnect. figure 2?54 shows an example floorplan for the ep2sgx130 device and the location of the m-ram interfaces. figures 2?55 and 2?56 show the interface between the m-ram block and the logic array. clock_a clock_b clocken_a clocken_b aclr_a aclr_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect renwe_a renwe_b 6 local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect
altera corporation 2?77 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?54. ep2sgx130 device with m-ram interface locations note (1) note to figure 2?54 : (1) the device shown is an ep2sgx130 device. the number and po sition of m-ram blocks varies in other devices. dsp blocks dsp blocks m4k blocks m512 blocks labs m-ram block m-ram block m-ram block m-ram block m-ram block m-ram block m-ram blocks interface to labs on right and left sides for easy access to horizontal i/o pins
2?78 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory figure 2?55. m-ram block lab row interface note (1) note to figure 2?55 : (1) only r24 and c16 interconnects cross the m-ram block boundaries. m-ram block port b port a row unit interface allows lab rows to drive port b datain, dataout, address and control signals to and from m-ram block row unit interface allows lab rows to drive port a datain, dataout, address and control signals to and from m-ram block labs in row m-ram boundary labs in row m-ram boundary lab interface blocks l0 l1 l2 l3 l4 l5 r0 r1 r2 r3 r4 r5
altera corporation 2?79 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?56. m-ram row unit interface to interconnect lab row interface block m-ram block 16 up to 28 datain_a[ ] addressa[ ] addr_ena_a renwe_a byteena_a[ ] clocken_a clock_a aclr_a m-ram block to lab row interface block interconnect region r4 and r24 interconnects c4 interconnect direct link interconnects dataout_a[ ] up to 16
2?80 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory table 2?20 shows the input and output data signal connections along with the address and control signal input connections to the row unit interfaces (l0 to l5 and r0 to r5). f refer to the trimatrix embedded memory blocks in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on trimatrix memory. table 2?20. m-ram row interface unit signals unit interface block input signals output signals l0 datain_a[14..0] byteena_a[1..0] dataout_a[11..0] l1 datain_a[29..15] byteena_a[3..2] dataout_a[23..12] l2 datain_a[35..30] addressa[4..0] addr_ena_a clock_a clocken_a renwe_a aclr_a dataout_a[35..24] l3 addressa[15..5] datain_a[41..36] dataout_a[47..36] l4 datain_a[56..42] byteena_a[5..4] dataout_a[59..48] l5 datain_a[71..57] byteena_a[7..6] dataout_a[71..60] r0 datain_b[14..0] byteena_b[1..0] dataout_b[11..0] r1 datain_b[29..15] byteena_b[3..2] dataout_b[23..12] r2 datain_b[35..30] addressb[4..0] addr_ena_b clock_b clocken_b renwe_b aclr_b dataout_b[35..24] r3 addressb[15..5] datain_b[41..36] dataout_b[47..36] r4 datain_b[56..42] byteena_b[5..4] dataout_b[59..48] r5 datain_b[71..57] byteena_b[7..6] dataout_b[71..60]
altera corporation 2?81 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture digital signal processing (dsp) block the most commonly used dsp function s are finite impuls e response (fir) filters, complex fir filter s, infinite impulse response (iir) filters, fast fourier transform (fft) functions, direct cosine transform (dct) functions, and correlators. all of these use the multiplier as the fundamental building block. additionally, some applications need specialized operations such as mul tiply-add and multiply-accumulate operations. stratix ii gx devices provide dsp blocks to meet the arithmetic requirements of these functions. each stratix ii gx device has tw o to four columns of dsp blocks to efficiently implement dsp functions faster than alm-based implementations. stratix ii gx de vices have up to 24 dsp blocks per column (see table 2?21 ). each dsp block can be configured to support up to: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier as indicated, the stratix ii gx dsp block can support one 36 36-bit multiplier in a single dsp block, and is true for any combination of signed, unsigned, or mixed sign multiplications.
2?82 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block figures 2?57 shows one of the columns with surrounding lab rows. figure 2?57. dsp blocks arranged in columns dsp block column 4 lab rows dsp block
altera corporation 2?83 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?21 shows the number of dsp blocks in each stratix ii gx device. dsp block multipliers can optionally feed an adder/subtractor or accumulator in the block, depending on the configuration, which makes routing to alms easier, saves alm routing resources, and increases performance because all connections and blocks are in the dsp block. additionally, the dsp block input regi sters can efficiently implement shift registers for fir filter applications, and dsp blocks support q1.15 format rounding and saturation. figure 2?58 shows the top-level diagram of the dsp block configured for 18 18-bit multiplier mode. table 2?21. dsp blocks in stratix ii gx devices note (1) device dsp blocks total 9 9 multipliers total 18 18 multipliers total 36 36 multipliers ep2sgx30 16 128 64 16 ep2sgx60 36 288 144 36 ep2sgx90 48 384 192 48 ep2sgx130 63 504 252 63 note to table 2?21 : (1) this list only shows functi ons that can fit into a single dsp block. multiple dsp blocks can support larger multiplication functions.
2?84 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block figure 2?58. dsp block diagram fo r 18 18-bit configuration adder/ subtractor/ accumulator 2 adder/ subtractor/ accumulator 1 summation optional pipeline register stage multiplier stage output selection multiplexer optional output register stage clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena optional serial shift register inputs from previous dsp block optional stage configurable as accumulator or dynamic adder/subtractor summation stage for adding four multipliers together optional input register stage with parallel input or shift register configuration optional serial shift register outputs to next dsp block in the column to multitrack interconnect
altera corporation 2?85 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture modes of operation the adder, subtractor, and accumulate functions of a dsp block have four modes of operation: simple multiplier multiply-accumulator two-multipliers adder four-multipliers adder table 2?22 shows the different number of multipliers possible in each dsp block mode according to size. these modes allow the dsp blocks to implement numerous applications for dsp including ffts, complex fir, fir, 2d fir filters, equalizers, iir, correlators, matrix multiplication, and many other functions. the dsp bloc ks also support mixed modes and mixed multiplier sizes in the same bl ock. for example, half of one dsp block can implement one 18 18-bit mu ltiplier in multiply-accumulator mode, while the other half of the ds p block implements four 9 9-bit multipliers in simple multiplier mode. dsp block interface the stratix ii gx device dsp block input registers can generate a shift register that can cascade down in the same dsp block column. dedicated connections between dsp blocks prov ide fast connections between the shift register inputs to cascade the shift register chains. you can cascade registers within multiple dsp blocks for 9 9- or 18 18-bit fir filters larger than four taps, with additi onal adder stages implemented in alms. if the dsp block is configured as 36 36 bits, the adder, subtractor, or accumulator stages are implemen ted in alms. each dsp block can route the shift register chain out of the block to cascade multiple columns of dsp blocks. table 2?22. multiplier size and configurations per dsp block dsp block mode 9 9 18 18 36 36 multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier with one product output multiply-accumulator ? two 52-bit multiply- accumulate blocks ? two-multipliers adder four two-multiplier adder (two 9 9 complex multiply) two two-multiplier adder (one 18 18 complex multiply) ? four-multipliers adder two four-multipl ier adder one four-multiplier adder ?
2?86 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block the dsp block is divided into four bl ock units that interface with four lab rows on the left and right. each block unit can be considered one complete 18 18-bit multiplier with 36 inputs and 36 outputs. a local interconnect region is associated with each dsp block. like a lab, this interconnect region can be fed with 16 direct link interconnects from the lab to the left or right of the dsp block in the same row. r4 and c4 routing resources can access the dsp block?s local interconnect region. the outputs also work similarly to la b outputs. eighteen outputs from the dsp block can drive to the left la b through direct link interconnects and 18 can drive to the right lab through direct link interconnects. all 36 outputs can drive to r4 and c4 routing interconnects. outputs can drive right- or left-column routing. figures 2?59 and 2?60 show the dsp block interfaces to lab rows. figure 2?59. dsp block interconnect interface a1[17..0] b1[17..0] a2[17..0] b2[17..0] a3[17..0] b3[17..0] a4[17..0] b4[17..0] oa[17..0] ob[17..0] oc[17..0] od[17..0] oe[17..0] of[17..0] og[17..0] oh[17..0] dsp block r4, c4 & direct link interconnects r4, c4 & direct link interconnects
altera corporation 2?87 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?60. dsp block interface to interconnect a bus of 44 control signals feeds the entire dsp block. these signals include clocks, asynchronous clears, clock enables, signed and unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. the clock signals are routed from lab row cloc ks and are generated from specific lab rows at the dsp block interface. the lab row source for control signals, data inputs, an d outputs is shown in table 2?23 . f refer to the dsp blocks in stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on dsp blocks. lab lab row interface block dsp block row structure 16 oa[17..0] ob[17..0] a[17..0] b[17..0] dsp block to lab row interface block interconnect region 36 inputs per row 36 outputs per row r4 interconnect c4 interconnect direct link interconnect from adjacent lab direct link outputs to adjacent labs direct link interconnect from adjacent lab 36 36 36 36 control 12 16 18
2?88 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block table 2?23. dsp block signal sources and destinations lab row at interface control signals generated data inputs data outputs 0 clock0 aclr0 ena0 mult01_saturate addnsub1_round/ accum_round addnsub1 signa sourcea sourceb a1[17..0] b1[17..0] oa[17..0] ob[17..0] 1 clock1 aclr1 ena1 accum_saturate mult01_round accum_sload sourcea sourceb mode0 a2[17..0] b2[17..0] oc[17..0] od[17..0] 2 clock2 aclr2 ena2 mult23_saturate addnsub3_round/ accum_round addnsub3 sign_b sourcea sourceb a3[17..0] b3[17..0] oe[17..0] of[17..0] 3 clock3 aclr3 ena3 accum_saturate mult23_round accum_sload sourcea sourceb mode1 a4[17..0] b4[17..0] og[17..0] oh[17..0]
altera corporation 2?89 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture plls and clock networks stratix ii gx devices provide a hierarchical clock structure and multiple phase-locked loops (plls) with adva nced features. the large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast plls provides a complete clock management solution. global and hierarchical clocking stratix ii gx devices provide 16 de dicated global cl ock networks and 32 regional clock networks (eight per device quadrant). these clocks are organized into a hierarchical clock stru cture that allows for up to 24 clocks per device region with low skew and delay. this hierarchical clocking scheme provides up to 48 unique cloc k domains in stratix ii gx devices. there are 12 dedicated clock pins to dr ive either the global or regional clock networks. four clock pins drive ea ch side of the device, as shown in figures 2?61 and 2?62 . internal logic and enhanced and fast pll outputs can also drive the global and region al clock networks. each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enable s or disables the clock to reduce power consumption. table 2?24 shows global and regional clock features. global clock network these clocks drive throughout the entire device, feeding all device quadrants. the global clock networks can be used as clock sources for all resources in the device ioes, alms, dsp blocks, and all memory blocks. these resources can also be used for control signals, such as clock enables and synchronous or asynch ronous clears fed from the external pin. the global clock networks can also be driv en by internal logic for internally table 2?24. global and regional clock features feature global clocks regional clocks number per device 16 32 number available per quadrant 16 8 sources clock pins, pll outputs, core routings, inter-transceiver clocks clock pins, pll outputs, core routings, inter-transceiver clocks dynamic clock source selection v ? dynamic enable/disable vv
2?90 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks generated global clocks and asynchrono us clears, clock enables, or other control signals with large fanout. figure 2?61 shows the 12 dedicated clk pins driving global clock networks. figure 2?61. global clocking regional clock network there are eight regional clock networks ( rclk[7..0] ) in each quadrant of the stratix ii gx device th at are driven by the dedicated clk[15..12] and clk[7..0] input pins, by pll outputs, or by internal logic. the regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. the clk pins symmetrically drive the rclk networks in a part icular quadrant, as shown in figure 2?62 . global clock [15..0] clk[15..12] clk[3..0] clk[7..4] global clock [15..0]
altera corporation 2?91 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?62. regional clocks dual-regional clock network a single source ( clk pin or pll output) can generate a dual-regional clock by driving two regi onal clock network lines in adjacent quadrants (one from each quadrant), which allows logic that spans multiple quadrants to utilize the same low skew clock. the routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant. internal logic-array routing can also drive a dual-regional clock. clock pins and enhanced pl l outputs on the top and bottom can drive horizontal dual-regional clocks. clock pins and fast pll outputs on the left and right can drive vertical dual-regional clocks, as shown in figure 2?63 . corner plls cannot drive dual-regional clocks. rclk [3..0] rclk [7..4] rclk [23..20] rclk [19..16] rclk [11..8] rclk [15..12] rclk [31..28] rclk [27..24] stratix ii gx transceiver block stratix ii gx transceiver block 12 6 11 5 clk[7..4] clk[15..12] clk[3..0] 1 7 2 8
2?92 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?63. dual-reg ional clocks combined resources within each quadrant, there are 24 distinct dedicated clocking resources consisting of 16 global clock lines and 8 regional clock lines. multiplexers are used with these clocks to form bu ses to drive lab row clocks, column ioe clocks, or row ioe cl ocks. another multiplexer is used at the lab level to select three of the six row cl ocks to feed the alm registers in the lab (see figure 2?64 ). figure 2?64. hierarchical clock networks per quadrant clock pins or pll clock outputs can drive dual-regional network clk[15..12] clk[7..4] clk[3..0] plls plls clock pins or pll clock outputs can drive dual-regional network clk[15..12] clk[7..4] clk[3..0] clock [23..0] column i/o cell io_clk[7..0] lab row clock [5..0] row i/o cell io_clk[7..0] global clock network [15..0] regional clock network [7..0] clocks available to a quadrant or half-quadrant
altera corporation 2?93 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture ioe clocks have row and column bloc k regions that are clocked by 8 i/o clock signals chosen from the 24 quadrant clock resources. figures 2?65 and 2?66 show the quadrant relation ship to the i/o clock regions. figure 2?65. ep2sgx30 devi ce i/o clock groups io_clkc[7..0] io_clkf[7..0] io_clke[7..0] io_clka[7..0] io_clkb[7..0] io_clkd[7..0] io_clkh[7..0] io_clkg[7..0] 8 8 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 8 8 8 8 8 8 i/o clock regions
2?94 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?66. ep2sgx60, ep2sgx90 and ep 2sgx130 device i/o clock groups you can use the quartus ii software to control whether a clock input pin drives either a global, regional, or dual-regional clock network. the quartus ii software automatically se lects the clocking resources if not specified. clock control block each global clock, regional clock, and pll external cl ock output has its own clock control block. the co ntrol block has two functions: clock source selection (dynamic selection for global clocks) clock power-down (dynamic clock enable or disable) io_clkj[7..0] io_clki[7..0] io_clka[7..0] io_clkb[7..0] 8 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 8 8 8 i/o clock regions io_clkl[7..0] io_clkk[7..0] io_clkc[7..0] io_clkd[7..0] 888 8 8 8 8 8 8 8 8 8 io_clke[7..0] io_clkf[7..0] io_clkg[7..0] io_clkh[7..0] io_clkn[7..0] io_clkm[7..0] io_clkp[7..0] io_clko[7..0]
altera corporation 2?95 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figures 2?67 through 2?69 show the clock control block for the global clock, regional clock, and pll ex ternal clock outp ut, respectively. figure 2?67. global cloc k control blocks notes to figure 2?67 : (1) these clock select signals can be dynamically controlled th rough internal logic when the device is operating in user mode. (2) these clock select signals ca n only be set through a configuration file (sram object file [ .sof ] or programmer object file [ .pof ]) and cannot be dynamically contro lled during user mode operation. figure 2?68. regional clock control blocks notes to figure 2?68 : (1) these clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) only the clkn pins on the top and bottom of the de vice feed to regional clock select. clkp pins pll counter outputs internal logic clkn pin enable/ disable gclk internal logic static clock select this multiplexer supports user-controllable dynamic switching clkselect[1..0] (1) (2) 2 2 2 clkp pin pll counter outputs internal logic clkn pin enable/ disable rclk internal logic static clock select (1) 2 (2)
2?96 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?69. external pll output clock control blocks notes to figure 2?69 : (1) these clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) the clock control block feed s to a multiplexer within the pll_out pin?s ioe. the pll_out pin is a dual-purpose pin. therefore, this multiplexer selects either an inte rnal signal or the output of the clock control block. for the global clock control block, the clock source selection can be controlled either statically or dyna mically. you have the option of statically selecting the clock source by using the quartus ii software to set specific configuration bits in the configuration file ( .sof or .pof ) or you can control the selection dynamically by using internal logic to drive the multiplexer select inputs . when selecting statically, the clock source can be set to any of the inputs to the se lect multiplexer. when selecting the clock source dynamically, you can eith er select between two pll outputs (such as the c0 or c1 outputs from one pll), between two plls (such as the c0 / c1 clock output of one pll or the c0 / c1 c1ock output of the other pll), between two clock pins (such as clk0 or clk1 ), or between a combination of clock pins or pll outputs. for the regional and pll_out clock control block, the clock source selection can only be controlled statically using configuration bits. any of the inputs to the clock select multiplex er can be set as the clock source. pll counter outputs (c[5..0]) enable/ disable pll_out pin internal lo g ic static clock select ioe (1) static clock select (1) 6 internal lo g ic (2)
altera corporation 2?97 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture the stratix ii gx clock networks can be disabled (powered down) by both static and dynamic approaches. when a clock net is powered down, all the logic fed by the clock net is in an off-state, thereby reducing the overall power consumption of the device. the global and regional clock networks can be powered down statically through a setting in the configuration file ( .sof or .pof ). clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by th e quartus ii software. the dynamic clock enable and disable feature allows the internal logi c to control power up and down synchronously on gclk and rclk nets and pll_out pins. this function is independent of the pll and is applied directly on the clock network or pll_out pin, as shown in figures 2?67 through 2?69 . enhanced and fast plls stratix ii gx devices provide robu st clock management and synthesis using up to four enhanced plls and four fast plls. these plls increase performance and provide advanced cl ock interfacing and clock frequency synthesis. with features such as clock switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the stratix ii gx devi ce?s enhanced plls provide you with complete control of clocks and system timing. the fast plls provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential i/o support. enhanced and fast plls work together with the stratix ii gx hi gh-speed i/o and advanced clock architecture to prov ide significant improvements in system performance and bandwidth.
2?98 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks the quartus ii software enables th e plls and their features without requiring any external devices. table 2?25 shows the plls available for each stratix ii gx device and their type. table 2?25. stratix ii gx de vice pll availability notes (1) , (2) device fast plls enhanced plls 123 (3) 4 (3) 789 (3) 10 (3) 5 6 11 12 ep2sgx30 vv vv ep2sgx60 vv v v vvv v ep2sgx90 vv v v vvv v ep2sgx130 vv v v vvv v notes to table 2?25 : (1) ep2sgx30c/d and ep2sgx60c/d devices only have two fast plls (1 and 2), but the connectivity from these two plls to the global and regional clock networks remain s the same as shown. the ep2s60c/d devices only have two enhanced plls (5 and 6). (2) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a dedicated clock input pin or other pll must drive the global or regional source. th e source cannot be driven by internally generated logic before driving the fast pll. (3) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. however, these plls are listed in table 2?25 because the stratix ii gx pll numbering scheme is cons istent with stratix and stratix ii devices.
altera corporation 2?99 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?26 shows the enhanced pll and fast pll features in stratix ii gx devices. table 2?26. stratix ii gx pll features feature enhanced pll fast pll clock multiplication and division m /( n post-scale counter) (1) m /( n post-scale counter) (2) phase shift down to 125-ps increments (3) , (4) down to 125-ps increments (3) , (4) clock switchover vv (5) pll reconfiguration vv reconfigurable bandwidth vv spread spectrum clocking v programmable duty cycle vv number of internal clock outputs 6 4 number of external clock output s three differential/six single-ended (6) number of feedback clock inputs o ne single-ended or differential (7) , (8) notes to table 2?26 : (1) for enhanced plls, m , n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle. (2) for fast plls, m , and post-scale counters range from 1 to 32. the n counter ranges from 1 to 4. (3) the smallest phase shif t is determined by the voltage controlle d oscillator (vco) period divided by 8. (4) for degree increments, stratix ii gx devices can shift all output frequencies in increments of at least 45. smaller degree increments are possible depending on the frequency and divide parameters. (5) stratix ii gx fast plls only support manual clock switchover. (6) fast plls can drive to any i/o pin as an external clock. for high-speed differential i/o pins, the device uses a data channel to generate txclkout . (7) if the feedback input is used, you will lose one (or two, if f bin is differential) external clock output pin. (8) every stratix ii gx device has at least two enhanced plls with one single-ended or differential external feedback input per pll.
2?100 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?70 shows a top-level diagram of the stratix ii gx device and pll floorplan. figure 2?70. pll locations figures 2?71 and 2?72 shows global and regional clocking from the fast pll outputs and the side clock pins . the connections to the global and regional clocks from th e fast pll outputs, internal drivers, and the clk pins on the left side of the device are shown in table 2?27 . fpll7clk fpll8clk clk[3..0] 7 1 2 8 5 11 6 12 clk [ 7..4 ] clk[15..12] plls
altera corporation 2?101 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?71. global and regional cloc k connections from center cl ock pins and fast pll outputs notes (1) , (2) notes to figure 2?71 : (1) ep2sgx30c/d and p2sgx60c/d devices only have two fast plls (1 and 2) and two enhanced plls (5 and 6), but the connectivity from these plls to the global and regional clock networks remains the same as shown. (2) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a dedicated clock input pin or other pll must drive the global or regional source. the source cannot be driven by intern ally generated logic before driving the fast pll. c0 c1 c2 c3 fast pll 1 rclk0 rclk2 rclk1 rclk3 gclk0 gclk2 gclk1 gclk3 rclk4 rclk6 rclk5 rclk7 c0 c1 c2 c3 fast pll 2 logic array signal inpu t to clock network clk0 clk1 clk2 clk3
2?102 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?72. global and regional cloc k connections from corner clock pins and fast pll outputs notes (1) , (2) notes to figure 2?72 : (1) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a dedicated clock input pin or other pll must drive the global or regional source. the source cannot be driven by intern ally generated logic before driving the fast pll. (2) ep2sgx30c/d and ep2sgx60c/d devices only have two fast plls (1 and 2); they do not contain corner fast plls. table 2?27. global and regional clock connections from left side cl ock pins and fast pll outputs (part 1 of 3) left side global and regional clock network connectivity clk0 clk1 clk2 clk3 rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7 clock pins clk0p vv v v clk1p vv v v clk2p vv v v clk3p vv v v c0 c1 c2 c3 fast pll 7 rclk0 rclk2 rclk1 rclk3 gclk0 gclk2 gclk1 gclk3 rclk4 rclk6 rclk5 rclk7 c0 c1 c2 c3 fast pll 8
altera corporation 2?103 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture drivers from internal logic gclkdrv0 vv gclkdrv1 vv gclkdrv2 vv gclkdrv3 vv rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv pll 1 outputs c0 vv vvvv c1 vv vvvv c2 vvvvvv c3 vvvvvv pll 2 outputs c0 vv vvvv c1 vv vvvv c2 vvvvvv c3 vvvvvv pll 7 outputs c0 vv v v c1 vvv v c2 vv v v c3 vv v v table 2?27. global and regional clock connections from left side cl ock pins and fast pll outputs (part 2 of 3) left side global and regional clock network connectivity clk0 clk1 clk2 clk3 rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7
2?104 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks pll 8 outputs c0 vv v v c1 vv v v c2 vv v v c3 vv v v table 2?27. global and regional clock connections from left side cl ock pins and fast pll outputs (part 3 of 3) left side global and regional clock network connectivity clk0 clk1 clk2 clk3 rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7
altera corporation 2?105 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?73 shows the global and regional clocking from enhanced pll outputs and top and bottom clk pins. figure 2?73. global and regional cloc k connections from top and bo ttom clock pins and enhanced pll outputs notes (1) , (2) notes to figure 2?73 : (1) ep2sgx30c/d and ep2sgx60c/d devices only have two enha nced plls (5 and 6), but th e connectivity from these two plls to the global and regional cloc k networks remains the same as shown. (2) if the design uses the feedback input, you will lose one (or two, if fbin is differential) external clock output pin. g15 g14 g13 g12 rclk31 rclk30 rclk29 rclk28 rclk27 rclk26 rclk25 rclk24 g7 g6 g5 g4 rclk15 rclk14 rclk13 rclk12 rclk11 rclk10 rclk9 rclk8 pll 6 clk7 clk6 clk5 clk4 pll 12 pll 5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 clk14 clk15 clk13 clk12 pll 11 pll11_fb pll5_out[2..0]p pll5_out[2..0]n pll11_out[2..0]p pll11_out[2..0]n pll12_out[2..0]p pll12_out[2..0]n pll6_out[2..0]p pll6_out[2..0]n pll5_fb pll12_fb pll6_fb global clocks regional clocks regional clocks (2) (2) (2) (2)
2?106 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks the connections to the global and region al clocks from the top clock pins and enhanced pll outputs are shown in table 2?28 . the connections to the clocks from the bottom clock pins are shown in table 2?29 . table 2?28. global and regional clock connections from top clock pins and enhanced pll outputs (part 1 of 2) top side global and regional clock network connectivity dllclk clk12 clk13 clk14 clk15 rclk24 rclk25 rclk26 rclk27 rclk28 rclk29 rclk30 rclk31 clock pins clk12p vvv v v clk13p vvv v v clk14p vvvv v clk15p vvv v v clk12n vvv clk13n vvv clk14n vvv clk15n vvv drivers from internal logic gclkdrv0 v gclkdrv1 v gclkdrv2 v gclkdrv3 v rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv enhanced pll5 outputs c0 vvv v v c1 vvv v v
altera corporation 2?107 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture c2 vvvv v c3 vvv v v c4 v vvvv c5 v vvvv enhanced pll 11 outputs c0 vv v v c1 vv v v c2 vv v v c3 vv v v c4 vvvv c5 vvvv table 2?29. global and regional cloc k connections from bottom clock pins and enhanced pll outputs (part 1 of 2) bottom side global and regional clock network connectivity dllclk clk4 clk5 clk6 clk7 rclk8 rclk9 rclk10 rclk11 rclk12 rclk13 rclk14 rclk15 clock pins clk4p vvv v v clk5p vvv v v clk6p vvvv v clk7p vvvvv clk4n vvv clk5n vvv clk6n vvv clk7n vvv drivers from internal logic gclkdrv0 v gclkdrv1 v table 2?28. global and regional clock connections from top clock pins and enhanced pll outputs (part 2 of 2) top side global and regional clock network connectivity dllclk clk12 clk13 clk14 clk15 rclk24 rclk25 rclk26 rclk27 rclk28 rclk29 rclk30 rclk31
2?108 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks gclkdrv2 v gclkdrv3 v rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv enhanced pll 6 outputs c0 vvv v v c1 vvv v v c2 vvvv v c3 vvvvv c4 vvvvv c5 v vvvv enhanced pll 12 outputs c0 vv v v c1 vv v v c2 vv v v c3 vvvv c4 vvvv c5 vvvv table 2?29. global and regional cloc k connections from bottom clock pins and enhanced pll outputs (part 2 of 2) bottom side global and regional clock network connectivity dllclk clk4 clk5 clk6 clk7 rclk8 rclk9 rclk10 rclk11 rclk12 rclk13 rclk14 rclk15
altera corporation 2?109 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture enhanced plls stratix ii gx devices contain up to four enhanced plls with advanced clock management features. these feat ures include support for external clock feedback mode, spread-spectrum clocking, and counter cascading. figure 2?74 shows a diagram of the enhanced pll. figure 2?74. stratix ii gx enhanced pll note (1) notes to figure 2?74 : (1) each clock source can come from any of the four clock pins that are physically located on the same side of the device as the pll. (2) if the feedback input is used, you will lose one (or two, if fbin is differential) external clock output pin. (3) each enhanced pll has three differential external cloc k outputs or six single-ended external clock outputs. (4) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. fast plls stratix ii gx devices contain up to four fast plls with high-speed serial interfacing ability. the fast plls of fer high-speed outputs to manage the high-speed differenti al i/o interfaces. figure 2?75 shows a diagram of the fast pll. /n char g e pump vco /c2 /c3 /c4 /c0 8 4 6 4 global clocks /c1 lock detect to i/o or g eneral routin g inclk[3..0] fbin global or re g ional clock pfd /c5 from adjacent pll /m spread spectrum i/o buffers (3) (2) loop filter & filter post-scale counters clock switchover circuitry phase frequency detector vco phase selection selectable at each pll output port vco phase selection affecting all outputs shaded portions of the pll are reconfigurable re g ional clocks 8 6
2?110 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?75. stratix ii gx device fast pll notes to figure 2?75 : (1) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. (2) in high-speed differential i/o suppo rt mode, this high-speed pll clock feeds the serializer/deserializer (serdes) circuitry. stratix ii gx devices only suppo rt one rate of data transfer per fa st pll in high-speed differential i/o support mode. (3) this signal is a differential i/o serdes control signal. (4) stratix ii gx fast plls only support manual clock switchover. f refer to the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on enhanced and fast plls. refer to ?high-speed differential i/o with dpa support? on page 2?136 for more information on high-speed differential i/o support. i/o structure the stratix ii gx ioes provide many features, including: dedicated differential and single-ended i/o buffers 3.3-v, 64-bit, 66-mhz pci compliance 3.3-v, 64-bit, 133-mhz pci-x 1.0 compliance joint test action group (jtag) boundary-scan test (bst) support on-chip driver series termination on-chip termination for differential standards programmable pull-up during configuration output drive strength control tri-state buffers bus-hold circuitry programmable pull-up resistors programmable input and output delays charge pump vco c1 8 8 4 4 8 clock input pfd c0 m loop filter phase frequency detector vco phase selection selectable at each pll output port post-scale counters global clocks diffioclk1 load_en1 load_en0 diffioclk0 regional clocks to dpa block global or regional clock (1) global or regional clock (1) c2 k c3 n 4 clock switchover circuitry (4) shaded portions of the pll are reconfigurable (2) (2) (3) (3)
altera corporation 2?111 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture open-drain outputs dq and dqs i/o pins double data rate (ddr) registers the ioe in stratix ii gx devices contains a bidirectional i/o buffer, six registers, and a latch for a complete embedded bidirectional single data rate or ddr transfer. figure 2?76 shows the stratix ii gx ioe structure. the ioe contains two input registers (p lus a latch), two output registers, and two output enable registers. you can use both input registers and the latch to capture ddr input and both output registers to drive ddr outputs. additionally, you can use the ou tput enable (oe) register for fast clock-to-output enable timing. the nega tive edge-clocked oe register is used for ddr sdram interfacing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins.
2?112 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?76. stratix ii gx ioe structure the ioes are located in i/o bloc ks around the periphery of the stratix ii gx device. there are up to four ioes per row i/o block and four ioes per column i/o block. the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. dq output register output a dq output register output b input a input b dq oe register oe dq oe register dq input register dq input register dq input latch logic array clk ena
altera corporation 2?113 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?77 shows how a row i/o block connects to the logic array. figure 2?77. row i/o block c onnection to the interconnect note to figure 2?77 : (1) the 32 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0] , four input clock enables io_ce_in[3..0] , four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0] , four asynchronous clear and preset signals io_aclr/apreset[3..0] , and four synchronous clear and preset signals io_sclr/spreset[3..0] . 32 r4 & r24 interconnects c4 interconnect i/o block local interconnect 32 data & control signals from logic array (1) io_dataina[3..0] io_datainb[3..0] io_clk[7:0] horizontal i/o block contains up to four ioes direct link interconnect to adjacent lab direct link interconnect to adjacent lab lab local interconnect lab horizontal i/o block
2?114 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?78 shows how a column i/o bloc k connects to th e logic array. figure 2?78. column i/o block connection to the interconnect note to figure 2?78 : (1) the 32 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0] , four input clock enables io_ce_in[3..0] , four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0] , four asynchronous clear and preset signals io_aclr/apreset[3..0] , and four synchronous clear and preset signals io_sclr/spreset[3..0] . 32 data & control signals from logic array (1) vertical i/o block contains up to four ioes i/o block local interconnect io_dataina[3..0] io_datainb[3..0] r4 & r24 interconnects lab local interconnect c4 & c16 interconnects 32 lab lab lab io_clk[7..0] vertical i/o block
altera corporation 2?115 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture there are 32 control and data signals that feed each row or column i/o block. these control and data signals are driven from the logic array. the row or column ioe clocks, io_clk[7..0] , provide a dedicated routing resource for low-skew, high-speed cl ocks. i/o clocks are generated from global or regional clocks. refer to ?plls and clock networks? on page 2?89 for more information. figure 2?79 illustrates the signal pa ths through the i/o block. figure 2?79. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr/apreset , sclr/spreset , clk_in , and clk_out . figure 2?80 illustrates the control signal selection. row or column io_clk[7..0] io_dataina io_datainb io_dataouta io_dataoutb io_oe oe ce_in ce_out io_ce_in aclr/apreset io_ce_out sclr/spreset io_sclr io_aclr clk_in io_clk clk_out control signal selection ioe to logic array from logic array to other ioes
2?116 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?80. control signal selection per ioe note (1) note to figure 2?80 : (1) control signals ce_in , ce_out , aclr/apreset , sclr/spreset , and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. the ioe_clk signals can drive the i/o local interconnect, which then dri ves the control selection multiplexers. in normal bidirectional operation, you can use the input register for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for da ta requiring fast clock-to-output performance. you can use the oe register for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from local interconnect in the associated lab, dedicated i/o clocks, and the column and row interconnects. figure 2?81 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/apreset sclr/spreset dedicated i/o clock [7..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_oe io_aclr local interconnect io_sclr io_ce_out io_ce_in io_clk
altera corporation 2?117 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?81. stratix ii gx ioe in bi directional i/o configuration note (1) notes to figure 2?81 : (1) all input signals to the io e can be inverted at the ioe. (2) the optional pci clamp is only available on column i/o pins. the stratix ii gx device ioe includes programmable delays that can be activated to ensure input ioe register -to-logic array register transfers, input pin-to-logic array register transf ers, or output ioe register-to-pin transfers. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena output register v ccio v ccio pci clamp (2) programmable pull-up resistor column, row, or local interconnect ioe_clk[7..0] bus-hold circuit oe register t co delay clrn/prn dq ena input register input pin to input register delay input pin to logic array delay drive strength control open-drain output on-chip termination sclr/spreset oe clkout ce_out aclr/apreset clkin ce_in output pin delay
2?118 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure a path in which a pin directly drives a register can require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may n ot require the delay. programmable delays exist for decreasing input-pin-to-logic-array and ioe input register delays. the quartus ii compiler can program these delays to automatically mini mize setup time while prov iding a zero hold time. programmable delays can increase the register-to-pin delays for output and/or output enable registers. programmable delays are no longer required to ensure zero hold times fo r logic array register-to-ioe register transfers. the quartus ii compiler can create the zero hold time for these transfers. table 2?30 shows the programmable delays for stratix ii gx devices. the ioe registers in stratix ii gx devices share the same source for clear or preset. you can program preset or clear for each individual ioe. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the re gisters. if programmed to power up high, an asynchronous preset can co ntrol the registers. this feature prevents the inadvertent activation of another de vice?s active-low input upon power-up. if one register in an ioe uses a preset or clear signal, all registers in the ioe must use that same signal if they require preset or clear. additionally, a synchronous re set signal is available for the ioe registers. double data rate i/o pins stratix ii gx devices have six registers in the ioe, which support ddr interfacing by clocking data on both positive and negative clock edges. the ioes in stratix ii gx devices support ddr inputs, ddr outputs, and bidirectional ddr modes. when using the ioe for ddr inputs, the two input registers clock double rate in put data on alternating edges. an input latch is also used in the ioe for ddr input acquisition. the latch holds the data that is present during the clock high time s, allowing both bits of data to be synchronous with the same clock edge (either rising or falling). figure 2?82 shows an ioe configured for ddr input. figure 2?83 shows the ddr input timing diagram. table 2?30. stratix ii gx programmable delay chain programmable delays quartus ii logic option input pin to logic array delay input delay from pin to internal cells input pin to input register delay inpu t delay from pin to input register output pin delay delay from output register to output pin output enable register t co delay delay to output enable pin
altera corporation 2?119 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?82. stratix ii gx ioe in ddr input i/o configuration note (1) notes to figure 2?82 : (1) all input signals to the io e can be inverted at the ioe. (2) this signal connection is only al lowed on dedicated dq function pins. (3) this signal is for dedicated dqs function pins only. (4) the optional pci clamp is only available on column i/o pins. clrn/prn dq ena chip-wide reset input register clrn/prn dq ena input register vccio vccio pci clamp (4) programmable pull-up resistor column, row, or local interconnect dqs local bus (2) to dqs logic block (3) ioe_clk[7..0] bus-hold circuit clrn/prn dq ena latch i nput pin to input registerdelay sclr/spreset clkin aclr/apreset on-chip termination ce_in
2?120 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?83. input timing diagram in ddr mode when using the ioe for ddr output s, the two output registers are configured to clock two data paths from alms on risi ng clock edges. these output registers are multiplexed by the clock to drive the output pin at a 2 rate. one output register clocks the first bi t out on the clock high time, while the other output regist er clocks the second bit out on the clock low time. figure 2?84 shows the ioe configured for ddr output. figure 2?85 shows the ddr output timing diagram. data at input pin clk a0 b0 b1 a1 a1 b2 a2 a3 a2 a3 b1 a0 b0 b2 b3 b3 b4 input to logic array
altera corporation 2?121 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?84. stratix ii gx ioe in ddr output i/o configuration notes (1) , (2) notes to figure 2?84 : (1) all input signals to the io e can be inverted at the ioe. (2) the tri-state buffer is active low. the ddio megafuncti on represents the tri-state buffer as active-high with an inverter at the oe register data port. (3) the optional pci clamp is only available on column i/o pins. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena oe register clrn/prn dq ena output register v ccio v ccio pci clamp (3) programmable pull-up resistor column, row, or local interconnect ioe_clk[7..0] bus-hold circuit oe register t co delay clrn/prn dq ena output register drive strength control open-drain output used for ddr, ddr2 sdram sclr/spreset aclr/apreset clkout output pin delay on-chip termination oe ce_out clk
2?122 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?85. output timing diagram in ddr mode the stratix ii gx ioe operates in bidirectional ddr mode by combining the ddr input and ddr output configurations. the negative-edge-clocked oe register holds the oe signal inacti ve until the falling edge of the cl ock to meet ddr sdram timing requirements. external ram interfacing in addition to the six i/o registers in each ioe, stratix ii gx devices also have dedicated phase-shift circuitry fo r interfacing with external memory interfaces, including ddr and ddr2 sdram, qdr ii sram, rldram ii, and sdr sdram. in every stratix ii gx device, the i/o banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device support dq and dqs signals with dq bus modes of 4, 8/9, 16/18, or 32/36. table 2?31 shows the number of dq and dqs buses that are supported per device. from internal registers ddr output clk b1 a1 b2 a2 b3 a3 b4 a4 a2 a1 a3 a4 b1 b2 b3 b4 table 2?31. dqs and dq bus mode support device package number of 4 groups number of 8/ 9 groups number of 16/ 18 groups number of 32/ 36 groups ep2sgx30 780-pin fineline bga 18 8 4 0 ep2sgx60 780-pin fineline bga 18 8 4 0 1,152-pin fineline bga 36 18 8 4 ep2sgx90 1,152-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 ep2sgx130 1,508-pin fineline bga 36 18 8 4
altera corporation 2?123 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture a compensated delay element on ea ch dqs pin automatically aligns input dqs synchronization signals with the data window of their corresponding dq data signals. the dqs signals drive a local dqs bus in the top and bottom i/o banks. this dq s bus is an additional resource to the i/o clocks and is used to cloc k dq input registers with the dqs signal. the stratix ii gx device has two phase- shifting reference circuits, one on the top and one on the bottom of the de vice. the circuit on the top controls the compensated delay elements for a ll dqs pins on the top. the circuit on the bottom controls the compensated delay elements for all dqs pins on the bottom. each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequenc y as the dqs signal. clock pins clk[15..12]p feed the phase circuitry on the top of the device and clock pins clk[7..4]p feed the phase circuitr y on the bottom of the device. in addition, pll clock outputs can also feed the phase-shifting reference circuits. figure 2?86 shows the phase-shift reference circuit control of each dqs delay shift on the top of the device. this same circuit is duplicated on the bottom of the device. figure 2?86. dqs phase- shift circuitry notes (1) , (2) notes to figure 2?86 : (1) there are up to 18 pairs of dqs and dqsn pins availabl e on the top or the bottom of the stratix ii gx device. there are up to 10 pairs on the right side and 8 pairs on the left side of the dqs phase-shift circuitry. (2) the ?t? module represents the dqs logic block. (3) clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase circuitry on the bottom of the device. you can also use a pll clock output as a reference clock to the phaseshift circuitry. (4) you can only use pll 5 to feed the dqs phase-shift circ uitry on the top of the device and pll 6 to feed the dqs phase-shift circuitry on the bottom of the device. dqs pin dqsn pin dqsn pin dqs pin dqs pin dqsn pin dqs pin dqsn pin from pll 5 (4) clk[15..12]p (3) to ioe to ioe to ioe to ioe to ioe to ioe to ioe t t t t t t t to ioe dqs phase-shift circuitry t dqs logic blocks
2?124 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure these dedicated circuits combined, with enhanced pll clocking and phase-shift ability, provide a complete hardware solution for interfacing to high-speed memory. f for more information on external memory interfaces, refer to the external memory inte rfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . programmable drive strength the output buffer for each stra tix ii gx device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl, lvcmos, sstl, and hstl standards have several levels of drive strength that you can control. the de fault setting used in the quartus ii software is the maximum current streng th setting that is used to achieve maximum i/o performance. for all i/ o standards, the minimum setting is the lowest drive strength that guarantees the i oh /i ol of the standard. using minimum settings provides signal slew rate control to reduce system noise and signal overshoot.
altera corporation 2?125 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?32 shows the possible settings fo r the i/o standards with drive strength control. open-drain output stratix ii gx devices provide an opti onal open-drain (equivalent to an open collector) output for each i/o pi n. this open-drain output enables the device to provide system-level co ntrol signals (for example, interrupt and write enable signals) that can be asserted by any of several devices. bus hold each stratix ii gx device i/o pin prov ides an optional bus-hold feature. the bus-hold circuitry can hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. table 2?32. programmable drive strength note (1) i/o standard i oh / i ol current strength setting (ma) for column i/o pins i oh / i ol current strength setting (ma) for row i/o pins 3.3-v lvttl 24, 20, 16, 12, 8, 4 12, 8, 4 3.3-v lvcmos 24, 20, 16, 12, 8, 4 8, 4 2.5-v lvttl/lvcmos 16, 12, 8, 4 12, 8, 4 1.8-v lvttl/lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.5-v lvcmos 8, 6, 4, 2 4, 2 sstl-2 class i 12, 8 12, 8 sstl-2 class ii 24, 20, 16 16 sstl-18 class i 12, 10, 8, 6, 4 10, 8, 6, 4 sstl-18 class ii 20, 18, 16, 8 ? hstl-18 class i 12, 10, 8, 6, 4 12, 10, 8, 6, 4 hstl-18 class ii 20, 18, 16 ? hstl-15 class i 12, 10, 8, 6, 4 8, 6, 4 hstl-15 class ii 20, 18, 16 ? note to table 2?32 : (1) the quartus ii software default current setting is the maximum setting for each i/o standard.
2?126 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the programmable pull-up option cannot be used. disable the bu s-hold feature when the i/o pin has been configured for differential signals. the bus-hold circuitry uses a resistor with a nominal resistance (rbh) of approximately 7 k to pull the signal level to the last-driven state. f refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook for the specific sustaining current driven through this resistor and overdr ive current used to identify the next-driven input level. this information is provided for each v ccio voltage level. the bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. programmable pull-up resistor each stratix ii gx device i/o pin provides an optional programmable pull-up resistor during user mode. if you enable this feature for an i/o pin, the pull-up resistor (typically 25 k ) holds the output to the v ccio level of the output pin?s bank. programmable pull-up resistors are only supported on user i/o pins and are not supported on dedicated co nfiguration pins, jtag pins, or dedicated clock pins. advanced i/o standard support the stratix ii gx device ioes support the following i/o standards: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci 3.3-v pci-x mode 1 lvds lvpecl (on input and output clocks only) differential 1.5-v hstl class i and ii differential 1.8-v hstl class i and ii differential sstl-18 class i and ii
altera corporation 2?127 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture differential sstl-2 class i and ii 1.2-v hstl class i and ii 1.5-v hstl class i and ii 1.8-v hstl class i and ii sstl-2 class i and ii sstl-18 class i and ii table 2?33 describes the i/o standards supported by stratix ii gx devices. table 2?33. stratix ii gx supported i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) lvttl single-ended ? 3.3 ? lvcmos single-ended ? 3.3 ? 2.5 v single-ended ? 2.5 ? 1.8 v single-ended ? 1.8 ? 1.5-v lvcmos single-ended ? 1.5 ? 3.3-v pci single-ended ? 3.3 ? 3.3-v pci-x mode 1 single-ended ? 3.3 ? lvds differential ? 2.5 (3) ? lvpecl (1) differential ? 3.3 ? hypertransport technology differential ? 2.5 (3) ? differential 1.5-v hstl class i and ii (2) differential 0.75 1.5 0.75 differential 1.8-v hstl class i and ii (2) differential 0.90 1.8 0.90 differential sstl-18 class i and ii (2) differential 0.90 1.8 0.90 differential sstl-2 class i and ii (2) differential 1.25 2.5 1.25 1.2-v hstl (4) voltage-referenced 0.6 1.2 0.6 1.5-v hstl class i and ii voltage-referenced 0.75 1.5 0.75 1.8-v hstl class i and ii voltage-referenced 0.9 1.8 0.9 sstl-18 class i and ii voltage-referenced 0.90 1.8 0.90
2?128 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure f for more information on i/o standard s supported by stratix ii gx i/o banks, refer to the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . stratix ii gx devices contain six i/o banks and four enhanced pll external clock output banks, as shown in figure 2?87 . the two i/o banks on the left of the device contain ci rcuitry to support source-synchronous, high-speed differential i/o for lvds inputs and outputs. these banks support all stratix ii gx i/o standard s except pci or pci-x i/o pins, and sstl-18 class ii and hstl output s. the top and bottom i/o banks support all single-ended i/o standards. additionally, enhanced pll external clock output banks allow clock output capabilities such as differential support for sstl and hstl. sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25 notes to table 2?33 : (1) this i/o standard is only available on input and output column clock pins. (2) this i/o standard is only available on input clock pins and dqs pins in i/o banks 3, 4, 7, and 8, and output clock pins in i/o banks 9,10, 11, and 12. (3) v ccio is 3.3 v when using this i/o standard in input and output column clock pins (in i/o banks 3, 4, 7, 8, 9, 10, 11, and 12). (4) 1.2-v hstl is only support ed in i/o banks 4, 7, and 8. table 2?33. stratix ii gx supported i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v)
altera corporation 2?129 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?87. stratix ii gx i/o banks notes (1) , (2) notes to figure 2?87 : (1) figure 2?87 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. (2) depending on the size of the device, differen t device members have different numbers of v ref groups. refer to the pin list and the quartus ii so ftware for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) horizontal i/o banks feature serdes and dpa circuitr y for high-speed differentia l i/o standards. see the high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook 2 for more information on differential i/o standards. each i/o bank has its own vccio pins. a single de vice can support 1.5-, 1.8-, 2.5-, and 3.3-v interfaces ; each bank can support a different v ccio level independently. each bank also has dedicated vref pins to support the voltage-referenced standards (such as sstl-2). each i/o bank can support multiple standards with the same v ccio for input and output pins. each bank can support one v ref voltage level. for example, when v ccio is 3.3 v, a bank can support lvttl, lvcmos, and 3.3-v pci for inputs and outputs. i/o banks 3, 4, 9, and 11 support all single-ended i/o standards for both input and output operations. all differential i/o standards are supported for both input and output operations at i/o banks 9 and 11. i/o banks 7, 8, 10 and 12 support all single-ended i/o standards for both input and output operations. all differential i/o standards are supported for both input and output operations at i/o banks 10 and 12. i/o banks 1 & 2 support lvttl, lvcmos, 2.5 v, 1.8 v, 1.5 v, sstl-2, sstl-18 class i, lvds, pseudo-differential sstl-2 and pseudo-differential sstl-18 class i standards for both input and output operations. hstl-18 class ii, sstl-18 class ii, pseudo-differential hstl and pseudo-differential sstl-18 class ii standards are only supported for input operations. (4) dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 pll11 vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 pll12 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 bank 11 vref3b2 vref4b2 vref0b1 vref2b1 vref3b1 vref4b1 pll1 pll2 bank 1 bank 2 bank 3 bank 4 bank 12 bank 8 bank 7 pll7 pll8 pll6 pll5 bank 9 bank 10 vref1b1 vref0b2 vref1b2 vref2b2 dqs 8 dqs 8 this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. (3) this i/o bank supports lvds and lvpecl standards for input clock operation. differential hstl and differential sstl standards are supported for both input and output operations. (3) this i/o bank supports lvds and lvpecl standards for input clock operation. differential hstl and differential sstl standards are supported for both input and output operations. (3) this i/o bank supports lvds and lvpecl standards for input clock operation. differential hstl and differential sstl standards are supported for both input and output operations. (3) transmitter: bank 13 receiver: bank 13 refclk: bank 13 transmitter: bank 14 receiver: bank 14 refclk: bank 14 transmitter: bank 15 receiver: bank 15 refclk: bank 15
2?130 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure on-chip termination stratix ii gx devices provide differential (for the lvds technology i/o standard) and series on-chip term ination to reduce reflections and maintain signal integrity. on-chip termination simplifies board design by minimizing the number of external termination resistors required. termination can be placed inside the package, eliminating small stubs that can still le ad to reflections. stratix ii gx devices provide four types of termination: differential termination (r d ) series termination (r s ) without calibration series termination (r s ) with calibration parallel termination (r t ) with calibration table 2?34 shows the stratix ii gx on-chip termination support per i/o bank. table 2?34. on-chip termination support by i/o banks (part 1 of 2) on-chip termination s upport i/o standard support top and bottom banks (3, 4, 7, 8) left bank (1, 2) series termination without calibration 3.3-v lvttl vv 3.3-v lvcmos vv 2.5-v lvttl vv 2.5-v lvcmos vv 1.8-v lvttl vv 1.8-v lvcmos vv 1.5-v lvttl vv 1.5-v lvcmos vv sstl-2 class i and ii vv sstl-18 class i v v sstl-18 class ii v ? 1.8-v hstl class i vv 1.8-v hstl class ii v ? 1.5-v hstl class i vv 1.2-v hstl v ?
altera corporation 2?131 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture differential on-chip termination stratix ii gx devices support intern al differential termination with a nominal resistance value of 100 for lvds input receiver buffers. lvpecl input signals (supported on clock pins only) require an external termination resistor. differential on-c hip termination is supported across the full range of supported differen tial data rates, as shown in the high-speed i/o specifications section of the dc & switching characteristics chapter in volume 1 of the stratix ii gx de vice handbook . f for more information on differential on-chip termination, refer to the high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . series termination with calibration 3.3-v lvttl v ? 3.3-v lvcmos v ? 2.5-v lvttl v ? 2.5-v lvcmos v ? 1.8-v lvttl v ? 1.8-v lvcmos v ? 1.5-v lvttl v ? 1.5-v lvcmos v ? sstl-2 class i and ii v ? sstl-18 class i and ii v ? 1.8-v hstl class i v ? 1.8-v hstl class ii v ? 1.5-v hstl class i v ? 1.2-v hstl v ? differential termination (1) lv d s ? v hypertransport technology ? v note to table 2?34 : (1) clock pins clk1 and clk3 , and pins fpll[7..8]clk do not support differential on-chip termination. clock pins clk0 and clk2 , do support differential on -chip termination. clock pins in the top and bottom banks ( clk[4..7, 12..15] ) do not support differential on-chip termination. table 2?34. on-chip termination support by i/o banks (part 2 of 2) on-chip termination s upport i/o standard support top and bottom banks (3, 4, 7, 8) left bank (1, 2)
2?132 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure f for more information on tolerance specifications for differential on-chip termination, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . on-chip series termination without calibration stratix ii gx devices support driver impedance matching to provide the i/o driver with controll ed output impedance that closely matches the impedance of the transmission line . as a result, reflections can be significantly reduced. stratix ii gx devices support on-chip series termination for single-ended i/o standards with typical r s values of 25 and 50 . once matching impedance is selected, current drive strength is no longer selectable. table 2?34 shows the list of output standards that support on-chip seri es termination without calibration. f for more information about series on-chip termination supported by stratix ii gx devices, refer to the selectable i/o standa rds in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . f for more information about toleran ce specifications for on-chip termination without calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . on-chip series termination with calibration stratix ii gx devices support on-chip series termination with calibration in column i/o pins in top and bottom banks. there is one calibration circuit for the top i/o banks and one circuit for the bottom i/o banks. each on-chip series termination calibration circuit compares the total impedance of each i/o buffer to the external 25- or 50- resistors connected to the rup and rdn pins, and dynamically enables or disables the transistors until they match. cali bration occurs at the end of device configuration. once the calibration ci rcuit finds the correct impedance, it powers down and stops changing th e characteristics of the drivers. f for more information about series on-chip termination supported by stratix ii gx devices, refer to the selectable i/o standa rds in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . f for more information about toleran ce specifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx de vice handbook .
altera corporation 2?133 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture on-chip parallel termination with calibration stratix ii gx devices support on -chip parallel termination with calibration for column i/o pins only. there is one calibration circuit for the top i/o banks and one circuit for the bottom i/o banks. each on-chip parallel termination calibration circ uit compares the total impedance of each i/o buffer to the external 50- resistors connected to the rup and rdn pins and dynamically enables or di sables the transistors until they match. calibration occurs at the end of device configuration. once the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. 1 on-chip parallel termination with calibration is only supported for input pins. f for more information about on-chip termination supported by stratix ii devices, refer to the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . f for more information about toleran ce specifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook. multivolt i/o interface the stratix ii gx architecture support s the multivolt i/o interface feature that allows stratix ii gx devices in all packages to inte rface with systems of different supply voltages. the stratix ii gx vccint pins must always be connected to a 1.2-v power supply. with a 1.2-v v ccint level, input pins are 1.2-, 1.5-, 1.8-, 2. 5-, and 3.3-v tolerant. the vccio pins can be connected to either a 1.2-, 1.5-, 1. 8-, 2.5-, or 3.3-v power supply, depending on the output requirements. the output levels are compatible with systems of the same voltage as the power supply (for example, when vccio pins are connected to a 1.5-v po wer supply, the output levels are compatible with 1.5-v sy stems). the stratix ii gx vccpd power pins must be connected to a 3.3-v power suppl y. these power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. the vccpd pins also power configuration input pins and jtag input pins.
2?134 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure table 2?35 summarizes stratix ii gx multivolt i/o support. the tdo and nceo pins are powered by v ccio of the bank that they reside. tdo is in i/o bank 4 and nceo is in i/o bank 7. ideally, the v cc supplies for the i/o buffers of any two connected pins are at the same voltage level. this may not always be possible depending on the v ccio level of tdo and nceo pins on master devices and the configuration voltage level chosen by v ccsel on slave devices. master and slave devices can be in any position in the chain. master in dicates that it is driving out tdo or nceo to a slave device. for multi-device passive configuration schemes, the nceo pin of the master device drives the nce pin of the slave device. the vccsel pin on the slave device selects which input buffer is used for nce . when v ccsel is logic high, it selects the 1.8-v/1.5-v buffer powered by v ccio . when v ccsel is logic low, it selects the 3.3-v/2.5-v input buffer powered by v ccpd . the ideal case is to have the v ccio of the nceo bank in a master device match the v ccsel settings for the nce input buffer of the slave device it is connected to, bu t that may not be possible depending on the application. table 2?35. stratix ii gx multivolt i/o support note (1) v ccio (v) input signal (v) output signal (v) 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 2.5 3.3 5.0 1.2 (4) v (2) v (2) v (2) v (2) v (4) ?? ??? 1.5 (4) vvv (2) v (2) v (3) v ???? 1.8 (4) v vv (2) v (2) v (3) v (3) v ??? 2.5 (4) ?? vvv (3) v (3) v (3) v ?? 3.3 (4) ?? v vv (3) v (3) v (3) v (3) vv notes to ta b l e 2 ? 3 5 : (1) to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and select the allow lvttl and lvcmos input levels to overdrive input buffer option in the quartus ii software. (2) the pin current may be slightly higher than the default value. you must verify that the driving device?s v ol maximum and v oh minimum voltages do not violate the applicable stratix ii gx v il maximum and v ih minimum voltage specifications. (3) although v ccio specifies the voltage necessary for the stratix ii gx device to drive out, a receiving device powered at a different level can still interface with the stratix ii gx device if it has inputs that tolerate the v ccio value. (4) stratix ii gx devices support 1.2-v hstl. they do not support 1.2-v lvttl and 1.2-v lvcmos.
altera corporation 2?135 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?36 contains board design recommendations to ensure that nceo can successfully drive nce for all power supply combinations. for jtag chains, the tdo pin of the first device drives the tdi pin of the second device in the chain. the v ccsel input on the jtag input i/o cells ( tck , tms , tdi , and trst ) is internally hardwired to gnd selecting the 3.3-v/2.5-v input buffer powered by v ccpd . the ideal case is to have the v ccio of the tdo bank from the first device match the v ccsel settings for tdi on the second device, but that may not be possible depending on the application. table 2?37 contains board design recommendations to ensure proper jtag chain operation. table 2?36. board design recommendations for nceo and nce input buffer power nce input buffer power in i/o bank 3 stratix ii gx nceo v ccio voltage level in i/o bank 7 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v vccsel high (v ccio bank 3 = 1.5 v) v (1) , (2) v (3) , (4) v (5) vv vccsel high (v ccio bank 3 = 1.8 v) v (1) , (2) v (3) , (4) vv level shifter required vccsel low (nce powered by v ccpd = 3.3 v) v v (4) v (6) level shifter required level shifter required notes to table 2?36 : (1) input buffer is 3.3-v tolerant. (2) the nceo output buffer meets v oh (min) = 2.4 v. (3) input buffer is 2.5-v tolerant. (4) the nceo output buffer meets v oh (min) = 2.0 v. (5) input buffer is 1.8-v tolerant. (6) an external 250- pull-up resistor is not required, but recommende d if signal levels on the board are not optimal. table 2?37. supported tdo/tdi voltage combinations (part 1 of 2) device tdi input buffer power stratix ii gx tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v stratix ii gx always v ccpd (3.3 v) v (1) v (2) v (3) level shifter required level shifter required
2?136 altera corporation stratix ii gx device handbook, volume 1 october 2007 high-speed differential i/o with dpa support high-speed differential i/o with dpa support stratix ii gx devices contain dedicated circuitry for supporting differential standards at speeds up to 1 gbps. the lvds differential i/o standards are supported in the stratix ii gx device. in addition, the lvpecl i/o standard is supported on input and output clock pins on the top and bottom i/o banks. the high-speed differential i/o circuitry supports the following high-speed i/o interconnect standards and applications: spi-4 phase 2 (pos-phy level 4) sfi-4 parallel rapidio standard there are two dedicated high-speed plls in the ep2sgx30 device and four dedicated high-speed plls in the ep2sgx60, ep2sgx90, and ep2sgx130 devices to multiply refere nce clocks and drive high-speed differential serdes channels. tables 2?38 through 2?41 show the number of channels that each fast pll can clock in each of the stratix ii gx devices. in tables 2?38 through 2?41 , the first row for each transmitter or receiver provides the number of channels driven directly by the pll. the second row below it shows the maximum channels a fast pll can driv e if cross bank channels are used from the adjacent center fast pll. for example, in the 780-pin fineline bga ep2sgx30 device, pll 1 can drive a maximum of non- stratix ii gx vcc = 3.3 v v (1) v (2) v (3) level shifter required level shifter required vcc = 2.5 v v (1) , (4) v (2) v (3) level shifter required level shifter required vcc = 1.8 v v (1) , (4) v (2) , (5) v level shifter required level shifter required vcc = 1.5 v v (1) , (4) v (2) , (5) v (6) vv notes to table 2?37 : (1) the tdo output buffer meets v oh (min) = 2.4 v. (2) the tdo output buffer meets v oh (min) = 2.0 v. (3) an external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal. (4) input buffer must be 3.3-v tolerant. (5) input buffer must be 2.5-v tolerant. (6) input buffer must be 1.8-v tolerant. table 2?37. supported tdo/tdi voltage combinations (part 2 of 2) device tdi input buffer power stratix ii gx tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v
altera corporation 2?137 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture 16 transmitter channels in i/o bank 1 or a maximum of 29 transmitter channels in i/o banks 1 and 2. the quartus ii software can also merge receiver and transmitter plls when a receiver is driving a transmitter. in this case, one fast pll can drive b oth the maximum numbers of receiver and transmitter channels. table 2?38. ep2sgx30 device differential channels note (1) package transmitter/rec eiver total channels center fast plls package pll1 pll2 780-pin fineline bga transmitter 29 16 13 receiver 31 17 14 table 2?39. ep2sgx60 device differential channels note (1) package transmitter/receiver total channels center fast plls corner fast plls pll1 pll2 pll7 pll8 780-pin fineline bga transmitter 29 16 13 ? ? receiver 31 17 14 ? ? 1,152-pin fineline bga transmitter 42 21 21 21 21 receiver 42 21 21 21 21 table 2?40. ep2sgx90 device differential channels note (1) package transmitter/receiver total channels center fast plls corner fast plls pll1 pll2 pll7 pll8 1,152-pin fineline bga transmitter 45 23 22 23 22 receiver 47 23 24 23 24 1,508-pin fineline bga transmitter 59 30 29 29 29 receiver 59 30 29 29 29
2?138 altera corporation stratix ii gx device handbook, volume 1 october 2007 high-speed differential i/o with dpa support therefore, the total number of channels is not the addition of the number of channels accessible by plls 1 and 2 with the number of channels accessible by plls 7 and 8. dedicated circuitry with dpa support stratix ii gx devices support source-synchronous interfacing with lvds signaling at up to 1 gbps. stratix ii gx devices can transmit or receive serial channels alon g with a low-speed or high-speed clock. the receiving device pll multiplies the clock by an integer factor w = 1 through 32. the serdes factor j dete rmines the parallel data width to deserialize from receivers or to serialize for transmitters. the serdes factor j can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the pll clock-multiplication w value. a design using the dynamic phase aligner also supports all of these j factor values. for a j factor of 1, the stratix ii gx device bypasses the serdes block. for a j factor of 2, the stratix ii gx device bypasses the serdes block, and the ddr input and output registers are used in the ioe. figure 2?88 shows the block diagram of the stratix ii gx transmitter channel. table 2?41. ep2sgx130 device differential channels note (1) package transmitter/receiver total channels center fast plls corner fast plls pll1 pll2 pll7 pll8 1508-pin fineline bga transmitter 71374137 41 receiver 73 37 41 37 41 note to tables 2?38 through 2?41 : (1) the total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
altera corporation 2?139 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?88. stratix ii gx transmitter channel each stratix ii gx receiver cha nnel features a dpa block for phase detection and selection, a serdes, a synchronizer, and a data realigner circuit. you can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel. in addition, you can dynamically switch between using th e dpa block or bypassing the block via a control signal from the logic array. fast pll refclk diffioclk dedicated transmitter interface local interconnect 10 + ? up to 1 gbps load_en regional or global clock data from r4, r24, c4, or direct link interconnect 10
2?140 altera corporation stratix ii gx device handbook, volume 1 october 2007 high-speed differential i/o with dpa support figure 2?89 shows the block diagram of the stratix ii gx receiver channel. figure 2?89. stratix ii gx receiver channel an external pin or global or regional clock can drive the fast plls, which can output up to three clocks: two mu ltiplied high-speed clocks to drive the serdes block and/or external pin, and a low-speed clock to drive the logic array. in addition, eight phase- shifted clocks from the vco can feed to the dpa circuitry. f for more information on the fast pll, see the plls in stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . the eight phase-shifted clocks from th e fast pll feed to the dpa block. the dpa block selects the closest phase to the center of the serial data eye to sample the incoming data. this allows the source-synchronous circuitry to capture incoming data correctly regardless of the channel-to-channel or clock-to-channel skew. the dpa block locks to a phase closest to the serial data ph ase. the phase-aligned dpa clock is used to write the data into the synchronizer. the synchronizer sits between the dpa block and the data realignment and serdes circuitry. since every channel utilizing the dpa block can have a different phase selected to sa mple the data, the synchronizer is needed to synchronize th e data to the high-speed clock domain of the data realignment and the serdes circuitry. + ? fast pll refclk load_en diffioclk regional or global clock data to r4, r24, c4, or direct link interconnect up to 1 gbps 10 dedicated receiver interface eight phase clocks data retimed_data dpa_clk dpa synchronizer 8 dq data realignment circuitry
altera corporation 2?141 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture for high-speed source synchronous interfaces such as pos-phy 4 and the parallel rapidio standard, the source synchronous cloc k rate is not a byte- or serdes-rate multiple of th e data rate. byte alignment is necessary for these protocols because the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. the stratix ii gx device?s high-speed differential i/o circuitry provides dedicated da ta realignment circuitry for user-controlled byte boundary shifting. this simplifies designs while saving alm resources. you can use an alm-based state machine to signal the shift of receiver byte bo undaries until a specified pattern is detected to indica te byte alignment. fast pll and channel layout the receiver and transmitter channels are interleaved such that each i/o bank on the left side of the device has one receiver channel and one transmitter channel per lab row. figure 2?90 shows the fast pll and channel layout in the ep2sgx30c /d and ep2sgx60c/d devices. figure 2?91 shows the fast pll and channel layout in ep2sgx60e, ep2sgx90e/f, and ep2sgx130g devices. figure 2?90. fast pll and channel layout in t he ep2sgx30c/d and ep 2sgx60c/d devices note (1) note to figure 2?90 : (1) see table 2?38 for the number of channels each device supports. lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock quadrant quadrant quadrant quadrant 4 4 4 2 2
2?142 altera corporation stratix ii gx device handbook, volume 1 october 2007 referenced documents figure 2?91. fast pll and channel layout in the ep2sgx60e to ep2sgx130 devices note (1) note to figure 2?91 : (1) see tables 2?39 through tables 2?41 for the number of channels each device supports. referenced documents this chapter references the following documents: dc & switching characteristics chapter in volume 1 of the stratix ii gx handbook dsp blocks in stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook selectable i/o standards in st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook stratix ii gx device handbook , volume 2 stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx handbook lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock fast pll 7 quadrant quadrant quadrant quadrant 4 4 2 4 2 2 fast pll 8 2
altera corporation 2?143 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture stratix ii performance and logic efficiency analysis white paper trimatrix embedded memory blocks in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx de vice handbook document revision history table 2?42 shows the revision history for this chapter. table 2?42. document revision history (part 1 of 6) date and document version changes made summary of changes october 2007, v2.2 updated: ?programmable pull-up resistor? ?reverse serial pre-cdr loopback? ?receiver input buffer? ?pattern detection? ?control and status signals? ?individual power down and reset for the transmitter and receiver? updated: figure 2?14 figure 2?26 figure 2?27 figure 2?86 (notes only) figure 2?87 updated: table 2?4 table 2?7 removed note from table 2?31 . removed tables 2-2, 2-7, and 2-8. minor text edits. august 2007, v2.1 added ?reverse serial pre-cdr loopback? section. updated table 2?2. added ?referenced documents? section.
2?144 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history february 2007 v2.0 added chapter 02 ?stratix ii gx transceivers? to the beginning of chapter 03 ?stratix ii gx architecture?. changed chapter number to chapter 02. combined chapter 02 ?stratix ii gx transceivers? and chapter 03 ?stratix ii gx architecture? in the new chapter 02 ?stratix ii gx architecture? added the ?document revision history? section to this chapter. moved the ?stratix ii gx transceiver clocking? section to after the ?receiver path? section. table 2?42. document revision history (part 2 of 6) date and document version changes made summary of changes
altera corporation 2?145 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture moved the ?transmit state machine? section to after the ?8b/10b encoder? section. moved the ?pci express receiver detect? and ?pci express electric idles (or individual transmitter tri-state)? sections to after the ?transmit buffer? section. moved the ?dynamic reconfiguration? section to the ?other transceiv er features? section. moved the ?calibration block?, ?receiver pll & cru?, and ?deserializer (serial-to-parallel converter)? sections to the ?receiver path? section. moved the ?8b/10b decoder? and ?receiver state machine? sections to after the ?rate matcher? section. moved the ?byte ordering block? section to after the ?byte deserializer? section. updated the clocking diagrams. added the ?clock resource for pld- transceiver interface? section. added the ?on-chip parallel termination with calibration? section to the ?on-chip termination? section. updated: table 2?2. table 2?10 table 2?14. table 2?3. table 2?5. table 2?8. table 2?13 table 2?18 table 2?19 table 2?29. updated figures 2?3, 2?9, 2?24, 2?25, 2?28, 2?29, 2?60, 2?62. change 622 mbps to 600 mbps throughout the chapter. table 2?42. document revision history (part 3 of 6) date and document version changes made summary of changes
2?146 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history updated: ?transmitter plls? ?transmitter phase compensation fifo buffer? ?8b/10b encoder? ?byte serializer? ?programmable output driver? ?receiver pll & cru? ?programmable pre-emphasis? ?receiver input buffer? ?control and status signals? ?programmable run length violation? ?channel aligner? ?basic mode? ?byte ordering block? ?receiver phase compensation fifo buffer? ?loopback modes? ?serial loopback? ?parallel loopback? ?regional clock network? ?multivolt i/o interface? ?high-speed differential i/o with dpa support? updated bulleted lists at the beginning of the ?transceivers? section. added reference to the ?transmit buffer? section. deleted the programmable v od table from the ?programmable output driver? section. changed ?pld interface? heading to ?parallel data width? heading in table 2?14. deleted ?global & regional clock connections from right side clock pins & fast pll outputs? table. updated notes to tables 2?29 and 2?37. updated notes to figures 2?72, 2?73 and 2?74. updated bulleted list in the ?advanced i/o standard support? section. table 2?42. document revision history (part 4 of 6) date and document version changes made summary of changes
altera corporation 2?147 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture previous chapter 02 changes: june 2006, v1.2 updated notes 1 and 2 in figure 2?1. updated ?byte serializer? section. updated tables 2?4, 2?7, and 2?16. updated ?programmable output driver? section. updated figure 2?12. updated ?programmable pre-emphasis? section. added table 2?11. added ?dynamic reconfiguration? section. added ?calibration block? section. updated ?programmable equalizer? section, including addition of figure 2?18. updated input frequency range in table 2?4. previous chapter 02 changes: april 2006, v1.1 updated figure 2?3. updated figure 2?7. updated table 2?4. updated ?transmit buffer? section. updated input frequency range in table 2?4. previous chapter 02 changes: october 2005 v1.0 added chapter to the stratix ii gx device handbook . previous chapter 03 changes: august 2006, v1.4 updated table 3?18 with note. previous chapter 03 changes: june 2006, v1.3 updated note 2 in figure 3?41. updated column title in table 3?21. previous chapter 03 changes: april 2006, v1.2 updated note 1 in table 3?9. updated note 1 in figure 3?40. updated note 2 in figure 3?41. updated table 3?16. updated figure 3?56. updated tables 3?19 through 3?22. updated tables 3?25 and 3?26. updated ?fast pll & channel layout? section. added 1,152-pin fineline bga package information for ep2sgx60 device in table 3?16. table 2?42. document revision history (part 5 of 6) date and document version changes made summary of changes
2?148 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history previous chapter 03 changes: december 2005 v1.1 updated figure 3?56. previous chapter 03 changes: october 2005 v1.0 added chapter to the stratix ii gx device handbook . table 2?42. document revision history (part 6 of 6) date and document version changes made summary of changes
altera corporation 3?1 october 2007 3. configuration & testing ieee std. 1149.1 jtag boundary- scan support all stratix ? ii gx devices provide join t test action group (jtag) boundary-scan test (bst) circuitry that complies with the ieee std. 1149.1. you can perform jtag boun dary-scan testing either before or after, but not during configuration. st ratix ii gx devices can also use the jtag port for configuration with the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). stratix ii gx devices support ioe i/o standard setting reconfiguration through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode through the config_io instruction. you can use this capability for jtag testing before configuration wh en some of the stratix ii gx pins drive or receive from other devices on the board using voltage-referenced standards. since the stratix ii gx de vice may not be configured before jtag testing, the i/o pins may not be configured for appropriate electrical standards for chip-to-chip communication. programming these i/o standards via jtag allows you to fully test i/o connections to other devices. a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms , and trst pins have weak internal pull-up resistors. the jtag input pins are powered by the 3.3-v vccpd pins. the tdo output pin is powered by the vccio power supply in i/o bank 4. stratix ii gx devices also use the jtag port to monitor the logic operation of the device with the signaltap ? ii embedded logic analyzer. stratix ii gx devices support the jtag instructions shown in table 3?1 . 1 stratix ii gx devices must be wi thin the first eight devices in a jtag chain. all of these devices have the same jtag controller. if any of the stratix ii gx devices appear after the eighth device in the jtag chain, they will fail configuration. this does not affect signaltap ii em bedded logic analysis. siigx51005-1.4
3?2 altera corporation stratix ii gx device handbook, volume 1 october 2007 ieee std. 1149.1 jtag boundary-scan support table 3?1. stratix ii gx jtag instructions jtag instruction instr uction code description sample/preload 00 0000 0101 allows a snapshot of signals at t he device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 1111 allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation while holding the i/o pins to a state defined by the data in the boundary- scan register. icr instructions used when configuring a stratix ii gx device via the jtag port with a usb-blaster?, masterblaster?, byteblastermv?, or byteblaster ii download cable, or when using a .jam or .jbc via an embedded processor or jrunner. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io (2) 00 0000 1101 allows configuration of i/o standards through the jtag chain for jtag testing. can be executed before, during, or after configuration. stops configuration if executed during configuration. once issued, the config_io instruction holds nstatus low to reset the configuration device. nstatus is held low until the ioe configuration register is loaded and the tap controller state machine transitions to the update_dr state. signaltap ii instructions monitors internal device oper ation with the signaltap ii embedded logic analyzer. notes to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest . (2) for more informa tion on using the config_io instruction, refer to the morphio: an i/o reconfiguration solution for altera devices white paper .
altera corporation 3?3 october 2007 stratix ii gx device handbook, volume 1 configuration & testing the stratix ii gx device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary- scan register length and device idcode information for stratix ii gx devices. signaltap ii embedded logic analyzer stratix ii gx devices feature the si gnaltap ii embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. you ca n analyze internal logic at speed without bringing intern al signals to the i/o pi ns. this feature is particularly important for advanced packages, such as fineline bga packages, because it can be difficul t to add a connection to a pin during the debugging process after a board is designed and manufactured. configuration the logic, circuitry, and interconnects in the stratix ii gx architecture are configured with cmos sram elements. altera ? fpgas are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification. stratix ii gx devices are configured at system power-up with data stored in an altera configuration device or provided by an external controller (for example, a max ? ii device or microprocessor). you can configure stratix ii gx devices using the fast passive parallel (fpp), active serial table 3?2. stratix ii gx boun dary-scan register length device boundary-scan register length ep2sgx30 1,320 ep2sgx60 1,506 ep2sgx90 2,016 ep2sgx130 2,454 table 3?3. 32-bit stratix ii gx device idcode device idcode (32 bits) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) ep2sgx30 0000 0010 0000 1110 0001 000 0110 1110 1 ep2sgx60 0000 0010 0000 1110 0010 000 0110 1110 1 ep2sgx90 0000 0010 0000 1110 0011 000 0110 1110 1 ep2sgx130 0000 0010 0000 1110 0100 000 0110 1110 1
3?4 altera corporation stratix ii gx device handbook, volume 1 october 2007 configuration (as), passive serial (ps) , passive parallel asynchronous (ppa), and jtag configuration schemes. the stratix ii gx device?s optimized interface allows microprocessors to configur e it serially or in parallel and synchronously or asynchronously . the interface also enables microprocessors to treat stratix ii gx devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. in addition to the number of configuration methods supported, stratix ii gx devices also offer the design security, decompression, and remote system upgrade features. the design security feature, using configuration bitstream encryption and advanced encryption standard (aes) technology, provides a me chanism to protect designs. the decompression feature allows stratix ii gx fpgas to receive a compressed configuration bitstream an d decompress this data in real- time, reducing storage re quirements and configuration time. the remote system upgrade feature allows real-t ime system upgrades from remote locations of stratix ii gx designs. for more information, refer to the ?configuration schemes? on page 3?6 . operating modes the stratix ii gx architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sram data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power-up, and before and during configuration. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allo w you to reconfigure stratix ii gx devices in-circuit by loading new configuration data into the device. with real-time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, re-initializes the device, and resumes user-mode operation. you can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. the porsel pin is a dedicated input used to select power-on reset (por) delay times of 12 ms or 100 ms during power up. when the porsel pin is connected to ground, the po r time is 100 ms. when the porsel pin is connected to v cc , the por time is 12 ms.
altera corporation 3?5 october 2007 stratix ii gx device handbook, volume 1 configuration & testing the nio _ pullup pin is a dedicated input that chooses whether the internal pull-up resistors on the user i/o pins and dual-purpose configuration i/o pins ( ncso , asdo , data[7..0] , nws , nrs , rdynbsy , ncs , cs , runlu , pgm[2..0] , clkusr , init_done , dev_oe , dev_clr ) are on or off before and during config uration. a logic high (1.5, 1.8, 2.5, 3.3 v) turns off the weak internal pull -up resistors, while a logic low turns them on. stratix ii gx devices also offer a new power supply, v ccpd , which must be connected to 3.3 v in order to power the 3.3-v/2.5-v buffer available on the configuration input pins and jtag pins. v ccpd applies to all the jtag input pins ( tck , tms , tdi , and trst ) and the following configuration pins: nconfig , dclk (when used as an input), nio_pullup , data[7..0] , runlu , nce , nws , nrs , cs , ncs , and clkusr . the vccsel pin allows the v ccio setting (of the banks where the configuration inputs reside) to be independent of the voltage required by the configuration inputs. ther efore, when selecting the v ccio voltage, you do not have to take the v il and v ih levels driven to the configuration inputs into consideration. the configuration input pins, nconfig , dclk (when used as an input), nio_pullup , runlu , nce , nws , nrs , cs , ncs , and clkusr , have a dual buffer design: a 3.3-v/2.5-v input buffer and a 1.8-v/1.5-v input buffer. the v ccsel input pin selects which input buffer is used. the 3.3-v/2.5-v inpu t buffer is powered by v ccpd , while the 1.8- v/1.5-v input buffer is powered by v ccio . v ccsel is sampled during power-up. therefore, the v ccsel setting cannot change on-the-fly or during a reconfiguration. the v ccsel input buffer is powered by v ccint and must be hardwired to v ccpd or ground. a logic high v ccsel connection selects the 1.8-v/1. 5-v input buffer; a logic low selects the 3.3-v/2.5-v input buffer. v ccsel should be set to comply with the logic levels driven out of the configuration device or the max ii microprocessor. if the design must support configuratio n input voltages of 3.3 v/2.5 v, set v ccsel to a logic low. you can set the v ccio voltage of the i/o bank that contains the configuration inputs to any supported voltage. if the design must support configuration input vo ltages of 1.8 v/1.5 v, set v ccsel to a logic high and the v ccio of the bank that contains the configuration inputs to 1.8 v/1.5 v. f for more information on multi-volt support, including information on using tdo and nceo in multi-volt systems, refer to the stratix ii gx architecture chapter in volume 1 of the stratix ii gx de vice handbook .
3?6 altera corporation stratix ii gx device handbook, volume 1 october 2007 configuration configuration schemes you can load the configuration data for a stratix ii gx device with one of five configuration schemes (refer to table 3?4 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a stratix ii gx device. a configuration device can automatically configure a stratix ii gx device at system power-up. multiple stratix ii gx devices can be configured in any of the five configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. stratix ii gx fpgas offer the following: configuration data decompression to reduce configuration file storage design security using configurat ion data encryption to protect designs remote system upgrades for remotely updating stratix ii gx designs table 3?4 summarizes which configuration features can be used in each configuration scheme. f refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information about configuration schemes in stratix ii gx devices. table 3?4. stratix ii gx confi guration features (part 1 of 2) configuration scheme configuration method desi gn security decompression remote system upgrade fpp max ii device or microprocessor and flash device v (1) v (1) v enhanced configuration device v (2) v as serial configuration device vvv (3) ps max ii device or microprocessor and flash device vvv enhanced configuration device vvv download cable (4) vv ppa max ii device or microprocessor and flash device v
altera corporation 3?7 october 2007 stratix ii gx device handbook, volume 1 configuration & testing device security using config uration bitstream encryption stratix ii and stratix ii gx fpgas are the industry?s firs t fpgas with the ability to decrypt a configuration bi tstream using the aes algorithm. when using the design security feature, a 128-bit security key is stored in the stratix ii gx fpga. to successfully configure a stratix ii gx fpga that has the design security feature enabled, the device must be configured with a configuration file that was encrypted using the same 128-bit security key. the security ke y can be stored in non-volatile memory inside the stratix ii gx de vice. this nonvolat ile memory does not require any external devices, such as a battery back up, for storage. 1 an encrypted configuration file is the same size as a non-encrypted configuration file. when using a serial configuration scheme such as passiv e serial (ps) or active serial (as), configuration time is the same whether or not the design security feature is enabled. if the fast passive parallel (fpp) scheme is used with the desi gn security or decompression feature, a 4 dclk is required. this results in a slower configuration time when compared to the configuration time of an fpga that has neither th e design security nor the decompression feature enabled. for more information about this feature, contact an altera sales representative. device configuratio n data decompression stratix ii gx fpgas support decompression of configuration data, which saves configuration memory space an d time. this feature allows you to store compressed configuration data in configuration devices or other jtag download cable (4) max ii device or microprocessor and flash device notes for ta b l e 3 ? 4 : (1) in these modes, the host system must send a dclk that is 4 the data rate. (2) the enhanced configuration device decompression feature is available, while the stratix ii gx decompression feature is not available. (3) only remote update mode is supported when using the as configuration scheme. local update mode is not supported. (4) the supported download cables inc lude the altera usb-blaster universal se rial bus (usb) port download cable, masterblaster serial/usb communications cable, by teblaster ii parallel port download cable, and the byteblastermv parallel port download cable. table 3?4. stratix ii gx confi guration features (part 2 of 2) configuration scheme configuration method desi gn security decompression remote system upgrade
3?8 altera corporation stratix ii gx device handbook, volume 1 october 2007 configuration memory, and transmit this compressed bitstream to stratix ii gx fpgas. during configuration, the stratix ii gx fpga decompresses the bitstream in real time and programs its sram cells. stratix ii gx fpgas support decompression in the fpp (when using a max ii device or microprocessor and flash memory), as, and ps configuration schemes. decompression is not supported in th e ppa configuration scheme nor in jtag-based configuration. remote system upgrades shortened design cycles, evolving standards, and system deployments in remote locations are difficult challe nges faced by system designers. stratix ii gx devices can help effectiv ely deal with these challenges with their inherent re programmability and dedicated circuitry to perform remote system updates. remote system updates help deliver feature enhancements and bug fixes without costly recalls, reducing time to market, and extending product life. stratix ii gx fpgas feature dedicated remote system upgrade circuitry to facilitate remote system updates. soft logic (nios processor or user logic) implemented in the stratix ii gx device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. the dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. this dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades. remote system configuration is support ed in the following stratix ii gx configuration schemes: fpp, as, ps, and ppa. remote system configuration can also be implemented in conjunction with stratix ii gx features such as real-time decomp ression of configuration data and design security using aes for secure and efficient field upgrades. f refer to the remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx de vice handbook for more information about remote configuration in stratix ii gx devices. configuring stratix ii gx fpgas with jrunner the jrunner? software driver conf igures altera fpgas, including stratix ii gx fpgas, through the by teblaster ii or byteblastermv cables in jtag mode. the programming input file supported is in raw binary file ( .rbf ) format. jrunner also requires a chain description file ( .cdf )
altera corporation 3?9 october 2007 stratix ii gx device handbook, volume 1 configuration & testing generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code is developed for the windows nt operating system (os), but can be customized to run on other platforms. f for more information on the jrunner software driver, refer to the an 414: an embedded so lution for pld jtag configuration and the source files on the altera web site ( www.altera.com ). programming serial configur ation devices with srunner a serial configuration device can be programmed in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit into different embedded systems. srunner reads a raw programming data file ( .rpd ) and writes to serial configuration devices. the serial configuration device programming time using srunner is comparable to the programming time when using the quartus ii software. f for more information about srunner, refer to the an 418 srunner: an embedded solution for serial configuration device programming and the source code on the altera web site. f for more information on programmin g serial configuration devices, refer to the serial configuration devices (epcs1, epcs4, epcs64, and epcs128) data sheet in the configuration handbook . configuring stratix ii fpgas with the microblaster driver the microblaster software driver supports an rbf programming input file and is ideal for embedded fpp or ps configuration. the source code is developed for the windows nt operating system, although it can be customized to run on other operating systems. f for more information on the microblaster software driver, refer to the configuring the microblaster fast passive parallel software driver white paper or the configuring the microblaster passi ve serial software driver white paper on the altera web site. pll reconfiguration the phase-locked loops (plls) in the stratix ii gx device family support reconfiguration of their multiply, divide, vco-phase selection, and bandwidth selection settings without reconfiguring the entire device. you can use either serial data from th e logic array or regular i/o pins to program the pll?s counter settings in a serial chain. this option provides
3?10 altera corporation stratix ii gx device handbook, volume 1 october 2007 temperature sensing diode (tsd) considerable flexibility for freque ncy synthesis, allowing real-time variation of the pll frequency and delay. the rest of the device is functional while re configuring the pll. f see the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on stratix ii gx plls. temperature sensing diode (tsd) stratix ii gx devices include a diode-connected transistor for use as a temperature sensor in power manageme nt. this diode is used with an external digital thermometer device. these devices steer bias current through the stratix ii gx diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus 1 sign bit). the ex ternal device?s output represents the junction temperature of the stratix ii gx device and can be used for intelligent power management. the diode requires two pins ( tempdiodep and tempdioden ) on the stratix ii gx device to connect to the external temperature-sensing device, as shown in figure 3?1 . the temperature sensing diode is a passive element and therefore can be used before the stratix ii gx device is powered. figure 3?1. external temperature-sensing diode stratix ii gx device temperature-sensin g device tempdiodep tempdioden
altera corporation 3?11 october 2007 stratix ii gx device handbook, volume 1 configuration & testing table 3?5 shows the specifications for bias voltage and current of the stratix ii gx temperature sensing diode. the temperature-sensing diode works for the entire operating range shown in figure 3?2 . figure 3?2. temperature versus te mperature-sensing diode voltage table 3?5. temperature-sensing di ode electrical characteristics parameter minimum typical maximum unit ibias high 80 100 120 a ibias low 8 10 12 a vbp - vbn 0.3 0.9 v vbn 0.7 v series resistance 3 0.90 0.85 0.95 0.75 0.65 voltage (across diode) temperature (?c) 0.55 0.45 0.60 0.50 0.40 0.70 0.80 ?55 ?30 ?5 20 45 70 95 120 10 a bias current 100 a bias current
3?12 altera corporation stratix ii gx device handbook, volume 1 october 2007 automated single event upset (seu) detection the temperature sensing diode is a very sensitive circuit which can be influenced by noise coupled from other traces on the board, and possibly within the device package itself, depending on device usage. the interfacing device registers temperatur e based on millivolts of difference as seen at the tsd. switching i/o near the tsd pins can affect the temperature reading. altera recomme nds you take temperature readings during periods of no ac tivity in the device (for example, standby mode where no clocks are toggling in the de vice), such as when the nearby i/os are at a dc state, and disable clock networks in the device. automated single event upset (seu) detection stratix ii gx devices offer on-chip circuitry for automat ed checking of single event upset (seu) detection. some applications that require the device to operate error free at high elevations or in close proximity to earth?s north or south pole will require periodic checks to ensure continued data integrity. the error detection cyclic redundancy check (crc) feature controlled by the device & pin options dialog box in the quartus ii software uses a 32-bit crc ci rcuit to ensure data reliability and is one of the best options for mitigating seu. you can implement the error detection crc feature with ex isting circuitry in stratix ii gx devices, eliminat ing the need for external logic. stratix ii gx devices compute crc during configuration and checks the computed-crc against an automatically computed crc during normal operation. the crc_error pin reports a soft error when configuration sram data is corrupted, triggering device reconfiguration. custom-built circuitry dedicated circuitry is built into stra tix ii gx devices to automatically perform error detection. this circuitry constantly checks for errors in the configuration sram cells while the device is in user mode. you can monitor one external pin for the error and use it to trigger a reconfiguration cycle. you can select the desired time between checks by adjusting a built-in clock divider. software interface beginning with version 4.1 of the quartus ii software, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc betw een 400 khz to 50 mhz. this controls the rate that the crc circuitry verifi es the internal configuration sram bits in the stratix ii gx fpga. f for more information on crc, refer to an 357: error detection using crc in altera fpga devices .
altera corporation 3?13 october 2007 stratix ii gx device handbook, volume 1 configuration & testing referenced documents this chapter references the following documents: an 357: error detection usin g crc in altera fpga devices an 414: an embedded solution for pld jtag configuration an 418 srunner: an embe dded solution for serial configuration device programming configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook configuring the microblaster fast pass ive parallel soft ware driver white paper configuring the microblaster passive serial software driver white paper morphio: an i/o reconfiguration solution for altera devices white paper plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook serial configuration devices (epcs1, epcs4, epcs64, and epcs128) data sheet in the configuration handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . document revision history table 3?6 shows the revision history for this chapter. table 3?6. document revision history date and document version changes made summary of changes october 2007 v1.4 minor text edits. ? august 2007 v1.3 updated the note in the ?ieee std. 1149.1 jtag boundary-scan support? ? updated ta b l e 3 ? 3 .? added the ?referenced documents? section. ? may 2007 v1.2 updated the ?temperature sensing diode (tsd)? section. ? february 2007 v1.1 added the ?document revi sion history? section to this chapter. added support information for the stratix ii gx device. october 2005 v1.0 added chapter to the stratix ii gx device handbook . ?
3?14 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history
altera corporation 4?1 june 2009 4. dc and switching characteristics operating conditions stratix ? ii gx devices are offered in both commercial and industrial grades. industrial devices are offered in -4 speed grade and commercial devices are offered in -3 (fast est), -4, and -5 speed grades. tables 4?1 through 4?51 provide information on absolute maximum ratings, recommended operating conditions, dc electrical characteristics, and other specifications for stratix ii gx devices. absolute maximum ratings table 4?1 contains the absolute maximum ratings for the stratix ii gx device family. table 4?1. stratix ii gx device absolute maximum ratings notes (1) , (2) , (3) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground ?0.5 1.8 v v ccio supply voltage with respect to ground ?0.5 4.6 v v ccpd supply voltage with respect to ground ?0.5 4.6 v v i dc input voltage (4) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias ?55 125 c notes to ta b l e 4 ? 1 : (1) see the operating requirements for altera devices data sheet for more information. (2) conditions beyond those listed in table 4?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (4) during transitions, the inputs may overshoot to the voltage shown in table 4?2 based upon the input duty cycle. the dc case is equivalent to 100% dut y cycle. during transitions, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. siigx51006-4.6
4?2 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions recommended oper ating conditions table 4?3 contains the stratix ii gx device family recommended operating conditions. table 4?2. maximum duty cy cles in voltage transitions symbol parameter condition maximum duty cycles (%) (1) v i maximum duty cycles in voltage transitions v i = 4.0 v 100 v i = 4.1 v 90 v i = 4.2 v 50 v i = 4.3 v 30 v i = 4.4 v 17 v i = 4.5 v 10 note to ta b l e 4 ? 2 : (1) during transition, the inputs may overshoot to the voltages shown based on the input duty cycle. the duty cycle case is equivalent to 100% duty cycle. table 4?3. stratix ii gx device recommend ed operating conditions (part 1 of 2) note (1) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers 100 s rise time 100 ms (3) 1.15 1.25 v v ccio supply voltage for output buffers, 3.3-v operation 100 s rise time 100 ms (3) , (6) 3.135 (3.00) 3.465 (3.60) v supply voltage for output buffers, 2.5-v operation 100 s rise time 100 ms (3) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation 100 s rise time 100 ms (3) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation 100 s rise time 100 ms (3) 1.425 1.575 v supply voltage for output buffers, 1.2-v operation 100 s rise time 100 ms (3) 1.15 1.25 v v ccpd supply voltage for pre-drivers as well as configuration and jtag i/o buffers. 100 s rise time 100 ms (4) 3.135 3.465 v v i input voltage (see table 4?2 ) (2) , (5) ?0.5 4.0 v v o output voltage 0 v ccio v
altera corporation 4?3 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics transceiver block characteristics tables 4?4 through 4?6 contain transceiver block specifications. t j operating junction temperat ure for commercial use 0 85 c for industrial use ?40 100 c notes to ta b l e 4 ? 3 : (1) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (2) during transitions, the inputs may overshoot to the voltage shown in table 4?2 based upon the input duty cycle. the dc case is equivalent to 100% dut y cycle. during transitions, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) maximum v cc rise time is 100 ms, and v cc must rise monotonically from ground to v cc . (4) v ccpd must ramp-up from 0 v to 3.3 v within 100 s to 100 ms. if v ccpd is not ramped up within this specified time, the stratix ii gx device will not configure su ccessfully. if the system does not allow for a v ccpd ramp-up time of 100 ms or less, hold nconfig low until all power supplies are reliable. (5) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint , v ccpd , and v ccio are powered. (6) v ccio maximum and minimum conditions for pci and pci-x are shown in parentheses. table 4?3. stratix ii gx device recommend ed operating conditions (part 2 of 2) note (1) symbol parameter conditions minimum maximum unit table 4?4. stratix ii gx transceiver block absolute maximum ratings note (1) symbol parameter conditions minimum maximum units v cca transceiver block supply voltage commercial and industrial ?0.5 4.6 v v ccp transceiver block supply voltage commercial and industrial ?0.5 1.8 v v ccr transceiver block supply voltage commercial and industrial ?0.5 1.8 v v cct transceiver block supply voltage commercial and industrial ?0.5 1.8 v v cct_b transceiver block supply voltage commercial and industrial ?0.5 1.8 v v ccl transceiver block supply voltage commercial and industrial ?0.5 1.8 v v cch_b transceiver block supply voltage commercial and industrial ?0.5 2.4 v note to ta b l e 4 ? 4 : (1) the device can tolerate prolonged op eration at this absolute maximum, as long as the maximum specification is not violated.
4?4 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?5. stratix ii gx transceiv er block operating conditions symbol parameter conditions minimum typical maximum units v cca transceiver block supply voltage commercial and industrial 3.135 3.3 3.465 v v ccp transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v ccr transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v cct transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v cct_b transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v ccl transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v cch_b (2) transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v 1.425 1.5 1.575 v r ref (1) reference resistor commercial and industrial 2000 ?1% 2000 2000 +1% notes to ta b l e 4 ? 5 : (1) the dc signal on this pin must be as clean as po ssible. ensure that no noise is coupled to this pin. (2) refer to the stratix ii gx device handbook , volume 2 , for more information. table 4?6. stratix ii gx transceiver bl ock ac specification (part 1 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max reference clock input frequency from refclk input 50 - 622.08 50 - 622.08 50 - 622.08 mhz input frequency from pld input 50 - 325 50 - 325 50 - 325 mhz input clock jitter refer to table 4?20 on page 4?36 for the input jitter specifications for the reference clock. absolute v max for a refclk pin (12) --3.3--3.3--3.3v
altera corporation 4?5 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics absolute v min for a refclk pin (12) -0.3 - - -0.3 - - -0.3 - - v rise/fall time - 0.2 - - 0.2 - - 0.2 - ui duty cycle 40 - 60 40 - 60 40 - 60 % peak-to-peak differential input voltage 200 - 2000 200 - 2000 200 - 2000 mv spread- spectrum clocking 30 0 to -0.5% -33 0 to -0.5% 30 0 to -0.5% -33 0 to -0.5% 30 0 to -0.5% -33 0 to -0.5% khz on-chip termination resistors 115 20% 115 20% 115 20% v icm (ac coupled) (12) 1200 5% 1200 5% 1200 5% mv v icm (dc coupled) (4) 0.25 - 0.55 0.25 - 0.55 0.25 - 0.55 v rref 2000 1% 2000 1% 2000 1% transceiver clocks calibration block clock frequency 10 - 125 10 - 125 10 - 125 mhz calibration block minimum power-down pulse width 30 - - 30 - - 30 - - ns time taken for one-time calibration - -8 - -8 --8ms fixedclk clock frequency pci express receiver detect - 125 - - 125 - - 125 - mhz adaptive equalization (aeq) 2.5 - 125 2.5 - 125 - - - mhz table 4?6. stratix ii gx transceiver bl ock ac specification (part 2 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?6 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions reconfig_c lk clock frequency 2.5 - 50 2.5 - 50 2.5 - 50 mhz transceiver block minimum power-down pulse width 100 - - 100 - - 100 - - ns receiver data rate 600 - 6375 600 - 5000 600 - 4250 mbps absolute v max for a receiver pin (1) --2.0--2.0--2.0v absolute v min for a receiver pin -0.4 - - -0.4 - - -0.4 - - v maximum peak-to-peak differential input voltage v id (diff p-p) v cm = 0.85 v - - 3.3 - - 3.3 - - 3.3 v minimum peak-to-peak differential input voltage v id (diff p-p) v cm = 0.85 v dc gain = 3db 160 - - 160 - - 160 - - mv v icm v icm = 0.85 v setting 85010% 85010% 85010% mv v icm = 1.2 v setting (11) 120010% 120010% 120010% mv on-chip termination resistors 100 setting 10015% 10015% 10015% 120 setting 12015% 12015% 12015% 150 setting 15015% 15015% 15015% bandwidth at 6.375 gbps bw = low - 20 - - - - - - - mhz bw = med - 35 - - - - - - - mhz bw = high - 45 - - - - - - - mhz table 4?6. stratix ii gx transceiver bl ock ac specification (part 3 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?7 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics bandwidth at 3.125 gbps bw = low - 30 - - 30 - - 30 - mhz bw = med - 40 - - 40 - - 40 - mhz bw = high - 50 - - 50 - - 50 - mhz bandwidth at 2.5 gbps bw = low - 35 - - 35 - - 35 - mhz bw = med - 50 - - 50 - - 50 - mhz bw = high - 60 - - 60 - - 60 - mhz return loss differential mode 100 mhz to 2.5 ghz (xaui): -10 db 50 mhz to 1.25 ghz (pci-e): -10 db 100 mhz to 4.875 ghz (oif/cei): -8db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope return loss common mode 100 mhz to 2.5 ghz (xaui): -6 db 50 mhz to 1.25 ghz (pci-e): -6 db 100 mhz to 4.875 ghz (oif/cei): -6db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope programmable ppm detector (2) 62.5, 100, 125, 200, 250, 300, 500, 1000 62.5, 100, 125, 200, 250, 300, 500, 1000 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm run length (3) , (9) 80 80 80 ui programmable equalization - - 16 - - 16 - - 16 db signal detect/loss threshold (4) 65 - 175 65 - 175 65 - 175 mv cdr ltr time (5) , (9) - - 75 - - 75 - - 75 us cdr minimum t1b (6) , (9) 15 - - 15 - - 15 - - us ltd lock time (7) , (9) 0 100 4000 0 100 4000 0 100 4000 ns data lock time from rx_freqloc ked (8) , (9) - -4 - -4 --4us programmable dc gain 0, 3, 6 0, 3, 6 0, 3, 6 db transmitter table 4?6. stratix ii gx transceiver bl ock ac specification (part 4 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?8 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions data rate 600 - 6375 600 - 5000 600 - 4250 mbps v ocm v ocm = 0.6 v setting 58010% 58010% 58010% mv v ocm = 0.7 v setting 68010% 68010% 68010% mv on-chip termination resistors 100 setting 10810% 10810% 10810% 120 setting 12510% 12510% 12510% 150 setting 15210% 15210% 15210% return loss differential mode 312 mhz to 625 mhz (xaui): -10 db 625 mhz to 3.125 ghz (xaui): -10 db/decade slope 50 mhz to 1.25 ghz (pci-e): -10db 100 mhz to 4.875 ghz (oif/cei): -8db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope return loss common mode 50 mhz to 1.25 ghz (pci-e): -6db 100 mhz to 4.875 ghz (oif/cei): -6db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope rise time 35 - 65 35 - 65 35 - 65 ps fall time 35 - 65 35 - 65 35 - 65 ps intra differential pair skew v od = 800 mv - - 15 - - 15 - - 15 ps intra- transceiver block skew (x4) - - 100 - - 100 - - 100 ps inter- transceiver block skew (x8) - - 300 - - 300 - - 300 ps txpll (txpll0 and txpll1) vco frequency range (low gear) 500 - 1562.5 500 - 1562.5 500 - 1562.5 mhz vco frequency range (high gear) 1562.5 3187.5 1562.5 2500 1562. 5 - 2125 mhz table 4?6. stratix ii gx transceiver bl ock ac specification (part 5 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?9 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics bandwidth at 6.375 gbps bw = low - 2 - - - - - - - mhz bw = med - 3 - - - - - - - mhz bw = high - 7 - - - - - - - mhz bandwidth at 3.125 gbps bw = low - 3 - - 3 - - 3 - mhz bw = med - 5 - - 5 - - 5 - mhz bw = high - 9 - - 9 - - 9 - mhz bandwidth at 2.5 gbps bw = low - 1 - - 1 - - 1 - mhz bw = med - 2 - - 2 -- - 2 - mhz bw = high - 4 - - 4 - - 4 - mhz tx pll lock time from gxb_ powerdown deassertion (9) , (10) - - 100 - - 100 - - 100 us pld-transceiver interface interface speed 25 - 250 25 - 250 25 - 200 mhz digital reset pulse width minimum is 2 paral lel clock cycles notes to ta b l e 4 ? 6 : (1) the device cannot tolerate prolonged operation at this absolute maximum. refer to figure 4?5 for more information. (2) the rate matcher supports only up to +/-300 ppm. (3) this parameter is measured by embedding the run length data in a prbs sequence. (4) this feature is only available in pci-express (pipe) mode. (5) time taken to rx_pll_locked goes high from rx_analogreset deassertion. refer to figure 4?1 . (6) this is how long gxb needs to stay in ltr mode after rx_pll_locked is asserted and before rx_locktodata is asserted in manual mode. refer to figure 4?1 . (7) time taken to recover valid data from gxb after rx_locktodata signal is asserted in manual mode. measurement results are based on prbs31, for native data rates only. refer to figure 4?1 . (8) time taken to recover valid data from gxb after rx_freqlocked signal goes high in automatic mode. measurement results are based on prbs31, for native data rates only. refer to figure 4?1 . (9) please refer to the protocol characterization do cuments for lock times specific to the protocols. (10) time taken to lock tx pll from gxb_powerdown deassertion. (11) the 1.2 v rx v icm setting is intended for dc-coupled lvds links. (12) for ac-coupled links, the on-chip biasing circuit is switch ed off before and during configuration. make sure that input specifications are not vi olated during this period. table 4?6. stratix ii gx transceiver bl ock ac specification (part 6 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?10 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions figure 4?1 shows the lock time parameters in manual mode, figure 4?2 shows the lock time parame ters in automatic mode. 1 ltd = lock to data ltr = lock to reference clock figure 4?1. lock time parameters for manual mode ltr ltd invalid data valid data r x_locktodata ltd lock time cdr status r x_dataout r x_pll _locked r x_analogreset cdr ltr time cdr minimum t1b
altera corporation 4?11 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics figure 4?2. lock time parameters for automatic mode figures 4?3 and 4?4 show differential receiver input and transmitter output waveforms, respectively. figure 4?3. receiver input waveform ltr ltd invalid data valid data r x_freqlocked data lock time from rx_freqlocked r x_dataout cdr status single-ended waveform differential waveform v id (diff peak-peak) = 2 x v id (single-ended) positive channel (p) ne g ative channel (n) ground v id v id v id p ? n = 0 v v cm
4?12 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions figure 4?4. transmitter output waveform figure 4?5. maximum receiver input pin voltage note to figure 4?5 : (1) the absolute v max that the receiver input pins can tolerate is 2 v. tables 4?7 through 4?12 show the typical v od for data rates from 600 mbps to 6.375 gbps. the specific ation is for measurement at the package ball. single-ended waveform differential waveform v od (diff peak-peak) = 2 x v od (single-ended) positive channel (p) ne g ative channel (n) ground v od v od v od p ? n = 0 v v cm single-ended waveform positive channel (p) ne g ative channel (n) ground v (sin g le-ended p-p)max = 3.3 v/2 v cm = 0.85 v v max = v cm + v (sin g le-ended p-p)max = 0.85 + 0.825 = 1.675 v (1) 2 table 4?7. typical v od setting, tx term = 100 note (1) v cch tx = 1.5 v v od setting (mv) 200 400 600 800 1000 1200 1400 v od typical (mv) 220 430 625 830 1020 1200 1350 note to ta b l e 4 ? 7 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball.
altera corporation 4?13 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?8. typical v od setting, tx term = 120 note (1) v cch tx = 1.5 v v od setting (mv) 240 480 720 960 1200 v od typical (mv) 260 510 750 975 1200 note to ta b l e 4 ? 8 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at th e package ball. table 4?9. typical v od setting, tx term = 150 note (1) v cch tx = 1.5 v v od setting (mv) 300 600 900 1200 v od typical (mv) 325 625 920 1200 note to ta b l e 4 ? 9 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at th e package ball. table 4?10. typical v od setting, tx term = 100 note (1) v cch tx = 1.2 v v od setting (mv) 320 480 640 800 960 v od typical (mv) 344 500 664 816 960 note to table 4?10 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at th e package ball.
4?14 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions tables 4?13 through 4?18 show the typical first post-tap pre-emphasis. table 4?11. typical v od setting, tx term = 120 note (1) v cch tx = 1.2 v v od setting (mv) 192 384 576 768 960 v od typical (mv) 210 410 600 780 960 note to ta b l e 4 ? 11 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at th e package ball. table 4?12. typical v od setting, tx term = 150 note (1) v cch tx = 1.2 v v od setting (mv) 240 480 720 960 v od typical (mv) 260 500 730 960 note to table 4?12 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at th e package ball. table 4?13. typical pre-emphasis (first post-tap), note (1) (part 1 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 100 400 24% 62% 112% 184% 600 31% 56% 86% 122% 168% 230% 329% 457% 800 20% 35% 53% 73% 96% 123% 156% 196% 237% 312% 387% 1000 23% 36% 49% 64% 79% 97% 118% 141% 165% 200% 1200 17% 25% 35% 45% 56% 68% 82% 95% 110% 125%
altera corporation 4?15 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 1400 20% 26% 33% 41% 51% 58% 67% 77% 86% note to table 4?13 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball. table 4?13. typical pre-emphasis (first post-tap), note (1) (part 2 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 table 4?14. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 120 240 45% 480 41% 76% 114% 166% 257% 355% 720 23% 38% 55% 84% 108% 137% 179% 226% 280% 405% 477% 960 15% 24% 36% 47% 64% 80% 97% 122% 140% 170% 196% 1200 18% 22% 30% 41% 51% 63% 77% 86% 98% 116% note to table 4?14 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball. table 4?15. typical pre-emphasis (first post-tap), note (1) (part 1 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 150 300 32% 85%
4?16 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions 600 33% 53% 80% 115% 157% 195% 294% 386% 900 19% 28% 38% 56% 70% 86% 113% 133% 168% 196% 242% 1200 17% 22% 31% 40% 52% 62% 75% 86% 96% 112% note to table 4?15 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball. table 4?15. typical pre-emphasis (first post-tap), note (1) (part 2 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 table 4?16. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.2 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 100 320 24% 61% 114% 480 31% 55% 86% 121% 170% 232% 333% 640 20% 35% 54% 72% 95% 124% 157% 195% 233% 307% 373% 800 23% 36% 49% 64% 81% 97% 117% 140% 161% 195% 960 18% 25% 35% 44% 57% 69% 82% 94% 108% 127% note to table 4?16 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at the package ball.
altera corporation 4?17 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?17. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.2 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 120 192 45% 384 41% 76% 114% 166% 257% 355% 576 23% 38% 55% 84% 108% 137% 179% 226% 280% 405% 477% 768 15% 24% 36% 47% 64% 80% 97% 122% 140% 170% 196% 960 18% 22% 30% 41% 51% 63% 77% 86% 98% 116% note to table 4?17 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at the package ball. table 4?18. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.2 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 150 240 31% 85% 480 32% 52% 78% 112% 152% 195% 275% 720 19% 28% 37% 56% 68% 86% 108% 133% 169% 194% 239% 960 17% 22% 30% 39% 51% 59% 75% 85% 94% 109% note to table 4?18 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at the package ball.
4?18 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?19 shows the stratix ii gx transc eiver block ac specifications. table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 1 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max sonet/sdh transmit jitter generation (7) peak-to-peak jitter at 622.08 mbps refclk = 77.76 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.1 - - 0.1 - - 0.1 ui rms jitter at 622.08 mbps refclk = 77.76 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.01 - - 0.01 - - 0.01 ui peak-to-peak jitter at 2488.32 mbps refclk = 155.52 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.1 - - 0.1 - - 0.1 ui rms jitter at 2488.32 mbps refclk = 155.52 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.01 - - 0.01 - - 0.01 ui
altera corporation 4?19 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sonet/sdh receiver jitter tolerance (7) jitter tolerance at 622.08 mbps jitter frequency = 0.03 khz pattern = prbs23 no equalization dc gain = 0 db > 15 > 15 > 15 ui jitter frequency = 25 khz pattern = prbs23 no equalization dc gain = 0 db > 1.5 > 1.5 > 1.5 ui jitter frequency = 250 khz pattern = prbs23 no equalization dc gain = 0 db > 0.15 > 0.15 > 0.15 ui jitter tolerance at 2488.32 mbps jitter frequency = 0.06 khz pattern = prbs23 no equalization dc gain = 0 db > 15 > 15 > 15 ui jitter frequency = 100 khz pattern = prbs23 no equalization dc gain = 0 db > 1.5 > 1.5 > 1.5 ui jitter frequency = 1 mhz pattern = prbs23 no equalization dc gain = 0 db > 0.15 > 0.15 > 0.15 ui jitter frequency = 10 mhz pattern = prbs23 no equalization dc gain = 0 db > 0.15 > 0.15 > 0.15 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 2 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?20 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions fibre channel transmit jitter generation (8) , (17) total jitter fc-1 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.23 - - 0.23 - - 0.23 ui deterministic jitter fc-1 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.11 - - 0.11 - - 0.11 ui total jitter fc-2 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.33 - - 0.33 - - 0.33 ui deterministic jitter fc-2 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.2 - - 0.2 - - 0.2 ui total jitter fc-4 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.52 - - 0.52 - - 0.52 ui deterministic jitter fc-4 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.33 - - 0.33 - - 0.33 ui fibre channel receiver jitter tolerance (8) , (18) deterministic jitter fc-1 pattern = cjtpat no equalization dc gain = 0 db > 0.37 > 0.37 > 0.37 ui random jitter fc- 1 pattern = cjtpat no equalization dc gain = 0 db > 0.31 > 0.31 > 0.31 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 3 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?21 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter fc-1 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-2 pattern = cjtpat no equalization dc gain = 0 db > 0.33 > 0.33 > 0.33 ui random jitter fc- 2 pattern = cjtpat no equalization dc gain = 0 db > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-2 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-4 pattern = cjtpat no equalization dc gain = 0 db > 0.33 > 0.33 > 0.33 ui random jitter fc- 4 pattern = cjtpat no equalization dc gain = 0 db > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-4 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui xaui transmit jitter generation (9) total jitter at 3.125 gbps refclk = 156.25 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.3 - - 0.3 - - 0.3 ui deterministic jitter at 3.125 gbps refclk = 156.25 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.17 - - 0.17 - - 0.17 ui xaui receiver jitter tolerance (9) total jitter pattern = cjpat no equalization dc gain = 3 db > 0.65 > 0.65 > 0.65 ui deterministic jitter pattern = cjpat no equalization dc gain = 3 db > 0.37 > 0.37 > 0.37 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 4 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?22 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions peak-to-peak jitter jitter frequency = 22.1 khz > 8.5 > 8.5 > 8.5 ui peak-to-peak jitter jitter frequency = 1.875 mhz > 0.1 > 0.1 > 0.1 ui peak-to-peak jitter jitter frequency = 20 mhz > 0.1 > 0.1 > 0.1 ui pci express transmit jitter generation (10) total jitter at 2.5 gbps compliance pattern v od = 800 mv pre-emphasis (1st post-tap) = setting 5 - - 0.25 - - 0.25 - - 0.25 ui pci express receiver jitter tolerance (10) total jitter at 2.5 gbps compliance pattern no equalization dc gain = 3 db > 0.6 > 0.6 > 0.6 ui serial rapidio transmit jitter generation (11) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat v od = 800 mv no pre-emphasis - - 0.17 - - 0.17 - - 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat v od = 800 mv no pre-emphasis - - 0.35 - - 0.35 - - 0.35 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 5 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?23 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics serial rapidio receiver jitter tolerance (11) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.55 > 0.55 > 0.55 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 6 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?24 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 8.5 > 8.5 > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.1 > 0.1 > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.1 > 0.1 > 0.1 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 7 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?25 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics gige transmit jitter generation (12) deterministic jitter (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = crpat v od = 1400 mv no pre-emphasis - - 0.14 - - 0.14 - - 0.14 ui total jitter (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = crpat v od = 1400 mv no pre-emphasis - - 0.279 - - 0.279 - - 0.279 ui gige receiver jitter tolerance (12) deterministic jitter tolerance (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = cjpat no equalization > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = cjpat no equalization > 0.66 > 0.66 > 0.66 ui higig transmit jitter generation (4) , (13) deterministic jitter (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.17 - ui total jitter (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.35 - ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 8 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?26 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions higig receiver jitter tolerance (13) deterministic jitter tolerance (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.37 - - ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.65 - - ui jitter frequency = 22.1 khz data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 8.5 - - ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 9 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?27 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 1.875 mhz data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.1 - - ui jitter frequency = 20 mhz data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.1 - - ui (oif) cei transmitter jitter generation (14) total jitter (peak-to-peak) data rate = 6.375 gbps refclk = 318.75 mhz p a t t e r n = p r b s 1 5 vod=1000 mv (5) no pre-emphasis ber = 10 -12 0.3 n/a n/a ui (oif) cei receiver jitter tolerance (14) deterministic jitter tolerance (peak-to-peak) data rate = 6 . 3 7 5 g b p s pattern = prbs31 equalizer setting = 15 d c g a i n = 0 d b ber = 10 -12 > 0.675 n/a n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 10 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?28 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions combined deterministic and random jitter tolerance (peak-to-peak) data rate = 6 . 3 7 5 g b p s pattern = prbs31 equalizer setting = 15 d c g a i n = 0 d b ber = 10 -12 > 0.988 n/a n/a ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 38.2 khz data rate = 6.375 gbps p a t t e r n = p r b s 3 1 equalizer setting = 1 5 d c g a i n = 0 d b ber = 10 -12 > 5 n/a n/a ui jitter frequency = 3.82 mhz data r a t e = 6 . 3 7 5 g b p s p a t t e r n = p r b s 3 1 equalizer setting = 1 5 d c g a i n = 0 d b ber = 10 -12 > 0.05 n/a n/a ui jitter frequency = 20 mhz data rate = 6.375 gbps p a t t e r n = p r b s 3 1 equalizer setting = 1 5 d c g a i n = 0 d b ber = 10 -12 > 0.05 n/a n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 11 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?29 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics cpri transmitter jitter generation (15) deterministic jitter (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps and 1.2288 gbps refclk = 122.88 mhz for 2.4576 gbps pattern = cjpat v o d = 1 4 0 0 m v no pre-emphasis 0.14 0.14 n/a ui total jitter (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps and 1.2288 gbps refclk = 122.88 mhz for 2.4576 gbps pattern = cjpat v o d = 1 4 0 0 m v no pre-emphasis 0.279 0.279 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 12 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?30 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions cpri receiver jitter tolerance (15) deterministic jitter tolerance (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.4 > 0.4 n/a ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.66 > 0.66 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 13 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?31 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter tolerance (peak-to-peak) (6) jitter frequency = 2 2 . 1 k h z data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 8.5 > 8.5 n/a ui jitter frequency = 1.875 mhz data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.1 > 0.1 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 14 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?32 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions sinusoidal jitter tolerance (peak-to-peak) (6) (cont.) jitter frequency = 2 0 m h z data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.1 > 0.1 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 15 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?33 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sdi transmitter jitter generation (16) alignment jitter (peak-to-peak) data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = color bar vod = 800 mv no pre-emphasis low-frequency roll-off = 100 khz 0.2 0.2 0.2 ui data rate = 2.97 gbps (3g) refclk = 148.5 mhz pattern = color bar v o d = 8 0 0 m v no pre-emphasis low-frequency roll-off = 100 khz 0.3 0.3 0.3 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 16 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?34 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions sdi receiver jitter tolerance (16) sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 15 khz data rate = 2 . 9 7 g b p s ( 3 g ) refclk = 148.5 mhz pattern = single line scramble color bar n o e q u a l i z a t i o n dc gain = 0 db > 2> 2> 2ui jitter frequency = 100 khz data rate = 2 . 9 7 g b p s ( 3 g ) refclk = 148.5 mhz pattern = single line scramble color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.3 > 0.3 > 0.3 ui jitter frequency = 148.5 mhz data rate = 2 . 9 7 g b p s ( 3 g ) refclk = 148.5 mhz pattern = single line scramble color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.3 > 0.3 > 0.3 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 17 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
altera corporation 4?35 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 20 khz data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = 75% color bar n o e q u a l i z a t i o n dc gain = 0 db > 1> 1> 1ui jitter frequency = 100 khz data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = 75% color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.2 > 0.2 > 0.2 ui jitter frequency = 148.5 mhz data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = 75% color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.2 > 0.2 > 0.2 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 18 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max
4?36 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?20 provides information on recomme nded input clock jitter for each mode. notes to table 4?19 : (1) dedicated refclk pins were used to drive the input reference clocks. (2) jitter numbers specified are valid for the stated conditions only. (3) refer to the protocol characteriza tion documents for detailed information. (4) higig configuration is available in a -3 speed grade only. for more in formation, refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook . (5) stratix ii gx transceivers meet cei jitter generation specification of 0.3 ui for a v od range of 400 mv to 1000 mv. (6) the sinusoidal jitter tolerance mask is defi ned only for low voltage (lv) variant of cpri. (7) the jitter numbers for sonet/sdh are compliant to the gr-253-core issue 3 specification. (8) the jitter numbers for fibre channel are compliant to the fc-p i-4 specification revision 6.10. (9) the jitter numbers for xaui are compliant to the ieee802.3ae-2002 specification. (10) the jitter numbers for pci express are co mpliant to the pcie base specification 2.0. (11) the jitter numbers for serial rapidio are compliant to the rapidio specification 1.3. (12) the jitter numbers for gige are compliant to the ieee802.3-2002 specification. (13) the jitter numbers for higig are compliant to the ieee802.3ae-2002 specification. (14) the jitter numbers for (oif) cei are compliant to the oif-cei-02.0 specification. (15) the jitter numbers for cpri are compliant to the cpri specification v2.1. (16) the hd-sdi and 3g-sdi jitter numbers are compliant to the smpte292m and smpte424m specifications. (17) the fibre channel transmitter jitter generation numbers are compliant to the specification at t interoperability point. (18) the fibre channel receiver ji tter tolerance numbers are comp liant to the specification at r interoperability point. table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 19 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max table 4?20. recommended input clock jitter (part 1 of 2) mode reference clock (mhz) vectron lvpecl xo type/model frequency range (mhz) rms jitter (12 khz to 20 mhz) (ps) period jitter (peak to peak) (ps) phase noise at 1 mhz (db c/hz) pci-e 100 vcc6-q/r 10 to 270 0.3 23 -149.9957 (oif) cei phy 156.25 vcc6-q/r 10 to 270 0.3 23 -146.2169 622.08 vcc6-q 270 to 800 2 30 not available gige 62.5 vcc6-q/r 10 to 270 0.3 23 -149.9957 125 vcc6-q/r 10 to 270 0.3 23 -146.9957 xaui 156.25 vcc6-q/r 10 to 270 0.3 23 -146.2169
altera corporation 4?37 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics tables 4?21 and 4?22 show the transmitter and receiver pcs latency for each mode, respectively. sonet/sdh oc-48 77.76 vcc6-q/r 10 to 270 0.3 23 -149.5476 155.52 vcc6-q/r 10 to 270 0.3 23 -149.1903 311.04 vcc6-q 270 to 800 2 30 not available 622.08 vcc6-q 270 to 800 2 30 not available sonet/sdh oc-12 62.2 vcc6-q/r 10 to 270 0.3 23 -149.6289 311 vcc6-q 270 to 800 2 30 not available 77.76 vcc6-q/r 10 to 270 0.3 23 -149.5476 155.52 vcc6-q/r 10 to 270 0.3 23 -149.1903 622.08 vcc6-q 270 to 800 2 30 not available table 4?20. recommended input clock jitter (part 2 of 2) mode reference clock (mhz) vectron lvpecl xo type/model frequency range (mhz) rms jitter (12 khz to 20 mhz) (ps) period jitter (peak to peak) (ps) phase noise at 1 mhz (db c/hz) table 4?21. pcs latency (part 1 of 2) note (1) functional mode configuration transmitter pcs latency tx pipe tx phase comp fifo byte serializer tx state machine 8b/10b encoder sum (2) xaui - 2-3 1 0.5 0.5 4-5 pipe 1, 4, 8 8-bit channel width 13-4 1 - 1 6-7 1, 4, 8 16-bit channel width 13-4 1 - 0.5 6-7 gige - 2-3 1 - 1 4-5 sonet/sdh oc-12 - 2-3 1 - 1 4-5 oc-48 - 2-3 1 - 0.5 4-5 oc-96 - 2-3 1 - 0.5 4-5 (oif) cei phy - 2-3 1 - 0.5 4-5 cpri (3) 614 mbps, 1.228 gbps -2 1 - 1 4 2.456 gbps - 2-3 1 - 1 4-5
4?38 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions serial rapidio 1.25 gbps, 2.5 gbps, 3.125 gbps -2-3 1 - 0.5 4-5 sdi hd 10-bit channel width -2-3 1 - 1 4-5 hd, 3g 20-bit channel width -2-3 1 - 0.5 4-5 basic single width 8-bit/10-bit channel width -2-3 1 - 1 4-5 16-bit/20-bit channel width -2-3 1 - 0.5 4-5 basic double width 16-bit/20-bit channel width -2-3 1 - 1 4-5 32-bit/40-bit channel width -2-3 1 - 0.5 4-5 parallel loopback/ bist -2-3 1 - 1 4-5 notes to table 4?21 : (1) the latency numbers are with respect to the pld-transceiver interface clock cycles. (2) the total latency number is rounded off in the sum column. (3) for cpri 614 mbps and 1.228 gbps data rates, the quartus ii software customizes the pld-transceiver interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation fifo latency. for more details, refer to the cpri mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx de vice handbook . table 4?21. pcs latency (part 2 of 2) note (1) functional mode configuration transmitter pcs latency tx pipe tx phase comp fifo byte serializer tx state machine 8b/10b encoder sum (2)
altera corporation 4?39 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?22. pcs latency (part 1 of 3) note (1) functional mode configuration receiver pcs latency word aligner deskew fifo rate matcher (3) 8b/10b decoder receiver state machine byte de- serializer byte order receiver phase comp fifo receiver pipe sum (2) xaui 2-2.5 2-2.5 5.5-6.5 0.5 1 1 1 1-2 - 14-17 pipe 1, 4, 8 8-bit channel width 4-5 - 11-13 1 - 1 1 2-3 1 21-25 1, 4, 8 16-bit channel width 2-2.5 - 5.5-6.5 0.5 - 1 1 2-3 1 13-16 gige 4-5 - 11-13 1 - 1 1 1-2 - 19-23 sonet/ sdh oc-12 6-7 - - 1 - 1 1 1-2 - 10-12 oc-48 3-3.5 - - 0.5 - 1 1-2 1-2 - 7-9 oc-96 2-2.5 - - 0.5 - 1 1 1-2 - 6-7 (oif) cei phy 2.5 - - 0.5 - 1 1 1-2 - 6-7 cpri (4) 614 mbps, 1.228 gbps 4-5--1-111-8-9 2.456 gbps 4-5 - - 1 - 1 1 1-2 - 8-10 serial rapidio 1.25 gbps, 2.5 gbps, 3.125 gbps 2-2.5 - - 0.5 - 1 1 1-2 - 6-7 sdi hd 10-bit channel width 5--1-111-2-9-10 hd, 3g 20-bit channel width 2.5 - - 0.5 - 1 1 1-2 - 6-7
4?40 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions basic single width 8/10-bit channel width; with rate matcher 4-5 - 11-13 1 - 1 1 1-2 1 19-23 8/10-bit channel width; without rate matcher 4-5--1-111-2-8-10 16/20-bit channel width; with rate matcher 2-2.5 - 5.5-6.5 0.5 - 1 1 1-2 - 11-14 16/20-bit channel width; without rate matcher 2-2.5 - - 0.5 - 1 1 1-2 - 6-7 table 4?22. pcs latency (part 2 of 3) note (1) functional mode configuration receiver pcs latency word aligner deskew fifo rate matcher (3) 8b/10b decoder receiver state machine byte de- serializer byte order receiver phase comp fifo receiver pipe sum (2)
altera corporation 4?41 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics basic double width 16/20-bit channel width; with rate matcher 4-5 - 11-13 1 - 1 1 1-2 - 19-23 16/20-bit channel width; without rate matcher 4-5--1-111-2-8-10 32/40-bit channel width; with rate matcher 2-2.5 - 5.5-6.5 0.5 - 1 1 1-2 - 11-14 32/40-bit channel width; without rate matcher 2-2.5 - - 0.5 - 1 1-3 1-2 - 6-9 notes to table 4?21 : (1) the latency numbers are with respect to the pld-transceiver interface clock cycles. (2) the total latency number is rounded off in the sum column. (3) the rate matcher latency shown is the steady state latency. actual latency may vary depe nding on the skip ordered set gap allowed by the protocol, actual ppm differe nce between the reference clocks, and so forth. (4) for cpri 614 mbps and 1.228 gbps data rates, the quartus ii software customizes the pld- transceiver interface clocking to achieve zero clock cycle uncertainty in the receiver phase compensation fifo latency. for more details, refer to the cpri mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook table 4?22. pcs latency (part 3 of 3) note (1) functional mode configuration receiver pcs latency word aligner deskew fifo rate matcher (3) 8b/10b decoder receiver state machine byte de- serializer byte order receiver phase comp fifo receiver pipe sum (2)
4?42 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions dc electrical characteristics table 4?23 shows the stratix ii gx device family dc electrical characteristics. table 4?23. stratix ii gx device dc operating conditions (part 1 of 2) note (1) symbol parameter conditions devi ce minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0v (2) all ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0v (2) all ?10 10 a i ccint0 v ccint supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c ep2sgx30 0.30 (3) a ep2sgx60 0.50 (3) a ep2sgx90 0.62 (3) a ep2sgx130 0.82 (3) a i ccpd0 v ccpd supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c, v ccpd = 3.3v ep2sgx30 2.7 (3) ma ep2sgx60 3.6 (3) ma ep2sgx90 4.3 (3) ma ep2sgx130 5.4 (3) ma i cci00 v ccio supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c ep2sgx30 4.0 (3) ma ep2sgx60 4.0 (3) ma ep2sgx90 4.0 (3) ma ep2sgx130 4.0 (3) ma
altera corporation 4?43 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics i/o standard specifications tables 4?24 through 4?47 show the stratix ii gx device family i/o standard specifications. r conf (4) value of i/o pin pull-up resistor before and during configuration vi = 0, v ccio = 3.3 v 10 25 50 kohm vi = 0, v ccio = 2.5 v 15 35 70 kohm vi = 0, v ccio = 1.8 v 30 50 100 kohm vi = 0, v ccio = 1.5 v 40 75 150 kohm vi = 0, v ccio = 1.2 v 50 90 170 kohm recommended value of i/o pin external pull-down resistor before and during configuration 12kohm notes to table 4?23 : (1) typical values are for t a = 25 c, v ccint = 1.2 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (2) this value is specified for normal device operation. th e value may vary during power- up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (3) maximum values depend on the actual tj and design utilization. see powerplay early power estimator (epe) and power analyzer or the quartus ii powerplay power analyzer and optimization technology (available at www.altera.com ) for maximum values. see the section ?power consumption? on page 4?59 for more information. (4) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . table 4?23. stratix ii gx device dc operating conditions (part 2 of 2) note (1) symbol parameter conditions devi ce minimum typical maximum unit table 4?24. lvttl specifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 3.135 3.465 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.8 v v oh high-level output voltage i oh = ?4 ma (2) 2.4 v
4?44 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions v ol low-level output voltage i ol = 4 ma (2) 0.45 v notes to table 4?24 : (1) stratix ii gx devices comply to the narrow range for th e supply voltage as specified in the eia/jedec standard, jesd8-b. (2) this specification is supported across all the programmab le drive strength settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?25. lvcmos specifications note (1) symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 3.135 3.465 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.8 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma (2) v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma (2) 0.2 v notes to table 4?25 : (1) stratix ii gx devices comply to the narrow range for th e supply voltage as specified in the eia/jedec standard, jesd8-b. (2) this specification is supported across all the programmab le drive strength available for this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?26. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.7 v v oh high-level output voltage i oh = ?1 ma (2) 2.0 v v ol low-level output voltage i ol = 1 ma (2) 0.4 v notes to table 4?26 : (1) the stratix ii gx device v ccio voltage level support of 2.5 to 5% is na rrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmable drive settings available for this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?24. lvttl specifications (part 2 of 2) symbol parameter conditions minimum maximum unit
altera corporation 4?45 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?27. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 1.71 1.89 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (2) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 ma (2) 0.45 v notes to table 4?27 : (1) the stratix ii gx device v ccio voltage level support of 1.8 to 5% is narrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?28. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 1.425 1.575 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (2) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (2) 0.25 v ccio v notes to table 4?28 : (1) the stratix ii gx device v ccio voltage level support of 1.5 to 5% is narrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook .
4?46 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions figures 4?6 and 4?7 show receiver input and transmitter output waveforms, respectively, for all differential i/o standards (lvds and lvpecl). figure 4?6. receiver input waveform s for differential i/o standards figure 4?7. transmitter output wavefo rms for differential i/o standards single-ended waveform differential waveform positive channel (p) = v ih ne g ative channel (n) = v il ground v id v id v id p ? n = 0 v v cm v id (peak-to-peak) single-ended waveform differential waveform positive channel (p) = v oh ne g ative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm
altera corporation 4?47 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?29. 2.5-v lvds i/o specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage for left and right i/o banks (1, 2, 5, and 6) 2.375 2.5 2.625 v v id input differential voltage swing (single-ended) 100 350 900 mv v icm input common mode voltage 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 450 mv v ocm output common mode voltage r l = 100 1.125 1.375 v r l receiver differential input discrete resistor (external to stratix ii gx devices) 90 100 110 table 4?30. 3.3-v lvds i/o specifications symbol parameter conditions minimum typical maximum unit v ccio (1) i/o supply voltage for top and bottom pll banks (9, 10, 11, and 12) 3.135 3.3 3.465 v v id input differential voltage swing (single-ended) 100 350 900 mv v icm input common mode voltage 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 710 mv v ocm output common mode voltage r l = 100 840 1,570 mv r l receiver differential input discrete resistor (external to stratix ii gx devices) 90 100 110 note to table 4?30 : (1) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output/feedback differential buffers are powered by vcc_pll_out . for differential clock output/feedback operation, connect vcc_pll_out to 3.3 v.
4?48 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?31. pcml specifications note (1) symbol parameter references reference clock 3.3-v pcml 1.5-v pcml 1.2-v pcml reference clock supported pcml standards v id peak-to-peak differential input voltage the specifications are located in the reference clock section of table 4?6 on page 4?4 . the specifications listed in ta b l e 4 ? 6 are applicable to pcml input standards. v icm input common mode voltage r on-chip termination resistors receiver 3.3-v pcml 1.5-v pcml 1.2-v pcml receiver supported pcml standards v id peak-to-peak differential input voltage the specifications are located in the receiver section of table 4?6 on page 4?4 . the specifications listed in ta b l e 4 ? 6 are applicable to pcml input standards. v icm input common mode voltage r on-chip termination resistors transmitter 1.5-v pcml 1.2-v pcml transmitter supported pcml standards v cch output buffer supply voltage the specifications are located in table 4?5 on page 4?4 . v od peak-to-peak differential output voltage the specifications are located in tables 4?7 , 4?8 , 4?9 , 4?10 , 4?11 , and 4?12 . the specifications listed in t hese tables are applicable to pcml output standards. v ocm output common mode voltage the specifications are located in the transmitter section of table 4?6 on page 4?4 . the specifications listed in ta b l e 4 ? 6 are applicable to pcml output standards. r on-chip termination resistors note to table 4?31 : (1) stratix ii gx devices support pcml input and output on gxb banks 13, 14, 15, 16, and 17. this table references stratix ii gx pcml specifications that are located in other sections of the stratix ii gx device handbook .
altera corporation 4?49 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?32. lvpecl specifications symbol parameter conditions minimum typical maximum unit v ccio (1) i/o supply voltage 3.135 3.3 3.465 v v id input differential voltage swing (single-ended) 300 600 1,000 mv v icm input common mode voltage 1.0 2.5 v v od output differential voltage (single-ended) r l = 100 525 970 mv v ocm output common mode voltage r l = 100 1,650 2,250 mv r l receiver differential input resistor 90 100 110 note to table 4?32 : (1) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output/feedback differential buffers are powered by vcc_pll_out . for differential clock output/feedback operation, connect vcc_pll_out to 3.3 v. table 4?33. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.3 0.3 v ccio v v oh high-level output voltage i out = ?500 a 0.9 v ccio v v ol low-level output voltage i out = 1,500 a 0.1 v ccio v table 4?34. pci-x mode 1 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.3 0.35 v ccio v v ipu input pull-up voltage 0.7 v ccio v v oh high-level output voltage i out = ?500 a 0.9 v ccio v v ol low-level output voltage i out = 1,500 a 0.1 v ccio v
4?50 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?35. sstl-18 clas s i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.8 1.89 v v ref reference voltage 0.855 0.9 0.945 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih (dc) high-level dc input voltage v ref + 0.125 v v il (dc) low-level dc input voltage v ref ? 0.125 v v ih (ac) high-level ac input voltage v ref + 0.25 v v il (ac) low-level ac input voltage v ref ? 0.25 v v oh high-level output voltage i oh = ?6.7 ma (1) v tt + 0.475 v v ol low-level output voltage i ol = 6.7 ma (1) v tt ? 0.475 v note to table 4?35 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?36. sstl-18 clas s ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.8 1.89 v v ref reference voltage 0.855 0.9 0.945 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih (dc) high-level dc input voltage v ref + 0.125 v v il (dc) low-level dc input voltage v ref ? 0.125 v v ih (ac) high-level ac input voltage v ref + 0.25 v v il (ac) low-level ac input voltage v ref ? 0.25 v v oh high-level output voltage i oh = ?13.4 ma (1) v ccio ? 0.28 v v ol low-level output voltage i ol = 13.4 ma (1) 0.28 v note to table 4?36 : (1) this specification is supported across all the programmabl e drive settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook .
altera corporation 4?51 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?37. sstl-18 class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.8 1.89 v v swing (dc) dc differential input voltage 0.25 v v x (ac) ac differential input cross point voltage (v ccio /2) ? 0.175 (v ccio /2) + 0.175 v v swing (ac) ac differential input voltage 0.5 v v iso input clock signal offset voltage 0.5 v ccio v v iso input clock signal offset voltage variation 200 mv v ox (ac) ac differential cross point voltage (v ccio /2) ? 0.125 (v ccio /2) + 0.125 v table 4?38. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.188 1.25 1.313 v v ih (dc) high-level dc input voltage v ref + 0.18 3.0 v v il (dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih (ac) high-level ac input voltage v ref + 0.35 v v il (ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?8.1 ma (1) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (1) v tt ? 0.57 v note to table 4?38 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?39. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.188 1.25 1.313 v
4?52 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions v ih (dc) high-level dc input voltage v ref + 0.18 v ccio + 0.3 v v il (dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih (ac) high-level ac input voltage v ref + 0.35 v v il (ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?16.4 ma (1) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (1) v tt ? 0.76 v note to table 4?39 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?40. sstl-2 class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v swing (dc) dc differential input voltage 0.36 v v x (ac) ac differential input cross point voltage (v ccio /2) ? 0.2 (v ccio /2) + 0.2 v v swing (ac) ac differential input voltage 0.7 v v iso input clock signal offset voltage 0.5 v ccio v v iso input clock signal offset voltage variation 200 mv v ox (ac) ac differential output cross point voltage (v ccio /2) ? 0.2 (v ccio /2) + 0.2 v table 4?41. 1.2-v hstl specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.14 1.2 1.26 v v ref reference voltage 0.48 v ccio 0.5 v ccio 0.52 v ccio v v ih (dc) high-level dc input voltage v ref + 0.08 v ccio + 0.15 v v il (dc) low-level dc input voltage ?0.15 v ref ? 0.08 v v ih (ac) high-level ac input voltage v ref + 0.15 v ccio + 0.24 v v il (ac) low-level ac input voltage ?0.24 v ref ? 0.15 v table 4?39. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit
altera corporation 4?53 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics v oh high-level output voltage i oh = 8 ma v ref + 0.15 v ccio + 0.15 v v ol low-level output voltage i oh = ?8 ma ?0.15 v ref ? 0.15 v table 4?42. 1.5-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.425 1.5 1.575 v v ref input reference voltage 0.713 0.75 0.788 v v tt termination voltage 0.713 0.75 0.788 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v note to table 4?42 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?43. 1.5-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.425 1.50 1.575 v v ref input reference voltage 0.713 0.75 0.788 v v tt termination voltage 0.713 0.75 0.788 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v note to table 4?43 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?41. 1.2-v hstl specifications symbol parameter conditions minimum typical maximum unit
4?54 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?44. 1.5-v hstl class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.425 1.5 1.575 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.68 0.9 v v dif (ac) ac differential input voltage 0.4 v v ox (ac) ac differential cross point voltage 0.68 0.9 v table 4?45. 1.8-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref input reference voltage 0.85 0.90 0.95 v v tt termination voltage 0.85 0.90 0.95 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v note to table 4?45 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook .
altera corporation 4?55 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?46. 1.8-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref input reference voltage 0.85 0.90 0.95 v v tt termination voltage 0.85 0.90 0.95 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v note to table 4?46 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?47. 1.8-v hstl class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.71 1.80 1.89 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.78 1.12 v v dif (ac) ac differential input voltage 0.4 v v ox (ac) ac differential cross point voltage 0.68 0.9 v
4?56 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions bus hold specifications table 4?48 shows the stratix ii gx device family bus hold specifications. on-chip termination specifications tables 4?49 and 4?50 define the specification for internal termination resistance tolerance when using series or differential on-chip termination. table 4?48. bus hold parameters parameter conditions v ccio level unit 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v min max min max min max min max min max low sustaining current v in > v il (maximum) 22.5 25 30 50 70 a high sustaining current v in < v ih (minimum) ?22.5 ?25 ?30 ?50 ?70 a low overdrive current 0 v < v in < v ccio 120 160 200 300 500 a high overdrive current 0 v < v in < v ccio ?120 ?160 ?200 ?300 ?500 a bus-hold trip point 0.45 0.95 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 v table 4?49. on-chip termination specification for top and bott om i/o banks (part 1 of 2) notes (1) , (2) symbol description conditions resistance tolerance commercial max industrial max unit 25- r s 3.3/2.5 internal series termination with calibration (25- setting ) v ccio = 3.3/2.5 v 5 10 % internal series termination without calibration (25- setting ) v ccio = 3.3/2.5 v 30 30 % 50- r s 3.3/2.5 internal series termination with calibration (50- setting ) v ccio = 3.3/2.5 v 5 10 % internal series termination without calibration (50- setting ) v ccio = 3.3/2.5 v 30 30 %
altera corporation 4?57 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 50- r t 2.5 internal parallel termination with calibration (50- setting ) v ccio = 1.8 v 30 30 % 25- r s 1.8 internal series termination with calibration (25- setting ) v ccio = 1.8 v 5 10 % internal series termination without calibration (25- setting ) v ccio = 1.8 v 30 30 % 50- r s 1.8 internal series termination with calibration (50- setting ) v ccio = 1.8 v 5 10 % internal series termination without calibration (50- setting ) v ccio = 1.8 v 30 30 % 50- r t 1.8 internal parallel termination with calibration (50- setting ) v ccio = 1.8 v 10 15 % 50- r s 1.5 internal series termination with calibration (50- setting ) v ccio = 1.5 v 8 10 % internal series termination without calibration (50- setting ) v ccio = 1.5 v 36 36 % 50- r t 1.5 internal parallel termination with calibration (50- setting ) v ccio = 1.5 v 10 15 % 50- r s 1.2 internal series termination with calibration (50- setting ) v ccio = 1.2 v 8 10 % internal series termination without calibration (50- setting ) v ccio = 1.2 v 50 50 % 50- r t 1.2 internal parallel termination with calibration (50- setting ) v ccio = 1.2 v 10 15 % note for ta b l e 4 ? 4 9 : (1) the resistance tolerance for calibrated soct is for the moment of calibration. if the temperature or voltage changes over time, the tolerance may also change. (2) on-chip parallel termination with calibr ation is only supported for input pins. table 4?49. on-chip termination specification for top and bott om i/o banks (part 2 of 2) notes (1) , (2) symbol description conditions resistance tolerance commercial max industrial max unit
4?58 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions pin capacitance table 4?51 shows the stratix ii gx device family pin capacitance. table 4?50. series and differentia l on-chip termination specification for left i/o banks note (1) symbol description conditions resistance tolerance commercial max industrial max unit 25- r s 3.3/2.5 internal series termination without calibration (25- setting ) v ccio = 3.3/2.5v 30 30 % 50- r s 3.3/2.5/1.8 internal series termination without calibration (50- setting ) v ccio = 3.3/2.5/1.8v 30 30 % 50- r s 1.5 internal series termination without calibration (50- setting ) v ccio = 1.5v 36 36 % r d internal differential termination for lvds (100- setting) v ccio = 2.5 v 20 25 % note to table 4?50 : (1) on-chip parallel termination with calibr ation is only supported for input pins. table 4?51. stratix ii gx device capacitance note (1) symbol parameter typical unit c iotb input capacitance on i/o pins in i/o banks 3, 4, 7, and 8. 5.0 pf c iol input capacitance on i/o pins in i/o banks 1 and 2, including high-speed differential receiver and transmitter pins. 6.1 pf c clktb input capacitance on top/bottom clock input pins: clk[4..7] and clk[12..15] . 6.0 pf c clkl input capacitance on left clock inputs: clk0 and clk2 . 6.1 pf c clkl+ input capacitance on left clock inputs: clk1 and clk3 . 3.3 pf c outfb input capacitance on dual-purpose clock output/feedback pins in pll banks 11 and 12. 6.7 pf note to table 4?51 : (1) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf.
altera corporation 4?59 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics power consumption altera offers two ways to calculate power for a design: the excel-based powerplay early power estimator po wer calculator and the quartus ? ii powerplay power analyzer feature. the interactive excel-based powerplay early power estimator is typically used prior to designing the fpga in order to get an estimate of device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. the power analyzer can apply a combination of user-entered, simulation-derived and estimated signa l activities which, combined with detailed circuit models, can yield very accurate power estimates. in both cases, these calculations should only be used as an estimation of power, not as a specification. f for more information on powerplay tools, refer to the powerplay early power estimators (epe) and power analyzer, the quartus ii powerplay analysis and optimization technology , and the powerplay power analyzer chapter in volume 3 of the quartus ii handbook . the powerplay early power estimators are available on the altera web site at www.altera. com . 1 see table 4?23 on page 42 for typical i cc standby specifications. timing model the directdrive technology and mu ltitrack interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across all stratix ii gx device densities and speed grades. this section describes and specifies the pe rformance, internal, external, and pll timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. preliminary and final timing timing models can have either preliminary or final status. the quartus ii software issues an informational me ssage during the design compilation if the timing models are preliminary. table 4?52 shows the status of the stratix ii gx device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible.
4?60 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual performance of the device under worst-case voltage and juncti on temperature conditions. i/o timing measurement methodology different i/o standards require different baseline loading techniques for reporting timing delays. altera char acterizes timing delays with the required termination for each i/o st andard and with 0 pf (except for pci and pci-x which use 10 pf) loading and the timing is specified up to the output pin of the fpga device. the quartus ii software calculates the i/o timing for each i/o standard wi th a default baseline loading as specified by the i/o standards. the following measurements are made during device characterization. altera measures clock-to-output delays (t co ) at worst-case process, minimum voltage, and maximum temperature (pvt) for default loading conditions shown in table 4?53 . use the following equations to calculate clock pin to output pin timing for stratix ii gx devices. t co from clock pin to i/o pin = de lay from clock pad to i/o output register + ioe output register clock-to-output delay + delay from output register to outp ut pin + i/o output delay t xz /t zx from clock pin to i/o pin = delay from clock pad to i/o output register + ioe output re gister clock-to-output delay + delay from output register to output pin + i/o output delay + output enable pin delay simulation using ibis models is required to determine the delays on the pcb traces in addition to the output pin delay timing reported by the quartus ii software and the timing model in the device handbook. 1. simulate the output driver of choi ce into the generalized test setup, using values from table 4?53 . 2. record the time to v meas . table 4?52. stratix ii gx device timing model status device preliminary final ep2sgx30 v ep2sgx60 v ep2sgx90 v ep2sgx130 v
altera corporation 4?61 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 3. simulate the output driver of ch oice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay should be added to or subt racted from the i/o standard output adder delays to yield the actual worst-case propagation delay (clock-to-output) of the pcb trace. the quartus ii software reports the ti ming with the conditions shown in table 4?53 using the above equation. figure 4?8 shows the model of the circuit that is represented by the outp ut timing of the quartus ii software. figure 4?8. output delay timing reporting setup modeled by quartus ii notes to figure 4?8 : (1) output pin timing is reported at the ou tput pin of the fpga device. additional delays for loading and board trace delay need to be accounted for with ibis model simulations. (2) v ccpd is 3.085 v unless otherwise specified. (3) v ccint is 1.12 v unless otherwise specified. output buffer v tt v ccio r d output n output p r t c l r s v meas output gnd gnd table 4?53. output timing measurement me thodology for output pins (part 1 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r s ( ) r d ( )r t ( )v ccio (v) v tt (v) c l (pf) v meas (v) lv t t l (4) 3.135 0 1.5675 lv c m o s (4) 3.135 0 1.5675 2.5 v (4) 2.375 0 1.1875 1.8 v (4) 1.710 0 0.855 1.5 v (4) 1.425 0 0.7125
4?62 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model pci (5) 2.970 10 1.485 pci-x (5) 2.970 10 1.485 sstl-2 class i 25 50 2.325 1.123 0 1.1625 sstl-2 class ii 25 25 2.325 1.123 0 1.1625 sstl-18 class i 25 50 1.660 0.790 0 0.83 sstl-18 class ii 25 25 1.660 0.790 0 0.83 1.8-v hstl class i 50 1.660 0.790 0 0.83 1.8-v hstl class ii 25 1.660 0.790 0 0.83 1.5-v hstl class i 50 1.375 0.648 0 0.6875 1.5-v hstl class ii 25 1.375 0.648 0 0.6875 1.2-v hstl with oct 1.140 0 0.570 differential sstl-2 class i 25 50 2.325 1.123 0 1.1625 differential sstl-2 class ii 25 25 2.325 1.123 0 1.1625 differential sstl-18 class i 50 50 1.660 0.790 0 0.83 differential sstl-18 class ii 25 25 1.660 0.790 0 0.83 1.5-v differential hstl class i 50 1.375 0.648 0 0.6875 1.5-v differential hstl class ii 25 1.375 0.648 0 0.6875 1.8-v differential hstl class i 50 1.660 0.790 0 0.83 1.8-v differential hstl class ii 25 1.660 0.790 0 0.83 lvds 100 2.325 0 1.1625 lvpecl 100 3.135 0 1.5675 notes to table 4?53 : (1) input measurement point at internal node is 0.5 v ccint . (2) output measuring point for v meas at buffer output is 0.5 v ccio . (3) input stimulus edge rate is 0 to v cc in 0.2 ns (internal signal) from th e driver preceding the i/o buffer. (4) less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v with less than 30-mv ripple. (5) v ccpd = 2.97 v, less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v. table 4?53. output timing measurement me thodology for output pins (part 2 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r s ( ) r d ( )r t ( )v ccio (v) v tt (v) c l (pf) v meas (v)
altera corporation 4?63 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics figures 4?9 and 4?10 show the measurement setu p for output disable and output enable timing. figure 4?9. measurement setup for t xz note (1) note to figure 4?9 : (1) v ccint is 1.12 v for this measurement. t xz , driving high to tristate t xz , driving low to tristate 100 din oe dout v ccio oe enable disable dout din t lz 100 mv ? v ccint ?0? 100 din oe dout oe enable disable dout din t hz 100 mv ? v ccint ?1? gnd
4?64 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model figure 4?10. measurement setup for t zx table 4?54 specifies the input ti ming measurement setup. t zx , tristate to driving high t zx , tristate to driving low 1 m din oe dout 1 m din oe dout oe disable enable dout din t zh ? v ccint ?1? ? v ccio oe disable enable dout din ? v ccint ?0? t zl ? v ccio table 4?54. timing measurement metho dology for input pins (part 1 of 2) notes (1) , (2) , (3) , (4) i/o standard measurement conditions measurement point v ccio (v) v ref (v) edge rate (ns) vmeas (v) lv t t l (5) 3.135 3.135 1.5675 lv c m o s (5) 3.135 3.135 1.5675 2.5 v (5) 2.375 2.375 1.1875 1.8 v (5) 1.710 1.710 0.855 1.5 v (5) 1.425 1.425 0.7125 pci (6) 2.970 2.970 1.485 pci-x (6) 2.970 2.970 1.485 sstl-2 class i 2.325 1.163 2.325 1.1625 sstl-2 class ii 2.325 1.163 2.325 1.1625 sstl-18 class i 1.660 0.830 1.660 0.83 sstl-18 class ii 1.660 0.830 1.660 0.83 1.8-v hstl class i 1.660 0.830 1.660 0.83
altera corporation 4?65 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 1.8-v hstl class ii 1.660 0.830 1.660 0.83 1.5-v hstl class i 1.375 0.688 1.375 0.6875 1.5-v hstl class ii 1.375 0.688 1.375 0.6875 1.2-v hstl with oct 1.140 0.570 1.140 0.570 differential sstl-2 class i 2.325 1.163 2.325 1.1625 differential sstl-2 class ii 2.325 1.163 2.325 1.1625 differential sstl-18 class i 1.660 0.830 1.660 0.83 differential sstl-18 class ii 1.660 0.830 1.660 0.83 1.5-v differential hstl class i 1.375 0.688 1.375 0.6875 1.5-v differential hstl class ii 1.375 0.688 1.375 0.6875 1.8-v differential hstl class i 1.660 0.830 1.660 0.83 1.8-v differential hstl class ii 1.660 0.830 1.660 0.83 lvds 2.325 0.100 1.1625 lvpecl 3.135 0.100 1.5675 notes to table 4?54 : (1) input buffer sees no load at buffer input. (2) input measuring point at buffer input is 0.5 v ccio . (3) output measuring point is 0.5 v cc at internal node. (4) input edge rate is 1 v/ns. (5) less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v with less than 30-mv ripple. (6) v ccpd = 2.97 v, less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v. table 4?54. timing measurement metho dology for input pins (part 2 of 2) notes (1) , (2) , (3) , (4) i/o standard measurement conditions measurement point v ccio (v) v ref (v) edge rate (ns) vmeas (v)
4?66 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model table 4?55 shows the stratix ii gx performance for some common designs. all performance values we re obtained with the quartus ii software compilation of lpm or megacore functions for fir and fft designs. table 4?55. stratix ii gx performance notes (part 1 of 3) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade units le 16-to-1 multiplexer (4) 21 0 0 657.03 620.73 589.62 477.09 mhz 32-to-1 multiplexer (4) 38 0 0 534.75 517.33 472.81 369.27 mhz 16-bit counter 16 0 0 568.18 539.66 507.61 422.47 mhz 64-bit counter 64 0 0 242.54 231.0 217.77 180.31 mhz trimatrix memory m512 block simple dual-port ram 32 x 18bit 0 1 0 500.0 476.19 447.22 373.13 mhz fifo 32 x 18 bit 22 1 0 500.00 476.19 460.82 373.13 mhz trimatrix memory m4k block simple dual- port ram 128 x 36bit 0 1 0 540.54 515.46 483.09 401.6 mhz true dual-port ram 128 x 18bit 0 1 0 540.54 515.46 483.09 401.6 mhz fifo 128 x 36 bit 22 1 0 524.10 500.25 466.41 381.38 mhz
altera corporation 4?67 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics trimatrix memory megaram block single port ram 4k x 144bit 0 1 0 349.65 333.33 313.47 261.09 mhz simple dual- port ram 4k x 144bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 4k x 144 bit 0 1 0 349.65 333.33 313.47 261.09 mhz single port ram 8k x 72 bit 0 1 0 354.6 337.83 317.46 263.85 mhz simple dual- port ram 8k x 72 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 8k x 72 bit 0 1 0 349.65 333.33 313.47 261.09 mhz single port ram 16k x 36 bit 0 1 0 364.96 347.22 325.73 271.73 mhz simple dual- port ram 16k x 36 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 16k x 36 bit 0 1 0 359.71 342.46 322.58 268.09 mhz single port ram 32k x 18 bit 0 1 0 364.96 347.22 325.73 271.73 mhz simple dual- port ram 32k x 18 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 32k x 18 bit 0 1 0 359.71 342.46 322.58 268.09 mhz table 4?55. stratix ii gx performance notes (part 2 of 3) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade units
4?68 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model trimatrix memory megaram block (cont.) single port ram 64k x 9 bit 0 1 0 364.96 347.22 325.73 271.73 mhz simple dual-port ram 64k x 9 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 64k x 9 bit 0 1 0 359.71 342.46 322.58 268.09 mhz dsp block 9 x 9-bit multiplier (5) 0 0 1 430.29 409.16 385.2 320.1 mhz 18 x 18-bit multiplier (5) 0 0 1 410.17 390.01 367.1 305.06 mhz 18 x 18-bit multiplier (7) 0 0 1 450.04 428.08 403.22 335.12 mhz 36 x 36-bit multiplier (5) 0 0 1 250.0 238.15 224.01 186.6 mhz 36 x 36-bit multiplier (6) 0 0 1 410.17 390.01 367.1 305.06 mhz 18-bit, 4-tap fir filter 0 0 1 410.17 390.01 367.1 305.06 mhz notes to table 4?55 : (1) these design performance numbers were obtained using the quartus ii software. (2) this column refers to -3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to -3 speed grades for ep2sgx130 devices. (4) this application uses regi stered inputs and outputs. (5) this application uses registered multiplier input and output stages within the dsp block. (6) this application uses registered multiplier input, pipeline, and output stages within the dsp block. (7) this application uses registered multiplier inputs with outputs of the multiplier stage feeding the accumulator or subtractor within the dsp block. table 4?55. stratix ii gx performance notes (part 3 of 3) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade units
altera corporation 4?69 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics internal timing parameters refer to tables 4?56 through 4?61 for internal timing parameters. table 4?56. le_ff internal timing microparameters symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max t su le register setup time before clock 90 95 101 121 ps t h le register hold time after clock 149 157 167 200 ps t co le register clock-to-output delay 62 94 62 99 62 105 62 127 ps t clr minimum clear pulse width 204 214 227 273 ps t pre minimum preset pulse width 204 214 227 273 ps t clkl minimum clock low time 612 642 683 820 ps t clkh minimum clock high time 612 642 683 820 ps t lut 170 378 170 397 170 422 170 507 t adder 372 619 372 650 372 691 372 829 notes to table 4?56 : (1) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (2) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?57. ioe internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max t su ioe input and output register setup time before clock 122 128 136 163 ps t h ioe input and output register hold time after clock 72 75 80 96 ps t co ioe input and output register clock-to-output delay 101 169 101 177 101 188 101 226 ps
4?70 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model t pin2combout_r row input pin to ioe combinational output 410 760 410 798 410 848 410 1018 ps t pin2combout_c column input pin to ioe combinational output 428 787 428 825 428 878 428 1054 ps t combin2pin_r row ioe data input to combinational output pin 1101 2026 1101 2127 1101 2261 1101 2439 ps t combin2pin_c column ioe data input to combinational output pin 991 1854 991 1946 991 2069 991 2246 ps t clr minimum clear pulse width 200 210 223 268 ps t pre minimum preset pulse width 200 210 223 268 ps t clkl minimum clock low time 600 630 669 804 ps t clkh minimum clock high time 600 630 669 804 ps (1) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (2) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?58. dsp block internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max t su input, pipeline, and output register setup time before clock 50 52 55 67 ps t h input, pipeline, and output register hold time after clock 180 189 200 241 ps t co input, pipeline, and output register clock-to-output delay 0 0 0 0 0 0 0 0 ps table 4?57. ioe internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max
altera corporation 4?71 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics t inreg2pipe9 input register to dsp block pipeline register in 9 9-bit mode 1312 2030 1312 2131 1312 2266 1312 2720 ps t inreg2pipe18 input register to dsp block pipeline register in 18 18- bit mode 1302 2010 1302 2110 1302 2244 1302 2693 ps t inreg2pipe36 input register to dsp block pipeline register in 36 36- bit mode 1302 2010 1302 2110 1302 2244 1302 2693 ps t pipe2outreg2add dsp block pipeline register to output register delay in two-multipliers adder mode 924 1450 924 1522 924 1618 924 1943 ps t pipe2outreg4add dsp block pipeline register to output register delay in four-multipliers adder mode 1134 1850 1134 1942 1134 2065 1134 2479 ps t pd9 combinational input to output delay for 99 2100 2880 2100 3024 2100 3214 2100 3859 ps t pd18 combinational input to output delay for 18 18 2110 2990 2110 3139 2110 3337 2110 4006 ps t pd36 combinational input to output delay for 36 36 2939 4450 2939 4672 2939 4967 2939 5962 ps t clr minimum clear pulse width 2212 2322 2469 2964 ps t clkl minimum clock low time 1190 1249 1328 1594 ps t clkh minimum clock high time 1190 1249 1328 1594 ps (1) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (2) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?58. dsp block internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max
4?72 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model table 4?59. m512 block internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max t m512rc synchronous read cycle time 2089 2318 2089 2433 2089 2587 2089 3104 ps t m512weresu write or read enable setup time before clock 22 23 24 29 ps t m512wereh write or read enable hold time after clock 203 213 226 272 ps t m512datasu data setup time before clock 22 23 24 29 ps t m512datah data hold time after clock 203 213 226 272 ps t m512waddrsu write address setup time before clock 22 23 24 29 ps t m512waddrh write address hold time after clock 203 213 226 272 ps t m512raddrsu read address setup time before clock 22 23 24 29 ps t m512raddrh read address hold time after clock 203 213 226 272 ps t m512dataco1 clock-to-output delay when using output registers 298 478 298 501 298 533 298 640 ps t m512dataco2 clock-to-output delay without output registers 2102 2345 2102 2461 2102 2616 2102 3141 ps t m512clkl minimum clock low time 1315 1380 1468 1762 ps t m512clkh minimum clock high time 1315 1380 1468 1762 ps
altera corporation 4?73 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics t m512clr minimum clear pulse width 144 151 160 192 ps (1) the m512 block f max obtained using the quartus ii software does not necessarily equal to 1/tm512rc. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?60. m4k block internal timing microparameters (part 1 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max t m4krc synchronous read cycle time 1462 2240 1462 2351 1462 2500 1462 3000 ps t m4kweresu write or read enable setup time before clock 22 23 24 29 ps t m4kwereh write or read enable hold time after clock 203 213 226 272 ps t m4kbesu byte enable setup time before clock 22 23 24 29 ps t m4kbeh byte enable hold time after clock 203 213 226 272 ps t m4kdataasu a port data setup time before clock 22 23 24 29 ps t m4kdataah a port data hold time after clock 203 213 226 272 ps t m4kaddrasu a port address setup time before clock 22 23 24 29 ps t m4kaddrah a port address hold time after clock 203 213 226 272 ps t m4kdatabsu b port data setup time before clock 22 23 24 29 ps table 4?59. m512 block internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max
4?74 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model t m4kdatabh b port data hold time after clock 203 213 226 272 ps t m4kraddrbsu b port address setup time before clock 22 23 24 29 ps t m4kraddrbh b port address hold time after clock 203 213 226 272 ps t m4kdataco1 clock-to-output delay when using output registers 334 524 334 549 334 584 334 701 ps t m4kdataco2 clock-to-output delay without output registers 1616 2453 1616 2574 1616 2737 1616 3286 ps t m4kclkh minimum clock high time 1250 1312 1395 1675 ps t m4kclkl minimum clock low time 1250 1312 1395 1675 ps t m4kclr minimum clear pulse width 144 151 160 192 ps (1) the m512 block f max obtained using the quartus ii software does not necessarily equal to 1/tm4krc. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?61. m-ram block internal timi ng microparameters (part 1 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max t megarc synchronous read cycle time 1866 2774 1866 2911 1866 3096 1866 3716 ps t megaweresu write or read enable setup time before clock 144 151 160 192 ps t megawereh write or read enable hold time after clock 39 40 43 52 ps table 4?60. m4k block internal timing microparameters (part 2 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max
altera corporation 4?75 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics t megabesu byte enable setup time before clock -9 -10 -11 -13 ps t megabeh byte enable hold time after clock 39 40 43 52 ps t megadataasu a port data setup time before clock 50 52 55 67 ps t megadataah a port data hold time after clock 243 255 271 325 ps t megaaddrasu a port address setup time before clock 589 618 657 789 ps t megaaddrah a port address hold time after clock -347 -365 -388 -465 ps t megadatabsu b port setup time before clock 50 52 55 67 ps t megadatabh b port hold time after clock 243 255 271 325 ps t megaaddrbsu b port address setup time before clock 589 618 657 789 ps t megaaddrbh b port address hold time after clock -347 -365 -388 -465 ps t megadataco1 clock-to-output delay when using output registers 480 715 480 749 480 797 480 957 ps t megadataco2 clock-to-output delay without output registers 1950 2899 1950 3042 1950 3235 1950 3884 ps t megaclkl minimum clock low time 1250 1312 1395 1675 ps t megaclkh minimum clock high time 1250 1312 1395 1675 ps t megaclr minimum clear pulse width 144 151 160 192 ps (1) the m512 block f max obtained using the quartus ii software does not necessarily equal to 1/tmegarc. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?61. m-ram block internal timi ng microparameters (part 2 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max
4?76 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model stratix ii gx clock timing parameters see tables 4?62 through 4?78 for stratix ii gx clock timing parameters. ep2sgx30 clock timing parameters tables 4?63 through 4?66 show the maximum clock timing parameters for ep2sgx30 devices. table 4?62. stratix ii gx clock timing parameters symbol parameter t cin delay from clock pad to i/o input register t cout delay from clock pad to i/o output register t pllcin delay from pll inclk pad to i/o input register t pllcout delay from pll inclk pad to i/o output register table 4?63. ep2sgx30 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.615 1.633 2.669 2.968 3.552 ns t cout 1.450 1.468 2.427 2.698 3.228 ns t pllcin 0.11 0.129 0.428 0.466 0.547 ns t pllcout -0.055 -0.036 0.186 0.196 0.223 ns table 4?64. ep2sgx30 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.365 1.382 2.280 2.535 3.033 ns t cout 1.370 1.387 2.276 2.531 3.028 ns t pllcin -0.151 -0.136 0.043 0.037 0.032 ns t pllcout -0.146 -0.131 0.039 0.033 0.027 ns
altera corporation 4?77 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics ep2sgx60 clock timing parameters tables 4?67 through 4?70 show the maximum clock timing parameters for ep2sgx60 devices. table 4?65. ep2sgx30 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.493 1.507 2.522 2.806 3.364 ns t cout 1.353 1.372 2.525 2.809 3.364 ns t pllcin 0.087 0.104 0.237 0.253 0.292 ns t pllcout -0.078 -0.061 0.237 0.253 0.29 ns table 4?66. ep2sgx30 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.246 1.262 2.437 2.712 3.246 ns t cout 1.251 1.267 2.437 2.712 3.246 ns t pllcin -0.18 -0.167 0.215 0.229 0.263 ns t pllcout -0.175 -0.162 0.215 0.229 0.263 ns table 4?67. ep2sgx60 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.722 1.736 2.940 3.275 3.919 ns t cout 1.557 1.571 2.698 3.005 3.595 ns t pllcin 0.037 0.051 0.474 0.521 0.613 ns t pllcout -0.128 -0.114 0.232 0.251 0.289 ns
4?78 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model table 4?68. ep2sgx60 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.494 1.508 2.582 2.875 3.441 ns t cout 1.499 1.513 2.578 2.871 3.436 ns t pllcin -0.183 -0.168 0.116 0.122 0.135 ns t pllcout -0.178 -0.163 0.112 0.118 0.13 ns table 4?69. ep2sgx60 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.577 1.591 2.736 3.048 3.648 ns t cout 1.412 1.426 2.740 3.052 3.653 ns t pllcin 0.065 0.08 0.334 0.361 0.423 ns t pllcout -0.1 -0.085 0.334 0.361 0.423 ns table 4?70. ep2sgx60 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.342 1.355 2.716 3.024 3.622 ns t cout 1.347 1.360 2.716 3.024 3.622 ns t pllcin -0.18 -0.166 0.326 0.352 0.412 ns t pllcout -0.175 -0.161 0.334 0.361 0.423 ns
altera corporation 4?79 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics ep2sgx90 clock timing parameters tables 4?71 through 4?74 show the maximum clock timing parameters for ep2sgx90 devices. table 4?71. ep2sgx90 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.861 1.878 3.115 3.465 4.143 ns t cout 1.696 1.713 2.873 3.195 3.819 ns t pllcin -0.254 -0.237 0.171 0.179 0.206 ns t pllcout -0.419 -0.402 -0.071 -0.091 -0.118 ns table 4?72. ep2sgx90 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.634 1.650 2.768 3.076 3.678 ns t cout 1.639 1.655 2.764 3.072 3.673 ns t pllcin -0.481 -0.465 -0.189 -0.223 -0.279 ns t pllcout -0.476 -0.46 -0.193 -0.227 -0.284 ns table 4?73. ep2sgx90 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.688 1.702 2.896 3.224 3.856 ns t cout 1.551 1.569 2.893 3.220 3.851 ns t pllcin -0.105 -0.089 0.224 0.241 0.254 ns t pllcout -0.27 -0.254 0.224 0.241 0.254 ns
4?80 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model ep2sgx130 clock timing parameters tables 4?75 through 4?78 show the maximum clock timing parameters for ep2sgx130 devices. table 4?74. ep2sgx90 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.444 1.461 2.792 3.108 3.716 ns t cout 1.449 1.466 2.792 3.108 3.716 ns t pllcin -0.348 -0.333 0.204 0.217 0.243 ns t pllcout -0.343 -0.328 0.212 0.217 0.254 ns table 4?75. ep2sgx130 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.980 1.998 3.491 3.706 4.434 ns t cout 1.815 1.833 3.237 3.436 4.110 ns t pllcin -0.027 -0.009 0.307 0.322 0.376 ns t pllcout -0.192 -0.174 0.053 0.052 0.052 ns table 4?76. ep2sgx130 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.741 1.759 3.112 3.303 3.950 ns t cout 1.746 1.764 3.108 3.299 3.945 ns t pllcin -0.261 -0.243 -0.089 -0.099 -0.129 ns t pllcout -0.256 -0.238 -0.093 -0.103 -0.134 ns
altera corporation 4?81 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics clock network skew adders the quartus ii software models skew within dedicated clock networks such as global and regional clocks . therefore, the intra-clock network skew adder is not specified. table 4?79 specifies the intra-clock skew between any two clock networks driving any registers in the stratix ii gx device. table 4?77. ep2sgx130 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.815 1.834 3.218 3.417 4.087 ns t cout 1.650 1.669 3.218 3.417 4.087 ns t pllcin 0.116 0.134 0.349 0.364 0.426 ns t pllcout -0.049 -0.031 0.361 0.378 0.444 ns table 4?78. ep2sgx130 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.544 1.560 3.195 3.395 4.060 ns t cout 1.549 1.565 3.195 3.395 4.060 ns t pllcin -0.149 -0.132 0.34 0.356 0.417 ns t pllcout -0.144 -0.127 0.342 0.356 0.417 ns table 4?79. clock network specifications (part 1 of 2) name description min typ max unit clock skew adder ep2sgx30 (1) inter-clock network, same side 50 ps inter-clock network, entire chip 100 ps clock skew adder ep2sgx60 (1) inter-clock network, same side 50 ps inter-clock network, entire chip 100 ps clock skew adder ep2sgx90 (1) inter-clock network, same side 55 ps inter-clock network, entire chip 110 ps
ioe programmable delay see tables 4?80 and 4?81 for ioe programmable delay. clock skew adder ep2sgx130 (1) inter-clock network, same side 63 ps inter-clock network, entire chip 125 ps (1) this is in addition to intra-clock network sk ew, which is modeled in the quartus ii software. table 4?79. clock network specifications (part 2 of 2) name description min typ max unit table 4?80. stratix ii gx ioe programmable delay on column pins note (1) parameter paths affected available settings minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min offset max offset min offset max offset min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad to i/o dataout to core 8 0 1781 0 2881 0 3025 0 3217 0 3,860 ps input delay from pin to input register pad to i/o input register 64 0 2053 0 3275 0 3439 0 3657 0 4388 ps delay from output register to output pin i/o output register to pad 2 0 332 0 500 0 525 0 559 0 670 ps output enable pin delay t xz , t zx 2 0 320 0 483 0 507 0 539 0 647 ps (1) the incremental values for the settings are generally linear. fo r the exact delay associated wi th each setting, use the late st version of the quartus ii software. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices.
default capacitive loading of different i/o standards see table 4?82 for default capacitive loading of different i/o standards. table 4?81. stratix ii gx ioe progr ammable delay on row pins note (1) parameter paths affected available settings minimum timing -3 speed grade -3 speed grade -4 speed grade -5 speed grade unit min offset max offset min offset max offset min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad to i/o dataout to logic array 8 0 1782 0 2876 0 3020 0 3212 0 3853 ps input delay from pin to input register pad to i/o input register 64 0 2054 0 3270 0 3434 0 3652 0 4381 ps delay from output register to output pin i/o output register to pad 2 0 332 0 500 0 525 0 559 0 670 ps output enable pin delay t xz , t zx 2 0 320 0 483 0 507 0 539 0 647 ps (1) the incremental values for the settings are generally linear. for the exact delay associated with each setting, use the late st version of the quartus ii software. table 4?82. default loading of different i/o standards for stratix ii gx devices (part 1 of 2) i/o standard capacitive load unit lvttl 0 pf lvcmos 0 pf 2.5 v 0 pf 1.8 v 0 pf 1.5 v 0 pf pci 10 pf pci-x 10 pf sstl-2 class i 0 pf sstl-2 class ii 0 pf
i/o delays see tables 4?83 through 4?87 for i/o delays. sstl-18 class i 0 pf sstl-18 class ii 0 pf 1.5-v hstl class i 0 pf 1.5-v hstl class ii 0 pf 1.8-v hstl class i 0 pf 1.8-v hstl class ii 0 pf differential sstl-2 class i 0 pf differential sstl-2 class ii 0 pf differential sstl-18 class i 0 pf differential sstl-18 class ii 0 pf 1.5-v differential hstl class i 0 pf 1.5-v differential hstl class ii 0 pf 1.8-v differential hstl class i 0 pf 1.8-v differential hstl class ii 0 pf lv d s 0 p f table 4?83. i/o delay parameters symbol parameter t dip delay from i/o datain to output pad t op delay from i/o output register to output pad t pcout delay from input pad to i/o dataout to core t pi delay from input pad to i/o input register table 4?82. default loading of different i/o standards for stratix ii gx devices (part 2 of 2) i/o standard capacitive load unit table 4?84. stratix ii gx i/o input de lay for column pins (part 1 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit lv t t l t pi 707 1223 1282 1364 1637 ps t pcout 428 787 825 878 1054 ps
2.5 v t pi 717 1210 1269 1349 1619 ps t pcout 438 774 812 863 1036 ps 1.8 v t pi 783 1366 1433 1523 1829 ps t pcout 504 930 976 1037 1246 ps 1.5 v t pi 786 1436 1506 1602 1922 ps t pcout 507 1000 1049 1116 1339 ps lv c m o s t pi 707 1223 1282 1364 1637 ps t pcout 428 787 825 878 1054 ps sstl-2 class i t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps sstl-2 class ii t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps sstl-18 class i t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps sstl-18 class ii t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.5-v hstl class i t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps 1.5-v hstl class ii t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps 1.8-v hstl class i t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.8-v hstl class ii t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps pci t pi 712 1214 1273 1354 1625 ps t pcout 433 778 816 868 1042 ps pci-x t pi 712 1214 1273 1354 1625 ps t pcout 433 778 816 868 1042 ps differential sstl-2 class i (1) t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps table 4?84. stratix ii gx i/o input de lay for column pins (part 2 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
differential sstl-2 class ii (1) t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps differential sstl-18 class i (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps differential sstl-18 class ii (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.8-v differential hstl class i (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.8-v differential hstl class ii (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.5-v differential hstl class i (1) t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps 1.5-v differential hstl class ii (1) t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps (1) these i/o standards are only supported on dqs pins. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?85. stratix ii gx i/o input delay for row pins (part 1 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit lv t t l t pi 749 1287 1350 1435 1723 ps t pcout 410 760 798 848 1018 ps 2.5 v t pi 761 1273 1335 1419 1704 ps t pcout 422 746 783 832 999 ps 1.8 v t pi 827 1427 1497 1591 1911 ps t pcout 488 900 945 1004 1206 ps 1.5 v t pi 830 1498 1571 1671 2006 ps t pcout 491 971 1019 1084 1301 ps table 4?84. stratix ii gx i/o input de lay for column pins (part 3 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
lv c m o s t pi 749 1287 1350 1435 1723 ps t pcout 410 760 798 848 1018 ps sstl-2 class i t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps sstl-2 class ii t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps sstl-18 class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps sstl-18 class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.5-v hstl class i t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps 1.5-v hstl class ii t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps 1.8-v hstl class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.8-v hstl class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps pci t pi 830 1498 1571 1671 2006 ps t pcout 491 971 1019 1084 1301 ps pci-x t pi 830 1498 1571 1671 2006 ps t pcout 491 971 1019 1084 1301 ps lv d s (1) t pi 540 948 994 1057 1269 ps t pcout 201 421 442 470 564 ps hypertransport t pi 540 948 994 1057 1269 ps t pcout 201 421 442 470 564 ps differential sstl-2 class i t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps differential sstl-2 class ii t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps table 4?85. stratix ii gx i/o input delay for row pins (part 2 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
differential sstl-18 class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps differential sstl-18 class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.8-v differential hstl class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.8-v differential hstl class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.5-v differential hstl class i t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps 1.5-v differential hstl class ii t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps (1) the parameters are only availabl e on the left side of the device. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?85. stratix ii gx i/o input delay for row pins (part 3 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
table 4?86. stratix ii gx i/o output de lay for column pins (part 1 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit lv t t l 4 m a t op 1236 2351 2467 2624 2820 ps t dip 1258 2417 2537 2698 2910 ps 8ma t op 1091 2036 2136 2272 2448 ps t dip 1113 2102 2206 2346 2538 ps 12 ma t op 1024 2036 2136 2272 2448 ps t dip 1046 2102 2206 2346 2538 ps 16 ma t op 998 1893 1986 2112 2279 ps t dip 1020 1959 2056 2186 2369 ps 20 ma t op 976 1787 1875 1994 2154 ps t dip 998 1853 1945 2068 2244 ps 24 ma (1) t op 969 1788 1876 1995 2156 ps t dip 991 1854 1946 2069 2246 ps lv c m o s 4 m a t op 1091 2036 2136 2272 2448 ps t dip 1113 2102 2206 2346 2538 ps 8ma t op 999 1786 1874 1993 2153 ps t dip 1021 1852 1944 2067 2243 ps 12 ma t op 971 1720 1805 1919 2075 ps t dip 993 1786 1875 1993 2165 ps 16 ma t op 978 1693 1776 1889 2043 ps t dip 1000 1759 1846 1963 2133 ps 20 ma t op 965 1677 1759 1871 2025 ps t dip 987 1743 1829 1945 2115 ps 24 ma (1) t op 954 1659 1741 1851 2003 ps t dip 976 1725 1811 1925 2093 ps
2.5 v 4 ma t op 1053 2063 2165 2302 2480 ps t dip 1075 2129 2235 2376 2570 ps 8ma t op 1001 1841 1932 2054 2218 ps t dip 1023 1907 2002 2128 2308 ps 12 ma t op 980 1742 1828 1944 2101 ps t dip 1002 1808 1898 2018 2191 ps 16 ma (1) t op 962 1679 1762 1873 2027 ps t dip 984 1745 1832 1947 2117 ps 1.8 v 2 ma t op 1093 2904 3048 3241 3472 ps t dip 1115 2970 3118 3315 3562 ps 4ma t op 1098 2248 2359 2509 2698 ps t dip 1120 2314 2429 2583 2788 ps 6ma t op 1022 2024 2124 2258 2434 ps t dip 1044 2090 2194 2332 2524 ps 8ma t op 1024 1947 2043 2172 2343 ps t dip 1046 2013 2113 2246 2433 ps 10 ma t op 978 1882 1975 2100 2266 ps t dip 1000 1948 2045 2174 2356 ps 12 ma (1) t op 979 1833 1923 2045 2209 ps t dip 1001 1899 1993 2119 2299 ps 1.5 v 2 ma t op 1073 2505 2629 2795 3002 ps t dip 1095 2571 2699 2869 3092 ps 4ma t op 1009 2023 2123 2257 2433 ps t dip 1031 2089 2193 2331 2523 ps 6ma t op 1012 1923 2018 2146 2315 ps t dip 1034 1989 2088 2220 2405 ps 8ma (1) t op 971 1878 1970 2095 2262 ps t dip 993 1944 2040 2169 2352 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 2 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
sstl-2 class i 8 ma t op 957 1715 1799 1913 2041 ps t dip 979 1781 1869 1987 2131 ps 12 ma (1) t op 940 1672 1754 1865 1991 ps t dip 962 1738 1824 1939 2081 ps sstl-2 class ii 16 ma t op 918 1609 1688 1795 1918 ps t dip 940 1675 1758 1869 2008 ps 20 ma t op 919 1598 1676 1783 1905 ps t dip 941 1664 1746 1857 1995 ps 24 ma (1) t op 915 1596 1674 1781 1903 ps t dip 937 1662 1744 1855 1993 ps sstl-18 class i 4 ma t op 953 1690 1773 1886 2012 ps t dip 975 1756 1843 1960 2102 ps 6ma t op 958 1656 1737 1848 1973 ps t dip 980 1722 1807 1922 2063 ps 8ma t op 937 1640 1721 1830 1954 ps t dip 959 1706 1791 1904 2044 ps 10 ma t op 942 1638 1718 1827 1952 ps t dip 964 1704 1788 1901 2042 ps 12 ma (1) t op 936 1626 1706 1814 1938 ps t dip 958 1692 1776 1888 2028 ps sstl-18 class ii 8 ma t op 925 1597 1675 1782 1904 ps t dip 947 1663 1745 1856 1994 ps 16 ma t op 937 1578 1655 1761 1882 ps t dip 959 1644 1725 1835 1972 ps 18 ma t op 933 1585 1663 1768 1890 ps t dip 955 1651 1733 1842 1980 ps 20 ma (1) t op 933 1583 1661 1766 1888 ps t dip 955 1649 1731 1840 1978 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 3 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
1.8-v hstl class i 4ma t op 956 1608 1687 1794 1943 ps t dip 978 1674 1757 1868 2033 ps 6ma t op 962 1595 1673 1779 1928 ps t dip 984 1661 1743 1853 2018 ps 8ma t op 940 1586 1664 1769 1917 ps t dip 962 1652 1734 1843 2007 ps 10 ma t op 944 1591 1669 1775 1923 ps t dip 966 1657 1739 1849 2013 ps 12 ma (1) t op 936 1585 1663 1768 1916 ps t dip 958 1651 1733 1842 2006 ps 1.8-v hstl class ii 16 ma t op 919 1385 1453 1545 1680 ps t dip 941 1451 1523 1619 1770 ps 18 ma t op 921 1394 1462 1555 1691 ps t dip 943 1460 1532 1629 1781 ps 20 ma (1) t op 921 1402 1471 1564 1700 ps t dip 943 1468 1541 1638 1790 ps 1.5-v hstl class i 4ma t op 956 1607 1686 1793 1942 ps t dip 978 1673 1756 1867 2032 ps 6ma t op 961 1588 1666 1772 1920 ps t dip 983 1654 1736 1846 2010 ps 8ma t op 943 1590 1668 1774 1922 ps t dip 965 1656 1738 1848 2012 ps 10 ma t op 943 1592 1670 1776 1924 ps t dip 965 1658 1740 1850 2014 ps 12 ma (1) t op 937 1590 1668 1774 1922 ps t dip 959 1656 1738 1848 2012 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 4 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
1.5-v hstl class ii 16 ma t op 924 1431 1501 1596 1734 ps t dip 946 1497 1571 1670 1824 ps 18 ma t op 927 1439 1510 1605 1744 ps t dip 949 1505 1580 1679 1834 ps 20 ma (1) t op 929 1450 1521 1618 1757 ps t dip 951 1516 1591 1692 1847 ps pci - t op 1082 1956 2051 2176 2070 ps t dip 1104 2022 2121 2250 2160 ps pci-x - t op 1082 1956 2051 2176 2070 ps t dip 1104 2022 2121 2250 2160 ps differential sstl- 2 class i (2) 8ma t op 957 1715 1799 1913 2041 ps t dip 979 1781 1869 1987 2131 ps 12 ma t op 940 1672 1754 1865 1991 ps t dip 962 1738 1824 1939 2081 ps differential sstl-2 class ii (2) 16 ma t op 918 1609 1688 1795 1918 ps t dip 940 1675 1758 1869 2008 ps 20 ma t op 919 1598 1676 1783 1905 ps t dip 941 1664 1746 1857 1995 ps 24 ma t op 915 1596 1674 1781 1903 ps t dip 937 1662 1744 1855 1993 ps differential sstl-18 class i (2) 4ma t op 953 1690 1773 1886 2012 ps t dip 975 1756 1843 1960 2102 ps 6ma t op 958 1656 1737 1848 1973 ps t dip 980 1722 1807 1922 2063 ps 8ma t op 937 1640 1721 1830 1954 ps t dip 959 1706 1791 1904 2044 ps 10 ma t op 942 1638 1718 1827 1952 ps t dip 964 1704 1788 1901 2042 ps 12 ma t op 936 1626 1706 1814 1938 ps t dip 958 1692 1776 1888 2028 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 5 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
differential sstl-18 class ii (2) 8ma t op 925 1597 1675 1782 1904 ps t dip 947 1663 1745 1856 1994 ps 16 ma t op 937 1578 1655 1761 1882 ps t dip 959 1644 1725 1835 1972 ps 18 ma t op 933 1585 1663 1768 1890 ps t dip 955 1651 1733 1842 1980 ps 20 ma t op 933 1583 1661 1766 1888 ps t dip 955 1649 1731 1840 1978 ps 1.8-v differential hstl class i (2) 4ma t op 956 1608 1687 1794 1943 ps t dip 978 1674 1757 1868 2033 ps 6ma t op 962 1595 1673 1779 1928 ps t dip 984 1661 1743 1853 2018 ps 8ma t op 940 1586 1664 1769 1917 ps t dip 962 1652 1734 1843 2007 ps 10 ma t op 944 1591 1669 1775 1923 ps t dip 966 1657 1739 1849 2013 ps 12 ma t op 936 1585 1663 1768 1916 ps t dip 958 1651 1733 1842 2006 ps 1.8-v differential hstl class ii (2) 16 ma t op 919 1385 1453 1545 1680 ps t dip 941 1451 1523 1619 1770 ps 18 ma t op 921 1394 1462 1555 1691 ps t dip 943 1460 1532 1629 1781 ps 20 ma t op 921 1402 1471 1564 1700 ps t dip 943 1468 1541 1638 1790 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 6 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
1.5-v differential hstl class i (2) 4ma t op 956 1607 1686 1793 1942 ps t dip 978 1673 1756 1867 2032 ps 6ma t op 961 1588 1666 1772 1920 ps t dip 983 1654 1736 1846 2010 ps 8ma t op 943 1590 1668 1774 1922 ps t dip 965 1656 1738 1848 2012 ps 10 ma t op 943 1592 1670 1776 1924 ps t dip 965 1658 1740 1850 2014 ps 12 ma t op 937 1590 1668 1774 1922 ps t dip 959 1656 1738 1848 2012 ps 1.5-v differential hstl class ii (2) 16 ma t op 924 1431 1501 1596 1734 ps t dip 946 1497 1571 1670 1824 ps 18 ma t op 927 1439 1510 1605 1744 ps t dip 949 1505 1580 1679 1834 ps 20 ma t op 929 1450 1521 1618 1757 ps t dip 951 1516 1591 1692 1847 ps (1) this is the default setting in the quartus ii software. (2) these i/o standards are only supported on dqs pins. (3) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (4) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?87. stratix ii gx i/o output delay for row pins (part 1 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit lv t t l 4 m a t op 1328 2655 2786 2962 3189 ps t dip 1285 2600 2729 2902 3116 ps 8ma t op 1200 2113 2217 2357 2549 ps t dip 1157 2058 2160 2297 2476 ps 12 ma (1) t op 1144 2081 2184 2321 2512 ps t dip 1101 2026 2127 2261 2439 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 7 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
lv c m o s 4 m a t op 1200 2113 2217 2357 2549 ps t dip 1157 2058 2160 2297 2476 ps 8ma (1) t op 1094 1853 1944 2067 2243 ps t dip 1051 1798 1887 2007 2170 ps 12 ma (1) t op 1061 1723 1808 1922 2089 ps t dip 1018 1668 1751 1862 2016 ps 2.5 v 4 ma t op 1183 2091 2194 2332 2523 ps t dip 1140 2036 2137 2272 2450 ps 8ma t op 1080 1872 1964 2088 2265 ps t dip 1037 1817 1907 2028 2192 ps 12 ma (1) t op 1061 1775 1862 1980 2151 ps t dip 1018 1720 1805 1920 2078 ps 1.8 v 2 ma t op 1253 2954 3100 3296 3542 ps t dip 1210 2899 3043 3236 3469 ps 4ma t op 1242 2294 2407 2559 2763 ps t dip 1199 2239 2350 2499 2690 ps 6ma t op 1131 2039 2140 2274 2462 ps t dip 1088 1984 2083 2214 2389 ps 8ma (1) t op 1100 1942 2038 2166 2348 ps t dip 1057 1887 1981 2106 2275 ps 1.5 v 2 ma t op 1213 2530 2655 2823 3041 ps t dip 1170 2475 2598 2763 2968 ps 4ma (1) t op 1106 2020 2120 2253 2440 ps t dip 1063 1965 2063 2193 2367 ps sstl-2 class i 8 ma t op 1050 1759 1846 1962 2104 ps t dip 1007 1704 1789 1902 2031 ps 12 ma (1) t op 1026 1694 1777 1889 2028 ps t dip 983 1639 1720 1829 1955 ps sstl-2 class ii 16 ma (1) t op 992 1581 1659 1763 1897 ps t dip 949 1526 1602 1703 1824 ps table 4?87. stratix ii gx i/o output delay for row pins (part 2 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
sstl-18 class i 4ma t op 1038 1709 1793 1906 2046 ps t dip 995 1654 1736 1846 1973 ps 6ma t op 1042 1648 1729 1838 1975 ps t dip 999 1593 1672 1778 1902 ps 8ma t op 1018 1633 1713 1821 1958 ps t dip 975 1578 1656 1761 1885 ps 10 ma (1) t op 1021 1615 1694 1801 1937 ps t dip 978 1560 1637 1741 1864 ps 1.8-v hstl class i 4ma t op 1019 1610 1689 1795 1956 ps t dip 976 1555 1632 1735 1883 ps 6ma t op 1022 1580 1658 1762 1920 ps t dip 979 1525 1601 1702 1847 ps 8ma t op 1004 1576 1653 1757 1916 ps t dip 961 1521 1596 1697 1843 ps 10 ma t op 1008 1567 1644 1747 1905 ps t dip 965 1512 1587 1687 1832 ps 12 ma (1) t op 999 1566 1643 1746 1904 ps t dip 956 1511 1586 1686 1831 ps 1.5-v hstl class i 4ma t op 1018 1591 1669 1774 1933 ps t dip 975 1536 1612 1714 1860 ps 6ma t op 1021 1579 1657 1761 1919 ps t dip 978 1524 1600 1701 1846 ps 8ma (1) t op 1006 1572 1649 1753 1911 ps t dip 963 1517 1592 1693 1838 ps differential sstl-2 class i 8ma t op 1050 1759 1846 1962 2104 ps t dip 1007 1704 1789 1902 2031 ps 12 ma t op 1026 1694 1777 1889 2028 ps t dip 983 1639 1720 1829 1955 ps differential sstl-2 class ii 16 ma t op 992 1581 1659 1763 1897 ps t dip 949 1526 1602 1703 1824 ps table 4?87. stratix ii gx i/o output delay for row pins (part 3 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
maximum input and output clock toggle rate maximum clock toggle rate is de fined as the maximum frequency achievable for a clock type signal at an i/o pin. the i/o pin can be a regular i/o pin or a de dicated clock i/o pin. the maximum clock toggle rate is different from the maximum data bit rate. if the maximum clock toggle rate on a regular i/o pin is 300 mhz, the maximum data bit rate for dual data rate (ddr) could be potentially as high as 600 mbps on the same i/o pin. tables 4?88 through 4?90 specify the maximum inpu t clock toggle rates. tables 4?91 through 4?96 specify the maximum output clock toggle rates at 0 pf load. table 4?97 specifies the derating factors for the output clock toggle rate for a non 0 pf load. differential sstl-18 class i 4ma t op 1038 1709 1793 1906 2046 ps t dip 995 1654 1736 1846 1973 ps 6ma t op 1042 1648 1729 1838 1975 ps t dip 999 1593 1672 1778 1902 ps 8ma t op 1018 1633 1713 1821 1958 ps t dip 975 1578 1656 1761 1885 ps 10 ma t op 1021 1615 1694 1801 1937 ps t dip 978 1560 1637 1741 1864 ps lv d s (2) -t op 1067 1723 1808 1922 2089 ps t dip 1024 1668 1751 1862 2016 ps hypertransport - t op 1053 1723 1808 1922 2089 ps t dip 1010 1668 1751 1862 2016 ps (1) this is the default setting in the quartus ii software. (2) the parameters are only availabl e on the left side of the device. (3) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (4) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?87. stratix ii gx i/o output delay for row pins (part 4 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit
to calculate the output toggle rate for a non 0 pf load, use this formula: the toggle rate for a non 0 pf load = 1,000 / (1,000/ toggle rate at 0 pf load + derating factor load value in pf /1,000) for example, the output toggle rate at 0 pf load for sstl-18 class ii 20 ma i/o standard is 550 mhz on a -3 device clock output pin. the derating factor is 94 ps/pf. for a 10 pf load the toggle ra te is calculated as: 1,000 / (1,000/550 + 94 10 /1,000) = 363 (mhz) table 4?88 shows the maximum input clock toggle rates for stratix ii gx device column pins. table 4?88. stratix ii gx maximum input cloc k rate for column i/o pins (part 1 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit lvttl 500 500 450 mhz 2.5 v 500 500 450 mhz 1.8 v 500 500 450 mhz 1.5 v 500 500 450 mhz lvcmos 500 500 450 mhz sstl-2 class i 500 500 500 mhz sstl-2 class ii 500 500 500 mhz sstl-18 class i 500 500 500 mhz sstl-18 class i i 500 500 500 mhz 1.5-v hstl class i 500 500 500 mhz 1.5-v hstl class i i 500 500 500 mhz 1.8-v hstl class i 500 500 500 mhz 1.8-v hstl class ii 500 500 500 mhz pci 500 500 450 mhz pci-x 500 500 450 mhz differential sstl-2 class i 500 500 500 mhz differential sstl-2 class ii 500 500 500 mhz differential sstl-18 class i 500 500 500 mhz
table 4?89 shows the maximum input clock toggle rates for stratix ii gx device row pins. differential sstl-18 class i i 500 500 500 mhz 1.8-v differential hstl class i 500 500 500 mhz 1.8-v differential hstl class ii 500 500 500 mhz 1.5-v differential hstl class i 500 500 500 mhz 1.5-v differential hstl class i i 500 500 500 mhz 1.2-v hstl 280 250 250 mhz 1.2-v differential hstl 280 250 250 mhz table 4?88. stratix ii gx maximum input cloc k rate for column i/o pins (part 2 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit table 4?89. stratix ii gx maximum input cl ock rate for row i/o pins (part 1 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit lvttl 500 500 450 mhz 2.5 v 500 500 450 mhz 1.8 v 500 500 450 mhz 1.5 v 500 500 450 mhz lvcmos 500 500 450 mhz sstl-2 class i 500 500 500 mhz sstl-2 class ii 500 500 500 mhz sstl-18 class i 500 500 500 mhz sstl-18 class ii 500 500 500 mhz 1.5-v hstl class i 500 500 500 mhz 1.5-v hstl class ii 500 500 500 mhz 1.8-v hstl class i 500 500 500 mhz 1.8-v hstl class ii 500 500 500 mhz pci 500 500 425 mhz pci-x 500 500 425 mhz differential sstl-2 class i 500 500 500 mhz
table 4?90 shows the maximum input clock toggle rates for stratix ii gx device dedicated clock pins. differential sstl-2 class ii 500 500 500 mhz differential sstl-18 class i 500 500 500 mhz differential sstl-18 class i i 500 500 500 mhz 1.8-v differential hstl class i 500 500 500 mhz 1.8-v differential hstl class i i 500 500 500 mhz 1.5-v differential hstl class i 500 500 500 mhz 1.5-v differential hstl class ii 500 500 500 mhz lv d s (1) 520 520 420 mhz hypertransport 520 520 420 mhz (1) the parameters are only availabl e on the left side of the device. table 4?89. stratix ii gx maximum input cl ock rate for row i/o pins (part 2 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit table 4?90. stratix ii gx maximu m input clock rate for dedi cated clock pins (part 1 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit lvttl 500 500 400 mhz 2.5 v 500 500 400 mhz 1.8 v 500 500 400 mhz 1.5 v 500 500 400 mhz lvcmos 500 500 400 mhz sstl-2 class i 500 500 500 mhz sstl-2 class ii 500 500 500 mhz sstl-18 class i 500 500 500 mhz sstl-18 class ii 500 500 500 mhz 1.5-v hstl class i 500 500 500 mhz 1.5-v hstl class ii 500 500 500 mhz 1.8-v hstl class i 500 500 500 mhz
1.8-v hstl class i 500 500 500 mhz pci 500 500 400 mhz pci-x 500 500 400 mhz differential sstl-2 class i 500 500 500 mhz differential sstl-2 class ii 500 500 500 mhz differential sstl-18 class i 500 500 500 mhz differential sstl-18 class ii 500 500 500 mhz 1.8-v differential hstl class i 500 500 500 mhz 1.8-v differential hstl class ii 500 500 500 mhz 1.5-v differential hstl class i 500 500 500 mhz 1.5-v differential hstl class i i 500 500 500 mhz hypertransport (1) 717 717 640 mhz 450 450 400 mhz lvpecl (1) , (2) 717 717 640 mhz 450 450 400 mhz lv d s (1) 717 717 640 mhz 450 450 400 mhz (1) the first set of numbers refers to the hio dedicated clock pins. the second set of numbers refers to the vio dedicated clock pins. (2) lvpecl is only supported on column clock pins. table 4?90. stratix ii gx maximu m input clock rate for dedi cated clock pins (part 2 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit
table 4?91 shows the maximum output clock toggle rates for stratix ii gx device column pins. table 4?91. stratix ii gx maximum output cl ock rate for column pins (part 1 of 3) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl 4 ma 270 225 210 mhz 8 ma 435 355 325 mhz 12 ma 580 475 420 mhz 16 ma 720 594 520 mhz 20 ma 875 700 610 mhz 24 ma (1) 1030 794 670 mhz lvcmos 4 ma 290 250 230 mhz 8 ma 565 480 440 mhz 12 ma 790 710 670 mhz 16 ma 1020 925 875 mhz 20 ma 1066 985 935 mhz 24 ma (1) 1100 1040 1000 mhz 2.5 v 4 ma 230 194 180 mhz 8 ma 430 380 380 mhz 12 ma 630 575 550 mhz 16 ma (1) 930 845 820 mhz 1.8 v 2 ma 120 109 104 mhz 4 ma 285 250 230 mhz 6 ma 450 390 360 mhz 8 ma 660 570 520 mhz 10 ma 905 805 755 mhz 12 ma (1) 1131 1040 990 mhz 1.5 v 2 ma 244 200 180 mhz 4 ma 470 370 325 mhz 6 ma 550 430 375 mhz 8ma (1) 625 495 420 mhz sstl-2 class i 8 ma 400 300 300 mhz 12 ma (1) 400 400 350 mhz sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma (1) 400 400 350 mhz
sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma (1) 700 550 400 mhz sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma (1) 550 500 450 mhz 1.8-v hstl class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma (1) 700 700 650 mhz 1.8-v hstl class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma (1) 650 550 550 mhz 1.5-v hstl class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma (1) 700 700 700 mhz 1.5-v hstl class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma (1) 700 650 600 mhz pci - 1000 790 670 mhz pci-x - 1000 790 670 mhz differential sstl-2 class i 8 ma 400 300 300 mhz 12 ma 400 400 350 mhz differential sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma 400 400 350 mhz table 4?91. stratix ii gx maximum output cl ock rate for column pins (part 2 of 3) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit
differential sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma 700 550 400 mhz differential sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma 550 500 450 mhz 1.8-v hstl differential class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma 700 700 650 mhz 1.8-v hstl differential class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma 650 550 550 mhz 1.5-v hstl differential class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma 700 700 700 mhz 1.5-v hstl differential class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma 700 650 600 mhz (1) this is the default setting in the quartus ii software. table 4?91. stratix ii gx maximum output cl ock rate for column pins (part 3 of 3) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit
table 4?92 shows the maximum output clock toggle rates for stratix ii gx device row pins. table 4?92. stratix ii gx maximum output clock rate for row pins (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl 4 ma 270 225 210 mhz 8 ma 435 355 325 mhz 12 ma (1) 580 475 420 mhz lvcmos 4 ma 290 250 230 mhz 8 ma 565 480 440 mhz 12 ma (1) 350 350 297 mhz 2.5 v 4 ma 230 194 180 mhz 8 ma 430 380 380 mhz 12 ma (1) 630 575 550 mhz 1.8 v 2 ma 120 109 104 mhz 4 ma 285 250 230 mhz 6 ma 450 390 360 mhz 8ma (1) 660 570 520 mhz 1.5 v 2 ma 244 200 180 mhz 4ma (1) 470 370 325 mhz sstl-2 class i 8 ma 400 300 300 mhz 12 ma (1) 400 400 350 mhz sstl-2 class ii 16 ma 350 350 300 mhz 20 ma (1) 350 350 297 mhz sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma (1) 350 350 297 mhz 1.8-v hstl class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma (1) 700 700 650 mhz 1.5-v hstl class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8ma (1) 700 650 600 mhz
table 4?93 shows the maximum output clock toggle rate for stratix ii gx device dedicated clock pins. differential sstl-2 class i 8 ma 400 300 300 mhz 12 ma 400 400 350 mhz differential sstl-2 class ii 16 ma (1) 350 350 300 mhz differential sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma (1) 500 400 400 mhz lvds - 717 717 640 mhz hypertransport - 717 717 640 mhz (1) this is the default setting in quartus ii software. table 4?92. stratix ii gx maximum output clock rate for row pins (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 1 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit lvttl 4 ma 270 225 210 mhz 8 ma 435 355 325 mhz 12 ma 580 475 420 mhz 16 ma 720 594 520 mhz 20 ma 875 700 610 mhz 24 ma (1) 1030 794 670 mhz lvcmos 4 ma 290 250 230 mhz 8 ma 565 480 440 mhz 12 ma 790 710 670 mhz 16 ma 1020 925 875 mhz 20 ma 1066 985 935 mhz 24 ma (1) 1100 1040 1000 mhz
2.5 v 4 ma 230 194 180 mhz 8 ma 430 380 380 mhz 12 ma 630 575 550 mhz 16 ma (1) 930 845 820 mhz 1.8 v 2 ma 120 109 104 mhz 4 ma 285 250 230 mhz 6 ma 450 390 360 mhz 8 ma 660 570 520 mhz 10 ma 905 805 755 mhz 12 ma (1) 1131 1040 990 mhz 1.5 v 2 ma 244 200 180 mhz 4 ma 470 370 325 mhz 6 ma 550 430 375 mhz 8 ma (1) 625 495 420 mhz sstl-2 class i 8 ma 400 300 300 mhz 12 ma (1) 400 400 350 mhz sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma (1) 400 400 350 mhz sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma (1) 650 550 400 mhz sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma (1) 550 500 450 mhz 1.8-v hstl class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma (1) 700 700 650 mhz table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 2 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit
1.8-v hstl class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma (1) 550 550 550 mhz 1.5-v hstl class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma (1) 700 700 700 mhz 1.5-v hstl class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma (1) 700 650 600 mhz pci - 1000 790 670 mhz pci-x - 1000 790 670 mhz differential sstl-2 class i 8 ma 400 300 300 mhz 12 ma 400 400 350 mhz differential sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma 400 400 350 mhz differential sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma 650 550 400 mhz differential sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma 550 500 450 mhz 1.8-v differential class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma 700 700 650 mhz table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 3 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit
table 4?94 shows the maximum output clock toggle rate for stratix ii gx device series-terminated column pins. 1.8-v differential class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma 550 550 550 mhz 1.5-v differential class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma 700 700 700 mhz 1.5-v differential class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma 700 650 600 mhz hypertransport - 300 250 125 mhz lvpecl - 450 400 300 mhz (1) this is the default setting in quartus ii software. table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 4 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit table 4?94. stratix ii gx maximum ou tput clock rate for column pi ns (series termination) (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl oct_25_ohms 400 400 350 mhz oct_50_ohms 400 400 350 mhz lvcmos oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 2.5 v oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 1.8 v oct_25_ohms 700 550 450 mhz oct_50_ohms 700 550 450 mhz 1.5 v oct_50_ohms 550 450 400 mhz sstl-2 class i oct_50_ohms 600 500 500 mhz sstl-2 class ii oct_25_ohms 600 550 500 mhz
table 4?95 shows the maximum output clock toggle rate for stratix ii gx device series-terminated row pins. sstl-18 class i oct_50_ohms 560 400 350 mhz sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.5-v hstl class i oct_50_ohms 600 550 500 mhz 1.8-v hstl class i oct_50_ohms 650 600 600 mhz 1.8-v hstl class ii oct_25_ohms 500 500 450 mhz differential sstl-2 class i oct_50_ohms 600 500 500 mhz differential sstl-2 class ii oct_25_ohms 600 550 500 mhz differential sstl-18 class i oct_50_ohms 560 400 350 mhz differential sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.8-v differential hstl class i oct_50_ohms 650 600 600 mhz 1.8-v differential hstl class ii oct_25_ohms 500 500 450 mhz 1.5-v differential hstl class i oct_50_ohms 600 550 500 mhz table 4?94. stratix ii gx maximum ou tput clock rate for column pi ns (series termination) (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?95. stratix ii gx maximum output clock rate for row pins (series termination) (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl oct_25_ohms 400 400 350 mhz oct_50_ohms 400 400 350 mhz lvcmos oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 2.5 v oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 1.8 v oct_50_ohms 700 550 450 mhz 1.5 v oct_50_ohms 550 450 400 mhz
table 4?96 shows the maximum output clock toggle rate for stratix ii gx device series-terminated dedicated clock pins. sstl-2 class i oct_50_ohms 600 500 500 mhz sstl-2 class ii oct_25_ohms 600 550 500 mhz sstl-18 class i oct_50_ohms 590 400 350 mhz 1.5-v hstl class i oct_50_ohms 600 550 500 mhz 1.8-v hstl class i oct_50_ohms 650 600 600 mhz differential sstl-2 class i oct_50_ohms 600 500 500 mhz differential sstl-2 class ii oct_25_ohms 600 550 500 mhz differential sstl-18 class i oct_50_ohms 590 400 350 mhz differential hstl-18 class i oct_50_ohms 650 600 600 mhz differential hstl-15 class i oct_50_ohms 600 550 500 table 4?95. stratix ii gx maximum output clock rate for row pins (series termination) (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?96. stratix ii gx maximum output clock rate for dedicated clock pins (series termination) (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl oct_25_ohms 400 400 350 mhz oct_50_ohms 400 400 350 mhz lvcmos oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 2.5 v oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 1.8 v oct_25_ohms 700 550 450 mhz oct_50_ohms 700 550 450 mhz 1.5 v oct_50_ohms 550 450 400 mhz sstl-2 class i oct_50_ohms 600 500 500 mhz sstl-2 class ii oct_25_ohms 600 550 500 mhz sstl-18 class i oct_50_ohms 450 400 350 mhz
table 4?97 specifies the derating factors for the output clock toggle rate for a non 0 pf load. sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.5-v hstl class i oct_50_ohms 600 550 500 mhz 1.8-v hstl class i oct_50_ohms 650 600 600 mhz 1.8-v hstl class ii oct_25_ohms 500 500 450 mhz differential sstl-2 class i oct_50_ohms 600 500 500 mhz differential sstl-2 class ii oct_25_ohms 600 550 500 mhz differential sstl-18 class i oct_50_ohms 560 400 350 mhz differential sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.8-v differential hstl class i oct_50_ohms 650 600 600 mhz 1.8-v differential hstl class ii oct_25_ohms 500 500 450 mhz 1.5-v differential hstl class i oct_50_ohms 600 550 500 mhz table 4?96. stratix ii gx maximum output clock rate for dedicated clock pins (series termination) (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?97. maximum output clock toggle rate derating factors (part 1 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5 3.3-v lvttl 4 ma 478 510 510 478 510 510 466 510 510 8 ma 260 333 333 260 333 333 291 333 333 12 ma 213 247 247 213 247 247 211 247 247 16 ma 136 197 197 - - - 166 197 197 20 ma 138 187 187 - - - 154 187 187 24 ma 134 177 177 - - - 143 177 177
3.3-v lvcmos 4 ma 377 391 391 377 391 391 377 391 391 8 ma 206 212 212 206 212 212 178 212 212 12 ma 141 145 145 - - - 115 145 145 16 ma 108 111 111 - - - 86 111 111 20 ma 83 88 88 - - - 79 88 88 24 ma 65 72 72 - - - 74 72 72 2.5-v lvttl/ lv c m o s 4 ma 387 427 427 387 427 427 391 427 427 8 ma 163 224 224 163 224 224 170 224 224 12 ma 142 203 203 142 203 203 152 203 203 16 ma 120 182 182 - - - 134 182 182 1.8-v lvttl/ lv c m o s 2 ma 951 1,421 1,421 951 1,421 1,421 904 1,421 1,421 4 ma 405 516 516 405 516 516 393 516 516 6 ma 261 325 325 261 325 325 253 325 325 8 ma 223 274 274 223 274 274 224 274 274 10 ma 194 236 236 - - - 199 236 236 12 ma 174 209 209 - - - 180 209 209 1.5-v lvttl/ lv c m o s 2 ma 652 963 963 652 963 963 618 963 963 4 ma 333 347 347 333 347 347 270 347 347 6 ma 182 247 247 - - - 198 247 247 8 ma 135 194 194 - - - 155 194 194 sstl-2 class i 8 ma 364 680 680 364 680 680 350 680 680 12 ma 163 207 207 163 207 207 188 207 207 sstl-2 class ii 16 ma 118 147 147 118 147 147 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 sstl-18 class i 4 ma 458 570 570 458 570 570 505 570 570 6 ma 305 380 380 305 380 380 336 380 380 8 ma 225 282 282 225 282 282 248 282 282 10 ma 167 220 220 167 220 220 190 220 220 12 ma 129 175 175 - - - 148 175 175 table 4?97. maximum output clock toggle rate derating factors (part 2 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
sstl-18 class ii 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 2.5-v sstl-2 class i 8 ma 364 680 680 364 680 680 350 680 680 12 ma 163 207 207 163 207 207 188 207 207 2.5-v sstl-2 class ii 16 ma 118 147 147 118 147 147 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 1.8-v sstl-18 class i 4 ma 458 570 570 458 570 570 505 570 570 6 ma 305 380 380 305 380 380 336 380 380 8 ma 225 282 282 225 282 282 248 282 282 10 ma 167 220 220 167 220 220 190 220 220 12 ma 129 175 175 - - - 148 175 175 1.8-v sstl-18 class ii 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 1.8-v hstl class i 4 ma 245 282 282 245 282 282 229 282 282 6 ma 164 188 188 164 188 188 153 188 188 8 ma 123 140 140 123 140 140 114 140 140 10 ma 110 124 124 110 124 124 108 124 124 12 ma 97 110 110 97 110 110 104 110 110 1.8-v hstl class ii 16 ma 101 104 104 - - - 99 104 104 18 ma 98 102 102 - - - 93 102 102 20 ma 93 99 99 - - - 88 99 99 1.5-v hstl class i 4 ma 168 196 196 168 196 196 188 196 196 6 ma 112 131 131 112 131 131 125 131 131 8 ma 84 99 99 84 99 99 95 99 99 10 ma 87 98 98 - - - 90 98 98 12 ma 86 98 98 - - - 87 98 98 table 4?97. maximum output clock toggle rate derating factors (part 3 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
1.5-v hstl class ii 16 ma 95 101 101 - - - 96 101 101 18 ma 95 100 100 - - - 101 100 100 20 ma 94 101 101 - - - 104 101 101 2.5-v differential sstl class ii (3) 8 ma 364 680 680 - - - 350 680 680 12 ma 163 207 207 - - - 188 207 207 16 ma 118 147 147 - - - 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 1.8-v differential sstl class i (3) 4 ma 458 570 570 - - - 505 570 570 6 ma 305 380 380 - - - 336 380 380 8 ma 225 282 282 - - - 248 282 282 10 ma 167 220 220 - - - 190 220 220 12 ma 129 175 175 - - - 148 175 175 1.8-v differential sstl class ii (3) 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 1.8-v differential hstl class i (3) 4 ma 245 282 282 - - - 229 282 282 6 ma 164 188 188 - - - 153 188 188 8 ma 123 140 140 - - - 114 140 140 10 ma 110 124 124 - - - 108 124 124 12 ma 97 110 110 - - - 104 110 110 1.8-v differential hstl class ii (3) 16 ma 101 104 104 - - - 99 104 104 18 ma 98 102 102 - - - 93 102 102 20 ma 93 99 99 - - - 88 99 99 1.5-v differential hstl class i (3) 4 ma 168 196 196 - - - 188 196 196 6 ma 112 131 131 - - - 125 131 131 8 ma 84 99 99 - - - 95 99 99 10 ma 87 98 98 - - - 90 98 98 12 ma 86 98 98 - - - 87 98 98 table 4?97. maximum output clock toggle rate derating factors (part 4 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
1.5-v differential hstl class ii (3) 16 ma 95 101 101 - - - 96 101 101 18 ma 95 100 100 - - - 101 100 100 20 ma 94 101 101 - - - 104 101 101 3.3-v pci 134 177 177 - - - 143 177 177 3.3-v pci-x 134 177 177 - - - 143 177 177 lvds - - - 155 (1) 155 (1) 155 (1) 134 134 134 lvpecl (4) - - - - - - 134 134 134 3.3-v lvttl oct 50 133 152 152 133 152 152 147 152 152 2.5-v lvttl oct 50 207 274 274 207 274 274 235 274 274 1.8-v lvttl oct 50 151 165 165 151 165 165 153 165 165 3.3-v lvcmos oct 50 300 316 316 300 316 316 263 316 316 1.5-v lvcmos oct 50 157 171 171 157 171 171 174 171 171 sstl-2 class i oct 50 121 134 134 121 134 134 77 134 134 sstl-2 class ii oct 25 56 101 101 56 101 101 58 101 101 sstl-18 class i oct 50 100 123 123 100 123 123 106 123 123 sstl-18 class ii oct 25 61 110 110 - - - 59 110 110 1.2-v hstl (2) oct 50 95 - - - - - 95 - - (1) for lvds output on row i/o pins the toggle rate derating factors apply to loads larger than 5 pf. in the derating calculation, subtract 5 pf from the intended load value in pf for the correct result. for a load less than or equal to 5pf, refer to tables 4?91 through 4?95 for output toggle rates. (2) 1.2-v hstl is only supported on column i/o pins on -3 devices. (3) differential hstl and sstl is only supported on column clock and dqs outputs. (4) lvpecl is only supported on column clock outputs. table 4?97. maximum output clock toggle rate derating factors (part 5 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
duty cycle distortion duty cycle distortion (dcd) describe s how much the falling edge of a clock is off from its idea l position. the ideal position is when both the clock high time (clkh) and the clock low time (clkl) equal half of the clock period (t), as shown in figure 4?11 . dcd is the deviation of the non-ideal falling edge from the ideal falling edge, such as d1 for the falling edge a and d2 for the falling edge b (see figure 4?11 ). the maximum dcd for a clock is the larger value of d1 and d2. figure 4?11. duty cycle distortion dcd expressed in absolution deriva tion, for example, d1 or d2 in figure 4?11 , is clock-period independent. dcd can also be expressed as a percentage, and the percentage number is clock-period dependent. dcd as a percentage is defined as: (t/2 ? d1) / t (the low percentage boundary) (t/2 + d2) / t (the high percentage boundary) dcd measurement techniques dcd is measured at an fpga output pin driven by registers inside the corresponding i/o element (ioe) block. when the ou tput is a single data rate signal (non-ddio), on ly one edge of the regist er input clock (positive or negative) triggers output transitions ( figure 4?12 ). therefore, any dcd present on the input clock signal or caused by the clock input buffer or different input i/o standard does not transfer to the output signal. clkh = t/2 clkl = t/2 d1 d2 fallin g ed g e a ideal fallin g ed g e clock period (t) fallin g ed g e b
figure 4?12. dcd measurement technique for non-ddio (single-data rate) outputs however, when the output is a doub le data rate input/output (ddio) signal, both edges of the input clock signal (posit ive and negative) trigger output transitions ( figure 4?13 ). therefore, any dist ortion on the input clock and the input clock buff er affect the output dcd. figure 4?13. dcd measurement technique for ddio (double-data rate) outputs when an fpga pll generates the inte rnal clock, the pll output clocks the ioe block. as the pll only monitors the positive edge of the reference clock input and internally re-creates the output cloc k signal, any dcd present on the reference clock is filt ered out. therefore, the dcd for a ddio output with pll in the clock path is better than the dcd for a ddio output without pll in the clock path.
tables 4?98 through 4?105 show the maximum dcd in absolution derivation for different i/o standard s on stratix ii gx devices. examples are also provided that show how to calculate dcd as a percentage. here is an example for calculatin g the dcd as a percentage for a non-ddio output on a row i/o on a -3 device: if the non-ddio output i/o standard is sstl-2 class ii, the maximum dcd is 95 ps (see table 4?99 ). if the clock frequency is 267 mhz, the clock period t is: t = 1/ f = 1 / 267 mhz = 3.745 ns = 3,745 ps to calculate the dcd as a percentage: (t/2 ? dcd) / t = (3,745 ps/2 ? 95 ps) / 3,745 ps = 47.5% (for low boundary) (t/2 + dcd) / t = (3,745 ps/2 + 95 ps) / 3,745 ps = 52.5% (for high boundary) table 4?98. maximum dcd for non- ddio output on row i/o pins row i/o output standard maximum dcd (ps) for non-ddio output -3 devices -4 and -5 devices unit 3.3-v lvtttl 245 275 ps 3.3-v lvcmos 125 155 ps 2.5 v 105 135 ps 1.8 v 180 180 ps 1.5-v lvcmos 165 195 ps sstl-2 class i 115 145 ps sstl-2 class ii 95 125 ps sstl-18 class i 55 85 ps 1.8-v hstl class i 80 100 ps 1.5-v hstl class i 85 115 ps lvds 55 80 ps
therefore, the dcd percentage for the output clock at 267 mhz is from 47.5% to 52.5%. table 4?99. maximum dcd for non-dd io output on column i/o pins column i/o output standard i/o standard maximum dcd (ps) for non-ddio output unit -3 devices -4 and -5 devices 3.3-v lvttl 190 220 ps 3.3-v lvcmos 140 175 ps 2.5 v 125 155 ps 1.8 v 80 110 ps 1.5-v lvcmos 185 215 ps sstl-2 class i 105 135 ps sstl-2 class ii 100 130 ps sstl-18 class i 90 115 ps sstl-18 class ii 70 100 ps 1.8-v hstl class i 80 110 ps 1.8-v hstl class ii 80 110 ps 1.5-v hstl class i 85 115 ps 1.5-v hstl class ii 50 80 ps 1.2-v hstl-12 170 200 ps lvpecl 55 80 ps
here is an example for calculating the dcd in percentage for a ddio output on a row i/o on a -3 device: if the input i/o standard is 2. 5-v sstl-2 and the ddio output i/o standard is sstl-2 class= ii, the maximum dcd is 60 ps (see table 4?100 ). if the clock frequency is 267 mhz, the clock period t is: t = 1/ f = 1 / 267 mhz = 3.745 ns = 3,745 ps calculate the dcd as a percentage: (t/2 ? dcd) / t = (3,745 ps/2 ? 60 ps) / 3745 ps = 48.4% (for low boundary) (t/2 + dcd) / t = (3,745 ps/2 + 60 ps) / 3745 ps = 51.6% (for high boundary) table 4?100. maximum dcd for ddio output on row i/o pins without pll in the clock path for -3 devices note (1) maximum dcd (ps) for row ddio output i/o standard input i/o standard (no pll in clock path) unit ttl/cmos sstl-2 sstl/hstl lvds 3.3 and 2.5 v 1.8 and 1.5 v 2.5 v 1.8 and 1.5 v 3.3 v 3.3-v lvttl 260 380 145 145 110 ps 3.3-v lvcmos 210 330 100 100 65 ps 2.5 v 195 315 85 85 75 ps 1.8 v 150 265 85 85 120 ps 1.5-v lvcmos 255 370 140 140 105 ps sstl-2 class i 175 295 65 65 70 ps sstl-2 class ii 170 290 60 60 75 ps sstl-18 class i 155 275 55 50 90 ps 1.8-v hstl class i 150 270 60 60 95 ps 1.5-v hstl class i 150 270 55 55 90 ps lvds 180 180 180 180 180 ps (1) the information in table 4?100 assumes the input clock has zero dcd.
therefore, the dcd percentage for the output clock is from 48.4% to 51.6%. table 4?101. maximum dcd for ddio output on row i/o pi ns without pll in the clock path for -4 and -5 devices note (1) maximum dcd (ps) for row ddio output i/o standard input i/o standard (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl lvds 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 3.3v 3.3-v lvttl 440 495 170 160 105 ps 3.3-v lvcmos 390 450 120 110 75 ps 2.5 v 375 430 105 95 90 ps 1.8 v 325 385 90 100 135 ps 1.5-v lvcmos 430 490 160 155 100 ps sstl-2 class i 355 410 85 75 85 ps sstl-2 class ii 350 405 80 70 90 ps sstl-18 class i 335 390 65 65 105 ps 1.8-v hstl class i 330 385 60 70 110 ps 1.5-v hstl class i 330 390 60 70 105 ps lvds 180 180 180 180 180 ps (1) table 4?101 assumes the input clock has zero dcd. table 4?102. maximum dcd for ddio output on column i/o pins without pll in the clock path for -3 devices (part 1 of 2) note (1) maximum dcd (ps) for ddio column output i/o standard input io standard (no pll in the clock path) unit ttl/cmos sstl-2 s stl/hstl hstl12 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 1.2v 3.3-v lvttl 260 380 145 145 145 ps 3.3-v lvcmos 210 330 100 100 100 ps 2.5 v 195 315 85 85 85 ps 1.8 v 150 265 85 85 85 ps 1.5-v lvcmos 255 370 140 140 140 ps sstl-2 class i 175 295 65 65 65 ps sstl-2 class ii 170 290 60 60 60 ps sstl-18 class i 155 275 55 50 50 ps
sstl-18 class ii 140 260 70 70 70 ps 1.8-v hstl class i 150 270 60 60 60 ps 1.8-v hstl class ii 150 270 60 60 60 ps 1.5-v hstl class i 150 270 55 55 55 ps 1.5-v hstl class ii 125 240 85 85 85 ps 1.2-v hstl 240 360 155 155 155 ps lvpecl 180 180 180 180 180 ps (1) table 4?102 assumes the input clock has zero dcd. table 4?103. maximum dcd for ddio output on column i/ o pins without pll in th e clock path for -4 and -5 devices note (1) maximum dcd (ps) for ddio column output i/o standard input io standard (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 3.3-v lvttl 440 495 170 160 ps 3.3-v lvcmos 390 450 120 110 ps 2.5 v 375 430 105 95 ps 1.8 v 325 385 90 100 ps 1.5-v lvcmos 430 490 160 155 ps sstl-2 class i 355 410 85 75 ps sstl-2 class ii 350 405 80 70 ps sstl-18 class i 335 390 65 65 ps sstl-18 class ii 320 375 70 80 ps 1.8-v hstl class i 330 385 60 70 ps 1.8-v hstl class ii 330 385 60 70 ps 1.5-v hstl class i 330 390 60 70 ps 1.5-v hstl class ii 330 360 90 100 ps lvpecl 180 180 180 180 ps (1) table 4?103 assumes the input clock has zero dcd. table 4?102. maximum dcd for ddio output on column i/o pins without pll in the clock path for -3 devices (part 2 of 2) note (1) maximum dcd (ps) for ddio column output i/o standard input io standard (no pll in the clock path) unit ttl/cmos sstl-2 s stl/hstl hstl12 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 1.2v
table 4?104. maximum dcd for ddio output on row i/o pins with pll in the clock path maximum dcd (ps) for row ddio output i/o standard stratix ii gx devices (pll output feeding ddio) unit -3 device -4 and -5 device 3.3-v lvttl 110 105 ps 3.3-v lvcmos 65 75 ps 2.5v 75 90 ps 1.8v 85 100 ps 1.5-v lvcmos 105 100 ps sstl-2 class i 65 75 ps sstl-2 class ii 60 70 ps sstl-18 class i 50 65 ps 1.8-v hstl class i 50 70 ps 1.5-v hstl class i 55 70 ps lvds 180 180 ps table 4?105. maximum dcd for ddio output on column i/o pins with pll in the clock path (part 1 of 2) maximum dcd (ps) for column ddio output i/o standard stratix ii gx devices (pll output feeding ddio) unit -3 device -4 and -5 device 3.3-v lvttl 145 160 ps 3.3-v lvcmos 100 110 ps 2.5v 85 95 ps 1.8v 85 100 ps 1.5-v lvcmos 140 155 ps sstl-2 class i 65 75 ps sstl-2 class ii 60 70 ps sstl-18 class i 50 65 ps sstl-18 class ii 70 80 ps 1.8-v hstl class i 60 70 ps 1.8-v hstl class ii 60 70 ps 1.5-v hstl class i 55 70 ps 1.5-v hstl class ii 85 100 ps
high-speed i/o specifications table 4?106 provides high-spe ed timing specific ations definitions. 1.2-v hstl 155 155 ps lvpecl 180 180 ps table 4?105. maximum dcd for ddio output on column i/o pins with pll in the clock path (part 2 of 2) maximum dcd (ps) for column ddio output i/o standard stratix ii gx devices (pll output feeding ddio) unit -3 device -4 and -5 device table 4?106. high-speed timing spec ifications and definitions high-speed timing spec ifications definitions t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. j deserialization factor (width of parallel data bus). w pll multiplication factor. t rise low-to-high transmission time. t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f in fast pll input clock frequency f hsdr maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. channel-to-channel skew (tccs) the timing difference between the fastest and the slowest output edges including t co variation and clock skew across channels driven by the same fast pll. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid in order to capture it correctly. the setup and hold ti mes determine the ideal strobe position within the sampling window. input jitter peak-to-peak inpu t jitter on high-speed plls. output jitter peak-to-peak out put jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls.
table 4?107 shows the high-speed i/o timing specifications for -3 speed grade stratix ii gx devices. table 4?107. high-speed i/o specifi cations for -3 speed grade notes (1) , (2) symbol conditions -3 speed grade unit min typ max f in = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 520 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 717 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps j = 2 (lvds, hypertransport technology) (4) 760 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps tccs all differential standards - 200 ps sw all differential standards 330 - ps output jitter 190 ps output t rise all differential i/o standards 160 ps output t fall all differential i/o standards 180 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance (5) data channel peak-to-peak jitter 0.44 ui dpa lock time number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate. (5) for setup details, refer to the characterization report.
table 4?108 shows the high-speed i/o timing specifications for -4 speed grade stratix ii gx devices. table 4?108. high-speed i/o specifi cations for -4 speed grade notes (1) , (2) symbol conditions -4 speed grade unit min typ max f in = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 520 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 717 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps j = 2 (lvds, hypertransport technology) (4) 760 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps tccs all differential standards - 200 ps sw all differential standards 330 - ps output jitter 190 ps output t rise all differential i/o standards 160 ps output t fall all differential i/o standards 180 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance data channel peak-to-peak jitter 0.44 ui dpa lock time number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate.
table 4?109 shows the high-speed i/o timing specifications for -5 speed grade stratix ii gx devices. table 4?109. high-speed i/o specifi cations for -5 speed grade notes (1) , (2) symbol conditions -5 speed grade unit min typ max f in = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 420 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 640 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 840 mbps j = 2 (lvds, hypertransport technology) (4) 700 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 840 mbps tccs all differential i/o standards - 200 ps sw all differential i/o standards 440 - ps output jitter 190 ps output t rise all differential i/o standards 290 ps output t fall all differential i/o standards 290 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance data channel peak-to-peak jitter 0.44 ui dpa lock time number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 840. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate.
pll timing specifications tables 4?110 and 4?111 describe the stratix ii gx pll specifications when operating in both the commercial junction temperature range (0 to 85 c) and the industrial junction temper ature range (?40 to 100 c), except for the clock switchover and phase-sh ift stepping features. these two features are only supported from the 0 to 100 c junction temperature range. table 4?110. enhanced pll speci fications (part 1 of 2) name description min typ max unit f in input clock frequency 4 500 mhz f inpfd input frequency to the pfd 4 420 mhz f induty input clock duty cycle 40 60 % f enduty external feedback input clock duty cycle 40 60 % t injitter input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth 0.85 mhz 0.5 ns (peak- to-peak) input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth > 0.85 mhz 1.0 ns (peak- to-peak) t outjitter dedicated clock output period jitter 250 ps for 100 mhz outclk 25 mui for < 100 mhz outclk ps or mui (p-p) t fcomp external feedback compensation time 10 ns f out output frequency for internal global or regional clock 1.5 (2) 550 mhz f outduty duty cycle for external clock output 45 50 55 % f scanclk scanclk frequency 100 mhz t configepll time required to reconfigure scan chains for eplls 174/f scanclk ns f out_ext pll external clock output frequency 1.5 (2) (1) mhz t lock time required for the pll to lock from the time it is enabled or the end of device configuration 0.03 1 ms t dlock time required for the pll to lock dynamically after automatic clock switchover between two identical clock frequencies 1ms f switchover frequency range where the clock switchover performs properly 1.5 1 500 mhz f clbw pll closed-loop bandwidth 0.13 1.2 16.9 mhz
f vco pll vco operating range for ?3 and ?4 speed grade devices 300 1,040 mhz pll vco operating range for ?5 speed grade devices 300 840 mhz f ss spread-spectrum modulation frequency 100 500 khz % spread percent down spread for a given clock frequency 0.4 0.5 0.6 % t pll_pserr accuracy of pll phase shift 30 ps t areset minimum pulse width on areset signal. 10 ns t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandone goes high. 500 ns t reconfigwait the time required for the wait after the reconfiguration is done and the areset is applied. 2us (1) this is limited by the i/o f max . see tables 4?91 through 4?95 for the maximum. (2) if the counter cascading feature of the pll is ut ilized, there is no minimum output clock frequency. table 4?111. fast pll specifications (part 1 of 2) name description min typ max unit f in input clock frequency (for -3 and -4 speed grade devices) 16 717 mhz input clock frequency (for -5 speed grade devices) 16 640 mhz f inpfd input frequency to the pfd 16 500 mhz f induty input clock duty cycle 40 60 % t injitter input clock jitter tolerance in terms of period jitter. bandwidth 2mhz 0.5 ns (p-p) input clock jitter tolerance in terms of period jitter. bandwidth > 0.2 mhz 1.0 ns (p-p) table 4?110. enhanced pll speci fications (part 2 of 2) name description min typ max unit
external memory interface specifications tables 4?112 through 4?116 contain stratix ii gx device specifications for the dedicated circuitry used for in terfacing with external memory devices. f vco upper vco frequency range for ?3 and ?4 speed grades 300 1,040 mhz upper vco frequency range for ?5 speed grades 300 840 mhz lower vco frequency range for ?3 and ?4 speed grades 150 520 mhz lower vco frequency range for ?5 speed grades 150 420 mhz f out pll output frequency to gclk or rclk 4.6875 550 mhz pll output frequency to lvds or dpa clock 150 1,040 mhz f out_ext pll clock output frequency to regular i/o 4.6875 (1) mhz t configpll time required to reconf igure scan chains for fast plls 75/f scanclk ns f clbw pll closed-loop bandwidth 1.16 5 28 mhz t lock time required for the pll to lock from the time it is enabled or the end of the device configuration 0.03 1 ms t pll_pserr accuracy of pll phase shift 30 ps t areset minimum pulse width on areset signal. 10 ns t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandone goes high. 500 ns (1) this is limited by the i/o f max . see tables 4?91 through 4?95 for the maximum. table 4?111. fast pll specifications (part 2 of 2) name description min typ max unit table 4?112. dll frequency range specifications (part 1 of 2) frequency mode frequency range (mhz) resolution (degrees) 0 100 to 175 30 1 150 to 230 22.5 2 200 to 350 (?3 speed grade) 30 200 to 310 (?4 and ?5 speed grade) 30
3 240 to 400 (?3 speed grade) 36 240 to 350 (?4 and ?5 speed grade) 36 table 4?113. dqs jitter specificati ons for dll-delayed clock (t dqs _ jitter ) note (1) number of dqs delay buffer stages (2) commercial (ps) industrial (ps) 1 80 110 2 110 130 3 130 180 4 160 210 (1) peak-to-peak period jitter on the phase-shifted dqs cl ock. for example, jitter on two delay stages under commercial condit ions is 200 ps peak-to-peak or 100 ps. (2) delay stages used for requested dqs phase shift are reported in a project?s compilation report in the quartus ii software. table 4?112. dll frequency range specifications (part 2 of 2) frequency mode frequency range (mhz) resolution (degrees) table 4?114. dqs phase-shift error spec ifications for dll-delayed clock (t dqs _ pserr ) number of dqs delay buffer stages (1) ?3 speed grade (ps) ?4 speed grade (ps) ?5 speed grade (ps) 1 253035 2 506070 37590105 4 100 120 140 (1) delay stages used for request dqs phase shift are repo rted in a project?s compilation report in the quartus ii software. for example, phase-shift erro r on two delay stages under -3 conditio ns is 50 ps peak-to-peak or 25 ps.
jtag timing specifications figure 4?14 shows the timing requirem ents for the jtag signals table 4?115. dqs bus clock sk ew adder specifications (t dqs _clock_skew_adder) mode dqs clock skew adder (ps) (1) 4 dq per dqs 40 9 dq per dqs 70 18 dq per dqs 75 36 dq per dqs 95 (1) this skew specification is the absolute maximum and minimum skew. for example, skew on a 40 dq group is 40 ps or 20 ps. table 4?116. dqs phase offset delay per stage (ps) notes (1) , (2) , (3) speed grade positive offset negative offset min max min max -3 10 15 8 11 -4 10 15 8 11 -5 10 16 8 12 (1) the delay settings are linear. (2) the valid settings for phase offset are -32 to +31. (3) the typical value equals the average of the minimum and maximum values.
figure 4?14. stratix ii g x jtag waveforms. table 4?117 shows the jtag timing parameters and values for stratix ii gx devices. tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms si g nal to be captured si g nal to be driven t jszx t jssu t jsh t jsco t jsxz table 4?117. stratix ii gx jtag timing parameters and values symbol parameter min max unit t jcp tck clock period 30 ns t jch tck clock high time 12 ns t jcl tck clock low time 12 ns t jpsu jtag port setup time 4 ns t jph jtag port hold time 5 ns t jpco jtag port clock to output 9 ns t jpzx jtag port high impedance to valid output 9 ns t jpxz jtag port valid output to high impedance 9 ns t jssu capture register setup time 4 ns t jsh capture register hold time 5 ns t jsco update register clock to output 12 ns t jszx update register high impedance to valid output 12 ns t jsxz update register valid output to high impedance 12 ns
referenced documents this chapter references the following documents: operating requirements for altera devices data sheet powerplay power analyzer chapter in volume 3 of the quartus ii handbook . powerplay early power estima tor (epe) and power analyzer quartus ii powerplay analysis and optimization technology stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook v olume 2, stratix ii gx device handbook
document revision history table 6?105 shows the revision hi story for this chapter. table 4?118. document revision history (part 1 of 5) date and document version changes made summary of changes june 2009 v4.6 replaced table 4?31 updated: table 4?5 table 4?6 table 4?7 table 4?8 table 4?9 table 4?10 table 4?11 table 4?12 table 4?13 table 4?14 table 4?15 table 4?16 table 4?17 table 4?18 table 4?20 table 4?50 table 4?95 table 4?105 table 4?110 table 4?111 october 2007 v4.5 updated: table 4?3 table 4?6 table 4?16 table 4?19 table 4?20 table 4?21 table 4?22 table 4?55 table 4?106 table 4?107 table 4?108 table 4?109 table 4?112 updated title only in tables 4?88 and 4?89. minor text edits.
august 2007 v4.4 removed note ?the data in this table is preliminary. altera will provide a report upon completion of characterization of the stratix ii gx devices. conditions for testing the silicon have not been determined.? from each table. removed note ?the data in tables xxx through xxx is preliminary. altera will provide a report upon completion of characterization of the stratix ii gx devices. conditions for test ing the silicon have not been determined.? in the clock timing parameters sections. updated clock timing parameter tables 4?63 through 4?78 (table 4?75 was unchanged). updated table 4?21 and added new table 4?22. updated: table 4?6 table 4?16 table 4?19 table 4?49 table 4?52 table 4?107 added note to table 4?50. added: figure 4?3 figure 4?4 figure 4?5 added the ?referenced documents? section. may 2007 v4.3 changed 1.875 khz to 1.875 mhz in table 4?19, xaui receiver jitter tolerance section. table 4?118. document revision history (part 2 of 5) date and document version changes made summary of changes
february 2007 v4.2 added the ?document revision history? section to this chapter. added support information for the stratix ii gx device. updated table 4?5: removed last three lines removed note 1 added new note 4 deleted table 6-6. replaced table 4?6 with all new information. added figures 4?1 and 4?2. added tables 4?7 through 4?19. removed figures 6-1 through 6-4. updated table 4?22: changed r conf information. updated table 4?52 sstl-18 class i, column 1: changed 25 to 50. updated: table 4?54 table 4?87 table 4?91 table 4?94 updated tables 4?62 through 4?77 updated tables 4?79 and 4?80 added ?units? column updated tables 4?83 through 4?86 changed column title to ?fast corner industrial/commercial?. updated table 4?109. added a new line to the bottom of the table. august 2006 v4.1 update table 6?75, table 6?84, and table 6?90. table 4?118. document revision history (part 3 of 5) date and document version changes made summary of changes
june 2006, v4.0 updated table 6?5. updated table 6?6. updated all values in table 6?7. added tables 6?8 and 6?9. added figures 6?1 through 6?4. updated table 6?18. updated tables 6?85 through 6?96. added table 6?80, stratix ii gx maximum output clock rate for dedicated clock pins. updated table 6?100. in ?i/o timing measurement methodology? section, updated table 6?42. in ?internal timing parameters? section, updated tables 6?43 through 6?48. in ?stratix ii gx clock timing parameters? section, updated tables 6?50 through 6?65. in ?ioe programmable delay? section, updated tables 6?67 and 6?68. in ?i/o delays? section, updated tables 6?71 through 6?74. in ?maximum input & output clock toggle rate? section, updated tables 6?75 through 6?83. in ?dcd measurement techniques? section, updated tables 6?85 through 6?92. in ?high-speed i/o spec ifications? section, updated tables 6?94 through 6?96. in ?external memory interface specifications? section, updated table 6?100. removed rows for v id , v od , v icm , and v ocm from table 6?5. updated values for rx, tx, and refclkb in table 6?6. removed table containing 1.2-v pcml i/o information. that information is in table 6?7. added values to table 6?100. table 4?118. document revision history (part 4 of 5) date and document version changes made summary of changes
april 2006, v3.0 updated table 6?3. updated table 6?5. updated table 6?7. added table 6?42. updated ?internal timing parameters? section (tables 6?43 through 6?48). updated ?stratix ii gx clock timing parameters? section (tables 6?49 through 6?65). updated ?ioe programmable delay? section (tables 6?67 and 6?68) updated ?i/o delays? section (tables 6?71 through 6?74. updated ?maximum input & output clock toggle rate? section. replaced tables 6-73 and 6-74 with tables 6?75 through 6?83. input and output clock rates for row, column, and dedicated clock pins are now in separate tables. february 2006, v2.1 updated tables 6?4 and 6?5. updated tables 6?49 through 6?65 (removed column designations for industrial/commercial and removed industrial numbers). december 2005, v2.0 updated timing numbers. october 2005 v1.1 updated table 6?7. updated table 6?38. updated 3.3-v pcml information and notes to tables 6?73 through 6?76. minor textual changes throughout the document. october 2005 v1.0 added chapter to the stratix ii gx device handbook . table 4?118. document revision history (part 5 of 5) date and document version changes made summary of changes

5. reference and ordering information software stratix ? ii gx devices are supported by the altera ? quartus ? ii design software, which provides a co mprehensive environment for system-on-a-programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, compilation and logic synthesis, full simulation and adva nced timing anal ysis, signaltap ? ii logic analyzer, and device configuration. f refer to the quartus ii development software handbook for more information on the quartus ii software features. the quartus ii software supports the windows xp/2000/nt, sun solaris 8/9, linux red hat v7.3, linux red hat enterprise 3, and hp-ux operating systems. it also supports seamless integration with industry-leading eda tools through the nativelink interface. device pin-outs stratix ii gx device pin-outs ( pin-out files for altera devices ) are available on the altera web site at www.altera.com . ordering information figure 5?1 describes the ordering codes for stratix ii gx devices. f for more information on a specific package, refer to the package information for stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . siigx51007-1.3
5?2 altera corporation stratix ii gx device handbook, volume 1 august 2007 referenced documents figure 5?1. stratix ii gx device packaging ordering information (1) product code notations for es silicon for all ep2sgx130 family members (standard and lead free) and ep2sgx90 (lead free) use the following codings to denote pin count: 35 for 1152-pin devices and 40 for 1508-pin devices referenced documents this chapter references the following documents: package information for stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook pin-out files for altera devices quartus ii development software handbook document revision history table 5?1 shows the revision history for this chapter. device type package type 780 1,152 1,508 es: n: nes: f: fineline bga ep2sgx: stratix ii gx 30 60 90 130 number of transceiver channels c: 4 d: 8 e: 12 f: 16 g: 20 c: 3, 4, or 5, with 3 bein g the fastest commercial temperature (t j = 0 ? c to 85 ? c) i: industrial temperature (t j = ? 40 ? c to 100 ? c) optional suffix family signature operating temperature speed grade pin count en g ineerin g sample lead free lead-free en g ineerin g sample 3 ep2sgx 130 c 40 f ges indicates specific device options or shipment method. (1) table 5?1. document revision history (part 1 of 2) date and document version changes made summary of changes august 2007 v1.3 added the ?referenced documents? section. minor text edits.
altera corporation 5?3 august 2007 stratix ii gx device handbook, volume 1 reference and ordering information february 2007 v1.2 added the ?document revision history? section. added support information for the stratix ii gx device. june 2006, v1.1 updated ?device pin-outs? section. updated figure 7?1. october 2005 v1.0 added chapter to the stratix ii gx device handbook . table 5?1. document revision history (part 2 of 2) date and document version changes made summary of changes
5?4 altera corporation stratix ii gx device handbook, volume 1 august 2007 document revision history
101 innovation drive san jose, ca 95134 www.altera.com stratix ii gx device handbook, volume 2 siigx5v2-4.3
copyright ? 2007 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time with out notice. altera assumes no responsibility or liabil- ity arising out of the application or use of any information, produc t, or service described herein except as expressly agreed to in writing by al tera corporation. altera customers are advised to obtain the latest ver- sion of device specifications before relying on an y published information and before placing orders for products or services . ii altera corporation preliminary
altera corporation iii contents section i. stratix ii gx transceiver user guide chapter 1. stratix ii gx transceiver block overview introduction ................................................................................................................... ......................... 1?1 building blocks ................................................................................................................ ...................... 1?1 transmitter channel overview ................................................................................................... ........ 1?2 clock multiplier unit .......................................................................................................... ............. 1?3 phase compensation fifo buffer ................................................................................................. . 1?3 byte serializer ................................................................................................................ ................... 1?3 8b/10b encoder ................................................................................................................. ............... 1?3 serializer ..................................................................................................................... ....................... 1?4 transmitter differential output buffers ....................................................................................... 1 ?4 receiver channel overview ..................................... ................................................................. .......... 1?4 receiver differential input buffers ............................ ................................................................ .... 1?5 receiver pll ................................................................................................................... .................. 1?5 clock recovery unit ............................................................................................................ ............ 1?5 deserializer ................................................................................................................... ..................... 1?5 word aligner ................................................................................................................... ................. 1?6 channel aligner (deskew) ....................................................................................................... ....... 1?6 rate matcher ................................................................................................................... .................. 1?6 8b/10b decoder ................................................................................................................. ............... 1?7 byte deserializer .............................................................................................................. ................. 1?7 byte ordering .................................................................................................................. .................. 1?7 receiver phase compensation fifo buffe r ................................................................................. 1?7 pipe interface ................................................................................................................. ................... 1?8 loopback ....................................................................................................................... .......................... 1?8 built-in self-test ............................................................................................................. ....................... 1?8 reset and power down ........................................................................................................... ............. 1?9 referenced document ............................................................................................................ ............... 1?9 document revision history ...................................................................................................... ........... 1?9 chapter 2. stratix ii gx transceiver architecture overview introduction ................................................................................................................... ......................... 2?1 stratix ii gx alt2gxb ports list ................................................................................................. ...... 2?2 transmitter modules ............................................................................................................ ................. 2?9 clock multiplier unit .......................................................................................................... ............. 2?9 transmitter phase compensation fifo buffer ................. ......................................................... 2?31 byte serializer ................................................................................................................ ................. 2?32 8b/10b encoder ................................................................................................................. ............. 2?33 serializer ..................................................................................................................... ..................... 2?46
iv altera corporation contents stratix ii gx device handbook, volume 2 transmitter buffer ............................................................................................................. ............. 2?48 receiver modules ............................................................................................................... ........... ...... 2?52 receiver buffer ................................................................................................................ ................ 2?53 receiver pll ................................................................................................................... ................ 2?61 clock recovery unit ............................................................................................................ .......... 2?63 deserializer ................................................................................................................... ................... 2?66 word aligner ................................................................................................................... ............... 2?71 channel aligner (deskew) ....................................................................................................... ..... 2?97 rate matcher ................................................................................................................... ................ 2?98 8b/10b decoder ................................................................................................................. ........... 2?103 byte deserializer .............................................................................................................. ............. 2?112 byte ordering .................................................................................................................. .............. 2?113 receiver phase compensation fifo bu ffer ............. ........... ........... ........... ......... ......... ............. 2?118 pld-transceiver interface clocking ............................................................................................. .. 2?119 multiple protocols and data rates in a transceiver block ........... ............ ........... ........... ............. 2?135 transceiver block-based controls ............................................................................................. 2? 136 native modes ................................................................................................................... ............ ...... 2?145 basic single-width mode ........................................................................................................ .... 2?146 basic double-width mode ........................................................................................................ .. 2?149 pci express (pipe) mode ........................................................................................................ .... 2?150 xaui mode ...................................................................................................................... ............. 2?167 gige mode ...................................................................................................................... .............. 2?177 sonet/sdh mode ................................................................................................................. .... 2?186 (oif) cei-phy interface mode .................................................................................................. 2 ?192 serial digital interface (sdi) mode ............................................................................................ 2?195 serial rapidio mode ............................................................................................................ ....... 2?197 cpri mode ...................................................................................................................... .............. 2?200 loopback modes ................................................................................................................. ........... .... 2?205 serial loopback ................................................................................................................ ............ 2?205 pci express pipe reverse parallel loop back ................ ........... ............ ........... ........... ............. 2?206 reverse serial loopback ........................................................................................................ ..... 2?207 reverse serial pre-cdr loopback ............................... .............................................................. 2?2 08 parallel loopback .............................................................................................................. ........... 2?209 built-in self-test modes ....................................................................................................... ............ 2?211 bist in single-width mode ...................................................................................................... .. 2?212 bist in double-width mode ...................................................................................................... 2?213 reset control and power down ............. ...................................................................................... ... 2?214 user reset and enable signals .................................................................................................. . 2?215 power down ..................................................................................................................... ............ 2?220 timequest timing analyzer ...................................................................................................... 2?221 unconstrained asynchro nous alt2gxb ports ... ............ ........... ........... ........... ......... ............. 2?228 calibration blocks ............................................................................................................. ........... ...... 2?229 pll and output buffer calibration block ........... ........... ........... ............ ........... ........... ............. 2?229 termination resistor calibrat ion block ...................... ........... ........... ........... ........... ............ ...... 2?230 referenced documents ............................................ ............................................................... .......... 2?231 document revision history ...................................................................................................... ....... 2?231
altera corporation v contents contents chapter 3. stratix ii gx dynamic reconfiguration introduction ................................................................................................................... ......................... 3?1 dynamic reconfiguration controller arch itecture .......................................................................... 3?2 dynamic reconfiguration setup in the megawizard plug-in manager .................................. 3?4 dynamic configuration controller (alt2gxb _reconfig), alt2gxb design examples ...... 3?13 channel and pma controls reconfiguratio n ............ ............ ........... ........... ........... ......... ......... ...... 3?20 example for using logical channel address to perform channel reconfiguration .......... 3?24 channel reconfiguration ........................................................................................................ ...... 3?30 core clocking .................................................................................................................. ............... 3?45 pld data path interface ........................................................................................................ ........ 3?52 alt2gxb_reconfig setup for channel reconfiguration . .................................................. 3?65 dynamic transmit rate switch ................................................................................................... .3?65 reset recommendations .......................................................................................................... ..... 3?66 overall design flow for channel reconfiguration .......... ......................................................... 3?69 channel reconfiguration design examples ................... ............................................................ 3?72 pseudo-write sequence for simulati ng channel reconfiguration ......................................... 3?86 channel and clock multiplier unit (cmu) pll reconfiguratio n ............ ........... ......... ......... ...... 3?87 introduction ................................................................................................................... ................. 3?87 synopsis of existing dynamic reconfiguration features ........................................................ 3?87 overview of quartus ii software version 7.1 features for dynamic reconfiguration ....... 3?88 clocking enhancements and requirements ............................................................................... 3?90 input reference clock requirements for reusing mifs .......................................................... 3?94 logical tx pll .................................................................................................................. ............. 3?98 using the channel and cmu pll reconfiguration featur e ................................................... 3?98 logical tx pll select ........................................................................................................... ....... 3?105 tx pll powerdown ................................................................................................................ ..... 3?109 channel and cmu pll reconfiguration duration ........... ........... ........... ......... ......... ............. 3?110 reset recommendations .......................................................................................................... ... 3?110 quartus ii settings and requirements .... ........... ........... ........... ........... ........... ............ ........... .... 3?111 merging transceiver channels with dynamic reco nfiguration enabled ..... ......... ............. 3?120 design examples ................................................................................................................ .......... 3?121 adaptive equalization (aeq) .................................................................................................... ...... 3?137 conventions used ............................................................................................................... ......... 3?137 aeq feature requirements ....................................................................................................... . 3?138 enabling the aeq hardware ..................................................................................................... 3 ?138 controlling the aeq hardware ................................................................................................. 3? 141 power down options ............................................................................................................. ..... 3?144 quartus ii software merging requirem ents .............. ........... ........... ........... ........... ............ ...... 3?147 summary ........................................................................................................................ ............ ......... 3?147 referenced documents ............................................ ............................................................... .......... 3?147 document revision history ...................................................................................................... ....... 3?148 chapter 4. stratix ii gx alt2 gxb megafunction user guide introduction ................................................................................................................... ......................... 4?1 basic mode ..................................................................................................................... ......................... 4?2 physical interface for pci-express (pip e) mode ............ ........... ........... ........... ........... ............ ........ 4?31
vi altera corporation contents stratix ii gx device handbook, volume 2 xaui mode ...................................................................................................................... ........ ............. 4?56 gige mode ...................................................................................................................... ........ ............. 4?76 sonet/sdh mode ................................................................................................................. ......... 4?102 (oif) cei phy interface mode ................................................................................................... ..... 4?129 cpri mode ...................................................................................................................... ......... ........... 4?153 sdi mode ....................................................................................................................... ............ ......... 4?184 serial rapidio mode ............................................................................................................ ............. 4?215 referenced documents ............................................ ............................................................... .......... 4?243 document revision history ...................................................................................................... ....... 4?244 chapter 5. stratix ii gx alt2gxb_re config megafunction user guide introduction ................................................................................................................... ......................... 5?1 dynamic reconfiguration ........................................................................................................ ............ 5?1 referenced document ............................................................................................................ ............. 5?15 document revision history ...................................................................................................... ......... 5?16 chapter 6. specifications & additional information transceiver blocks ............................................................................................................. .................... 6?1 8b/10b code .................................................................................................................... ...................... 6?3 code notation .................................................................................................................. ................. 6?3 disparity calculation .......................................................................................................... ............. 6?3 supported codes ................................................................................................................ .............. 6?4 document revision history ...................................................................................................... ......... 6?13 section ii. clock management chapter 7. plls in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 7?1 enhanced plls .................................................................................................................. ..................... 7?5 enhanced pll hardware overview ............................................................................................. 7?5 enhanced pll software overview ................................................................................................ 7 ?9 enhanced pll pins .............................................................................................................. .......... 7?12 fast plls ...................................................................................................................... .............. ........... 7?15 fast pll hardware overview ..................................................................................................... 7?15 fast pll software overview ..................................................................................................... ... 7?16 fast pll pins .................................................................................................................. ................. 7?18 clock feedback modes ........................................................................................................... ............ 7?20 source-synchronous mode ...................................... .................................................................. ... 7?20 no compensation mode ........................................................................................................... .... 7?21 normal mode .................................................................................................................... .............. 7?22 zero delay buffer mode ......................................................................................................... ....... 7?23 external feedback mode ......................................................................................................... ...... 7?24 hardware features .............................................................................................................. ................ 7?25 clock multiplication and division .............................................................................................. 7?26 phase-shift implementation ..................................................................................................... .... 7?27
altera corporation vii contents contents programmable duty cycle ........................................................................................................ ... 7?29 advanced clear and enable control ........................................................................................... 7?2 9 advanced features .............................................................................................................. ................ 7?32 counter cascading .............................................................................................................. ........... 7?32 clock switchover ............................................................................................................... ............. 7?33 reconfigurable bandwidth ................. ...................................................................................... ......... 7?44 pll reconfiguration ............................................................................................................ ......... ...... 7?51 spread-spectrum clocking ....................................................................................................... ......... 7?51 board layout ................................................................................................................... .......... ........... 7?56 v cca and gnda ...................................................................................................................... ...... 7?56 v ccd ............................................................................................................................ ....................................................................................... 7? 58 external clock output power .................................................................................................... .. 7?58 guidelines ..................................................................................................................... ................... 7?61 pll specifications ............................................................................................................. ........... ........ 7?62 clocking ....................................................................................................................... .............. ........... 7?62 global and hierarchical clocking ............................................................................................... .7?62 clock sources per region ....................................................................................................... ....... 7?64 clock input connections ........................................................................................................ ....... 7?69 clock source control for enhanced plls ...................... ............................................................ 7?73 clock source control fo r fast plls ............................................................................................. 7?73 delay compensation for fast plls ............................................................................................. 7? 75 clock output connections ....................................................................................................... ..... 7?76 clock control block ............................................................................................................ ........... ...... 7?86 clkena signals ................................................................................................................. ................. 7?90 conclusion ..................................................................................................................... ............ ........... 7?91 referenced documents ............................................ ............................................................... ............ 7?91 document revision history ...................................................................................................... ......... 7?91 section iii. memory chapter 8. trimatrix embedded memory blocks in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 8?1 trimatrix memory overview ..................................... ................................................................. ........ 8?1 parity bit support ............................................................................................................. ................ 8?3 byte enable support ............................................................................................................ ............ 8?4 pack mode support .............................................................................................................. ............ 8?7 address clock enable support ................................................................................................... ... 8?8 memory modes ................................................................................................................... ................... 8?9 single-port mode ............................................................................................................... ............. 8?10 simple dual-port mode .......................................................................................................... ....... 8?12 true dual-port mode ............................................................................................................ ......... 8?15 shift-register mode ............................................................................................................ ........... 8?18 rom mode ....................................................................................................................... ............... 8?20 fifo buffers mode .............................................................................................................. ........... 8?20 clock modes .................................................................................................................... ..................... 8?20
viii altera corporation contents stratix ii gx device handbook, volume 2 independent clock mode ......................................................................................................... ..... 8?21 input/output clock mode ........................................................................................................ ... 8?23 read/write clock mode .......................................................................................................... ..... 8?26 single-clock mode .............................................................................................................. ........... 8?28 designing with trimatrix memory ................................................................................................ .. 8?31 selecting trimatrix memory blocks ............................................................................................ 8? 31 synchronous and pseudo-asynchronous modes ...................................................................... 8?32 power-up conditions and memory init ialization ..................................................................... 8?32 read-during-write operation at the sa me address ......... ........... ............ ........... ........... ......... ...... 8?33 same-port read-during-write mode .......................................................................................... 8?33 mixed-port read-during-write mode ............................ ............................................................ 8?34 conclusion ..................................................................................................................... ............ ........... 8?35 referenced documents ............................................ ............................................................... ............ 8?36 document revision history ...................................................................................................... ......... 8?36 chapter 9. external memory interfaces in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 9?1 external memory standards ...................................................................................................... .......... 9?4 ddr and ddr2 sdram ............................................................................................................. .... 9?4 rldram ii ...................................................................................................................... ................. 9?8 qdrii sram ..................................................................................................................... .............. 9?10 stratix ii and stratix ii gx ddr memory support overvi ew ................. ........... ........... ......... ...... 9?13 ddr memory interface pins ...................................................................................................... ... 9?14 dqs phase-shift circuitry ...................................................................................................... ...... 9?21 dqs logic block ................................................................................................................ ............. 9?28 ddr registers .................................................................................................................. ............... 9?31 pll ............................................................................................................................ ....................... 9?38 enhancements in stratix ii an d stratix ii gx devices ..... ............ ........... ........... ............ ........... ...... 9?38 conclusion ..................................................................................................................... ............ ........... 9?38 referenced documents ............................................ ............................................................... ............ 9?39 document revision history ...................................................................................................... ......... 9?39 section iv. i/o standards chapter 10. selectable i/o standards in stratix ii and stratix ii gx devices introduction ................................................................................................................... ............ ........... 10?1 stratix ii and stratix ii gx i/o features ........................................................................................ .. 10?1 stratix ii and stratix ii gx i/o standard s support ........ ........... ........... ........... ........... ............ ........ 10?2 single-ended i/o standards ..................................................................................................... ... 10?3 differential i/o standards ..................................................................................................... ..... 10?10 stratix ii and stratix ii gx external memo ry interface ............. ........... ........... ........... ............ ...... 10?19 stratix ii and stratix ii gx i/o banks ............................................................................................ . 10?20 programmable i/o standards .................................................................................................... 1 0?22 on-chip termination ............................................................................................................ ............ 10?27 on-chip series termination without calibration ......... ........... ............ ........... ........... ............. 10?28
altera corporation ix contents contents on-chip series termination with calibr ation ............... ........... ............ ........... ........... ............. 10?30 on-chip parallel termination with ca libration ............ ........... ............ ........... ........... ............. 10?31 design considerations .......................................................................................................... ............ 10?33 i/o termination ................................................................................................................ ........... 10?33 i/o banks restrictions ......................................................................................................... ....... 10?34 i/o placement guidelines ....................................................................................................... ... 10?36 dc guidelines .................................................................................................................. ............. 10?39 conclusion ..................................................................................................................... ............ ......... 10?42 references ..................................................................................................................... ......... ............. 10?42 referenced documents ............................................ ............................................................... .......... 10?43 document revision history ...................................................................................................... ....... 10?44 chapter 11. high-speed differe ntial i/o interfaces with dpa in stratix ii & stratix ii gx devices introduction ................................................................................................................... ............ ........... 11?1 i/o banks ...................................................................................................................... ......... ......... ...... 11?1 differential transmitter ...................................... ................................................................. ......... ...... 11?6 differential receiver .......................................................................................................... .................. 11?8 receiver data realignment circuit ............................................................................................. 1 1?9 dynamic phase aligner .......................................................................................................... ..... 11?10 synchronizer ................................................................................................................... .............. 11?12 differential i/o termination ................................................................................................... ........ 11?12 fast pll ...................................................................................................................... ........... ............. 11?13 clocking ....................................................................................................................... .............. ......... 11?14 source synchronous timing bu dget ........... ........... ............ ........... ........... ........... ......... ............. 11?16 differential data orientation ........... ....................................................................................... .... 11?17 differential i/o bit position .................................................................................................. ..... 11?17 receiver skew margin for non-dpa ...... ........... ........... ........... ........... ........... ............ ........... .... 11?19 differential pin placement guidelines .......................................................................................... . 11?21 high-speed differential i/os and sing le-ended i/os .... ........... ........... ........... ......... ............. 11?21 dpa usage guidelines ........................................................................................................... ..... 11?22 non-dpa differential i/o usage guidelin es ................... ........... ........... ........... ......... ............. 11?26 board design considerations .................................................................................................... ...... 11?27 conclusion ..................................................................................................................... ............ ......... 11?28 referenced documents ............................................ ............................................................... .......... 11?29 document revision history ...................................................................................................... ....... 11?29 section v. digital sign al processing (dsp) chapter 12. dsp blocks in stratix ii & stratix ii gx devices introduction ................................................................................................................... ............ ........... 12?1 dsp block overview ............................................................................................................. .............. 12?1 architecture ................................................................................................................... ............ ........... 12?8 multiplier block ............................................................................................................... ............... 12?8 adder/output block ............................................................................................................. ...... 12?16
x altera corporation contents stratix ii gx device handbook, volume 2 operational modes .............................................................................................................. .............. 12?21 simple multiplier mode ......................................................................................................... ..... 12?22 multiply accumulate mode ....................................................................................................... 12?25 multiply add mode .............................................................................................................. ....... 12?26 software support ............................................................................................................... ................ 12?32 conclusion ..................................................................................................................... ............ ......... 12?32 referenced documents ............................................ ............................................................... .......... 12?33 document revision history ...................................................................................................... ....... 12?33 section vi. configuration& remote system upgrades chapter 13. configuring stratix ii & stratix ii gx devices introduction ................................................................................................................... ............ ........... 13?1 configuration devices .......................................... ................................................................ ......... 13?1 configuration features ......................................... ................................................................ .............. 13?4 configuration data decompression ........ .................................................................................... 13? 5 design security using configuration bitstream encryp tion ................................................... 13?8 remote system upgrade .......................................................................................................... ..... 13?9 power-on reset circuit ......................................................................................................... ........ 13?9 v ccpd pins .......................................................................................................................... ........... 13?10 vccsel pin ..................................................................................................................... ............. 13?10 output configuration pins ...................................................................................................... ... 13?13 fast passive parallel configuration ... ......................................................................................... .... 13?14 fpp configuration using a max ii device as an exte rnal host ......... ........... ......... ............. 13?15 fpp configuration using a microprocess or .......... ............ ........... ........... ........... ......... ............. 13?26 fpp configuration using an enhanced configuration device ............ ........... ......... ............. 13?26 active serial configuration (serial configuration devices) .... ........... ........... ........... ............ ...... 13?34 estimating active serial configuratio n time .............. ........... ........... ........... ............ ........... .... 13?43 programming serial conf iguration devices ............ ........... ........... ........... ......... ......... ............. 13?43 passive serial configuration ................................... ................................................................ ......... 13?46 ps configuration using a max ii device as an extern al host .......... ........... ........... ............. 13?47 ps configuration using a microprocesso r ............ ............ ........... ........... ........... ......... ............. 13?54 ps configuration using a configuratio n device ......... ........... ........... ........... ............ ........... .... 13?55 ps configuration using a download ca ble ............. ........... ........... ........... ......... ......... ............. 13?67 passive parallel asynchronous configuration ......... ........... ........... ............ ........... ........... ............. 13?73 jtag configuration ............................................................................................................. ............. 13?84 jam stapl ...................................................................................................................... .............. 13?91 device configuration pins ...................................................................................................... ......... 13?92 conclusion ..................................................................................................................... ............ ....... 13?106 referenced documents ............................................ ............................................................... ........ 13?106 document revision history ...................................................................................................... ..... 13?107 chapter 14. remote system upgrades with stratix ii & stratix ii gx devices introduction ................................................................................................................... ............ ........... 14?1 functional description ......................................................................................................... ......... ...... 14?2
altera corporation xi contents contents configuration image types and pages ....................................................................................... 14?5 remote system upgrade modes .................................................................................................... ... 14?8 overview ....................................................................................................................... .................. 14?8 remote update mode ............................................................................................................. ....... 14?9 local update mode .............................................................................................................. ........ 14?12 dedicated remote system upgr ade circuitry ......... ........... ........... ............ ........... ........... ............. 14?14 remote system upgrade registers ............................................................................................ 14?1 5 remote system upgrade state machine ... ........... ........... ........... ............ ........... ........... ............. 14?19 user watchdog timer ............................................................................................................ ...... 14?20 interface signals between remote system up grade circuitry and fp ga logic array .... 14?21 remote system upgrade pin descriptions ............... ........... ........... ........... ......... ......... ............. 14?23 quartus ii software support ..................................................................................................... ....... 14?24 altremote_update megafunction ................................................................................................ 14 ?24 remote system upgrade atom .................................................................................................. 14? 28 system design guidelines ....................................................................................................... ......... 14?28 remote system upgrade with serial configuration de vices .............. ........... ......... ............. 14?29 remote system upgrade with a max ii device or microprocessor and flash device .... 14?29 remote system upgrade with enhanced configuratio n devices ......... ......... ......... ............. 14?30 conclusion ..................................................................................................................... ............ ......... 14?31 referenced documents ............................................ ............................................................... .......... 14?31 document revision history ...................................................................................................... ....... 14?32 chapter 15. ieee 1149.1 (jtag) boundary -scan testing for stratix ii & stratix ii gx devices introduction ................................................................................................................... ............ ........... 15?1 ieee std. 1149.1 bst architectu re ........... ........... ............ ........... ........... ........... ......... ......... ......... ...... 15?2 ieee std. 1149.1 boundary-scan register ........ ........... ............ ........... ........... ......... ......... ......... ........ 15?4 boundary-scan cells of a stratix ii or stratix ii gx de vice i/o pin ...................................... 15?5 ieee std. 1149.1 bst operation control .... ........... ........... ........... ........... ........... ........... ............ ....... . 15?7 sample/preload instruction mode ....... ............ ........... ........... ........... ......... ......... ............. 15?11 capture phase .................................................................................................................. ............. 15?12 shift and update phases ........................................................................................................ ...... 15?12 extest instruction mode ........................................................................................................ .. 15?13 capture phase .................................................................................................................. ............. 15?14 shift and update phases ........................................................................................................ ...... 15?14 bypass instruction mode ........................................................................................................ .. 15?15 idcode instruction mode ........................................................................................................ . 15?16 usercode instruction mode ................................................................................................... 15? 16 clamp instruction mode ......................................................................................................... . 15?17 highz instruction mode ......................................................................................................... .. 15?17 i/o voltage support in jtag chain .............................................................................................. 15?17 using ieee std. 1149.1 bst circuitry ........................................................................................... .. 15?19 bst for configured devices ..................................................................................................... ........ 15?19 disabling ieee std. 1149.1 bst circuitry ........... ............ ........... ........... ........... ........... ........... ......... 15?20 guidelines for ieee std. 1149.1 boundary -scan testing ...... ........... ........... ........... ......... ............. 15?20 boundary-scan description language (b sdl) support ............. ........... ........... ............ ........... .... 15?21 conclusion ..................................................................................................................... ............ ......... 15?21
xii altera corporation contents stratix ii gx device handbook, volume 2 references ..................................................................................................................... ......... ............. 15?22 referenced documents ............................................ ............................................................... .......... 15?22 document revision history ...................................................................................................... ....... 15?22 section vii. pcb layout guidelines chapter 16. package information for stratix ii & stratix ii gx devices introduction ................................................................................................................... ............ ........... 16?1 thermal resistance ............................................................................................................. ........... ...... 16?2 package outlines ............................................................................................................... .................. 16?5 484-pin fbga - flip chip ....................................................................................................... ....... 16?5 672-pin fbga - flip chip ....................................................................................................... ....... 16?6 780-pin fbga - flip chip ....................................................................................................... ....... 16?9 1,020-pin fbga - flip chip .... ................. ........... ........... ........... ........... ......... ......... ......... ......... .... 16?11 1,152-pin fbga - flip chip .... ................. ........... ........... ........... ........... ......... ......... ......... ......... .... 16?13 1,508-pin fbga - flip chip .... ................. ........... ........... ........... ........... ......... ......... ......... ......... .... 16?15 document revision history ...................................................................................................... ....... 16?17
altera corporation xiii chapter revision dates the chapters in this book, stratix ii gx device handbook, volume 2 , were revised on the following dates. where chapters or groups of chapters ar e available separately, part numbers are listed. chapter 1. stratix ii gx tr ansceiver block overview revised: october 2007 part number: siigx52001-2.4 chapter 2. stratix ii gx transc eiver architecture overview revised: october 2007 part number: siigx52002-4.2 chapter 3. stratix ii gx dynamic reconfiguration revised: october 2007 part number: siigx52007-1.1 chapter 4. stratix ii gx alt2gxb megafunction user guide revised: october 2007 part number: siigx52003-4.2 chapter 5. stratix ii gx alt2gxb_re config megafunction user guide revised: october 2007 part number: siigx52006-1.4 chapter 6. specifications & additional information revised: october 2007 part number: siigx52004-3.1 chapter 7. plls in stratix ii and stratix ii gx devices revised: october 2007 part number: sii52001-4.5 chapter 8. trimatrix embedded memory blocks in stratix ii and stratix ii gx devices revised: october 2007 part number: sii52002-4.5 chapter 9. external memory interfaces in stratix ii and stratix ii gx devices revised: october 2007 part number: sii52003-4.5
xiv altera corporation chapter revision dates stratix ii gx device handbook, volume 2 chapter 10. selectable i/o standards in stratix ii and stratix ii gx devices revised: october 2007 part number: sii52004-4.6 chapter 11. high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices revised: october 2007 part number: sii52005-2.3 chapter 12. dsp blocks in stratix ii & stratix ii gx devices revised: october 2007 part number: sii52006-2.2 chapter 13. configuring stratix ii & stratix ii gx devices revised: october 2007 part number: sii52007-4.5 chapter 14. remote system upgrades with stratix ii & stratix ii gx devices revised: october 2007 part number: sii52008-4.5 chapter 15. ieee 1149.1 (jtag) boundary-scan te sting for stratix ii & stratix ii gx devices revised: october 2007 part number: sii52009-3.3 chapter 16. package information for st ratix ii & stratix ii gx devices revised: may 2007 part number: sii52010-4.3
altera corporation xv preliminary about this handbook this handbook provides comprehe nsive information about the altera ? stratix ? ii gx family of devices. how to contact altera for the most up-to-date information about altera products, refer to the following table. typographic conventions this document uses the typogr aphic conventions shown below. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature altera literature services email literature@altera.com non-technical support (general) (software licensing) email nacomp@altera.com email authorization@altera.com note to table: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board design.
xvi altera corporation preliminary typographic conventions stratix ii gx device handbook, volume 2 italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: , .pof file. initial capital letters keyboard keys and menu names ar e shown with initial capital letters. examples: delete key, the options menu. ?subheading title? references to sections within a document and titles of on-line help topics are shown in quotation marks. example: ?typographic conventions.? courier type signal and port names are shown in lowercase courier type. examples: data1 , tdi , input. active-low signals are denoted by suffix n , e.g., resetn . anything that must be typed exactly as it appears is shown in courier type. for example: c:\qdesigns\tutorial\chiptrip.gdf . also, sections of an actual file, such as a report file, refere nces to parts of files (e.g., the ahdl keyword subdesign ), as well as logic function names (e.g., tri ) are shown in courier. 1., 2., 3., and a., b., c., etc. numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ? bullets are used in a list of items when the sequence of the items is not important. v the checkmark indicates a procedur e that consists of one step only. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or the user?s work. w the warning calls attention to a conditi on or possible situation that could cause injury to the user. r the angled arrow indicates you should press the enter key. f the feet direct you to more information on a particular topic. visual cue meaning
altera corporation section i?1 preliminary section i. stratix ii gx transceiver user guide this section provides information on the configuration modes for stratix ? ii gx devices. it also includes information on testing, stratix ii gx port and parameter in formation, and pin constraint information. this section includes the following chapters: chapter 1, stratix ii gx transceiver block overview chapter 2, stratix ii gx transceiver architecture overview chapter 3, stratix ii gx dynamic reconfiguration chapter 4, stratix ii gx alt2gxb megafunction user guide chapter 5, stratix ii gx alt2gxb_ reconfig megafunction user guide chapter 6, specifications & additional information revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section i?2 altera corporation preliminary stratix ii gx transceiver user guide stratix ii gx device handbook, volume 2
altera corporation 1?1 october 2007 1. stratix ii gx transceiver block overview introduction stratix ? ii gx devices combine highly advanced 6.375-gigabits per second (gbps) four-channel gigabit tran sceiver blocks with the industry?s most advanced fpga architecture. the stratix ii gx transceiver builds on the success of the stratix gx fam ily by offering higher data rate support and additional features that enable you to support a wide variety of standard and custom protocols. each self-contained stratix ii gx gigabit transceiver block has a va riety of embedded functions to implement commonly required tasks. building blocks stratix ii gx transceivers are structur ed into duplex four-channel groups called transceiver blocks. you can configure each channel within a transceiver block in either sing le-width or double-width mode. single-width mode has an 8-bit/10-bi t serializer/deserializer (serdes) data path through the transceiver and supports data rates from 600 mbps to 3.125 gbps. double-width mode ha s a 16-bit/20-bit serdes data path through the transceiver and supports data rates from 1 gbps to 6.375 gbps. all blocks in the transc eiver can operate in double-width mode, except deskew first-in first-ou t (fifo), which is available only in single-width mode. the options for bl ocks available in the transceiver may differ depending on which mode (single or double) you use. 1 this documentation uses the terminology inter-transceiver block routing instead of inter-quad (iq) routing, as seen in the quartus ii software. in addition to custom (basic) modes, stratix ii gx transceivers support the following protocols: physical interface for pci express (pip e) ? single lane (1), four lane (4), and eight lane (8) xaui (10 gigabit attachment unit interface) gige (gigabit ethernet) sonet/sdh (synchronous optical network) ? oc-12, oc-48, and oc-96 (oif) cei phy interface (common electrical i/o) serial rapidio (1.25 gbps, 2.5 gbps, and 3.125 gbps) cpri (common public radio interface) sdi (serial digital interface) (hd-sdi and 3g-sdi) siigx52001-2.4
1?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter channel overview figure 1?1 shows a block diagram of the gigabit transceiver block in single-width mode. you enable or disable various optional modules based on the functional mode you select. the sections that follow figure 1?1 give a brief description of each block. f for detailed information about each block, refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook . figure 1?1. stratix ii gx gigabi t transceiver block diagram transmitter channel overview this section provides a brief descri ption about the various components within the transmitter block ( figure 1?2 ). the modules are listed in order from the parallel logic array to the transmit buff er of the transmitter. figure 1?2. stratix ii gx tr ansmitter block diagram receiver analog circuits receiver digital logic de- serializer clock recovery unit receiver pll deskew fifo word aligner rate match fifo 8b/10b decoder byte de- serializer byte serializer byte ordering rx phase compen- fifo transmitter analog circuits transmitter digital logic serializer cmu pld logic array sation phase compen- fifo sation tx 8 b/10b encoder refernce clocks reset logic state machines reference clocks pipe interface pipe interface byte serializer transmitter analog circuits transmitter digital logic serializer reference clocks cmu phase compen- fifo sation tx 8b/10b encoder
altera corporation 1?3 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver block overview clock multiplier unit each gigabit transceiver block ha s a clock multiplier unit (cmu) to provide clocking flexibility and su pport a range of incoming data streams. each cmu contains two transmitter phase-locked loops (plls) that generate the required clock freq uencies based upon the synthesis of an input reference clock. each tran smitter pll supports multiplication factors to allow the use of variou s input clock frequencies. both transmitter plls are identical and su pport data ranges from 600 mbps to 6.375 gbps. however, each pll can be configured to support different data rates. each transmitter pll driv es up to four channels. in pipe x8 mode, the transmitter pll of the ma ster transceiver block drives all eight channels. this cmu block is active in both single- and double-width modes and is powered down when not in use. phase compensation fifo buffer the transmitter data path has a dedicated phase compensation fifo buffer that decouples phase variatio ns between the fpga and transceiver clock domains. this block is active in both single- and double-width modes and cannot be bypassed. byte serializer the byte serializer allows the programmable logic device (pld) to run at half the rate of the transmit data path to allow the core to run at a lower frequency. without the byte serializer, at the maximum data rate of 6.375 gbps with a 20-bit serialization factor, the pld-transceiver interface needs to run at 318.75 mhz. the pld-tr ansceiver interface can run at a maximum frequency of 250 mhz. with the byte serializer, the pld-transceiver interface needs to ru n at 159.375 mhz. this block is available in both single- and double-w idth modes. in single-width mode, the pld interface is either 16 or 20 bits when the by te serializer used. in double-width mode, using the byte serializer creates a pld interface of 32 bits or 40 bits, depending on the serialization factor. 8b/10b encoder many protocols use 8b/10b encoding. stratix ii gx devices have two dedicated 8b/10b encoders in each transmitter channel. this encoding technique ensures sufficient data transitions and a dc-balanced stream within the data signal for successful data recovery at the receiver. this block is available in single- and double-width modes. in single-width mode, one of the 8b/10b encoders is active. in double-width mode, both 8b/10b encoders are active and oper ate in a cascade mode. the 8b/10b encoder follows the ieee 802.3 1998 edition standard for 8b/10b encoding.
1?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver channel overview serializer the serializer converts the incoming lower speed parallel signal from the transceiver?s physical coding sublayer (pcs) to a high-sp eed serial signal on the transmit side. the serializer supports a variety of conversion factors, ensuring implem entation flexibi lity. the serializer supports an 8- or 10-bit serialization factor in si ngle-width mode and a 16- or 20-bit serialization factor in double-width mode. the serializer block also performs clock synthesis on the sl ow-speed clock for the parallel transmitter logic in th e transceiver and pld. transmitter differential output buffers the gigabit transceiver block differenti al output buffers support the 1.5-v pcml and 1.2-v pcml i/o standards and have a variety of features that improve system signal integrity. programmable pre-emphasis helps compensate for high frequency losses. a variety of programmable voltage output differential (v od ) settings allow noise margin tuning capabilities. additionally, on-chip termination (oct) provides the appropriate transmitter buffer termination for 100-, 120-, or 150- transmission lines. the transmitter buffer circuit also contains a receiver-detect circuit for use with the pci express (pipe) protocol to detect if a receiver is connected. the buffer can be tri-stated to reduce electromagnetic interference (emi) and power consumption when not in use. in pipe mode, the tri-state feature generates electrical idle. receiver channel overview this section provides a brief descri ption about the various components within the receiver block. the module s originate from the serial receiver buffer to the parallel fpga interface ( figure 1?3 ). figure 1?3. stratix ii gx receiver block diagram receiver analog circuits receiver digital logic de- serializer clock recovery unit receiver pll deskew fifo word aligner rate match fifo 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo reference clock
altera corporation 1?5 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver block overview receiver differen tial input buffers stratix ii gx transceiver block differ ential input buffers support 1.5-v pcml and 1.2-v pcml i/o standards and have a variety of features that improve system signal integrity. programmable equalization capabilities compensate for signal degradatio n across transmission mediums. additionally, on-chip termination pr ovides the appropriate receiver termination for 100-, 120-, or 150- transmission lines. a signal detection block indicates if there is a valid signal at the receiver input. 1 stratix ii gx receiver input bu ffers also support the adaptive equalization (aeq) capability to compensate for changing link characteristics. receiver pll the receiver pll ramps the voltage controlled oscillator (vco) to the frequency of the reference clock. once that occurs, the clock recovery unit (cru) controls the vco. each receiv er channel in the transceiver has a dedicated receiver pll that provides clocking flexibility and supports a range of data rates. these plls generate the required clock frequencies based upon the synthesis of an input reference clock. clock recovery unit the stratix ii gx transceiver block cru performs analog clock data recovery (cdr). the cru recovers the embedded clock in the data stream to properly clock the incomi ng data. the recovered clock also clocks the reset of the receiver logic clock ( rx_digitalreset ) and is available in the pld fabric. deserializer the deserializer block converts th e incoming data stream from a high-speed serial signal to a lower-speed parallel signal that can be processed in the fpga logic array on the receive side. the deserializer supports a variety of conversion fa ctors, ensuring implementation flexibility. the deserializer supports an 8- or 10-bit deserialization factor in the single-width mode and a 16- or 20-bit deserialization factor in double-width mode. the deserializer block also performs clock synthesis on the slow-speed clock from the cr u and forwards the recovered clock to the parallel receiver logic in the transceiver and for the pld.
1?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver channel overview word aligner the word aligner module contains a fully programmable pattern detector to identify specific patt erns within the incoming data stream. the pattern detector includes recognition support for control code groups for 8b/10b encoded data and a1a2 or a1a1a2a2-type frame alignment patterns for scrambled data. custom alignment patte rns are also available. the word aligner can be bypassed in some functional modes. in single-width mode, the following word-alignment options are available: manual bit-slip mode manual alignment to 7-, 10-, or 16-bit patterns synchronization state machine that offers programmable hysteresis for synchronization. in double-width mode, the following word-alignment options are available: manual bit-slip mode manual alignment to 7-, 8-, 10-, 16-, 20-, or 32-bit patterns channel aligner (deskew) an embedded channel aligner aligns byte boundaries across multiple channels and synchronizes the data entering the logic array from the gigabit transceiver block?s four channels. the stratix ii gx channel aligner is optimized for a 10-gig abit ethernet xaui four-channel implementation. the channel aligner includes the control circuitry and channel alignment character dete ction defined by the 10-gigbit attachment unit interface (xaui) protocol. 1 this block is only available for the xaui protocol and is disabled for all other protocols. rate matcher in cdr-based systems, the clock fr equencies of the transmitting and receiving devices often do not match. this mismatch can cause the data to transmit at a rate slightly faster or slower than the receiving device can interpret. the stratix ii gx rate matcher resolves the frequency differences between the recovered clock and the fpga logic array clock by inserting or deleting removable ch aracters from the data stream, as defined by the transmission protocol , without compromising transmitted
altera corporation 1?7 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver block overview data. the rate matcher block is avai lable for single- and double-width basic modes and for specific protocols?xaui, gigabit ethernet (gige), and pci express (pipe). 8b/10b decoder various protocols use 8b/10b decodi ng. stratix ii gx devices have two dedicated 8b/10b decoders in each channel to support high data rates. this decoding technique ensures fast disparity and code group error detection. this block is available in single- and double-width modes. in single-width mode, only one of the 8b/10b decoders is active. in double-width mode, both 8b/10b decoders are active and operate in a cascade mode. the current running disparity can be sent to the pld for each decoded code group. the 8b/ 10b decoder follows the ieee 802.3 1998 edition standard for 8b/10b decoding. byte deserializer the byte deserializer widens the tr ansceiver data path before the pld interface to reduce the rate at which th e received data must be clocked in the pld logic. this byte deserializer block is available in both single- and double-width modes. in single-width mode, the pld interface is either 16 or 20 bits when used. in double-width mode, using the byte deserializer creates a pld interface of 32 or 40 bi ts, depending on your serialization factor. byte ordering each receiver has an optional byte orde ring block that is available in some functional modes when the byte deseri alizer is used. this block restores the expected word ordering if the byte deserialization of the data word does not match the expected word or dering after the by te deserializer block. this block is not av ailable when the rate matcher is used (single- or double-width mode) because the rate matcher may alter the byte order by adding or deleting bytes. it is also not available when 8b/10b is used in single-width mode. receiver phase compensation fifo buffer each receiver data path has a dedica ted phase compensation fifo buffer that decouples phase variations betw een the fpga and transceiver clock domains. this block is always used and cannot be bypassed.
1?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 loopback pipe interface the pipe interface suppor ts the pci express protocol. the pipe interface simplifies and standardizes the ba ck-end interface to the pci express physical layer. this block is automatically enabled in pipe mode and is not available in any other mode. loopback there are four available loopback modes for diagnostic purposes. the following loopback modes are available: serial loopback reverse serial loopback pre-cdr loopback built-in self test (bist) incremental test parallel loopback pci express (pipe) reverse parallel loopback figure 1?4 shows the available loopback modes. figure 1?4. loopback modes built-in self-test the gigabit transceiver block contains several features that simplify design verification. embedded pattern generators and pattern verifiers provide a simple approach to board verification with out the need to design additional logic in the pld fabric. the bist pseudo-random binary sequence (prbs) and incremen tal pattern generators, along with their respective pattern verifiers, provide a full self-test path. transmitter digital logic receiver digital logic analog receiver and transmitter logic tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator serial loopback parallel loopback reverse serial loopback pci express pipe reverse parallel loopback bist incremental generator
altera corporation 1?9 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver block overview reset and power down stratix ii gx transceivers offer multipl e reset signals to control separate ports of the transceiver channels an d blocks. each unused channel is automatically powered down to reduce power consumption. additionally, there are dynamic power-down signals for each receiver and transmitter block. referenced document this chapter references the following document: stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. document revision history table 1?1 shows the revision history for this chapter. table 1?1. document revision history (part 1 of 2) date and document version changes made summary of changes october 2007, v2.4 added note to ?receiver differential input buffers? section. ? updated bulleted list in ?building blocks? and ?loopback? sections. ? updated: ?clock multiplier unit? ?byte serializer? ? added ?referenced document? section. ? minor text edits. ? august 2007 v2.3 minor text edits. ? february 2007 v2.2 changed 622 mbps to 600 mbps in: ?building blocks? ?clock multiplier unit? ? changed 3.125 gbps to 1 gbps in ?building blocks?. ? modified the following: ?clock multiplier unit? ?byte serializer? ?8b/10b encoder? ?loopback? ? updated figure 1?3. ?
1?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history april 2006, v2.1 minor change to figures 1?1 and 1?3. ? february 2006, v2.0 updated ?building blocks? section. updated ?word aligner? section. updated ?byte ordering? section. updated ?loopback? section. updated ?built-in self-test? section. ? october 2005 v1.0 added chapter to the stratix ii gx device handbook . ? table 1?1. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation 2?1 october 2007 2. stratix ii gx transceiver architecture overview introduction this chapter provides detailed info rmation about the architecture of stratix ? ii gx devices. figure 2?1 shows the stratix ii gx block diagram. figure 2?1. stratix ii gx tr ansceiver block diagram receiver pll sipo channel aligner clock recovery unit refclk word aligner byte de- rate matcher 8b/10b decoder serializer byte ordering phase comp- ensation fifo pipe interface receiver transmitter pipe interface byte serializer 8b/10b encoder phase fifo compensation piso transmitter clock divider high-speed clock central block reset logic xaui, pcie, and gige state machines input output rx_datain rx_enapatternalign rx_a1a2size rx_bitslip pll_inclk pipe8b10binvpolarity rx_digitalreset rx_analogreset rx_locktodata rx_seriallpbken rx_locktorefclk gxb_powerdown rx_cruclk tx_datain gxb_enable reconfig_togxb tx_ctrlenable tx_detectrxloopback tx_forceelecidle tx_forcedispcompliance powerdn cal_blk_powerdown cal_blk_clk tx_digitalreset fixedclk rx_dataout pipephydonestatus rx_patterndetect rx_syncstatus rx_ctrldetect pipestatus pipeelecidle rx_errdetect rx_signaldetect rxvalid rx_a1a2sizeout coreclkout rx_bistdone pll_locked tx_clkout rx_disperr rx_bisterr tx_dataout rx_channelaligned reconfig_fromgxb central control unit rx_byteorderalignstatus alt2gxb rx_enabytord rx_invpolarity rx_revbitorderwa rx_revbyteorderwa tx_forcedisp tx_dispval tx_invpolarity debug_tx_phase_comp_fifo_error debug_rx_phase_comp_fifo_erro r aeq_togxb aeq_fromgxb siigx52002-4.2
2?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii gx alt2gxb ports list stratix ii gx alt2gxb ports list table 2?1 provides information about the stratix ii gx ports. table 2?1. stratix ii gx alt2gxb ports (part 1 of 7) port name input/output description scope receiver physical coding sublayer (pcs) ports rx_dataout output receiver parallel data output. the bus width depends on the channel width multiplied by the number of channels per instance. rx_clkout output recovered clock from the receiver channel. channel rx_coreclk output optional read clock port for the receiver phase compensation first-in fi rst-out (fifo). if not selected, quartus ii software automatically selects rx_clkout/tx_clkout as the read clock for receiver phase compensation fifo. if selected, you must drive this port with a clock that is frequency locked to rx_clkout/tx_clkout . channel rx_enapatternalign input enables word aligner to align to the comma. this port can either be edge or level sensitive based on the word aligner mode. in the double-width mode, this port is only edge-sensitive. channel rx_bitslip input word aligner bit-slip control. the word aligner slips a bit of the current word boundary every rising edge of this signal. channel rx_rlv output run-length violation indicator. a high pulse is given when the run length has detected a violation. channel rx_byteorderalignstatus output from byte ordering block. a high pulse is given when the byte ordering block has successfully aligned the bytes of the pcs output. channel pipe8b10binvpolarity input physical interface for pci express (pipe) polarity inversion at the 8b/10b decoder input. this port inverts the data at the input to the 8b/10b decoder. channel
altera corporation 2?3 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview pipestatus output pipe receiver status port. in case of multiple status signals, the lower number signal takes precedence. 000 ? received data ok 001 ? 1 skip added (not supported) 010 ? 1 skip removed (not supported) 011 ? receiver detected 100 ? 8b/10b decoder error 101 ? elastic buffer overflow 110 ? elastic buffer underflow 111 ? received disparity error. channel pipephydonestatus output pipe indicates a mode transition completion? power transition and rx_detect . a pulse is given. channel rx_pipedatavalid output pipe valid data indicator on the rx_dataout port. channel pipeelecidle output pipe signal detect for pci express. channel rx_digitalreset input reset port for the receiver pcs block. this port resets all the digital logic in the receiver channel. the minimum pulse width is two parallel clock cycles. channel rx_bisterr output built-in self test (bist) block error flag. this port latches high if an error is detected. assertion of rx_digitalreset resets the bist verifier, which clears the error flag. channel rx_bistdone output built-in self test verifier done flag. this port goes high if the receiver finishes reception of the test sequence. channel rx_ctrldetect output receiver control code indicator port. indicates whether the data at the output of rx_dataout is a control or data word. used with the 8b/10b decoder. channel rx_errdetect output 8b/10b code group violation signal. indicates that the data at the output of rx_dataout has a code violation or a disparity error. used with disparity error signal to differentiate between a code group error and/or a disparity error. in addition, in xaui mode, rx_errdetect is asserted in the corresponding byte position when alt2gxb substitutes the received data with 9?b1fe because of xaui protocol violations. channel table 2?1. stratix ii gx alt2gxb ports (part 2 of 7) port name input/output description scope
2?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii gx alt2gxb ports list rx_syncstatus output indicates when the word aligner either aligns to a new word boundary (in single-width mode the rx_patterndetect port is level sensitive), indicates that a resynchronization is needed (in single- or double-width mode the rx_patterndetect is edge sensitive), or indicates if synchronization is achieved or not (in single-width mode, the dedicated synchronization stat e machine is used). channel rx_disperr output 8b/10b disparity error indicator port. indicates that the data at the output of rx_dataout has a disparity error. channel rx_patterndetect output indicates when the word aligner detects the alignment pattern in the current word boundary. channel rx_a1a2size input available only in sonet/sdh oc-12 and oc-48 modes to select between one of the following two word alignment options: 0 ? 16-bit a1a2 1 ? 32-bit a1a1a2a2 channel rx_a1a2sizeout output available only in sonet/sdh oc-12 and oc-48 modes to indicate one of the following two word alignment options: 0 ? 16-bit a1a2 1 ? 32-bit a1a1a2a2 channel rx_invpolarity input available in all modes except (oif) cei phy. inverts the polarity of the received data at the input of the word aligner. channel rx_revbitorderwa input available in basic m ode with bit-slip word alignment or dynamic re configuration enabled. reverses the bit-order of the received data at a byte level at the output of the word aligner. channel rx_revbyteorderwa input available in basic double-width mode only. swaps the msbyte and lsbyte of the 16/20-bit data at the output of the word aligner. channel rx_enabyteord input available in modes with byte ordering block enabled. triggers the byte ordering block to perform byte alignment. channel debug_rx_phase_comp_ fifo_error output indicates receiver phase compensation fifo overrun or underrun situation. channel table 2?1. stratix ii gx alt2gxb ports (part 3 of 7) port name input/output description scope
altera corporation 2?5 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview receiver physical media attachment (pma) rx_pll_locked output receiver pll locked signal. indicates if the receiver pll is phase locked to the cru reference clock. channel rx_analogreset input receiver analog reset. resets all analog circuits in the receiver pma. channel rx_freqlocked output cru mode indicator port. indicates if the cru is locked to data mode or locked to the reference clock mode. 0 ? receiver cru is in lock-to-reference clock mode 1 ? receiver cru is in lock-to-data mode channel rx_signaldetect output signal detect port. in pipe mode, indicates if a signal that meets the specified range is present at the input of the receiver buffer. in all other modes, rx_signaldetect is forced high and must not be used as an indication of a valid signal at receiver input. channel rx_seriallpbken input serial loopback control port. 0 ? normal data path, no serial loopback 1 ? serial loopback channel rx_locktodata input lock-to-data control for the cru. use with rx_locktorefclk . channel rx_locktorefclk input lock-to-reference lock mode for the cru. use with rx_locktodata . rx_locktodata /rx_ locktorefclk 0/0 ? cru is in automatic mode 0/1 ? cru is in lock -to-reference clock 1/0 ? cru is in lock-to-data mode 1/1 ? cru is in lock-to-data mode channel rx_cruclk input receiver pll/cru reference clock. channel transmitter pcs tx_datain input transmitter parallel data input. the bus width is the channel width multiplied by the number of channels in the instance. channel tx_clkout output pld logic array clock from the transceiver to the pld. in a single-channel mode, there is one tx_clkout per channel. channel table 2?1. stratix ii gx alt2gxb ports (part 4 of 7) port name input/output description scope
2?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii gx alt2gxb ports list tx_coreclk input optional write clock port for the transmitter phase compensation fifo. if not selected, quartus ii software automatically selects tx_clkout as the write clock for transmitter phase compensation fifo. if selected, you must drive this port with a clock that is frequency locked to tx_clkout . channel tx_detectrxloopback input pipe receiver detect / loopback pin. depending on the power-down state the signal either activates receiver detect or loopback. channel tx_forceelecidle input pipe electrical idle mode. channel tx_forcedispcompliance input pipe forced negative disparity port for transmission of the compliance pattern. the pattern requires starting at a negative disparity. assertion of this port at the first byte ensures that the first byte has a negative disparity. this port must be deasserted after the first byte. channel powerdn input pipe power mode port. this port sets the power mode of the associated pci express channel. the power modes are as follows: 2'b00: p0 ? normal operation 2'b01: p0s ? low recover time latency, power saving state 2'b10: p1 ? longer recovery time (64 us max) latency, lower power state 2'b11: p2 ? lowest power state channel tx_digitalreset input reset port for the transmitter pcs block. this port resets all the digital logic in the transmit channel. the minimum pulse width is two parallel clock cycles. channel tx_ctrlenable input transmitter control code indicator port. indicates whether the data at the tx_datain port is a control or data word. this port is used with the 8b/10b encoder. channel tx_forcedisp input available in basic mode with 8b/10b encoding enabled. forces positive or negative disparity on the current symbol depending on the tx_dispval signal level. channel tx_dispval input available in basic mode with 8b/10b encoding enabled. a high forces negative starting running disparity on the current symbol and a low forces positive starting running disparity on the current symbol, provided tx_forcedisp signal is asserted. channel table 2?1. stratix ii gx alt2gxb ports (part 5 of 7) port name input/output description scope
altera corporation 2?7 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview tx_invpolarity input available in all modes except (oif) cei phy. inverts the polarity of the data to be transmitted at the transmitter pcs-pma interface (input to the serializer). channel debug_tx_phase_comp_ fifo_error output indicates transmitter phase compensation fifo overrun or underrun situation. channel transmitter pma fixedclk input 2.5-125 mhz clock for adaptive equalization (aeq) feature. 125-mhz clock for receiver detect functionality in pci express (pipe) mode. channel central control unit (ccu) rx_channelaligned output 10-gigabit attachment unit interface (xaui) deskew fifo aligned fl ag. this signal goes high after the channel aligner acquires channel alignment per the ieee 802.3ae specification. transceiver block coreclkout output 4 mode output. this is the clock output from the central clock generation block. in 8 mode, the central clock generator block from the lower transceiver generates this clock. for use with xaui, pci express, 4, and 8 modes. transceiver block reconfig_clk input input reference clock for the dynamic reconfiguration controller. the frequency range of this clock is 2.5 mhz to 50 mhz. the assigned clock uses global resources by default. this same clock should be connected to alt2gxb. reconfig_togxb input from reconfiguration controller for dynamic reconfiguration. transceiver block reconfig_fromgxb output to reconfiguration controller. transceiver block aeq_togxb input from reconfiguration controller for adaptive equalization. transceiver block aeq_fromgxb output to reconfiguration controller for adaptive equalization. transceiver block cmu pma gxb_powerdown input transceiver block reset and power down. this resets and powers down all circuits in the transceiver block. this does not affect the refclk buffers and reference clock lines. transceiver block table 2?1. stratix ii gx alt2gxb ports (part 6 of 7) port name input/output description scope
2?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii gx alt2gxb ports list pll_locked output pll locked indicator for the transmitter plls. transceiver block pll_inclk input reference clocks for the transmitter plls. transceiver block calibration block cal_blk_clk input calibration clock for the transceiver termination blocks. this clock supports frequencies from 10 mhz to 125 mhz. device cal_blk_powerdown (active_low) input power-down signal for the calibration block. assertion of this signal may interrupt data transmission and reception. use this signal to recalibrate the termination resistors if temperature and/or voltage changes warrant it. device external signals tx_dataout output transmitter serial output port. channel rx_datain input receiver serial input port. channel rrefb (1) output reference resistor port. this port is always used and must be tied to a 2k- resistor to ground. this port is highly sensitive to noise. there must be no noise coupled to this port. device refclk (1) input dedicated reference clock inputs (two per transceiver block) for the transceiver. the buffer structure is similar to the receiver buffer, but the termination is not calibrated. transceiver block gxb_enable input dedicated transceiver block enable pin. if instantiated, this port must be tied to the pll_ena input pin. a high level on this signal enables the transceiver block; a low level disables it. transceiver block note to ta b l e 2 ? 1 : (1) these are dedicated pins for the transc eiver and do not appear in the megawizard ? plug-in manager. table 2?1. stratix ii gx alt2gxb ports (part 7 of 7) port name input/output description scope
altera corporation 2?9 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 1 this chapter uses ?transceiver block number? and ?transceiver bank number? interchangeably. table 2?2 maps transceiver block numb er to the stratix ii gx transceiver bank number. transmitter modules this section describes the stratix ii gx transceiver?s transmitter path. this section describes the following modules: clock multiplier unit (cmu) transmitter phase compensation fifo buffer byte deserializer 8b/10b encoder serializer transmitter buffer clock multiplier unit the cmu in stratix ii gx devices takes the reference clock from either the pld or the dedicated reference clock inputs ( refclk0 and refclk1 ) and synthesizes the clocks that ar e used for the transmitter logic, serializer, receiver pll reference clock, and pld clocks. each transceiver block has its own cm u block that is further divided into three cmu sub blocks: transmitter pll block central clock divider block transmitter local clock divider block the transmitter pll block and central clock divider blocks are located in the central block of the transceiver bl ock. a transmitter local clock divider block is located in each transmitte r of the transceiver block. each transceiver block has a dedicated cmu block and two dedicated reference clock inputs that feed the cmu (refer to figure 2?2 ). table 2?2. transceiver block number to transceiver bank number mapping transceiver block number transceiver bank number 013 114 215 316 417
2?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules figure 2?2. clock multiplier unit block diagram note to figure 2?2 : (1) the global clock line must be driven by an input pin. the quartus ? ii software simplifies the cmu settings. it sets most of the settings automatically for protoc ol modes; for example, pll multiplication factors. you need provide only the data rate in the alt2gxb megawizard plug-in manager and then select the input clock frequency. dedicated reference clock pin specifications table 2?3 shows the i/o standards allowed for the reference clock pins. transmitter pll block central clock divider block tx clock gen block tx clock gen block transmitter channel [3..2] transmitter channel [1..0] transmitter high-speed & low-speed clocks transmitter high-speed & low-speed clocks transmitter local clock divider block transmitter local clock divider block reference clocks (refclks, global clock (1) , inter-transceiver lines) central block table 2?3. reference clock specifications (part 1 of 2) protocol i/o standard coupling termination basic, xaui, gige, sonet/sdh, (oif) cei phy, serial rapidio, sdi, cpri 1.2-v pcml, 1.5-v pcml, 3.3-v pcml, differential lvpecl, lvds ac on-chip
altera corporation 2?11 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?3 shows an example termination scheme for a reference clock signal when configured as hcsl. figure 2?3. dc coupling and external te rmination scheme for pci express reference clock notes (1) , (2) notes to figure 2?3 : (1) no biasing is required if the reference clock signals are generated from a clock source that conforms to the pci express specification. (2) select resistor values as recommended by the pci express clock source vendor. transmitter pll block the transmitter pll block contains two transmitter pl ls (transmitter pll0 and transmitter pll1) per tr ansceiver block, as shown in figure 2?4 . the transmitter pll block multip lies the reference clock to the frequency required to support the serial data rate. transmitter pll0 and transmitter pll1 can support data rates from 600 mbps to 6.375 gbps. each pll has a dedicated locked signal ( pll_locked ) that is fed to the pld logic array to indicate when th e plls are locked to the reference clock. pipe 1.2-v pcml, 1.5-v pcml, 3.3-v pcml, differential lvpecl, lvds ac on-chip hcsl (1) dc external (2) notes to ta b l e 2 ? 3 : (1) in pipe mode, you have the option of selecting the hcsl standard for the reference clock if compliance to pci express is required. the quartus ii software automatically selects dc coupling with external termination for the refclk signal if config ured as hcsl. (2) refer to figure 2?3 for an example termination scheme. table 2?3. reference clock specifications (part 2 of 2) protocol i/o standard coupling termination pci express (hcsl) refclk source refclk + refclk - stratix ii gx rs rs rp = 50 rp = 50 (2) (2)
2?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules you can use transmitter pll0 and tr ansmitter pll1 individually (one pll active at a time) to provide a base high-speed clock to the entire transceiver block, or simultaneously to provide support for the different data rates within the transceiver block that does not have a common base reference clock frequency. for exampl e, one pll can support a 1.25 gbps data rate with a 125 mhz reference clock and the other pll can support a 2.488 gbps data rate with a 62.2 mhz reference clock. you can use up to two reference clocks for the transmitter plls in a single transceiver block at any given time. the reference clocks can come from the following: dedicated reference clock pins of the associated transceiver blocks (two total per transceiver block) pld clock network (one per transc eiver block, must be connected directly from an input clock pin an d cannot be driven by user logic or enhanced pll) inter-transceiver lines (up to five total, one from each transceiver block) 1 if you assign an i/o or a non- refclk clock pin to provide clock only for the pll_inclk/rx_cruclk ports of the transceiver, the quartus ii software requires the following setting for the clock source in the assignment editor for successful compilation: assignment name: stratix ii gx refclk and termination setting value: use as regular i/o.
altera corporation 2?13 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?4 shows the transmitter pll block. figure 2?4. transmitter pll block note to figure 2?4 : (1) the global clock line must be driven by an input pin. transmitter plls there are two transmitter plls in each cmu (transmitter pll0 and transmitter pll1). transmitter pll0 and transmitter pll1 receive the reference clock from one of five inter-transceiver lines (refer to ?inter-transceiver line routing? on page 2?19 for more information), a global pld clock driven from a clock input pin, or from the dedicated reference clock refclk0 or refclk1 (both reference clock pins can drive either transmitter pll0 or transmitter pll1). you can divide the reference clocks from the refclk pins by two to support higher reference clock frequencies. transmitter pll0 and transmitter pll1 have half-rate vcos that operate at half the rate of the serial data st ream. the range of these vcos are from 500 mhz to 3.1875 ghz to support a native data rate of 1 gbps to 6.375 ghz. lower data rates (600 mbps to 1 gbps) are supported via additional clock di viders (refer to ?clock synthesis? on page 2?16 for more information). pfd dedicated local refclk 0 cp+lf up dn vco m high-speed transmitter pll cloc k inter-transceiver block routing (iq[4..0]) inter-transceiver block routing (iq[4..0]) inclk l pfd dedicated local refclk 1 cp+lf up dn vco m 2 inclk l transmitter pll 1 transmitter pll 0 high-speed transmitter pll0 clock high-speed transmitter pll1 clock to inter-transceiver block line /2 2 from global clock (1)
2?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules the pll contains two multiplier bl ocks in the pll feedback loop to multiply the reference cl ock to support the requ ired data rate. the quartus ii software automatically sele cts the values for all the dividers. you must input a data rate and select the input clock frequency. the pll output feeds the central clock divider block through the high-speed transmitter pll clock mul tiplexer or feeds the transmitter local clock divider block in each transmitter channel through the high-speed transmitter pll clocks. central clock divider block the central clock divider block is located in the central block of the transceiver block (refer to figure 2?2 ). this block provid es the high-speed clock for the serializer and the low- speed clock for the transceiver?s pcs logic within the transceiver block in a four-lane mode. in physical interface for pci express (pipe) 8 mode, the central clock divider block also provides the high-speed clock and low-speed clock for the adjacent upper transceiver block and provides the high- and low-speed clocks to the associated transceiver block. th e plls, central clock divider block, and the transmitter local clock dividers are powered down in the adjacent upper transceiver block in an eight-lane configuration. figure 2?5 shows the central clock divider block. the / 4, /5, /8, and /10 block generates the slow-speed clock ba sed on the serialization factor. in an eight-lane configuration in pi pe mode, the slow-speed clock is multiplexed from the lowe r transceiver block. the high-speed clock goes directly into each channel?s serializer through a clock multiplexer.
altera corporation 2?15 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?5. central clock divider block notes to figure 2?5 : (1) feeds the transmitter within the transcei ver and the above adjacent transceiver block. (2) feeds the pcs logic. figure 2?6 shows the clock selection for the serializer. figure 2?6. serializer high-speed clock connection the central clock divider block feeds all the channels in the transceiver block and, in pipe 8 mode, it also feeds the adjacent upper transceiver block. this ensures that the serializer in each channel outputs the same bit number at the same time and mini mizes the channel-to-channel skew. 4, 5, 8, or 10 high-speed transmitter pll clock slow-speed clock from lower transceiver block high-speed clock to transmitter (1 ) slow-speed clock to transceiver block (2) central clock divider block central clock divider block of lower transceiver block high speed clock from: serializer
2?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules transmitter local clock divider block the tx local clock divider blocks are located in each transmitter channels of the transceiver block. the purpos e of this block is to provide the high-speed clock for the serializer and the low-speed clock for the transmitter data path and the pld fo r all the transmitters within the transceiver block. this allows for each of the transmitter channels to run at different rates. the /n divider offers a /1, /2, and /4 factors to provide capability to reduce base frequency of the driving pll to a half or a quarter rate. this allows each transmi tter channel to run at a /1, /2, or /4 of the original data rate. figure 2?7 shows the transmitter lo cal clock divider block. figure 2?7. transmitter local clock divider block each transmitter local clock divider bl ock is operated independently, so there is no guarantee that each channe l sends out the same bit at the same time. clock synthesis each pll in a transceiver block receives a reference clock and generates a high-speed clock that is forwarded to the clock generator blocks. there are two types of clock generators: the transmitter local clock divider block the central clock divider block the transmitter local clock divider bl ock resides in the transmit channel and synthesizes the high-speed serial clock (used by th e serializer) and slow-speed clock (used by the transmitter?s pcs logic). the central clock divider block resides in the transcei ver block outside the transmit or receive channels. this block synthesizes the high-speed serial clock (used by the serializer) and sl ow-speed clock (used by the transceive r block pcs logic?transmitter and receiver (if th e rate matcher is used). the pld 4, 5, 8, or 10 high-speed clock to transmitte r slow-speed clock to transmitter high-speed clock from transmitter pll0 high-speed clock from transmitter pll1 1, 2, or 4 n
altera corporation 2?17 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview clock is also supplied by the central clock divider block and goes through the divide-by-two block (located in the central block of the transceiver block) if the byte serializer/deserializer is used. the plls in the transceiver have half rate vcos that run at half the rate of the data stream. when in the indi vidual channel mode, the slow-speed clocks for the transmitter logic an d the serializer need only be / 4 or a / 5 divider to support a 8 and 10 serialization factor. the 16 and 20 serialization factor is supported by the / 8 and / 10 clock divider. table 2?4 shows the divider settings for achievin g the available serialization factor. in the four-lane mode, the central clock divider block supplies all the necessary clocks for the entire transceiver block. the reference clock ranges from 50 mhz to 622.08 mhz. the phase frequency detector (pfd) has a mini mum frequency limit of 50 mhz and a maximum frequency limit of 325 mhz. the refclk pre-divider (/2 ) is available if you use the dedicated refclk pins for the input reference clock. the refclk pre-divider is required if one of the following conditions is satisfied: 1. if the input clock frequenc y is greater than 325 mhz. 2. for functional modes with a data ra te less than 3.125 gbps (the data rate is specified in the what is the data rate? option in the general tab of the alt2gxb megawizard): if the input clock frequency is greater than or equal to 100 mhz and if the ratio of data rate to input clock frequency is 4, 5, or 25 table 2?4. serialization factor and divider settings serialization factor divider setting 8 / 4 10 / 5 16 / 8 20 / 10
2?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules 3. for functional modes with an data rate greater than 3.125 gbps: if the input clock frequency is greater than or equal to 100 mhz and if the ratio of data rate to input clock frequency is 8, 10, or 25 table 2?5 shows the refclk pre-divider and the available pll multiplication factors. table 2?6 shows the multiplication values for basic mode. transmitter pll bandwidth setting the stratix ii gx transmitter plls in the transceiver offer a programmable bandwidth setting. the bandwidth of a pll is the measure of its ability to track the input clock and jitter. it is determined by the ?3db frequency of the cl osed-loop gain of the pll. there are three bandwidth settings: high, medium, and low. the high bandwidth setting filters out intern al noise from the vco because it tracks the input clock above the freq uency of the internal vco noise. with the low bandwidth setting, if th e noise on the input reference clock table 2?5. multiplication values as a function of the reference cloc k source to the transmitter pll transmitter pll reference clock so urce reference clock pre-divider / m (2) / l inter-transceiver routing 1, 2 (1) 1, 4, 5, 8, 10, 16, 20, 25 1, 2, 4 dedicated local reference clock 1, 2 1,4,5,8,10,16,20, 25 1, 2, 4 notes to ta b l e 2 ? 5 : (1) the / 2 is achieved by using the pre-divider on the driving refclk pin. (2) the m, l counters are automaticall y selected by the quartus ii software based on the selected data rate and protocol and the reference clock frequency. table 2?6. multiplication values allowed in basic mode protocol functional mode reference clock pre-divider / m basic single width 1, 2 4, 5, 8, 10, 16, 20, 25 basic double width (1 gbps to 3.125 gbps) 1, 2 4, 5, 8, 10, 16, 20, 25 basic double width (> 3.125 gbps to 6.375 gbps) 1, 2 8, 10, 16, 20, 25
altera corporation 2?19 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview is greater than the internal noise of the vco, the pll filters out the noise above the ?3db frequency of the closed -loop gain of the pll. the medium bandwidth setting is a compromise between the high and low settings. the ?3db frequencies for these settings can vary because of the non-linear nature and frequency dependencies of the circuit. inter-transceiver line routing the inter-transceiver lines allow the refclk of one transceiver block to drive other transceiver blocks. there are a maximum of five inter-transceiver clock routing lines available in each device in the stratix ii gx family. each tran sceiver block can drive one inter-transceiver line from ei ther one of its associated refclk pins. the inter-transceiver lines can drive any or all of the transmitter plls and receiver plls in the device. the inter-transceiver lines offer flexibility when multiple channels in separate transceiver blocks share a common reference clock frequency. the inter-tr ansceiver lines only distribute the reference clock and cannot be used to bond channels because each pll and clock dividers operate independently. if you select an input reference clock frequency such that it requires the use of the refclk pre-divider, you cannot use the clock on refclk pins to drive pld logic. the inter-transceiver lines also dr ive the reference clock from the refclk pins into the pld, which reduces the need to drive multiple clocks of the same frequency into the device. the quartus ii software automat ically uses the appropriate inter-transceiver line if the transc eiver block is being clocked by the dedicated reference clock ( refclk ) pin of another transceiver block. figure 2?8 shows the inter-transceiver line interface to the transceivers in the gigabit transceiver blocks an d to the pld. the connections of transceiver block 0 are shown. the oth er connections are the same, with the exception of the inter-transceive r line number that the transceiver block drives.
2?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules figure 2?8. inter-transceiver lines of a fi ve transceiver block device (2sgx130g) note to figure 2?8 : (1) the global clock line must be driven by an input pin. transceiver clock distribution this section describes single-lan e, four-lane, and eight-lane configurations for the high-speed an d low-speed transceiver clocks. all protocol support falls in the single -lane configuration except for the four-lane and eight-lane pipe mode and xaui. the four -lane pipe mode uses the four-lane configuration. th e eight-lane pipe mode uses the eight-lane configuration. single lane in a single-lane configuration, the plls in the central block supply the high speed clock and the clock genera tion blocks in each transmitter channel divides down that clock to the frequency needed to support its particular data rate. in this config uration, two separate clocks can be supplied through the central block to provide support for two separate base frequencies. the transmitter cl ock generation blocks can divide those down to create additional frequencies for specific data rate transmitter pll 0 transceiver block 0 4 receiver plls transmitter pll 1 from global clock (1) rx_cruclk refclk0 2 refclk1 2 transceiver block 1 transceiver block 2 transceiver block 3 transceiver block 4 to iq4 to iq3 to iq2 to iq1 to iq0 iq[4..0] iq[4..0] iq[4..0]
altera corporation 2?21 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview requirements. each of the four tran smitter channels can operate at a different data rate with the use of the individual transmitter local clock dividers and both transmitter pll0 and transmitter pll1. 1 if you instantiate four channels and are not in pipe 4, xaui, or basic single-width mode with 4 clocking, the quartus ii software automatically chooses the single-lane configuration. figure 2?9. clock distribution for individual channel configuration four-lane mode in a four-lane configuration ( figure 2?10 ), the central block generates the parallel and serial clocks that feed the transmitter channels within the transceiver. all channels in a transceiver must operate at the same data rate. this configuration is only supported in pipe 4, xaui and basic single-width mode with 4 clocking. tx local clk div block tx local clk div block tx channel 2 central block tx channel 0 refclk 0 refclk1 txpll block txpll 0 txpll 1 tx channel 3 tx channel 1 high speed txpll 0 clock high speed txpll 1 clock
2?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules figure 2?10. clock distribution for a four-lane configuration note to figure 2?10 : (1) the global clock line must be driven by an input pin. eight-lane mode the eight-lane mode (refer to figure 2?11 ) is reserved for pipe 8 use only. the central block of the lower transceiver supplies the parallel and serial clocks for all eigh t transmitter channels. the clock distribution uses a dedicated eight-lane clocking routing that offers low skew for transmitter channel-to-channel skew specification. the high- and low-speed clocks are forwarded using this dedicated eight-lane clocking tree. the central block of the upper transceiver block and all the transmitter clock generation blocks are unused and are powered down in this mode. the clock to the pld ( coreclkout ) is generated by the central clock generation block of the master transceiver block (the lower transceiver block). transmitter channel 2 transmitter channel 0 transmitter pll block transmitter pll0 transmitter channel 3 transmitter channel 1 transmitter pll1 central clock divider block coreclk_out to pld reference clocks (refclks, global clock (1) , iq lines) central block 2
altera corporation 2?23 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?11. clock distribu tion for eight-lane mode note to figure 2?11 : (1) the global clock line must be driven by an input pin. only designated lower transceiver blocks can be used as a master (transceiver blocks 1 and 3), and de signated upper transceiver blocks (transceiver blocks 0 and 2) can be us ed as a slave as long as they are coupled to the lower master transcei ver block. the quartus ii software automatically utilizes the correct transceiver blocks in a 8 mode if you do not assign placement. if you do not place the master and slave transceiver blocks accordingly (throu gh pin assignments), a no fit error occurs. transmitter channel 0 transmitter channel 1 transmitter channel 2 central block transmitter channel 0 transmitter channel 3 transmitter channel 1 transmitter channel 2 transmitter channel 3 central block coreclkout to pld 2 slave master transmitter pll block transmitter pll0 transmitter pll1 reference clocks (refclks, global clock (1) , iq lines) central clock divider block
2?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules single transceiver block devices (e p2sgx30c and ep2sgx60c) cannot be used for pci-e 8 mode. figure 2?12 shows how double transceiver block devices (ep2sgx30d and ep2sgx60d) are configured for pci-e 8 mode. figure 2?12. two transceiver block device with one 8 pci-e link gxb_tx/rx1 gxb_tx/rx0 gxb_tx/rx2 gxb_tx/rx3 gxb_tx/rx5 gxb_tx/rx4 gxb_tx/rx6 gxb_tx/rx7 ep2sgx30df ep2sgx60df pcie lane 4 pcie lane 5 pcie lane 7 pcie lane 6 pcie lane 0 pcie lane 1 pcie lane 3 pcie lane 2 bank 13 (slave) bank 14 (master)
altera corporation 2?25 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the three transceiver block devices (ep2sgx60e and ep2sgx90e) support only one pci-e 8 link. figure 2?13 shows the pci-e 8 configuration. figure 2?13. three transceiver block de vice with one 8 pci-e link note (1) note to figure 2?13 : (1) transceiver bank 15 can be active and used to support other protocols. gxb_tx/rx1 gxb_tx/rx0 gxb_tx/rx2 gxb_tx/rx3 gxb_tx/rx5 gxb_tx/rx4 gxb_tx/rx6 gxb_tx/rx7 ep2sgx60ef ep2sgx90ef pcie lane 4 pcie lane 5 pcie lane 7 pcie lane 6 pcie lane 0 pcie lane 1 pcie lane 3 pcie lane 2 bank 13 (slave) bank 14 (master) gxb_tx/rx9 gxb_tx/rx8 gxb_tx/rx10 gxb_tx/rx11 bank 15
2?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules a four transceiver block device (ep2sgx90f) supports up to two pci-e 8 links (refer to figure 2?14 ). the transceiver block pairs are blocks 0 and 1 and blocks 2 and 3. if only one pci-e 8 link is used, the other transceiver blocks can be active and be used to support other protocols. figure 2?14. four transceiver block device with two 8 pci-e links gxb_tx/rx1 gxb_tx/rx0 gxb_tx/rx2 gxb_tx/rx3 gxb_tx/rx5 gxb_tx/rx4 gxb_tx/rx6 gxb_tx/rx7 ep2sgx90ff pcie lane 4 pcie lane 5 pcie lane 7 pcie lane 6 pcie lane 0 pcie lane 1 pcie lane 3 pcie lane 2 bank 13 (slave) bank 14 (master) gxb_tx/rx9 gxb_tx/rx8 gxb_tx/rx10 gxb_tx/rx11 gxb_tx/rx13 gxb_tx/rx12 gxb_tx/rx14 gxb_tx/rx15 pcie lane 4 pcie lane 5 pcie lane 7 pcie lane 6 pcie lane 0 pcie lane 1 pcie lane 3 pcie lane 2 first pipe x8 channel second pipe x8 channel bank 15 (slave) bank 16 (master)
altera corporation 2?27 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview a five transceiver device (ep2sg x130g) supports up to two pci-e 8 links (refer to figure 2?15 ). the transceiver block pairs are the same as in the four transceiver device?blocks 0 an d 1 and blocks 2 and 3. block 4 is not used for pci-e 8 mode. if any tran sceiver blocks are not used in the pci-e 8 mode, they can be used to support any other protocol. figure 2?15. five transceiver block de vice with two 8 pci-e links note (1) note to figure 2?15 : (1) transceiver bank 17 can be active and used to support other protocols. gxb_tx/rx1 gxb_tx/rx0 gxb_tx/rx2 gxb_tx/rx3 gxb_tx/rx5 gxb_tx/rx4 gxb_tx/rx6 gxb_tx/rx7 ep2sgx130gf pcie lane 4 pcie lane 5 pcie lane 7 pcie lane 6 pcie lane 0 pcie lane 1 pcie lane 3 pcie lane 2 bank 13 (slave) bank 14 (master) gxb_tx/rx9 gxb_tx/rx8 gxb_tx/rx10 gxb_tx/rx11 gxb_tx/rx13 gxb_tx/rx12 gxb_tx/rx14 gxb_tx/rx15 pcie lane 4 pcie lane 5 pcie lane 7 pcie lane 6 pcie lane 0 pcie lane 1 pcie lane 3 pcie lane 2 first pipe x8 channel second pipe x8 channel gxb_tx/rx17 gxb_tx/rx16 gxb_tx/rx18 gxb_tx/rx19 bank 17 bank 15 (slave) bank 16 (master)
2?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules channel clock distribution this section describes clocking within each channel for: individual channels in basic (without 4 clocking enabled), sonet/sdh, pipe x1, gige, (o if) cei phy interface (with low-jitter option disabled), serial rapidio, sdi, and cpri modes bonded channels in xaui, pipe 4, pipe 8, basic (with 4 clocking enabled), and (oif) cei phy interface (with low-jitter option enabled) modes individual channels clocking in individual channel modes, the transmitter logic is clocked by the slow-speed clock from the clock di vider block. the transmitter phase compensation fifo buffer and the pipe interface (in pipe mode) are clocked by the tx_clkout clock of the channel that is fed back to the transmitter channel from the pld logic. figure 2?16 shows the clock routing for the transmitter channel. figure 2?16. individual channel transmitter logic clocking the receiver logic clocking has two clocking methods: one when rate matching is used and the other when rate matching is not used. if rate matching is used (pipe, gige, and basic modes), the receiver logic from the serializer to the rate matche r is clocked by the recovered clock from its associated channel. the rest of the logic is cl ocked by the slow clock from the clock divider block of its associat ed channel. the read side of the phase compensation fifo buff er and the pipe interface (for pipe mode) is clocked by the tx_clkout fed back through the pld logic. figure 2?17 shows the clocking of the receiv er logic with the rate matcher. byte serializer transmitter analog circuits transmitter digital logic serializer pld logic array phase compen- fifo sation tx 8b/10b encoder pipe interface xcvr central block reference clocks tx_clkout 1, 2
altera corporation 2?29 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?17. individual channel receiver logic clocking with rate matching if rate matching is no t used (basic, sonet/sd h, cpri, (oif) cei phy interface, sdi, serial rapidio modes) , then the receiver logic is clocked by the recovered clock of its associated channel ( figure 2?18 ). the receiver phase compensation fifo buffer?s read port is clocked by the recovered clock that is fed back from the pld logic array as rx_clkout . figure 2?18. individual channel receiver logic clocking without rate matching transmitter clocking (bonded channels) the clocking in bonded channel modes ( figure 2?19 ) is different from that of the individual channel. all the transmitters are synchronized to the same transmitter pll and clock div ider from the central block. in 4 bonded channel modes, the central cl ock divider of the transceiver block clocks all 4 channels. in pipe 8 bo nded channel mode, the central clock divider of the master transceive r block clocks all 8 channels. the transmitter logic up to the read port of the transmitter phase compensation fifo buffer is clocked by the slow -speed clock from the central block. the pipe interface an d the write port of the transmitter phase compensation fifo bu ffer is clocked by the coreclkout signal routed from the pld. in the pipe 8 slave transceiver, the central block of the associated transceiver is not ac tive and the transm itter logic to the read port of the transmitter phase comp ensation fifo buff er is clocked by receiver digital logic receiver analog circuits rx phase compen- sation fifo clock recovery unit central block referenc e clocks word aligner 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer pipe interface pld tx_clkout xcvr 1, 2 receiver digital logic receiver analog circuits rx phase compen- sation fifo clock recovery unit word aligner 8b/10b decoder byte de- serializer byte ordering de- serializer pipe pld rx_clkout xcvr 1, 2
2?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules the slow-speed clock from the master transceiver. the pipe interface and the write port of the transmitter ph ase compensation fifo buffer is clocked by the coreclkout signal of the master transceiver. the slave transceiver does not output a coreclkout signal because the cmu is powered down. figure 2?19. transmitter channel cl ocking in transceiver mode for the receiver logic, in xaui mode ( figure 2?20 ), the local recovered clock feeds the logic up to the write clock of the deskew fifo buffer. the recovered clock from channel[0] feeds the read clock of the deskew fifo buffer and the write port of th e rate matcher. the slow clock from the central block feeds the rest of the logic up to the write port of the phase compensation fifo buffer. the coreclkout signal routed through the pld from the central block feeds the re ad side of the phase compensation fifo buffer. figure 2?20. receiver channel clocking in xaui mode in the pipe 4 and pipe 8 modes ( figure 2?21 ), the local recovered clock feeds the logic up to the write port of the rate matcher fifo buffer. the slow clock from the central block feeds the rest of the logic up to the write port of the phase compensation fifo buffer. the coreclkout signal routed through the pld from the centra l block feeds the read side of the phase compensation fifo buffer. in pipe 8, the slave transceiver takes byte serializer transmitter analog circuits transmitter digital logic serializer pld logic array phase compen- fifo sation tx 8b/10b encoder pipe interface xcvr central block reference clocks coreclkout 1, 2 receiver digital logic receiver analog circuits rx phase compen- sation fifo clock recovery unit word aligner 8b/10b decoder byte de- serializer byte ordering rate match fifo deskew fifo de- serializer pld coreclkout xcvr central block reference clocks recovered clock from channel 0 1, 2
altera corporation 2?31 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the clocks from the central block of th e master transceiver. the individual channel clock distribution of the sl ave transceiver is the same as the master transceiver. figure 2?21. receiver channel pipe 4 and 8 modes transmitter phase compensation fifo buffer the transmitter phase compensation fifo buffer ( figure 2?22 ) is located at the device?s logic array interf ace in the transmitter block and compensates for phase difference betw een the transmitter clock and the clock from the pld. th e transmitter phase compensation fifo buffer operates in two modes: low latency and high latency. in the low latency mode, the fifo buffer is four wo rds deep. the quartus ii software chooses low latency mode automatically for every mode except the pci-express pipe mode (which automatically uses high latency mode). in high latency mode, the fifo buffer is eight words deep. figure 2?22. transmitter phase compensation fifo buffer the phase compensation fifo buffer ?s read port is clocked by the transmitter pll clock. th e write clock is fed by tx_clkout of the associated channel in a single-channel conf iguration. the fifo buffer?s write clock is clocked by coreclkout in the four- or eight-channel configuration. receiver digital logic receiver analog circuits rx phase compen- sation fifo clock recovery unit word aligner 8b/10b decoder byte de- serializer byte ordering pipe rate match fifo de- serializer pld coreclkout xcvr central block reference clocks 1, 2 transmitter phase compensation fifo dataout[39..0] from pipe or pld datain[39..0] control signals in [3..0 control signals out [3..0] to byte serialize r tx_clkout or coreclk_out from pld slow-speed transmitter clock
2?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules the transmitter phase compensation fifo buffer is always used and cannot be bypassed. the input to the transmitter phase compensation fifo buffer is the data from the pld logic array or the pipe interface in pipe mode. transmitter phase compensation fifo error flag the write port of the transmitter phase compensation fifo can be clocked by either transm itter pll output clock ( tx_clkout or coreclkout ) or a pld clock. the read po rt is always clocked by the transmitter pll output cl ock. in all configurations, the write clock and the read clock must have 0 ppm di fference to avoid overrun/underflow of the phase compensation fifo. an optional debug_tx_phase_comp_fifo_error port is available in all modes to indicate transmit ter phase compensation fifo overrun/underflow condition. the debug_tx_phase_comp_fifo_error is asserted high when the phase compensation fifo gets either full or empty. this feature is useful to verify the phase compensation fifo overrun/underflow condition as a probable cause of link errors. byte serializer the byte serializer ( figure 2?23 ) converts the two- or four-byte interface into a one- or two-byte-wide data pa th for the transceiver from the pld interface. the pld interface has a limi t of 250 mhz, so the byte serializer is required to stripe the parallel data into the single- or double-wide transceiver data path. at 6.375 gb ps, the transceiver logic has a double-byte-wide data path that runs at 318.75 mhz in a 20 serializer factor, which is above the maximum pld interface speed. by using the byte serializer, the pld interface width doubles to 40-bits (36 bits when using the 8b/10b encoder) and the interface speed drops to 159.375 mhz. figure 2?23. byte serializer byte serializer dataout[19..0] from transmitter phase compensation fifo datain[39..0] control signals in [3..0] control signals out [1..0] to 8b/10b encode r slow-speed transmitter clock slow-speed transmitter clock or divide b y 2 version 2
altera corporation 2?33 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the byte serializer takes in a 40-, 32- , 20-, or 16-bit-wide input from the phase compensation fifo bu ffer and serializes it to 20, 16, 10, or 8 bits, respectively (refer to table 2?7 ). at the same time, the clock frequency is doubled. after serialization, the byte serializer transmits the leas t significant byte to the most significant byte. always use the transmitter digital reset to reset the byte serializer fifo pointe rs whenever the transmitter pll loses lock. refer to ?reset control and power down? on page 2?214 for further details on the reset sequence. figure 2?24 shows byte serializer input and output signals when serializing a 20-bit input to 10 bits. the tx_datain signal is the input from the fpga?s logic array that has already passed through the transmitter phase compensation fifo buffer. figure 2?24. transmitter byte serializer in figure 2?24 , the lsb is transmitted before the msb in the transmitter byte serializer. for the input of d1, the output is d1 lsb and then d1 msb . 8b/10b encoder the 8b/10b encoder (refer to figure 2?25 ) is part of the stratix ii gx transceiver digital blocks and lies between the byte serializer and the serializer. the 8b/10b encoder operat es in two modes: single-width and double-width and can be bypassed if the 8b/10b encoder is not used. in single-width mode, the 8b/10b enco der generates a 10-bit code group table 2?7. byte serializer input and output data widths input data width (bits) output data width after byte serialization (bits) 40 20 32 16 20 10 16 8 d1 lsb d1 msb d2 lsb d2 msb datain[19..0] dataout[9..0] d1 d2 d3 {10'h3e0, 10'h2a0} xxxxxxxxxx 10'h2a0 xxxxxxxxxx 10'h3e0 10'h318 10'h3c7 {10'h318, 10'h3c7} {10'h2aa, 10'h333}
2?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules from the 8-bit data and 1-bit contro l identifier. in double-width mode, there are two 8b/10b encoders that ar e cascaded together to generate two 10-bit code groups from two 8-bit data and their respective control identifiers. the 8b/10b encoder co nforms to the ieee 802.3 1998 edition standards. figure 2?25. 8b/10b encoder note to figure 2?25 : (1) the control signal is tx_ctrlenable . single-width mode the 8b/10b encoder data path active in single-width mode is highlighted in figure 2?26 . figure 2?26. 8b/10b encoder , single-width mode note to figure 2?26 : (1) the control signal is tx_ctrlenable . 8b/10b encoder msbyte dataout[19..10] from byte serializer datain[15..8] control signals[1] (1) 8b/10b encoder lsbyte dataout[9..0] datain[7..0] control signals[0] to serialize r (1) 8b/10b encoder msbyte dataout[19..10] from byte serializer datain[15..8] control signal[1] (1) 8b/10b encoder lsbyte dataout[9..0] datain[7..0] control signal[0] to serialize r (1)
altera corporation 2?35 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 10-bit encoding in single-width mode, the 8b/10b en coder translates the 8-bit data or 8-bit control character (as qualified by the control identifier) to a 10-bit code group with proper disparity. figure 2?27 shows the conversion format. the lsb is transmitted first. f for additional information regarding the 8b/10b code itself, refer to the specifications & addi tional information chapter in volume 2 of the stratix ii gx handbook . figure 2?27. 8b/10b conversion format reset condition the tx_digitalreset signal resets the 8b/10b encoder. during reset, the running disparity registers and the data registers are cleared. the 8b/10b encoder outputs a k28.5 pattern from the rd- column continuously until tx_digitalreset goes low. the input data and tx_ctrlenable signals are ignored during the reset state. once out of reset, the 8b/10b encoder starts wi th a negative disparity (rd-) and transmits three k28.5 code groups fo r synchronizing before it starts encoding and transmitti ng the data on the tx_datain port. while the tx_digitalreset signal is asserted, the 8b/10b decoder receives errors in the form of an invalid code error, synchronization error, control detect, and/or disparity error. 7 6 5 4 3 2 1 0 hgf edcba 8b/10b conversion 7 6 5 4 3 2 1 0 9 8 gf iedcba jh lsb msb ctrl
2?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules figure 2?28 shows the 8b/10b encoder?s reset behavior. when in reset ( tx_digitalreset is high), a k28.5- (k28.5 10-bit code group from the rd- column) is sent continuously until tx_digitalreset is low. the transmitter channel pipeli ning causes some ?don?t cares (10'hxxx)? until the first of three k28.5 is sent. user data follows the third k28.5. figure 2?28. transmitter output during reset conditions control code encoding the tx_ctrlenable port identifies if the 8-bit data at the tx_datain port is to be encoded as a control word (kx.y). if this port is not used, there is no way to send control words out. when tx_ctrlenable is low, the byte at tx_datain port of the transceiver is encoded as data (dx.y). when tx_ctrlenable is high, the data at the tx_datain port is encoded as a kx.y code group. the waveform in figure 2?29 shows that the 2nd 0xbc is encoded as a control word (k28.5). the rest of the tx_datain bytes are encoded as data (dx.y). figure 2?29. control word identification waveform 1 the 8b/10b encoder does not check to see if the code word entered is one of the 12 valid codes. if you enter an invalid control code, the resultant 10-bit code group may be encoded as an invalid code (does not map to a valid dx.y or kx.y code), or unintended valid dx.y code, depending on the value entered. clock tx_dataout[9..0 ] tx_digitalreset k28.5- k28.5- k28.5- xxx xxx k28.5- k28.5+ k28.5- dx.y+ ... clock tx_datain[7..0] tx_ctrlenable 83 78 bc bc 0f 00 bf 3c d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1 code group
altera corporation 2?37 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview it is possible for an 8b/10b decoder to decode an invalid control word encoded into a valid dx.y code without asserting any code error flags. for example, depending on the current running disparity, the invalid code k24.1 ( tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (018c), which is equiva lent to a d24.6+ (8'hd8 from the rd+ column). altera recommends that you do not send invalid control words. double-width mode in double-width mode, the 8b/10b en coder operates in a cascaded mode. the least significant byte is transmi tted prior to the most significant byte. figure 2?30 shows the active 8b/10b enco der blocks in double-width mode. figure 2?30. active 8b/10b encoder blocks in double-width mode note to figure 2?30 : (1) the control signal is tx_ctrlenable . 20-bit encoding in double-width mode, the cascaded 8b/10b encoders generate two 10-bit code groups from two 8-bit data and their respective control identifiers. the 8b/10b encoder forw ards the current running disparity value from the lsbyte encoder to the msbyte encoder to calculate the disparity of the symbol going into the msbyte encoder. the msbyte encoder?s ending running disparity is then fed back to the lsbyte encoder on the next clock cycle. 8b/10b encoder msbyte dataout[19..10] from byte serializer datain[15..8] control signals[1] (1) 8b/10b encoder lsbyte dataout[9..0] datain[7..0] control signals[0] to serializer (1)
2?38 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules refer to figure 2?31 for the conversion format . the lsb is transmitted first. figure 2?31 shows the 20-bit encoding. figure 2?31. 8b/10b conversion format reset condition the tx_digitalreset signal resets the 8b/10b encoder. during reset, the running disparity registers and the data registers are cleared. also, the 8b/10b encoder outputs a k28.5 pattern with proper disparity continuously until tx_digitalreset goes low. the tx_datain and tx_ctrlenable ports are ignored during the reset state. once out of reset, the 8b/10b encoder starts th e lsbyte with a negative disparity (rd-) bias and the msbyte with a po sitive disparity (rd+) and transmits six k28.5 code groups (three on th e lsbyte and three on the msbyte encoder) for synchronizing before it starts encoding and transmitting the data on tx_datain . if the reset signal for the 8b/10b en coder is asserted, the 8b/10b decoder receiving the data may receive an invalid code error, synchronization error, control detect, and/or disparity error while tx_digitalreset is high. figure 2?32 shows the reset behavior of the 8b/10b encoder. when in reset ( tx_digitalreset is high) a k28.5- code group is sent continuously until tx_digitalreset is low. transmitter channel pipelining causes some ?don?t cares? (10?hxxx) until the first k28.5 is sent ( figure 2?32 shows six don?t cares, but the number can vary). both lsbyte and msbyte transmit three k28.5 code groups each before the data at the tx_datain port is encoded and sent out. 8b/10b encoder lsbyte 8b/10b encoder msbyte dataout[19:1 0] dataout[9: 0] datain[15:8 ] to serializer (piso) datain [7:0] from byte serializer control signals[0] control signals[1] (1) (1)
altera corporation 2?39 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?32. transmitter output during reset conditions control code encoding the tx_ctrlenable port identifies which 8-bit data is encoded as a control word. if this port is not us ed, control words cannot be sent. in double-width mode, the tx_ctrlenable port has two bits. the lower bit is associated wi th the lsbyte and the upper bit is associated with the msbyte. when tx_ctrlenable is low, the byte at the tx_datain port of the transceiver is encoded as data (dx.y), otherwise, it is encoded as a control code (kx.y). figure 2?33 shows that the lower byte of the second byte of tx_datain (8?hbc) is encoded as a control code as identified by a high on the lower tx_ctrlenable bit?s second clock cycle. figure 2?33. control word identification waveform the 8b/10b encoder does not check to se e if the code word entered is one of the 12 valid codes. if an invalid control code is entered, the resultant 10-bit code may be encoded as an invalid code (does not map to a valid dx.y or kx.y code), or unintended valid dx.y code, depending on the value entered. it is possible for an 8b/10b decoder to decode an invalid control word encoded into a valid dx.y code without asserting any code error flags. for example, depending on the current running disparity, the invalid code clock dataout[19..10 ] tx_digitalreset k28.5- k28.5- k28.5- xxx xxx xxx k28.5+ k28.5+ k28.5+ dx.y+ dataout[9..0 ] k28.5+ k28.5+ k28.5+ xxx xxx xxx k28.5- k28.5- k28.5- dx.y- clock tx_datain[15..0] tx_ctrlenable[1..0] 83 78 bc bc 0f 00 bf 3c d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1 code group 01 0
2?40 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules k24.1 ( tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0x18c), which is equivale nt to a d24.6+ (8'hd8 from the rd+ column). altera recommends that you do not send invalid control words. transmitter force disparity upon power on or reset, the 8b/10b encoder has a negative disparity and will choose the 10-bit code from th e rd- column. the transmitter force disparity feature allows altering the running disparity via the tx_forcedisp and tx_dispval ports. two optional ports namely tx_forcedisp and tx_dispval ports are available in 8b/10b enabled basic single-width and basic double-width modes. in double-width mode, both tx_forcedisp and tx_dispval signals have two bits. the low bit is as sociated to the lsbyte and the high bit is associated to the msbyte. a high value on the tx_forcedisp bit will change the disparity value of th e data to the value indicated by the associated tx_dispval bit. if the tx_forcedisp bit is low, then tx_dispval is ignored and the current running disparity is not altered. forcing disparity can either maintain the current running disparity calculations if the forced disparity value (on the tx_dispval bit) happens to match the current running disparity, or flip the current running disparity calculations if it does not. if the forced disparity flips the current running disparity, the down stream 8b/10b decoder may detect a disparity error which should be tolerated by the down stream device. figure 2?34 shows the current running disp arity being altered in basic single-width mode by forcing a positive disparity on a negative disparity k28.5. in this example, a series of k28.5 code groups are continuously being sent. the stream alternates between a positive ending running disparity (rd+) k28.5 and a negative ending running disparity (rd-) k28.5 as governed by the 8b/10b en coder to maintain a neutral overall disparity. the current running disparity at time n +3 indicates that the k28.5 in time n +4 should be encoded with a ne gative disparity. since the tx_forcedisp is high at time n +4, and tx_dispval is also high, the k28.5 at time n +4 is encoded as a positive disparity code group. as the tx_forcedisp is low at n +5 the k28.5 will take the current running disparity of n +4 and encode the k28.5 in time n +5 with a negative disparity. if the tx_forcedisp were driven high at time n +5, that k28.5 would also be encoded with positive disparity.
altera corporation 2?41 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?34. transmitter force dispar ity feature in single-width mode figure 2?35 shows the current running disp arity being altered in basic double-width mode by forcing a positive disparity on a negative disparity k28.5. in this example, a se ries of k28.5 are continuously being sent. the stream alternates between a positive ending running disparity (rd+) k28.5 and a negative ending running disparity (rd-) k28.5 as governed by the 8b/10b encoder to ma intain a neutral overall disparity. the current running disparity at the end of time n +2 indicates that the k28.5 at the low byte position in time n +4 should be encoded with a positive disparity. since the tx_forcedisp is high at time n +4, the signal level of tx_dispval is used to convert the lower byte k28.5 to be encoded as a negative disparity code word. as the upper bit of tx_forcedisp is low at n +4 the high byte k28.5 will take the current running disparity dictated by the low byte and encode the upper byte k28.5 with a positive disparity. if the upper bit of tx_forcedisp were driven high in time n +4, the upper byte k28.5 in time n +4 will be encoded with negative disparity. current disparity clock tx_in[7:0] tx_forcedisp bc bc bc bc bc bc bc tx_ctrlenable bc tx_out 17c 283 17c 283 283 283 17c 17c rd- rd+ rd+ rd- rd+ rd- rd+ rd- n n+1 n+2 n+3 n+4 n+5 n+6 n+7 tx_dispval
2?42 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules figure 2?35. transmitter force dispar ity feature in d ouble-width mode transmitter polarity inversion the positive and negative signals of a serial differential link might accidentally be swapped during board layout. solutions like a board re-spin or major updates to the pld logic can prove expensive. the transmitter polarity inversion feature is provided to corr ect this situation. an optional tx_invpolarity port is available in all single-width and double-width modes except (oif) cei phy to dynamically enable the transmitter polarity inversion feature. in single-width modes, a high value on the tx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the serializer in the transmitter data path. in double-width modes, a high value on the tx_invpolarity port inverts the polarity of every bit of the 16-bit or 20-bit input data word to the serializer in the transmitter data path. since inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. the tx_invpolarity is a dynamic signal and may cause initial disparity errors at the receiver of an 8b/10b encoded link. the downstream system must be able to tolerate these disparity errors. current disparity clock tx _ in [ 15 : 0 ] tx _ forcedisp [1 :0 ] bc bc bc bc bc bc bc tx _ ctrlenable [1 :0 ] bc encoded value 17c 283 17c 283 283 283 17c 17c rd - rd + rd + rd - rd+ rd- rd+ rd- nn+2n+4n+6 tx _ dispval [1:0] 01 00 00 00
altera corporation 2?43 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?36 illustrates the transmitter polarity inversion feature in a single-width 10-bit wide data path configuration. figure 2?36. transmitter po larity inversion in single-width mode 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 output from transmitter pcs input to transmitter pma to serializer tx _invpolarity = high
2?44 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules figure 2?37 illustrates the transmitter polarity inversion feature in double-width 20-bit wide data path configuration. figure 2?37. transmitter po larity inversion in double-width mode 1 0 1 0 0 0 0 0 1 1 output from transmitter pcs input to transmitter pma to serializer tx _invpolarity = high 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0
altera corporation 2?45 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview transmitter bit reversal by default, the stratix ii gx transmi tted bit order is lsbit to msbit. in single-width mode, the least significan t bit of the 8/10-bit data word is transmitted first and the most significant bit is transmitted last. in double-width mode, the least significant bit of the 16/20-bit data word is transmitted first and the most significant bit is transmitted last. the transmitter bit reversal feature a llows reversing the transmitted bit order as msbit to lsbit. if the transmitter bit reversal feature is enabled in basic single-width mode, the 8-bit d[7:0] or 10-bit d[9:0] data at the input of the serializer gets rewired to d[0:7] or d[0:9], respectively. if the transmitter bit reversal feature is enabled in basic double-width mode, the 16-bit d[15:0] or 20-bit d[19:0] data at the input of the serializer gets rewired to d[0:15] or d[0:19], respectively. flipping the parallel data using this feature and transmitting lsbit to msbit effect ively provides msbit to lsbit transmission. figure 2?38 illustrates the transmitter bit reversal feature in basic single-width 10-bit wide data path configuration. figure 2?38. transmitter bit reve rsal in single-width mode d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] d[8] d[9] output from transmitter pcs input to transmitter pma to serializer tx bit reversal = enabled
2?46 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules figure 2?39 illustrates the transmitter bit reversal feature in basic double-width 20-bit wide data path configuration. figure 2?39. transmitter bit reve rsal in double-width mode serializer the serializer block converts parallel data to serial data at the transmitter output buffer. the serializer block supports 8-bit ( figure 2?40 ), 10-bit, 16-bit, and 20-bit words. the 8-bit and 10-bit operations are for use in the single-width mode and support the data rate range from 600 mbps to 3.125 gbps. the 16-bit and 20-bit operations are for the double-width mode and support the data rate range from 1 gbps to 6.375 gbps. output from transmitter pcs input to transmitter pma to serializer tx bit reversal = enabled d[0] d[2] d[1] d[4] d[3] d[6] d[5] d[8] d[7] d[10] d[9] d[12] d[11] d[15] d[13] d[14] d[17] d[16] d[19] d[18] d[18] d[19] d[16] d[17] d[15] d[13] d[14] d[11] d[12] d[9] d[10] d[7] d[8] d[5] d[6] d[3] d[4] d[1] d[2] d[0]
altera corporation 2?47 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the serializer block drives the serial data to the ou tput buffer as shown in the figure below. the serializer block drives the serial bit-stream at a data rate range of 600 mbps to 6.375 gbps. the serializer block natively transmits the lsb of the word first. figure 2?40. serializer block in 8-bit mode figure 2?41 shows the serial bit order of the serializer block output. in this example a constant 8'h6a (01101010) va lue is serialized , and the serial data is transmitted from lsb to msb. figure 2?41. serializer bit order d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 8 low-speed parallel clock high-speed serial clock to output buffe r low-speed tx_pll_clk 01101010 01 0 0 0 1 1 1 00000000 high-speed tx_pll_clk tx_datain[7..0] tx_dataout[0]
2?48 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules in the individual channel mode, the serializer block supplies the pld and transceiver parallel clock. the serializer takes the 8 or 10 parallel clock from the clock divider block and dist ributes it to the transmitter?s pcs logic in the associated transmitter channel. in single-width mode, the clock is unaltered. in double-width mode, the serializer block creates a 16 or 20 clock from the cl ock provided by the clock divider block, depending on the serialization factor. 1 in quartus ii software version 7. 1 and later, basic single width allows 8-bit serializat ion (disable 8b/10b). transmitter buffer the stratix ii gx transmitter buffers support 1.2-v and 1.5-v pseudo current mode logic (pcml) up to 6.375 gbps and can drive 40 inches of fr4 trace across two connectors. the transmitter buffer (refer to figure 2?42 ) has additional circuitry to improve signal integrity? programmable output voltage, prog rammable three-tap pre-emphasis circuit, and internal te rmination circuitry?and the capability to detect the presence of a downstream receiver. figure 2?42. transmitter buffer programmable voltage output differential (v od ) stratix ii gx device?s allow you to cu stomize the differential output voltage (v od ) to handle different trace leng ths, various backplanes, and receiver requirements (refer to figure 2?43 ). you select the v od from a range between 200 and 1,400 mv, as shown in table 2?8 . 50 ?? , 60 , 75 50 ?? , 60 , 75 transmitter output pins programmable pre-emphasis and v od +vtt- receiver detect
altera corporation 2?49 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?43. v od (differential) signal level table 2?8 shows the differential output voltage v od setting per supply voltage for each of the on-chip tr ansmitter programmable termination values. you set the v od values in the megawizard. the transmitter buffer is powered by either a 1.2-v or a 1.5-v power supply. you choose the transmitter buffer power (v cch ) of 1.2 v or 1.5 v through the alt2gxb megawizard plug-in manager (the what is the transmit buffer power (v cch )? option). the transmitter buffer power supply in stratix ii gx devices is transceiver based. the 1.2-v power supply supports the 1.2-v pcml standard. single-ended waveform differential waveform v a v b +v od +v od -v od v od 0-v differential +700 -700 - v od (differential) = v a ? v b table 2?8. programmable v od v od differential peak to peak 1.2-v vcc 1.5-v vcc 100- (mv) 120- (mv) 150- (mv) 100- (mv) 120- (mv) 150- (mv) ? 192 240 200 240 300 320 384 480 400 480 600 480 576 720 600 720 900 640 768 960 800 960 1,200 800 960 ? 1,000 1,200 ? 960 ? ? 1,200 ? ? ? ? ? 1,400 ? ?
2?50 altera corporation stratix ii gx device handbook, volume 2 october 2007 transmitter modules you specify the v od settings either thro ugh the megawizard or dynamically using the dynamic reco nfiguration controller. refer to ?introduction? on page 2?1 for more information programmable pre-emphasis the programmable pre-emphasis module in each transmit buffer boosts the high frequencies in th e transmit data signal, which may be attenuated in the transmission media. using pr e-emphasis can maximize the data eye opening at the far-end receiver. the transmission line?s transfer function can be represented in the frequency domain as a low-pass filter. any frequency components below the ?3db frequency pass through with minimal losses. frequency components greater than the ?3db frequency are attenuated. this variation in frequency response yields data-dependent jitter and other isi effects. by applying pre-emphasis, the high frequency components are boosted, that is, pre-emphasized. pr e-emphasis equalizes the frequency response at the receiver so the difference between the low-frequency and high-frequency components are reduced, which minimizes the isi effects from the transmission medium. the pre-emphasis requirements increa se as data rates through legacy backplanes increase. the stratix i i gx transmitter buffer employs a pre-emphasis circuit with up to 477% of pre-emphasis to correct for losses in the transmission medium. you set pre-emphasis settings thro ugh a slider menu in the alt2gxb megawizard plug-in manager. specify the pre-emphasis settings (pre-emphasis control pre-tap, pr e-emphasis 1st post tap, and pre-emphasis 2nd post tap) thro ugh the megawizard or dynamically using the dynamic reconfiguration controller. to enable the dynamic reconfiguration controller, you must first enable the option for dynamic reconfiguration in the alt2gxb megawizard. after you enable that option, you must configure the se ttings in the alt2gxb_reconfig megawizard plug-in manager (stratix ii gx device family) in the quartus ii software. refer to ?introduction? on page 2?1 for more information. programmable transm itter termination the stratix ii gx transmitter buffer includes programmable on-chip differential termination of 100 , 120 , or 150 . the resistance is adjusted by the on-chip calibration circuit in the calibration block (refer to ?calibration blocks? on page 2?229 for more information), which compensates for temperature, voltage, and process changes. the stratix ii gx transmitter buffers in the transceiver are current mode
altera corporation 2?51 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview drivers, so the resultant v od is a function of the transmitter termination value. refer to ?programmable voltage output differential (vod)? on page 2?48 for more information regarding resultant v od values. you can disable the on-chip termination to use ex ternal termination. if you select external termination, th e transmitter common mode is also tri-stated. you select transmitter termination in the quartus ii software (in the assignments menu choose assignment organizer, then options for individual nodes only, and then stratix ii gx termination value). by default, the value is 100 . if you plan to use 100- termination, the quartus ii software automatically sets it during the compilation. you set the transmitter termination se tting through a pull-down menu in the alt2gxb megawizard programmable common mode you can set the common mode in stratix ii gx devices to 600 mv or 700 mv. use the 600-mv setting with the 1.2-v pcml standard. use the 700-mv setting for the 1.5-v pcml standard. table 2?9 shows the available common mode settings for 1.2-v/1.5-v v cch . pci express receiver detect the stratix ii gx transmitter buffer has a built-in receiver detection circuit for use in the pipe mode. this circuit detects if there is a receiver downstream by sending out a pulse on the common mode of the transmitter and monitoring the refl ection. this mode requires the transmitter buffer to be tri-stated (in electrical idle mode) and the use of on-chip termination and a 125 mhz fixedclk signal. table 2?9. common mode settings for the available pcml standards note (1) common mode settings 1.2-v pcml standard 1 .5-v pcml standard data rates (mbps) 600 mv vv 600 to 3125 600 mv ? v 3126 to 6375 700 mv ? v 600 to 3125 note to ta b l e 2 ? 9 : (1) the pipe protocol only allows 1.2-v pcml with 600 mv common mode. it does not allow a 1.5-v pcml and 700 mv combination.
2?52 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules this feature is only available in the pipe mode and you enable it by setting the tx_forceelecidle and tx_detectrxloopback ports to 1?b1. you must set the powerdn port to 2?b10 to plac e the transmitter in the pci-express p1 power-down state. the results of the receiver detect is encoded on the pipestatus port. pci express electrical idle the stratix ii gx transmitter buffer supports pci express electrical idle (or individual transmitter tri-state). this feature is only active in the pipe mode. the tx_forceelecidle port puts the transmitter buffer in electrical idle mode. this port is available in all pci express power-down modes and has a specific use in each mode. table 2?10 shows the usage in each power mode. receiver modules this section describes the stratix ii gx transceiver?s receiver path. this section describes the following modules: receiver buffer receiver pll clock recovery unit deserializer word aligner channel aligner (deskew) rate matcher 8b/10b decoder byte deserializer byte ordering receiver phase compensation fifo buffer table 2?10. power mode usage power mode usage p0 tx_forceelecidle must be asserted. if this signal is deasserted, it indicates that there is valid data. p1 tx_forceelecidle must be asserted. p2 when deasserted, the beacon si gnal must be transmitted. refer to ?pci express (pipe) mode? on page 2?150 .
altera corporation 2?53 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview receiver buffer the stratix ii gx receiver buffers support 1.2-v, 1.5-v, 3.3-v pcml (pseudo-current mode logic), differential lvpecl and lvds i/o standards. the receiver buffers support data rates from 600 mbps to 6.375 gbps and are capable of compensa ting up to 40 inches of fr4 trace across two connectors. the receiver buffer ( figure 2?44 ) has additional circuitry to improve signal inte grity, including a programmable equalization circuit and internal term ination circuitry. through a signal detect circuit, the receiver buffers can also detect if a signal of predefined amplitude exists at the receiver. figure 2?44. receiver buffer programmable receiver termination the stratix ii gx receiver buffer ha s an optional programmable on-chip differential termination of 100 , 120 , or 150 . you can set the receiver termination resistance setting using one of the two ways. set the receiver termination resist ance option in the megawizard if on-chip termination is used . the settings allowed are 100 , 120 , and 150 . if the design requires external receive termination, check the use external receiver termination option. you make the differential termination assignment per pin in the quartus ii software (in the assi gnments menu, choose assignment organizer, then options for in dividual nodes only, and then stratix ii gx gxb termination value). 1 verify and set the receiver termination settings before compilation. to cru signal detect 50 ? , 60 , 75 50 ? , 60 , 75 receiver input pins +vtt- programmable equalizer adaptive equalization (aeq)
2?54 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules signal threshold detection circuit the signal detect feature supporte d only in pipe mode. the signal detect/loss threshold detector senses if the specified voltage level exists at the receiver buffer. this detector has a hysteresis response, that filters out any high-frequency ringing caused by inter-symbol interference or high-frequency losses in th e transmission medium. the rx_signaldetect signal indicates if a sign al conforms to the signal detection settings. a high level indica tes that the signal conforms to the settings, a low level indicates that the signal does not conform to the settings. the signal detect levels are to be determined by characterization. the signal detect levels may vary because of changing data patterns. the signal/detect loss threshold dete ctor also switches the receiver pll/cru from lock to reference mode to lock to data mode. the lock to reference and lock to data modes di ctate whether the vco of the clock recovery unit (cru) is trained by the reference clock or by the data stream. refer to ?lock-to-reference and lock-to-data modes? on page 2?64 for more information regarding this process. you can bypass the signal/detect lo ss threshold detection circuit by choosing the forced signal detect option in the megawizard. this is useful in lossy enviro nments where the voltag e thresholds might not meet the lowest voltage threshold setting. forcing this signal high enables the receiver pll to switch from vco training based on the reference clock to the incoming data without de tecting a valid voltage threshold. receiver common mode stratix ii gx transceivers support the receiver buffer common mode voltage of 0.85 v and 1.2 v. for ac-coupled links, altera recommen ds selecting 0.85 v as the receiver buffer common mode voltage. fo r dc-coupled links, refer to ?dc coupling? on page 2?55 for recommendations on selecting the receiver common mode voltage. programmable equalization the stratix ii gx device offers an equalization circuit in each gigabit transceiver block receiver channel to increase noise margins and help reduce the effects of high-frequency losses. the programmable equalizer compensates for the high-frequency lo sses that distort the signal and reduces the noise margin of the tran smission medium by equalizing the frequency response. there are 16 equa lizer control settings allowed for a stratix ii gx device (including a settin g with no equalization). in addition
altera corporation 2?55 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview to equalization, stratix ii gx device s offer an equalizer dc gain option. there are three legal settings for dc gain. you specify the equalizer settings (equalization settings an d dc gain) either through the megawizard or dynamically using the dynamic reconfiguration controller. to enable the dynamic re configuration controller, you first enable the option for dynamic configuration in the alt2gxb megawizard plug-in manager. after you enable that option, you must configure the settings in the alt2 gxb_reconfig megawizard plug-in manager (stratix ii gx device family) in the quartus ii software. refer to ?introduction? on page 2?1 for more information. the transmission line?s transfer function can be represented in the frequency domain as a low-pass filter. any frequency components below the ?3-db frequency pass through with minimal losses. frequency components that are greater than the ?3-db frequency are attenuated. this variation in frequency response yields data-dependant jitter and other isi effects. by applying equaliz ation, the low frequency components are attenuated. this equalizes the frequency response such that the delta between the low frequency and high frequency components are reduced, which in return minimizes the isi ef fects from the transmission medium. 1 stratix ii gx receiver also offers the adaptive equalization (aeq) feature. if you enable this feature, the equalizer circuit automatically selects and adjusts appropriate equalization levels, depending on the changing link characteristics. you can enable this feature through the dynamic reconfiguration controller. for more information, refer to the stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . dc coupling a high-speed serial link can eith er be ac-coupled or dc-coupled, depending on the serial protocol bein g implemented. while most of the serial protocols require links to su pport ac-coupling, protocols like common electrical i/o (cei) op tionally allow dc coupling. in an ac coupled link, the dc blocki ng capacitor blocks the transmitter dc common mode voltage (tx v cm ). the stratix ii gx receiver buffer allows a common mo de voltage (rx v cm ) setting of 0.85 v and 1.2 v. the on-chip receiver termination and bias circuitry automatically restores the selected common mode voltage. if yo u select external termination, you must ensure that the link is terminat ed properly to the selected common mode voltage.
2?56 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules figure 2?45 shows an ac coupled link. figure 2?45. ac coupled link in a dc coupled link, the transmitter dc common mode voltage is seen unblocked at the receiver buffer. the trace common mode voltage depends on the transmitter common mode voltage and the receiver common mode voltage. the external or on-chip receiver termination and bias circuitry must ensure compatib ility between the transmitter and the receiver common mode voltage. figure 2?46 shows a dc coupled link. figure 2?46. dc coupled link trace trace transmitter receiver dc block dc block tx v cm rx v cm 50/60/75- tx termination 50/60/75- rx termination r s trace trace transmitter receiver tx v cm rx v cm 50/60/75- tx termination 50/60/75- rx termination r s
altera corporation 2?57 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the following protocols mandate ac coupled links: pci express (pipe) gigabit ethernet serial rapidio cpri xaui sdi you may choose to dc couple the hi gh-speed link for the following functional modes only: basic single and double width sonet/sdh cei the following sections discuss dc coupling requirements for a high-speed link with a stratix ii gx device used as the transmitter, receiver, or both. specifically, the following link configurations are discussed: stratix ii gx transmitter (pcml) to stratix ii gx receiver (pcml) stratix ii gx transmitter (pcml) to stratix gx receiver (pcml) stratix gx transmitter (pcml) to stratix ii gx receiver (pcml) lvds transmitter to stratix ii gx receiver (pcml) stratix ii gx transmitter (pcml) to stratix ii gx receiver (pcml) figure 2?47 shows a typical stratix ii gx to stratix ii gx dc coupled link. figure 2?47. stratix ii gx to st ratix ii gx dc coupling trace trace stratix ii gx receiver tx v cm rx v cm 50/60/75- rx termination vcch = 1.2 v/1.5 v stratix ii gx transmitter 50/60/75- tx termination 50/60/75- tx termination 0.6 v/0.7 v 50/60/75- rx termination 0.85 v r s
2?58 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules table 2?11 shows the allowed transmitter and receiver settings in a stratix ii gx to stratix ii gx dc coupled link. stratix ii gx transmitter (pcml) to stratix gx receiver (pcml) figure 2?48 shows a typical stratix ii gx to stratix gx dc coupled link. figure 2?48. stratix ii gx to stratix gx dc coupling note (1) note to figure 2?48 : (1) when dc coupling to a stratix gx receiver, you must select the enable stratix gx to stratix gx dc coupling option for the stratix gx receiver. table 2?11. settings for a stratix ii gx to stratix ii gx dc coupled link transmitter (stratix ii gx) settings receiver (stratix ii gx) settings data rate vcch (1) tx v cm (1) differential termination data rate rx v cm differential termination 600-6375 mbps 1.2 v/1.5 v 0.6 v/0.7 v 100/120/150- 600-6375 mbps 0.85 v 100/120/150- note to table 2?10 : (1) vcch = 1.2 v with tx vcm = 0.6 v can support data ra tes from 600 mbps to 3125 mbps. vcch = 1.5 v with tx vcm = 0.7 v can support data rates from 600 mbps to 3125 mbps. vcch = 1.5 v with tx vcm = 0.6 v can support data rates from 600 mbps to 6375 mbps. trace trace stratix gx receiver tx v cm rx v cm 50/60/75- rx termination vcch = 1.2 v/1.5 v stratix ii gx transmitter 50/60/75- tx termination 50/60/75- tx termination 0.6 v/0.7 v 50/60/75- rx termination 1.1 v r s
altera corporation 2?59 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview table 2?12 shows the allowed transmitter and receiver settings in a stratix ii gx to stratix gx dc coupled link. stratix gx transmitter (pcml) to stratix ii gx receiver (pcml) figure 2?49 shows a typical stratix gx to stratix ii gx dc coupled link. figure 2?49. stratix gx to st ratix ii gx dc coupling table 2?12. settings for a stratix ii gx to stratix gx dc coupled link transmitter (stratix ii gx) settings receiver (stratix gx) settings data rate vcch (1) tx v cm (1) differential termination data rate rx v cm differential termination 600-3187.5 mbps 1.5 v (1.5 v pcml) 0.6 v/0.7 v 100/120/150- 600-3187.5 mbps 1.1 v 100/120/150- note to table 2?12 : (1) vcch = 1.5 v with tx vcm = 0.7 v can support data ra tes from 600 mbps to 3125 mbps. vcch = 1.5 v with tx vcm = 0.6 v can support data rates from 600 mbps to 3187.5 mbps. trace trace stratix ii gx receiver tx v cm rx v cm 50/60/75- rx termination vcch = 1.5 v stratix gx transmitter 50/60/75- tx termination 50/60/75- tx termination 0.75 v 50/60/75- rx termination 0.85 v r s
2?60 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules table 2?13 shows the allowed transmitter and receiver settings in a stratix gx to stratix ii gx dc coupled link. lvds transmitter to stratix ii gx receiver (pcml) figure 2?50 shows a typical lvds transmitte r to stratix ii gx receiver dc coupled link. figure 2?50. lvds to stratix ii gx dc coupling table 2?14 shows the allowed transmitter an d receiver settings in a lvds to stratix ii gx dc coupled link. table 2?13. settings for a stratix gx to stratix ii gx dc coupled link transmitter (stratix gx) settings receiver (stratix ii gx) settings data rate vcch tx v cm differential termination data rate i/o standard rx v cm differential termination 600-3187.5 mbps 1.5 v 0.75 v 100/120/150- 600-3187.5 mbps 1.5 v pcml 0.85 v 100/120/150- trace trace stratix ii gx receiver rx v cm 50/60/75- rx termination lvds transmitter 50/60/75- rx termination 1.2 v r s table 2?14. settings for a lvds to stratix ii gx dc coupled link note (1) receiver (stratix ii gx) settings rx v cm differential termination r s 1.2 v 100- 88- 10% note to table 2?14 : (1) when dc coupling an lvds transmitter to the stratix ii gx receiver, use rx vcm = 1.2 v and series resistance value rs = 88- to verify compliance to the lvds specification.
altera corporation 2?61 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview receiver pll each transceiver block contains four receiver plls, which receive the reference clock to train the vco used by the cru to match the phase and frequency of the reference clock. figure 2?51 shows the block diagram for the lock-to-reference portion as the receiver pll is active. table 2?15 lists some of the pll specifications. table 2?16 lists the available /m and /l values within the receiver pll. figure 2?51. receiver pll block diagram note to figure 2?51 : (1) values of /m and /l counters are specified in table 2?16 . the quartus ii software sele cts these values automatically based on the data rate and the se lected reference clock frequencies. f this section focuses on the receiver pll in lock-to-reference mode only (the receiver is not active in lock-to- data mode). the lock-to-data mode is discussed in the section ?clock recovery unit? on page 2?63 . for information on the operation between the lock-to-reference and lock-to-data modes, refer to ?lock-to-reference and lock-to-data modes? on page 2?64 . the receiver pll has an optional lock indicator, rx_pll_locked , which indicates when the receiver pll is phase and frequency locked to the reference clock. the rx_pll_locked is an active high signal. a high signal indicates that the pll is phas e and frequency-locked to a reference clock, a low signal indicates that th e pll is not locked to the reference clock. if the cru is locked to the incoming data, the rx_pll_locked port may toggle (assert and deassert) because the phase and/or frequency differences between the recovered clock and the reference clock might be large enough to trigger a loss of lock. this is an expected behavior because the receiver pll is inactive in the lock-to-data mode rx_cruclk cp+lf up down vco /m rx_datain high-speed recovered clock low-speed recovered clock down up rx_locktorefclk rx_locktodata rx_freqlocked clock recovery unit control pfd /l 2 n 1, 2, 4 1, 2, 4 inactive circuits active circuits rx_pll_locked
2?62 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules and the rx_pll_locked signal is ignored when the cru is in lock-to-data mode. table 2?15 lists the specifications for the clock recovery unit. table 2?16 lists the available /m an d /l values within the receiver pll. clock synthesis the maximum input frequency of the receiver pll?s phase frequency detector (pfd) is 325 mhz. to achiev e a reference clock frequency above this limitation, the di vide by 2 pre-divider on the dedicated local refclk path is automatically enabled by the quartus ii software. this divides the reference clock frequency by a factor of 2, and the /m pll multiplier multiplies this pre-divided clock to yield the configured data rate. for example, in a situation with a data rate of 2,488 mbps and a reference clock of 622 mhz, the reference clock must be assigned to the refclk port where the 622-mhz reference clock can be divided by 2, yielding a 311-mhz clock at the pfd. the vco runs at half the data rate, so the selected multiplication factor shou ld yield a 1244 mhz high-speed clock. the quartus ii software automatically se lects a multiplication factor of 4 in this case to generate a 1244 mhz clock from the pre-divided 311 mhz clock. if the /2 pre-divider is used, the reference clock must be fed by a dedicated reference clock input ( refclk ) pin. otherwise the quartus ii compiler gives a fitter error. the pre-divider and the multiplication factors are automatically set by the quartus ii software. the megawizard takes the data rate input and provides a list of the available refere nce clock frequencies that fall within the supported multiplication factors that you can select. table 2?15. clock recovery unit specifications parameter specifications input reference frequency range 50 mhz to 622.08 mhz data rate support 600 mbps to 6.375 gbps table 2?16. available /m and /l values within the receiver pll rx pll reference clock source /m /l rx_cruclk 1, 4, 5, 8, 10, 16, 20, 25 1, 2, 4
altera corporation 2?63 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview ppm frequency threshold detector the ppm frequency threshold detec tor senses whethe r the incoming reference clock to the clock recovery unit (cru) and the pll vco of the cru are within a prescribed ppm tole rance range. valid parameters are 62.5, 100, 125, 200, 250, 300, 500, or 1, 000 ppm. the default parameter, if no assignments are made, is 1,000 ppm. the output of the ppm frequency threshold detector is one of the variables that assert the rx_freqlocked signal. refer to ?automatic lock mode? on page 2?64 for more details regarding the rx_freqlocked signal. receiver bandwidth type the stratix ii gx receiver pll in the cru offers a programmable bandwidth setting. the pl l bandwidth is the measure of its ability to track the input data and jitter. the bandwidth is determined by the ?3db frequency of the closed-loop gain of the pll. a higher bandwidth setting helps re ject noise from the vco and power supplies. a low bandwidth setting fi lters out more high-frequency data input jitter. valid receiver bandwidth settings are low, medium, or high. the ?3db frequencies for these settings vary be cause of the non-linear nature and data dependencies of the circuit. you can vary the bandwidth to adjust and customize the performanc e on specific systems. clock recovery unit the cru (refer to figure 2?52 ) in each stratix ii gx transceiver channel recovers the clock from the serial data stream on rx_datain . you can set the cru to automatically or manual ly lock to the data phase and frequency to match the bit transition to eliminate any clock-to-data skew or to keep the receiver pll locked to the reference clock (lock-to-data or lock-to-reference mode). the cru generates two clocks: a high-speed clock that feeds the deserializer and a slow-speed clock that feeds the rest of the receiver?s digital logic.
2?64 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules figure 2?52. clock recovery unit lock-to-reference and lock-to-data modes the lock-to-reference and lock-to-data modes describe the receiver pll and the cru. the receiver pll is active in the lock-to-reference mode and the cru is active in the lock-to-da ta mode. the switch between the two modes can be done automatically or manually. automatic lock mode the cru, by default, initially locks to the cru reference clock (lock-to-reference mode) until switch ing over to the incoming data (lock-to-data mode). the switch to lock -to-data mode is indicated by the assertion of the rx_freqlocked signal. the rx_freqlocked signal only indicates the current mode of cru (lock-to-data or lock-to-reference). after switching in to lock-to-data mode (assertion of the rx_freqlocked signal), the cru unit ne eds time to acquire phase lock to the incoming data stream. for automatic transition from th e lock-to-reference mode to the lock-to-data mode, the following conditions must be met: the serial data at the receiver inpu t buffer is within the prescribed voltage signal loss threshold. the cru pll is within the prescribed ppm frequency threshold setting (62.5, 100, 125, 200, 250, 300 , 500, or 1,000 ppm) of the cru reference clock. the reference clock and cru pll output are phase matched (phases are within approximately 0.08 ui). rx_cruclk cp+lf up down vco /m rx_datain high-speed recovered clock low-speed recovered clock down up rx_locktorefclk rx_locktodata rx_freqlocked clock recovery unit control pfd l 2 n 1, 2, 4 inactive circuits active circuits rx_pll_locked
altera corporation 2?65 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview when the receiver pll and cru is in lock-to-reference mode, the ppm detector, phase detector, and sign al-detect circuits monitor the relationship of the reference clock to the receiver pll and vco output. if the frequency difference is within the prescribed ppm setting, the amplitude is within the prescribed limits, and the phase is within 0.08 ui, then the cru switches to the lock-to-data mode. in lock-to-data mode, the pll uses a phase detector to keep the recovered clock aligned properly wi th the data. if the pll does not stay locked to data because of problems such as frequency drift or severe amplitude attenuation, the receiver pll locks back to the reference clock of the cru to train the vco. when the devi ce is in lock-to-data mode ( rx_freqlocked is asserted), the cru is tr ying to align with incoming data and there is no phase relati onship with the reference clock. the rx_freqlocked signal indicates which mode the cru is in (either lock-to-data or lock-to-reference mode). in lock-to-data mode, the rx_freqlocked signal is high. in lock-to-reference mode, the rx_freqlocked signal is low. in lock-to-data mode, the rx_freqlocked signal is asserted and the rx_pll_locked signal loses its significance because the rx_pll_locked signal indicates that th e cru has locked to the reference clock. when the cru is in lock-to-data mode, the phase of the vco may differ from the referenc e clock, which may deassert the rx_pll_locked signal. you should ignore the rx_pll_locked signal when the rx_freqlocked signal is high. in automatic lock mode, there are two conditions that force the cru to fall out of lock-to-data mode. the serial data at the receiver input buffer is not within the prescribed voltage signal loss threshold. this condition is ignored if the force signal detection option in the megawizard is enabled. the cru pll is not within the pr escribed ppm frequency threshold setting (62.5, 100, 125, 200, 250, 300, 500, or 1,000 ppm) of the cru reference clock. if the cru falls out of lock-to-data mode, the rx_freqlocked signal is deasserted. you can also deassert the rx_freqlocked signal by asserting either rx_analogreset (powers down the receiver) or gxb_powerdown (powers down all four channels of the transceiver block.
2?66 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules manual lock options two optional input pins ( rx_locktorefclk and rx_locktodata ) allow you to control whether the cr u pll automatically or manually switches between lock-to-reference mode and lock-to-data modes. this enables you to bypass the default automat ic switchover circuitry if either rx_locktorefclk or rx_locktodata is instantiated. when the rx_locktorefclk signal is asserted, it forces the cru pll to lock to the reference clock ( rx_cruclk ). asserting rx_locktodata forces the cru pll to lock to data . this occurs whether th e cru is ready or not. when both signals are asserted, the rx_locktodata signal takes precedence over the rx_locktorefclk signal. the signal loss threshol d detector, ppm threshold frequency detector, and phase relationship detector reaction times may be too long for some applications. you can manually cont rol the cru to reduce cru lock times using the rx_locktorefclk and rx_locktodata ports. using the manual mode may reduce the time it takes for the cru to switch from lock-to-reference mode to lock-to-data mode. you can assert the rx_locktorefclk to initially train the cru. the rx_locktodata signal should be asserted after training the cru. when the rx_locktorefclk signal is asserted, the rx_freqlocked signal does not have any significance because it is low, indicating that the cru is in lock-to-reference mode. if lock-to-data mode is asserted, the rx_freqlocked signal is always asserted, indicating that the cru is in lock-to-data mode. when both signals are asserted, lock-to-data mode takes precedence. if both signals are deasserted, the cru switchover is in automatic mode. table 2?17 shows a summary of the control signals. deserializer the deserializer block converts incoming high-speed serial data streams to 8-, 10-, 16-, or 20-bit-wide parall el data synchronized to the recovered clock of the cru. use the 8- and 10 -bit operations, which support a data rate from 600 mbps to 3.125 gbps, in the single-width mode. use the 16- and 20-bit operations, which su pport a data rate from 1 gbps to 6.375 gbps, for the double-width mode. table 2?17. cru user control lock signals rx_locktorefclk rx_ locktodata cru mode 1 0 lock-to-reference clock x 1 lock to data 0 0 automatic
altera corporation 2?67 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the deserializer block drives the parallel data to the pattern detector and word aligner, as shown in figure 2?53 . the deserializer block output bus data rate is the input data rate divid ed by the width of the output data bus. for example, for a 10-bit bus and a serial input data rate of 2.5 gbps, the parallel data rate is 2.5 10 or 250 mhz. the first bit into the deserializer block is the lsb of the data bus out. figure 2?53. deserializer block in 8-bit mode figure 2?54 shows the serial bit order of the deserializer block input and the parallel data out of the deserializer block. figure 2?54 shows a serial stream (01101010) deserialized into a value 8?h6a (01101010). the serial data is received lsb to msb. 1 in quartus ii software version 7. 1 and later, basic single width allows 8-bit deserializ er (disable 8b/10b). d7 d6 d5 d4 d3 d2 d1 d0 low-speed parallel clock high-speed serial clock 8 d7 d6 d5 d4 d3 d2 d1 d0 from cru to word aligne r
2?68 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules figure 2?54. deserializer bit order generic receiver polarity inversion the positive and negative signals of a serial differential link are often erroneously swapped during board layout. solutions like a board re-spin or major updates to the pld logic can prove expensive. the receiver polarity inversion feature is pr ovided to correct this situation. an optional rx_invpolarity port is available in all single-width and double-width modes except (oif) cei phy to dynamically enable the receiver polarity inversion feature. in single-width modes, a high value on the rx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the word aligner in the receiver data path. in double-width modes, a high value on the rx_invpolarity port inverts the polarity of every bit of the 16-bit or 20-bit input data word to the word aligner in the receiver data path. sinc e inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. the rx_invpolarity is a dynamic signal and may cause initial disparity errors in an 8b/10b encoded link. th e downstream system must be able to tolerate these disparity errors. the generic receiver polarity inversion feature is different from the pipe 8b/10b polarity inversion feature. the generic receiver polarity inversion feature inverts the polarity of the data bits at the input of the word aligner. the pipe 8b/10b polarity inversion feature inverts the polarity of the data bits at the input of the 8b/10b decoder and is available only in pipe mode. enabling the generic receiver polarity inversion and the pipe 8b/10b polarity inversion simultaneously is not allowed in pipe mode. low-speed rcvd_clk 01101010 01 0 0 0 1 1 1 00000000 00000000 high-speed rcvd_clk rx_datain[0] rx_dataout[7..0]
altera corporation 2?69 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?55 illustrates the receiver polarity inversion feature in single-width 10-bit wide data path configuration. figure 2?55. receiver polarity inversion in single-width mode 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 output from deserializer input to word aligner to word aligner rx _ invpolarity = high
2?70 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules figure 2?56 illustrates the receiver polarity inversion feature in double-width 20-bit wide data path configuration. figure 2?56. receiver polarity in version in double-width mode 1 0 1 0 0 0 0 0 1 1 output from deserializer input to word aligner to word aligner rx _invpolarity = high 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0
altera corporation 2?71 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview word aligner the word aligner (refer to figure 2?57 ) is part of the stratix ii gx transceiver digital blocks and is located in the receiver path between the deserializer and the de-skew fifo bu ffer. the word aligner restores the byte boundary of the upstream transmitter based on a programmable alignment pattern that appears in the serial data stream. figure 2?57. word aligner the word aligner block consis ts of four main sub-blocks: aligner block pattern detect block manual bit-slip block run-length checker there are three modes in which the word aligner works: single-width mode, double-width mode, and automatic synchronization state machine mode. the following sections explain each of the blocks in each mode of operation. the word aligner cannot be bypassed and must be used. however, you can use the rx_enapatternalign port to set the word alignment to not align to the pattern. single-width mode in single-width mode, there are three blocks active in the word aligner: pattern detector manual word aligner automatic synchronization state machine the pattern detector detects if the pattern exists in the current word boundary. the manual alignment identi fies the alignment pattern across the byte boundaries and aligns to the correct byte boundary. the synchronization state machine detect s the number of alignment patterns and good code groups for sync hronization and goes out of word aligner datain dataout bitslip enapatternalign syncstatus patterndetect clock
2?72 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules synchronization if code group errors (bad code groups) are detected. figure 2?58 and table 2?18 show the modes available in the single-width mode and the supported alignment modes. figure 2?58. word aligner components in single-width mode table 2?18. word alignment modes word alignment mode effective mode control signals status signals synchronization state machine pci express, xaui, gige, serial rapidio, cpri, or basic automatically controlled to adhere to the specified standard or by user entered parameter rx_syncstatus rx_patterndetect manual 7- and 10-bit alignment mode alignment to detected pattern when allowed by the rx_enapatternalign signal rx_enapatternalign rx_syncstatus rx_patterndetect manual 16-bit alignment mode alignment to detected pattern when allowed by the rx_enapatternalign signal rx_enapatternalign rx_syncstatus rx_patterndetect manual bit-slipping alignment mode manual bit slip controlled by the pld logic array rx_bitslip rx_patterndetect bit-slip mode 7-bit mode single-width mode synchronization state machines manual alignment mode pattern detector 16-bit mode 10-bit mode xaui mode gige mode 16-bit mode 10-bit mode 7-bit mode 10-bit mode 16-bit mode basic mode pipe mode
altera corporation 2?73 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview pattern detector module the pattern detector matches a pre- defined alignment pattern to the current byte boundary. when the patt ern detector locates the alignment pattern, the optional rx_patterndetect signal is asserted for the duration of one clock cycle to signify that the alignment pattern exists in the current word boundary. the pattern detector module only indicates that the signal exists and does not modify the word boundary. modification of the word boundary is discussed in the sections ?manual alignment modes? on page 2?75 and ?synchronization state machine mode? on page 2?81 . in the megawizard, you can program a 7-bit, 10-bit, or 16-bit pattern for the pattern detector to recognize. th e pattern used for pattern matching is automatically derived from th e word alignment pattern in the megawizard. for the 7-bit and 10-bi t patterns, the actual alignment pattern specified in the megawizard and its complement are checked. for the 16-bit alignment pattern, only the actual pattern is checked. table 2?19 shows the supported alignment patterns. 1 in 8b/10b encoded data, actual and complement pattern indicates positive and negative disparities. each bit in the rx_patterndetect and rx_syncstatus signal indicates the status of the gr oup of 8 or 10 bits in the rx_dataout port. for the rx_dataout width of 8/10, 16/20, and 32/40 bits, the rx_patterndetect and rx_syncstatus widths are 1, 2, and 4 bits, respectively. an example of corresponding signals for rx_dataout (widths of 16 and 32) is shown in table 2?20 . table 2?19. supported alignment patterns pattern detect mode supported protocols pattern checked 7 bit basic, cpri actual and complement 10 bit basic, xaui, gige, cpri, serial rapidio, and pipe actual and complement two consecutive 8-bit characters sonet/sdh actual table 2?20. corresponding signals for rx_dataout (part 1 of 2) data width signal corresponding signal 16 rx_patterndetect[1] rx_dataout[15:8] rx_patterndetect[0] rx_dataout[7:0]
2?74 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules 7-bit pattern mode in the 7-bit pattern detection mode (use this mode with 8b/10b code), the pattern detector matches the seven ls bs of the 10-bit alignment pattern, which you specified in your alt2gxb custom megafunction variation, in the current word boundary. both positive and negative disparities are also checked in this mode. the 7-bit pattern mode can mask out the three msbs of the data, which allows the pattern detector to recognize multiple alignment patterns. for example, in the 8b/10b encoded data, a /k28.5/ (b'0011111010), /k28.1/ (b'0011111001), and /k28.7/ (b'0011111000) share seven common lsbs. masking the three msbs allows the pattern detector to resolve all three alignment patterns and indicate them on the rx_patterndetect port. in 7-bit pattern mode, the word al igner still aligns to a 10-bit word boundary. the specified 7-bit pattern forms the least significant seven bits of the 10-bit word. 10-bit pattern mode in the 10-bit pattern detection mode (use this mode with 8b/10b code), the module matches the 10-bit alignment pattern you specified in your alt2gxb custom megafunction variation with the data and its complement in the current word boundary. both positive and negative disparities are checked by the pattern checker in this mode. for example, if you specify a /k28.5/ (b?0011111010) pattern as the comma, rx_patterndetect is asserted if b?0011111010 or b?1100000101 is detected in the incoming data. 16-bit pattern mode you specify the 16-bit alignment pattern in the megawizard and it is oriented with the msb first and the lsb last. a1 represents the least significant byte, which consists of bits [7..0] . a2 represents the most significant byte, which consists of bits [15..8] . therefore, the alignment pattern is specified as [a2,a1] in the megawizard. only the actual alignment pattern specified in the megawizard is detected in this mode. 32 rx_patterndetect[3] rx_dataout[31:24] rx_patterndetect[2] rx_dataout[23:16] rx_patterndetect[1] rx_dataout[15:8] rx_patterndetect[0] rx_dataout[7:0] table 2?20. corresponding signals for rx_dataout (part 2 of 2) data width signal corresponding signal
altera corporation 2?75 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the pattern detector is defaulted to the a1a2 mode. only the positive disparity is detected in this mode. manual alignment modes the word aligner has three manual a lignment modes (7-, 10-, and 16-bits) when the transceiver data path is in single-width mode. the 10- and 7-bit alignment modes are used with 8b/1 0b code and the 16-bit alignment mode is for scrambled or non-scrambled data. 7-bit alignment mode in the 7-bit alignment mode (use th e 8b/10b encoded data with this mode), the module looks for the 7-bi t alignment pattern you specified in the megawizard plug-in manager in the incoming data stream. the 7-bit alignment mode is useful because it can mask out the three most significant bits of the data, which allows the word aligner to align to multiple alignment patterns. for example, in the 8b/10b encoded data, a /k28.5/ (b'0011111010), /k28.1/ (b'0011111001), and /k28.7/ (b'0011111000) share seven common lsbs. masking the three msbs allows the word aligner to resolve all thr ee alignment patterns synchronized to it. the word aligner places the boundary of the 7-bit pattern in the lsbyte position with bit positions [0..7] . the true and complement of the patterns is checked. use the rx_enapatternalign port to enable the 7-bit manual word alignment mode. when the rx_enapatternalign signal is high, the word aligner detects the specified alignment patterns and realigns the byte boundary if needed. the rx_syncstatus port is asserted for one parallel clock cycle to signify that th e word boundary was detected across the current word boundary and has synchronized to the new boundary, if a rising edge was detected previously on the rx_enapatternalign port. you must differentiate if the ac quired byte bounda ry is correct, because the 7-bit pattern can appear between word boundaries. for example, in the standard 7-bit alignm ent pattern -7'b1111100, if a k28.7 is followed by a k28.5, the 7-bit a lignment pattern appears on k28.7, between k28.7 and k28.5, and also again in k28.5 (refer to figure 2?59 ). figure 2?59. cross boundary 7-bit comma when /k28.7 is followed by /k28.5 0 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 k28.7 k28.5 7-bit comma- 7-bit comma+ 7-bit comma-
2?76 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules manual 10-bit alignment mode you can configure the word aligner to align to a 10-bit word boundary. the internal word alignment circuitry shifts to the correct word boundary if the alignment pattern specified in the pattern detector is detected in the data stream. the rx_enapatternalign port enables the word alignment in the manual 10-bit alignment mode. when the rx_enapatternalign signal is high, the word aligner detects the specified alignment pattern and realigns the byte boundary if necessary. the rx_syncstatus port is asserted for one parallel clock cycle to signify that the word boundary has been detected across the word bo undary and has synchronized to the new boundary. the rx_enapatternalign signal is held high if the alignment pattern is known to be unique and does not a ppear across the byte boundaries of other data. for example, if an 8b/10b encoding scheme guarantees that the /k28.5/ code group is a unique pattern in the data stream, the rx_enapatternalign port is held at a constant high. if the alignment pattern can exis t between word boundaries, the rx_enapatternalign port must be controlled by the user logic in the pld to avoid false word alignment. fo r example, assume that 8b/10b is used and a /+d19.1/ (b'110010 1001) character is specified as the alignment pattern. in this case, a false word boundary is detected if a /-d15.1/ (b'010111 1001) is followed by a /+d18.1/ (b'010011 1001). refer to figure 2?60 . figure 2?60. false word boundary alignment if alignment pattern exists across word boundaries, single width in this example, the rx_enapatternalign signal is deasserted after the word aligner locates the initial word alignment to prevent false word boundary alignment. when the rx_enapatternalign signal is deasserted, the current word boundary is locked even if the alignment pattern is detected across differ ent boundaries. in this case, the rx_syncstatus acts as a re-synchronizatio n signal to signify that the ?.. ?.. 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 - d15.1 +d18.1 +d19.1
altera corporation 2?77 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview alignment pattern was detected, but th e boundary is different than the current boundary. you must monitor this signal and reassert the rx_enapatternalign signal if realignment is desired. figure 2?61 shows an example of how the wo rd aligner signals interact in 10-bit alignment mode. in this exam ple, a /k28.5/ (10'b0011111010) is specified as the alig nment pattern. the rx_enapatternalign signal is held high at time n , so alignment occurs when ever a alignment pattern exists in the pattern. the rx_patterndetect signal is asserted for one clock cycle to signify that the pattern exists on the re-aligned boundary. the rx_syncstatus signal is also asserted for one clock cycle to signify that the boundary has been synchronized. at time n + 1, the rx_enapatternalign signal is deasserted to instruct the word aligner to lock the current word boundary. the alignment pattern is detected at time n + 2, but it exists on a different boundary than the curren t locked boundary. the bit orientation of the stratix ii gx device is lsb to msb, so the alignment pattern exists across time n + 2 and n + 3 (refer to figure 2?61 ). in this condition the rx_patterndetect remains low because the alignment pattern does not exist on the current word boundary, but the rx_syncstatus signal is asserted for one clock cycle to signify a resynchronization condition. this means that the alignment pattern has been detected across another word boundary. the user logic design in the pld must decide whether or not to assert the rx_enapatternalign to re-initiate the word alignment process. at time n + 5 the rx_patterndetect signal is asserted for one clock cycle to signify that the alignment pattern has been detected on the current word boundary. figure 2?61. word aligner symbol intera ction in 10-bit m anual alignment mode rx_clkout rx_enapatternalign rx_patterndetect rx_syncstatus rx_dataout[10..0] 111110000 0101111100 111110000 111110000 1000000101 0101111100 1111001010 n n + 1 n + 2 n + 3 n + 4 n + 5
2?78 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules manual sonet/sdh alignment mo de (two consecutive 8-bit characters (a1a2) or four consec utive 8-bit charac ters (a1a1a2a2)) the word aligner can be configured to align to a 16-bit word boundary in sonet/sdh protocol mode. in the sonet/sdh protocol mode, the word aligner either aligns to two cons ecutive 8-bit characters (a1a2) or four consecutive 8-bit ch aracters (a1a1a2a2). the rx_a1a2size signal can be used to differentiate between the two and four consecutive modes. the word aligner aligns to the a1a2 pattern when the rx_a1a2size signal is held low ?0,? or to the a1a1a2a2 when rx_a1a2size is high ?1.? the rx_a1a2sizeout port sends the state of the rx_a1a2size signal as seen by the word alig ner back to the pld logic array. word alignment is enabled or re-enabled by the rx_enapatternalign signal, but the behavior is different than that described for the 7-bit or 10-bit manual mode in single-width configuration. in the 7/10-bit mode the byte boundary can be dynamically changed if the rx_enapatternalign signal is held high. however, in the sonet/sdh mode the byte boundary is locked after the first alignment pattern is detected and aligned after the rising edge of the rx_enapatternalign signal. if the byte boundary changes, the rx_enapatternalign signal must be deasserted and reasserted to re-enable the alignment circuit. this feature is valuable in sonet/sdh because the data is scrambled and not encoded. the alignment pattern can potentially exist across byte boundaries and can trigger a false realignment. in sonet/sdh the byte boundary should be aligned and locked at the beginning of a sonet/sdh frame since the a1a2 alignment pattern resides in the framing section at the beginning of the transport overhead. initially, the word aligner locks onto the first alignment pattern detected. in this scenario the rx_patterndetect signal is asserted for one clock cycle to signify that th e alignment pattern has been aligned. the rx_syncstatus signal is asserted for a cl ock cycle to signify that the word boundary has been synchronized. after the word boundary has been locked, regardless of whether the rx_enapatternalign signal is held high or low, the rx_syncstatus signal asserts for one clock cycle whenever the alignment pattern is detected across a different byte boundary. the rx_syncstatus signal operates in this resynchronization state until a rising edge is detected on rx_enapatternalign . figure 2?62 shows an example of how the wo rd aligner signals interact in sonet/sdh alignment mode for an a1 a2 pattern. for this example, a sonet/sdh a1a2 framing pattern uses 16'hf628 (16'b1111011000101000) with the reverse bi t ordering. this option reverses
altera corporation 2?79 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the bit order so that the data can be transmitted and received msb to lsb. if the bit reversal option in the me gawizard plug-in mana ger is not used, the transceiver transmits and receives lsb to msb. figure 2?62. word aligner symbol interaction in sonet/sdh a1a2 manual alignment mode the rx_a1a2size signal is held low, which sets the sonet/sdh alignment mode to a1a2. the rx_enapatternalign signal is toggled high at time n , so the aligner locks to the boundary of the next present alignment pattern. the a1a2 al ignment pattern appears on the rx_dataout port during this period. the alignment pattern exists, so the rx_patterndetect and rx_syncstatus signals are asserted for one clock cycle to signify that the a1a2 alignment pattern has been detected and the word boundary has been lo cked. the a1a2 alignment pattern appears again across word boundaries in during periods n +1, and n +2. the rx_enapatternalign signal is held high, but the word aligner does not re-align the byte boundary as it would in 10-bit manual alignment mode. instead the rx_syncstatus signal is asserted for one clock cycle to signify a re-synchronization condition. you must deassert and reassert the rx_enapatternalign signal to re-trigger the word aligner and align on the next alig nment pattern. the next transition occurs at time n +3, where rx_enapatternalign is deasserted and the a1a2 pattern is present on the rx_dataout port. the word aligner then asserts the rx_patterndetect signal for one clock cycle to flag the detection of the alignment pattern on the current word boundary. manual 16-bit alignment mode you enable the 16-bit alignment mode in the single-width mode. this mode aligns to the 16-bit alignment pattern you specified in the megawizard. rx_clkout rx_enapatternalign rx_patterndetect rx_syncstatus rx_out 11110110 00101000 11111111 11110110 10000000 00101000 01100010 nn+1n+2n+3 rx_a1a2size 01000110
2?80 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules the byte boundary is locked after th e first alignment pattern is detected and after the rising edge of the rx_enapatternalign port. if the byte boundary changes, the rx_enapatternalign port is deasserted and reasserted to enable the alignment ci rcuit to search for and align to the next available alignment pattern. on the rising edge of the rx_enapatternalign port, the word aligner locks onto the first alignment patt ern detected. in this scenario, rx_patterndetect is asserted to signify th at the alignment pattern has been aligned. the rx_syncstatus signal is also asserted for one clock cycle to signify that the word bounda ry has been synchronized. after the word boundary is lo cked, whether or not rx_enapatternalign is held high or low, the rx_syncstatus signal asserts for one clock cycle whenever the alignment pattern is detected across a different byte boundary. the rx_syncstatus signal operat es in this resynchronization state until a ri sing edge is detected on the rx_enapatternalign port. manual bit-slip alignment mode you can also achieve word alignment by enabling the manual bit-slip option in the megawizard. with this op tion enabled, the transceiver shifts the word boundary msb to lsb one bi t every parallel clock cycle. the transceiver shifts the word boundary every time the bit-slipping circuitry detects a rising edge of the rx_bitslip signal. at each rising edge of the rx_bitslip signal, the word boundary slip s one bit. the bit that arrives at the receiver first is skipped. when the word boundary matches the alignment pattern you specified in the megawizard, the rx_patterndetect signal is asserted for one clock cycle. you must implement the logic in the pld logic a rray to control the bit-slip circuitry. the bit slipper is useful if the a lignment pattern ch anges dynamically when the stratix ii gx device is in user mode. you can implement the controller in the logic array, so you can build a custom controller to dynamically change the alignment pa ttern without needing to reprogram the stratix ii gx device. figure 2?63 shows an example of how the wo rd aligner signals interact in the manual bit-slip al ignment mode. fo r this example, 8?b00111100 is specified as the alignment pattern an d an 8?b11110000 value is held at the rx_datain port. every rising edge on the rx_bitslip port causes the rx_dataout data to shift one bit from the msb to the ls b by default. this is shown at time n + 2 where the 8?b11110000 data is shifted to a value of 8?b01111000. at this state the rx_patterndetect signal is held low because the specified alignment pattern does not exist in the current word boundary.
altera corporation 2?81 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the rx_bitslip is disabled at time n + 3 and re-enabled at time n + 4. the output of the rx_dataout now matches the specified alignment pattern, thus the rx_patterndetect signal is asserted for one clock cycle. at time n + 5, the rx_patterndetect signal is still asserted because the alignment pattern still ex ists in the current word boundary. finally, at time n + 6 the rx_dataout boundary is shifted again and the rx_patterndetect signal is deasserted to signify that the word boundary does not contai n the alignment pattern. figure 2?63. word aligner symbol inte raction in manual bit-slip mode synchronization state machine mode in single-width mode, you can choos e to have the link synchronization handled by a state machine. unlike the manual alignment mode where there is no built-in hysteresis to go into or fall out of synchronization, the synchronization state machine offers automatic detection of a valid number of alignment patterns and sync hronization and detection of code group errors for automatically falli ng out of synchronization. the synchronization state machine is available in the basic (single-width mode only), xaui, gige, and pipe modes. for the xaui, gige, and pipe modes, the number of alignmen t patterns, consecutive code groups, and bad code groups are fixed. you must use the 8b/10b code for the synchronization state machine. in xaui, gige, and pipe modes, the 8b/10b encoder/decoder is embedded in the transceiver data path. in basic single-width mode, you can configure the megawizard to either use or bypass the 8b/10b encoder/deco der in the transceiver. if the synchronization state machine is enabled and the 8b/10b encoder/decoder is bypassed, the 8b /10b encoder/decoder logic must be implemented outside the transceiver as a requirement for using the synchronization state machine. rx_clkout rx_datain rx_dataout[7..0] rx_bitslip rx_patterndetect n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 11110000 01111000 00111100 00011110 00001111
2?82 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules in basic mode, you can configure the state machine to suit a variety of standard and custom pr otocols. in the megawizard, you can program the number of alignment pa tterns to acquire link sy nchronization. you can program the number of bad code groups to fall out of synchronization. you can program the number of good code groups to negate a bad code group. you enter these valu es in the megawizard. the rx_syncstatus port indicates the link status. a high level indicates link synchronization is achieved, a low level indicates th at synchronization has not yet been achieved or that there were enough code group errors to fall out of synchronization. figure 2?64 shows a flowchart of the synchronization state machine.
altera corporation 2?83 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?64. word aligner synchroniza tion state machine flow chart the maximum value for the number of valid alignment patterns and good code groups is 256. the maxi mum value of invalid or bad code groups to fall out of synchronization is 8. for example, if 3 is set for the number of good code groups, then wh en 3 consecutive good code groups are detected after a bad code group, the effect of the bad code group on synchronization is negated. this does not negate the bad code group that actually triggers the loss of sync hronization. to negate a loss of synchronization, the protocol-defin ed number of alignment patterns must be received. comma detect if data == comma kcntr++ else kcntr=kcntr loss of sync data= !valid data= comma data=valid; kcntr 2?84 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules when either xaui or gige mode is used, the synchronization and word alignment is handled automatically by a built-in state machine that adheres to either the ieee 802.3ae or ieee 802.3 synchronization specifications, respectively. if you sp ecify either standard, the alignment pattern is automatically defaulted to /k28.5/ (b'0011111010). when you specify the xaui protocol , code-group synchronization is achieved upon the reception of fo ur /k28.5/ commas. each comma can be followed by any number of valid code groups. invalid code groups are not allowed during the synchronization stage. when code-group synchronization is achieved the optional rx_syncstatus signal is asserted. refer to clause 47-48 of the ieee p802.3ae standard or ?xaui mode? on page 2?167 for more information regarding the operation of the synchronization phase. if you specify the gige protocol, code -group synchronization is achieved upon the reception of three consecutive ordered sets. an ordered set starts with the /k28.5/ comma and can be followed by an odd number of valid data code groups. invalid code groups are not allowed during the reception of three ordered-sets. wh en code-group synchronization is achieved the optional rx_syncstatus signal is asserted. in pipe mode, lane sync hronization is ac hieved when the word aligner sees 4 good /k28.5/ commas and 16 good code groups. this is accomplished through the reception of 4 good pci express training sequences (ts1 or ts2). the pci-expres s fast training sequence (fts) can also be used to achieve lane or link synchronization, but requires at least five of these training sequences. the rx_syncstatus signal is asserted when synchronization is achieved and is deasserted when the word aligner receives 23 code group errors. double-width mode in the double-width mode, there ar e two blocks active in the word aligner: the pattern detector and manual alignment mode. the pattern detector detects if the pattern exists in the current word boundary. the manual alignment identifies the al ignment pattern across the byte boundaries and aligns to the corr ect byte boundary. there are no synchronization state machines available for the double-width mode.
altera corporation 2?85 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?65. word aligner com ponents, double-width mode pattern detector module the pattern detector matches a pre- defined comma to the current word boundary. if the pattern detector loca tes the correct alignment pattern, the optional rx_patterndetect signal is asserted for the duration of one clock cycle to signify that the alignmen t pattern exists in the current word boundary. the pattern detector module only indicates that the signal exists and does not modify the word boundary. you can program and then specify in th e megawizard a 7-bit, 8-bit, 10-bit, 16-bit, 20-bit, or 32-bit, pattern for the pattern detector to recognize in double-width mode. for the 7-bit, 10-bi t, and 20-bit patterns, the actual and complement of the alignment pa tterns are checked and used with 8b/10b coding. for the 8-bit, 16-bit, and 32-bit alignment patterns, only the actual patterns are checked, not the complements. these patterns are used for scrambled coding or non-encoded data. 7-bit pattern mode in the 7-bit pattern detection mode , the pattern detector matches the seven least significant bits of the 10-bi t alignment pattern in the lsbyte as specified in the megawizard in the current word boundary. the pattern detector checks both po sitive and negative dispa rities in this mode. the 7-bit pattern mode can mask out th e three most significant bits of the data, which allows the pattern detec tor to recognize multiple alignment patterns. for example, in the 8b/10b encoded data, a /k28.5/ (b?0011111010), /k28.1/ (b?0011111001), and /k28.7/ (b?0011111000) share seven common lsbs, so masking th e three msbs allows the pattern double-width mode pattern detector and manual alignment mode 7-bit mode 32-bit mode 16-bit mode 8-bit mode 20-bit mode 10-bit mode
2?86 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules detector to resolve all three alignmen t patterns and indicate it on the rx_patterndetect port. if the alignment pattern appears on the msbyte, no actions are taken by the pattern detect module. 8-bit pattern mode you can enable a single 8-bit characte r (a1) detection in the megawizard. in this mode, the pattern detector de tects a single 8-bit alignment pattern character in the lsbyte of the data path. if the alignment pattern appears in the msbyte, no action is taken by the pattern detector. 10-bit pattern mode in the 10-bit pattern detection mode, the pattern detector matches the 10-bit alignment pattern you specifie d in the megawizard to the lsbyte data and its complement in the cu rrent word boundary. the pattern detector checks both posi tive and negative dispari ties in this mode. for example, if you specified a /k28.5/ (b'0011111010) pattern as the alignment pattern, the rx_patterndetect signal is asserted if b?0011111010 or b?1100000101 is detected in the incoming data. if the alignment pattern appears on the ms byte, no action is taken by the pattern detector. 16-bit pattern mode you enable the two consecutiv e 8-bit characters (a1a2). you specify the 16-bit alignment patter n, which has the bit orientation of [msb..lsb] , in the megawizard. a1 repr esents the least significant byte, which consists of bits [7..0] . a2 represents the most significant byte, which consists of bits [15..8] . therefore, the alignment pattern is specified as [a2,a1] in the megawi zard. only the actual alignment pattern you specified in the megawizard is detected in this mode. 20-bit pattern mode in the 20-bit pattern detection mode, the pattern detector matches the 20-bit comma (k1k2) you specified in the megawizard to the incoming data stream. the pattern detector checks the true and complement of the pattern. for example, if you specify a /k28.5/ and /k28.0/ (10?b0011111010, 10?b0011110100) patter n as the alignment pattern, the rx_patterndetect signal is asserted if 10?b0011111010 or 10?b1100000101 and 10?b0011110100 or 10?b1 100001011 are detected in the incoming data. you do not need to enter the correct disparity in the megawizard, because the true and complement of each code group is checked. in this mode, only kx.y codes are used as the true and complement to represent the same code group (but different disparity). the dx.y code group does not necessarily use its true and complement to represent the same code group.
altera corporation 2?87 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 32-bit pattern mode you enable the four consecutiv e 8-bit character (a1a2a3a4 or a1a1a2a2) detection in the megawizard. you specify the 32-bit alignment pattern in the megawizard and it is oriented with the msb first and the lsb last. a1 represents the least significant byte, which consists of bits [7..0] . a4 represents the most signif icant byte, which consists of bits [31..24] . therefore, the alignment pattern is specified as [a4,a3,a2,a1] in the megawizard. on ly the actual alignment pattern you specified in the megawizard is detected in this mode. manual alignment modes the word aligner has six manual alig nment modes (7-, 8- 10-, 16-, 20- and 32-bits) when the transceiver data path is in double-width mode. the 7-, 10-, and 20-bit alignment modes are used with 8b/10b encoded data. both the actual and complement of the alignment pattern are checked for these modes. the 8-, 16-, and 32-bit al ignment modes are for scrambled or non-scrambled data. only the actual alignment pattern is checked for these modes. manual 7-bit alignment mode in the 7-bit alignment mode (use th e 8b/10b encoded data with this mode), the module looks for the 7-bi t alignment pattern you specified in the megawizard plug-in manager in the incoming data stream. the 7-bit alignment mode is useful because it can mask out the three most significant bits of the data, which allows the word aligner to align to multiple alignment patterns. for example, in the 8b/10b encoded data, a /k28.5/ (b'0011111010), /k28.1/ (b'0011111001), and /k28.7/ (b'0011111000) share seven common lsbs. masking the three msbs allows the word aligner to resolve all thr ee alignment patterns synchronized to it. the word aligner places the boundary of the 7-bit pattern in the lsbyte position with bit positions [0..7] . the true and complement of the patterns is checked. in 7-bit manual word alignment mode, the word aligner looks for the 7-bit alignment pattern after detect ing a rising edge on the rx_enapatternalign signal. on finding th e alignment pattern, the word aligner locks the word boundary and asserts the rx_syncstatus signal. the rx_syncstatus signal remains high until it sees another rising edge on the rx_enapatternalign . after detecting a rising edge on the rx_enapatternalign signal, the word aligner starts looking for the 7-bit word alignment pa ttern again and asserts the rx_syncstatus signal once it finds the 7-bit alignment pattern. yo u must differentiate if the acquired byte boundary is corr ect, because the 7-bit pattern can appear between word boundaries. fo r example, in the standard 7-bit
2?88 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules alignment pattern -7'b1111100, if a k28. 7 is followed by a k28.5, the 7-bit alignment pattern appears on k28.7, between k28.7 and k28.5, and also again in k28.5 (refer to figure 2?66 ). figure 2?66. cross boundary 7-bit comma when /k28.7 is followed by /k28.5 manual 8-bit alignment mode you can enable the 8-bit alignment mode in the double-width mode. this mode aligns to the 8-bit alignmen t pattern you specified in the megawizard. the byte boundary is locked after th e first alignment pattern is detected and after the rising edge of the rx_enapatternalign signal. the detected pattern is placed in the ls byte of the 16-bit word. if the byte boundary changes, the rx_enapatternalign port must be deasserted and reasserted to enable the alignmen t circuit to search for and align to the next available alignment patter n. on the rising edge of the rx_enapatternalign signal, the word aligner locks onto the first alignment pattern detected and places the detected pattern in the data stream on the lsbyte posi tion. in this scenario, rx_patterndetect is asserted to signify that the alignm ent pattern has been aligned. the rx_syncstatus signal is also asserted to signify that the word boundary has been synchronized. manual 10-bit alignment mode you can configure the word aligner to align to a 10-bit word boundary. the internal word alignment circuitry shifts to the correct word boundary if the alignment pattern you specified in the pattern detector is detected in the data stream. the word aligner then puts the alignment pattern in the lsbyte of the data path. in 10-bit manual word alignment mo de, the word aligner looks for the 10-bit alignment pattern after de tecting a rising edge on the rx_enapatternalign signal. on finding th e alignment pattern, the word aligner locks the word boundary and asserts the rx_syncstatus signal. the rx_syncstatus signal remains high until it sees another rising edge on the rx_enapatternalign . after detecting a rising edge 0 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 k28.7 k28.5 7-bit comma- 7-bit comma+ 7-bit comma-
altera corporation 2?89 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview on the rx_enapatternalign signal, the word aligner starts looking for the 10-bit word alignment pattern again and asserts the rx_syncstatus signal once it finds the 10 -bit alignment pattern. the rx_enapatternalign port only operates in an edge-sensitive fashion in double-width mode. you must deassert the rx_enapatternalign signal and assert it again for re-ali gnment. altera recommends using the /k28.5/ code group as one of the control codes for this alignment pattern. for example, assume th at 8b/10b coding is used and a /+d19.1/ (b'110010 1001) character is specified as the alignment pattern. in that case, a false word boundary is detected if a /-d15.1/ (b'010111 1001) is followed by a /+d18.1/ (b'010011 1001). refer to figure 2?67 . figure 2?67. false word boundary alignment if alignment pattern exists across word boundaries, double width if there is no rising edge on the rx_enapatternalign port, the current word boundary is locked, even if the alignment pattern is detected across different boundaries. figure 2?68 shows an example of how the wo rd aligner signals interact in 10-bit alignment mode. for this exampl e, a /k28.5/ (10'b0011111010) is specified as the alig nment pattern. the rx_enapatternalign signal is as a rising edge at time n , alignment occurs whenever an alignment pattern exists in the pattern. the rx_patterndetect signal is asserted for one clock cycle to signify that th e pattern exists on the re-aligned boundary. the rx_syncstatus signal also gets as serted to signify that the boundary has been synchronized. at time n + 1, the rx_enapatternalign signal is deasserted an d no rising edge occurs, which instructs the word aligner to lo ck the current word boundary. the alignment pattern is detected at time n + 2, but it exists on a different boundary than the curr ent locked boundary. figure 2?68 shows that the alignment pattern ex ists across time n + 1 and n + 2. in this condition the rx_patterndetect signal remains low beca use the alignment pattern does not exist on the current word bo undary. it is up to the user logic to decide whether or not to assert the rx_enapatternalign signal to re-initiate the word alignment process. at time n + 3, the rx_patterndetect signal is asserted for one clock cycle to signify that ?.. ?.. 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 - d15.1 +d18.1 +d19.1
2?90 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules the alignment pattern has been detect ed on the lsbyte of the current word boundary. if the pattern exists on the msbyte, the rx_syncstatus signal goes high. figure 2?68. word aligner symbols intera cting in 10-bit manual alignment mode manual 16-bit alignment mode you can enable the 16-bit alignment mode in the double-width mode. this mode aligns to the 16-bit alig nment pattern you specified in the megawizard. the byte boundary is locked after the pattern detector detects the first alignment pattern and then af ter the rising edge of the rx_enapatternalign port. if the byte boundary changes, the rx_enapatternalign port must be deasserted and reasserted to enable the alignment circuit to search for and align to the next available alignment pattern. on th e rising edge of the rx_enapatternalign signal, the word aligner locks onto the first alignment patte rn detected. in this scenario the rx_patterndetect signal is asserted to signify that the alignment pattern has been aligned. the rx_syncstatus signal is also asserted to signify that the word boundary has been synchronized. manual 20-bit alignment mode in the 20-bit alignment mode, the pa ttern detector looks for the 20-bit alignment pattern (k1k2) you specified in the megawizard in the incoming data stream. the pattern detector checks the true and complement of the pattern. for example, if you specified a /k28.5/ and /k28.0/ (10'b0011111010, 10'b00111 10100) pattern as the alignment pattern, the byte boundary is set to the pattern boundary when 10'b0011111010 or 10'b1100000101 and 10'b0011110100 or 10'b1100001011 are detected in the incoming data. it is not necessary to enter the correct disparity in the megawizard because the true and complement of each code group is checked automatically by the pattern detector. do not use dx.y codes as the alignment pattern in the 20-bit alignment mode. rx_clkout rx_enapatternalign rx_patterndetect rx_syncstatus rx_datain[15..0] 111110000 0101111100 111110000 111110000 1000000101 0101111100 1111001010 n n + 1 n + 2 n + 3 0101010101
altera corporation 2?91 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview in 20-bit manual word alignment mo de, the word aligner looks for the 20-bit alignment pattern after de tecting a rising edge on the rx_enapatternalign signal. on finding th e alignment pattern, the word aligner locks the word boundary and asserts the rx_syncstatus signal. the rx_syncstatus signal remains high until it sees another rising edge on the rx_enapatternalign . after detecting a rising edge on the rx_enapatternalign signal, the word aligner starts looking for the 20-bit word alignment pattern again and asserts the rx_syncstatus signal once it finds the 20 -bit alignment pattern. the rx_enapatternalign port can only operate in an edge-sensitive fashion in double-width mode. deassertion of the rx_enapatternalign port is necessary for realignment. altera recommends that you include the /k 28.5/ code group as one of the control codes in this alignment pattern. manual 32-bit alignment mode you can enable the 32-bit alignment mode in the double-width mode only. this mode aligns to the 32-bit al ignment pattern you specified in the megawizard. the byte boundary is locked after th e first alignment pattern is detected and then after the rising edge of the rx_enapatternalign port. if the byte boundary changes, the rx_enapatternalign port must be deasserted and reasserted to enable the alignment circuit to search for and align to the next available alignmen t pattern. on the rising edge of rx_enapatternalign , the word aligner locks onto the first alignment pattern detected. in this scenario, the rx_patterndetect is asserted to signify that the alignment pattern has been aligned. the rx_syncstatus signal is asserted to signif y that the word boundary has been synchronized. manual bit-slipping alignment mode in the double-width mode, word alignm ent is also achieved by enabling the manual bit-slip opti on in the megawizard. this mode operates the same way as the bit slip in the si ngle-width mode. with this option enabled, the transceiver shifts the word boundary one bit from the msb to the lsb every parallel clock cycl e. this occurs every time the bit-slipping circuitry dete cts a rising edge of the rx_bitslip signal. at each rising edge of rx_bitslip , the word boundary slips one bit. the bit that arrives at the receiver first is skipped. when the word boundary matches what you specified as the al ignment pattern in the megawizard, the rx_patterndetect signal is asserted for one clock cycle. you must implement the logic in the pld logic a rray to control the bit-slip circuitry.
2?92 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules run-length violation detection circuit the programmable run-length violation circuit resides in the word aligner block and detects consecutive 1s or 0s in the data. if the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv signal. this signal is not synchronized to the parallel data and appears in the logic array earlier than the run-length violation data. to ensure that the pld can latch this signal in systems where there are frequency variations between the recovered clock and the pld logic array clock, the rx_rlv signal is asserted for a minimum of two clock cycles in single-width modes and a minimum of three clock cycles in double-width modes. the rx_rlv signal may be asserted longer, depending on the run-length of the received data. in single-width mode, the run-length violation circuit detects up to a run length of 128 (for an 8-bit deserial ization factor) or 160 (for a 10-bit deserialization factor). th e settings are in increments of 4 or 5 for the 8-bit or 10-bit deserialization factors, respectively. in double-width mode, the run-length violation circuit maximum run-length detection is 512 (with a run-length increment of 8) and 640 (with a run-length increment of 10) for the 16-bit and 20-bit deserialization factors, respectively. table 2?21 summarizes the detection capabilities of the run-length violation circuit. receiver bit reversal by default, the stratix ii gx re ceiver assumes an lsbit to msbit transmission. if the transmission order is msbit to lsbit, then the receiver will put out the bit-flipped version of the data on the pld interface. the receiver bit reversal feature is av ailable to correct this situation. table 2?21. run-length violation circuit minimum and maximum range data path deserialization factor run-length violation detector range minimum maximum single-width 8 4 128 10 5 160 double-width 16 8 512 20 10 640
altera corporation 2?93 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the receiver bit reversal feature is available only in basic single-width and basic double-width modes. if the receiver bit reversal feature is enabled in basic single-width mode, the 10-bit data d[9:0] at the output of the word aligner gets rewired to d[0:9] . if the receiver bit reversal feature is enabled in basic double-width mode without the 8b/10b decoder, the msbyte d[15:8] and lsbyte d[7:0] at the output of the word aligner get rewired to d[8:15] and d[0:7] , respectively. if the receiver bit reversal feature is enabled in basic double-width mode with the 8b/10b decoder, the msbyte d[19:0] and lsbyte d[9:0] at the output of the word aligner get rewired to d[0:19] and d[0:9] , respectively. flipping the parallel data using this feature allows the receiver to put out the correctly bit-ordered data on the pld interface in case of msbit to lsbit transmission. since the receiver bit reversal is done at the output of the word aligner, a dynamic bit reversal would also require a reversal of word alignment pattern. as a result, the receiver bit reversal feature is dynamic only if the receiver is dynamically reconfigurable (allows changing the word alignment pattern dynamically) or us es manual bit slip alignment mode (no word alignment pattern). the receiver bit reversal feature is static in all other basic mode configurations and can be enabled through the megawizard plug-in. in configurations where this feature is dynamic, an rx_revbitordwa port is available to control the bit reversal dynamically. a high on the rx_revbitordwa port reverses the bit order at the input of the word aligner.
2?94 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules figure 2?69 illustrates the receiver bit reversal feature in basic single-width 10-bit wide data path configuration. figure 2?69. receiver bit reve rsal in single-width mode d [ 9 ] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] d[8] d[9] output of word aligner before rx bit reversal output of word aligner after rx bit reversal rx bit reversal = enabled
altera corporation 2?95 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?70 illustrates the receiver bit reversal feature in basic double-width 20-bit wide data path configuration. figure 2?70. receiver bit reve rsal in double-width mode to serializer rx bit reversal = enabled d[0] d[2] d[1] d[4] d[3] d[6] d[5] d[8] d[7] d[10] d[9] d[12] d[11] d[15] d[13] d[14] d[17] d[16] d[19] d[18] d[18] d[19] d[16] d[17] d[15] d[13] d[14] d[11] d[12] d[9] d[10] d[7] d[8] d[5] d[6] d[3] d[4] d[1] d[2] d[0] output of word aligner before rx bit reversal output of word aligner after rx bit reversal
2?96 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules receiver byte reversal the msbyte and lsbyte of the input data to the transmitter are often erroneously swapped. the receiver by te reversal feature is available to correct this situation. an optional port rx_revbyteordwa is available only in basic double-width mode to enable receiver byte reversal. in 8b/10b enabled mode, a high value on rx_revbyteordwa swaps the 10-bit msbyte and lsbyte of the 20-bit word at the output of the word aligner in the receiver data path. in non 8b/10b en abled mode, a high value on rx_revbyteordwa swaps the 8-bit msbyte and lsbyte of the 16-bit word at the output of the word aligner in the receiver data path. this compensates for the erroneous swapping at the transmitter and hence corrects the data received by the downstream systems. the rx_revbyteorderwa is a dynamic signal and may cause an initial disparity error at the receiver of an 8b/10b encoded link. the downstream system must be able to tolerate this disparity error. figure 2?71 illustrates the receiver byte reversal feature. figure 2?71. receiver byte reversal feature 01 00 03 02 05 04 07 06 09 08 0b 0a msbyte lsbyte xx xx xx xx 07 06 09 08 0b 0a msbyte lsbyte 00 01 02 03 04 05 06 07 08 09 0a 0b msbyte lsbyte data to be transmitted input data to transmitter word aligner output with rx _revbyteordwa asserted rx_ revbyteordwa
altera corporation 2?97 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview channel aligner (deskew) the channel aligner is au tomatically used when implementing the xaui protocol to ensure that the channels are aligned with respect to each other. the channel aligner uses a 16-word-deep fifo buffer. 1 the channel aligner is only available in the xaui mode. it is possible for ordered sets to be misaligned with respect to one another because of board skew or differen ces between the independent clock recoveries per serial lane . channel alignment, also referred to as deskew or channel bonding, realigns the orde red sets by using the alignment code group, referred to as /a/. the /a/ code group is transmitted simultaneously on all four lanes, constituting an ||a|| ordered set, during idles or inter-packet gaps (ipg). xaui receivers use these code groups to resolve any lane-to-lane skew. skew between the lanes can be up to 40 ui (12.8ns) as specified in the standard, which relaxes the board design constraints. figure 2?72 shows lane skew at the receiver input and how the deskew circuitry uses the /a/ code group to deskew the channels. figure 2?72. lane deskew with /a/ code group stratix ii gx devices manage xaui ch annel alignment with a dedicated deskew macro that consists of a 16-word-deep fifo buffer that is controlled by a xaui deskew state machine. the xaui deskew state machine first looks for the /a/ code group within each channel. when the xaui deskew state machine detects /a/ in each channel, the deskew fifo buffer is enabled. the desk ew state machine now monitors the reception of /a/ code groups. when four aligned /a/ code groups are received, the rx_channelaligned signal is asserted. the deskew state machine continues to monitor the reception of /a/ code groups and de-asserts the rx_channelaligned signal if alignment conditions are lanes are deskewed by lining up the "align"/a/, code groups lanes skew at receiver input a lane 0 k k r a k r r k k k rr lane 1 k k r a k r r k k k rr lane 0 k k r k r r k k k rr lane 1 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr
2?98 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules lost. this built-in deskew macro is only enabled for the xaui protocol. the pcs deskew state diagram specifie d in clause 48 of the ieee p802.3ae is shown in figure 2?73 . figure 2?73. ieee 802.3ae pcs deskew state diagram rate matcher the rate matcher ( figure 2?74 ) compensates for clock frequency differences between the upstream tran smitter and the local receiver. the rate matcher operates in five modes: gige, xaui, pipe, basic single-width mode, and basic double-width mode. figure 2?74. rate matcher reset + (sync_status=fail * sudi) sync_status ok * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi sudi(![/||a||/]) loss_of_alignment align_status ? fail enable_deskew ? true audi align_detect_1 enable_deskew ? false audi align_detect_2 audi align_detect_3 audi 3 !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align_acquired_1 enable_deskew ? false audi align_acquired_2 audi align_acquired_3 audi 1 2 3 !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align_acquired_4 audi 2 sudi(![/||a||/]) 1 sudi(![/||a||/]) rate matcher dataout datain wrclock rdclock
altera corporation 2?99 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the transceiver block can operate in multi-crystal environments, which can tolerate frequency variations of 300 ppm between crystals. stratix ii gx devices have embedded circuitry to perform clock rate compensation. clock rate compensati on is achieved by inserting or removing skip characters from the ipg or idle streams. this process is called rate matching or clock rate compensation. the rate matcher in the transceive r consists of a 20-word-deep fifo buffer and necessary logic to detect and perform the insertion and deletion functions. xaui the rate matcher in xaui mode operates in a synchronized 4 mode and supports up to a 100 ppm clock difference between the upstream transmitter and receiver. in this mo de, the rate matcher can insert or delete a column of /r/ characters as denoted by the ||r|| designation, depending on whether the fifo buffer is approaching an empty or full condition. the rate matcher does not operate until the xaui synchronization state machine achi eves word alignment and channel alignment. until that point, the rate matcher is not active (read and write pointers do not move). if the ||r|| code words are not receiv ed on all channels, rate matching does not occur and may lead to over/u nderflow conditions in the rate matching fifo buffer. if this situat ion occurs, the data output of the receiver outputs a constant 9'h19c (8'h9c on the rx_dataout output and 1'b1 on the rx_ctrldetect output) in lane 0 (rest of the lane are data 8'h00). the receiver digital re set must be asserted and the lanes resynchronized before data can be received. gige the rate matcher in gige mode oper ates in a channel-by-channel mode and supports up to a 100 ppm clock difference between the upstream transmitter and the receiver. the rate matcher either inserts or deletes the /i2/ ordered set depending on whethe r the fifo buffer is approaching an empty or full condition. the /i2/ order set consists of a /k28.5+/ code group and a /d16.2-/ code group (the sign after the code group signifies the running disparity at the end of the code group). the rate matcher in gige mode waits until the gige sync hronization state machine achieves synchronization. once synchronizatio n is achieved, the rate matcher is active.
2?100 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules in the event the rate matching fifo buffer in the gige mode approaches overflow or underflow, the transcei ver outputs a sequence code group (9'h19c)?8'h9c on rx_dataout and 1'b1 on rx_ctrldetect . the rx_digitalreset signal must be asserted to reset the rate matcher fifo buffer. pipe mode in pipe mode, the rate matcher suppo rts up to 300 ppm (600 ppm total) differences between the upstream transmitter and the receiver. the rate matcher looks for the skip ordered se t, which is usually a /k28.5/ comma followed by three /k28.0/ skip char acters. the rate matcher deletes or inserts skip characters when necess ary to prevent the rate-matching fifo buffer from overflowing or underflowing. the rate matcher can delete only on e skip character in a consecutive cluster of skip characters in pipe mode only. figure 2?69 shows a pipe mode rate matcher deletion of two skip characters. figure 2?75. pipe mode with two deletions (one per cluster) the rate matcher can perform skip ch aracter insertion one insertion per skip cluster in pipe mode. there is no limit on the consecutive number of skip characters allowed per skip cluster. the stratix ii gx rate matcher in pipe mode has fifo buffer overflow and underflow protection. in the event of a fifo buffer overflow, the rate matcher deletes any data after the overflow condition to prevent fifo pointer corruption until the rate ma tcher is not full. in an underflow condition, the rate matcher inserts 9? h1fe (/k30.7/) until the fifo buffer is not empty. these measures ensure th at the fifo buffer gracefully exits the overflow and underflow conditio n without requiring a fifo buffer reset. k28.5 k28.0 k28.0 k28.0 dx.y k28.5 k28.0 k28.0 datain skip cluster skip cluster skip cluster skip cluster k28.5 k28.0 k28.0 dx.y k28.5 k28.0 dx.y dx.y dataout two skips deleted
altera corporation 2?101 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview single-width general rate matching in basic single-width mode, the rate matcher supports up to 300 ppm differences between the upstream transmitter and the receiver. the rate matcher looks for the skip ordere d set, which is a /k28.5/ comma followed by three programmable neutra l disparity skip characters (for example, /k28.0/). for general rate matching, you can customize the sos to support a variety of protocols, including custom pr otocols. the sos must contain a valid control code group (kx.y), followed by any neutral disparity skip code group (any kx.y or dx.y of neutral disparity, for example, k28.0). the rate matcher dele tes or inserts skip characters when necessary to prevent the rate matching fifo buffer from overflowing or underflowing. the rate matcher in single-width mo de can delete any number of skip characters as necessary in a cluster as long as th ere are skip characters to delete. there are no restrictions regarding deleting more than one skip character in a cluster of skip characters. figure 2?76 shows an example of a single-width mode rate matcher deletion of two skip characters. although the skip characters are programmable, the /k28.0/ control group is used for illustration purposes. figure 2?76. single-width mode dele tion of two skip characters the rate matcher inserts skip characters as required for rate matching. for a given skip ordered set, the rate matc her inserts skip characters so that the total number of consecutive skip ch aracters does not ex ceed five at the output of the rate matching fifo buffer. figure 2?77 shows an example where a skip character insertion is made on the second set of skip ordered sets because the first set has the ma ximum number of skip characters. k28.5 k28.0 k28.0 k28.0 dx.y k28.5 k28.0 k28.0 datain clock k28.5 k28.0 dx.y k28.5 k28.0 k28.0 dx.y dx.y dataout two skips deleted
2?102 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules figure 2?77. single-width mode inse rtion of a skip character the stratix ii gx rate matcher in si ngle-width mode has fifo buffer overflow and underflow protection. in the event of a fifo buffer overflow the rate matcher deletes any data after the overflow condition to prevent fifo buffer pointer corruption until the rate matcher is not full. in an underflow condition, the rate matcher inserts 9'h1fe (/k30.7) until the fifo buffer is not empty. these me asures ensure that the fifo buffer gracefully exits the overflow and underflow condition without requiring a fifo buffer reset. double-width general rate matching in double-width mode, the rate ma tcher can support up to 300 ppm differences between the upstream transmitter and the receiver. the rate matcher looks for the skip ordered se t, which is usually a /k28.5/ comma followed by programmable neutral disparity skip characters (for example, /k28.0/). for general rate matching, you can customize the sos to support a variety of protocols, including custom pr otocols. the sos must contain a valid control code group (kx.y), followed by any neutral disparity skip code group (any kx.y or dx.y of neutral disparity, for example, k28.0). the rate matcher dele tes or inserts dual skip characters when necessary to prevent the rate matching fifo buffer from overflowing or underflowing. the rate matcher deletes skip characters by pairs when they appear on the upper and lower bytes at the same time. there are no other restrictions for the deletion of skip characters. figure 2?78 shows an example of deleting two skip characters. k28.5 k28.0 k28.0 k28.0 k28.0 k28.0 dx.y k28.5 datain clock k28.5 k28.0 k28.0 k28.0 k28.0 k28.0 dx.y k28.5 dataout one skip inserted k28.0 dx.y k28.0 k28.0 one skip inserted
altera corporation 2?103 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?78. deletion of skip characters in double-width mode the rate matcher inserts skip characters by pairs on the upper and lower byte ( figure 2?79 ). the insertion occurs after a /k28.5/ or the programmed control code group is detected by the rate matcher. if the comma is detected on the lower by te, the high byte must be a skip character. the insertion happens on the next double byte, if needed. if the comma appears on the upper byte, and the skip character is in the next lower byte, the insertion occurs on the double byte after the comma character, if needed. figure 2?79. insertion of skip c haracters in double-width mode 8b/10b decoder the 8b/10b decoder ( figure 2?80 ) is part of the st ratix ii gx transceiver digital blocks and lies in the receiv er path between the rate matcher and the byte deserializer blocks. the 8b/1 0b decoder operates in two modes: single-width and double-width modes and can be bypassed if 8b/10b decoding is not needed. in single-width mode, the 8b/10b decoder k28.0 k28.0 dx.y dx.y dx.y datain[15..8] clock k28.5 k28.0 dx.y dx.y dx.y datain[7..0] k28.0 dx.y dx.y dx.y dx.y dataout[15..8] k28.5 dx.y dx.y dx.y dx.y dataout[7..0] two skips deleted k28.5 dx.y dx.y dx.y dx.y datain[15..8] clock dx.y dx.y dx.y dx.y datain[7..0] k28.5 k28.0 dx.y dx.y dx.y dataout[15..8] dx.y k28.0 dx.y dx.y dataout[7..0] two skips inserted k28.0 k28.0
2?104 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules restores the 8-bit data + 1-bit contro l identifier from the 10-bit code. in double-width mode, there are two 8b/10b decoders cascaded together, which restores the 16-bit (2 8-bit) data + 2-bit (2 1-bit) control identifier from the 20-bit (2 10-bit) code. this 8b/10b decoder conforms to the ieee 802.3 1998 edition standards. figure 2?80. 8b/10b decoder note to figure 2?80 : (1) status signals include rx_ctrldetect , rx_disperr , and rxerrdectect . single-width mode in single-width mode, the stratix ii gx 8b/10b decoder operates in a similar fashion as the stratix gx 8b/10b decoder. the highlighted data path in figure 2?81 is active in the single-width mode. figure 2?81. active data pa th in single-width mode note to figure 2?81 : (1) status signals include rx_ctrldetect , rx_disperr , and rxerrdectect . 8b/10b decoder msbyte datain[19..10] to byte deserializer dataout[15..8] status signals[1] (1) 8b/10b decoder lsbyte datain[9..0] dataout[7..0] status signals[0] from rate matcher (1) 8b/10b decoder msbyte datain[19..10] to byte deserializer dataout[15..8] status signals[1] (1) 8b/10b decoder lsbyte datain[9..0] dataout[7..0] status signals[0] from rate matcher (1)
altera corporation 2?105 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 10-bit decoding the 8b/10b decoder in single-width mode translates the 10-bit encoded code into the 8-bit equivalent data or control code. the 10-bit code received must be from the supported dx.y or kx.y list with the proper disparity or error flag asserted. a ll 8b/10b control signals (disparity error, control detect, code error, and so on) are pipelined and edge-aligned with the data. figure 2?82 shows how the 10-bit symbol is decoded to the 8-bit data, plus a 1-bit control indicator. figure 2?82. 10-bit to 8-bit conversion code error detect the rx_errdetect signal indicates when the code received contains an error. this port is optional but, if not in use, there is no way to detect if a code received is valid or not. the rx_errdetect signal goes high if a code received is an invalid code or if it has a disparity error. if a code is received that is not part of th e valid dx.y or kx.y list, the rx_errdetect signal goes high. this signal is aligned to the invalid code word received at the pld logic array. in gige, xaui, and pipe mode, the inva lid code is replaced by a /k30.7/ code (8'hfe on rx_dataout + 1'b1 on rx_ctrldetect ). in all other modes, the value of the invalid code value can vary and should be ignored. disparity error detector the 8b/10b decoder detects disparity errors based on which 10-bit code it received. the disparity error is indicated at the optional rx_disperr port. 9876543210 8b/10b conversion jhgfiedcba msb received last lsb received first 76543210 hgfed cb a ctrl parallel data
2?106 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules f refer to the specifications & additional information chapter in volume 2 of the stratix ii gx device handbook for information on the disparity calculation. if negative disparity is calculated for the last 10-bit code, a neutral or positive disparity 10-bit code is expe cted. if the 8b/10b decoder does not receive a neutral or positive disparity 10-bit code, the rx_disperr signal goes high, indicating that the code received had a disparity error. if a positive disparity is calculated, a neutral or negative disparity 10-bit code is expected. the rx_disperr signal goes high if the code received is not as expected. 1 when rx_disperr is high, rx_errdetect also goes high. the detection of the disparity error might be delayed, depending on the data that follows the actual disparity error. the 8b/10b control codes terminate propagation of the dispar ity error. any disparity errors propagated stop at the control code , terminating that disparity error. in gige and xaui modes, the code that contains a disparity error is replaced by a /k30.7/ code (8'hfe on rx_dataout + rx_ctrldetect ). in all other modes, the code with inco rrect disparity should be treated as an invalid code and ignored. figure 2?83 shows a case where the disparity is violated. a k28.5 code has an 8-bit value of 8?hbc and a 10-bit value that depends on the disparity calculation at the point of the generation of the k28.5 code. the 10-bit value is 10?b0011111010 (10?h17c) for rd- or 10?b1100000101 (10?h283) for rd+. if the running disparity at time n - 1 is negative, the expected code at time n must be from the rd- column. a k28.5 does not have a balanced 10-bit code (equal numb er of 1s and 0s), so the expected rd code must toggle back and forth between rd- and rd+. at time n + 3, the 8b/10b decoder received a rd+ k28.5 code (10'h283), which makes the current running disparity negative. at time n + 4, because the current disparity is negative, a k28. 5 from the rd- column is expected, but a k28.5 code from the rd+ is received instead. this prompts rx_disperr to go high during time n + 4 to indicate that this particular k28.5 code had a disparity error. the current running disparity at the end of time n + 4 is negative because a k28.5 from the rd+ column was received. based on the current running disparity at the end of time n + 5, a positive disparity k28.5 code (from the rd-) column is expected at time n + 5.
altera corporation 2?107 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?83. disparity error control detect the 8b/10b decoder differentiates between data and control codes through the rx_ctrldetect port. this port is optional but, if not in use, there is no way to differentiate a dx.y from a kx.y. figure 2?84 shows an example waveform de monstrating the receipt of a k28.5 code (bc + ctrl). the rx_ctrldetect=1'b1 is aligned with 8'hbc, indicating that it is a control code. th e rest of the codes received are dx.y code groups. figure 2?84. control code detection bc bc bc bc xx bc bc bc n n+1 n+2 n+3 n+4 n+5 n+6 n+7 clock rx_disperr rx_dataout[7..0 ] rx_errdetect expected rd code rx_ctrldetect rd code received rx_datain rd- rd+ rd- rd+ rd- rd- rd+ rd- rd- rd+ rd- rd+ rd+ rd- rd+ rd- 17c 283 17c 283 283 17c 283 17c 83 78 bc bc 0f 00 bf 3c clock rx_ctrldetect rx_dataout[7..0 ] code group d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1
2?108 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules double-width mode in double-width mode, the dual 8b/10b decoder operates in cascaded fashion. the lsbyte is received first, followed by the msbyte. the highlighted data path in figure 2?85 is active in the double-width mode. figure 2?85. active data pa th in double-width mode note to figure 2?85 : (1) status signals include rx_ctrldetect , rx_disperr , and rxerrdectect . 20-bit decoding the 8b/10b decoder in double-width mode translates the 20-bit (2 10-bits) encoded code into the 16-bit (2 8-bits) equivalent data or control code. the 20-bit upper and lower symb ols received must be from the supported dx.y or kx.y list with th e proper disparity or error flags asserted. all 8b/10b control signals ( disparity error, control detect, and code error) are pipelined with the data in the stratix ii gx receiver block and are edge-aligned with the data. figure 2?86 shows how the 20-bit code is decoded to the 16-bit data plus a 2-bit control indicator. 8b/10b decoder msbyte datain[19..10] to byte deserializer dataout[15..8] status signals[1] (1) 8b/10b decoder lsbyte datain[9..0] dataout[7..0] status signals[0] from rate matcher (1)
altera corporation 2?109 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?86. 20-bit to 16-bit conversion code error detect the rx_errdetect signal indicates when a co de received contains an error. this port is optional but, if not in use, there is no way to detect if the code received is valid or not. the rx_errdetect signal goes high if a code received is an invalid code or if it has a disparity error. if a code is received that is not part of th e valid dx.y or kx.y list, the rx_errdetect signal goes high. this signal is aligned to the invalid code word received at the pld logic array. in double-width mode, the rx_errdetect signal is 2-bits wide in the pcs portion of the transceiver. the lower bit indicates if the lsbyte contains a code error, the upper bit indicates if the msbyte contains a code error. the value of the invalid code can vary and should be ignored. disparity error detector the 8b/10b decoder in double-width mode forwards the current running disparity value from the lsbyte decoder to the msbyte decoder to check the disparity of the symbol going in to the msbyte decoder. the msbyte decoder?s ending running disparity is then fed back to the lsbyte decoder on the next clock cycle. f refer to the specifications & additional information chapter in volume 2 of the stratix ii gx device handbook for information on the disparity calculation. 19 18 17 16 15 14 13 12 11 10 cascaded 8b/10b conversion j 1 h 1 g 1 f 1 i 1 e 1 d 1 c 1 b 1 a 1 msb lsb 15 14 13 13 11 10 9 8 h 1 g 1 f 1 e 1 d 1 c 1 b 1 a 1 ctrl[1..0] 9876543210 jhgfiedcba 7 6543 21 0 hgfed cb a parallel data
2?110 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules the rx_disperr port is 2-bits wide in the pcs. when high, the lower bit indicates if the lsbyte decoder detected a disparity error in the low byte code conversion. when high, the upper bit indicates if the msbyte decoder detected a disparity error in the high byte code conversion. if both of the rx_disperr bits are low, there is no error. the detection of the disparity error might be delayed, depending on the data that follows the actual disparity error. the 8b/10b control codes terminate any propagation of the disparity error. any disparity errors propagated assert rx_disperr on the control code byte, terminating that disparity error. figure 2?87 shows a case where the disparity is violated. a k28.5 code has an 8-bit value of 8'hbc and a 10-bi t value that depends on the disparity calculation at the point of the gene ration of the k28.5 code. the 10-bit value is 10?b0011111010 (10?h17c) for rd- or 10?b1100000101 (10?h283) for rd+. this example uses double-width mode and the 20-bit codes are split into two 10-bit codes for clarity. the expected running disparity is indicated for each 10-bit code. at time n , rx_datain receives 10?h283 first and the decoded version goes on the lsbyte of rx_dataout . at time n + 2, the high byte received a k28.5 code of incorrect disparity. the upper bits of the rx_disperr and rx_errdetect ports are asserted, resulting in the 2?h2 values shown in figure 2?87 . figure 2?87. disparity error bcbc 3 02 0 0 02 0 0 bcbc xxbc bcbc n n+1 n+2 n+3 clock rx_disperr[1..0] rx_dataout[15..0 ] rx_errdetect[1..0] expected rd code rx_ctrldetect[1..0] rd code received rx_datain rd- rd- rd- rd+ rd- rd- rd+ rd+ rd+ rd+ rd+ rd- rd+ rd+ rd+ rd- 17c 283 17c 283 283 283 283 17c
altera corporation 2?111 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview control detect the 8b/10b decoder indicates to th e pld logic array the difference between data and control codes through the rx_ctrldetect port. this port is optional but, if not in use, there is no way to differentiate a dx.y from a kx.y. in double-width mode, the rx_ctrldetect port is 2-bits wide inside the pcs. the lower bit indicates if th e lsbyte is a control word or data, and the upper bit indicates if the msbyte is a control word or data. when a control word is decoded, the corresponding rx_ctrldetect bit goes high. for data, the corresponding rx_ctrldetect bit goes low. the rx_ctrldetect port in the pld logic array is edge-aligned with the code group it is associated with. figure 2?88 shows an example waveform that shows the receipt of a k28.5 code (bc + ctrl). the rx_ctrldetect=2'b1 is aligned with 8?hbc on the lsbyte, indicating that it is a control code. the 8?hbc on the msbyte is a data, not a control word. the rest of the codes received are dk.y control codes. figure 2?88. control code detection reset the reset for the 8b/10b decoder block is derived from the receiver digital reset ( rx_digitalreset ). when rx_digitalreset is asserted, the 8b/10b decoder block resets. in reset, the disparity registers are cleared and the outputs of the 8b/10b decoder block are driven low. after reset, the 8b/10b decoder starts with either a positive or negative disparity, depending on the disparity of the data it receives. the decoder calculates the initial running disparity based on the first valid code received. 1 the receiver block must be word aligned after reset before the 8b/10b decoder can decode valid data or control codes. if word alignment has not been achieved , the data from the 8b/10b decoder is discarded and considered invalid. clock rx_dataout[15..0] rx_ctrldetect[1..0] 83 78 bc bc 0f 00 bf 3c d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1 code group 01 0
2?112 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules polarity inversion the 8b/10b decoder has a pci express compatible polarity inversion on the data bus prior to 8b/10b decoding. this polarity inversion inverts the bits of the incoming data stream prio r to the 8b/10b decoding block to fix potential p-n polarity inversion on the differential input buffer. you use the optional pipe8b10binvpolarity port to invert the inputs to the 8b/10b decoder dynamically from the pld. byte deserializer use the byte deserializer ( figure 2?89 ) to convert the one- or two-byte interface into a two- or four-byte-wide data path from the transceiver to the pld logic (refer to table 2?22 ). the pld interface has a limit of 250 mhz, so the byte deserializer is needed to widen the bus width at the pld interface and reduce the interfac e speed. for example, at 6.375 gbps, the transceiver logic has a double-byte-wide data path that runs at 318.75 mhz in a 20 deserializer fa ctor, which is above the maximum pld interface speed. figure 2?89. byte deserializer when using the byte deserializer, the pld interface width doubles to 40-bits (36-bits when using the 8b/ 10b encoder) and the interface speed drops to 159.375 mhz. byte deserializer datain[19..0] to byte ordering block dataout[39..0] control signals out [3..0] control signals in[1..0] from 8b/10b decoder slow-speed receiver cru slow-speed receiver cru or divide by 2 version 2 table 2?22. byte deserializer input and output widths input data width (bits) deserialized output data width to the fpga logic array (bits) 20 40 16 32 10 20 816
altera corporation 2?113 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview if you use the byte deserializer, the by te ordering might be different than what you intended. figure 2?90 shows the byte deserializer operating in single-width mode. the expected data pattern is a at the lower byte, followed by b at the upper byte. c and d follow in the next lower and upper bytes, respectively. figure 2?90. intended transmitter pattern the receiver may receive the intended transmitter pattern or slip a byte, as shown in figure 2?91 , where a arrives when the byte deserializer is stuffing the upper byte instead of stuffing the lower byte. this is a nondeterministic swap, be cause it depends on pll lock times and link delay. figure 2?91. incorrect byte position at receiver after byte deserializer you can use the byte ordering block or a byte reordering circuit to restore the byte order to the expected pattern. byte ordering the stratix ii gx device has a dedicate d byte ordering circuit on each receiver to obtain a certain byte order on multiple lanes. this circuit is used in conjunction with the byte deserializer block. the byte deserializer doubles the number of lanes for each receiver. if you use the single-width mode, the receiver output at the pld interface 8-bits or 10-bits (single lane) if the byte deserializer is not used, and 16-bit or 20-bit (dual lanes) if it is used. if you use double-width mode, the receiver?s output at the pld interface is 16-bits or 20-bits (dual lanes) or 36-bits or 40-bits (transceiver block lanes) if the byte de serializer is used. the nature of the byte deserializer block does not lend it self to preserving the lane striping of the source transmitter. the least si gnificant byte of the transmitter may be received in a different location. refer to ?byte deserializer? on page 2?112 for more details on how the bytes can be re-ordered. the byte ordering block ensures that the correct la ne striping is kept at the receiver output. xbd xac acx xbd
2?114 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules you cannot use the byte ordering bl ock in conjunction with the rate matcher because it disturbs the byte ordering by adding or deleting bytes because of the data and clock ppm offset. figure 2?92. byte ordering block word alignment based on byte ordering in word alignment based on byte ordering, the byte ordering block performs lane alignment after the word aligner achieves byte alignment. the byte ordering block is trigge red by the rising edge of the rx_syncstatus signal. to achieve lane alig nment, the byte reordering block monitors the data stream for th e alignment patterns. when the byte reordering block finds the correct alignment pa ttern, it inserts the programmable pad byte in the data stream until the alignment pattern can be placed in the lsbyte position (lane 0). when the alignment pattern is placed in the lsbyte position, the byte ordering process is complete and the status signal rx_byteorderalignstatus asserts (stays high). if the alignment pattern is al ready in the lsbyte posi tion, the byte ordering block detects this, considers the by te ordering process complete, and asserts the rx_byteorderalignstatus signal.byte ordering is not performed again, even if the alignmen t byte exists in the data stream, until the channel is reset by the rx_digitalreset port ( rx_analogreset and gxb_powerdown also reset the receiver channel). figure 2?93 shows how the byte ordering block works in a double-width mode four-lane configuration (four-by te-wide interface). the alignment character, denoted by the ?a? character, goes into the byte ordering block in lane two. the byte ordering bloc k inserts two pad bytes, denoted by pd, delaying the alignment byte until it appears in the lsbyte position (lane 0). byte ordering datain[39..0] to receiver phase compensation fifo datain[39..0] control signals out [3..0] control signals in[3..0] from byte deserialize r slow-speed receiver clock or divide b y 2 version rx_clkout or coreclk_out from pld rx_bytereorderalignstatus
altera corporation 2?115 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?93. double-width byte orderi ng with two pad byte inserts figure 2?94 shows the byte ordering block in single-width mode two-lane configuration. in figure 2?94 , the alignment pattern ?a? is in the msbyte position (lane 1). the byte ordering block inserts a pad character to force the alignment character to the lsbyte position (lane 0). if the alignment pattern already exists in lane 0, the byte orde ring process completes without any ordering done because it is unnecessary. after the ordering process is complete, the rx_byteorderalignstatus signal asserts and stays high until rx_digitalreset , rx_analogreset , or gxb_powerdown is asserted to reset the byte ordering block. figure 2?94. single-width byte ordering with one pad insert pld-controlled byte ordering unlike word alignment based byte ordering, pld-controlled byte ordering provides control to the user logic to restore correct byte order at the receiver. when enabled, an rx_enabyteord port is available at the pld interface. a rising edge on the rx_enabyteord port triggers the byte ordering block. the byte ordering block looks for the user-programmed byte ordering pattern in the data stream from the byte deserializer. when the byte reorderi ng block finds the byte ordering pattern, it inserts the user-programmed pad byte in the data stream until the byte ordering pattern can be plac ed in the lsbyte position. when the byte ordering pattern is placed in th e lsbyte position, the byte ordering process is complete and the status signal rx_byteorderalignstatus is asserted (stays high). if the alig nment pattern is already in the lsbyte position, the byte ordering block does not add any pad by te, considers the byte ordering process co mplete, and asserts the rx_byteorderalignstatus signal. pd d3 pd d2 byte ordering xd1 x lane 3 lane 2 lane 1 lane 0 a d1 x a x xd3 xd2 pd d1 d0 a byte ordering lane 1 lane 0 a d2 d0 d1
2?116 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules unlike word alignment based byte ordering, pld-controlled byte ordering does not require resetting the channel to re-trigger the byte ordering process. a rising edge on the rx_enabyteord signal re-triggers the process by de-asserting the rx_byteorderalignstatus signal. the byte ordering block starts looking for the byte ordering patt ern again and adds pad bytes as necessary to achieve byte ordering. on ce it completes the byte ordering process, it asserts the rx_byteorderalignstatus signal. figure 2?95 shows pld-controlled byte ordering in basic double-width mode. figure 2?95. user-controlled byte ordering in double-width mode after the first rising edge of the rx_enabyteord signal in figure 2?95 , the byte ordering block finds the byte ordering pattern a in the second most significant byte. it adds two pa d bytes pd to push the byte ordering pattern to the least si gnificant byte position and asserts the rx_byteorderalignstatus signal. after the second rising edge of the rx_enabyteord signal, rx_byteorderalignstatus is de-asserted and the byte ordering block starts looking for byte ordering pattern a. it finds the byte ordering pattern a in the second least significant byte position and adds three pad bytes pd . the byte ordering pattern a now appears at the least significant byte position and rx_byteordalignstatus is asserted. d1 a x x d5 d4 d3 d2 d2 d1 a x d6 d5 d4 d3 rx_enabyteord pd pd x x d3 d2 d1 a pd pd pd x d3 d2 d1 a rx_byteordalignstatus input to byte ordering block output from byte ordering bloc k
altera corporation 2?117 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview two critical aspects related to pld-co ntrolled byte ordering process are: what to choose as the byte ordering pattern when to assert the rx_enabyteord signal in stratix ii gx configurations, pld-controlled byte ordering is available only in sonet/sdh oc-48 mode or basic double-width mode. in sonet/sdh oc-48 mode, byte a2 of the a1a2 word alignment pattern is automatically selected as the byte ordering pattern. in basic double-width mode, you programs the byte ordering pattern while configuring the transceiver using the megawizard plug-in manager. since the byte ordering block is de signed to place the byte ordering pattern at the lsbyte position, you must select a pattern that appears at the lsbyte position at the source. this ensures that when the byte ordering block pushes the byte or dering pattern byte to the lsbyte position at the receiver, the data is co rrectly byte ordered. ideally, if this pattern is unique and is guaranteed to appear only at the lsbyte position at the source, the instance at which the rx_enabyteord signal is asserted becomes irrelevant. for example, in packet-based 8b/10b encoded links, you could choose the star t of packet (sop) byte as the byte ordering pattern if it is a unique co ntrol code (say k28.0). in non 8b/10b scrambled data links, it may be difficult to find a unique pattern since there is a possibility of the pattern appearing in the scrambled payload and causing the byte ordering block to add pad bytes incorrectly. in such cases, the instance at which the rx_enabyteord signal is asserted becomes critical. the rx_enabyteord signal must be asserted after the word aligner has aligned to the correct word boundary. th is ensures that the byte ordering block does not find a byte ordering pattern between the word boundaries. if the rx_enabyteord signal is asserted before the intended byte ordering byte appears at the receiver , then the byte ordering block will add necessary pad bytes to achiev e correct byte ordering. if the rx_enabyteord signal is asserted before the unintended data byte that matches the byte ordering pattern, then the byte ordering block may incorrectly add pad bytes and assert the rx_byteorderalignstatus signal. in the sonet/sdh oc-48 configuration, since the receiver anticipates the byte ordering pattern a2 every 125 s, the rx_enabyteord signal assertion can be easily timed to avoid incorrect byte ordering. in basic double-width mode, it is up to you to either select a unique byte ordering pattern or an appropriate instance to assert rx_enabyteord , depending on the dynamics of the implemented protocol.
2?118 altera corporation stratix ii gx device handbook, volume 2 october 2007 receiver modules receiver phase compensation fifo buffer the receiver phase compensation fifo buffer ( figure 2?96 ) is located at the fpga logic array interface in the receiver block and is used to compensate for phase difference between the receiver clock and the clock from the pld. the receiver phase comp ensation fifo buff er operates in two modes: low latency and high latency. in low latency mode, the fifo buffer is four words deep. the quartus ii software chooses the low latency mode automatically for every mode except the pci-express pipe mode (which automatically uses high latency mode). in high latency mode, the fifo buffer is eight words deep. figure 2?96. receiver phase compensation fifo buffer note to figure 2?96 : (1) the receiver clock can either be the re covered clock or the transmitter cmu clock, depending on whether the rate matcher is used or not. in basic mode, the write port is clocked by the recovered clock from the cru. this clock is half the rate if th e byte deserializer is used. the read clock is clocked by the associated channel?s recovered clock. 1 the receiver phase compensation fifo is always used and cannot be bypassed. in four-channel (4) and eight-channe l (8) bonding modes, all the read pointers are derived from a common so urce so that there is no need to synchronize the data of each channel in the pld logic. receiver phase compensation fifo error flag depending on the transceiver configuration, the write port of the receiver phase compensation fifo can be clocked by either the recovered clock ( rx_clkout ) or transmitter pll output clock ( tx_clkout or coreclkout ). the read port can be cl ocked by the recovered clock ( rx_clkout ), transmitter pll output clock ( tx_clkout or receiver phase compenstation fifo datain[31..0] to pipe or pld dataout[31..0] control signals out [3..0] control signals in [3..0] from byt e ordering block slow-speed receiver clock or divide by 2 version (1) rx_clkout or coreclk_out from pld
altera corporation 2?119 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview coreclkout ) or a pld clock. in all conf igurations, the write clock and the read clock must have 0 ppm di fference to avoid overrun/underflow of the phase compensation fifo. an optional debug_rx_phase_comp_fifo_error port is available in all modes to indicate receiver phase compensation fifo overrun/underflow condition. debug_rx_phase_comp_fifo_error is asserted high when the phase comp ensation fifo gets either full or empty. this feature is useful to verify the phase compensation fifo overrun/underflow condition as a probable cause of link errors. pld-transceiver interface clocking there are 32 pld interface clocks available between the pld logic and the transceiver blocks. the 32 pld inte rface clocks are divided equally between the top and bottom half of the device (16 pld interface clocks for the top half of the device and 16 pld interface clocks for the lower half). the pld interface clocks are used as the receiver and transmitter phase compensation fifo clocks. figure 2?97 shows the pld clock interface. figure 2?97. pld interface clock (2sgx130g) the following clock inputs utili ze the pld interface clocks: rx_cruclk (if driven from the pld clock tree) pll_inclk (if driven from the pld clock tree) tx_coreclk rx_coreclk cal_blk_clk 16 pld interface clocks to support transceiver blocks 0 and 1 transceiver block 2 transceiver block 0 transceiver block 1 transceiver block 3 transceiver block 4 16 pld interface clocks to support transceiver blocks 2, 3, and 4 pld transceiver top half of device bottom half of device
2?120 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking the rx_cruclk and the pll_inclk are reference clocks to the transceiver receiver pll and transmitter pll. these two ports can take the reference clock from the dedicated refclk pins or from the pld global clock pins. if th e pld global clock pins are used to feed the transceiver plls, a pld interface clock will be used for each independent reference clock feeding the transceiver. each transceiver block has one possible pld connection to pll_inclk and four possible connections to rx_cruclk . only one reference clock frequency can be fed from the pld to each transceiver block. the receiver plls of each channel can possibly have a different reference clock frequency as long as there are pld interface cloc ks available. the tx_coreclk and rx_coreclk are input clocks to the transmitter and receiver phase compensation fifo s, respectively. by default, the quartus ii software automatically routes the tx_clkout or coreclk_out to the tx_coreclk , and the rx_clkout , tx_clkout , or coreclk_out to the rx_coreclk port, depending on the transceiver block and channel configuration as listed in the above section. there are options to route other pld clocks to the tx_coreclk and rx_coreclk ports. the non-transceiver clocks that feed these ports are required to be frequency locked (0 ppm ) to the transceiver output clocks of the associated channel or tran sceiver block, depending on the configuration. the method of using this option is discussed in a later section. the cal_blk_clk feeds the calibration block. if a single clock from the pld feeds mu ltiple ports listed above, then only one pld interface clock will be used. it is recommended that whenever possible, utilize a common clock. this will save pld clock resources and pld interface resources. each transceiver block (with all channels running in the same configuration), by default, uses a mi nimum of five pld interface clocks as seen in figure 2?98 . this is with each rx_coreclk clocked by the associated rx_clkout of each rx channel, and since all the tx channels are the same, the quartus ii soft ware will automatically route tx_clkout[0] to all the tx_coreclk inputs. the reference clock can use the dedicated refclk pins to save on pld interface clocks. the quartus ii software does not cross th e transceiver block boundary when combining like tx channels. also, the quartus ii software does not combine rx clocks automatically.
altera corporation 2?121 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?98. minimum pld inte rface clock utilization 1 note that in this configuration, the user logic needs to be clocked by the tx_clkout[0] for the tx path and the individual rx channel logic needs to be clocked by its associated rx_clkout . if you use the default configuration, and the user logic is clocked by another clock than the tr ansceiver clock associated with that channel, a pld phase compensation must decouple the phase difference. figure 2?99 shows of tx and rx pld phase compensation fifos decoupling the user logic from the transceiver. rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 3 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 2 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 1 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 0 tx_clkout[0] tx_clkout[0] tx_clkout[0] tx_clkout[0] rx_clkout[3] rx_clkout[2] rx_clkout[1] rx_clkout[0] pld xcvr
2?122 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking figure 2?99. phase compensation fifo implementation in pld logic if more tx channels are used acro ss transceiver blocks, and/or rx channels are also configured in a similar fashion and have the same data rate and pld output cloc k frequency, you will ne ed to manually connect the tx_coreclk and rx_coreclk ports. rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 3 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 2 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 1 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 0 pld rx phase comp fifo pld rx phase comp fifo pld rx phase comp fifo pld rx phase comp fifo pld tx phase comp fifo pld tx phase comp fifo pld tx phase comp fifo pld tx phase comp fifo pld clock to user logic tx_clkout[0] tx_clkout[0] tx_clkout[0] tx_clkout[0] rx_clkout[3] rx_clkout[2] rx_clkout[1] rx_clkout[0] pld xcvr
altera corporation 2?123 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the pld interface clock utilization can be further reduced by directly feeding the tx_coreclk and/or the rx_coreclk ports of like channels directly with a single clock. the source clock must be frequency locked to the associated transceiver output cl ock. any ppm difference results in data corruption. to help guard against incorr ect usage, the use of the tx_coreclk and rx_coreclk options requires clock assi gnments in the assignment organizer. if no assignments are used, the quartus ii software will give a compilation error. there are 4 settings to enable the pld interface clocking options: stratix ii gx gxb shared clock group setting stratix ii gx gxb shared clock group driver setting stratix ii gx 0ppm clock group setting stratix ii gx 0ppm clock group driver setting as the name indicates, there are two ma in settings, each with a driver and clock group setting. when specifying cl ock groups, an integer identifier is used as the group name in order to differentiate other clock group settings from one another. the stratix ii gx gxb shared clock group setting is the safest assignment. the quartus ii compiler will analyze the netlist during compilation to ensure tx channel members are derived from the same source. the quartus ii software will give a fitting error for incompatible assignments. the software cannot check for the output of the rx frequency locked to the driving clock as the exact frequency is dictated by the upstream transmitter's source clock. it will be up to you to ensure that the rx_coreclk is derived from the same source clock as the upstream transmitter. the stratix ii gx gxb shared clock group driver setting assignment must be made to the source channel of the tx_clkout or coreclk_out . specifying anything except the tx channels (the source for the tx_clkout or coreclk_out ) will result in a fitter error. if the source clock is not from tx_clkout or coreclk_out (for example, the source is from rx_clkout or from a pld clock input), the 0 ppm setting must be used instead. for example, in a synchronous system, the tx and rx are of the same data rate and configuration. th e clock output of the ch annel 0 is used (but any tx clock output can be used). the stratix ii gx gxb shared clock group driver setting is made in the assignment editor on the tx_dataout[0] name. you can use a group identifier value of "1" to identify the group that this driver feeds. the stratix ii gx gxb shared
2?124 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking clock group setting is made to all the rx_datain channels that the tx_dataout[0] output clock drives. (note that the other tx_dataout channels do not need an assignme nt as the quartus ii software automatically groups the like transm itters in a transceiver block). a group identifier value of "1" is also made to the rx_datain assignments. a breakdown of the assignment in the assignment editor is shown in table 2?23 : figure 2?100 shows the clocking configuration of the example. 1 for 4 transceiver bloc k configurations, the coreclk_out can replace the tx_clkout[0] but the driver assignment still remains tx_dataout[0] . table 2?23. assignment editor to: tx_dataout[0] assignment name: stratix ii gx gxb shared clock group driver setting value: 1 to: rx_datain[] (note that the [] signifies the entire rx_datain group) assignment name: stratix ii gx gxb shared clock group setting value: 1
altera corporation 2?125 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?100. tx_clkout[0] feeding all the tx_coreclk and rx_coreclk posts of a transceiver block the stratix ii gx 0ppm clock group setting is for more advanced users that know the clocking configuratio n of the entire system and wants to reduce the pld global clock resource and pld interface clock resource utilization. the quartus ii compiler does not pe rform any checking on the clock source. it is up to you to ensure that there is no frequency difference from the associated transceiver clock of the group and the dr iving clock to the tx_coreclk and rx_coreclk ports. rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 3 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 2 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 1 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 0 tx_clkout[0] to user logic tx_coreclk[3] rx_coreclk[3] tx_coreclk[2] rx_coreclk[2] tx_coreclk[1] rx_coreclk[1] tx_coreclk[0] rx_coreclk[0]
2?126 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking the stratix ii gx 0ppm clock group driver setting can be made to any of the transceiver output clocks ( tx_clkout , rx_clkout , and coreclk_out ) as well as any pld cloc k input pins, transceiver dedicated refclk pin, or pld pll output. us er logic cannot be used as a driver. as with the shared clock gr oup setting, the driv er setting for the transceiver output clocks is made to the associated channel. for example, for tx_clkout or coreclk_out , the transmitter channel name is specified. for the rx_clkout being the driver, the receiver channel name of the associated rx_clkout is specified. for the pld input clock pins and the transceiver refclk pins, the name of the clock pin can be specified. for the pll output, the pll clock output port of the pll can be found in the node finder and entered as the driver name. an integer value is specified for the group identification. the stratix ii gx 0 ppm clock group setting is made to the tx or rx channel names. a breakdown of the assignment in the assignment editor is shown in table 2?24 : the following are examples of clocking configurations that can use the 0ppm assignment: all rx channels are configured the same and one recovered clock is feeding the rx_coreclk as shown in figure 2?101 . though this example shows all the rx channels res ide in a transceiver block, rx_clkout[0] of this transceiver block can feed ot her rx channels of other transceiver blocks. note that this example is not showing any tx channels. if the rx_clkout is used as a driver, it can only feed rx channels. if these channels are used in a duplex mode, the tx_clkout from the tx channels should be used as the driver and feed the tx as well as the rx phase compensation fifos. the rx_clkout cannot feed the tx_coreclk ports. table 2?24. assignment editor to: tx_dataout, rx_datain, pld_clk_pin_name, refclk_pin, and pll_outclk assignment name: stratix ii gx gxb 0 ppm clock group driver setting value: 1 to: rx_datain[] and tx_dataout[] assignment name: stratix ii gx gxb 0 ppm clock group setting value: 1
altera corporation 2?127 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview it is important to note that asserting the rx_analogreset of the rx channel associated with the driver cloc k will flatline the clock. all logic and rx phase compensation fifos read port that it feeds will not be receiving a clock during analog reset of the driving channel. if the reset state machine is clocked by the driver clock, the reset state machine will hang and may not come out of reset. all the rx channels will need to go through a digital reset in order to restore the phase compensation fifo pointers. figure 2?101. rx_clkout[0] feeding all receiv ers of the same transceiver block rx phase comp fifo cru rx tx channel 3 rx phase comp fifo cru rx tx channel 2 rx phase comp fifo cru rx tx channel 1 rx phase comp fifo cru rx tx channel 0 rx_clkout[0] to user logic
2?128 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking the next example is similar to the shared clock example of a tx_clkout feeding all the rx and tx channels, ex cept that with the 0ppm setting, the tx_clkout can drive across transceiver blocks, as shown in figure 2?102 . the upstream device feeding the rx channels must be frequency locked to the tx_clkout used. as with the rx channel example above, it is important to note that powering down the transceiver bloc k where the driving channel resides will flatline the tx_clkout . all logic and the write ports of all the tx phase compensation fifo will the driving clock feeds will flatline. a digital reset must be done on all channels after a driving transceiver block power down event.
altera corporation 2?129 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?102. tx_clockout[0] feeding tx and rx phase co mpensation fifos across multiple transceiver blocks the next example features the dedicated refclk feeding the tx_coreclk and rx_coreclk ports as well as supplying the transceiver with the reference clock ( figure 2?103 ). this requires that the frequency of the reference clock at the refclk pin be of the same frequency as the transceiver output clocks of the associated channels. any frequency difference yields corruption of data. rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 3 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 2 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 1 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 0 tx_clkout[0] to user logic tx_coreclk[3] rx_coreclk[3] tx_coreclk[2] rx_coreclk[2] tx_coreclk[1] rx_coreclk[1] tx_coreclk[0] rx_coreclk[0]
2?130 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking figure 2?103. dedicated refclk feeding pcfifo clock ports another example is where the pld inpu t clock or pll ou tput is feeding the tx_coreclk and rx_coreclk ports. note that the driver clock must be the same frequency as the transceiver output clocks. also, though this example shows the cha nnels within a single transceiver block, the 0ppm setting will also allow tx and/or rx channel pcfifos of multiple transceiver blocks to be clocked by a common clock. rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 3 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 2 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 1 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 0 refclk to user logic pld xcvr tx_coreclk[3] rx_coreclk[3] tx_coreclk[2] rx_coreclk[2] tx_coreclk[1] rx_coreclk[1] tx_coreclk[0] rx_coreclk[0] central block
altera corporation 2?131 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?104. pld-driven clock feeding the tr ansceiver phase compensation fifos pld interface clock resources for the regional or global clock netw ork to route into the transceiver, a local route input output (lrio) channel is required. each lrio clock region has up to eight clock path s and each transceiver block has maximum of eight clock paths for co nnecting with lrio clocks. these resources are limited and determine the number of clocks that can be used between the pld and transceiver blocks. tables 2?25 through 2?28 give the number of lrio resources availa ble for stratix ii gx devices with different numbers of transceiver blocks. rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 3 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 2 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 1 rx phase comp fifo tx phase comp fifo cru rx tx tx clk div block channel 0 refclk to user logic pld xcvr pld input pin / pld pll tx_coreclk[3] rx_coreclk[3] tx_coreclk[2] rx_coreclk[2] tx_coreclk[1] rx_coreclk[1] tx_coreclk[0 ] rx_coreclk[0]
2?132 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking table 2?25. available clocking connecti ons for transceivers in 2sgx30d clock resource transceiver global clock regional clock bank13 8 clock i/o bank14 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 12-1 v table 2?26. available clocking connecti ons for transceivers in 2sgx60e clock resource transceiver global clock regional clock bank13 8 clock i/o bank14 8 clock i/o bank15 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 vv region2 8 lrio clock v rclk 12-19 vv region3 8 lrio clock v rclk 12-19 v table 2?27. available clocking connections fo r transceivers in 2sgx90f (part 1 of 2) clock resource transceiver global clock regional clock bank13 8 clock i/o bank14 8 clock i/o bank15 8 clock i/o bank16 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 v
altera corporation 2?133 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview clock signal provides information about clock signal on the transceiver block. region2 8 lrio clock v rclk 12-19 v region3 8 lrio clock v rclk 12-19 v table 2?27. available clocking connections fo r transceivers in 2sgx90f (part 2 of 2) clock resource transceiver global clock regional clock bank13 8 clock i/o bank14 8 clock i/o bank15 8 clock i/o bank16 8 clock i/o table 2?28. available clocking connecti ons for transceivers in 2sgx130g clock resource transceiver global clock regional clock bank13 8 clock i/o bank14 8 clock i/o bank15 8 clock i/o bank16 8 clock i/o bank17 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 region2 8 lrio clock v rclk 12-19 vv region3 8 lrio clock v rclk 12-19 vv table 2?29. clock port list (part 1 of 2) clock name maximum number per transceiver block notes pll_inclk 2 (1) rx_cruclk 4 rx_cruclk can share resources with pll_incl k tx_clkout / tx_coreclk 4 rx_clkout / rx_coreclk 4
2?134 altera corporation stratix ii gx device handbook, volume 2 october 2007 pld-transceiver interface clocking example of clock usage in a five transceiver block device or using channel reconfiguration, it is possible to exceed the number of lrio clocks available. table 2?30 shows an example of lrio clock resource usage in a ep2sgx130g device. in this case, the quartus ii software does not give errors for transceiver configurations. reconfig_clock 1 used only for dynamic reconfiguration. cal_blk_clk 1 one for all transceiver blocks. fixedclk 1 pci-express (pipe) mode only. coreclkout 1 used only for four-lane configurations. note to table 2?29 : (1) altera recommends using the refclk pin for pll_inclk . the refclk pin uses inter-transceiver line; therefore, th ere is no need to use the lrio clock resource. this usage helps with performance and resource. table 2?29. clock port list (part 2 of 2) clock name maximum number per transceiver block notes table 2?30. example of lrio cloc k resource usage (part 1 of 2) clock name number of signals in the transceiver block lrio resource usage routing bank13 xaui pll_inclk 10 using one refclk pin. rx_cruclk 40 connect to pll_inclk. coreclkout 1 1 to pld fabric. region0 lrio clock 1/8 bank14 gige 4ch pll_inclk 10 using one refclk pin. rx_cruclk 40 connect to pll_inclk. tx_clkout 4 1 to pld fabric. region1 lrio clock 1/8
altera corporation 2?135 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview multiple protocols and data rates in a transceiver block stratix ii gx supports multiple protoc ols and/or data rates in a single transceiver block. this allows for better utilizat ion of the channels and power savings. there can be up to four independent data rates supported and up to two separate frequencies for the tx channels and up to four separate frequencies for the rx cha nnels within a single transceiver block. on the tx side, the tx local dividers and the two txplls in the central block can be used together or separate ly to achieve multiple data rates and/or protocols in a tran sceiver block. refer to ?transmitter local clock divider block? on page 2?16 and ?central clock divider block? on page 2?14 for more information regarding the tx local divider blocks and the dual txpll configuration. on the rx side, it is possible to have up to four receiver channels to be of different data rates and configurations as long as there are enough pld interface clocks to support the cha nnels. since each receiver channel contains a dedicated rxpll, there are no data rate or configuration restrictions. bank15 basic 4ch pll_inclk 10 using one refclk pin. rx_cruclk 40 connect to pll_inclk. rx_clkout 4 4 to pld fabric. tx_clkout 4 1 to pld fabric. cal_blk_clk 1 1 from pld fabric. bank16 basic 4ch pll_inclk 10 using one refclk pin. rx_cruclk 40 connect to pll_inclk. rx_clkout 4 4 to pld fabric. tx_clkout 4 1 to pld fabric. bank17 pcie 4 pll_inclk 10 using one refclk pin. rx_cruclk 40 connect to pll_inclk. coreclkout 1 1 to pld fabric. fixedclk 1 1 from pld fabric. region2 lrio clock 8/8 (or 7/8, 6/8) region3 lrio clock 5/8 (or 6/8, 7/8) table 2?30. example of lrio cloc k resource usage (part 2 of 2) clock name number of signals in the transceiver block lrio resource usage routing
2?136 altera corporation stratix ii gx device handbook, volume 2 october 2007 multiple protocols and data rates in a transceiver block quartus ii software automatical ly combines multiple alt2gxb megafunction instances into a transceive r block if possible. if there is a particular placement re quired, altera recommends that you force the placement via tx and/or rx channel pin assignment in the assignment editor. quartus ii software checks to see if th e desired placement is possible. if not, the quartus ii software sends a fitter error. since the tx channel parameters are the deciding factors on whether the channels can be combined in a sing le transceiver bloc k, the following sections will concentrate on the tx side. transceiver block-based controls first, in order to comb ine channels into a single transceiver block, the transceiver block-based control sign als must be driven from the same source. the following is a list of transceiver block-based control signals: gxb_powerdown reconfig_clk reconfig_togxb the gxb_powerdown signal of all the instances that are to be combined in a single transceiver block must be connected to a single point; for example, the same input pin or same logic. any driving logic differences will prevent the instance from being combined in a single transceiver block. if you use dynamic reconfiguration, only one dynamic reconfiguration controller is allowed to drive the inst ances to be combined in a single transceiver block. if you use mu ltiple dynamic reconfiguration controllers, the quartus ii software will not be able to combine the instances into a single transceiver block as the pld logic cannot be combined. all the reconfig_clk and reconfig_togxb ports need to be tied to a single dynami c reconfiguration block.
altera corporation 2?137 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?105 is an example of correct transceiver block-control signal connection. figure 2?105. transceiver bloc k-control signal connections txpll sharing multiple channels in using the basic protocol can share a common txpll. their data path configuration can differ as long as they are within the same width mode; for example, if all operate in single-width mode or if all operate in double-width mode. mixing single-width and double-width modes is not allowed for txpll sharing. inst 1 gxb_powerdown inclk / rx _cruclk gxb_powerdown inclk / rx _cruclk gxb_powerdown inclk / rx _cruclk gxb_powerdown inclk / rx _cruclk refclk powerdown logic inst 2 inst 3 1 duplex channel 1 duplex channel 1 duplex channel alt2gxb_reconfig reconfig_clk/ reconfig_togxb alt2gxb alt2gxb alt2gxb reconfig_clk/ reconfig_togxb reconfig_clk/ reconfig_togxb reconfig_clk/ reconfig_togxb inst 4 alt2gxb 1 duplex channel
2?138 altera corporation stratix ii gx device handbook, volume 2 october 2007 multiple protocols and data rates in a transceiver block the data rate range of single-width versus double-width mode is listed in table 2?31 . if the desired data rate range falls within a mode using the tx local divider factors (/1, /2, or /4), you can use a single txpll to support the desired data rate range. if the desired data rate range straddles two modes, txpll sharing cannot be done. they can still be in the same transceiver block, but you w ill need to use two txplls. in order to share a txpll, their pll configurations are required to be the same. the following is a list of txpll parameters that must be identical: pll bandwidth primary data rate reference clock frequency pre-divider on the dedicated refclk (if applicable) though the txpll settings must be identical, the tx local divider settings on the channels can vary. you will need to set up the txpll for the highest data rate and use the divide rs to drop the data rate down on the slower channels to /4 or /2 of the primary data rate. use the alt2gxb megawizard to make your changes. non-basic protocol modes cannot share a txpll unless they are all of the same protocol and sub protocol. 1 txpll sharing is restricted to th e channels within a transceiver block. also, the analog buffer voltage setting vcch must be the same across all the channels in the transceiver block. the quartus ii software will not allow channels with different vcch settings into the same transceiver block. the following is an example of inst ances that can be combined into a single transceiver block. we have two 4 gbps, one 2 gbps, and one 1 gbps links. since the target data rate is either a /1, /2, or /4 division factor from the highest data rate, it is possible to combine this into a single transceiver block. it is assumed that the vcch , transceiver block signals table 2?31. single-width versus d ouble-width data rate range mode minimum data rate maximum data rate single width 600 mbps 3.125 gbps double width 1 gbps 6.375 gbps
altera corporation 2?139 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview (for example, gxb_powerdown) , dynamic reconfig ports, reference clock frequency, and pll bandwidth of each instance are the same and/or are driven from the same point. each instance must be created with the same primary data rate set a 4 gbps so that the txplls can be combined. use the local dividers to achieve the desired data rate for each channel. because the goal is to have all four channels in a transceiver bloc k driven off of a single txpll, the reference clock will need to be from the same point - either from a single dedicated refclk pin or from though the example shows that there are two 4 gbps channels configured in a single alt2gxb instance, duplicate channels may not need to be configured in the same instance. if the two 4 gbps channels were to be configured in separate instances, the resultant transceiver block configuration will not have changed.
2?140 altera corporation stratix ii gx device handbook, volume 2 october 2007 multiple protocols and data rates in a transceiver block figure 2?106 shows an example of txpll sharing compatible instances. figure 2?106. txpll sharing compatible instances ch 1 data rate: 4 gbps tx loc div: /1 ch 0 inst 1 txpll primary data rate : 4 gbps alt2gxb data rate: 4 gbps tx loc div: /1 ch 0 inst 2 txpll primary data rate : 4 gbps alt2gxb data rate: 2 gbps tx loc div: /2 ch 0 inst 3 txpll primary data rate : 4 gbps alt2gxb data rate: 1 gbps tx loc div: /4
altera corporation 2?141 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the instances shown in figure 2?106 net the transceiver block configuration shown in figure 2?107 after compilation. the specific data rate on the channel location may differ depending on either the placement algorithm or yo ur assignments. since al l the channels in this transceiver block are utilized, the second txpll is not used. however, you can use the second dedicated refclk input to feed the iq lines or the pld logic if you do not use the first dedicated refclk to drive the iq lines or pld logic. figure 2?107. resultant transceiver bloc k configuration after combining instances transceiver block ch 1 data rate : 4 gbps tx loc div: / 1 ch 0 data rate : 4 gbps tx loc div: / 1 txpll primary data rate: 4 gbps ch 3 data rate : 1 gbps tx loc div: / 4 ch 2 data rate : 2 gbps tx loc div: / 2
2?142 altera corporation stratix ii gx device handbook, volume 2 october 2007 multiple protocols and data rates in a transceiver block using two txplls if the desired data rates and/or pr otocols cannot utilize a single txpll within a single transceive r block, the other txpll within that transceiver block may be able to support the additional data rates and/or protocol configuration. this is useful if combining channe ls operating in single-width and double-width modes, or two quartus i i software-defined protocols (for example, basic, gige, sonet/sdh, sdi, or pci express [pipe] modes) in the same transceiver block. you can configure channels in the same protocol group from individual alt2gx b instances, or you can configure the whole group in a single instance. the example in figure 2?108 will not be able to share a single txpll due to incompatible primary data rates. since there are only two different primary data rates, you can merge the four channels into a single transceiver block. it is assumed that the channels sharing the same txpll will meet the requirements describe d in the above example. for the channels not sharing the same tx pll, the pll parameters may be different; for example, different data rate, reference clock input frequency, reference clock input pin, and pll bandwidth. also, the primary data rates need not be a multiple of the other txpll primary data rate. the transceiver block-based signals will have to be the same across all channels. in addition to the primary data rate di fferences, the mode of operations also differs which require the use of separate txplls. the 4 gbps channels operate in a double-width mode while the 2 gbps and 1 gbps channels operate in a single-width mode (due to the sub 3.125 gbps primary data rate).
altera corporation 2?143 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?108. txpll sharing incompatible instances ch 1 data rate: 4 gbps tx loc div: /1 ch 0 inst 1 txpll primary data rate : 4 gbps alt2gxb data rate: 4 gbps tx loc div: /1 ch 0 inst 2 txpll primary data rate : 2 gbps alt2gxb data rate: 2 gbps tx loc div: /1 ch 0 inst 3 txpll primary data rate : 2 gbps alt2gxb data rate: 1 gbps tx loc div: /2
2?144 altera corporation stratix ii gx device handbook, volume 2 october 2007 multiple protocols and data rates in a transceiver block figure 2?109 is the resultant transceiver block configuration after combining the above instances. since the two txplls primary data rates can be derived from the same reference clock frequency, one reference clock input is needed. if the referenc e clock frequency differs, or if the primary data rates differ (for exampl e, 2.488 gbps instead of 2 gbps), two reference clocks will be needed. 1 if the reference clock is driv en from the pld, only one connection exists for each transc eiver block. both txplls in a transceiver block cannot be dr iven from separate pld clock pins. if the reference clock frequencies are the same, it is possible to drive both txplls in a transc eiver block from a single pld clock pin (or the dedicated refclk pin). figure 2?109. resultant transceiver bloc k configuration with two txplls transceiver block ch 1 data rate: 4 gbps tx loc div : / 1 ch 0 data rate: 4 gbps tx loc div : / 1 txpll 0 primary data rate : 4 gbps ch 3 data rate : 1 gbps tx loc div : / 2 ch 2 data rate: 2 gbps tx loc div : / 1 txpll 1 primary data rate : 2 gbps
altera corporation 2?145 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview combining rx channels in a transceiver block receiver channels of different configuration and data rates can be combined in to a single transceiver block. since each receiver channel contains a dedicated rxpll, there are no data rate or configuration restrictions. however, there are some restrictions. one restriction is for the dedicate reference clock usage. al l the rx channels referenced off of the same dedicated refclk pin must have the same input frequency and the same usage of the refclk pre-divider. the other restriction is that since this is a rx-only co nfiguration, the use of the rate matcher block is not allowed. if rate matching is ne eded, you will need to implement the rate matching fifo in the pld core. it is possible to have up to four receiv er channels to be different data rates and configurations, as long as ther e are enough pld interface clocks to support the channels. as with the tx channels, each receiver channel can be configured from separate alt2gxb instances or the entire group (as long as all the rx channels are the same) can be configured in one instance. combining rx and tx channels in a transceiver block you can combine duplex channels and/or a mixture of tx and rx channel instances into a single tr ansceiver block. for combining the duplex channel configuration, the tx rules and restrictions is a superset of the rx side and is covered in ?txpll sharing? on page 2?137 and ?using two txplls? on page 2?142 . the rules and restrictions for a combination of separate rx and tx channel instances in the same transcei ver block are the sa me as outlined in ?txpll sharing? on page 2?137 and ?using two txplls? on page 2?142 for the transmitter and ?combining rx channels in a transceiver block? on page 2?145 . native modes the stratix ii gx transceiver operates in one of nine native modes: basic single-width mode (600 mbps to 3.125 gbps) double-width mode (1 gbps to 6.375 gbps) pci express (pipe) mode (2.5 gbps) xaui (3.125 gbps up to ?higig? 3.75 gbps) gige (1.25 gbps) sonet/sdh mode (oc-12, oc-48, and oc-96) (oif) cei phy interface (>3.135 gbps to 6.375 gbps) serial rapidio (1.25 gbps, 2.5 gbps, 3.125 gbps) sdi (hd, 3g) cpri (614 mbps, 1.228 gbps, 2.456 gbps)
2?146 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes basic single-width mode use the basic single-width mode for cu stom protocols that are not part of the pre-defined supported protocol s, for example pipe. with some restrictions, the following pcs blocks are available: transmitter phase compensation fifo buffer transmitter byte serializer 8b/10b encoder word aligner rate matcher 8b/10b decoder byte deserializer byte ordering block receiver phase compensation fifo buffer the byte ordering block is availabl e only in reverse serial loopback configuration in basic mode. the rate matcher is coupled with the 8b/10b code groups, which requires the use of the 8b/10b encoder or decoder either in the pcs or pld logic array. basic single-width mode with x4 clocking in basic single-width mode, the alt2gxb megawizard provides a 4 option under the which subprotocol will you be using? option. if you select this option, all four transmit ter channels within the transceiver block are clocked by clocks generated from the central clock divider block (refer to ?transmitter clocking (bon ded channels)? on page 2?29 ). the low-speed clock from the central cloc k divider block clocks the bonded transmitter pcs logic in all four ch annels. this reduces the transmitter channel-to-channel skew within the transceiver block. each receiver channel within the transceiver bloc k is clocked individually by the recovered clock from its own clock recovery unit (cru). 1 configuring transceivers in this mode yields low transmitter channel-to-channel skew within a transceiver block. it does not provide skew reduction for channe ls placed acro ss transceiver blocks.
altera corporation 2?147 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?110 shows the data path in this mode. figure 2?110. basic single-widt h mode with 4 clocking the transmitter data path consists of a 16-bit pld-transceiver interface, transmitter phase compensation fifo , 16:8-bit byte serializer, and 8:1 serializer. the receiver data path consists of the clock recovery unit (cru), 1:8 deserializer, bit-slip word aligner, 8:16 byte deserializer, receiver phase compensation fifo, and 16-bi t transceiver-pld interface. transceiver placement limitations if one or more channels in a transceiver block are configured to basic single-width mode with 4 clocki ng option enabled, the remaining channels in that transceiver bl ock must either have the same configuration or must be unused. all used channels within a transceiver block configured to this mode must al so run at the same data rate. all channels within the transceiver block configured to this mode must be instantiated using the same alt2gxb megawizard instance. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer
2?148 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figures 2?111 and 2?112 show examples of legal and illegal transceiver placements with respect to the basic single-width mode with 4 clocking enabled. figure 2?111. examples of legal transceiver placement figure 2?112. examples of ill egal transceiver placement clocking and reset recommendations to minimize the transmitter channel to channel skew across transceiver blocks, altera recommends: using the dedicated refclk pins of the centrall y located transceiver block in your design to provide the input reference clock for all transceiver blocks. this reduces the skew on the input reference clock driving the cmu pll in each transceiver block. for example, in a design with 12 cha nnels placed across banks 13, 14, and 15, use the refclk pins of bank 14 to provide th e input reference clock. in a design with 16 channels placed ac ross banks 13, 14, 15, and 16, use the refclk pins of either bank 14 or 15. de-asserting the tx_digitalreset signal of all used transceiver blocks simultaneously after pll_locked signal from all active transceiver blocks goes high. ch0 ch1 ch2 ch3 ch0 ch1 ch2 ch3 basic single-width mode with x4 clocking option enabled basic single-width mode with x4 clocking option enabled unused channel unused channel serial rapidio serial rapidio basic single-width mode with x4 clocking option disabled basic single-width mode with x4 clocking option disabled ch0 ch1 ch2 ch3 ch0 ch1 ch2 ch3 basic single-width mode with x4 clocking option enabled basic single-width mode with x4 clocking option enabled serial rapidio serial rapidio basic single-width mode with x4 clocking option disabled basic single-width mode with x4 clocking option disabled basic single-width mode with x4 clocking option enabled basic single-width mode with x4 clocking option enabled
altera corporation 2?149 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?113 shows the recommended clocking for 12 transceiver channels across transc eiver banks 13, 14, and 15 in the ep2sgx90ef1152 device. figure 2?113. clocking recommendations to minimize transmitter channel-to-channel skew basic double-width mode use basic double-width mode for custom protocols that are not part of the pre-defined supported protocols, for example, pipe. with some restrictions, the following pcs blocks are available: transmitter phase compensation fifo buffer transmitter byte serializer inter-transceiver block (iq) clock bank13 four channels in basic x4 clocking mode pll_inclk pll_inclk bank14 four channels in basic x4 clocking mode bank15 four channels in basic x4 clocking mode pll_inclk inter-transceiver block (iq) clock refclk_b14
2?150 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes 8b/10b encoder word aligner rate matcher 8b/10b decoder byte deserializer byte ordering block receiver phase compensation fifo buffer the rate matcher is not available with the byte ordering block and vice versa. because the rate matcher removes one byte at a time, the ordering of the blocks changes if ra te matching occurs . the rate matcher is coupled with the 8b/10b code gr oups, which require the use of the 8b/10b encoder or decoder either in the pcs or pld logic array. pci express (pipe) mode pci express is an evolution of periph eral component interconnect (pci). pci is bandwidth-limited for today?s applications because it relies on synchronous single-ended type sign aling with a wide multi-drop data bus (refer to figure 2?114 ). clock and data-trace matching is required with pci. pci express uses differential serial signaling with an embedded clock to enable an effective through-put of 2 gbps per link to circumvent the limitations of pci. pci express operates in 1, 4, 8, 16, and 32 configurations and is also backward compatible with pci on a software and driver level. figure 2?114. pipe mode 1 stratix ii gx devices support the pipe standard in 1, 4, and 8 configurations. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer
altera corporation 2?151 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the stratix ii gx device has dedicated circuits to support the pci express protocol, including the following: 8b/10b encoder and decoder rate matcher, which supports a multi-crystal environment up to 300 ppm (600 ppm total) clock difference pipe interface (physical interface for pci express) receiver detection beacon transmit capability loopback inversion disparity control the phy state machines, except for rate matching, are not included in the transceiver. those state machines can be created in the pld logic. this mode of operation is called the pipe mode.the pipe mode has a separate reset sequence. refer to ?reset sequence for pipe mode? on page 2?218 for more information. f the equalizer dc gain value in the megawizard plug-in manager for pipe mode is set to a default value of 1. if the equalizer dc gain is controlled by the alt2gxb_reconfig controller, the rx_eqdcgain input to the alt2gxb_reconfig cont roller should be tied to ?01? to be pci e-compliant. refer to the alt2gxb megafunction user guide chapter in volume 2 of the stratix ii gx device handbook for more information. synchronization in pipe mode, the synchronizatio n automatically occurs when the receiver receives 4 good /k28.5/ commas and 16 good code groups. synchronization can be accomplished through the reception of four good pci express training sequences (ts1 or ts2) or four fast training sequences. figure 2?115 shows a state diagram of the pci-e synchronization.
2?152 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?115. pipe mode synchr onization state machine tables 2?32 and 2?33 describe the ts1 and ts 2 training sequences, respectively. a pci express fast traini ng sequence consists of a /k28.5/, followed by three /k28.1/ code group. if there is one code group error during the synchronization process, resynchronization must be performed. comma detect if data == comma kcntr++ else kcntr=kcntr loss of sync data= !valid data= comma data=valid; kcntr<3 kcntr = 3 synchronized data=valid data= !valid synchronized error detect if data == !valid ecntr++ gcntr=0 else if gcntr==16 ecntr- - gcntr=0 else gcntr++ ecntr = 17 ecntr = 0
altera corporation 2?153 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview table 2?32. pci express ts1 ordered set symbol number allowed values encoded values description 0 k28.5 comma code group for symbol alignment 1 0?255 d0.0?d31.7, and k23.7 link number with component 2 0?31 d0.0?d31.0, and k23.7 lane number within port 3 0?255 d0.0?d31.7 n_fts. the number of fast training ordered sets required by the receiver to obtain reliable bit and symbol lock. 4 2 d2.0 data rate identifier bit 0?reserved, set to 0 bit 1 = 1, generation 1 (2.5 gbps) data rate supported bit 2..7?reserved, set to 0 5 bit 0 = 0, 1 bit 1 = 0, 1 bit 2 = 0, 1 bit 3 = 0, 1 bit 4..7 = 0 d0.0, d1.0, d2.0, d4.0, and d8.0 training control bit 0?hot reset bit 0 = 0, deassert bit 0 = 1, assert bit 1?disable link bit 1 = 0, deassert bit 1 = 1, assert bit 1?loopback bit 2 = 0, deassert bit 2 = 1, assert bit 3?disable scrambling bit 3 = 0, deassert bit 3 = 1, assert bit 4..7?reserved bit 0 = 0, deassert set to 0 6?15 d10.2 ts1 identifier
2?154 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes table 2?33. pci express ts2 ordered set symbol number allowed values encoded values description 0 k28.5 comma code group for symbol alignment. 1 0?255 d0.0?d31.7, and k23.7 link number with component. 2 0?31 d0.0?d31.0, and k23.7 lane number within port. 3 0?255 d0.0?d31.7 n_fts. the number of fast training ordered sets required by the receiver to obtain reliable bit and symbol lock. 4 2 d2.0 data rate identifier bit 0?reserved, set to 0 bit 1 = 1, generation 1 (2.5 gbps) data rate supported bit 2..7?reserved, set to 0 5 bit 0 = 0, 1 bit 1 = 0, 1 bit 2 = 0, 1 bit 3 = 0, 1 bit 4..7 = 0 d0.0, d1.0, d2.0, d4.0, and d8.0 training control bit 0?hot reset bit 0 = 0, deassert bit 0 = 1, assert bit 1?disable link bit 1 = 0, deassert bit 1 = 1, assert bit 1?loopback bit 2 = 0, deassert bit 2 = 1, assert bit 3?disable scrambling bit 3 = 0, deassert bit 3 = 1, assert bit 4..7?reserved bit 0 = 0, deassert set to 0 6?15 d5.2 ts2 identifier
altera corporation 2?155 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview rate matching in pipe mode, the rate matcher suppo rts up to 300 ppm (600 ppm total) differences between the upstream transmitter and the receiver. the rate matcher looks for skip ordered sets , which usually contain a /k28.5/ comma followed by three /k28.0/ sk ip characters. the rate matcher deletes or inserts skip characters when necessary to prevent the rate matching fifo buffer from overflowing or underflowing. the rate matcher can delete skip charac ters on only one skip character in a consecutive cluster of skip characters. figure 2?116 shows an example of a pipe mode rate matcher de letion of two skip characters. figure 2?116. pipe mode with two dele tions (one deletion per cluster) the rate matcher can insert skip charac ters one insertion per skip cluster. there is no limit on the consecutive number of skip characters allowed per skip cluster. the stratix ii gx rate matcher in pipe mode has fifo buffer overflow and underflow protection. in the event of a fifo buffer overflow, the rate matcher deletes any data after the overflow condition to prevent fifo pointer corruption until the rate ma tcher is not full. in an underflow condition, the rate matcher inserts 9' h1fe (/k30.7/) until the fifo buffer is not empty. these measures ensure that the fifo buffer can gracefully exit the overflow/underflow conditio n without requiring a fifo reset. power state there are four supported power states in stratix ii gx devices: p0, p0s, p1, and p2. p0 is the normal power state. p0s is a low recovery time power state that is lower than p0. p1 is a lower power state than p0s and have higher latency to come out of this st ate. p2 is the lowest power state supported by this mode. k28.5 k28.0 k28.0 k28.0 dx.y k28.5 k28.0 k28.0 datain skip cluster skip cluster skip cluster skip cluster k28.5 k28.0 k28.0 dx.y k28.5 k28.0 dx.y dx.y dataout two skips deleted
2?156 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes the powerdn port transitions the transcei ver into different power states. the encoded value is shown in table 2?34 . the pipephydonestatus signal reacts to the powerdn request and pulses hi gh for one parallel clock cycle. there are specific functions that are performed at each of the power states. the power-down states are fo r pipe emulation. the transceiver does not go into actual power saving mode, with the exception of the transmitter buffer for el ectrical idle. this shou ldn?t matter because the power consumption for the pld logic is much greater than the transceiver power consumption. poweri ng down the transceiver does not save much when compared to the overall power consumption of the entire device. table 2?34 shows each power state and its function. there are two signals associated with the power states: tx_detectrxloopback and tx_forceelecidle . the tx_detectrxloopback signal controls whether the channel goes into loopback when the power state is in p0 or receiver detect when in p1 state. this signal does not have any affe ct in any other power states. the tx_forceelecidle signal governs when the transmitter goes into an electrical idle state. the tx_forceelecidle signal is asserted in p0s and p1 states and deasserted in p0 state. in p2 state, under normal conditions, the tx_forceelecidle signal is asserted and then deasserted when the beacon signal must be sent out, signifying the intent to exit the p2 power-down state. table 2?35 shows the behavior of the tx_detectrxloopback and tx_forceelecidle signals in the power states. table 2?34. power state functions and descriptions power state powerdn function description p0 2?b00 transmits normal data, transmits electrical idle, or enters into loopback mode. normal operation mode p0s 2?b01 only trans mits electrical idle. low recovery time power saving state p1 2?b10 transmitter buffer is powered down and can do a receiver detect while in this state. high recovery time power saving state p2 2?b11 transmits electrical idle or a beacon to wake up the downstream receiver. lowest power saving state
altera corporation 2?157 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview receiver status the pipe interface for pci express has a receiver status indicator that reports the status of the phy (pcs and pma). the receiver status is communicated to the pld logic by the 3-bit pipestatus port. this port enumerates the status as shown in table 2?36 . if more than one event occurs at the same time, the signal is resolved with the higher priority status.the skip character added and removed flags (3'b001 and 3'b010) are not supported. the pipestatus port may be encoded to 3b'001 and 3'b010, which should be ignored. it do es not indicate that a skip has been added or removed and should be considered the same as 3'b000? received data. if the upper mac laye r must know when a skip character was added or removed, altera recommends monitoring the number of skip characters received. the tran smitter should send three skip characters in a standard skip-ordered set. table 2?35. power states and functions allowed in each power state power state tx_detectrxloopback tx_forceelecidle p0 0: normal mode 1: data path in loopback mode 0: must be deasserted. 1: illegal mode p0s don?t care 0: illegal mode 1: must be asserted in this state p1 0: electrical idle 1: receiver detect 0: illegal mode 1: must be asserted in this state p2 don?t care deasserted in this state for sending beacon. otherwise asserted. table 2?36. pipestatus description and priority pipestatus description priority 3?b000 received data 6 3?b001 one skip character added (not supported) n/a 3?b010 one skip character removed (not supported) n/a 3?b011 receiver detected 1 3?b100 8b/10b decoder error 2 3?b101 elastic buffer overflow 3 3?b110 elastic buffer underflow 4 3?b111 received disparity error 5
2?158 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes an additional status port, rx_pipedatavalid , indicates that the data on the rx_dataout port is valid. this signal is equivalent to the rx_syncstatus port. the rx_pipedatavalid port operates in parallel with the pipestatus signal. receiver detect the receiver detect circuitry is available for pci express applications. the receiver detect circuitry is only available in the p1 power state and is set through the tx_detectrxloopback port and requires a 125 mhz fixedclk signal. in the p1 power state, a high on tx_detectrxloopback port triggers the receiver detect circuitry to alter the transmitter buffer common mo de voltage. the sudden change in common mode voltage effectively appears as a step voltage at the serial link. if a receiver (that complies to pci-express input impedance requirements) is present at the far en d, the time constant of the step voltage is higher. if a receiver is not present or powered down, the time constant of the step voltage is lower. the receiver detect circuitry snoops the serial line ( tx_dataout ) for the time constant of the step voltage to detect the presence of the receiver at the far end. upon receiver detect, the pipestatus port indicates if a receiver is detected or not. there is some latency after asserting the tx_detectrxloopback signal, before the receiver detection is indicated. the tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to the tx_detectrxloopback to ensure that the transmitter buffer is tri-stated. beacon transmission the beacon is an optional 30 khz to 500 mhz in-band signal that wakes the receiver from a p2 power state. this signal is optional, and the stratix ii gx device does not have dedicated beacon transmission circuitry. the stratix ii gx device suppo rts the transmission of the beacon signal through a 10-bit encoded code word that has a five 1?s pulse (for example, k28.5). because the beacon signal is a pu lse that ranges from 2 ns to 500 ns, sending out a k28.5 at 2.5 gbps meets the lower requirement with its five 1?s pulse. (though other 8b/10b co de groups might meet the beacon requirement, this docume nt uses the k28.5 control code group as the beacon signal.) the beacon transmissi on takes place only in the p2 power state. the tx_forceelecidle port controls when the transmitter is in electrical idle or not. this port must be deasserted in order to transmit the k28.5 code group.
altera corporation 2?159 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview compliance pattern tr ansmission support pci express has an option to transmit a compliance pattern for testing purposes. the compliance pattern must be transmitted with a negative disparity. in pipe mode, you set the negative disparity with the tx_forcedispcompliance port. asserting the tx_forcedispcompliance port sets the associated byte in the tx_datain port to be encoded, by the 8b/10b encoder, to a negative disparity. if a wider pld interface is used, only the lsbyte is encoded with a negative disparity. the tx_forcedispcompliance port must be deasserted after the firs t byte of the compliance pattern is clocked into the transceiver. the compliance pattern generator is not part of the stratix ii gx transceiver and must be designed using the pld logic. however, you can set the beginning of the disparity of the compliance pattern to negative by asserting the tx_forcedispcompliance port. ntfs fast recovery ip (nfri) the pci-e specification fast training sequences (fts) are used for bit and byte synchronization to transition from l0s state to l0 (stratix ii gx p0s to p0) power states. the pci-e base sp ecification states that the required time period for this transaction be within 16 ns to 4 us. currently, the default pipe alt2gxb settings do not meet these requirements. therefore, altera developed ntfs fast recovery ip (nfri), a soft ip that enables the receiver to transition from the p0s to the p0 state within 4 us. the quartus ii software creates this nfri soft ip when the enable fast recovery mode option is selected in the alt2gxb megawizard plug-in manager. this option is availabl e from the quartus ii software version 6.0, sp1. fts ordered sets are used by the receiver to detect exit from electrical idle (eidle) and align the receiver?s bi t/symbol receiver circuitry to the incoming data. if the fts time period (4 us) expires prior to the receiver obtaining alignment and deskew on al l lanes, the receiver transitions to the recovery state (the pci express [pipe] alt2gxb performs only word alignment. the deskew operation should be done in the user logic). following the electrical idle condition, the stratix ii gx device requires 255 fts sequences to recover valid data.
2?160 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes pipe mode default settings in the pipe mode default settings, th e receiver pll is in automatic lock mode. the pll moves from lock to reference mode to lock to data mode based on the rx_freqlocked being asserted. for the rx_freqlocked signal to be asserted, the cru pll clock should be within the ppm threshold settings of th e cru reference clock. the ppm detector checks the ppm th reshold settings by comparing the cru pll clock outp ut with the reference cl ock for approximately 32768 clock cycles. for a 250 mhz pld in terface clock frequency, this comparison time period exceeds 4 us, which violates the pci-e specification. the ntfs soft ip overcomes the restriction. enable fast recovery mode option when you select the enable fast recovery mode option, consider the following: nfri is created in the pld side for each pci-e channel nfri is a soft ip, so it consumes logic resources this block is self-contained, so no input/output ports are available to access the soft ip the nfri takes control of the rx_locktorefclk and rx_locktodata signals on the alt2gxb transceiver an d therefore avoids the delay of the ppm detector discussed in ?pipe mode default settings? on page 2?160 . 1 if you select the rx_locktorefclk and rx_locktodata signals in the megawizard plug-in manager, the enable fast recovery mode option cannot be used. ntfs fast recovery ip (nfri) in software versions before quartus ii 7.2 this section discusses the solution to control the sequence of events around the results of the 4 us timing requirement during the p0s to p0 state transition. this is only applic able for software versions before quartus ii 7.2 with the transceiver channel configured in pci express (pipe) mode and the optional fast recovery mode enabled in the alt2gxb megawizard. use this for synchronous and non-synchronous pci express (pipe) modes. the solution requires that you use the data in user logic in the core only if the data is valid. 1 in the quartus ii software version 7.2, the solution is built into the software when you enable the fast recovery mode option in the alt2gxb megawizard.
altera corporation 2?161 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview some logic can be added per channe l which controls the circuit with different possible results. the proposed logic in the pld is referred to as nfri_pld_logic . the output signals generated by the nfri_pld_logic are referred to as pipeelecidle_pld and pipedatavalid_pld . figure 2?117 shows the top-level block diagram of the overall system. figure 2?117. nfri_pld_logic top level diagram note to figure 2?117 : (1) this signal is also provided to the user logic. 1 the proposed logic runs with the tx_clkout . to reset this logic, use the same signal that connects to the tx_digitalreset port of the pci-express (pipe) alt2gxb instance. the nfri_pld_logic contains: a state machine sequence to generate the pipeelecidle_pld and pipedatavalid_pld signals. 4us_timer : a user-implemented timer in the pld logic to count 4 us. this timer represents the maximum time period to transition from p0s to p0 per the protocol specification. 3.2us_timer : a user-implemented timer in the pld logic to count 3.2 us. this timer represents the mi nimum time period to wait before looking for valid data. alt2gxb rx_dataout, rx_ctrldetect, and other status/control signals nfri_pld_logic user logic rx_ctrldetect (1) rx_dataout (1) pipedatavalid pipeelecidle rx_signaldetect (1) tx_clkout (1) tx_digitalreset (1) pipedatavalid_pld pipeelecidle_pld
2?162 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes sequence to generate pipeelec idle_pld and pipedatavalid_pld signals to generate the pipeelecidle_pld and pipedatavalid_pld signals, follow these steps: 1. when you detect eios ordered set or the falling edge of rx_signaldetect : assert pipeelecidle_pld deassert pipedatavalid_pld 2. wait 250 ns. this is the minimum time required for rx_signaldetect to get deasserted when there is no valid signal at the receive input. 3. wait for rx_signaldetect to get asserted. 4. start the 3.2us_timer and 4us_timer . ignore rx_signaldetect during this step. 5. wait for the 3.2us_timer to expire. ignore rx-signaldetect during this step. 6. if one fts ordered set is received and the 4us_timer has not expired: set pipeelecidle_pld to the pipeelecidle value (that is, forward the pipeelecidle value from the alt2gxb to the user logic). assert pipedatavalid_pld . reset and pause the 3.2us_timer and 4us_timer . return to step 1. 7. if rx_signaldetect gets deasserted and the 4us_timer has not expired: reset and pause the 3.2us_timer and 4us_timer . set pipeelecidle_pld to the pipeelecidle value (that is, forward the pipeelecidle value from the alt2gxb to the user logic). set the pipedatavalid_pld to the pipedatavalid value (that is, forward the pipedatavalid value from the alt2gxb to the user logic). return to step 1.
altera corporation 2?163 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 8. if the 4us_timer has expired: reset and pause the 3.2us_timer and 4us_timer . set the pipeelecidle_pld to the pipeelecidle value (that is, forward the pipeelecidle value from the alt2gxb to the user logic). set pipedatavalid_pld to the pipedatavalid value (that is, forward the pipedatavalid value from the alt2gxb to the user logic). return to step 1.
2?164 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?118 shows the nfri_pld_l ogic state machine. figure 2?118. nfri_pld_l ogic state machine notes to figure 2?118 : (1) forward the alt2gxb value to the nfri_pld_logic output. for example, forward the pipedatavalid value from the alt2gxb to the pipedatavalid_pld for use in user logic. (2) after the 3.2us_timer expires, it is important to reset rx_digitalreset for two parallel clock cycles. for example, now that correct data is coming through, the fi fo should be cleared and the pointers reset to the middle. following this reset, look for the fts ordered set. for other cases to assert rx_diditalreset , refer to ?reset sequence for pipe mode? on page 2?218 . start wait for eios or falling edge of rx_signaldetect . eios or falling edge detected. assert pipeeleidle_pld . de-assert pipedatavalid_pld . wait 250 ns and then wait until rx_signaldetect is asserted. rx_signaldetect asserted. start 3.2 us and 4 us timers. wait for the 3.2 us timer to expire and ignore rx_signaldetect . 3.2 us timer expires. assert rx_digitalreset for two parallel clock cycles (2) . wait for rx_signaldetect de-asserts, or an fts ordered set or the 4 us timer expires. one fts ordered set received and the 4 us timer not expired. assert pipedatavalid_pld . set pipeeleidle_pld to pipeeleidle value (1) . wait for the 4 us timer to expire or rx_signaldetect de-asserts. "4 us timer expires" or " rx_signaldetect de-asserts and 4 us timer not expired". "4 us timer expires" or " rx_signaldetect de-asserts and 4 us timer not expired". reset 3.2 us and 4 us timers. set pipeeleidle_pld to pipeeleidle value (1) . set pipedatavalid_pld to pipedatavalid value (1) .
altera corporation 2?165 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?119 shows the timing diagram for the signals generated by the nfri_pld_logic. figure 2?119. timing for the signals g enerated by the nfri_pld_logic low-latency pipe mode the stratix ii gx receiver data path employs a rate match fifo in pipe mode to compensate up to 300 ppm difference between the upstream transmitter and the local receiver re ference clock. the rate match fifo adds a latency of 12-16 parallel cloc k cycles to the link. the low-latency pipe mode allows bypassing the rate match fifo in synchronous systems that derive the transmitter and receiv er reference clocks from the same source. you can bypass the rate match fifo by not selecting the enable rate match fifo option in the alt2gxb megawizard plug-in manager. you can bypass the rate match fifo in single-lane (1), four-lane (4) and eight-lane (8) pipe modes. in normal pipe mode, the receiver blocks following the rate match fifo are clocked by tx_clkout (1 mode) or coreclkout (4 and 8 modes) of the local port. in low-latency mode, since the rate match fifo is bypassed , these receiver blocks are clocked by the recovered clocks of the resp ective channels. as a result, the channels in a multi-lane (4 or 8) low-latency pipe mode are unbonded. except for the rate match fifo bein g bypassed and the resulting changes in transceiver internal clocking, th e low-latency pipe shares the same data path and state machines as th e normal pipe mode. however, some features supported in normal pipe mode are not supported in low-latency pipe mode. rx_dataout pipedatavalid pipeelecidle rx_signaldetect pipeelecidle_pld pipedatavalid_pld eios fts forward the pipeelecidle from the alt2gxb to the user logic forward the pipedatavalid from the alt2gxb to the user logic 3.2us 4us
2?166 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes 1 unlike regular pipe mode, th e quartus ii software in low-latency pipe mode does not automatical ly clock the transmitter and receiver phase compensation fifo write and read clock with the tx_clkout signal from channel 0. you must use the shared clock grouping or 0 ppm clock grouping assignments to manually clock the phase compensation fifos. refer to ?pld-transceiver interfac e clocking? on page 2?119 for more information on clock grouping. pipe reverse parallel loopback in normal pipe mode, if the transceiver is in p1 power state, a high value on the tx_rxdetectloop signal forces a reverse parallel loopback as discussed in ?pci express pipe reverse parallel loopback? on page 2?206 . parallel data at the output of the receiver rate match fifo gets looped back to the input of the transmitter serializer. in low-latency pipe mode, since the rate match fifo is bypassed, this feature is not supported. a high value on the tx_rxdetectloop signal, when the transceiver is in p1 power state, will not force it to perform reverse parallel loopback. link width negotiation in normal multi-lane (4 and 8) pipe configuration, the receiver phase compensation fifo control signals (for example, write/read enable ) are shared among all lanes within the link. as a result, all lanes are truly bonded and the lane-lane skew meet s the pci express specification. in low-latency pipe configuration, th e receiver phase compensation fifo of individual lanes do not share cont rol signals. the write port of the receiver phase compensation fifo of each lane is clocked by its recovered clock. as a result, the lanes within a link are not bonded. you should perform external lane de-skewing to ensure proper link width negotiation. pipestatus signal since the rate match fifo is bypassed in low-latency pipe mode, status signal combinations related to the rate match fifo on pipestatus[2:0] port become irrelevant and must not be interpreted ( table 2?37 ). table 2?37. normal and low-latency pipe status (part 1 of 2) pipestatus[2:0] normal pipe low-latency pipe 000 received data ok received data ok 001 not supported not supported
altera corporation 2?167 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview xaui mode this section briefly introduces the xaui standard (refer to figure 2?120 ) and the code groups and ordered sets associated with this self-managed interface. for full details on the xaui standard, refer to clause 47 and 48 in the 10 gigabit ethernet standard (ieee 802.3ae). stratix ii gx devices contain embedded macros dedicated to the xaui protocol, including synchronization, channel deskew, rate matching, xgmii extender sublayer (xgxs) to 10 gigabit media independent interface (xgmii) and xgmii to xgxs code-group conversion macros. for higig, the stratix ii gx xaui da ta rate protocol has been extended from 3.125 gbps up to 3.75 gbps. for hi gig data rates, select the xaui protocol and type in the increased data rate. the xaui standard is an optional sel f-managed interface that is inserted between the reconciliation sublayer and the phy layer to transparently extend the physical reach of xgmii. 010 not supported not supported 011 receiver detected receiver detected 100 8b/10b decoder error 8b/10b decoder error 101 elastic buffer overflow not supported 110 elastic buffer underflow not supported 111 received disparity error received disparity error table 2?37. normal and low-latency pipe status (part 2 of 2) pipestatus[2:0] normal pipe low-latency pipe
2?168 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?120. xaui mode xaui addresses several physical limitations of xgmii. xgmii signaling is based on the hstl class i single -ended io standard, which has an electrical distance limitation of approximately 7 cm. xaui utilizes a low-voltage differential signaling method, so the electrical limitation is increased to approximately 50 cm. another advantage of xaui is the simplification of backplane and boar d trace routing. xgmii is composed of 32 transmit channels, 32 receive ch annels, 1 transmit clock, 1 receive clock, 4 transmitter control characters , and 4 receive control characters for a total of a 74-pin wide interface. xaui consists of 4 differential transmitter channels and 4 differential receiver channels for a total of a 16-pin-wide interface. this reduction in pin count significantly simplifies the routing process in the layout design. figure 2?121 shows the relationships between the xgmii and xaui layers. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer
altera corporation 2?169 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?121. xgmii and xa ui relationship the xgmii interface consists of four la nes of 8 bits. at the transmit side of the xaui interface, the data and control characters are converted within the xgxs into an 8b/10b encoded data stream. each data stream is then transmitted across a single differential pair running at 3.125 gbps (3.75 gbps for higig). at the xaui receiver, the incoming data is decoded and mapped back to the 32 bit xgmii fo rmat. this provides a transparent extension of the physical reach of the xgmii and also reduces the interface pin count. xaui functions as a self-managed interface because code group synchronization, channel deskew, and clock domain decoupling is handled with no upper layer support requirements. this functionality is osi reference model layers application presentation session transport network data link physical pma pmd medium 10 gb/s xgmii xgmii mdi xaui optional xgmii extender phy mac (optional) llc lan csma/cd layers higher layers media access control (mac) medium dependent interface (mdi) physical coding sublayer (pcs) physical layer device (phy) logical link control (llc) physical medium attachment (pma) physical medium dependent (pmd) 10 gigabit attachment unit interface (xaui) 10 gigabit media independent interface (xgmii) xgmii extender sublayer (xgxs) reconciliation mac xgxs xgxs pcs
2?170 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes based on the pcs code groups that ar e used during the ipg time and idle periods. pcs code groups are mappe d by the xgxs to xgmii characters specified in table 2?38 . figure 2?122 shows an example of the mapping between xgmii characters and the pcs code groups that are used in xaui. the idle characters are mapped to a pseudo-r andom sequence of /a/, /r/, and /k/ code groups. figure 2?122. xgmii character to pcs code-group mapping table 2?38. xgmii character to pcs code-group mapping xgmii txc xgmii txd (1) pcs code group description 0 00 through ff dxx.y normal data transmission 1 07 k28.0, k28.3, or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1 fb k27.7 start 1 fd k29.7 terminate 1 fe k30.7 error 1 other value reserved xgmii character 1 any other value k30.7 deleted xgmii character note to table 2?38 : (1) values in txd column are in hexadecimal. dp t/rxd<7:0> |s ddd - - - - - - - - - - - - d dp t/rxd<15:8> |dp ddd t dp t/rxd<23:16> |dp ddd | dp t/rxd<31:24> | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dp ddd ddd ddd ddd ddd | lane 0 k r s ak rr lane 1 k r dp ak rr lane 2 k r k a k rr lane 3 k r k a k k k k k r r r r rr dp ddd - - - - - - - - - - - - d dp ddd t dp dp dd dp dp d d dd ddd ddd ddd ddd xgmii pcs
altera corporation 2?171 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the pcs code-groups are sent via pcs ordered sets. pcs ordered sets consist of combinations of special and data code groups defined as a column of code groups. these ordere d sets are composed of four code groups beginning in lane 0. table 2?39 lists the defined idle ordered sets (||i||) that are used for the se lf-managed properties of xaui. synchronization ||k|| (word aligner) xaui uses an embedded cl ocking scheme that re-t imes the data that can potentially alter the code-group boun dary. the boundaries of the code groups are re-aligned through a synchronization process specified in clause 48 of the ieee p802.3ae standard, which states that synchronization is achieved upon th e reception of four /k28.5/ commas. each comma can be followed by any number of valid code groups. invalid code groups are not allowed during the synchronization stage. when you configure stratix ii gx de vices to the xaui protocol, the built-in pattern detector, word aligner, and xaui state machines adhere to the pcs synchronization specification. after all the conditions for synchronization have been met, the rx_syncstatus signal is asserted and only de-asserts if synchronization is lost. table 2?39. defined idle ordered set code ordered set number of code groups encoding ||i|| idle substitute for xgmii idle ||k|| synchronization column 4 /k28.5/k28.5/k28.5/k28.5 ||r|| skip column 4 /k28.0/k28.0/k28.0/k28.0 ||a|| align column 4 /k28.3/k28.3/k28.3/k28.3
2?172 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?123 shows the pcs synchronization state diagram specified in clause 48 of the ieee p802.3ae. figure 2?123. ieee 802.3ae pcs sy nchronization state diagram reset + (signal_detectchange *pudi) (signal_detect=ok)* pudi([/comma/] pudi([/comma/] pudi([/comma/] pudi([/comma/] * ? [/invalid/] pudi([/comma/] * ? [/invalid/] pudi([/comma/] pudi([/comma/] * ? [/invalid/] pudi( ? [/invalid/])* good_cgs 3 pudi( ? [/invalid/]) pudi( ? [/invalid/])* good_cgs 3 pudi( ? [/invalid/])*good_cgs = 3 pudi( ? [/invalid/])*good_cgs = 3 pudi( ? [/invalid/]) pudi([/invalid/]) pudi([/invalid/]) pudi([/invalid/]) pudi([/invalid/]) pudi * signal_detect=fail)+ pudi(![/comma/]) loss_of_sync lane_sync_status ? fail enable_cgalign ? true sudi comma_detect_1 enable_cgalign ? false sudi sync_acquired_1 lane_sync_status ? ok sudi sync_acquired_2 good_cgs ? 0 sudi sync_acquired_3 good_cgs ? 0 sudi sync_acquired_4 good_cgs ? 0 sudi pudi([/invalid/]) pudi( ? [/invalid/]) pudi([/invalid/]) pudi([/invalid/]) pudi([/invalid/]) pudi([/invalid/]) pudi( ? [/invalid/]) pudi([/invalid/]) sync_acquired_2a good_cgs ? good_cgs + 1 sudi sync_acquired_3a good_cgs ? good_cgs + 1 sudi sync_acquired_4a good_cgs ? good_cgs + 1 sudi comma_detect_2 sudi comma_detect_3 sudi 1 pudi( ? [/invalid/])* good_cgs 3 pudi( ? [/invalid/])*good_cgs = 3 2 2 1
altera corporation 2?173 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview channel alignment ||a|| (deskew) it is possible for ordered sets to be misaligned with respect to one another because of board skew or differen ces between the independent clock recoveries per serial lane . channel alignment, also referred to as deskew or channel bonding, realigns the orde red sets by using the alignment code group, referred to as /a/. the /a/ code group is transmitted simultaneously on all four lanes, constituting an ||a|| ordered set, during idles or ipg. xaui receivers use these code groups to resolve any lane-to-lane skew. skew between the lanes can be up to 40 ui (12.8 ns) as specified in the standard, which relaxes the board design constraints. figure 2?124 shows lane skew at the receiver input and how the deskew circuitry uses the /a/ code group to deskew the channels. figure 2?124. lane deskew with the /a/ code group stratix ii gx devices manage xaui ch annel alignment with a dedicated deskew macro that consists of a 16-word-deep fifo buffer that is controlled by a xaui deskew state machine. the xaui deskew state machine first looks for the /a/ code group within each channel. when the xaui deskew state machine detects /a/ in each channel, the deskew fifo buffer is enabled. the desk ew state machine now monitors the reception of /a/ code groups. when four aligned /a/ code groups have been received the rx_channelaligned is asserted. the deskew state machine continues to monitor the reception of /a/ code groups and de-asserts the rx_channelaligned signal if alignment conditions are lost. this built-in deskew macro is only enabled for the xaui protocol. figure 2?125 shows the pcs deskew state diagram specified in clause 48 of the ieee p802.3ae. lanes are deskewed by lining up the "align"/a/, code groups lanes skew at receiver input a lane 0 k k r a k r r k k k rr lane 1 k k r a k r r k k k rr lane 0 k k r k r r k k k rr lane 1 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr
2?174 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?125. ieee 802.3ae pcs deskew state diagram clock compensation ||r|| (rate matcher) xaui can operate in multi-crystal environments, which can tolerate frequency variations of 100 ppm be tween crystals. stratix ii gx devices contain embedded circuitry to perform clock rate compen sation, which is achieved by inserting or removing the pcs skip code group (/r/) from the ipg or idle stream. this proces s is called rate matching and is sometimes referred to as clock rate compensation. the rate matcher in stratix ii gx devices consists of a 12-word-deep fifo buffer along with control logic that you can configure to support xaui, gige, or custom modes. in xaui mode the controller begins to write data into the fifo buffer whenever the rx_channelaligned signal is asserted. within the control logic ther e is a fifo counter that keeps track of the read and write executions. wh en the fifo counter reaches a value of greater than nine, the receivers delete the /r/ code-group reset + (sync_status=fail * sudi) sync_status ok * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi sudi(![/||a||/]) loss_of_alignment align_status ? fail enable_deskew ? true audi align_detect_1 enable_deskew ? false audi align_detect_2 audi align_detect_3 audi 3 !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align_acquired_1 enable_deskew ? false audi align_acquired_2 audi align_acquired_3 audi 1 2 3 !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align_acquired_4 audi 2 sudi(![/||a||/]) 1 sudi(![/||a||/])
altera corporation 2?175 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview simultaneously across all channels during ipg or idle conditions. if the fifo counter is less than five, the receivers insert the /r/ code-group simultaneously across all channels during ipg or idle conditions. 1 this circuitry compensates for 100 ppm frequency variations. pcs code group to xgmii character mapping in xaui mode, the 8b/10b decoder in stratix ii gx devices is controlled by a global receiver state machine that maps various pcs code groups into specific 8-bit xgmii codes. table 2?40 lists the pcs code group to xgmii character mapping. xgmii character to pcs code-group mapping in xaui mode, the 8b/10b encoder in stratix ii gx devices is controlled by a global transmitter state mach ine that maps various 8-bit xgmii codes to 10-bit pcs code groups. this state machine complies with the ieee 802.3ae pcs transmit specification. figure 2?126 shows the pcs transmit source state diagram specifie d in clause 48 of the ieee p802.3ae. table 2?40. pcs code group to xgmii character mapping xgmii rxc xgmii rxd (1) pcs code group description 0 00 through ff dxx.y normal data transmission 1 07 k28.0, k28.3, or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1 fb k27.7 start 1 fd k29.7 terminate 1 fe k30.7 error 1 fe invalid code group received code group note to table 2?40 : (1) values in rxd column are in hexadecimal.
2?176 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?126. ieee 802.3ae pcs transmit source state diagram send_random_k tx_code_group<39:0> ? ||k|| send_random_r tx_code_group<39:0> ? ||r|| send_random_a tx_code_group<39:0> ? ||a|| a_cnt 0 * cod_sel=1 a_cnt 0 * cod_sel=1 a_cnt 0 * cod_sel=1 a_cnt=0 a_cnt=0 a_cnt 0 * cod_sel=1 !q_det * cod_sel=1 q_det q_det !q_det !q_det * cod_set=1 a b b b a a b a cod_set=1 cod_set=1 b a pudr send_k tx_code_group<39:0> ? ||k|| next_ifg ? a (next_ifg + a_cnt 0) next_ifg = a_cnt 0 pudr send_a tx_code_group<39:0> ? ||a|| next_ifg ? k send_q tx_code_group<39:0> ? tqmsg q_det ? k pudr pudr send_q if tx=||t|| then cvtx_terminate tx_code_group<39:0> ? encode(tx) !reset !(tx=||idle|| + tx=||q|| pudr pudr send_random_q tx_code_group<39:0> ? tqmsg q_det ? false pudr reset uct uct
altera corporation 2?177 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview table 2?41 lists the xgmii character to pcs code-group mapping. gige mode the gigabit media independent interfac e (gmii) is an intermediate, or transition, layer that interfaces va rious mediums with the media access control (mac) in a gige system (refer to figure 2?127 ). the gmii is divided into three sublayers: the pcs, the pma, and the physical medium dependent (pmd) layers. gmii offers data rates up to 1000 mbps at either half- or full-duplex modes. table 2?41. xgmii character to pcs code-group mapping xgmii txc xgmii txd (1) pcs code group description 0 00 through ff dxx.y normal data transmission 1 07 k28.0, k28.3, or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1 fb k27.7 start 1 fd k29.7 terminate 1 fe k30.7 error 1 other value reserved xgmii character 1 any other value k30.7 invalid xgmii character note to table 2?41 : (1) values in txd column are in hexadecimal.
2?178 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?127. gige mode the pcs sublayer provides synchronization, encoding and decoding, and rate matching services to the ma c. the pcs also provides auto negotiation to the network to negoti ate speeds, carrier, and collision detect signals. the pma sublayer provides the pcs with a media-independent interface that a variety of serial physical me dia can be connected to. this layer handles the serialization and deserialization of the data. the pmd sublayer defines actual physical attachment, such as connectors for different media types. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer
altera corporation 2?179 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?128 shows the gmii position relative to the osi reference model. figure 2?128. gmii position relative to the osi reference model the stratix ii gx transceiver can be us ed for the pcs and the pma layers of the gmii. stratix ii gx devices in gige mode use the 8b/10b encoder/decoder, rate matcher, and synchronizer built-in hard macros. the rate matcher and synchronizer have a dedicated state machine governing their functions. this state machine is only active in gige mode. table 2?42 shows the code groups used in the gige protocol. if required for your design, you must implemen t the remaining functions of the pcs?auto negotiation, collision detect, and carrier detect?in user logic or external circuits. osi reference model layers application presentation session transport network data link physical medium gmii 1000 base-x phy mac (optional) llc lan csma/cd layers higher layers reconciliation mac pcs pma pmd table 2?42. gige code groups (part 1 of 2) code ordered set number of code groups encoding /c/ configuration alternating /c1/ and /c2/ /c1/ configuration 1 4 /k28.5/d21.5/ config_reg (1)
2?180 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes synchronization (word aligner) synchronization is required in gige mode to align the byte boundary of the receiver to the byte boundary of the transmitter, because the stratix ii gx transceiver block uses a non-source-synchronous serial stream. to correctly align the byte boundary at the receiver, a unique synchronization pattern must be rece ived that does not occur between any dx.y and/or kx.y code combinations. a /k28.5/ 10-bit comma is used for this purpose. synchronization is achieved when th e receiver sees three consecutive ordered sets. an ordered set defined for synchronization is a /k28.5/ comma followed by any odd number of valid /dx.y/ code (/dx.y/ denotes any valid data code group). although you can have a number of synchronization patterns based on the synchronization rule, three /k28.5/ followed by one /dx.y/ code is the fastest synchronization pattern. once the synchronization is achieved, the state machine considers a bad code group received ( cgbad ) if one of the following two conditions are met: the incoming code group has a disparity error or a code group violation the incoming code group is a comma character and rx_even=true . this condition occurs when an even number of non-comma code groups are received between two comma code groups. /c2/ configuration 2 4 /k28.5/d2.2/ config_reg (1) /i/ idle correcting /i1/, preserving /i2/ /i1/ idle 1 2 /k28.5/d5.6 /i2/ idle 2 2 /k28.5/d16.2 encapsulation /r/ carrier_extend 1 /k23.7/ /s/ start_of_packet 1 /k27.7/ /t/ end_of_packet 1 /k29.7/ /v/ error_propagation 1 /k30.7/ note to table 2?42 : (1) two data code groups representing the config_reg value. table 2?42. gige code groups (part 2 of 2) code ordered set number of code groups encoding
altera corporation 2?181 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview gige mode requires a special synchr onization sequence that follows the ieee 802.3 gmii pcs synchr onization specification ( figure 2?129 ). figure 2?129. synchronization state machine diagram power_on=true+mr_main_rest=true + (signal_detectchange=true + mr_loopback=false +pudi) (signal_detect=ok+mr_loopback=true)* * pudi([/comma/] pudi([/|dv|/] rx_even=false+pudi([/comma/] pudi(![/comma/] * ? [/invalid/] pudi([/|dv|/] cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood cggood pudi(![/|dv|/] pudi(![/|dv|/] [pudi * signal_detect=fail + mr_loopback=false] + pudi(![/comma/]) loss_of_sync sync_status ? fail rx_even ? ! rx_even sudi comma_detect_1 rx_even ? true sudi sync_acquired_2 rx_even ? ! rx_even sudi good_cgs ? 0 sync_acquired_3 sync_acquired_4 cgbad cgbad cggood cgbad cgbad cggood cgbad cgbad cgbad sync_acquired_2a sync_acquired_3a sync_acquired_4a acquire_sync_1 sudi comma_detect_2 sudi 2 cggood *good_cgs = 3 cggood *good_cgs = 3 3 3 2 pudi(![/comma/] * ? [/invalid/] rx_even ? true rx_even=false+pudi([/comma/] cgbad cgbad acquire_sync_2 sudi rx_even ? ! rx_even pudi(![/|dv|/] comma_detect_3 sudi rx_even ? true pudi([/|dv|/] sync_acquired_1 sudi sync_status ? ok rx_even ? ! rx_even rx_even ? ! rx_even rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1
2?182 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes gige transmitter synchronization the transmitter must send out the gi ge synchronization sequence to synchronize the target receiver. stratix ii gx devices do not contain a built-in macro that provides this fu nction upon power-up or reset. you must implement this function in user logic to send out a /k28.5/, /dx.y/, /k28.5/, /dx.y/, /k28.5/, /dx.y/ sequence. figure 2?130 shows an example of the gige synchronization pattern. although the example shows one d0.0 (8'h00) as the /dx.y/ code, any /dx.y/ and any odd number of /dx.y/ can be used. figure 2?130. gige synchroni zation transmit pattern gige receiver synchronization you must pre configure the receiver with a k28.5 (10'b0101111100 or 10'b1010000011) word align pattern ( align_pattern = 0101111100 or align_pattern = 1010000011). the align_pattern_length must be set to 10 even though a 7-bit comma string (7'b0011111 as a comma- or 7'b1100000 as a comma+) is allowed as sp ecified in ieee 802.3. this 7-bit comma is located within the /k28.1/ , /k28.5/, and /k28.7/ code groups. using a 10-bit /k28.5/ helps prevent a 7-bit comma from being detected across boundaries when a /k28.7/ code is followed by a /k28.x/, /d3.x/, /d3.x/, /d11.x/, /d12.x/, /d19.x/, /d20.x/, or /d28.x/, where x is a value from 0 to 7 ( figure 2?131 ). figure 2?131. cross boundary 7-bit comma when a /k 28.7/ is followed by a /k28.5/ code group gige synchronization pattern gige synchronization pattern 00 bc 00 bc 00 bc 00 8d tx_dataout[7..0 ] clock tx_ctrlenable a4 0 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 k28.7 k28.5 7-bit comma- 7-bit comma+ 7-bit comma-
altera corporation 2?183 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the receiver outputs a k28.4 ( 8'h9c + rx_ctrldetect ) at the rx_dataout port and de-asserts the rx_syncstatus (1'b0) signal when the receiver is not synchronized . once synchronized, the receiver asserts the rx_syncstatus signal (1'b1). this sign al is aligned with the first valid data re ceived from the rx_dataout port. figure 2?132 shows the receiver sync hronization waveform. the rx_syncstatus port goes high when synchronization is complete, indicating that the data is valid. in figure 2?132 , d1 is the first valid data. figure 2?132. synchronization complete the receiver remains synchronized until it detects a string of bad code groups or is reset. a bad code group is defined by the ieee 802.3 standard as four invalid code groups separated by less than three valid code groups. if the receiver detects a bad code group or is reset, the rx_syncstatus signal goes high, then low and a /k28.4/ appears on the rx_outrx_dataout port. idle generation in gige mode, any /dx.y/ followin g a /k28.5/ comma is replaced by the transmitter with either a /d5. 6/ (8'hc5) or a /d16.2/ (8'h50) depending on the current running disparity, except when the data following the /k28.5/ is /d21.5/ (8'h b5) or /d2.2/ (8'h42). this ensures the generation of the /i1/ (/k28.5/, /d5.6/) and /i2/ (/k28.5/, /d16.2/) ordered sets and to allows the configuration ordered sets /c1/ (/k28.5, /d21.5/) and /c2/ (/k28.5/, /d2.2/) to be received. if the running disparity before the idle ordered set is positive, a /i1/ is chosen. if the running disparity is negative, an /i2/ is chosen. the disparity at the end of an /i1/ is the opposite of th at at the beginning of the /i1/. the disparity at the end of an /i2/ is the same as the beginning running disparity (right before the idle code). this ensures a negative running disparity at the end of an idle orde red set. a /kx.y/ following a /k28.5/ is not replaced. clock rx_dataout[7..0] rx_syncstatus xx xx xx d1 d2 d3 d4 d5
2?184 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?133 shows the input data codes versus the output data codes. /d14.3/, /d24.0/, and /d15.8/ were re placed by /d5.6/ or /d16.2/ (for /i1/, /i2/ ordered sets) and /d21.5/ (part of the /c2/ order set) was not replaced. figure 2?133. example of the input data codes versus the output data codes rate matching (rate matcher) gige can operate in a multi crystal environment, so rate matching is necessary to compensate for the freq uency variations from different crystals. stratix ii gx devices co ntain a built-in rate matcher (12-word-deep fifo buffer with contro l logic) that can tolerate up to, and compensate for, a 100 ppm frequency variation. in the gige mode, rate matching occurs automatically in the rate matcher. if the gmii protocol is follow ed, the /i/ sets (/i1/, /i2/) are sent during the inter-frame gap (ifg). (the gmii protocol specifies 96-bits long). the /i2/ ordered set (/k28.5/, /d16.2/) is added or deleted based on how full or empty the rate matche r fifo buffer is and if the current running disparity is negative. the /i2/ order set contains two 10-bit code groups. two 10-bit groups (20-bits total) are deleted or added at a time. if the number of words in the fifo buffer (fifo count) is greater than nine, the fifo buffer stops writing when the /i2/ ordered set is detected ( figure 2?134 ). if the fifo count is less th an five, the fifo buffer stops reading and inserts the /i2/ ordered se ts in place of the next fifo data ( figure 2?135 ). 1 the gige rate matcher does not ha ve the capability of inserting or deleting /c1/or /c2/ ordered sets. if the rate matching fifo buffer is in an underflow or overflow condition (empty or full), the rece iver outputs a /k28.4/ ( 8'h9c + ctrl ). this might happen if the ppm (parts per mi llion) difference in the read and write clock is too great, the ifg or ip g is too small (there are not enough /i2/ code groups to remove), and/or the frame or packet size is too big. k28.5 d14.3 k28.5 d24.0 k28.5 d15.8 k28.5 d21.5 tx_datain [ ] clock dx.y dx.y k28.5 d5.6 k28.5 d16.2 k28.5 d16.2 k28.5 tx_dataout ordered set d21.5 /i1/ /i2/ /i2/ /c2/
altera corporation 2?185 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?134. /i2/ deleted when fifo count is greater than nine figure 2?135. /i2/ added when fi fo count is less than five reset condition after power up or reset, the gige transmitter outputs three /k28.5/ commas before user data can be se nt. this affects the synchronization ordered set transmission. after reset ( tx_digitalreset ), the 8b/10b encoder automatically sends three /k28.5/ commas (refer to ?8b/10b decoder? on page 2?103 for additional information). dependin g on when you start outputting the synchronization sequence, there could be an even or odd number of /dx.y/ sent as the transmitter befo re the synchronization sequence. the last of the three automatically sent /k28.5/and the first user-sent /dx.y/ are treated as one idle ordered set. this can be a problem if there are an even number of /dx.y/ transmitted before the start of the synchronization sequence. figure 2?136 shows an example of even numbers of /dx.y/ between the last automatically sent /k28.5/ and the first user-sent /k28.5/. the first user-sent ordered set is ignored, so three additional ordered sets are required for proper synchronization. figure 2?136 shows one don?t care data between the tx_digitalreset signal going low and the first of three automatic k28.5, but there could be more. /d/ /d/ /d/ /d/ /d/ /s/ /|2/ /|2/ /|1/ to rate matche r /d/ /d/ /d/ /d/ /d/ /d/ /s/ /|2/ /|1/ one /|2/ code removed from rate matcher /d/ /d/ /d/ /d/ /d/ /s/ /|2/ /|2/ /|1/ to rate matcher /d/ /d/ /d/ /d/ /d/ /d/ /s/ /|2/ /|2/ /|2/ /|1/ one /|2/ code added from rate matcher
2?186 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?136. gige synchronization ordered set considerations after reset sonet/sdh mode sonet/sdh is one of the most co mmon serial-interco nnect protocols used in backplanes deployed in communications and telecom applications. sonet/sdh defines various optical carrier (oc) subprotocols for carrying signals of different capacities through a synchronous optical hierarchy. stratix ii gx transceivers can be employed as physical layer devices in a sonet/sdh system. these transceivers provide support for sonet/sdh protocol-specific functions and electrical features; for example, alignment to a1a2 or a1a1a2a2 pattern. stratix ii gx transceivers are design ed to support the following three sonet/sdh subprotocols: oc-12 at 622 mbps with 8-bit channel width oc-48 at 2488.32 mbps with 16-bit channel width oc-96 at 4976 mbps with 32-bit channel width sonet/sdh fram e structure base oc-1 frames are byte-interleav ed to form sonet/sdh frames. for example, twelve oc-1 frames are byte-interleaved to form one oc-12 frame; forty-eight oc-1 frames are byte-interleaved to form one oc-48 frame and so on. sonet/sdh frame sizes are constant, with a frame transfer rate of 125 s. clock tx_dataout tx_digitalreset k28.5 k28.5 k28.5 k28.5 xxx dx.y dx.y k28.5 k28.5 k28.5 dx.y dx.y dx.y
altera corporation 2?187 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?137 shows the sonet/sdh frame structure. figure 2?137. sonet/sdh frame structure note to figure 2?137 (1) n=12 for oc-12, 48 for oc-48, and 96 for oc-96. transport overhead bytes a1 and a2 are used for recovering the frame boundary from the serial data stream. frame sizes are fixed, so the a1 and a2 bytes appear within the serial data stream every 125 s. in an oc-12 backplane system, twelve a1 bytes ar e followed by twelve a2 bytes. similarly, in an oc-48 backplane system, forty-eight a1 bytes are followed by forty-eight a2 bytes. in sonet/sdh systems, byte values of a1 and a2 are fixed as follows: a1 = ?11110110? or 8'hf6 a2 = ?00101000? or 8'h28 oc-12 and oc-48 data paths oc-12 and oc-48 configurations have similar data paths, as seen in figures 2?138 and 2?139 . the only difference is that oc-48 has a 16-bit pld interface as compared to the 8-bit pld interface in an oc-12 configuration. the oc-48 configuratio n employs the byte serializer and deserializer and a byte ordering bloc k to translate 16-bit pld interfaces into an 8-bit transceiver data path. nxa1 nxa2 nxj0/z0 9 rows nx3 bytes transport overhead nx3 bytes payload
2?188 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?138. oc-12 data path figure 2?139. oc-48 data path oc-96 data path the oc-96 data path is wider than the oc-12 and oc-48 data paths (refer to figure 2?140 ). it has a 32-bit wide pld interface that is translated to a 16-bit wide transceiver data path by the byte serializer and deserializer. as a result, the oc-96 configuration ha s a bit serialization factor of 16, unlike oc-12 and oc-48 with bit seri alization factors of 8. also, the oc-96 configuration does not have the byte ordering block in the transceiver data path. if required, you should implemen t byte ordering logic in the pld logic array in oc-96 configurations. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer 8 8 88 8 transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer 16 16 16 16 16 16 8 8 88 8
altera corporation 2?189 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?140. oc-96 data path sonet/sdh serial data transmission bit order unlike ethernet where the least sign ificant bit of the data byte is transferred first, sonet/sdh requires the most significant bit to be transferred first and the least signif icant bit to be transferred last. to facilitate msbit to lsbit transfer, yo u must enable the following options in the megawizard: flip transmitter input data bits (when used in transmit only or duplex mode) flip receiver output data bits (whe n used in receive only or duplex mode) depending on whether data bytes are transferred msbit to lsbit or lsbit to msbit, you must select approp riate word aligner settings in the megawizard. table 2?43 lists correct word aligner settings for each bit transmission order. oc-12 and oc-48 word alignment sonet/sdh mode uses manual word alignment as described in ?manual sonet/sdh alignment mode (two consecutive 8-bit characters (a1a2) or four consecut ive 8-bit characte rs (a1a1a2a2))? on page 2?78 . in oc-12 and oc-48 configurations, you can configure the word aligner to either align to a 16-bit a1a2 pa ttern or a 32-bit a1a1a2a2 pattern. this is controlled by the rx_a1a2size input port to the transceiver. a transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer 32 32 32 32 32 16 16 16 16 16
2?190 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes low level on the rx_a1a2size port configures the word aligner to align to a 16-bit a1a2 pattern and a high level configures it to align to a 32-bit a1a1a2a2 pattern. you can configure the word aligner to flip the alignment pattern bits programmed in the megawizard and compare it them with the incoming data for alignment. this feature offers flexibilit y to the sonet/sdh system for either an msbit to lsbi t or lsbit to msbit data transfer. table 2?43 lists word alignment patterns that you must program in the megawizard based on the bit-transmission order and the word aligner bit-flip option. the behavior of the sonet/sdh word aligner control and status signals along with an operational timing diagram are explained in ?manual sonet/sdh alignment mode (two consecutive 8-bit characters (a1a2) or four consecutive 8-bi t characters (a1a1a2a2))? on page 2?78 . oc-96 word alignment in oc-96 configuration, the word alig ner is only allowed to align to a a1a1a2a2 pattern, so input port rx_a1a2size is unavailable. barring this difference, the oc-96 word alignm ent operation is similar to that of the oc-12 and oc-48 configurations. oc-48 byte serializer and deserializer the oc-48 transceiver data path in cludes the byte serializer and deserializer to allow the pld interfac e to run at a lower speed. the oc-12 configuration does not use the byte serializer and deserializer blocks. the byte serializer and deserializer blocks are explained in the sections ?byte serializer? on page 2?32 and ?byte deserializer? on page 2?112 , respectively. the oc-48 byte serializ er converts 16-bit data words from table 2?43. word aligner settings serial bit transmission order word alignment bit flip word alignment pattern msbit to lsbit on 1111011000101000 (16'hf628) msbit to lsbit off 0001010001101111 (16'h146f) lsbit to msbit off 0010100011110110 (16'h28f6)
altera corporation 2?191 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the pld logic array and translate the 16-bit data words into two 8-bit data bytes at twice the rate. the oc-48 byte deserializer takes in two consecutive 8-bit data bytes and transl ates them into a 16-bit data word to the pld logic array at half the rate. oc-96 byte serializer and deserializer the oc-96 byte serializer converts 32-bit data words from the pld logic array and translates them into two 16-bi t data bytes at twice the rate. the oc-48 byte deserializer takes in two consecutive 16-bit data bytes and translates them into a 32-bit data wo rd to the pld logic array at half the rate. oc-48 byte ordering because of byte deserialization, the most significant byte of a word may appear at the rx_dataout port along with the le ast significant byte of the next word. in an oc-48 configuration, the byte ordering block is built into the data path and can be leveraged to perform byte ordering. in an oc-96 configuration, the byte ordering bloc k is unavailable and ordering must be performed in the pld logic array. the byte ordering in an oc-48 config uration is automatic as explained in ?word alignment based on byte ordering? on page 2?114 . in automatic mode, the byte ordering block is tr iggered by the rising edge of the rx_syncstatus signal. as soon as the by te ordering block sees the rising edge of the rx_syncstatus signal, it compares the least significant byte coming out of the byte deserializer with the a2 byte of the a1a2 alignment pattern. if the least significant byte coming out of the byte deserializer does not match a2 byte set in the megawizard, the byte ordering block inserts a pad character as seen in figure 2?141 . insertion of this pad character enables the byte ordering block to restore the correct byte order. note that the pad characte r is defaulted to the a1 byte of the a1a2 alignment pattern. once the byte orderi ng is achieved, the rx_byteorderalignstatus signal remains asserted high until rx_digitalreset is asserted. the byte ordering within the transceiver is a one-time event after the receiver comes out of rx_digitalreset . so, if a byte ordering operation is required, the receiver must go through an rx_digitalreset cycle.
2?192 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes if successful byte ordering occurs without successful word alignment, you should assert receive digital reset ( rx_digitalreset ) so that the byte ordering block performs another round of byte ordering (one time after asserting rx_digitalreset ). this is only required when the byte ordering block picks an incorrect byte order. figure 2?141. byte ordering block operation in oc-48 (oif) cei-phy interface mode the (oif) cei phy interface mode is intended to support two main protocols: common electrical i/o (cei-6g) pr otocol defined by the optical internetworking forum (oif) at data rates between 4.976 gbps and 6.375 gbps interlaken protocol at data rate s between 3.135 gbps and 6.375 gbps stratix ii gx transceivers support a data rate between 3.135 gbps and 6.375 gbps in (oif) ce i phy interface mode. rx_dataout (msb) rx_dataout (lsb) _ from byte deserializer rx_syncstatus rx_syncstatus rx_byteorderalignstatus to pld core rx_clkout a1 a1 a2 a2 d0 d2 a1 a1 pad a2 d1 d3 x a1 a1 a2 a2 d1 x a1 a1 a2 d0 d2 byte ordering block
altera corporation 2?193 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?142 shows the alt2gxb transceiver data path when configured in this mode. figure 2?142. (oif) cei-phy interface data path table 2?44 shows alt2gxb configurations supported by the stratix ii gx transceivers in (oif) cei phy interface mode. (oif) cei phy interface mode clocking for improved transmitter jitter performance, the alt2gxb megawizard plug-in manager provides an use central clock divider to improve transmitter jitter option. if you select this op tion, clocks generated by the central clock divider clock all four transceiver channels within the same transceiver block. otherwise, clocks generated by the local clock divider in each channel clock the respective channel. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer table 2?44. alt2gxb configurations in (oif) cei phy interface mode data rate (mbps) refclk frequency (pll multiplication factor) channel width 3135 < data rate 5700 data-rate/10 (m = 10) (1) data-rate/20 (m = 10) data-rate/40 (m = 20) 32 bit 5800 < data rate 6375 data-rate/10 (m = 10) (1) data-rate/20 (m = 10) 32 bit note to table 2?44 : (1) selecting the refclk frequency of data - rate/10 requires the use of the /2 refclk pre-divider; for example, selecting 500 mhz refclk frequency for 5000 mbps data rate.
2?194 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes 1 unlike pipe 4, xaui or basic x4 mode, the transmitter pcs is not bonded in the (oif) cei ph y interface with the low-jitter option selected. figure 2?143 shows transceiver clocking in (oif) cei phy interface mode with and without the improved transmitter jitter option enabled. figure 2?143. (oif) cei phy interface mode clocking transceiver placement limitations with improved jitter clocking option if one or more channels in a transceiver block are configured to (oif) cei phy interface mode with the improved jitter clocking option enabled, the remaining channels in that transceiver block must either be configured in (oif) cei phy interface mode with this option enabled or must be unused. all used channels within a transceiver block configured in (oif) cei phy interface mode with improv ed jitter clocking option enabled must also run at the same data rate. figures 2?144 and 2?145 show two examples each of legal and illegal transceiver placements wi th respect to the improved jitter clocking option in (oif) cei phy interface mode. tx pll transceiver block clocking with the "use central clock divider to improve transmitter jitter" option enabled central clock divider block channel 0 channel 1 channel 2 channel 3 transceiver block clocking with the "use central clock divider to improve transmitter jitter" option disabled tx pll ch 0 local clock divider block ch 1 local clock divider block ch 2 local clock divider block ch 3 local clock divider block channel 0 channel 1 channel 2 channel 3
altera corporation 2?195 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?144. examples of legal transceiv er placement in (oif) cei phy interface mode figure 2?145. examples of ill egal transceiver placement in (oif) cei phy interface mode serial digital interface (sdi) mode the society of motion picture and television engineers (smpte) defines various serial digital interface (s di) standards for transmission of uncompressed video. the following three smpte standards are popular in video broadcasting applications: smpte 259m standard?more popularly known as the standard-definition (sd) sdi, is defined to carry video data at 270 mbps. ch 0 ch 1 ch 2 ch 3 (oif) cei phy interface mode with the low-jitter option enabled (data rate = 5 gbps) (oif) cei phy interface mode with the low-jitter option enabled (data rate = 5 gbps) (oif) cei phy interface mode with the low-jitter option disabled (oif) cei phy interface mode with the low-jitter option disabled unused channel unused channel serial rapidio serial rapidio ch 0 ch 1 ch 2 ch 3 ch 0 ch 1 ch 2 ch 3 (oif) cei phy interface mode with the low-jitter option enabled (oif) cei phy interface mode with the low-jitter option enabled serial rapidio serial rapidio ch 0 ch 1 ch 2 ch 3 (oif) cei phy interface mode with the low-jitter option enabled ( data rate = 5 gbps ) (oif) cei phy interface mode with the low-jitter option enabled ( data rate = 5 gbps ) (oif) cei phy interface mode with the low-jitter option enabled ( data rate = 6 gbps ) (oif) cei phy interface mode with the low-jitter option enabled ( data rate = 6 gbps )
2?196 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes smpte 292m standard?more popularly known as the high-definition (hd) sdi, is defined to carry video data at either 1485 mbps or 1483.5 mbps. smpte 424m standard?more popularly known as the third-generation (3g) sdi, is defined to carry video data at either 2970 mbps or 2967 mbps. you can configure stratix ii gx tr ansceivers in hd-sdi or 3g-sdi configuration using the alt2gx b megawizard pl ug-in manager. figure 2?146 shows the alt2gxb transceiver data path in sdi mode. figure 2?146. sdi mode data path table 2?45 shows alt2gxb configurations supported by the stratix ii gx transceivers in sdi mode. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer table 2?45. alt2gxb configurations in sdi mode configuration data rate (mbps) refclk frequencies (mhz) channel width hd 1485 74.25, 148.5 10 bit, 20 bit 1483.5 74.175, 148.35 10 bit, 20 bit 3g 2970 148.5, 297 only 20-bit interface allowed in 3g 2967 148.35, 296.7 only 20-bit interface allowed in 3g
altera corporation 2?197 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview transmitter data path in the 10-bit channel width sdi configur ation, the transmitter data path is made up of the transmitter phase compensation fifo and the 10:1 serializer. in the 20-bit channel widt h sdi configuration, the transmitter data path also includes the byte serializer. 1 in sdi mode, the transmitter is purely a parallel-to-serial converter. sdi transmitter functi ons, such as scrambling and cyclic redundancy check (crc) code generation, must be implemented in the fpga logic array. receiver data path in the 10-bit channel width sdi config uration, the receiver data path comprises of the clock recovery unit (c ru), the 1:10 deserializer, the word aligner in bit-slip mode, and the receiver phase compensation fifo. in the 20-bit channel width sdi configurat ion, the receiver data path also includes the byte deserializer. 1 sdi receiver functions, such as de-scrambling, framing, and crc checker, must be implemented in the fpga logic array. receiver word alignment/framing in sdi systems, since the word a lignment and framing happens after de-scrambling, the word aligner in th e receiver data path is not useful. altera recommends driving the alt2gxb rx_bitslip signal low to avoid the word aligner from inserting bits in the received data stream. 1 altera offers sdi megacore function that can be configured at sd-sdi, hd-sdi, and 3g-sdi data rates. the sdi megacore function implements system-level functions like scrambling and de-scrambling and crc generation and checking. it also offers the capability of configuring th e three sdi data rates (sd, hd, and 3g) dynamically on the same transceiver channel. for more details, refer the sdi megacore function user guide . serial rapidio mode the rapidio? trade associatio n defines a high-performance, packet-switched interconnect stan dard to pass data and control information between microprocessors, digital signal, communications, and network processors, system memories, and peripheral devices.
2?198 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes serial rapidio physical layer specification defines three line rates: 1.25 gbps 2.5 gbps 3.125 gbps it also defines two link widths?single-lane (1) and bonded four-lane (4) at each line rate. stratix ii gx transceivers support on ly single-lane (1) configuration at all three line rates. four 1 channels configured in serial rapidio mode can be instantiated to achieve a 4 serial rapidio link. the four transmitter channels in this 4 se rial rapidio link are not bonded. the four receiver channels in this 4 serial rapidio link do not have lane alignment or deskew capability. figure 2?147 shows the alt2gxb transceiver data path when configured in serial rapidio mode. figure 2?147. serial rapidio mode stratix ii gx transceivers, when conf igured in serial rapidio functional mode, provide the following pcs and pma functions: 8b/10b encoding/decoding word alignment lane synchronization state machine clock recovery from the encoded data serialization/deserialization transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer
altera corporation 2?199 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 1 stratix ii gx transceivers do no t have built-in support for other pcs functions; for example, clock frequency compensation between upstream transmitter clock and local receiver clock (rate matcher), pseudo-random id le sequence generation, and lane alignment in 4 mode. depending on your system requirements, you must implemen t these functions in the logic array or external circuits. synchronization state machine in serial rapidio mode, the alt2gxb megawizard plug-in manager defaults the word alignment pattern to k28.5. the word aligner has a synchronization state machine th at handles the receiver lane synchronization. the alt2gxb megawizard plug-in mana ger automatically defaults the synchronization state machine to indicate synchronization when the receiver receives 127 k28.5 (10'b0101111100 or 10'b1010000011) synchronization code groups without receiving an intermediate invalid code group. once synchronized, the state machine indicates loss of synchronization when it detects three invalid code groups separated by less than 255 valid code groups or when it is reset. receiver synchronization is indicated on the rx_syncstatus port of each channel. a high on the rx_syncstatus port indicates that the lane is synchronized and a low indicates that it has fallen out of synchronization. table 2?46 lists the alt2gxb synchronization state machine parameters when configured in serial rapidio mode. table 2?46. synchronization state machi ne parameters in serial rapidio mode parameters number number of valid k28.5 code groups received to achieve synchronization. 127 number of errors received to lose synchronization. 3 number of continuous good code gr oups received to reduce the error count by one. 255
2?200 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes figure 2?148 gives a conceptual view of the synchronization state machine implemented in serial rapidio functional mode. figure 2?148. synchronization state ma chine in serial rapidio mode cpri mode the common public radio interface (cpri) specification defines a radio base station interface standard between the radio equipment control (rec) and the radio equipment (re). loss of sync data = comma comma detect if data == comma kcntr++ else kcntr=kcntr synchronized data = valid; kcntr < 3 kcntr = 127 synchronized error detect if data == !valid ecntr++ gcntr=0 else if gcntr==255 ecntr-- gcntr=0 else gcntr++ data = !valid data=valid ecntr = 0 ecntr = 3 data = !valid
altera corporation 2?201 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview cpri specification v2.1 defines the following three line rates for deployment flexibility: cpri line bit rate option 1: 614.4 mbps cpri line bit rate option 2: 1228.8 mbps (2 x 614.4 mbps) cpri line bit rate option 3: 2457.6 mbps (4 x 614.4 mbps) stratix ii gx transceivers suppor t all three line bit rate options. figure 2?149 shows the alt2gxb transceiver data path when configured in cpri mode. figure 2?149. alt2gxb transceiver data path in cpri mode table 2?47 shows alt2gxb configurations supported by the stratix ii gx transceivers in cpri mode. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering rate match fifo de- serializer table 2?47. alt2gxb configurations in cpri mode data rate (mbps) refclk frequencies (mhz) channel width 614 61.4, 76.675, 122.8, 153.5 8 bit 1228 61.4, 76.675, 122.8, 153.5, 245.6, 307 8 bit 2456 61.4, 76.675, 122.8, 153.5, 245.6, 307, 491.2, 614 8 bit
2?202 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes transmitter data path the cpri transmitter data path includes the tr ansmitter phase compensation fifo, the 8b/10b encode r, and the 10:1 serializer. layer 1 functions like hyperframe framing th at includes interleaving iq data, sync data, l1 inband protocol data, and so forth, that must be performed in the fpga logic array or external circuitry. receiver data path the receiver data path includes the clock recovery unit (cru), 1:10 deserializer, synchronization-st ate-machine-based word aligner, 8b/10b decoder, and receiver phase compensation fifo. the synchronization-state-machine-based word aligner is programmable. you can select the number of bad code groups detected to fall out of synchronization, the nu mber of valid synchronization code groups to acquire synchronization, an d the number of good code groups received to reduce the error count by 1. you can use this programmability to im plement the loss of signal (los), loss of frame synchroni zation (lof), and the re mote alarm indication (rai) features in the fpga logic a rray. the synchronization status is reported on the rx_syncstatus port from the alt2gxb. the rx_syncstatus signal is driven high when the programmed conditions for synchronization state machine are met. otherwise, it is driven low to indicate loss of synchronization. link delay accuracy requirement r-19 in cpri specification v2.1 requires the cpri link delay accuracy (excluding the transmission medium delay) to be tc/32, where tc is the length of a basic frame (260.42 ns). this requirement mandates the total uncertainty in cp ri link latency to be less than ~16.3 ns. to meet the strict cpri link delay accuracy requirements, the quartus ii software automatically adjusts the ro uting delays on the transmitter and receiver phase compensation fifo cl ocks. as a result of this delay adjustment, the transmitter and re ceiver phase compensation fifo latency becomes constant. 1 the quartus ii software performs the delay adjustment to minimize the uncertainty in link latency only in cpri mode.
altera corporation 2?203 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview table 2?48 shows the uncertainty in the cpri transceiver data path after delay adjustment. table 2?48 shows that the cpri link delay accuracy requirements are met within the transceiver data path. transceiver limitations in cpri mode to meet the cpri link delay accu racy requirements, the quartus ii software adjusts delays on the clock routes from the tx_clkout and rx_clkout ports to the write and read ports of the transmitter and receiver phase compensation fifos, respectively, for each transceiver channel. due to this requirement, the quartus ii software only allows the tx_clkout signal from each channel to clock the write port of its transmitter phase compensation fi fo. similarly, it allows the rx_clkout signal from each channel to clock the read port of its receiver phase compensation fifo. if your design requires dynamic reconfiguration between cpri mode and other modes, each channel?s phase compensation fifos must be clocked by its own tx_clkout and rx_clkout for other modes as well. the default transceiver configuration used to create the programming file ( .sof or .pof ) must be cpri for the delay algorithm to take effect. in cpri mode, you cannot group the tx_coreclk and/or rx_coreclk ports of multiple channels and drive them using a common clock driver using the shared clock or 0 ppm cl ock group assignments. each cpri channel will utilize at least two glob al and/or regional clock resources. since a maximum of 32 global and /or regional clock resources are available for transceivers in the stra tix ii gx device, the clock resource availability governs the maximum numb er of cpri channels that you can instantiate per device. table 2?48. uncertainty in cpri transceiver da tapath latency with delay adjustment note (1) data rate (mbps) receiver deserializer uncertainty (parallel clock cycles) receiver phase comp fifo uncertainty (parallel clock cycles) transmitter phase comp fifo uncertainty (parallel clock cycles) parallel clock period (ns) total uncertainty (ns) 614 0.9 0 0 16.3 14.67 1228 0.9 0 0 8.15 7.34 note to table 2?48 : (1) the delay adjustment is not made fo r cpri 2456 mbps line rate configuratio n since it meets the 16.3 ns link delay requirement without these adjustments.
2?204 altera corporation stratix ii gx device handbook, volume 2 october 2007 native modes 1 the maximum number of cpri channels per device also depends on the number of transceiver channels available in that device and the lrio clock resource limitations. cpri mode is supported only in c3 , c4, and i4 speed-grade devices. pld-transceiver interface clock duty cycle due to delay adjustments made to the tx_clkout and rx_clkout routes in the fpga clock network, the worst case duty cycle on these pld-transceiver interface clocks can be 60-40%. if these clocks are used to clock fpga logic array, you must set proper timing analyzer assignments to account for the 60-40% du ty cycle on these clocks. figure 2?150 shows how to set 60-40% duty cycle constraints in timequest timing analyzer for a cpri 614.4 mbps line rate configuration. in the timequest analyzer window, selecting the report clocks option lists all the tx_clkout and rx_clkout clocks in your design. select all clocks and adjust the falling edge timing appropriately for 60-40% duty cycle. figure 2?150. setting duty cycle in timequest timing analyzer figure 2?151 shows how to set 60-40% duty cycle constraints in classic timing analyzer. to set this option, go to the assignments menu and select settings , then select timing analysis settings and classic timing analyzer settings , and then click on the individual clocks tab. in the individual clocks window, select new . in the new clock settings window, browse to all rx_clkout and tx_clkout nodes and assign 60% in the duty cycle option for each of these phase compensation fifo clocks.
altera corporation 2?205 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?151. setting duty cycle in classic ti ming analyzer 1 if the pld-transceiver interface cl ocks are fed to an off-chip pll (for example, vcxo-based pll fo r de-jittering purposes), you must make sure that the pll ca n tolerate the 60-40% duty cycle on its input reference clock. loopback modes there are several loopback modes available on the stratix ii gx transceiver block that allow you to isolat e portions of the circuit. all paths are designed to run up to full speed. the available loopback paths are: serial loopback available in all fu nctional modes except pci express (pipe) reverse serial loopback availa ble in basic mode with 8b/10b pci express pipe reverse parallel loopback available in pci express protocol reverse serial pre-cdr loopback available in basic mode with 8b/10breverse serial loopback avai lable in basic mode with 8b/10b parallel loopback available in basic mode for bist testing only serial loopback figure 2?152 shows the data path for serial loopback. a data stream is fed to the transmitter from the fpga logic array and has the option of utilizing all the blocks in the transmitter. the data, in serial form, then traverses from the transmitter to the re ceiver. the serial data is the data that is transmitted from the stratix i i gx device. once the data enters the receiver in serial form, it can utilize any of the receiver blocks and is then fed into the fpga logic array.
2?206 altera corporation stratix ii gx device handbook, volume 2 october 2007 loopback modes use the rx_seriallpbken port to dynamically enable serial loopback on a channel by channel basis. when rx_seriallpbken is high, all blocks that are active wh en the signal is low are still active. when the serial loopback is enabled, the tx_dataout port is still active and drives out the output pins. serial loopback is often used to check the entire path of the transceiver. the data is retimed through different clock domains and an alignment pattern is still necessary for the word aligner. figure 2?152. stratix ii gx block in serial loopback mode pci express pipe reverse parallel loopback figure 2?153 shows the data path for the pci express pipe reverse parallel loopback. this data path is not flexible because it must be compliant with the pci express pipe specification. the data comes in from the rx_datain ports. the receiver uses the cru, deserializer, word aligner, and rate matching fifo bu ffer, loops back to the transmitter serializer, and then goes out the transmitter tx_dataout ports. the data also goes to the pld fabric on the receiver side to the tx_dataout port. the deskew fifo buffer is not enab led in this loopback mode. this loopback mode is optionally co ntrolled dynamically through the tx_detectrxloopback port. 1 this is the only loopback allowed in the pipe mode. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer serial loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20
altera corporation 2?207 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?153. stratix ii gx block in pci express pipe reverse parallel loopback mode reverse serial loopback reverse serial loopback is a subpr otocol in basic mode. it requires 8b/10b, and the word aligner pattern of k28.5. no dynamic pin control is available to select or deselect reverse serial loopback. the active block of the transmitter is only the buffer. the data sent to the receiver is retimed with the recovered clock and sent out to the transmitter. the data path for reverse serial loopback is shown in figure 2?154 . data comes in from the rx_datain ports in the receiver. the data is then fed through the cdr block in serial form directly to the tx_dataout ports in the transmitter block. you can enable reverse serial loop back for all cha nnels through the megawizard. any pre-emphasis setting on the transmitter buffer is ignored in reverse serial loopback. the data flows through the active blocks of the receiver and into the logic array. reverse serial loopback is often impl emented when using a bit error rate tester (bert). transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 pci express pipe reverse parallel loopback
2?208 altera corporation stratix ii gx device handbook, volume 2 october 2007 loopback modes figure 2?154. stratix ii gx block in reverse serial loopback mode reverse serial pre-cdr loopback the reverse serial pre-cdr loopback uses the analog portion of the transceiver. an external source (p attern generator or transceiver) generates the source data. the high-speed serial source data arrives at the high-speed differential receiver inpu t buffer, loops back before the cru unit, and is transmitted though the high-speed differential transmitter output buffer. it is for test or veri fication use only to verify the signal being received after the gain and eq ualization improvements of the input buffer. the signal at the output is n ot exactly what is received since the signal goes through the output bu ffer and the vod is changed to the vod setting level. the pre-emphas is settings have no effect. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer reverse serial loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20
altera corporation 2?209 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?155 show the stratix ii gx bloc k in reverse serial pre-cdr loopback mode. figure 2?155. stratix ii gx block in reverse serial pre-cdr loopback mode parallel loopback the data path for parallel loopback is shown in figure 2?156 . the forward parallel loopback allows a test flow check of the pcs using either the built-in test incremental pattern. this is available only as a subprotocol in basic double-width mode. when using the bist incremental para llel loopback, the deskew and the rate matching fifo buffer are not available. the 8b/10b encoder and decoder are used. no dynamic control pin is available to enable or disable the loopback. test result pins, rx_bistdone and rx_bisterr , are available in this loopback mode. when using parallel loopback, the tx_dataout ports are active and the differential output voltage on the tx_dataout ports is based on the v od settings. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer reverse serial loopback pre-cdr bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20
2?210 altera corporation stratix ii gx device handbook, volume 2 october 2007 loopback modes table 2?49 shows the available bist patterns in double-width mode. figure 2?156. stratix ii gx block in parallel loopback mode incremental pattern generator the incremental data generator sweeps through all the valid 8b/10b data and control characters. this mode is on ly available in basic mode with the bist/parallel loopback subprotocol in the quartus ii software. you can also enable the incremental bist veri fier to perform a quick verification of the 8b/10b encoder/decoder paths. in incremental mode, the bist generato r sends out the data pattern in the following sequence: k28.5 (comma), k 27.7 (start of frame, sof), data (00-ff incremental), k28.0, k28.1, k2 8.2, k28.3, k28.4, k28.6, k28.7, k23.7, k30.7, k29.7 (end of frame, eof), and then repeats. you must enable the 8b/10b encoder for proper operation. no dynamic control pin is available to enable or disable the loopback. test result pins are table 2?49. available bist patterns in double-width mode pattern word aligner alignment pattern byte order align pattern description double-width mode 16 bit 20 bit incremental with 8b/10b 20'h16e83 n/a all 8b/10b valid code groups v transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer parallel loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20
altera corporation 2?211 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview rx_bistdone and rx_bisterr . the rx_bistdone signal goes high at the end of the sequence. if the verifier detects an error before it is finished, rx_bisterr pulses high as long as the data is in error. built-in self-test modes besides the regular data flow blocks, each transceiver ch annel contains an embedded built-in self test (bist) generator and corresponding verifier block that you can use for quick devi ce and setup verifi cation (refer to figure 2?157 ). the generators reside in the transmitter block and the verifier in the receiver block. the generators can generate prbs and incremental patterns. the incremental pattern is available only in parallel loopback mode. the verifiers are only available for these data patterns. the bist blocks operate differently when in the single-width mode and the double-width mode. the bist modes are only available as subprotocols under basic mode. figure 2?157. built-in self test mode notes to figure 2?157 : (1) rx_seriallpbken[] is required in prbs. (2) rx_bisterr[] and rx_bistdone[] are only available in prbs and bist modes. buit-in self test (bist) pll_inclk[] rx_digitalreset[] rx_seriallpbken[] (1) tx_digitalreset[] rx_datain[] tx_dataout rx_bisterr (2) rx_bistdone (2)
2?212 altera corporation stratix ii gx device handbook, volume 2 october 2007 built-in self-test modes figure 2?158 shows the prbs blocks wi th loopback used in the transceiver channel. figure 2?158. prbs blocks with loopback in transceiver channel bist in single-width mode single-width mode supports prbs10 pa ttern generation and verification. prbs10 in basic mode is supported with or without serial loopback 1 the prbs10 pattern is only available when the serdes factor is 10 bits. table 2?50 shows the bist patterns for single-width mode. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte reorder bist incremental verify rate match fifo de- serializer bist prbs generator 20 serial loopback table 2?50. available bist patt erns in single-width mode pattern word aligner alignment pattern byte order align pattern description single-width mode 8 bit 10 bit prbs10 10'h3ff n/a x 10 + x 7 + 1 v
altera corporation 2?213 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview prbs10 pseudo-random bit sequences (prbs) are commonly used in systems to verify the integrity and robustness of the data transmission paths. when the serdes factor is 10, use the pr bs10 pattern. the prbs generator yields 2^10-1 unique patterns. you ca n use prbs with or without serial loopback. in prbs/ serial loopback mode, the rx_seriallpbken signal is available. in the prbs/no loopback mode, this control signal is not available. you enable prbs mode in the quartus ii alt2gxb megawizard plug-in manager. prbs10 does not use the 8b/10b encoder and decoder. the 8b/10b encoder and decoder are bypa ssed automatically in the prbs mode. the advantage of using a prbs data st ream is that the randomness yields an environment that stresses the transmission medium. in the data stream, you can observe both random jitter and deterministic jitter using a time interval analyzer, bit error rate tester, or oscilloscope. the prbs verifier can provide a quick check through the non-8b/10b path of the transceiver block. the prbs verifier is active once the receiver channel is synchronized. set the alignment pattern to 10?h3ff for the 10-bit serdes modes. the verifier stops checking the patterns after receiving all the prbs patterns (1023 patterns for 10-bit mode). the rx_bistdone signal goes high, indicating that the verifier has completed. if the verifier detects an error before it is finished, rx_bisterr pulses high for the time the data is incorrect. use the rx_digitalreset signal to re-start the prbs verification. the 8b/10b encoder is enabled, so the data stream is dc balanced. 8b/10b encoding guarantees a run leng th of less than 5 ui, which yields a less stressful pattern versus the prbs data. however, since the prbs generator bypasses the 8b/10b paths, the incremental bist can test this path. bist in double-width mode double-width mode supports only prbs7 pattern generation and verification. 1 the prbs7 pattern is only availa ble when the serdes factor is 20 bits.
2?214 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down table 2?51 shows the bist patterns for double-width mode. prbs7 pseudo-random bit sequences (prbs) are commonly used in systems to verify the integrity and robustness of the data transmission paths. the prbs7 generator generates 2^7-1 unique patterns. prbs can be used with or without serial loopback. in prbs/ serial loopback mode, the rx_seriallpbken signal is availa ble. in the prbs/no loopback mode, this control signal is not available. you enable prbs mode in the megawizard. prbs7 does not use the 8b/10b encoder and decoder. the 8b/10b encoder and decoder are bypassed automatically in the prbs mode. the advantage of using a prbs data st ream is that the randomness yields an environment that stresses the tran smission medium. in the data stream you can observe both random jitter and deterministic jitter using a time interval analyzer, bit error ra te tester, or oscilloscope. the prbs verifier provides a quick check through the non-8b/10b path of the transceiver block. the prbs ve rifier is active once the receiver channel is synchronized. set the al ignment pattern to 20'h43040 for the 20- bit serdes modes. the prbs verifier prevents the word aligner from aligning to a new pattern after the first five successfully verified words. the verifier stops checking the patterns after receiving all the prbs patterns (127 patterns for prbs7). the rx_bistdone signal goes high, indicating that the verifi er has completed. if the verifier detects an error before it is finished, rx_bisterr pulses high for as long as the data is in error. use the rx_digitalreset signal to re-start the prbs verification. reset control and power down stratix ii gx transceivers offer multipl e reset signals to control separate ports of the transceiver channels and blocks ( figure 2?159 ). you can set each unused channel to a powe r-down mode to reduce power consumption. table 2?51. available bist patterns in double-width mode pattern word aligner alignment pattern byte order align pattern description double-width mode 16 bit 20 bit prbs7 20'h43040 n/a x 7 + x 6 + 1 v
altera corporation 2?215 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?159. reset control and power down user reset and enable signals each transceiver block and each cha nnel in the transceiver block of the stratix ii gx device has individual reset signals to reset the digital and analog portions of the channel. the analog resets are power-down signals, which require a longer pu lse width for the circuits to power down. the tx_digitalreset , rx_digitalreset , and rx_analogreset signals affect the channels individually. the gxb_powerdown signal affects the entire transceiver block. 1 all the reset and enable signals are not required. if not used, the signals are defaulted to not reset for all reset sign als and enabled for the pll enable signal. all reset and enable signals are asynchronous. tx_digitalreset . the tx_digitalreset signal resets all digital logic in the transmitter, including the xaui transmit state machine, the bist-prbs generator, and the bist pattern generator. this signal operates independently from the other re set signals. the minimum pulse width is two parallel cycles. rx_digitalreset . the rx_digitalreset signal resets all digital logic in the receiver, including the xaui and gige receiver state machine, the xaui channel al ignment state machine, the bist- prbs verifier, and the bist-increment al verifier. this signal operates independently from the other re set signals. the minimum pulse width is two parallel cycles. rx_analogreset . the rx_analogreset signal resets part of the analog portion of the receiver cdr. this signal operates independently from the other re set signals. the minimum pulse width is two parallel clock cycles. reset control gxb_powerdown rx_analogreset rx_digitalreset tx_digitalreset
2?216 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down gxb_powerdown . the gxb_powerdown signal powers down the entire transceiver block. all digital and analog circuits are also reset. this signal operates independently from the other re set signals. the minimum pulse width for gxb_powerdown signal is 100 ns synchronization is performed afte r any reset condition. you must determine when the data is valid after reset (for example, by using the rx_syncstatus signal). table 2?52 shows the blocks affected by each reset and power-down signal. table 2?52. blocks affected by reset and power-down signals (part 1 of 2) transceiver blocks rx_digitalreset rx_analogreset tx_digitalreset gxb_powerdown transmitter phase compensation fifo buffer and byte serializer vv transmitter 8b/10b encoder vv transmitter serializer v transmitter analog circuits v transmitter plls v transmitter xaui state machine vv transmitter analog circuits v bist generators vv receiver deserializer v receiver word aligner vv receiver deskew fifo buffer vv receiver rate matcher vv receiver 8b/10b encoder vv receiver phase compensation fifo buffer and byte deserializer vv receiver pll and cru vv
altera corporation 2?217 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?160 shows a sample reset cycle. figure 2?160. reset power signal timing waveform notes to figure 2?160 : (1) tx_digitalreset is valid in transmitter on ly and duplex configuration. (2) rx_analogreset and rx_digitalreset are valid in receiver only and duplex configuration. the minimum pulse width for the gxb_powerdown port (between time marker 1 and 2) is 100 ns. the tx_digitalreset and rx_analogreset signals can be deasserted after the driving pll asserts its associated pll_locked signal. the rx_digitalreset signal can be de-asserted 4us after the rx_freqlocklocked signal goes high (time between markers 6 and 7). receiver xaui state machine vv receiver byte ordering block vv bist verifiers vv receiver analog circuits v table 2?52. blocks affected by reset and power-down signals (part 2 of 2) transceiver blocks rx_digitalreset rx_analogreset tx_digitalreset gxb_powerdown gxb_powerdown tx_digitalreset rx_analogreset rx_digitalreset rx_pll_locked rx_freqlocked 1 5 pll_locked 3 4 4 6 7 2 output status signals reset/power down signals t
2?218 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down in a transmitter only configuration, only the pll_locked , gxb_powerdown , and tx_digitalreset signals are used. in a receiver only configuration, only the rx_analogreset , rx_digitalreset , and rx_freqlocked signals are used. reset sequence for pipe mode the reset sequence used for the other modes looks for rx_freqlocked signal to deassert rx_digitalreset . in pipe mode, the rx_freqlocked signal does not go high during the pci-e compliance testing phase because of receiving electrical idle. figure 2?161 shows the reset sequence for pipe mode. figure 2?161. pipe mode reset sequence initialization and pci-e compliance phase after the device is powered up, any pci-e compliant device performs compliance testing. during this phas e, all the transceiver reset signals ( gxb_powerdown , tx_digitalreset , rx_analogreset , and rx_digitalreset ) are asserted. 1 the minimum time period between markers 1 and 2 for the gxb_powerdown signal is 100 ns ( figure 2?161 ). gxb_powerdown tx_digitalreset rx_analogreset rx_digitalreset rx_pll_locked rx_freqlocked 1 5 pll_locked 3 4 4 61011 2 initialization/pci-e compliance phase normal operation phase ignore receive data t1 789 t2 t4 t3
altera corporation 2?219 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview the tx_digitalreset and rx_analogreset signals can be deasserted after the pll_locked signal goes high. the reset controller should deassert the rx_digitalreset when the rx_pll_locked signal goes high. the parallel data sent to the pld logi c array in the receive side may not be valid until 4 us (t2) after rx_freqlocked goes high. normal operation phase during normal operations, the receive data is valid and the rx_freqlocked signal is high. in this situation, when rx_freqlocked is deasserted, (marker 8 in figure 2?161 ), the reset controller should wait for the rx_freqlocked to go high again and assert rx_digitalreset (marker 10 in figure 2?161 ) for two parallel receive clock cycles. the data from the gigabit transceiver block is not valid between the time when rx_freqlocked goes low until rx_digitalreset is deasserted. the pld logic should ignore the data during this time period (the time period between markers 8 and 11 in figure 2?161 ). 1 minimum t1 period is 100 ns. minimum t2 and t3 periods are 4 us. t4 indicates two para llel receive clock cycles. rate matcher fifo buffer over flow and underf low condition during the normal operating phase, the reset controller monitors the overflow and underflow status of the rate matcher fifo buffer. if there is overflow and underflow on the rate matcher fifo buffer, the reset controller asserts rx_digitalreset for two receive parallel clock cycles. you can monitor the rate matc her fifo buffer status through the pipestatus[2:0] signal from the pipe interface. this condition is shown in figure 2?162 . figure 2?162. pipe mode reset during rate matche r fifo buffer overflow and underflow condition notes to figure 2?162 : (1) pipestatus = 101 represents elastic overflow. (2) pipestatus = 110 represents elastic overflow. tx_digitalreset rx_analogreset rx_digitalreset rx_freqlocked pipestatus t4 t4 1 0 1 0 1 0 1 0 000 101 000 110 000
2?220 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down power down the quartus ii software automatically selects the power-down channel feature, which takes affect when yo u configure the stratix ii gx device. all unused transceiver and blocks in a design are powered down to reduce the overall power consumptio n. you cannot use the power-down feature on the fly to turn the transcei ver channels and transceiver blocks on and off without reconfiguration. you can set the transceiver block to power down automatically in the quartus ii software or to power down dynamically in the pld fabric through the gxb_powerdown port. assertion of this port does not power down the refclk reference clock buffer. 1 the gxb_powerdown port is optional. in simulation, if the gxb_powerdown port is not instantiated, you must assert tx_digitalreset , rx_digitalreset and rx_analogreset signals appropriately for correct simulation behavior. if the gxb_powerdown port is instantiated and other reset signals are not used, you must assert the gxb_powerdown signal for at least one parallel clock cycle for correct simulation behavior. in simulation, you can de-assert the rx_digitalreset immediately after rx_freqlocked signal goes high to reduce the simulatio n run time. it is not necessary to wait for 4 us as suggested in the actual reset sequence. 1 in pipe mode simulation, you must assert the tx_forceelecidle signal for at least on e parallel clock cycle before transmitting normal data for correct simulation behavior. table 2?53 lists the i/o pin states du ring power down for normal operation, power down, and pma lookback. table 2?53. i/o pin states during power-down (part 1 of 2) operation transmitter pins receiv er pins refclk pins rref pins normal operation transmitter receiver clk input ext. reference r power down tri-state (1) tri-state (1) tri-state (2) low (3)
altera corporation 2?221 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview timequest timing analyzer for stratix ii gx designs, you can ei ther use the classic timing analyzer or timequest for static timing analysis. timequest does not automatically constrain the transceiver reset po rts and asynchronous input/output ports. as a result, ti mequest does not perform timing analysis on these paths. timequest reports these unconstrai ned paths in red in the timing analyzer report. you must manually add the constraints in the synopsys design constraints ( .sdc ) file for timequest to analyze these paths. unconstrained reset ports in the quartus ii software versions 7.1 and 7.1 sp1, timequest does not constrain the following transceiver reset ports: gxb_powerdown tx_digitalreset rx_digitalreset rx_analogreset identifying unconstrained reset ports to identify the unconstrained rese t/powerdown ports, follow these steps: 1. after compiling your design, select the timequest timing analyzer in the to o l s drop-down menu. this opens up the quartus ii timequest timing analyzer window. pma loopback serial loopback tri-state (4) toggle receiver (5) ?? reverse serial loopback transmitter (4) receiver ? ? notes to table 2?53 : (1) either leave these pins floating or connect n_leg to gnd through a 10-k resistor and connect p_leg to gxb_vcc through a 10-k resistor to improve the device?s immunity to noise. (2) either leave these pins floating or connect refclk(n) to gnd through a 10-k resistor and connect refclk(p) to gxb_vcc through a 10-k resistor to improve the device?s immunity to noise. (3) altera recommends driving the reference resistor pin low for the powered down transceiver block. (4) all supported vods. (5) it must be left floating or driven to a constant value. table 2?53. i/o pin states during power-down (part 2 of 2) operation transmitter pins receiv er pins refclk pins rref pins
2?222 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down 2. in the ta s k s pane, execute report unconstrained paths . this will report all unconstrained paths in red in the report pane. 3. expand the unconstrained paths option in the report pane and further expand the setup analysis or hold analysis option. 4. under setup analysis or hold analysis , you will see unconstrained input port paths , unconstrained output port paths , or both, depending on how the reset/powerdown ports are driven. a. if a reset/powerdown port is driv en by an input pin, it will be listed in the unconstrained input port paths report. b. if a reset/powerdown port is driven by synchronous logic, it will be listed in the unconstrained output port paths report. 5. in the unconstrained input port paths and unconstrained output port paths reports, the unconstrained reset/powerdown ports of your alt2gxb instances are listed under the to column. consider the design example in figure 2?163 . figure 2?163. example design for timeq uest timing analyzer constraints in the design example in figure 2?163 , all reset/powerdown ports except the tx_digitalreset port for the two channels are driven by the reset controller. the tx_digitalreset port is driven from an input pin. figures 2?164 and 2?165 show the timequest timing analyzer report for unconstrained input port paths and unconstrained output port paths , respectively. alt2gxb channel 0 reset controller alt2gxb channel 1 top_tx_digitalreset gxb_powerdown rx_digitalreset rx_analogreset
altera corporation 2?223 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview figure 2?164. unconstrained input port paths
2?224 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down figure 2?165. unconstrained output port paths having identified the unconstrai ned reset/powerdown ports in the design, the next step is to constrain these ports. setting reset/powerdown port timing constraints you must add the reset/powerdown po rt timing constraints either directly in the sdc file or throug h the timequest timing analyzer gui. to add the timing constraints usin g the timequest gui, follow these steps: 1. locate the reset/powerdown ports in either the unconstrained input port paths or unconstrained output port paths report. 2. right click on the reset/powerdown port in the to column and select set max delay . on the resulting window, enter an initial delay value of 4 ns.
altera corporation 2?225 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 3. right click on the reset/powerdown port in the to column again and select set min delay . on the resulting window, enter an initial delay value of 1.2 ns. 1 the difference between the maximum delay and minimum delay is set to 2.8 ns which is the maximum skew allowed on reset/powerdown ports. 4. similarly, set the maximum and minimum delay for all transceiver reset/powerdown ports in your design. 5. execute update timing netlist and write sdc file by double-clicking these options in the ta s k s pane of the timequest timing analyzer window. conf irm that the above timing constraints were added to the sdc file linked with your design. 6. run the quartus ii fitter. 7. after the quartus ii fitter operation completes, execute update timing netlist by double-clicking this option in the ta s k s pane of timequest timing analyzer window. 8. execute report top failing paths by double-clicking this option in the ta s k s pane of the timequest timing analyzer window. 9. assuming all other paths in your design meet timing, one or more of the paths involving reset/powe rdown ports might report timing violations. this is because the design is not able to meet the preliminary timing constraints of 4 ns (maximum delay) and 1.2 ns (minimum delay). 10. note the slack in the timing report for all failing paths and adjust the maximum delay and the minimum delay values in the sdc file. maintain a difference of 2.8 ns between the maximum delay and the minimum delay for each reset/powerdown port. 11. after adjusting the delay values, execute update timing netlist and run the quartus ii fitter again. 12. after the quartus ii fitter operation completes, execute update timing netlist . 13. execute report top failing paths once again. if there are any failing paths involving the reset/powerdown ports, adjust the delay values in the sdc file and repeat the pr ocedure until no failing paths are reported.
2?226 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down consider the previous design exampl e in which all unconstrained ports were identified. the following exam ple shows how to set the constraints for the gxb_powerdown port. the same procedure must be followed for all other reset ports. after setting the maximum and minimum delay for the gxb_powerdown port, the sdc file should ha ve the following constraints: #**************************************************** # set maximum delay #**************************************************** set_max_delay -from [get_keepers {reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd own}] -to [get_ports {pipe_datagen_ch:inst|alt2gxb:alt2gxb_component|chann el_quad[0].cent_unit~observablequadreset}] 4.000 #**************************************************** # set minimum delay #**************************************************** set_min_delay -from [get_keepers {reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd own}] -to [get_ports {pipe_datagen_ch:inst|alt2gxb:alt2gxb_component|chann el_quad[0].cent_unit~observablequadreset}] 1.200 after running the quartus ii fitter wi th the above timing constraints for the gxb_powerdown port, the following slack is reported on this path after executing report top failing paths ( figure 2?166 ). figure 2?166. slack reported for the gxb_powerdown port
altera corporation 2?227 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview since the data arrival time is later th an the data required time by 0.798 ns, the maximum delay and minimum delay should both be incremented by 0.8 ns in the sdc file. the new sdc file should have the following modified constraints for the gxb_powerdown port. #*************************************************** # set maximum delay #**************************************************** set_max_delay -from [get_keepers {reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd own}] -to [get_ports {pipe_datagen_ch:inst|alt2gxb:alt2gxb_component|chann el_quad[0].cent_unit~observablequadreset}] 4.8 #**************************************************** # set minimum delay #**************************************************** set_min_delay -from [get_keepers {reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd own}] -to [get_ports {pipe_datagen_ch:inst|alt2gxb:alt2gxb_component|chann el_quad[0].cent_unit~observablequadreset}] 2.000 after modifying the sdc file and ru nning the quartus ii fitter, the update timing netlist option should be ex ecuted, followed by report top failing paths . if the gxb_powerdown port still shows in the failing paths, modify the slack appropriatel y in the sdc file and repeat the procedure until timing is met on this path. follow the same procedure to set timi ng constraints on all transceiver reset/powerdown ports in your design. 1 you should set constraints and meet timing for both fast and slow timing models. the same maximum and minimum delay constraints might not be able to meet timing for both timing models. this is acceptable as long as the skew is within the specified period (2.8 ns) for each path in the sdc file for each timing model.
2?228 altera corporation stratix ii gx device handbook, volume 2 october 2007 reset control and power down unconstrained asynchronous alt2gxb ports in the quartus ii software versions 7.1 and 7.1 sp1, timequest does not automatically constrain transceiver asynchronous input/output ports. these ports are listed in table 2?54 . you must manually add the timing constraints in the sdc file for timequest to analyze these paths. for these asynchronous ports, you only need to set a maximum delay constraint of 10 ns in the sdc file. to identify all unconstrained alt2 gxb asynchronous ports, execute report unconstrained paths in timequest timing analyzer after running the quartus ii fitter. set a maximum delay of 10 ns for all such ports in the sdc file. for example, if the rx_invpolarity signal is driven by the signal top_rx_invpolarity on an input pin, the sdc file constraint for this port should be set as: set_max_delay -from [get_ports {top_rx_invpolarity}] -to [get_keepers {xcvr_inst.receive~observableinvpol}] 10.000 table 2?54. timequest port names versus alt2gxb port names timequest port name alt2gxb port name ala2size rx_ala2size enapatternalign rx_enapatternalign bitslip rx_bitslip rlv rx_rlv invpol rx_invpolarity enabyteord rx_enabyteord pipe8b10binvpolarity pipe8b10binvpolarity revbitorderwa rx_revbitorderwa bisterr rx_bisterr bistdone rx_bitstdone phaselockloss rx_pll_locked freqlock rx_freqlocked seriallpbkben rx_seriallpbken
altera corporation 2?229 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview follow the same procedure to constrain all asynchronous alt2gxb ports in your design before closing timing analys is for your design. calibration blocks the stratix ii gx gigabit transceiver bl ock contains calibration circuits to calibrate the on-chip termination, th e plls, and the outp ut buffers. the calibration circuits are divided into two main blocks: the pll and output buffer calibration block and the term ination resistor calibration block (refer to figure 2?167 ). each transceiver block contains a pll and output buffer calibration block th at calibrates the plls and output buffers within that particular transceiver block. ea ch device contains one termination resistor calibration block that calibrates all the termination resistors in the transceiver channels of the entire device. figure 2?167. calibration block pll and output buffer calibration block each stratix ii gx transceiver block contains a pll and output buffer calibration circuit to counter the effects of pvt (process, voltage, and temperature) on the pll and output buffer. each transceiver block?s calibration circuit uses a voltage re ference derived from an external reference resistor. there is one referenc e resistor required for each active transceiver block in stratix ii gx de vices. unused transceiver block?s (except the transceiver blocks feeding the termination resistor calibration block) can be left unconnected or be tied to the 3.3-v transceiver analog vcc (if the transceiver block?s 3.3-v an alog supply is connected to 3.3 v). termination resistor calibration block pll and output buffer calibration block calibration_clk cal_blk_powerdown rref reference signal
2?230 altera corporation stratix ii gx device handbook, volume 2 october 2007 calibration blocks termination resistor calibration block the stratix ii gx transceiver?s on-chip termination resistors in the transceiver channels of the entire device are calibrated by a single calibration block. this block ensures that pr ocess, voltage, and temperature variations do not have an impact on the termination resistor value. there is only one termination resistor calibration block per device. the calibration block uses the referenc e resistor of transceiver block 0 or transceiver block 1, depending on th e device. the calibration block uses the reference resistor in transcei ver block 0 for ep2sgx30 and ep2sgx60 devices and the reference resistor in transceiver block 1 for ep2sgx90 and ep2sgx130 devices. a reference resistor must be connected to either transceiver block 0 or transceiver bloc k 1 to ensure proper operation of the calibration block, whether or n ot the transceiver block is in use. failing to connect the reference resis tor of the transceiver block feeding the calibration block results in incorrect termination values for all the termination resistors in the tran sceivers of the entire device. the termination resistor calibration circuit requires a calibration clock. you can use a global clock line if the refclk pins are used for the reference clock. you can instantiate a calibration clock port in the megawizard to supply your own clock through the cal_blk_clk port. the frequency range of the cal_blk_clk is 10 mhz to 125 mhz. if there are no slow-speed clocks availabl e, use a divide-down circuit (for example, a ripple counter) to divide the available clock to a frequency in that range. the quality of the calibratio n clock is not an issue, so pld local routing is sufficient to route the calibration clock. for multiple alt2gxb instances in the same device, if all the instances are the same, the calibration block must be active and the cal_blk_clk port of all instances must be tied to a common clock. physically, there is one cal_blk_clk port per device. the quartus ii software provides an error message if the cal_blk_clk port is tied to different clock sources, because this would be impossible to fit into a device. if there are different configurations of the alt2gxb in stance, only one must have the calibration block instantiated. if multiple instances of the alt2gxb custom megafunction vari ation have the calibration block instantiated, then all the cal_blk_clk ports must be tied to the same clock source. the calibration block can be powered down through the optional cal_blk_powerdown port (this is an active low input). powering down the calibration block during operatio ns may yield transmit and receive data errors. only use this port to re set the calibration block to initiate a recalibration of the termination resistors to account for variations in
altera corporation 2?231 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview temperature or voltage. the minimum pu lse duration for this port is to be determined by characterization. if ex ternal termination is used on all signals, the calibration block in alt2gxb need not be used. referenced documents this chapter references the following documents: alt2gxb megafunction user guide chapter in volume 2 of the stratix ii gx device handbook sdi megacore function user guide specifications & addi tional information chapter in volume 2 of the stratix ii gx handbook . stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook document revision history table 2?55 shows the revision history for this chapter. table 2?55. document revision history (part 1 of 6) date and document version changes made summary of changes october 2007, v4.2 updated: figure 2?1 figure 2?9 figure 2?12 figure 2?13 figure 2?14 figure 2?15 figure 2?38 figure 2?39 figure 2?44 figure 2?51 figure 2?70 figure 2?118 ? updated: ta b l e 2 ? 1 ta b l e 2 ? 3 ta b l e 2 ? 6 ta b l e 2 ? 8 table 2?18 table 2?19 table 2?24 ?
2?232 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history updated: ?reverse serial pre-cdr loopback? ?(oif) cei-phy interface mode? ?clock synthesis? ?clock multiplier unit? ?receiver pll? ?rate matcher? ?transmitter bit reversal? ?receiver common mode? ?native modes? ?basic single-width mode? ?basic double-width mode? ?sonet/sdh mode? ?receiver bit reversal? ?pattern detector module? ?channel clock distribution? ?low-latency pipe mode? ?synchronization (word aligner)? ?timequest timing analyzer? ? added: ?referenced documents? ?serial digital interface (sdi) mode? ?serial rapidio mode? ?cpri mode? ?dc coupling? ?basic single-width mode with x4 clocking? ? added table 2?2 .? minor text edits. ? table 2?55. document revision history (part 2 of 6) date and document version changes made summary of changes
altera corporation 2?233 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview august 2007, v4.1 moved the dynamic reconfigurati on section. the dynamic reconfiguration section was moved to the stratix ii gx dynamic reconfiguration chapter in this handbook. added table 2?45. ? added note to ?serializer? and ?deserializer?. ? updated the ?ntfs fast recovery ip (nfri)? section. ? updated: ?double-width general rate matching? and figure 2?73 in the same section ?pci express receiver detect? ?receiver detect? ?native modes? (introduction) ?xaui mode? ?manual 7-bit alignment mode? ?manual 8-bit alignment mode? ?manual 10-bit alignment mode? ?manual 16-bit alignment mode? ?manual 20-bit alignment mode? ?manual 32-bit alignment mode? figure 2?72 figure 2?73 ? updated table 2?6 and figure 2?62. ? added the ?timequest timing analyzer? section. ? added ?reverse serial pre-cdr loopback? section. ? february 2007, v4.0 replaced old dynamic rec onfiguration section with a new ?dynamic reconfiguration? section. ? added the ?document revision history? section to this chapter. ? updated figures 2?1, 2?2, 2?4, 2?8, 2?9, 2?11, 2?12, 2?20, 2?118, 2?119, 2?120 ? table 2?55. document revision history (part 3 of 6) date and document version changes made summary of changes
2?234 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history added the following sections: ?transmitter phase compensation fifo error flag? ?transmitter force disparity? ?transmitter polarity inversion? ?transmitter bit reversal? ?generic receiver polarity inversion? ?receiver bit reversal? ?receiver byte reversal? ?pld-controlled byte ordering? ?receiver phase compensation fifo error flag? ?multiple protocols and data rates in a transceiver block? ?low-latency pipe mode? ?design flow? ? added pld interface clock resources section, including: tables 2?21 through 2?26. ? updated tables 2?1, 2?9, 2?45. ? updated content from ?transmitter modules? through ?byte serializer?. ? updated and moved pld transceiver information to ?receiver phase compensation fifo error flag?. ? sections modified: ?receiver detect? ?reverse serial loopback? ?signal threshold detection circuit? ?parallel loopback? ?clock synthesis? ?double-width mode? ?inter-transceiver line routing? ?serial loopback? ?loopback modes? ?bist in single-width mode? ?bist in double-width mode? ?transmitter buffer? ?transmitter pll block? ?transmitter pll bandwidth setting? ?transmitter polarity inversion? ? table 2?55. document revision history (part 4 of 6) date and document version changes made summary of changes
altera corporation 2?235 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx transceiver architecture overview 622 mbps was changed to 600 mbps in: ?transmitter pll block? ?transmitter plls? ?serializer? ?receiver buffer? ?receiver common mode? ?deserializer? ? 3.125 to 6.375 gbps was changed to 1 to 6.375 gbps in: ?serializer? ?deserializer? ?native modes? ? updated note in ?normal operation phase? section. ? the automatic mode section was updated and changed to ?word alignment based on byte ordering?. ? changed ?bits[15..8]? to ?bits[31..24? in the ?32-bit pattern mode? section ? changed ?rx_outrx_dataout? to ?rx_dataout? in the ?gige receiver synchronization? section. ? added new note to the ?dynamic transmit rate switch? and ?dedicated reference clock pin specifications? sections. ? changed v cchtx to v cch throughout the chapter. changed tx v cm to v cm throughout the chapter. changed vcc_h to vcch throughout the chapter. ? june 2006, v3.2 minor change to figure 2?1. updated table 2?1. updated figures 2?90 and 2?96. added ?ntfs fast recovery ip (nfri)? section. updated descriptions for rx_errdetect and cal_blk_powerdown in table 2?1. table 2?55. document revision history (part 5 of 6) date and document version changes made summary of changes
2?236 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history april 2006, v3.1 added ?dedicated reference clock pin specifications? section, including table 2?3 and figure 2?3. updated figures 2?9, 2?16, 2?21, 2?22, 2?30, 2?35, 2?52, 2?53, 2?57, 2?68, 2?69, 2?73, 2?83, 2?84, 2?109, 2?110, and 2?118. updated data rate in ?deserializer? section. added ?7-bit alignment mode? section. removed references to the rx_runningdisp port. updated ?manual sonet alignment mode (two consecutive 8-bit charac ters (a1a2) or four consecutive 8-bit char acters (a1a1a2a2))? section. updated ?manual alignment modes? section. updated ?code error detect? section. updated ?disparity error detector? section. added ?reset sequence for pipe mode? section, including figures 2?119 and 2?120. updated ?dynamic reconfiguration setup for alt2gxb instance? section. updated table 2?34. updated tx_preemp_2t port description in table 2?34 . february 2006, v3.0 updated technical content throughout chapter. added ?dynamic reconfiguration? section. ? december 2005, v2.0 updated technical content throughout chapter. ? october 2005 v1.0 added chapter to the stratix ii gx device handbook . ? table 2?55. document revision history (part 6 of 6) date and document version changes made summary of changes
altera corporation 3?1 october 2007 3. stratix ii gx dynamic reconfiguration introduction the stratix ? ii gx gigabit transceiver bloc k gives you a simplified means to dynamically reconfigure: transmit and receive analog settings transmit data rate in the multiples of 1, 2, and 4 one channel at a time channel and clock multiplier unit (cmu) pll cmu pll only typically, to achieve the intended bit error rate (ber) for a system, you will take advantage of the multiple analog settings provided in the stratix ii gx device. being able to change the analog settings is a powerful tool that you can use during link and system debug. the following analog settings can be dynamically changed: pre-emphasis settings equalization settings dc gain settings voltage output differential (v od ) settings in addition to allowing you to change the equalization settings during runtime, the dynamic reconfiguration controller provides an option to dynamically control the adaptive equalization (aeq) hardware present in each of the transceiver channe ls. the aeq hardware continuously tunes the receiver equalization setting s based on the frequency content of the incoming signal. the dynamic data rate switch feature on the transmitter is enabled through a pld signal. depending on the setting of this signal, the transmitter data rate can be divided in steps of 1, 2, or 4 per channel. another important feature is the ability to dynamically reconfigure from one mode to another mode. this mode reconfiguration may involve reconfiguring the transceiver data path or data rate or both. you can reconfigure the transceiver data rate either by switching to the other cmu pll or by dynamically reconfiguring the cmu pll. the former is enabled in the quartus ? ii software version 6.1 and later, while the latter is enabled in the quartus ii so ftware version 7.1 and later. siigx52007-1.1
3?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture the dynamic reconfiguration feature facilitates mode transitions involving: protocol functional mode (1 only ) to and from basic functional mode protocol functional mode (1 only ) to protocol functional mode (1 only) one basic functional mode to other basic functional modes this is a very useful and powerf ul feature for transceiver system applications because it enables channels in a system to adapt to multiple serial data rates and system protocols. table 3?1 shows dynamic reconfiguration features supported in various quartus ii software versions. dynamic reconfiguration controller architecture the stratix ii gx device offers a simplified dynamic reconfiguration controller in the quartus ii alt2gxb_reconfig module to control the configurable settings of the transc eiver. the dynamic reconfiguration controller is a soft ip which utilizes stratix ii gx device pld resources. it is optimized for minimal pld resource usage. only one controller is allowed per transceiver block. the dynamic reconfiguration controller does not have the capability to cont rol multiple stratix ii gx devices or any off-chip interface. 1 the dynamic reconfiguration capability is only intended for stratix ii gx devices, having no backward compatibility to stratix gx devices. stratix ii gx dynamic reconfiguratio n is very flexible because of the following features: two transmit plls enabled?this allows you to achieve multiple data rates and protocols in a single transceiver block. table 3?1. software support for dynamic reconfiguration version transmitter and receiver analog settings (pma controls) transmitter data rate switch (1, 2, 4) channel reconfiguration channel and cmu pll reconfiguration cmu pll-only reconfiguration quartus ii 6.0 v ???? quartus ii 6.1 vvv ?? quartus ii 7.1 vvvvv
altera corporation 3?3 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration basic double-width modes?the minimum data rate is lowered to 1 gbps. this helps if you want to only switch data rates without changing the data path width. more optional features in basic mode. pld interface clocking of the transc eiver is enhanced by introducing ?core clocking options?. these co re clocking options help you optimize clock resource usage and allows you to set up the proper pld interface clocking on transmit and receive paths. figure 3?1 shows a conceptual view of these features. figure 3?1. block diagram of the dynamic rec onfiguration controller (alt2gxb_reconfig) the following items are not suppo rted as part of the dynamic reconfiguration feature: mode switch to and from any 4 and 8 configurations not backward compatible with stratix gx devices to and from pci express (pipe) mode with nfri ip testability features (pseudo-ra ndom binary sequence [prbs] and built-in self test [bist]) logical_channel_address[7:0] reconfig_togxb[2:0] address translation addr data reconfig_mode_sel[2:0] reconfig_data[15:0] pma control logic before qii 6.0 sp1 channel reconfiguration control logic dynamic reconfig parallel to serial converter reconfig_address_out reconfig_address_en channel_reconfig_done rate_switch_ctrl[1:0](tx-only) dynamic rate switch logical_tx_pll_sel_en logical_tx_pll_sel channel and cmu pll reconfiguration control logic pma controls (pe, eq, dc gain, vod) write_all read reconfig_fromgxb reconfig_clk data_valid busy error
3?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture dynamic reconfiguration setup in the megawizard plug-in manager the optional dynamic reconfiguratio n interface must be enabled through the megawizard ? plug-in manager (dynamic reconfiguration is turned off by default). the dynamic reconfiguration interface has the following signals: reconfig_togxb[2:0] as an input signal bus reconfig_fromgxb as an output signal from alt2gxb instance. reconfig_fromgxb is a transceiver block-based signal; for example, if the number of the channels selected in alt2gxb are: 0 < channels < 4, then signal reconfig_fromgxb = 1 bit 4 < channels < 8, then signal reconfig_fromgxb = 2 bits 8 < channels < 12, then signal reconfig_fromgxb = 3 bits 12 < channels < 16, then signal reconfig_fromgxb = 4 bits 16 < channels < 20, then signal reconfig_fromgxb = 5 bits after the dynamic reconfiguration op tion is enabled in the alt2gxb megawizard, you must set one more setting?the what is the dynamic reconfig starting channel number? option. the dynamic reconfiguration starting channel number setting range is from 0 - 156 in multiples of 4 (because the dynamic reconfiguration interface is per transceiver block). this range of 0 - 156 is the logical channel address based purely on the number of possible alt2gxb instances. to better understand how logical addressing works, consider the scenario of 20 separate transmit and receive instances of the alt2gxb megafunction in a design and how to set the address of the starting channel of each instance. the first instance of a transmit an d receive channel has the starting channel number setting of 0 . the second instance of a transmit and receive channel has the starting channel number setting of 4 . and so on. the twentieth instance of the same co nfiguration has the starting channel number of 76 . extending the same logic to the maxi mum possible instances case of 20 transmit-only and 20 receive-only co nfigurations, targeted for a five transceiver block stratix ii gx de vice, the maximum starting channel number of the dynamic reconfiguration option is 156 (40 instances * 4). configure the alt2gxb_reconfig and the alt2gxb modules, depending on the number of transceive r channels that are controlled by the dynamic reconfig controller (a lt2gxb_reconfig). use the logical channel views with the above mentioned logical addressing in the
altera corporation 3?5 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration alt2gxb instance. the quartus ii fi tter errors out if the dynamic reconfiguration option is enabled in the alt2gxb megafunction, but the reconfig_fromgxb and reconfig_togxb ports are not connected to the alt2gxb_reconfig instance. the megafunction and pre-fitter au tomatically map the logical channel into the physical placements. this physical placement includes merging (automatically done by the quartus ii software). the software performs merging (packing channels into the sa me transceiver block) only when multiple channels of the same data ra te and data path configuration are controlled by one dynamic reconfiguration (alt2gxb_reconfig) controller instance. channe ls connected to multiple alt2gxb_reconfig controllers will not be merged. dynamic reconfiguration controller interface the dynamic reconfiguration controller supports write and read transactions. figure 3?2 shows the dynamic reconfiguration interface list. the following transactions are allowed, based on the dynamic reconfiguration features: analog settings reconfiguration?write and read (read is optional) channel reconfiguration?write transaction only dynamic transmit rate switch?wri te and read (read is optional) channel and cmu pll reconfiguration cmu pll-only reconfiguration
3?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture figure 3?2. dynamic reconf iguration interface notes to figure 3?2 : (1) optional control and status signals. at least one control signal must be enabled if only analog settings reconfiguration is enabled. (2) if the channel reconfiguration feature is sele cted in the alt2gxb_reconfig megawizard, the reconfig_address_out is 5-bits wide [4..0]. if the channel and txpll select/reconfig feature is selected, the reconfig_address_out is 6-bits wide [5..0]. the reconfig_mode_sel signal determines the reconfiguration mode. this control signal is 3-bits wide if the adaptive equalization control option is not selected. if this option is selected, the reconfig_mode_sel signal is 4-bits wide. encoding of the reconfig_mode_sel signal (when the adaptive equalization control option is not selected) is as follows: reconfig_mode_sel [2:0] : 000 ? reconfiguration of analog controls. the analog controls feature has been enabled in the quartus ii software version 6.0 and later 001 ? channel reconfiguration 011 ? dynamic transmit rate switch 100, 101, 110 ? channel and cmu pll reconfiguration rx_eqdcgain[1..0] (1) dynamic reconfig reconfig_clk reconfig_fromgxb tx_preemp_1t[3..0] (1) read write_all tx_vodctrl[2..0] (1) rx_eqctrl[3..0] (1) tx_preemp_0t[3..0] (1) reconfig_togxb[2..0] data_valid tx_preemp_2t_out[3..0] (1) busy tx_vodctrl_out[2..0] (1) rx_eqctrl_out[3..0] (1) rx_eqdcgain_out[1..0] (1) tx_preemp_0t_out[3..0] (1) tx_preemp_1t_out[3..0] (1) tx_preemp_2t[3..0] (1) reconfig_mode_sel[] channel_reconfig_done reconfig_address_en reconfig_address_out[5..0] (2 ) rate_switch_ctrl [1..0] rate_switch_out [1..0] reconfig_data[15..0] reset_reconfig_address logical_tx_pll_sel_en logical_tx_pll_sel error
altera corporation 3?7 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 1 refer to ?channel and pma controls reconfiguration? on page 3?20 and ?channel and clock multiplier unit (cmu) pll reconfiguration? on page 3?87 for detailed reconfig_mode_sel[2:0] signal encoding. as described in ?stratix ii gx alt2gxb megafunction user guide? on page 4?1 , the signals reconfig_togxb[2:0] and reconfig_fromgxb are the interface signals between the alt2gxb instance and the alt2gxb_reconfig instance. the dynamic reconfiguration controller runs at a frequency determined by the clock reconfig_clk signal. the supported frequency range of the reconfig_clk is 2.5mhz?50mhz. 1 altera recommends the reconfig_clk signal be driven on a global clock resource. you must set the following two settings in the alt2gxb_reconfig megawizard: 1. what is the number of channe ls controlled by the controller? you must provide the number of channels for the megafunction, depending on the design setup suppo rted. there are two ways of using dynamic reconfiguration controllers. they are: single dynamic reconfiguratio n controller?one controller controlling all the instances of the alt2gxb in a device. when multiple instances of the alt2gxb me gafunction are controlled by a single alt2gxb_reconfig controller, the following rules should be followed for setting the ? what is the number of channels controlled by the controller ?? option: each instance of the megafunction must have a set of the consecutive channel numbers begi nning with a unique number that is a multiple of four. the number of channels controll ed is the last channel number. multiple dynamic reconfiguration controllers?for multiple instances of the alt2gxb, it is not possible to have two dynamic reconfiguration controllers contro lling the same alt2gxb instance. one controller is allowed to control multiple alt2gxb instances or every channel will have its own dynamic reconfiguration controller. if every channel has its own dyna mic reconfiguration controller, there may be problems with fitting. the quartus ii software cannot merge multiple transceiver channel instances into a transceiver block if multiple dynamic reconfiguration controllers are used, even if the channels are configured to the same protocol fu nctional mode and data rate.
3?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture for example, alt2gxb instance1 has five channels of the same data rate and functional mode; alt2gxb instance2 has three channels of same data rate and functional mode. both alt2gxb instances have separate dynamic reconfiguration controllers controlling them. these two alt2gxb instances (a total of eight channels) cannot be merged in to two transceive r blocks. these two instances can be merged only if they are controlled by one dynamic reconfiguration contro ller. this merging will not change the behavior of the si licon compared to functional simulations. 2. use the same control signals for all channels . check this option when you know th at the same analog control signals are used for all the channels in the design. by checking this option, the quartus ii software uses one set of an alog signals to control all channels used in all transceiver bl ocks that are controlled by this reconfiguration controller. table 3?2 describes the ports for the dynamic reconfiguration controller. table 3?2. port list of the dyna mic reconfiguration c ontroller (alt2gxb_rec onfig) (part 1 of 6) port name input/output description reconfig_clk input input reference clock for the dynamic reconfiguration controller. the frequency range of this clock is 2.5 mhz to 50 mhz. the assigned clock uses global resources by default. this same clock should be connected to alt2gxb. alt2gxb - alt2gxb_reconfig interface signals reconfig_fromgxb input interface bus signal from alt2gxb to alt2gxb_reconfig instance. the width of the signal in alt2gxb_reconfig is determined by the number of channels controlled by the controller. reconfig_togxb[2..0] output fixed bus interface between alt2gxb_reconfig and alt2gxb. this signal is independent of the number of channels. pld interface signals write_all input control signal to initiate a write transaction. this signal is active high. when the analog settings (v od , equalization, etc.) are reconfigured, the rec onfiguration controller writes to all the transceiver channel s connected to the controller. busy output status signal to indicate th at the reconfiguration controller has not completed the read or write transaction.
altera corporation 3?9 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration read input control signal to initiate a read transaction. this signal is active high. when the analog settings (v od , equalization, etc.) are read, the reconfigur ation controller reads the analog setting values from all the transceiver channels connected to the controller. w hen you select this signal, at least one of the output control ports (for example, tx_vodctrl_out ) should be selected. otherwise, when you initiate a read trans action, the reconfiguration controller may get into a deadlock state (since it cannot send data to any output). data_valid output status signal for the read transaction. if data_valid is high, the read back data is valid. that is, the current data on the output control signals after data_valid is asserted high is the valid data read out. this signal is only enabled when at least one read control port is enabled. when a read control port is enabled and a write transaction is finished, the data_valid signal goes high and the busy signal goes low. error output optional status signal to indicate that an unsupported operation is attempted. the error port can be enabled by selecting the options in the error checks/data rate switch tab. the dynamic reconfiguration controller de-asserts the busy signal and asserts the error signal for two reconfig_clk cycles when you attempt an unsupported operation. table 3?2. port list of the dyna mic reconfiguration c ontroller (alt2gxb_rec onfig) (part 2 of 6) port name input/output description
3?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture analog settings control/status signals tx_vodctrl input optional transmit buffer voltage output differential (v od ) control signal. it is 3-bits per channel. the number of settings varies based on the transmit buffer supply setting and the termination resistor setting in alt2gxb instance. the following shows the v od values corresponding to the tx_vodctrl settings for 100- termination. for v od values corresponding to other termination settings, refer to table 2?8 . tx_vodctrl v od (mv) v od (mv) for 1.5v v cch for 1.2v v cch 000 n/a n/a 001 400 320 010 600 480 011 800 640 100 1000 800 101 1200 960 110 1400 n/a 111 n/a n/a tx_preemp_0t (1) input optional pre-emphasis cont rol for pre-tap for the transmit buffer. it is 4-bits per channel . this signal controls both pre-emphasis positive and its inversion. 0 represents 0 1?7 represents -7 to -1 9?15 represents 1 to 7 8 maps to 0 tx_preemp_1t (1) input optional pre-emphasis cont rol for first post tap for the transmit buffer. it is 4-bits per channel. tx_preemp_2t (1) input optional pre-emphasis cont rol for second post-tap for the transmit buffer. it is 4-bits pe r channel. this signal controls both pre-emphasis posit ive and its inversion. 0 represents 0 1?7 represents -7 to -1 9?15 represents 1 to 7 8 maps to 0 rx_eqctrl input optional equalization control signal on the receive side of the pma. it is a 4-bit bus per each channel. table 3?2. port list of the dyna mic reconfiguration c ontroller (alt2gxb_rec onfig) (part 3 of 6) port name input/output description
altera corporation 3?11 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration rx_eqdcgain (2) input optional equalizer dc gain control. it supports three legal settings and is 2-bits wide per channel. 00 corresponds to 0 db 01 and 10 correspond to 3 db 11 corresponds to 6 db tx_vodctrl_out output optional transmit v od output signal. this signal reads out the value written into the v od control register. the signal width of this output signal is the same as its corresponding input signal. tx_preemp_0t_out output optional pre-tap, pre-em phasis output signal. this signal reads out the value written by its input control signal. the signal width of this output signal is the same as its corresponding input control signal. tx_preemp_1t_out output optional first post-tap, pre-emphasis output signal. this signal reads out the value written by its input control signal. the signal width of this output signal is the same as its corresponding input control signal. tx_preemp_2t_out output optional second post-t ap pre-emphasis output signal. this signal reads out the val ue written by its input control signal. the signal width of this output signal is the same as its corresponding input control signal. rx_eqctrl_out output output signal to read the setting of equalization setting of the alt2gxb instance. the signal width of this output signal is the same as its corresponding input signal. rx_eqdcgain_out output equalizer dc gain output si gnal. this signal reads out the settings of the alt2gxb instance dc gain. the signal width of this output signal is the same as its corresponding input signal. channel reconfiguration signals reset_reconfig_address input synchronous reset signal to the alt2gxb_reconfig to reset the reconfig_address_out port to 0 . use this signal when you want to restart the reconfiguration of a channel by initiating writing the memory initialization file (mif) word 0. reconfig_data[15:0] input sixteen bits input data word. you input it from the location that has the mif to reconfigure the registers. this input port is only used in the channel reconfiguration or channel and cmu pll reconfiguration feature (discussed in ?channel and clock multiplier unit (cmu) pll reconfiguration? on page 3?87 ). table 3?2. port list of the dyna mic reconfiguration c ontroller (alt2gxb_rec onfig) (part 4 of 6) port name input/output description
3?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture reconfig_mode_sel[2:0] input select the reconfiguration mode for the alt2gxb_reconfig megafunction. the signal encoding is as follows: 000 - reconfiguration for analog controls. this feature has been enabled in the quartus ii software version 6.0 and later versions. 001 - channel reconfiguration 010 - not supported (do not attempt to read or write with this value) 011 - dynamic transmit data rate switch *100 - txpll *101 - channel and txpll reconfiguration *110 - channel reconfiguration with txpll select 111 - not supported (do not attempt to read or write with this value) *the features corresponding to these values are discussed in ?channel and clock multiplier unit (cmu) pll reconfiguration? on page 3?87 . logical_channel_address [channel_address_width-1:0] input specify the logical channel address for the channel that needs to be reconfigured. the channel_address_width parameter is determined through the number_of_channels parameter. reconfig_address_out[5:0] output this signal indicates the address out and that the address read out is the current address to be reconfigured by the alt2gxb_reconfig megafunction during channel reconfiguration. this signal is 5-bit wide in channel reconfiguration mode and 6-bit wide in channel and cmu pll reconfiguration mode. reconfig_address_en output this port indicates the current address to be reconfigured for the alt2gxb_reconfig megafunction had already changed during channel reconfiguration. channel_reconfig_done output this port indicates that the alt2gxb_reconfig megafunction has finished writi ng all the words of a mif. this is only applicable for channel reconfiguration mode. dynamic transmit rate switch signals rate_switch_ctrl[1:0] input this input is the control si gnal to write the desired division factors on a per-channel transmitter basis. this port is only applicable when reconf_mode_sel is set to 011 . the output value is listed below: 00 - divide by 1 01 - divide by 2 10 - divide by 4 11 - not supported (do not attempt to read or write with this value) table 3?2. port list of the dyna mic reconfiguration c ontroller (alt2gxb_rec onfig) (part 5 of 6) port name input/output description
altera corporation 3?13 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration dynamic configuration controller (alt2gxb_reconfig), alt2gxb design examples the following design examples illustrate the various possible topologies of the dynamic reconfiguration contro ller with alt2gxb instances. the first two design examples specifically discuss a single controller controlling multiple instances of an alt2gxb and a single controller controlling one instance of an alt2gxb. design example three discusses the hdl construct needs if you are stamping the alt2gxb instances. each instance of an alt2gxb in turn can have more than one transceiver channel. also, in all the design examples, it is assumed that only the analog (pma) settings reconfigurat ion is enabled, to simplify the illustration. in the real system, you can enable other supported features along with the analog setting reconfiguration. example 1 consider a design with two instan ces of an alt2xgb configuration, instance1 with five transceiver ch annels and instance2 with three transceiver channels. rate_switch_out[1:0] output this signal reads out the value that has written in for the rate switch of specified transmitter outputs. this output port is only applicable when reconf_mode_sel is set to 011 . the output value is listed below: 00 - divide by 1 01 - divide by 2 10 - divide by 4 channel and cmu pll reconfiguration logical_tx_pll_sel input this control signal allows you to select the cmu pll that you wish to reconfigure. it also allows you to select the cmu pll to which the channel is listening in channel reconfiguration with tx pll select mode. refer to ?logical tx pll select? on page 3?105 for more information. logical_tx_pll_sel_en input this signal validates the logical_tx_pll_sel signal. refer to ?logical tx pll select? on page 3?105 for more information. notes to ta b l e 3 ? 2 : (1) not all combinations of bits are legal values. (2) in pipe mode, this input should be tied to 01 to be pci e-compliant. table 3?2. port list of the dyna mic reconfiguration c ontroller (alt2gxb_rec onfig) (part 6 of 6) port name input/output description
3?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture assume the following for this example: instance1 and instance2 cannot be merged due to their configurations. one dynamic reconfiguration controller controls all eight channels. only the transmit v od and receiver equalization controls are enabled. the following are the typical steps that help setup the configuration: five channel transceiver instance: in the alt2gxb megawizard, set the what is the number of channels? option to 5 along with other options in the alt2gxb megawizard. enable the analog controls option under the dynamic reconfiguration settings (to dynamically change equalization values, also enable the enable equalizer settings option). the output signal reconfig_fromgxb is transceiver-block based, so the number of bits for this in stance is two since the number of channels is five. the input signal reconfig_togxb is a fixed bus width of three bits. set the what is the startin g channel number? option to 0 . three channel transceiver instance: in the alt2gxb megawizard, set the what is the number of channels? option to 3 . enable the analog controls option under the dynamic reconfiguration settings (to dynamically change equalization values, also enable the enable equalizer settings option). the output signal reconfig_fromgxb is transceiver block based, so the number of bits for this in stance is one since the number of channels is three. the input signal reconfig_togxb is a fixed bus width of three bits. set the what is the startin g channel number? option to 8 . this address of eight is warranted because the previous alt2gxb instance has five channels which logically fits into two transceiver blocks (transceiver blocks with starting channel numbers 0 and 4), and since this case has multiple instances of the alt2gxb controlled by one dynamic controller, the nu mbering is consecutive channel numbers in multiples of four. alt2gxb_reconfig setup for pm a controls re configuration: launch the alt2gxb_reconfig megawizard. set the what is the number of ch annels controlled by the controller? option to 12 . the setting for this option has a number that is more than the total number of channels needed to be controlled
altera corporation 3?15 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration (eight channels) by dynamic reconfig uration. this is needed because based on this setting, the quartus ii software chooses the bus width of the signal reconfig_fromgxb in addition to the width of the analog control signals. in this case, the design needs 3-bits wide signals so the controller can control a total of three transceiver blocks (five channels in two transceiver bl ocks and three channels into one transceiver block). to make it simple, choose the cha nnel number based on a rounded-up channel number to the nearest transcei ver block multiple. in this case, it is eight channels required and since no merging is allowed, eight channels require three transceiver bl ocks. the three transceiver blocks round up to a transceiver block multi ple channel number of 12 (3 4 = 12). refer to the ? 1. what is the number of channels controlled by the controller? ? option in ?dynamic reconfiguration controller interface? on page 3?5 for more information about this setting. select the necessary analog contro l signals to write in and read out for v od and equalization from all th e options available in the megawizard. also note the analog control signal widths are for 12 channels since the above channel se tting is 12. control signals for unused channels 5 to 7 and channel 11 can be tied to logic low (zero/ground). in this design scenario, the v od signal ( tx_vodctrl ) width is 36 bits (12 channel tx_vodctrl[2:0] = tx_vodctrl[35:0] ). tie tx_vodctrl[35:33] and tx_vodctrl[23:15] to ground. use similar methods for the equalization setting. alt2gxb instances and alt2 gxb_reconfig instance connections: connect the reconfig_fromgxb signal from the alt2gxb instance to the same signal in the alt2gxb_reconfig instance. the lowest starting channel number transceiver block is connected to the lowest significant bit and so on . in this case, the configuration instance with five channels of the alt2gxb instance has a starting channel of zero, which has the signal reconfig_fromgxb[1:0] which should be connected to reconfig_fromgxb[1:0] of the alt2gxb_reconfig instance. the other three channel instances of alt2gxb, with a starting ch annel of eight, has the signal reconfig_fromgxb which should be connected to alt2gxb_reconfig reconfig_fromgxb[2] . refer to figure 3?3 for more information. connect the reconfig_togxb signal from the alt2gxb_reconfig instance to th e same signal on the alt2gxb instance.
3?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture figure 3?3. alt2gxb modules with one alt2gxb_reconfig module example 2 this design example has two instan ces of distinct configurations: instance1 with five transceiver ch annels and instance2 with three channels. this configuration requires separate dynamic reconfiguration controllers for the two instances. this scenario covers the case of multiple dynamic reconfiguration controllers co ntrolling multiple instances of the alt2gxb. assume that the analog settings (transmit v od and receive equalization controls) for both instances are enabled. the following are the typical steps to setup the configuration: five channel transceiver instance1: in the alt2gxb megawizard, set the what is the number of channels? option to 5 along with other options in the alt2gxb megawizard. enable the analog controls option under the dynamic reconfiguration settings (to dynamically change equalization values, also enable the enable equalizer settings option). alt2gxb_reconfig reconfig_clk reconfig_fromgxb[2] read write reconfig_togxb[2..0] data_valid busy reconfig_fromgxb[2:0] reconfig_fromgxb[1..0] tx_vodctrl[35..0] rx_eqctrl[47..0] rx_eqctrl_out[47..0] tx_vodctrl_out[35..0] alt2gxb instance (five channels) alt2gxb instance (three channels) what is the number of channels controlled by the controller? in alt2gxb_reconfig is 12 what is the starting channel number? in alt2gxb is 0 what is the starting channel number? in alt2gxb is 8
altera corporation 3?17 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration the output signal reconfig_fromgxb is transceiver-block based so the number of bits for this in stance is two since the number of channels is five. the input signal reconfig_togxb is a fixed width of three bits. set the what is the startin g channel number? option to 0 . dynamic reconfiguratio n controller instance1: launch the alt2gxb_reconfig megawizard. set the what is the number of ch annels controlled by the controller? option to 5 . this option helps th e quartus ii software choose the bus width of the signal reconfig_fromgxb in addition to the width of the analog control signals. in this case, the design needs 2-bits wide signal s so the controller can control a total of two transceiver blocks (five channels in two transceiver blocks). refer to ?introduction? on page 3?1 for more information about this setting. select the necessary analog contro l signals to write in and read out from the v od , pre-emphasis, equalization, and dc gain options for this setup. three channel transceiver instance2: set the what is the number of channels? option to 3 . enable the analog controls option under the dynamic reconfiguration settings (to dynamically change equalization values, also enable the enable equalizer settings option). the output signal reconfig_fromgxb is transceiver block based so the number of bits for this inst ance is one since the number of channels is three. the input signal reconfig_togxb is a fixed width of three bits. set the what is the startin g channel number? option to 0 . this address number of 0 is the same as the previous five channel alt2gxb instance setting. you do not need to have a consecutive channel starting number (multi ples of four) since these two alt2gxb instances are controlled by different dynamic reconfiguration controllers. dynamic reconfiguratio n controller instance2: launch the alt2gxb_reconfig megawizard. set the what is the number of ch annels controlled by the controller? option to 3 . this option helps th e quartus ii software choose the bus width of the signal reconfig_fromgxb , in addition to the width of the analog control signals. in this case, the design needs a 1-bit wide signal so the co ntroller can control a total of one transceiver block (three channels into one transceiver block) and have the option set to at least thr ee so that the quartus ii software enables three channels of the anal og control signals in the options sections.
3?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration controller architecture select the necessary analog contro l signals to write in and read out from the v od , pre-emphasis, equalization, and dc gain options. alt2gxb instances and alt2 gxb_reconfig instance connections: connect the reconfig_fromgxb signal from the alt2gxb instance to the same signal of the corresponding alt2gxb_reconfig instance. refer to figure 3?4 for more information. connect the reconfig_togxb signal from the alt2gxb_reconfig instance to the same signal of the corresponding alt2gxb instance. figure 3?4. alt2gxb_reconfig modules with two alt2gxb modules reconfig_clk reconfig_fromgxb read write reconfig_togxb[2..0] data_valid busy reconfig_fromgxb reconfig_fromgxb[1..0] tx_vodctrl[8..0] rx_eqctrl[11..0] alt2gxb_reconfig reconfig_clk read write reconfig_togxb[2..0] data_valid busy tx_vodctrl[14..0] rx_eqctrl[19..0] rx_eqctrl_out[19..0] tx_vodctrl_out[14..0] reconfig_fromgxb[1:0] tx_vodctrl_out[8..0] rx_eqctrl_out[11..0] what is the starting channel number? in alt2gxb is 0 what is the starting channel number? in alt2gxb is 0 alt2gxb instance (five channels) alt2gxb instance (three channels) what is the number of channels controlled by the controller? in alt2gxb_reconfig is 3 option what is the number of channels controlled by the controller? in alt2gxb_reconfig is 5 alt2gxb_reconfig
altera corporation 3?19 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration example 3 this design example consists of five channels of transceivers with the same data rate and functional mode. this configuration has one dynamic reconfiguration controller to control five channels. this scenario covers the case stamping five instantiations of one channel alt2gxb instance configuration. one channel alt2gxb configuration: set the what is the number of channels? option to 1 along with other options in the alt2gxb megawizard. enable the analog controls option under the dynamic reconfiguration settings (to dynamically change equalization values, also enable the enable equalizer settings option). the output signal reconfig_fromgxb is transceiver-block based so the number of bits for this in stance is one since the number of channels is one. the input signal reconfig_togxb is a fixed width of three bits. set the option what is the star ting channel number ? to 0 . instantiating five times using the above 1-channel alt2gxb: instantiate the alt2gxb.v file or the symbol file five times. note that after instantiat ing five times, add the starting channel number parameter to the symbol file. change the parameter option to 4 , 8 , 12 , and 16 for the instances 2, 3, 4, and 5 just created. if the instantiations are done in a verilog file, use the following command to force the parameter option to 4 , 8 , 12 , and 16 for the instances 2, 3, 4, and 5: defparam inst2. starting_channel_number= 4; defparam inst3. starting_channel_number= 8; dynamic reconfiguratio n controller instance: launch the alt2gxb_reconfig megawizard. set the what is the number of ch annels controlled by the controller? option to 20 so that five interface signals are enabled ( reconfig_fromgxb[4:0] ). select the necessary analog contro l signals to write in and read out from the v od , pre-emphasis, equalization, and dc gain options.
3?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration alt2gxb instances and alt2 gxb_reconfig instance connections: connect the reconfig_fromgxb signal from the alt2gxb instance to the same signal in the alt2gxb_reconfig instance. connect the reconfig_togxb signal from the alt2gxb_reconfig instance to th e same signal in the alt2gxb instance. channel and pma controls reconfiguration the write transaction of the controller is initiated on the assertion of the write_all signal. in pma reconfiguration mode, the write_all signal writes the current state of all the selected input signals into the alt2gxb instance channels. the write transaction involves the following sequence: 1. read the control analog registers (read before write). 2. write the current state of input si gnals of all channels into control registers. 3. update the output control signals (optional read control ports if any of the read control ports are enabled). if you select the read control port, the data_valid signal is enabled. reading and updating all the output control signals is part of the write transaction. therefore, the data_valid signal is asserted only when the write transaction is finished ( busy signal is low) and all the output control ports are updated with the ne w data. when a write transaction is initiated and a set of values for the selected analog settings is being written, you cannot change the input va lues of the control ports until the transaction is completed. otherwise, the results are unpredictable. the dynamic reconfiguration controller asserts the busy signal when you initiate a read or write transaction an d is deasserted after the operation is complete. 1 simultaneous write and read transactions are not allowed. figure 3?5 illustrates a write transaction for a transmit analog setting v od ( tx_vod ). the waveform shows a typical write transaction initiated by the pulsing of the write_all signal and also shows the behavior of the status signals busy and data_valid . set the reconfig_mode_sel signal to 000 to reconfigure the analog sett ings of a transceiver channel.
altera corporation 3?21 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?5. write transaction waveform - v od , analog settings reconfiguration in channel reconfiguration, only a write transaction can occur?no read transactions are allowed. set the reconfig_mode_sel control signal to 001 to use the channel reconfiguration fe ature. when you use this feature, the dynamic reconfiguration controller requires that you provide a 16-bit word ( reconfig_data[15:0] ) on every write transaction, using the write_all signal. this 16-bit word is part of a memory initialization file ( .mif , also known as mif) that is gene rated by the quartus ii software when an alt2gxb instance is compiled. refer to ?channel reconfiguration? on page 3?30 for more information about the mif. the dynamic reconfiguration controller ignores a new 16-bit word if the previously initiated write transaction is not complete. as explained above, an on-going or active writ e transaction is signified by the busy signal. you can only input a new word of 16-bits when the busy signal is de-asserted. to properly initiate and complete a write transaction during channel reconfiguration, the dynamic reco nfiguration controller provides additional signals. these signals are listed below and are classified into control and status signals. tx _vodctrl[2:0] reconfig _ clk busy read data _ valid write _ all 3'b001 3'b000
3?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration the following are control signals (other than the write_all and reconfig_mode_sel signals): logical_channel_address[7:0] : use this control signal to set the logical channel number of the channel that is being reconfigured by the dynamic reconfiguration cont roller. this signal gets enabled when the number of channels controlled by the dynamic reconfiguration controller is more than one. since the channel reconfiguration is done on a per-ch annel basis, you have to use this signal and provide the necessary logical channel address to write the mif words so that a successful channel reconfiguration is achieved for that channel. reset_reconfig_address : use this optional control signal to reset the reconfig_address_out value to 0 . this reset control signal is only applicable in channel reconfiguration. the following are status signals (other than the busy signal): reconfig_address_en : this is an optional output signal. the alt2gxb_reconfig asserts this si gnal to indicate the change in value on the reconfig_address_out port. this signal only gets asserted after the dynamic reco nfiguration controller completes writing the 16-bit data. reconfig_address_out[4:0] : this is an option al output signal. it provides the address value that you can use to read the appropriate word from the mif. use the value in this port in combination with the reconfig_address_en signal to decide when to initiate a new write transaction. channel_reconfig_done : this signal is available when you select the channel reconfiguration option in the dynamic reconfiguration controller. this port indicates that the alt2gxb_reconfig megafunction has finished writin g all the words of a mif in a sequence. this signal is very useful for user logic to implement reset recommendations during and after dynamic reconfiguration. refer to ?reset recommendations? on page 3?66 for more information about using this signal.
altera corporation 3?23 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration error : the alt2gxb_reconfig provides this status signal when you select the enable illegal mode checking option or the enable self recovery option in the error checks/data rate switch tab. the conditions under which the error signal is asserted, when the above two options are enabled, are: enable illegal mode checking option?when you select this option, the dynamic reconfigurat ion controller checks whether an attempted operation falls under one of the seven conditions listed below. the dynamic reconfiguration controller detects these conditions within two reconfig_clk cycles, de-asserts the busy signal, and asserts the error signal for two reconfig_clk cycles. 1. pma controls - read operation: ? none of the analog pma read output ports ( rx_eqctrl_out , rx_eqdcgain_out , tx_vodctrl_out , tx_preemp_0t_out , tx_preemp_1t_out , and tx_preemp_2t_out ) are selected in the alt2gxb_reconfig megawizard ? reconfig_mode_sel is set to 0 ? read signal is asserted 2. pma controls - write operation: ? none of the analog pma control write input ports ( rx_eqctrl , rx_eqdcgain , tx_vodctrl , tx_preemp_0t , tx_preemp_1t , and tx_preemp_2t ) are selected ? reconfig_mode_sel is set to 0 ? write_all signal is asserted 3. channel and/or tx pll reco nfiguration - read operation: ? reconfig_mode_sel input port is set to 1 , 4 , 5 , or 6 ? read signal is asserted 4. data rate switch - write operation with unsupported value: ? the rate_switch_ctrl[1:0] input port is set to 11 ? reconfig_mode_sel input port is set to 4 (if other reconfiguration mode options are selected in the reconfiguration settings tab) ? write_all is asserted
3?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 5. data rate switch - write operation without input port: ? the rate_switch_ctrl input port is not used ? reconfig_mode_sel port is set to 4 (if other reconfiguration mode options are selected in the reconfiguration settings tab) ? write_all is asserted 6. data rate switch - read op eration without output port: ? the rate_switch_out output port is not used ? reconfig_mode_sel port is set to 4 (if other reconfiguration mode options are selected in the reconfiguration settings tab) ? read is asserted 7. adaptive equalization - read operation: ? reconfig_mode_sel input port is set to 7 , 8 , 9 , or 10 ? read signal is asserted enable self recovery option?when this opti on is selected, the dynamic reconfiguration contro ller waits for a pre-defined number of reconfig_clk cycles based on the operation selected. if the busy signal does not go low within the pre-defined number of clock cycles, it asserts the error signal for two reconfig_clk cycles. example for using logical channel address to perform channel reconfiguration the dynamic reconfiguration controller provides an output port called logical_channel_address . this port is required for the channel reconfiguration and channel and cmu pll reconfiguration features to specify the logical transceiver channe l that is to be reconfigured. the logical_channel_address value depends on how the alt2gxb is instantiated in the design. in this sect ion, the different ways of setting up the alt2gxb instantiation and the corresponding logical_channel_address values for these transceiver channels are shown.
altera corporation 3?25 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration example 1: consider a design example in which the alt2gxb instantiation has six transceiver channels: in the alt2gxb megawizard (in the reconfig tab) set the starting channel number option to 0 . in the alt2gxb_reconfig megawizard, set the number of channels controlled by the reconfig controller option to 6 . the logical_channel_address value for channel 0 is 0 (channel 0 is the one that is assigned to tx_dataout[0] ). similarly, the logical_channel_address values for channels 1 through 5 are 1 through 5 , respectively. example 2: consider a design example with alt2gxb instance an that has one transceiver channel (assume the instantiation name is instantiation0 ). the starting channel number option value for this channel is 0 . if you use this instantiation to create five addi tional transceiver channels, you will need the following defparam parameter settings (for verilog designs) to change the starting channel number for the stamped instantiations: defparam . starting_channel_number = 4 defparam . starting_channel_number = 8 defparam . starting_channel_number = 12 defparam . starting_channel_number = 16 defparam . starting_channel_number = 20 therefore, the starting channel number option values for channels 0 through 5 are 0 , 4 , 8 , 12 , 16 , and 20 , respectively. in the alt2gxb_reconfig megawizard, set the number of channels controlled by the reconfig controller option to 24 . by setting this option, you get the reconfig_fromgxb port with a bus width of 6. connect the reconfig_fromgxb(0 to 5) port of the alt2gxb_reconfig instantiation to the reconfig_fromgxb ports of transceiver channels 0 to 5, respectively (as shown in figure 3?6 ). the logical_channel_address values for transceiver channels 0 through 5 ( tx_dataout[0] to tx_dataout[5] ) are 0 , 4 , 8 , 12 , 16 , and 20 , respectively.
3?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 1 the logical_channel_address value depends on the starting channel number option value that you set in the alt2gxb megawizard for the transceiver channel. however, it does not depend on the physical placements of the transceiver channel. for example, yo u can physically assign tx_dataout[1] ( tx_dataout of instantiation1) in the same transceiver block or in the other transceiver block. for both these assignments, the logical_channel_address value is 4 for instantiation1. figure 3?6. multiple stampings of a single channel alt2gxb instantiation alt2gxb instantiations alt2gxb_reconfig controller reconfig_from gxb[5:0] reconfig_ togxb[2:0] reconfig_fromgxb[0] reconfig_fromgxb[1] reconfig_fromgxb[4] channel 0 (logical channel number = 0) channel 1 (logical channel number = 4) channel 4 (logical channel number = 16) reconfig_fromgxb[2] channel 2 (logical channel number = 8) reconfig_fromgxb[3] channel 3 (logical channel number = 12) reconfig_fromgxb[5] channel 5 (logical channel number = 20)
altera corporation 3?27 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration example 3: consider a design example with alt2gxb instance an that has two transceiver channels (ass ume the example name is instantiation0 ). the starting channel number option for this instance is set to 0 . if you want to create six transceiver channels, stam p this instance th ree times. modify the starting channel number option for the other two instances to 4 and 8 using the defparam setting (for verilog design): defparam . starting_channel_number = 4 defparam . starting_channel_number = 8 in the alt2gxb_reconfig megawizard, set the number of channels controlled by the reconfig controller option to 12. connect the reconfig_fromgxb(0 to 2) port of the alt2gxb_reconfig instantiation to the reconfig_fromgxb ports of instantiation0 to instanti ation2, respectively (as shown in figure 3?7 ). in this case, the logical_channel_address values for transceiver channels 0 and 1 ( tx_dataout[0] and tx_dataout[1] ) are 0 and 1 . similarly, the logical_channel_address values for channels 2 to 5 are 4 , 5 , 8 , and 9 , respectively. (the starting channel number option value for instantiation1 is 4 . therefore, the logical_channel_address value for channel 2 is 4 ).
3?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?7. multiple stampings of a two channel alt2gxb instantiation figure 3?8 illustrates the write transaction for channel reconfiguration. figure 3?8. write transacti on general waveform ? channel reconfiguration alt2gxb instantiations alt2gxb_reconfig controller reconfig_from gxb[2:0] reconfig_ togxb[2:0] reconfig_fromgxb[0] reconfig_fromgxb[1] reconfig_fromgxb[2] channel 0 (logical channel number = 0) channel 1 (logical channel number = 1) channel 2 (logical channel number = 4) channel 3 (logical channel number = 5) channel 4 (logical channel number = 8) channel 5 (logical channel number = 9) reconfig _ clk reconfig _ address_en write _ all don't care 1 st 16- bits reconfig_data[15:0] _ 2 nd 16-bits busy addr 0 reconfig _ address _ out[4:0] addr 1
altera corporation 3?29 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration a write is allowed in dynamic transm it rate switch mode. the control signal rate_switch_ctrl[1:0] determines which division factor is written into the alt2gxb transmitter ( figure 3?9 ). figure 3?9. write transaction general waveform ? dynamic transmit rate switch reconfiguration (division 2) to initiate a read transaction, assert the read signal. the data on the output control ports is not valid until the data_valid signal is high. the data_valid signal goes high when the entire selected output signals have valid read values. both read and write transactions are based on the reconfig_clk and are edge triggered. assert the write_all and read signal for one reconfig_clk cycle. figure 3?10. read transaction waveform ? v od , analog settings reconfiguration rate _ switch _ ctrl [ 1 .. 0 ] reconfig _ clk busy read data _ valid write _ all 2'b01 xxx tx _ vodctrl _out [ 2 :0 ] reconfig _ clk data _ valid read invalid output 3'b000 busy
3?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?11. read transaction wavefo rm ? dynamic tr ansmit rate switch rec onfiguration (division 2) in addition to the pma reconfiguratio n, the quartus ii software (version 6.1 and later) dynamic reconfiguration controller enables these two features: channel reconfiguration dynamic transmit rate switch the following two sections explain these features. channel reconfiguration introduction channel reconfiguration provides you the flexibility to reconfigure a channel by writing a new set of legal register bits into the alt2gxb by the dynamic reconfiguratio n controller. with this feature you can either reconfigure the data rate of a channel or functional mode (including basic mode with the custom mode enumerat ion [cme] features), or a mix of data rates and functional modes. the cme features are additional transceiver features introduced in basic functional mode. some of the cme features are controlled by pld signals that allow you to dynamically control certai n features in real time. however, some of the cme features are static and set through the quartus ii alt2gxb configuration. 1 channel reconfiguration only affects the channel involved in the reconfiguration; other channels are not affected. rate _ switch _ out [ 1 .. 0] reconfig _clk data _ valid read invalid output 2'b01 busy
altera corporation 3?31 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration channel reconfiguration can be classi fied into two major areas?data rate reconfiguration and function al mode reconfiguration: data rate reconfiguration?data rate reconfiguration involves switching the data rate of a channel by switching between two tx plls and reconfiguring the rx plls. the two tx plls can be set to different base rates. with data rate reconfiguration, you can also switch the data rate using local cl ock dividers present in the transmit and receive sides of every transcei ver channel. you can reconfigure these clock dividers to 1, 2, and 4. when you reconfigure the clock dividers, ensure that the functional mode supports the minimum and maximum data rate. functional mode reconfiguration?this can be: switched between one protocol functional mode to another protocol functional mode switched between a protocol functional mode to a basic functional mode switched between a basic mode to another basic mode there is no limit to the number of mode switches in channel reconfiguration, assuming transceiver and core clocking supports the transition. channel reconfiguration supports the following configurations of the physical transceiver channel: duplex channels (tx and rx) tx only rx only independent tx/independent rx in one physical channel 1 for the following discussion, th e reference of a channel is a duplex channel, unless mentioned as tx-only or rx-only. design flow the quartus ii software provides a design flow called user memory initialization file ( .mif , also known as mif) flow to use the channel reconfiguration feature. this design flow involves writing the entire contents of the mif for a channel. th e quartus ii software generates the mifs when you provide appropriate project settings (d iscussed below) and then compile an alt2gxb instance. each mif has the settings for a full-duplex transceiver channel. the settings are all legal register settings of the transceiver channel. the al t2gxb_reconfig instance reads the value in the mif using the reconfig_data[15..0] port for every write transaction.
3?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration each mif contains twenty-eight 16-bi t words if you enable the settings shown below. 1 for the channel and cmu pll reconfiguration feature, the quartus ii software provides new settings that generates a mif file with 38 words. this is discussed in ?quartus ii settings and requirements? on page 3?111 . the quartus ii software creates the mif under the /reconfig_mif folder. the file name is based on the design name and the rx_ and tx_ pin names. for example: reconfig_datarate_1gto 2g_pin_af1_pin_af4.mif (the quartus ii software automatically generates fi le name).you can change the mif name. one design can have multiple mifs (no limit) an d one mif can be used to reconfigure multiple channels. these mifs can be stored in on-chip or off-chip memory. 1 if you do not specify pins for the tx_dataout and rx_datain for the transceiver channel, th e quartus ii software selects a channel and generates a mif for that channel. however, the mif can still be used for any transceiver channel. mif generation in quartus ii software the mif is not generated by default in a quartus ii compilation. there are three steps to enable mif generati on. once the quartus ii software settings are enabled, a mif is gene rated after you compile an alt2gxb instance. the three steps to enable mif generation are shown below.
altera corporation 3?33 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 1. on the assignments menu, select settings ( figure 3?12 ). figure 3?12. mif generation, step 1 (settings option)
3?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 2. select fitter settings , then choose more settings ( figure 3?13 ). figure 3?13. mif generation, step 2 (fitter settings)
altera corporation 3?35 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 3. in the option box of the more fitter settings page, set the generate stratix ii gx gxb reconfig mif option to on c ( figure 3?14 ). figure 3?14. mif generation, step 3 (enable settings) the mif is generated in the assemble r stage of the compilation process. however, for any change in the design or the above settings, the quartus ii software runs through the fitter stage before starting the assembler stage. as previously discussed, the channel reconfiguration can be a data rate reconfiguration using two tx plls and local clock dividers, or a functional mode reconfiguration, or both. to reconfigure a channel successfully, select the appropriate options in the alt2gxb megawizard (discussed in the sections below).
3?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration alt2gxb configuration related to channel re configuration you must setup the following two syst em design aspects in a alt2gxb megawizard instance: transceiver and core clocking pld data path interface transceiver and core clocking you must set up the core clocking and transceiver clocking options as part of channel reconfiguration for function al mode switchover or data rate transition. transceiver cl ocking covers all the cl ock options you need to set up: two tx plls for data rates and functional modes input reference clocks fo r transmit and receive internal clock mux reference index setups core clocking covers the pld interface clocking. pld interface clocking is related to the parallel transmit and receive clocks ( tx_clkout and rx_clkout ). these clocks are used to pa rallel transmit data into and parallel receive data out of the transcei ver. core clocking is needed in any channel reconfiguration. core cl ock assignments (clock grouping assignment and 0 ppm assignments) will override the core clocking set in the alt2gxb instance. the details related to transceiver and core clocking are discussed in the following section. transceiver and core clocking are classified as: data rate switch using local clock block dividers data rate switch based on clock frequencies of two plls in the transceiver block data rate switch using local clock block dividers if you intend to switch the data rate in multiples of 1, 2, and 4 of the base data rate, use the local clock dividers. local clock dividers further divide the tx pll base rate and are present in transmit and receive block of every transceiver channel (refer to figure 3?15 ).
altera corporation 3?37 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?15. transmit local clock divider block transmit local clock dividers are plac ed after the cmu plls and thus the tx plls are not affected during a data rate switch using local clock dividers. receive local clock dividers are placed before the rx pll (cdr). thus the rx pll is affected every time the data rate switch using local clock dividers occurs. the quartus ii software data rate divisi on factor chooses a combination of local clock dividers and feedback dividers present in the cdr that yields the best performance (refer to figure 3?16 ). figure 3?16. receive local clock divider block to configure the local divider using the same tx pll base setting, use the following steps: 1. set the base setting on the cmu pll (use the fastest data rate that is intended to be reconfigured to). 2. set the local clock divider setting (use the effective data rate for that configuration). 3. enable either the channel internals or channel interface option (refer to ?channel internals? on page 3?53 and ?channel interface? on page 3?53 for more information). /4,/5, /8,/10 high speed clock to tx slow speed cloc k to tx tx local clk div block high speed clock from txpll0 high speed clock from txpll1 /1,2,4 /n slow speed cloc k to rx rx local clk div block /1,2,4 /n cdr/ clock dividers rx_cru_clk rx_cru_clk_alt
3?38 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 4. setup core clocking (refer to ?transmitter core clocking? on page 3?45 and ?receiver core clocking? on page 3?48 for more information). 5. finish the alt2 gxb configuration. 6. repeat the previous 5 steps with the same tx pll base setting and different local clock divider settings. 7. group core clocking. 8. lock down the pin assignments for the clocks and generate the mifs for above instances. steps 1 and 2 are the only steps related to the local clock divider settings. step 4 is a mandatory step and is an im portant part of clocking in every channel reconfiguration (refer to figure 3?17 ). figure 3?17. alt2gxb instance?tx /rx local clock divider
altera corporation 3?39 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration data rate switch based on clock frequencies of two plls if your application requires the tr ansceiver to switch between multiple data rates, you can use channel reconfiguration to switch between the two tx plls in the tran sceiver block. th e following sections explain how to setup two plls and achieve multiple data rates using channel reconfiguration: 1. set the primary pll (mode1) data rate setting. 2. set the local clock divider (if needed). 3. enable the channel internals option in the dynamic reconfiguration section of the alt2gxb (refer to ?channel internals? on page 3?53 for more information). 4. in channel internals option, enable the use alternate reference clock (mode 2) option. set all the parameters related to alternate pll protocols, data rates, bandwidth, and clock frequency. 5. set the what is the logical reference index? option (refer to the logical reference index). 6. set the core clocking op tions?transmit and receive this is a mandatory step for ev ery channel reconfiguration that uses tx_clkout and rx_clkout (refer to ?transmitter core clocking? on page 3?45 ). 7. if there are no other settings to configure in the alt2gxb, select finish the alt2gxb instantiation . 8. lock down the input reference cl ocks pin placemen ts (refer to pin assignments). 9. compile and generate a mif for mode1 as primary and mode2 as alternate. 10. similarly, generate a mif for mode2 as primary and mode1 as alternate by going through steps 1 through 9 again (refer to ?example 1? on page 3?13 ).
3?40 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?18 illustrates steps 1 and 2. figure 3?18. local clock divider sett ings in the alt2gxb megawizard figure 3?19 illustrates steps 3 and 4 using basic mode at 2.5 gbps. in basic mode, the alternate pll setup is the most flexible, you can choose and set from the supported bandwidth op tions and input reference clock frequencies. for example, if the alternate pll happens to be a protocol functional mode like pci-e or gige , the alternate pll related options will be automatically populated by the quartus ii software. for more information about the channel internal option, refer to ?channel interface? on page 3?53 .
altera corporation 3?41 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?19. channel reconfiguration se ttings for the alt2gxb megafunction 1 to enable dynamic reconfiguration of a transceiver channel, select either the channel internals or channel interface options. selecting these fields creates the reconfig_fromgxb and reconfig_togxb ports in the alt2gxb instance. the alt2gxb_reconfig uses thes e ports to configure the transceiver channel. in step 5 , selecting the what is the local reference clock index? option controls the: mux that selects the high-speed clocks from the two tx plls mux that selects one of the two input reference clocks ( rx_cruclk or rx_cruclk_alt) on the receive side for example, consider a system switching from gige to sonet/sdh and vice versa. since both protocol s (gige with 125-mhz input reference clock and sonet/sdh oc48 with a 77.76-mhz input reference clock) cannot be achieved by one tx pll, yo u need a two tx pll setup. as part of the two tx pll setup, you will set the logical reference index. to generate a mif for the gige protoc ol, set the gige as the main configuration in the alt2gxb inst ance and sonet/sdh mode as the
3?42 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration alternate protocol. this means that gi ge is achieved with the main pll and the alternate pll/input reference clock configuration is sonet/sdh oc48. assume that you set the logical reference index option value to 0 (in the reconfig tab). by setting the logical reference index to 0 , you provide the quartus ii software with the following information. selection values for the two muxs mentioned above. the signal name muxselect* is an assumed name. logical reference index = alternat e input reference clock input leg muxselect* = ~(logical reference index) in this case, since the logical reference index is set to 0 (represents the sonet/sdh), the tx pll based on gige is routed to input1 of the clock mux, and the alternate pll configur ed for sonet/sdh is connected to input0 of the clock mux. in the gige mif, the clock mux select value is set to 1 to choose the clock from the gige tx pll. figures 3?20 and 3?21 show the clock mux connections for gige and sonet/sdh, respectively. figure 3?20. tx pll for gige and son et/sdh oc48 mode reconfiguration cmu block tx channel clocking block tx channel rx channel 0 1 tx high speed clocks tx pll 1 (sonet) tx pll 2 (gige) pll_inclk_alt (77.76mhz) pll_inclk (125 mhz) 625mhz 1244.16 mhz rx_cruclk (125 mhz) rx_cruclk_alt (77.76 mhz) muxselect =1 muxselect =1 0 1 clock to cdr local refclk
altera corporation 3?43 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration to generate a mif for the sonet/sdh protocol, set the sonet/sdh as the main configuration in the al t2gxb instance and gige as the alternate protocol. this means so net/sdh oc48 is achieved by the main pll and the alternate pll/input reference clock configuration is gige. set the logical reference index option to 1 (since you have set the logical reference index to 0 for the gige instance). in the sonet/sdh mif, the cloc k mux select value is set to 0 to choose the clock from the sonet/sdh tx pll figure 3?21. mux setting - gige and sonet/sdh mode, logical reference clock index = 1 when two modes are configured to switch from one to another using two tx plls, you have to carefully select the logical reference index. in this case, make sure the logical reference index that is set in one mif is a complement in the second mif. steps 6 is discussed in ?core clocking? on page 3?45 . cmu block tx channel clocking block tx channel rx channel 0 1 tx high speed clocks tx pll 1 (sonet) tx pll 2 (gige) pll_inclk (77.76mhz) pll_inclk_alt (125 mhz) 625 mhz 1244.16 mhz rx_cruclk_alt (125 mhz) rx_cruclk (77.76 mhz) muxselect=0 muxselect =0 0 1 clock to cdr local refclk
3?44 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration channel reconfiguration supported modes channel reconfiguration is supported in the following modes: duplex channels (tx and rx) tx only rx only independent tx/independent rx in one physical channel in the tx-only configuration, there is only one transmitter in a physical transceiver channel. the mif for the tx-only file has the bits of the unused receiver, but these bits are disabled. the rx-only configuration is the same as the tx-only configuration except it pertains to the receiver. 1 channel reconfiguration from a tx-only mode to an rx-only mode and vice versa is not allowed. the quartus ii software allows inde pendent tx-only configuration with another independent rx-only configurat ion in one physical channel. to place an independent tx config uration and an independent rx configuration in one physical channel, follow the steps below: perform the pin assignments accordingly instruct the quartus ii software to merge or group the tx and rx register settings into one mif there are constraints with the in dependent tx-only and independent rx-only configurations. both transmi tter and receiver have to go through a reset sequence, even if the tx or rx is reconfigured. to merge or group the independent tx-only and independ ent rx-only configurations, place the rx and tx pins into one physical channel. you can accomplish this with the appropriate pin assignment and generation of a mif through the quartus ii assignment editor by setting the stratix ii gxb reconfig group setting option to on in the quartus assignment editor ( figure 3?22 ).
altera corporation 3?45 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?22. quartus ii assignment edi tor ? tx-only/rx-only merge option core clocking core clocking configuration setup is a mandatory step in every channel reconfiguration. core clocking is the write and read clock options for the transmit phase comp fifo and the receive phase comp fifo, respectively. core clocking can be further classified to: transmitter core clocking receiver core clocking transmitter core clocking transmitter core clocking is the write clocking options for the transmit phase comp fifo. the transmitter core clocking is used to write the parallel data into the transmit phase comp fifo from the pld interface.
3?46 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration the possible transmit core clock options are: tx_clkout (the quartus ii software automatically routes to pld and back into transmitter phase comp fifo) tx_coreclk (user-supplied input clock) dynamic reconfiguration allows b oth transmit clock options. the alt2gxb megawizard provides two options only for the tx_clkout settings. when you select the tx_clkout options, ensure that the selected tx_clkout option is compatible for all the intended reconfiguration modes for the transceiver channel. the tx_coreclk selection and clock grouping assignments (assignment editor) overrides the tx_clkout settings set in the alt2gxb megawizard. figure 3?23 shows the two options in tr ansmit core clocking for tx_clkout routing. figure 3?23. alt2gxb megawizard reconfigura tion ? transmit core clocking options
altera corporation 3?47 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration option 1: share a single transmitter core clock between transmitters this option enables the quartus ii software to select channel 0 tx_clkout of a transceiver block and routes it to itself and three other channels. this is typically used when all four transmit channels are of the same mode (and also the same data rate) and switch to another mode. for example, figure 3?24 shows a setup which has all the transmits configured at 3 gbps and in the same functional mode. with the dynamic reconfiguration controller and using the channel reconfiguration feature, all four channels switch to 1.5 gbps an d vice versa. option 1 is applicable in this case and saves clock resources. figure 3?24. option 1: channel reconfi guration?transmit core clocking option 2: use respective chan nel transmitter core clocks this option enables the quartus ii software to select the individual channel tx_clkout signals and route them back through pld write clock resources to the tx phase comp fifo. this type of core clocking configuration is needed when indivi dual transmit channels can switch modes (basically, each channel switches to a different mode using channel reconfiguration). cmu pll0 tx1 (3 gbps) rx1 tx0 (3 gbps) rx0 tx2 (3 gbps) rx2 tx3 (3 gbps) rx3 cmu pll1
3?48 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?24 shows a setup with all the tran smitters configured at 3 gbps and each one at a unique functional mode. each channel can be switched to a different functional mode usin g the channel reconfiguration feature of the dynamic reconfiguration contro ller. in this ca se, option 2 is applicable. figure 3?25. option 2: channel reconfi guration?transmit core clocking receiver core clocking receiver core clocking is the read clocking options for the receive phase comp fifo. the receiver core clocking is used to read the parallel data into the receive phase comp fifo fr om the pld interface. the possible transmit core clock options are: rx_clkout (the quartus ii software automatically routes to pld and back into phase comp) rx_coreclk (user-supplied input clock) dynamic reconfiguration supports both receive clock options. the alt2gxb megawizard only asks for the rx_clkout settings. the quartus ii software automatically rout es the clock paths based on a given mode setup. you must verify that cloc k routing is compatible with each cmu pll0 tx1 (3 gbps) rx1 tx0 (3 gbps) rx0 tx2 (3 gbps) rx2 tx3 (3 gbps) rx3 cmu pll1
altera corporation 3?49 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration mode. the rx_coreclk selection and its grouping will override the rx_clkout settings set in the alt2gxb megawizard. there are three options in the receiver core clocking for rx_clkout routing. figure 3?26. alt2gxb megawizard reconfigura tion ? receive core clocking options option 1: share a single transmitte r core clock between receivers this option enables the quartus ii software to select channel 0 tx_clkout of a transceiver block and route it to all four receiver channels. this option is typically se t when a transceiver block (all four channels) is in basic or protocol mo de, with rate matching, switches to another basic or protocol mode with rate matching. figure 3?27 shows a setup with all four ch annels configured to a basic 2 gbps mode with rate matching, and then switches to a basic 3.125 gbps mode with rate matching. in this case, option 1 is applicable.
3?50 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?27. option 1: channel reconfi guration?receive core clocking option 2: use respective chan nel transmitter core clocks this option enables the quartus ii software to select the individual channel tx_clkout signal and route it to the same channel?s receiver pld interface clock signal. typically, this option is used when the individual channels in a transceive r block have rate matching with different data rates switched to another basic or protocol mode with rate matching. figure 3?28 illustrates a setup which has to switch between the following modes: tx1/rx1: basic 1 gbps with rate matching to basic 2 gbps with rate matching tx3/rx3: basic 4 gbps with rate matching to basic 1 gbps with rate matching tx0/rx0: basic 3.125 gbps with ra te matching to 1 gbps with rate matching and vice versa cmu pll0 tx1 rx1 tx0 rx0 tx2 rx2 tx3 rx3 (all 4 channels configured to basic 2g with rm and set up to switch to basic 3.125 with rm) cmu pll1
altera corporation 3?51 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?28. option 2: separate transmitter core clocks?receive core clocking option 3: use respective chan nel receiver core clocks this option enables the quartus ii software to select the individual channel rx_clkout signal and route it to the same channel?s receiver. typically, this option is used when a channel is set up to switch from a basic or protocol mode with or withou t rate matching to another basic or protocol mode with or without rate matching. figure 3?29 illustrates a setup which intends to switch between the following modes: tx1/rx1: gige to sonet/sdh oc48 tx2/rx2: basic 2.5 gbps no rate matching to basic 1.244 g bps no rate matching in this case, option 3 is applicable. transceiver block tx1 rx1 tx0 tx2 tx3 rx0 rx2 rx3
3?52 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?29. option 3: rxclk_out?receive core clocking pld data path interface for successful channel reconfiguration, you need to set up the following two system design aspects in the alt2gxb megawizard: transceiver and core clocking pld data path interface transceiver and core clocking has been explained in detail in the preceding sections. this section discusses the pld data path interface. the pld data path interface need s to be set up when dynamic reconfiguration involves the following: mode switches involving pld data width changes mode switches involving enabling and disabling of pcs blocks or features (for example, cme feat ures) in a transceiver channel in the alt2gxb instance?s reconfiguration section, the pld data path interface can be set up through two subsections: channel internals channel interface tx1 rx1 tx0 rx0 tx2 rx2 tx3 rx3 transceiver block
altera corporation 3?53 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration channel internals you should enable the channel internals option if the modes that are switched to and from involve the following: static pcs features (including cme features) are enabled or disabled. a data rate that needs another tx pll to be set up (options related to alternate txpll need to be configured; for example, the use alternate reference clock option and other sub-options). as long as the pld data path widt h is not changed and no additional control and status signals are needed. in this case, you only need to enable the channel internals option. to reconfigure between two modes that differ only in the static features, generate the following mifs: generate a mif with the channel internals option enabled and set the appropriate pcs and analog features in the alt2gxb megafunction. generate a mif with the channel internals option enabled but with a different set of pcs features (same analog features) configured in the alt2gxb megafunction. in this case, the use alternate reference clock option is not enabled, since the reconfiguration did not involve any changes to the data rate that would require another tx pll. you can use the channel internals option in conjunction with the channel interface option. channel interface the channel interface option is enabled if th e mode switches involve: pld data path width changes pld control and status flag changes the channel interface option involves the following: a new port called tx_datainfull[43:0] is enabled to the pld interface port list on the transmit side (44-bits wide) a new port called rx_dataoutfull[63:0] is enabled to the pld interface port list on the receive side (64-bits wide) enabling the channel interface pr ovides an option pane in the alt2gxb megafunction where you can select the necessary ports for control and status signals that are needed for each of their channel reconfiguration.
3?54 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration the signals tx_datainfull[43:0] and rx_dataoutfull[63:0] replace the existing tx_datain and rx_dataout ports of a channel. the quartus ii fitter and mapper imposes fewer legal checks related to the connectivity of the signals in tx_datainfull , rx_dataoutfull , and other optional signals. for example, the pipe mode signals pipestatus and powerdn can be potentially enabled through the alt2gxb megawizard (enabled through the reconfig2 tab); the quartus ii software will not restrict this selection. in this case, the software assumes you are planning to switch to and from a pci-e mode. figures 3?30 and 3?31 show the megawizard pages you use to select the channel internals and channel interface options. if the channel interface option is enabled, th e following signals are disabled: receiver pld interface: rx_dataout[39:0] rx_syncstatus[3:0] rx_patterndetect[3:0] rx_a1a2sizeout[3:0] rx_ctrldetect[3:0] rx_errdetect[3:0] rx_disperr[3:0] transmitter pld interface: tx_datain[39..0] tx_ctrlenable[3:0] tx_forcedisp[3:0] tx_dispval[3:0]
altera corporation 3?55 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?30. alt2gxb reconfiguration ? channel interface enabled
3?56 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?31. alt2gxb reconfiguration ? control/ status signals, channel interface enabled signal descriptions for tx_datainfull[43:0] and rx_dataoutfull[63:0] are shown in tables 3?3 and 3?4 . table 3?3. tx_datainfull[43:0] pld data signal descriptions (part 1 of 3) pld interface description transmit signal description (based on stratix ii gx supported pld interface widths) 8-bit pld interface tx_datainfull[7:0] : 8-bit data ( tx_datain ) the following signals are used only in 8b/10b modes: tx_datainfull[8] : control bit ( tx_ctrlenable ) tx_datainfull[9] : force disparity enable for tx_datainfull[7:0] (non pipe mode). transmitter force disparity compliance (pipe) ( tx_forcedisp ) in all modes except pipe. for pipe mode, ( tx_forcedispcompliance ) is used. tx_datainfull[10] : forced disparity value for tx_datainfull[7:0] ( tx_dispval ) 10-bit pld interface tx_datainfull[9:0] : 10-bit data ( tx_datain )
altera corporation 3?57 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 16-bit pld interface with pcs-pma set to 16/20 bits two 8-bit data ( tx_datain ) tx_datainfull[7:0 ] - tx_datain (lsbyte) and tx_datainfull[18:11] - tx_datain (msbyte ) the following signals are used only in 8b/10b modes: two control bits ( tx_ctrlenable ) tx_datainfull[8] - tx_ctrlenable (lsb) and tx_datainfull[19] - tx_ctrlenable (msb) force disparity enable tx_datainfull[9] - tx_forcedisp (lsb) and tx_datainfull[20] - tx_forcedisp (msb) force disparity value tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[21] - tx_dispval (msb) 16-bit pld interface with pcs-pma set to 8/10 bits two 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[29:22] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: two control bits ( tx_ctrlenable ) tx_datainfull[8] - tx_ctrlenable (lsb) and tx_datainfull[30] - tx_ctrlenable (msb) force disparity enable for non-pipe: tx_datainfull[9] - tx_forcedisp (lsb) and tx_datainfull[31] - tx_forcedisp (msb) for pipe: tx_datainfull[9] - tx_forcedispcompliance (lsb) and tx_datainfull[31] - tx_forcedispcompliance (msb) force disparity value tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[32] - tx_dispval (msb) 20-bit pld interface with pcs-pma set to 20 bits two 10-bit data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[20:11] - tx_datain (msbyte) 20-bit pld interface with pcs-pma set to 10 bits two 10-bit data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[31:22] - tx_datain (msbyte) table 3?3. tx_datainfull[43:0] pld data signal descriptions (part 2 of 3) pld interface description transmit signal description (based on stratix ii gx supported pld interface widths)
3?58 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 32-bit pld interface with pcs-pma set to 16/20 bits four 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[18:11] tx_datainfull[29:22] tx_datainfull[40:33] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: four control bits ( tx_ctrlenable ) tx_datainfull[8] - tx_ctrlenable (lsb) and tx_datainfull[19] tx_datainfull[30] tx_datainfull[41] - tx_ctrlenable (msb) force disparity enable ( tx_forcedisp ) tx_datainfull[9] - tx_forcedisp (lsb) and tx_datainfull[20] tx_datainfull[31] tx_datainfull[42] - tx_forcedisp (msb) force disparity value ( tx_dispval ) tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[21] tx_datainfull[32] tx_datainfull[43] - tx_dispval (msb) 40-bit pld interface with pcs-pma set to 20 bits four 10-bit data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[20:11] tx_datainfull[31:22] tx_datainfull[42:33] - tx_datain (msbyte) table 3?3. tx_datainfull[43:0] pld data signal descriptions (part 3 of 3) pld interface description transmit signal description (based on stratix ii gx supported pld interface widths)
altera corporation 3?59 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration table 3?4. rx_dataoutfull[63:0] pld data signal descriptions (part 1 of 6) pld interface description receive signal description (based on stratix ii gx supported pld interface widths) 8-bit pld fabric interface the following signals are used in 8-bit 8b/10b modes: rx_dataoutfull[7:0] : 8-bit decoded data ( rx_dataout ) rx_dataoutfull[8] : control bit ( rx_ctrldetect ) rx_dataoutfull[9] : code violation status signal . it indicates error detected in rx_dataoutfull[7:0] , which is replaced by in valid code-group (invalid or running disp.error) in gige mode. in pci express, when code violation occurs, the edb character is placed on the erroneous data byte (= k30.7) ( rx_errdetect ) rx_dataoutfull[10] : rx_syncstatus rx_dataoutfull[11] : disparity error status si gnal. it indicates disparity error detected in rx_dataoutfull[7:0] ( rx_disperr ) rx_dataoutfull[12] : pattern detect status signal ( rx_patterndetect ) rx_dataoutfull[13] : reserved rx_dataoutfull[14] : reserved rx_dataoutfull[14:13] : pipe/pci-e mode: 2'b00: data ok; 2'b01: 1 skp deletion; 2'b10: elastic buffer underflow if data is 0xfe, else 1 skp insertion; 2b11: elastic buffer overflow ( rx_pipestatus ) rx_dataoutfull[15] : reserved the following signals are used in 8-bit sonet/sdh mode: rx_dataoutfull[7:0] : 8-bit un-encoded data ( rx_dataout ) rx_dataoutfull[8] : rx_a1a2sizeout rx_dataoutfull[10] : rx_syncstatus rx_dataoutfull[11] : reserved rx_dataoutfull[12] : rx_patterndetect 10-bit pld fabric interface rx_dataoutfull[9:0] : 10-bit un-encoded data ( rx_dataout ) rx_dataoutfull[10] : rx_syncstatus rx_dataoutfull[11] : reserved rx_dataoutfull[12] : rx_patterndetect rx_dataoutfull[13] : reserved rx_dataoutfull[14] : reserved rx_dataoutfull[15] : reserved
3?60 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 16-bit pld interface with pcs-pma set to 16/20 bits two 8-bit un-encoded data ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[23:16] - rx_dataout (msbyte) the following signals are used in 16-bit 8b/10b modes: two control bits rx_dataoutfull[8] - rx_ctrldetect (lsb) and rx_dataoutfull[24] - rx_ctrldetect (msb) two receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) and rx_dataoutfull[25]- rx_errdetect (msb) two receiver sync status bits rx_dataoutfull [10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) two receiver disparity error bits rx_dataoutfull [11] - rx_disperr (lsb) and rx_dataoutfull[43] - rx_disperr (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[45] : reserved rx_dataoutfull[14] and rx_dataoutfull[46] : reserved two 2-bit pipe status bits rx_dataoutfull[14:13] - rx_pipestatus (lsb) and rx_dataoutfull[46:45] - rx_pipestatus (msb) pipe/pci-e mode: 2'b00: data ok 2'b01: 1 skp deletion 2'b10: elastic buffer underflow if dat a is hexfe, else 1 skp insertion 2'b11: elastic buffer overflow rx_dataoutfull[15] and rx_dataoutfull[47] : reserved table 3?4. rx_dataoutfull[63:0] pld data signal descriptions (part 2 of 6) pld interface description receive signal description (based on stratix ii gx supported pld interface widths)
altera corporation 3?61 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 16-bit pld interface with pcs-pma set to 8/10 bits two 8-bit data rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[39:32] - rx_dataout (msbyte) the following signals are used in 16-bit 8b/10b mode: two control bits rx_dataoutfull[8] - rx_ctrldetect (lsb) and rx_dataoutfull[40] - rx_ctrldetect (msb) two receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) and rx_dataoutfull[41] - rx_errdetect (msb) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) two receiver disparity error bits rx_dataoutfull[11] - rx_disperr (lsb) and rx_dataoutfull[43] - rx_disperr (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[45] : reserved rx_dataoutfull[14] and rx_dataoutfull[46] : reserved two 2-bit pipe status bits rx_dataoutfull[14:13] - rx_pipestatus (lsb) and rx_dataoutfull[46:45] - rx_pipestatus (msb) pipe/pci-e mode: 2'b00: data ok 2'b01: 1 skp deletion 2'b10: elastic buffer underflow if dat a is hexfe, else 1 skp insertion 2'b11: elastic buffer overflow ( rx_pipestatus ) rx_dataoutfull[15] and rx_dataoutfull[47] : reserved the following signals are used in 16-bit sonet/sdh mode: two 8-bit data rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[39:32] - rx_dataout (msbyte) two receiver alignment pattern length bits rx_dataoutfull[8] - rx_a1a2sizeout (lsb) and rx_dataoutfull[40] - rx_a1a2sizeout (msb) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) table 3?4. rx_dataoutfull[63:0] pld data signal descriptions (part 3 of 6) pld interface description receive signal description (based on stratix ii gx supported pld interface widths)
3?62 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 16-bit pld interface with pcs-pma set to 8/10 bits (continued) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) 20-bit pld interface with pcs-pma set to 20 bits two 10-bit data (rx_dataout) rx_dataoutfull[9:0] - rx_dataout (lsbyte) and rx_dataoutfull[25:16] - rx_dataout (msbyte) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[26] - rx_syncstatus (msb) rx_dataoutfull[11] and rx_dataoutfull[27] : reserved two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[28] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[29] : reserved rx_dataoutfull[14] and rx_dataoutfull[30] : reserved rx_dataoutfull[15] and rx_dataoutfull[31] : reserved 20-bit pld interface with pcs-pma set to 10 bits two 10-bit data rx_dataoutfull[9:0] - rx_dataout (lsbyte) and rx_dataoutfull[41:32] - rx_dataout (msbyte) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) rx_dataoutfull[11] and rx_dataoutfull[43] : reserved two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[45] : reserved rx_dataoutfull[14] and rx_dataoutfull[46] : reserved rx_dataoutfull[15] and rx_dataoutfull[47] : reserved table 3?4. rx_dataoutfull[63:0] pld data signal descriptions (part 4 of 6) pld interface description receive signal description (based on stratix ii gx supported pld interface widths)
altera corporation 3?63 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 32-bit mode four 8-bit un-encoded data ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) rx_dataoutfull[23:16] rx_dataoutfull[39:32] rx_dataoutfull[55:48] - rx_dataout (msbyte) the following signals are used in 32-bit 8b/10b mode: four control data bits ( rx_dataout ) rx_dataoutfull[8] - rx_ctrldetect (lsb) rx_dataoutfull[24] rx_dataoutfull[40] rx_dataoutfull[56] - rx_ctrldetect (msb) four receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) rx_dataoutfull[25] rx_dataoutfull[41] rx_dataoutfull[57] - rx_errdetect (msb) four receiver pattern detect bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] rx_syncstatus (msb) four receiver disparity error bits rx_dataoutfull[11] - rx_disperr (lsb) rx_dataoutfull[27] rx_dataoutfull[43] rx_dataoutfull[59] - rx_disperr (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) rx_dataoutfull[13] , rx_dataoutfull[29] , rx_dataoutfull[45] and rx_dataoutfull[61] : reserved rx_dataoutfull[14] , rx_dataoutfull[30] , rx_dataoutfull[46] , and rx_dataoutfull[62] : reserved rx_dataoutfull[15] , rx_dataoutfull[31] , rx_dataoutfull[47] , and rx_dataoutfull[63] : reserved table 3?4. rx_dataoutfull[63:0] pld data signal descriptions (part 5 of 6) pld interface description receive signal description (based on stratix ii gx supported pld interface widths)
3?64 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration the following signals are used in 32-bit sonet/sdh scrambled backplane mode: four control data bits ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) rx_dataoutfull[23:16] rx_dataoutfull[39:32] rx_dataoutfull [55:48] - rx_dataout (msbyte) rx_dataoutfull[8] , rx_dataoutfull[24] , rx_dataoutfull[40] , and rx_dataoutfull[56] : four reserved four receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) 40-bit mode four 10-bit control data bits ( rx_dataout ) rx_dataoutfull[9:0] - rx_dataout (lsbyte) rx_dataoutfull[25:16] rx_dataoutfull[41:32] rx_dataoutfull[57:48] - rx_dataout (msbyte) four receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) table 3?4. rx_dataoutfull[63:0] pld data signal descriptions (part 6 of 6) pld interface description receive signal description (based on stratix ii gx supported pld interface widths)
altera corporation 3?65 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration alt2gxb_reconfig setup fo r channel reconfiguration the alt2gxb_reconfig (dynamic reconfiguration controller) instance must be set up for the channel reconfiguration feature. you can have one dynamic reconfiguration co ntroller for one alt2gxb instance (each alt2gxb instance can have multiple transceiver channels) or one dynamic reconfiguration controller controlling more than one alt2gxb instance. select the feature channel reconfigura tion (protocol switch) . set the what is the number of channe ls controlled by the reconfig controller? option and select the opti onal signals in the channel reconfiguration section. connect the alt2gxb and alt2gxb_reconfig instances. dynamic transmit rate switch dynamic rate switch is only available for the transmit side and not for the receive side. the control signal rate_switch_ctrl[1:0] sets up the division factor for the local divi der inside the transmit side of the transceiver channel. the followi ng is the encoding for the rate_switch_ctrl port: 00 - divide by 1 01 - divide by 2 10 - divide by 4 11 - not supported, do not set this value the above values are written and based in the alt2gxb_reconfig instance initiating a write transaction by pulsing the write_all signal. this feature can be enabled throug h two other features?the analog settings and the channel reconfiguratio n. when two or more features are enabled, the reconfig_mode_sel signal needs to be set to the desired feature before a write transaction is initiated. a read transaction is allowed in this feature and the rate_switch_out[1:0] is required to read out the current data rate division factor through the alt2gxb_reconfig instance. do n ot perform a read transaction in this mode if the rate_switch_out is not selected in the alt2gxb_reconfig megawizard. 1 the dynamic rate switch has no effect on the dividers on the receive side of the transceiver channel. it can be used only for the transmitter. you must be aware of the device operating range before you enable and use this feature. there are no lega l checks that are imposed by the quartus ii software, since it is an on-t he-fly control feature. you also need to ensure that a specific functional mode supports the data rate range before dividing the clock when using this rate switch option.
3?66 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration reset recommendations altera recommends that you follow a proper reset sequence during and after for pma controls reconfiguration, channel reconfiguration, and dynamic transmit rate switching. pma controls reconfiguration during the first time th e dynamic reconfiguration controller initiates a read or write, for example to chan ge or read the pma controls (vod, pre-emphasis, equalization, or dc gain ), the transceiver channel switches permanently from the registers that co ntain static transceiver settings to registers that are written by the dy namic reconfiguration controller. due to this asynchronous switching, ther e may a few bit errors and transitions in the transceiver status signals. therefore, perform a one time pma control read or write transaction from the dynamic reconfiguration controller during system bringup (initialization). this operation sets th e transceiver to list en to the registers written by the dynamic reconfigur ation controller during system bringup. by performing this read or write transaction during system bringup, you avoid errors duri ng normal system operation. channel reconfiguration when you use the two tx plls in your design to reconfigure the channel, use the combination of the pll_locked and pll_locked_alt signals as part of your reset sequence. in the two tx pll designs, the updated tx pll locked signal is: pll_locked_final* = ( pll_locked and pll_locked_alt)
altera corporation 3?67 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?32 shows a waveform of the initialization and reset sequence of a design that uses main and alternate tx plls. figure 3?32. reset sequence (1 > 2 > 3 > 4 > 5 > 6) the general reset sequence recommendations for bringing the device up are also valid. f refer to the reset control and power down section of the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx handbook for more information. in addition to the above recommendations, if you are using the channel reconfiguration feature, consider this additional recommendation: if the channels are duplex and have individually switching modes using channel reconfiguration, consider the following: reset controllers shou ld be channel based the channel_reconfig_done signal can be used as a condition to reset the transmit and receive of the transceiver channel during and after channel reconfiguration transmit digital resets ( tx_digitalreset ) are asserted during and after channel reconfiguration assert the rx_analogreset signal and follow the reset sequence on the receiver side during and after the channel reconfiguration. figure 3?33 shows the reset sequence for channel reconfiguration. t= 4us gxb_powerdown tx_digitalreset rx_analogreset rx_digitalreset rx_freqlocked 1 3 4 4 5 6 2 output status signals reset/power down signals t pll_locked pll_locked_alt pll_locked_final
3?68 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?33. reset sequence (1 > 2 > 3 > 4) during and after channel reconfiguration notes to figure 3?33 : (1) tx_digitalreset is valid in transmitter-only and duplex configurations. (2) rx_analogreset and rx_digitalreset are valid in receiver-only and duplex configurations. if the channel reconfiguration is do ne in a tx-only design, assert the transmit digital reset ( tx_digitalreset ) during and after channel reconfiguration, as shown in figure 3?33 . ( channel_reconfig_done assertion signifies that the alt2gxb_reconfig controller finished the channel reconfiguration by shifting an entire mif into an alt2gxb channel.) if the channel reconfiguration is done in an rx-only design, assert the rx_analogreset signal and follow the reset sequence on the receiver side. figure 3?33 shows the receiver sequence. dynamic rate switching for a design using dynamic transmit rate switching, altera recommends that you assert the tx_digitalreset when you initiate the rate switch operation until the busy signal goes low. t 2 = 4us 2 3 t2 4 1 t1 t 1= 5 parallel clock cycles 2 reset sequence: 1 > 2 > 3 > 4 tx_digitalreset (1) rx_analogreset (2) rx_digitalreset (2) channel_reconfig_done rx_freqlocked resets output status signals
altera corporation 3?69 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration overall design flow for channel reconfiguration the following describes the design flow for stratix ii gx channel reconfiguration. alt2gxb instantiation 1. create an alt2gxb megawizard instantiation. select the protocol mode, single width, double width, data rate, and input reference clock frequency. 2. select the required status signals. 3. in the reconfig tab, select the channel internals. 1 if you intend to perform only rate division control, proceed to step 6 . 4. if you would like to switch between two configurations that have different input clock frequencies, select the use alternate reference clock option to configure the se cond tx pll. specify the what is the logical reference clock index? option value. 5. if the configuration requires different pld interface widths or additional control signals provided in the reconfig2 tab, select the channel interface option. 6. select the appropriate clocking scheme in the reconfig2 tab. 7. select the required additional cont rol signals for the configuration in the reconfig2 tab (this is only enabled if the channel interface option is selected). mif generation: 8. create a top-level design and connect the clock inputs in the rtl/schematic. specifically, for the transceiver clock inputs, connect pll_inclk and rx_cruclk to the input pins that provide the clock for the protocol mode specified in the general tab of the alt2gxb megawizard. similarly, connect pll_inclk_alt and rx_cruclk_alt to the clock source that provides the clock for the protocol mode specified in the reconfig tab of the alt2gxb megawizard. 1 if you do not specify pins for tx_dataout and rx_datain for the transceiver channel, the quartus ii software selects a channel and generates a mif for that cha nnel. however, the mif can still be used for any transceiver channel.
3?70 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 9. you can generate multiple mif in the following two ways: method 1: compile the design created in step 8 and generate the first mif. update the alt2gxb megawizard instance with the alternate configuration and connect the appropriate clock inputs, as mentioned in step 8. compile the design to get the second mif. 1 if you have to generate mifs for many configurations, this method takes more time to complete. method 2: in the top-level design, instantiate all the different configurations of the alt2gxb instantiation for which the mif is required. connect the appropriate clock inputs of all the alt2gxb instantiations (see step 8). generate the mif. the mifs are generated for all the alt2gxb configurations. 1 this method requires attention wh en generating the mif. please check the following: the different alt2gxb instan tiations shou ld have the appropriate logical reference clock index option values. the clock inputs for each instan ce should be connected to the appropriate clock source. when you generate the mif, use proper naming for the files so you know the configuration supported by the mif. alt2gxb_reconfig: 10. create the alt2gxb_reconfig instance. select the channel reconfiguration option to perform channel reconfiguration. select rate_switch_ctrl for the transmit side data rate division. 11. select the reconfig_address_out and reset_reconfig_address signals from the channel reconfiguration tab. control logic for alt2gxb_reconfig: 12. implement logic to control the alt2gxb_reconfig signals and to select the appropriate mifs from memory and send the mif data to alt2gxb_reconfig.
altera corporation 3?71 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration data path logic: 13. implement logic to handle the data from the transceiver. when you change the transceiver channel configuration, the data path, clocking, or pld interface width may change. therefore, implement logic in the pld to transmit and receive data between the transceiver and the pld logic, based on the transceiver configuration. figure 3?34 shows the design functional blocks to perform channel reconfiguration. reset control logic: 14. implement the reset control logic to handle the transceiver and the system resets. refer to ?reset recommendations? on page 3?66 for more information. figure 3?34. functional blocks fo r channel reconfiguration reset control logic data path logic alt2gxb_ reconfig control logic for alt2gxb_ reconfig alt2gxb mif1 mif2
3?72 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration channel reconfiguration design examples this section provides three ex amples for performing dynamic reconfiguration on a transceiver channel. example 1?configuri ng a transceiver channel between gige mode and sonet/sdh oc48 mode the gige mode in the alt2gxb mega function is different from the sonet/sdh oc48 mode in data pa th, clocking, and pld interface width. the differences between the two modes are listed in table 3?5 . these differences determine the selection of parameters in the alt2gxb megawizard and the required pld logic to configure a transceiver channel between these two modes. figure 3?35 shows the required functional blocks to perform channel reconfiguration. table 3?5. differences between gige and sonet/sdh oc48 number functional block gige sonet/sdh oc48 1 pld width 8 16 2 8b/10b enabled yes no 3 rate matcher yes no 4 byte order block no yes 5 clock used for synchronizing the receive output data ( rx_dataout ) tx_clkout (since rate matcher is used) rx_clkout 6 data rate 1.25 gbps 2.488 gbps 7 allowed input reference clock 62.5 mhz 125 mhz 77.76 mhz 155.52 mhz 311.04 mhz 622.08 mhz 8pcs-pma interface width 10 (since data is 8b/10b encoded) 8
altera corporation 3?73 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?35. reconfiguring between gige and sonet /sdh oc48 modes the discussion of the functional blocks is divided into four sections. the topics discussed in each section are as follows: section i?lists the steps to configure the alt2gxb instance to generate the mif for gige and sonet/sdh oc48 modes. then lists the steps to create the alt2gxb_reconfig instance. section ii?sets up the control logic for the alt2gxb_reconfig controller. section iii?logic to process the gige and sonet/sdh data. this logic is required due to the differences in the data interface widths and the clocking between the two modes (shown in table 3?5 ). section iv?resets the control logic to control the transceiver and system resets. reset control logic megawizard instantiation user logic in the pld control logic for reconfig controller alt2gxb_ reconfig alt2gxb logic for the gige and sonet datapath memory 1 containing gige mif memory 2 containing sonet mif
3?74 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration section i use the following steps to generate a mif for gige and sonet/sdh oc48 modes: 1. generate the alt2gxb instantiation for gige mode. 2. generate the al2gxb_r econfig instantiation. 3. create a top-level design and generate the mif for the gige protocol mode. 4. modify the alt2gxb instantiation for sonet /sdh oc48 mode. 5. generate the mif for sonet/sdh oc48 mode. 6. initialize two memory elements with the mif contents and write logic to select the mif and to control the alt2gxb_reconfig instance. step 1?generate the alt2gxb instantiation for gige mode: this example shows the alt2gxb instantiation for one-channel gige and sonet/sdh mode. 1. set the protocol to gige mode in the first screen. select the following control and status signals: rx_digitalreset tx_digitalreset rx_analogreset rx_pll_locked rx_freqlocked 2. add the other required status signals. f for a list of alt2gxb signals and their functionality, refer to ?stratix ii gx alt2gxb ports list? on page 2?2 in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook . 3. in the reconfig tab, set the following options: if you need control of the transceiver pma values, select the analog pma controls. for more information about pma controls, refer to ?introduction? on page 3?1 .
altera corporation 3?75 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 4. select the channel internals and use alternate reference clock options. selecting these options enable the second pll for the sonet/sdh oc48 mode. a second pll is needed because of the difference in the required input clock frequency and data rate between the gige and sonet/sdh oc48 modes (refer to rows 6 and 7 in table 3?5 ). 5. set the what is the protocol to be reconfigured? option to sonet/sdh . 6. set the sub protocol option to oc48 (see figure 3?31 ). 7. select the input clock frequency and alternate transmitter pll bandwidth mode options based on the requirements. the allowed reference clock input freque ncies for sonet/sdh oc48 are specified in row 7 of table 3?5 . 8. for the what is the logical reference index? option, select 1 or 0 . the quartus ii software uses the logi cal reference index to select the pll clock outputs for the transmit and receive channels when configured to sonet/sdh oc48 protocol. the mux values selected for the gige and sonet/sdh oc48 modes should be different. 1 for example, if you select 1 for the what is the logical reference index? option for the sonet/sdh oc48 mode, you should select 0 for gige mode. if you select the same values for the two modes, the transceiver behavior after reconfiguration becomes unpredictable. 9. select the channel interface option. selecting channel interface creates the data interface signals tx_datainfull and rx_dataoutfull that are comprised of control and data signals. this selection is required because of the differences in the pld interface width between the gige and sonet/sdh modes (row 1 in table 3?5 ). the description of individual bits of tx_datainfull and rx_datainfull are provided in ?channel interface? on page 3?53 . 10. in the reconfig2 tab, under the how should the receivers be clocked? option, check the use the respective channel core clocks option. selecting this option creates the rx_clkout port. select this option because of the clocking differences between the two modes (row 5 of table 3?5 ). therefore, the pld logic can clock the receive output of the alt2gxb with rx_clkout for sonet/sdh mode and tx_clkout for the gige mode.
3?76 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 11. in the how should the transmitters be clocked? option, select any option. since this exam ple assumes a one-channel reconfiguration in the transceiver block, the above op tions will not make a difference. however, if the number of channels used in channel reconfiguration is more than one, altera recommends you select the share single transmitter core cloc k between transmitters option to conserve clock routing resources. 12. select signals in the check a control box to use the corresponding control fields option based on the requir ements. the signals in this tab can be selected only if the channel interface option is enabled in the reconfig tab. for this example, select the signals rx_byteorderalignstatus and rx_a1a2sizeout , since these signals are required for sonet/sdh oc48 mode. 1 some of the signals are meaningf ul only for the modes for which they are intended. for example, the rx_byteorderalignstatus signal is only meaningful in sonet/sdh oc48 mode. pld logic should not use these signals for gige mode. f for more information about the protocol-specific alt2gxb interface signals, refer to ?stratix ii gx alt2gxb ports list? on page 2?2 in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook . 13. in the subsequent tabs, select the required signals and complete the megawizard instantiation. step 2?generate the alt2gx b_reconfig instantiation: 1. set the what is number of channels controlled by the reconfig controller? option to 1 . 2. select analog controls to modify the pma values, if desired. 3. select channel reconfiguration . this selection is required to perform a channel reconfiguration. 4. select the required signals under the write control and read control options, if the analog controls option in screen 1 is selected. f refer to the alt2gxb_reconfig mega function user guide chapter in volume 2 of the stratix ii gx device handbook for information about write-control and read-control signals.
altera corporation 3?77 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 5. in the channel reconfiguration page, select the reconfig_address_out . this signal incremen ts by 1, from 0 to 27, then starts at zero again. th e other available control signals in the megawizard are reconfig_address_en and reset_reconfig_address . selecting these signals is optional. the timing and description of these signals are provided in ?section ii?control logic for the reco nfig controller:? on page 3?84 . 6. complete the alt2gxb_reconfig megawizard instantiation. step 3?create a top-level design and generate the mif for gige protocol mode: clock input connectio ns for the alt2gxb megafunction are listed below. the clock source should feed the following clock inputs: gige mode? pll_inclk and rx_cruclk inputs. sonet/sdh oc48 mode? pll_inclk_alt and rx_cruclk_alt inputs. 1. since gige is the protocol mode you selected in the first page of the alt2gxb megawizard, the quartus ii software requires the gige clock source to be connected to pll_inclk and rx_cruclk inputs. 2. connect the cal_blk_clock input of the alt2gxb instance to a clock source. f refer to the ?stratix ii gx alt2gxb ports list? on page 2?2 in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for the cal_block_clk signal requirements. 3. connect the tx_dataout and rx_datain ports to the top-level module. this is required for the quartus ii software to compile successfully. to generate the mi f, connecting the other input and output ports of the alt2gxb instance is not mandatory. 4. assign pins for the clock ports ( pll_inclk , rx_cruclk , pll_inclk_alt , and rx_cruclk_alt ). if pin assignments are not made for the tx_dataout and rx_datain ports of the alt2gxb instantiation, the quar tus ii software automatically selects pins for these ports and names the mif with the pin name extension. the mif can still be used by any physical transceiver channel to perform reconfiguration.
3?78 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration after compilation of the design, the quartus ii software creates the mif in the reconfig_mif folder under the project directory. copy the mif and save it in a separate folder. otherwi se, the new mif that is generated for the sonet/sdh mode will overwrite the current mif. step 4?modify the alt2gxb inst antiation for sonet/sdh oc48 mode: 1. to create a mif for the sonet/sdh oc48 mode, either modify the existing alt2gxb instantiation created for gige mode or create a new instantiation for sonet mode. however, the first method is easier since it does not require major rtl or schematic changes. 2. open the existing alt2gxb instantiation. select the which protocol you will be using? option and set it to sonet/sdh . set the sub protocol option to oc48 . all the other signals selected for gige mode should not be changed. 3. in the reconfig tab, select the channel internals and alternate reference clock options. in the protocol section, select gige . select the same input clock frequency selected in step 1 . 4. for the logical reference clock index option, choose the complement of what yo u selected in step 10 . 5. select the channel interface and complete the instantiation. step 5?generate the mif for sonet/sdh oc48 mode: 1. before compiling the design, in the rtl or schematic, connect the pll_inclk and rx_cruclk to the clock source that provides the sonet/sdh oc48 clock. similarly, connect pll_inclk_alt and rx_cruclk_alt to the clock source that pr ovides the gige clock. the quartus ii software generates the new mif in the /reconfig_mif directory. step 6?initialize two memory elem ents with the mif contents and write logic to select th e mif and to control the alt2gxb_reconfig: 1. create two memory elements, each 16-wide and 28-bits deep. the memory elements can be a ra m/rom inside or outside the stratix ii gx device. assign the tw o mifs to each of these memory elements.
altera corporation 3?79 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration section ii?control logic fo r the reconfig controller: the control logic block is required to perform the following functions: select the memory to configure a channel to the gige or sonet/sdh mode. control the reconfiguration mode (namely the pma mode or the channel configuration mode). control the read and write si gnals to the alt2gxb_reconfig megafunction based on the busy , data valid , and address_out signals. the following is an example flow of channel reconfiguration by writing the mif contents of memory locati on 1 to the reconfig controller: 1. set the reconfig_mode_sel to -001 . 2. select the data input from memory location 1. 3. wait until the busy signal from the alt2gxb_reconfig megafunction is low. 4. check whether the reconfig_address_out is less than 28 decimals. 5. wait for the data out from memory location 1 corresponding to the new reconfig_address_out becomes available at the reconfig_data port before asserting the write_all signal. figure 3?36 shows the various signal transitions during channel reconfiguration. the alt2gxb_reconfig megafuncti on provides these additional signals: reconfig_address_en reset_reconfig_address the alt2gxb_reconfig megafunction asserts the reconfig_address_en signal to indicate that the reconfig_address_out has changed. in test designs, the reconfig_address_out was monitored to determine the end of the write operation. you can also use the channel_reconfig_done signal to determine the end of the write operation. the channel_reconfig_done signal goes high one clock cycle after the reconfig_address_out signal changes from 27 back to 0.
3?80 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?36. timing of the alt2gxb_reconfig signals section iii?logic and clocking fo r the gige and sonet/sdh oc48 datapath: in the alt2gxb megawizard, the channel interface that created tx_datainfull (44-bits wide) and rx_dataoutfull (64-bits wide) was selected. in addition, the rx_byteorderalignstatus and the rx_a1a2size signals were selected. the pld logic should selectively use some of these signals based on whether the transc eiver channel is configured in gige mode or sonet/sdh oc48 mode. channe l_reconfig_done 001 0 1800 reconfig_mode_sel busy reconfig_address_en write_all reconfig_address_out 27 reconfig_data 2000 0 1800
altera corporation 3?81 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration table 3?6 provides descriptions for the tx_datainfull and rx_dataoutfull signals for gige and sonet/sdh oc48 modes. clocking for the transmit side, the pld logi c for the sonet/sdh oc48 and gige modes sends the data synchronized to the tx_clkout signal. therefore, the clocking for the transmit side remains the same for the two modes. for the receive side, the data and status signals from the alt2gxb megafunction for the gige mode is synchronized to tx_clkout since rate matching is used. for the so net/sdh oc48 mode, the signals are synchronized to rx_clkout . therefore, the pld logic has two functional protocol-specific logic blocks to handle data for the gige and sonet/sdh oc48 modes. based on the configured protocol mode, the receive side logic selects the appropriate data path. table 3?6. pld interface signals?gi ge and sonet/sdh oc48 modes signal name description gige mode tx_datainfull[7:0] 8-bit unencoded data input to the transceiver channel tx_datainfull[8] tx_ctrlenable (control signal k/d) rx_dataoutfull[7:0] 8-bit unencoded data output from the transceiver channel rx_dataoutfull[8] rx_ctrldetect (control signal k/d) rx_dataoutfull[9] rx_errdetect rx_dataoutfull[10] rx_syncstatus rx_dataoutfull[11] rx_disperr rx_dataoutfull[12] rx_patterndetect sonet/sdh oc48 mode tx_datainfull[7:0] lsb data input to the transceiver channel tx_datainfull[29:22] msb data input to the transceiver channel rx_dataoutfull[7:0] lsb data output from the transceiver channel rx_dataoutfull[29:22 msb data output from the transceiver channel rx_dataoutfull[10], rx_dataoutfull[42] rx_syncstatus[1:0] rx_dataoutfull[12], rx_dataoutfull[44] rx_patterndetect[1:0]
3?82 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration figure 3?37 shows the block di agram for a receive side pld logic to handle the gige and sonet/sdh oc48 datapath. figure 3?37. rx pld logic to proces s gige and sonet/sdh oc 48 data section iv?reset control logic: the reset control sequence for channel reconfiguration (explained in ?reset recommendations? on page 3?66 ) must be followed during and after the channel configuration proces s. in addition, when resetting the transceiver channel, the reset control logic should reset the data path in the pld logic to clear the error data received during the reconfiguration process. 1 for a pma-only configuration (for example, changing the v od , equalization, dc gain, or pre-em phasis), the transceiver channel or the datapath in the pld logic does not require a reset after reconfiguration. reset is required only for channel reconfiguration or rate switch. simulation: to simulate channel reconfiguration, some simulation tools only allow .ram or .hex files to initialize the memory. to convert the generated mif to a .hex file, open the .mif in the quartus ii software and save it as a .hex file. initialize the memo ry elements with the .hex file to simulate the design. alt2gxb fifo sonet protocol-specific logic gige protocol-specific logic fifo system_clock rx_data outfull mux system logic rx_data outfull rx side pld logic for gige and sonet oc48 datapath tx_clkout rx_clkout system_clock
altera corporation 3?83 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration example 2?channel configuration betw een a basic mode configured for 3.125 gbps and a basic mode configured for 2.000 gbps the pcs functional blocks and the pld interface (16 bits) is the same for both modes. given that the functional blocks are the same, to achieve the two data rates mentioned above, use two different input reference clock frequencies for the two modes. table 3?7 shows the transceiver configuration for the two modes. the description for this design example is divided into four sections: section i?steps to create the mif for the two transceiver modes section ii?steps to create the alt2gxb_reconfig instantiation section iii?sets up control logic in the pld for alt2gxb_reconfig section iv?resets control logic section i?steps to create the mif for the two transceiver modes: 1. in the first page of the alt2gxb megawizard, complete the following: set mode to basic select single width set the channel width to 16 set the number of channels to 1 set the data rate to 3.125 gbps . 2. set the input reference clock to 156.25 mhz . 3. select all the resets, pll_locked , rx_freqlocked , and other required status signals. table 3?7. differences between two basic modes number 1 channel basic mode 1 1 channel basic mode 2 data rate 3125 2000 input reference clock frequency 156.25 mhz 125 mhz pld interface width 16 16 8b/10b enabled yes yes rate matcher no no clock used for synchronizing the receive output data ( rx_dataout ) rx_clkout rx_clkout
3?84 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration 4. in the reconfig tab, select analog controls if you wish to modify the pma values dynamically (v od , pre-emphasis, dc gain, and equalization). 5. select the channel internals and use alternate reference clock options. these options mu st be selected since basic mode 2 requires a different input clock frequency. 6. set the protocol option to basic , set the data rate to 2.000 gbps , and set the input clock frequency option to 125 mhz . for this example, since both the configurations ha ve the same pld interface width and functional blocks ( table 3?7 ), you do not need the channel interface option. 7. in the reconfig 2 tab, select the use respective receiver core clocks and use respective transmitter core clocks options (row 6, table 3?7 ). 8. complete the alt2gxb megawizard instantiation. section ii?control logic fo r the reconfig controller: follow the same procedure as described in ?example 1?configuring a transceiver channel between gige mode and sonet/sdh oc48 mode? on page 3?72 . section iii?logic for the basic mo de 1 and basic mode 2 datapath: clock the data to the transceiver with the tx_clkout signal on the transmitter side for both configuratio ns. similarly, for the receive side, clock the data from th e transceiver with the rx_clkout signal for both configurations. a single logic block ca n handle data processing when the transceiver channel is config ured between these two modes. section iv?reset and control logic: follow the same procedure as described in ?example 1?configuring a transceiver channel between gige mode and sonet/sdh oc48 mode? on page 3?72 . example 3: dynamic rate switch for the transmit side design example this design example explains the steps to dynamically divide the transmit data rate of a transceiver ch annel by 4, 2, or 1 without requiring mif generation. the alt2gxb_reconfig instance provides a rate_switch_ctrl signal for this purpose.
altera corporation 3?85 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 1 use the rate_switch_ctrl signal only for dividing the data rate of the transmit side. to divide the data rate for both the transmit and receive sides, a mif-based approach is required. this example uses a basic mode with 8b/10b enabled running at 4 gbps data rate. you can configure the mo de dynamically between 4.25 gbps, 2.25 gbps, and 1.125 gbps. the description for this design ex ample is divided into the following sections: section i?create the alt2gxb instantiation for the transceiver channel section ii?create the alt2gxb_reconfig instantiation section iii?create the top-level design section i?create the alt2gxb instantiation for the transceiver channel: 1. create a basic mode by setting the operation mode to transmit and receive . 2. select double width mode. this is required since the highest data rate in this example is 4.25 gbps ( single width can be selected only up to 3.125 gbps). set the channel width to 32 . the lowest pld frequency allowed in the quartus ii software is 25 mhz. therefore, the transceiver runs at 1.125 gbps with a 32-bit pld interface. the pld clock frequency in this case is 26.5 mhz (1125/40 = 26.5). 3. set the input frequency to 106.25 mhz . 4. in the reconfig tab, check the channel internals option. this is required to enable the alt2gxb_reconfig instance to modify the channel local divider values dynamically. the alternate reference clock is not required since one clock source is used. also, the data rates can be derived from the 106.25 mhz clock. 5. complete the alt2gxb megawizard instantiation. section ii?create the alt2gxb_reconfig instantiation: 1. instantiate the alt2gxb_reconfig megafunction as described in ?example 1?configuring a tran sceiver channel between gige mode and sonet/sdh oc48 mode? on page 3?72 . 2. select the modify the data rate using the local divider option in the reconfiguration settings tab. this creates the rate_switch_ctrl and rate_switch_ctrl_out signals.
3?86 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and pma controls reconfiguration table 3?8 shows the values for each of the rate_switch_ctrl settings. 3. complete the alt2gxb_reconfig megawizard instantiation. section iii: create the top-level design create the alt2gxb_reconfig instance control logic, reset control logic, and the pld logic to handle the data path. refer to ?reset recommendations? on page 3?66 for information on transceiver resets. 4. create the top-level design an d connect the func tional blocks. pseudo-write sequence for simu lating channel reconfiguration if you are simulating channel reconf iguration, consider a case where you are using multiple transceiver channels in your design driven by a single dynamic reconfiguration controller . when you first perform channel reconfiguration on a transceiver channel, rx_freqlocked and rx_clkout of all channels that are co nnected to the reconfiguration controller go to 0 for a few clock cycl es. this occurs because the receive plls in the simulation model require a relock when channel reconfiguration is enabled. 1 this issue happens only in simulation the first time you initiate channel reconfiguration. to work around this issue, perf orm the following one-time write sequence as part of your system initialization when you assert the gxb_powerdown or rx_analogreset signals. the signals that are referred to in the following write sequence correspond to the input and output ports of the alt2gxb_reconfig instantiation in your design. table 3?8. rate switch control signal settings rate_switch_ctrl[1:0] se ttings local divider val ue in the transmit channel 00 1 01 2 10 4 11 not applicable
altera corporation 3?87 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 1. set the reconfig_mode_sel signal to 001 . write the default .hex / .mif file contents for two reconfig_address_out signal increments. that is, pulse the write_all signal for the reconfig_address_out 0 and 1 based on the busy and reconfig_address_en signals. 2. the .hex / .mif file selected for writing should correspond to the default configuration in the alt2gxb megawizard. for example, if you have two .hex / .mif files that correspond to gige and sonet/sdh oc48 protocols, and if you have set gige as your default configuration (the protocol set in the general tab of the alt2gxb megawizard), write the first two words of the .hex / .mif file generated for gige protocol. 3. after you complete writing the first two words, wait for the busy signal to go low and assert the reset_reconfig_address signal to initialize the reconfig_address_out to 0. channel and clock multiplier unit (cmu) pll reconfiguration introduction the stratix ii gx transceiver can be dynamically reconfigured to various protocols and data rates. this section discusse s the dynamic reconfiguration features introduced in quartus ii software version 7.1. altera assumes you have prior knowledge about the dynamic reconfiguration controller architecture (refer to ?dynamic reconfiguration controller architecture? on page 3?2 ), the stratix ii gx transceiver architecture, and the memory initialization file ( .mif , also known as mif) flow (refer to ?mif generation in quartus ii software? on page 3?32 ) for dynamic reconfiguration. synopsis of existing dynamic reconfiguration features in the quartus ii software version 7.0 and earlier, the following dynamic reconfiguration features were available: pma reconfiguration?to control voltage output differential (v od ), pre-emphasis, equalization, and dc gain. channel reconfiguration?to dynamically reconfigure the transceiver data rates, protocol mo des, or a combination of these two options. this method requires a mif to reconfigure a channel. dynamic transmit rate switch? to dynamically reconfigure the transmit data rate by changing the local divider settings in the transmit side. the available local div ider options are by /1, /2, or /4. this method does not require a mif for reconfiguration. 1 this option can only change the transmitter data rate and not the receiver data rate.
3?88 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration figure 3?38 shows the transceiver blocks (grayed out) that can be dynamically reconfigured using the channel reconfiguration feature. 1 figure 3?38 shows that the tx plls and the clock multiplexer on the transmit side (inside the clock multiplier unit) could not be reconfigured using these featur es. it also shows that only two sources of input reference clocks were available for the tx plls and rx plls. figure 3?38. reconfigured func tional blocks with channel reconfiguration note (1) note to figure 3?38 : (1) supported from the quartus ii software version 6.1. overview of quartus ii software version 7.1 features for dynamic reconfiguration the quartus ii software version 7.1 provides the following enhancements to support dynamic reconfiguration: three additional features to dynami cally reconfigure the transceiver channel and the tx plls: tx pll-only reconfiguration channel and tx pll reconfiguration channel reconfiguration with tx pll select the number of possible clock source s for the input reference clocks is increased from two to five. clock mux main txpll clock multiplier unit full duplex transceiver channel tx channel logical tx pll select local dividers digital + analog logic clock mux rx channel clock mux digital + analog logic rx pll clock 1 clock 0 main txpll
altera corporation 3?89 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration settings to generate a mif with 38 words (required for the features mentioned above). you will need this mif just as you needed one in the channel reconfiguration feature (see ?channel reconfiguration? on page 3?30 ). 1 to write the mif, follow the sa me method used for channel reconfiguration (see ?channel reconfiguration? on page 3?30 for more information). the functi onality of all other signals, such as write_all , channel_reconfig_done , reconfig_address_en , logical_channel_address , data_valid , and busy is the same as that of the channel reconfiguration feature. these new features provide flexibility to reconfigure a tx pll to multiple data rates, dynamically switch the tran smit channel to listen to any of the two tx plls, and to configure a tr ansceiver channel. using these enhancements, you can use the strati x ii gx transceiver to dynamically support multiple protocols and data ra tes. in the following sections, the new dynamic reconfiguration features and the different software settings required to implement these features are discussed in detail. conventions used throughout this document, the following conventions are used: channel and cmu pll reconfiguration?refers to the three dynamic reconfiguration features introduced in the quartus ii software version 7.1. channel and tx pll reconfiguration?refers to one of the features in channel and cmu pll reconfiguration. channel?refers to the transceiver channel with digital and analog functional blocks. main txpll? refers to the tx pll that is configured in the general tab of the alt2gxb megawizard. alternate txpll?refers to the tx pl l that is configured in the reconfig alt pll tab of the alt2gxb megawizard. logical tx pll?refers to the logica l identification value 0 or 1, assigned to the main an d alternate txplls. you set this value in the reconfig clks 1 and reconfig alt pll tabs of the alt2gxb megawizard. reconfig controller?refers to the dynamic reconfiguration controller that you instantiate using the alt2gxb_reconfig megawizard. in this document, reconfig controller and alt2gxb_reconfig are used interchangeably.
3?90 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration clocking enhancements and requirements to configure the tx plls and rx plls for multiple data rates, it is important to understand the input re ference clock requirements. this helps you to efficiently create the cloc king scheme for reconfiguration and to reuse the mifs across all channe ls in the device. the new clocking enhancements and the implications of using input cloc ks from various clock sources are reviewed in this section. when you enable the channel and cmu pll reconfiguration option in the alt2gxb megawizard (by selecting the enable channel and transmitter pll reconfiguration option in the reconfig tab), the quartus ii software version 7.1 al lows a maximum of five possible sources available for in put reference clocks. figure 3?39 shows the different clock sources that connect to the transceiver block. figure 3?39. transceiver block w ith global clock line connections these five clock inputs appear as a pll_inclk_rx_cruclk[] port and can be provided from the inter transceiver block lines, also referred as inter quad (iq) lines, or from the global clock netw orks that are driven by an input pin. figure 3?40 shows the reference clock connections to tx plls and rx plls in a transceiver channel. 2 transmitter pll 0 global clk line iq[4..0] transceiver block 0 refclk0 transmitter pll 1 to iq0 iq[4..0] iq[4..0] global clk line 4 receiver plls refclk1 from global clock line (3) 2 2
altera corporation 3?91 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?40. input reference clock connec tions to the transceiver channel note to figure 3?40 : (1) these clocks can be provided from iq line s, global clock networks, or dedicated local refclks . 1 figure 3?40 shows the same input refe rence clocks connected to both the tx plls and rx plls. if you enable the channel and cmu pll reconfiguration option for a full-duplex configuration, you cannot provide separate reference clocks to the tx plls and rx plls. when you use the global clock line to provide input reference clocks, be aware of the following restrictions and implications: the hardware allows only one glob al clock input for the two tx plls in a transceiver block (refer to figure 3?39 ). in a receiver-only channel configur ation, the rx pll of each channel in a transceiver block can be clocke d by an independent global clock line. but, if you connect different clock input pins to the rx pll in each channel, you cannot reus e the mifs between these two channels. this constraint is explained further in ?input reference clock requirements for reusing mifs? on page 3?94 . each global clock line consumes a local route input output (lrio) resource. since each transceiver block has a fixed lrio resource, using the global clock line may rest rict the number of clocks you can provide to the transceiver channels in your design. pll_inclk_rx_cruclk[4:0] (1) 4 3 2 1 0 clock multiplier unit full duplex transceiver channel tx channel rx channel txpll0 txpll1 clock mux clock mux logical tx pll select local divider digital + analog logic rx pll digital + analog logic clock mux
3?92 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration f for more information on lrio reso urce limitation, refer to the pld clock resource section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook . using dedicated refclks when you use dedicated refclks as input reference clocks, the refclk pre-divider is required if one of the following conditions is satisfied: 1. if the input clock frequenc y is greater than 325 mhz. 2. for functional modes with a data ra te less than 3.125 gbps (the data rate is specified in the what is the data rate? option in the general tab of the alt2gxb megawizard). the txpll and rxpll is configured with the data rate that you set in this option. if the input clock frequency is greater than or equal to 100 mhz and if the ratio of data rate to input clock frequency is 4, 5, or 25 3. for functional modes with an data rate greater than 3.125 gbps: if the input clock frequency is greater than or equal to 100 mhz and if the ratio of data rate to input clock frequency is 8, 10, or 25 when you use the channel and cmu pll reconfiguration feature, you can dynamically reconfigure the tx plls and the rx pll in a transceiver block from any of the five available input reference clocks. the quartus ii software automatically instantiates the refclk pre-divider (if one of the above mentioned conditions is satisfied) for the clock sources that drive the main and alternate tx pll. 1 you specify the information for main and alternate tx pll in the general and reconfig alt pll tabs, respectively. for the other clock inputs, the alt2gxb megawizard provides optional options in the reconfig clks 1 and reconfig clks 2 tabs to specify whether a refclk pre-divider should be inst antiated by the quartus ii software. the available options are: a. what is the reconfig pr otocol driven by clock x? (?x? can be 0, 1, 2, 3, 4) b. what is clock x input frequency? c. use clock x reference clock divider?
altera corporation 3?93 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration for specific option values in a and b (mentioned above), the quartus ii software automatically instantiates the refclk pre-divider (field c is automatically selected in the alt2gxb megawizard). for example, when you select the pci express (pipe) option in the what is the reconfig protocol driven by clock0 field, the quartus ii software automatically instantiates the refclk pre-divider for clock source 0. when you select values in a and b (mentioned above) for a clock source and if field c is enabled, determine whether the data rate or the input clock frequency for the clock input meets one of the three conditions mentioned above. if one of the co nditions is met, select field c . for example, if you intend to use clock source1 to reconfigure the channel to basic mode with a 100 mhz input reference clock and a data rate of 2500 mhz, clock source1 satisfies condition 2 mentioned above. in the reconfig clk 1 tab, set the following values for clock source1 : set the what is the reconfig pr otocol driven by clock1? option to basic set the what is clock 1 input frequency? option to 100 mhz select the use clock1 reference clock divider? option (this enables the quartus ii software to instantiate the refclk pre-divider for clock source1 ). you can also use a dedicated refclk input pin from an unused transceiver block. if the quartus ii so ftware creates a pre-divider for this clock input, it automatic ally feeds the output of the pre-divider to the tx plls and rx plls of other transceiver blocks. the refclks do not use the lrio resource. f refer to figure 2?4 in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx de vice handbook for more information . 1 the refclk pre-divider is not part of the information stored in the mif. it is a static setting created during the alt2gxb megawizard configuration. the above mentioned clocking scheme also determines whether you can reuse the mif across all transceiver channels in your device. in the following section, the clocking requ irements to reuse mifs are discussed.
3?94 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration input reference clock requirements for reusing mifs the mif contains information about the input clock multiplexer and the functional blocks that you select ed during the alt2gxb megawizard instantiation. the quartu s ii software generates a mif for each channel. this mif can be used in any of the other channels in the device if you satisfy the following two requiremen ts for the input reference clocks: the order of the clock inputs mus t be consistent. for instance, assume that a mif is generated fo r a transceiver channel in bank 13 and the clock source is connected to the pll_inclk_rx_cruclk[0] port. when the generated mif is used in a channel in other transceiver blocks (for example, bank 14), the same clock source needs to be connected to the pll_inclk_rx_cruclk[0] port. figures 3?41 and 3?42 show the incorrect and correct order of inpu t reference clocks, respectively. in figure 3?41 , the clocking is incorrec t to reuse the mif because the input reference clock is n ot connected to the corresponding pll_inclk_rx_cruclk[] ports in the two instances. figure 3?41. incorrect input reference clock connection to reuse the mif 156.25 mhz clock source stratix ii gx device bank 13 alt2gxb instance 1 bank 14 alt2gxb instance 2 156.25 mhz pll_inclk_rx_cruclk[0] iq lines or global clock network pll_inclk_rx_cruclk[0] pll_inclk_rx_cruclk[1] pll_inclk_rx_cruclk[1] 125 mhz clock source 125 mhz
altera corporation 3?95 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?42. correct input reference clock connection to reuse the mif if you connect the input reference clock ports of the alt2gxb instances through different input pins, you cannot reuse the mif generated between these two instances, even if you provide the same clock frequency on these two pins. for example, in figure 3?43 the clock source provides 156.25 mhz clock to instance1 and instance2 through two different pins. in this case, if you generate a mif for instance1, you cannot reuse it in instance2. when you try to reconfigure us ing the mif for instance1 in a transceiver block (for example, bank 13) on instance2 in another transceiver block (for example, bank 14), the reconfig controller remaps the clock input multiplexer information in the mif (generated for instance1) to correspond to instance2. during this translation process, it assumes that the same clock input is connected to the pll_inclk_rx_cruclk[] port. therefore, the reconfig controller selects the clock multiplexer value for the iq line or global clock networ k that connects to the clock input of instance1. if you want to reuse the mif, connect the clock source to only one clock pin in the device. in your design, co nnect the clock input port of your transceiver instances to that cloc k pin. the quartus ii software automatically routes the clock input to all the tran sceiver blocks through iq lines or global cloc k routing resources, depending on whether you 156.25 mhz clock source stratix ii gx device bank 13 alt2gxb instance 1 bank 14 alt2gxb instance 2 156.25 mhz pll_inclk_rx_cruclk[0] iq lines or global clock network pll_inclk_rx_cruclk[0] pll_inclk_rx_cruclk[1] pll_inclk_rx_cruclk[1] 125 mhz clock source 125 mhz
3?96 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration selected a dedicated refclk pin or a clock i/o pin. figure 3?43 shows the incorrect clocking scheme. figure 3?44 shows the correct clocking scheme. figure 3?43. incorrect clocking scheme to reuse mif figure 3?44. correct clocking scheme for reusing mif clock source stratix ii gx device alt2gxb instance 1 bank 13 alt2gxb instance 2 bank 14 refclk0 156.25 mhz pll_inclk_rx_ cruclk[0] pll_inclk_rx_ cruclk[0] 156.25 mhz refclk0 two different clock pins clock source stratix ii gx device alt2gxb instance 1 bank 13 alt2gxb instance 2 bank 14 refclk0 156.25 mhz pll_inclk_rx_ cruclk[0] pll_inclk_rx_ cruclk[0] iq lines or global clock network
altera corporation 3?97 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration general guidelines for specifying the input reference clocks the following are general guidelines for your input reference clocks: assign the identification numbers to all input reference clocks that are used in the design (0, 1, 2, 3, and 4). the identification numbers are indicated by ?a? in figure 3?45 . keep the identification numbering consistent for all the subsequent mif configurations. provide the iden tification numbers indicated by ?b? and ?c? in figure 3?45 . maintain a consistent protocol, in put reference clock frequencies, and reference clock pre-divider settings for all the mif. set these options indicated by ?d?, ?e?, and ?f? in figure 3?45 . these fields are explained in detail in ?alt2gxb megawizard settings? on page 3?113 . figure 3?45. input clock settings of the reconfig clks 1 tab
3?98 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration logical tx pll in the channel reconfiguration feature ( ?channel reconfiguration? on page 3?30 ), you cannot reconfigure the tx plls dynamically. it was not necessary to know which of the two tx plls was configured for the specified data rate. you were required to set only the logical reference index option in the alt2gxb megawizard to select the output clocks of the main and alternate txplls and the clock mux in the rx pll side (refer to figure 3?40 for the location of these multiplexers). when you use the channel and cmu pll reconfiguration option, you can dynamically reconfigure the channel and the tx pll. therefore, to reconfigure the tx pll during run time, you need the flexibility to select the tx pll. when you enable this option, the alt2gxb megawizard provides a logical identification for the main and alternate txplls. this identification is referred to as the ?logical tx pll? value. this value provides a logical identification to the tx pll that is associated with a transceiver channel, without requir ing the knowledge of its physical location. in the alt2gxb megawizard, when you provide the main txpll with a logical tx pll value, for example 0 , the alternate txpll automatically takes the complement value 1 . the logical tx pll value for the main txpll is stored along with the other tran sceiver channel information in the generated mif. you can reuse the mif generated for one tx pll to reconfigure the other tx pll in the sa me or in other transceiver blocks. the dynamic reconfig controller provides you an optional logical_tx_pll_sel port for this purpose. the method to use this port and reconfigure a tx pll is explained in ?logical tx pll? on page 3?98 . using the channel and cmu pll reconfiguration feature the channel and cmu pll reconfiguration feature is divided into three categories based on the functionality: channel and tx pll reconfiguration tx pll reconfiguration channel reconfiguration with tx pll select
altera corporation 3?99 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration you can select these features by setting the appropriate values in the reconfig_mode_sel port of the alt2gxb reconfig tab. table 3?9 shows the reconfig_mode_sel values for all the dynamic reconfiguration features. 1 the read operation is valid only for the reconfig_mode_sel value 000 . do not use read for any other modes. ensure that the reconfig_mode_sel port is set to the above mentioned supported values only. setting the reconfig_mode_sel port to non-supported values may yi eld unpredictable transceiver behavior. when the enable adaptive eq ualization control option is enabled, the reconfig_mode_sel port is 4-bits wide. in this case, set the most significant bit (msb) of the reconfig_mode_sel to 0 when you use any of the above mentioned values. as with the channel reconfiguration feature, the reconfig controller automatically increments the reconfig_address_out values to read the appropriate words from the mif memory. table 3?10 shows the address values incremented by the re config controller for the different features. table 3?9. reconfig_mode_sel values for all dynamic reconfiguration modes reconfig_mode_sel[2:0] description 000 pma controls 001 channel reconfiguration 010 not supported (do not attempt to read or write with this value) 011 dynamic transmit rate switch 100 tx pll 101 channel and tx pll reconfiguration 110 channel reconfiguration with tx pll select 111 not supported (do not attempt to read or write with this value) table 3?10. address incremented by the reconfig controller (part 1 of 2) reconfig_mode_sel[2:0] i ncremented address 001 (channel reconfiguration) 0-27 100 (tx pll only) 0, 28-37
3?100 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration the procedure to write the mif contents to the transceiver is the same as in with the channel reconfiguration feature (refer to figure 3?8 on page 3?28 ). channel and tx pll reconfiguration the channel and tx pll reconfigur ation mode reconfigures the transceiver channel and the tx pll that provide high-speed clocks to the transceiver channel. this mode helps to switch across multiple protocols that require different data rates an d functional blocks. since the tx pll is also reconfigured when you use this feature, all the channels that are listening to the tx pll are affected. to perform channel and tx pll configuration, set the reconfig_mode_sel to 101 and write the mif contents. during reconfiguration, th e reconfig controller powers down the selected logical tx pll until the new values are updated. the power down feature is explained in ?tx pll powerdown? on page 3?109 . to illustrate the functional blocks that are reco nfigured, the following example is used. this same example is used for the three reconfiguration features. consider that you have an alt2gxb instantiation with the following default configuration: the full-duplex channel with the main txpll configured to 5 gbps data using a 156.25 mhz reference clock. the alte rnate txpll is configured to 2.5 gbps using a 125 mhz reference clock ( figure 3?46 shows the default configuration). assume that the logical tx pll value is set to 0 for the main txpll. (the settings to select the logical tx pll value for the tx plls are discussed in ?alt2gxb megawizard settings? on page 3?113 ). 101 (channel and tx pll reconfiguration) 0-37 110 (channel reconfiguration with tx pll select) 0-27 table 3?10. address incremented by the reconfig controller (part 2 of 2) reconfig_mode_sel[2:0] i ncremented address
altera corporation 3?101 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?46. transceiver channel default configuration consider that you intend to switch to the following two modes: mode1: full-duplex channel with the main txpll configured to 6.25 gbps data using a 156.25 mhz referenc e clock. assume that the logical tx pll is set to 0 for the main txpll. rate matcher is not enabled in the alt2gxb megafunction. the alternate txpll is configured to 2.5 gbps using a 125 mhz reference clock. mode2: full-duplex channel with the main txpll configured to 5 gbps data using a 156.25 mhz reference clock. as sume that the logical tx pll is set to 0 for the main txpll. rate matcher is enabled in the alt2gxb megafunction. the alternate txpll is configured to 2.5 gbps using a 125 mhz reference clock. consider that the mif is generated for mode1 and mode2. (details on the steps to generate the mif are covered la ter in this section. the intent of this example is to show how the functi onal blocks are reconfigured based on the feature used). /1 pll_inclk_rx_cruclk[1] 156.25 mhz 125 mhz pll_inclk_rx_cruclk[0] clock multiplier unit 5 gbps logical txpll0 2.5 gbps logical txpll1 clock mux clock mux full duplex transceiver channel tx channel rx channel 5 gbps digital + analog logic local divider logical tx pll select clock mux 5 gbps rx pll 5 gbps digital + analog logic
3?102 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration figure 3?47 shows the functional blocks that are reconfigured after the dynamic reconfig controller writes the mode2 mif. note that on the receive side, the rate matcher gets en abled after reconfiguration since the mode2 mif contains settings to enable the rate matcher block. figure 3?47. reconfigured functiona l blocks after the channel and tx pll reconfiguration tx pll reconfiguration using the tx pll reconfiguration mode, you can reconfigure the tx plls. this mode is very useful in saving reconfiguration time in certain applications. cons ider that you have four transmit-only instances in the same transceiver block that sw itch to different data rates together (assuming that the functional blocks are the same across the data rates). in this case, all these channels can listen to the same tx pll. instead of using the channel and tx pll reconfiguration option (write 38 words) for individual channels, you can configure the tx pll (write 10 words) once, to a different data rate. this, in turn, changes the transmit data rate of all the channels listening to this tx pll. this mode is also useful when combined with the channel reconfiguration with tx pll select mode. when the channel is listening to one tx pll, you can reconfigure th e other tx pll, and later switch the transmit channel to listen to the co nfigured tx pll (explained in ?channel reconfiguration with tx pll select? on page 3?103 ). /1 pll_inclk_rx_cruclk[1] 156.25 mhz pll_inclk_rx_cruclk[0] 125 mhz clock multiplier unit clock mux clock mux 6.25 gbps logical txpll0 2.5 gbps logical txpll1 reconfigured functional blocks after mif write rate matcher enabled rx channel 6.25 gbps rx pll clock mux 6.25 gbps digital + analog logic 6.25 gbps digital + analog logic full duplex transceiver channel tx channel logical tx pll select local divider
altera corporation 3?103 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration to perform tx pll reconfiguration, set the reconfig_mode_sel value to 100 and write the mif contents. th e dynamic reconfig controller automatically increments the values on the reconfig_address_out port to word 0 and 28 through 37 from the specified mif. the words 28-37 contain information to reconfigure th e tx pll. during reconfiguration, the reconfig controller powers down the tx pll until the new values are written. to understand the functional blocks that get reconfigured by this mode, consider the same example mentioned in ?channel and tx pll reconfiguration? on page 3?100 . figures 3?46 and 3?48 show the conditions before and after reconf iguration (using the mode1 mif), respectively. 1 all the channels listening to the configured tx pll are affected due to this reconfiguration. figure 3?48. reconfigured functi onal blocks after tx pll-only reconfiguration channel reconfiguration with tx pll select this option reconfigures the channel and the logical tx pll select multiplexer (shown in figure 3?49 ) that selects the clock output from one of the tx plls. to use this feature, set the reconfig_mode_sel value to 110 and write the mif contents. the channel reconfiguration with tx pll select option, in combination with the tx pll reconfiguration /1 pll_inclk_rx_cruclk[1] 156.25 mhz pll_inclk_rx_cruclk[0] 125 mhz clock multiplier unit clock mux 6.25 gbps logical txpll0 2.5 gbps logical txpll1 clock mux reconfigured functional blocks after mif write logical tx pll select local divider 6.25 gbps digital + analog logic full duplex transceiver channel tx channel rx channel 5 gbps rx pll 5 gbps digital + analog logic clock mux
3?104 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration option, is useful to switch the tx ch annel to multiple data rates. when the transmit side is using one tx pll, reconfigure the second tx pll using the tx pll reconfiguration feat ure. then, use the channel reconfiguration with tx pll select feature to switch the logical tx pll select multiplexer to listen to the reconfigured tx pll. this feature may require you to use the optional logical_tx_pll_sel port available in the alt2gxb reconfig tab. the function of this port is explained in ?logical tx pll? on page 3?98 . consider the same example mentioned in ?channel and tx pll reconfiguration? on page 3?100 (refer to figure 3?46 for conditions before reconfiguration). figure 3?49 shows the reconfigured functional blocks after the mode1 mif write is co mpleted. note that the tx plls are not reconfigured. since the new mif has the same functional blocks as the original configuration, there is no ch ange in the function al blocks or the data rate in the transmit side afte r reconfiguration. note that the mif configures the rx pll to 6.25 gbps. figure 3?49. reconfigured functional blocks after channel and tx p ll select reconfiguration /1 clock mux clock mux pll_inclk_rx_cruclk[1] 156.25 mhz 125 mhz pll_inclk_rx_cruclk[0] clock multiplier unit 5 gbps logical txpll0 2.5 gbps logical txpll1 clock mux rx channel 6.25 gbps rx pll 6.25 gbps digital + analog logic full duplex transceiver channel tx channel logical tx pll select local divider 5 gbps digital + analog logic reconfigured functional blocks after mif write
altera corporation 3?105 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration logical tx pll select you can reuse the mif created for one tx pll on the other tx pll using the optional logical_tx_pll_sel port in the alt2gxb_reconfig megawizard. if the logical_tx_pll_sel port is enabled, the reconfig controller uses the value on this port ir respective of the logical tx pll value contained in the mif. by using this port, you specify the identity of the tx pll that you intend to reconfigure. if you want to use the logical_tx_pll_sel only under some conditions and use the logical tx p ll value stored in the mif otherwise, enable an additi onal optional logical_tx_pll_sel_en port. if this port is enabled, the dynamic reconfig controller uses the value on the logical_tx_pll_sel port only if the logical_tx_pll_sel_en port is set to 1 (refer to figure 3?50 ). the values on th ese two ports should be held at a constant logic level until reconfiguration is completed. table 3?11 shows the selected logical_tx_pll value under all the combinations of these two signals. figure 3?50. effect of using logical_tx_pl l_sel and logical_tx_pll_sel_en ports table 3?11. logical_tx_pll_sel and logica l_tx_pll_en combinations (part 1 of 2) logical_tx_pll_sel port logical_tx_pll_se_en port selected logical tx pll value by the reconfig controller enabled enabled - value high value on the logical_tx_pll_sel port. enabled enabled - value zero logical tx pll value stored in the mif. 0 1 logical tx pll information in the mif logical_tx_pll_sel reconfig controller selected logical tx pll value logical_tx_pll_sel_en
3?106 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration when you configure a transceiver channel in the alt2gxb megawizard, altera recommends that you keep track of the tx pll that drives the channel. you may require this inform ation when you want to reconfigure the tx plls dynamically. this is illustrated in ?design examples? on page 3?121 . 1 the logical_tx_pll_sel port does not modify any transceiver setting on the rx side. figure 3?51 shows the required signal transitions to reconfigure the tx pll with a logical_tx_pll value of 1 . keep the logical_tx_pll_sel and logical_tx_pll_sel_en signals at a constant logic level until the reconfig controller asserts the channel_reconfig_done signal. figure 3?51. signal transitions of the logical_tx_pll_sel and logical_tx_pll_sel_en ports enabled not enabled value on the logical_tx_pll_sel port. not enabled not enabled logical tx pll value stored in the mif. table 3?11. logical_tx_pll_sel and logica l_tx_pll_en combinations (part 2 of 2) logical_tx_pll_sel port logical_tx_pll_se_en port selected logical tx pll value by the reconfig controller 101 logical_tx_pll_sel_en reconfig controller does not register the logical_tx_pll_sel value for this write since the logical_tx_pll_sel_en is low logical_tx_pll_sel write_all channel_reconfig_done reconfig_mode_sel
altera corporation 3?107 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration for illustration, the same example and mif specified in the ?channel and tx pll reconfiguration? on page 3?100 is used here. the results of the reconfiguration under all the channel and cmu pll reconfiguration modes are shown below. these result s were achieved during run time, with the logical_tx_pll_sel input of the dynamic reconfig controller set to 1 (assuming the logical_tx_pll_sel_en is tied to 1 ) and using the mode1 or mode2 mif. channel and tx pll reconfiguration refer to figure 3?46 for the channel configuration before the mif write. figure 3?52 shows the conditions after the channel is reconfigured using the mode2 mif and setting the logical_tx_pll_sel to 1 during reconfiguration. figure 3?52. reconfigured functional blocks using logical_tx_pll_ sel in channel and tx pll mode tx pll reconfiguration refer to figure 3?46 for the channel configuration before the mode1 mif is written. figure 3?53 shows that the logical txpll1 is configured to 6.25 gbps. the transmit channel still listens to the logical txpll0 and therefore runs at 5 gbps (since in this mode, the logical tx pll select mux is not reconfigured). the receive side is not configured with this feature. /1 pll_inclk_rx_cruclk[1] 156.25 mhz pll_inclk_rx_cruclk[0] 125 mhz clock mux clock mux clock multiplier unit 5 gbps logical txpll0 6.25 gbps logical txpll1 full duplex transceiver channel tx channel rx channel logical tx pll select local divider 6.25 gbps digital + analog logic rate matcher enabled clock mux 6.25 gbps rx pll 6.25 gbps digital + analog logic reconfigured functional blocks after .mif write
3?108 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration figure 3?53. reconfiguration func tional blocks usi ng logical_tx_pll_sel in tx pll mode channel reconfiguration with tx pll select refer to figure 3?46 for the channel configuration before the mode1 mif is written. figure 3?54 shows the blocks that are reconfigured by the mode1 mif and the logical_tx_pll_sel set to 1 . note that in this case, the tx pll is not configured. af ter the mif is written, the logical tx pll multiplexer gets configured to select the logical txpll1. /1 pll_inclk_rx_cruclk[1] pll_inclk_rx_cruclk[0] 156.25 mhz 125 mhz clock multiplier unit clock mux clock mux 5 gbps logical txpll0 6.25 gbps logical txpll1 full duplex transceiver channel logical tx pll select local divider 5 gbps digital + analog logic tx channel rx channel 5 gbps rx pll 5 gbps digital + analog logic clock mux reconfigured functional blocks after mif write
altera corporation 3?109 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?54. reconfigured functi onal blocks using logical_tx_pll_se l in channel reconfiguration with tx pll select you should keep the transceive r channel under reset during reconfiguration. therefore, the channel may not be able to receive or transmit user data during reconfiguration. you can use a mif generated for one channel to all the other channels in the device if you meet the clocking requirements mentioned in ?clocking enhancements and requ irements? on page 3?90 . tx pll powerdown during channel and tx pll reconfiguration or tx pll reconfiguration, the dynamic reconfig controller automatically powers down the selected tx pll until it completes reconfiguring the selected tx pll. the alt2gxb_reconfig megafunction does not provide any external ports to control the tx pll power down. if you reconfigure the main txpll, the pll_locked signal goes low. if you reconfigure the alternate txpll, the pll_locked_alt signal gets deasserted. therefore, after reconfiguring the transceiver, wait for the pll_locked or pll_locked_alt signal from the alt2gxb megafunction (depending on the tx pll that is reconfigured) before continuing normal operation. 1 the dynamic reconfig controller powers down only the selected tx pll. the other tx pll is not affected. /1 reconfigured functional blocks after .mif write pll_inclk_rx_cruclk[1] pll_inclk_rx_cruclk[0] 156.25 mhz 125 mhz clock mux clock mux 5 gbps logical txpll0 2.5 gbps logical txpll1 clock multiplier unit full duplex transceiver channel tx channel rx channel logical tx pll select local divider 2.5 gbps pcs + pma clock mux 6.25 gbps rx pll 6.25 gbps digital + analog logic
3?110 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration 1 the main txpll corresponds to the tx pll configuration set in the general tab of the alt2gxb megawizard and the alternate txpll corresponds to the reconfig alt pll tab. channel and cmu pll reconfiguration duration the dynamic reconfig controller take s the following number of reconfig clock cycles to write th e contents in the mif: words 0 to 27 - approximately 260 clock cycles per word words 28 to 37 - approximately 521 clock cycles per word reset recomm endations altera recommends that you follow a proper reset sequence during and after cmu pll reconfiguration. figure 3?55 shows the recommended reset sequence. figure 3?55. reset sequence during and after cmu p ll reconfiguration (1 > 2 > 3 > 4 > 5) as shown in figure 3?55 , assert the tx_digitalreset , rx_digitalreset and rx_analogreset when you initiate the cmu pll reconfiguration mif writes. after the dynamic reconfiguration control completes the cmu pll reconfiguration, it asserts the channel_reconfig_done signal. after the channel_reconfig_done signal goes high, wait for pll_locked and pll_locked_alt (if you are using the alternate pll) to go high (as channel_reconfig_done tx_digitalreset rx_analogreset rx_digitalreset rx_freqlocked 3 3 4 5 output status signals 1 2 pll_locked_alt pll_locked_final pll_locked t = 4us
altera corporation 3?111 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration represented by pll_locked_final ) and then de-assert the tx_digitalreset and rx_analogreset signals. wait for a minimum of 4 s after the rx_freqlocked signal goes high, then de-assert the rx_digitalreset signal. quartus ii settings and requirements the quartus ii software version 7.1 provides new assignments and settings to support the above mentioned channel and cmu pll reconfiguration features. mif generation for channel and cmu pll reconfiguration to enable the quartus ii software version 7.1 to generate a mif with 38 words, complete the following steps: 1. go to the assignments menu and select settings , then fitter settings . 2. click the more settings button and set the generate stratix ii gx gxb reconfig mif with pll option to on using the settings option (as shown in figure 3?56 ).
3?112 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration figure 3?56. quartus ii setting for mif generation grouping transceiver channels the quartus ii software version 7.1 requires the following assignment editor setting for all channels assi gned to the same transceiver bank, when you enable the channel and cmu pll reconfiguration option. assignment setting: assignment name - stratix ii gx gxb tx pll reconfig group setting (as shown in figure 3?57 ). if you have more than one channel with the channel and cmu pll reconfiguration feature enabled, and if you assign them to different reconfig groups without pin assignments for the tx_dataout pins, the quartus ii software autom atically assigns these channels to different transceiver blocks. if you use a strati x ii gx device with one transceiver block, you cannot compile the design if you assign different tx pll reconfig group values for the channels in your design.
altera corporation 3?113 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?57. reconfig group setting required fo r channel and cmu pll reconfiguration to understand the usage of this assi gnment setting, assume that you have two transmit channels in the sa me transceiver bank with the channel and cmu pll reconfiguration option enabled. if th e transmit output pins are tx_dataout_ch0 and tx_dataout_ch1 , set the following assignment setting to compile the design: to : tx_dataout_ch0 assignment name: stratix ii gx gxb tx pll reconfig group setting value : 0 to : tx_dataout_ch1 assignment name: stratix ii gx gxb tx pll reconfig group setting value : 0 alt2gxb megawizard settings this section discusses the enhancements in the alt2gxb megawizard to support the channel and cmu pll reconfiguration feature. reconfig tab settings when you enable the channel internals field, you can select the enable channel and transmitter pll option (shown in figure 3?58 ). this option allows you to use the channel and cmu pll reconfiguration feature. when you select this option, th e alt2gxb megawizard enables new tabs? reconfig_alt_pll , reconfig clks 1, and reconfig clks 2 ?to differentiate the settings for this feature from those of the channel reconfiguration feature (introduced in the quartus ii software version 6.1). this helps to maintain backwa rd compatibility with the channel reconfiguration feature.
3?114 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration 1 when you select the enable channel an d transmitter pll reconfiguration option, you cannot select the use alternate reference clock option (used in channel reconfiguration feature). these two fields are mutually exclusive. figure 3?58. reconfig tab
altera corporation 3?115 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration reconfig alt pll tab settings when you select the use alternate transmitter and receiver pll option, you can set the logical tx pll value to 0 or 1 for the alternate txpll from the what is the alternate pll logical reference index? option ( figure 3?59 ). figure 3?59. reconfig alt pll tab reconfig clks 1 tab this tab provides options for the inpu t reference clocks. the first option, what is the main pll logical reference clock index , provides the logical tx pll value for the main txpll. if you have enabled the alternate txpll in the reconfig alt pll tab, the alt2gxb megawizard automatically selects the logical tx pll value of the main txpll as the complement of the alternate txpll. otherwise, you can sele ct the logical tx pll value for the main txpll in this tab (at the what is the main pll logical reference clock index? option in figure 3?60 ).
3?116 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration figure 3?60. reconfig clks 1 tab the how many input clocks? option in figure 3?60 shows the number of input reference clocks. wh en you set this field to 5 , the alt2gxb megawizard provides a reconfig clks 2 tab to specify information about additional clock inputs. the what is the selected input clock source for the transmitter pll and receiver pll? and what is the selected input clock source for the alternate tr ansmitter pll and receiver pll? options are used to select the input clocks for the main and alternate txplls as well as the rx plls. the what is the reconfig protocol driven by clock 0? and what is clock 0 input frequency? options provide the protocol and clock frequency options for other clock sources that you anticipate you will use in your design. for additional information on the input clock requirements, refer to ?clocking enhancements and requirements? on page 3?90 .
altera corporation 3?117 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration based on your settings in thes e fields, the alt2gxb megawizard determines whether the refclk pre-divider should be enabled. for example, if you select the sonet/sdh oc-12 protocol in the what is the reconfig protocol driven by clock0 option, the alt2gxb megafunction automatically enables the refclk pre-divider and connects the output of the pre-divider to the input referenc e clock port of the tx plls and rx plls. similarly, if you select the input clock frequency greater than 325 mhz, the refclk pre-divider is enabled. when you select the use clock 0 reference clock divide r option, the quartus ii software instantiates the refclk pre-divider for the clock input. if the information provided in the general and reconfig alt pll tabs meet one of the conditions specified in ?using dedicated refclks? on page 3?92 , the quartus ii software au tomatically instantiates the refclk pre-divider for the corresponding cloc k input. for other clock inputs, you should determine whether the clock input frequency and the data rate meets one of the conditions specified in ?using dedicated refclks? on page 3?92 . example of a condition to select this option: assume that you are using a clock in put with a 125 mhz to configure the tx pll to run the channel at the 3.125 gb ps data rate. in this case, the ratio of tx pll data rate to inpu t clock frequency is 25. this meets condition 2 specified in ?using dedicated refclks? on page 3?92 . therefore, select this option so that the quartus ii software instantiates the refclk pre-divider for this clock source. 1 when the quartus ii software creates a pre-divider for a dedicated input reference clock ( refclk ), only the output of the pre-divider is available to clock the tx pll and /or rx pll. 1 if you would like to reuse the mif across transceiver channels, you must have the same order of clock inputs across all the alt2gxb instantiations that are using this mif.
3?118 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration figure 3?61 shows the mapping of the megawizard settings marked by ?a?, ?b?, ?c?, and ?d? with the actual settings in the hardware (refer to figure 3?60 for the reconfig clks 1 tab). figure 3?61. mapping between the megawizard settings and hardware settings the other settings in the alt2gxb megawizard are not specific to the channel and cmu pll reconfiguration fe ature. therefore, the other tabs are not discussed in this section. f refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about other alt2gxb megawizard settings. alt2gxb reconfig tab settings the quartus ii software version 7.1 has the following enhancements in the ports/values option in the alt2gxb_reconfig megawizard. reconfig_mode_sel : the alt2gxb_reconfig megawizard has new reconfig_mode_sel values to support the channel and cmu pll reconfiguration option. for a complete list of reconfig_mode_sel values, refer to table 3?9 . 0 1 2 3 4 b a c c d pll_inclk_rx_cruclk[4:0] clock mux clock mux main txpll alternate txpll clock multiplier unit full duplex transceiver channel tx channel rx channel logical tx pll select local dividers digital + analog logic clock mux rx pll digital + analog logic
altera corporation 3?119 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration logical_tx_pll_sel : the logical_tx_pll_sel port is optional. you can select this port in the channel and tx pll reconfiguration tab. the value set in this port during reconfiguration overrides the logical tx pll value stored in the mif. refer to ?logical tx pll select? on page 3?105 for more information. logical_tx_pll_sel_en : the logical_tx_pll_sel_en port is optional. you can select this port in the channel and tx pll reconfiguration tab. if this port is selected, the alt2gxb_reconfig block re gisters the value on the logical_tx_pll_sel only if the logical_tx_pll_sel_en is asserted. figure 3?62 shows the channel and tx pll reconfiguration tab in the alt2gxb_reconfig megawizard in the quartus ii software version 7.1. figure 3?62. alt2gxb reconfig tab the functionality of all other signals, such as write_all , channel_reconfig_done , reconfig_address_en , logical_channel_address , data_valid , and busy , have not changed since quartus ii software vers ion 6.1. to write the mif, follow the method used for the channel reconfiguration feature. refer to figure 3?8 on page 3?28 for more information.
3?120 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration merging transceiver channels with dynamic reconfiguration enabled the following are the quartus ii soft ware version 7.1 requirements for merging multiple transceiver channels that have the channel and cmu pll reconfiguration option selected in the same transceiver bank: assign all the channels to the same reconfig group. refer to ?quartus ii settings and requirements? on page 3?111 for more information on the reconfig group setting. all the channels should have the sa me reconfig options. that is, if you select pma controls , channel interface , or channel internals in one channel, all the other channels should have the same selection. some of the other scenarios for merging channels in the same transceiver bank are discussed below. case 1: merging transceiver channels listening to two tx plls consider that you create an alt2gxb instantiation for a full-duplex or tx-only configuration that has a main and alternate txpll. if you want to place other channels in the same transceiver bank, the other channels should also have a main and alternate txpll option to merge successfully. for example, consider that you create the following instantiation: instantiation1 ?one full-duplex channel with the main txpll (assume a logical_tx_pll value of 0 ), configured to 6.25 gbps data rate and the alternate txpll configured to 2.500 gbps. assume that you create another instantiation with the following configuration: instantiation2 ?one full-duplex channel with only one tx pll (assume a logical_tx_pll value of 0 ), configured to 6.25 gbps. in this case you cannot merge instan tiation1 and instantiation2 in the same transceiver bank since instantiation2 listens to only one tx pll. to successfully merge the two instances, create instantiation2 with an alternate txpll configured to 2.500 gbps. case ii: merging transceiver channels listening to one tx pll consider that you create an alt2xb instantiation (full-duplex or tx-only configuration) that has only one tx pll. if you would like to create another alt2gxb instantiation configured at a different data rate in the
altera corporation 3?121 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration same transceiver bank, provide differen t logical tx pll values for the two instantiations. for example, to merge the following instan tiations in the same transceiver bank: instantiation1 ?full-duplex channel configured at 3.125 gbps. instantiation 2 ?full-duplex channel configured at 2.500 gbps. if you set the what is the main pll logical reference clock index (in the reconfig clks 1 tab) for instantiation1 to 0 , set this option to 1 for instantiation2. since the quartus ii software requires separate tx plls for these two channels, the two inst antiations should have different logical tx pll values. case iii: merging separate transmit-o nly and receive-only instantiation in a full-duplex configuration with the channel and cmu pll reconfiguration option enabled, the software automatically connects the same reference clock input to the tx pll and rx pll (explained in ?clocking enhancements and requirements? on page 3?90 ). if you merge a transmit only and a receive only configuration, the quartus ii software allows you to provide separate cloc k inputs for the tx pll and rx pll (you can connect the pll_inclk_rx_cruclk[] port of the two instances to two different clock source). when you merge the transmit only and receive only configurations, you should add the stratix ii gx reconfig group setting in the assignment editor for the tx_dataout and rx_datain pins and assign the same value to these two pins ( 0 or 1 ). this setting enables the quartus ii software to create a single (combined) mif for the tx only and rx only instance. 1 using this merging method, yo u can provide separate clock inputs to the tx pll and rx pll. if you set the starting channel numbers in the alt2gxb megawizard for the tx instance to 0 and rx instance to 4 , you can use logical_channel_address in the reconfig controller set to 0 or 4 to perform channel and cmu pll reconfiguration on this transceiver channel. design examples this section covers the steps used in creating a design with the channel and cmu pll reconfiguration feature enabled.
3?122 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration case i: configuring transceiver channe ls to switch together between gige, sone-oc48, and fibre channel (fc)-4g protocols the gige, sonet/sdh oc48, and fc-4 g have different input reference clocks, data path, and clocking requ irements. for this example, assume the following stratix ii gx device configuration: three transceiver banks six full-duplex channels with two ch annels in each transceiver bank for a total of six channels (ch0 , ch1, ch2, ch3, ch4, ch5). each channel can independently switch between gige, sonet/sdh-oc48, and fc- 4g protocols. assume that all channels are conf igured to fc-4g protocol at system power up. fc-4g uses basic mode. fc-4g and fc-2g refer to the fibre channel protocol at 4.25 gbps and 2.125 gbps data rate, respectively. table 3?12 shows the different parameters and alt2gxb functional blocks for these three protocols. table 3?12. differences in functional blocks between gige, fibre channel, and sonet/sdh-oc48 note (1) parameters fibre channel (basic mode) 4.25 gbps gige 1.25 gbps sonet/sdh oc48 2.488 gbps selected input reference clock 106.25 mhz 125 mhz 77.76 mhz pld width 40 8 16 byte serializer/ byte deserializer yes no yes 8b/10b no yes no rate matcher no yes no byte order block yes no yes clock used for the receive side parallel interface rx_clkout tx_clkout (since rate matcher is used) rx_clkout note to table 3?12 : (1) the alt2gxb megawizard allows more options for the input reference clock. for this example, we have select ed the values shown in the table.
altera corporation 3?123 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration the differences between the thre e protocols determine the alt2gxb megawizard settings. figure 3?63 shows the top-level block diagram of the example design. figure 3?63. top-level block diag ram of the example design how many mifs do i require? for this example design, you can use one tx pll per channel since you require only two full-duplex channels in the transceiver bank. to switch between three protocols, you need th ree mifs. if you have consistent clocking across the three transceive r banks, you can reuse the same mif across all the channels in the device. figure 3?64 shows the clocking and tx pll connections only for ch0 and ch1 (ch2-ch3, ch4-ch5 have the same configuration). to simplify the illustration, only the transmit channels of ch0 and ch1 and th e tx pll connections are shown. if you create three mifs (for fc-4g, gige, and sonet/sdh oc48) for one tx pll, you can reuse the mi f in the other tx pll using the logical_tx_pll_sel port in the dynamic reconfig controller. this means that you do not need a sepa rate mif for ch1 (since the other tx pll is connected to ch1). similarly, the same method can be applied for all the other channels in this ex ample design. in total, you only need three mifs for this example design. user logic in the pld megawizard instantiation logic for the fibre channel, gige, and sonet data path reset control logic control logic for the reconfig controller fibre channel mif gige mif sonet mif alt2gxb instantiations of all the six channels alt2gxb_ reconfig
3?124 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration figure 3?64. tx pll connections to ch 0 and ch1 for the example design 1 the 4.25/1.25/2.48 gbps shown in figure 3?64 indicates the possible switched data rates for the tx pll to implement this example design. the following discus sion of the design is divided into five sections: section i?alt2gxb megawizard settings for the three protocols section ii?alt2gxb_reconfi g megawizard instantiation section iii?steps to create the mif section iv?reset control logic and user logic section v?top-level design and sram object file ( .sof ) generation section i? alt2gxb megawizard se ttings for the three protocols tables 3?13 , 3?14 , and 3?15 list the megawizard settings for each of the three protocols. pll_inclk_rx_cruclk[2] pll_inclk_rx_cruclk[1] pll_inclk_rx_cruclk[0] 77.76 mhz 125 mhz 106.25 mhz clock mux clock mux 4.25 gbps/ 1.25 gbps/ 2.48 gbps logical txpll0 4.25 gbps/ 1.25 gbps/ 2.48 gbps logical txpll1 tx side of ch1 tx side of ch0 table 3?13. fc-4g protocol settings (part 1 of 3) tab page and option setting general tab settings which protocol you will be using basic which sub protocol you wi ll be using serial loopback operation mode receiver and transmitter
altera corporation 3?125 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration what is deserializer block width double what is channel width 40 (8b/10b encoder/decoder in the alt2gxb is not used) what is the data rate 4250 mbps what is the input clock frequency 106.25 mhz what is the data rate division factor 1 select the rxdigitalreset , txdigitalreset , and rxanalogreset ports pll/ports tab settings select the gxb_powerdown , rx_freqlocked , pll_locked in the screen rx analog/cal blk tab settings select the calibration block select the cal_blk_powerdown if required tx analog tab setting select the appropriate settings based on your requirements reconfig tab settings select channel interface this is required since the three protocols require different pld widths (refer to table 3?12 ). select channel internals and enable channel and transmitter pll reconfiguration reconfig alt pll tab setting in this example design, you are using only two channels in the transceiver block. since there are two tx plls per transceiver block, use one tx pll for each channel and reconfigure the same tx pll to switch across protocols. therefore, you do not need an alternate txpll for this instance. reconfig clks 1 tab settings what is the main pll logical reference clock index 0 table 3?13. fc-4g protocol settings (part 2 of 3) tab page and option setting
3?126 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration how many input clocks 3 (77.76 mhz, 125 mhz, and 106.25 mhz). assume: clock2 = 77.76 mhz clock1 = 125 mhz clock0 = 106.25 mhz what is the select input clock source for transmitter and receiver pll 0 what is the reconfig protocol driven by clock1 gige what is clock1 input frequency 125 mhz use clock 1 reference clock di vider do not check this option what is the reconfig protocol driven by clock2 sonet/sdh what is clock2 input frequency 77.76 mhz use clock 2 reference clock di vider do not check this option reconfig2 tab settings how should the receivers be clocked select use respective core clocks since you clock the receive parallel date with tx_clkout for the gige protocol and rx_clkout for the other two protocols. refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for more information about these options. how should the transmitters be clocked u se the respective channel transmitter core clocks. check the control box to use the corresponding control port select the protocol-specific signals. for sonet/sdh, you need rx_byteorderalignstatus , rx_ala2sizeout , etc. refer to the stratix ii gx alt2gxb megafunction user guide chapter in volume 2 of the stratix ii gx device handbook for more information. basic1 and basic2 tab setting select the word alignment and other ports based on your requirements and complete the megawizard table 3?13. fc-4g protocol settings (part 3 of 3) tab page and option setting
altera corporation 3?127 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration . table 3?14. gige protocol settings (part 1 of 2) tab page and option setting general tab settings which protocol you will be using gige operation mode receiver and transmitter what is the input clock frequency 125 mhz select the rxdigitalreset , txdigitalreset , and rxanalogreset ports pll/ports, rx analog, cal blk, tx analog, reconfig tab settings set the same settings as the fc-4g alt2gxb instance mentioned in tables 3?13 . reconfig alt pll tab setting no selection required. reconfig clks 1 tab settings what is the main pll logical reference clock index 0 note: use this setting because you intend to generate the mif with a logical tx pll value of 0 . refer to ?how many mifs do i require?? on page 3?123 how many input clocks 3 (77.76 mhz, 125 mhz, and 106.25 mhz). what is the select input clock source for transmitter and receiver pll 1 what is the reconfig protocol driven by clock0 basic what is clock0 input frequency 106.25 mhz use clock 0 reference clock di vider do not check this option what is the reconfig protocol driven by clock2 sonet/sdh what is clock2 input frequency 77.76 mhz note: the order of the clock inputs is the same as of the fc-4g instantiation shown in table 3?13 use clock 2 reference clock di vider do not check this option reconfig2 tab settings same as of the fc-4g instantiation shown in table 3?13
3?128 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration . basic1 and basic2 tab setting select the word alignment and other ports based on your requirements and complete the megawizard table 3?15. sonet/sdh oc48 prot ocol settings (part 1 of 2) tab page and option setting general tab settings which protocol you wi ll be using sonet/sdh which sub protocol oc48 operation mode receiver and transmitter what is the input clock frequency 77.76 mhz select the rxdigitalreset , txdigitalreset , and rxanalogreset ports pll/ports, rx analog, cal blk, tx analog, reconfig tab settings set the same settings as the fc-4g alt2gxb instance mentioned in tables 3?13 reconfig alt pll tab setting no selection required. reconfig clks 1 tab settings what is the main pll logical reference clock index 0 how many input clocks 3 (77.76 mhz, 125 mhz, and 106.25 mhz) what is the select input clock source for transmitter and receiver pll 2 what is the reconfig protocol driven by clock0 basic what is clock0 input frequency 106.25 mhz use clock 0 reference clock di vider do not check this option what is the reconfig protocol driven by clock1 gige what is clock1 input frequency 125 mhz table 3?14. gige protocol settings (part 2 of 2) tab page and option setting
altera corporation 3?129 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration the alt2gxb megawizard instantiation for the three protocols is complete. the following are the settings for channel 1: assume that the default configuration of ch1 is fc-4g. you can copy the fc-4g instantiation created for ch0. the only change required for this new instantiation is in the reconfig clks 1 tab. set the what is the main pll logi cal reference clock index? option to 1 (this is the logical tx pll value) and complete the megawizard. for ch0, set the value in this field to 0 . since the design goal is to reconfigure these two channels independently, set different logical tx pll values for these two channels and complete the megawizard. for ch2 and ch4, reuse the ch0 instan ce. similarly, for ch3 and ch5, reuse the ch1 instance. section ii ? alt2gxb_reconfig megawizard instantiation the following are settings for the alt2gxb_reconfig megawizard: set the what is the number of channe ls controlled by the reconfig controller? option to 24 . in this design, you have six instantiations (for six channels). the starting ch annel numbers for each of these instantiations should be a multiple of four. each of these alt2gxb instantiation has a reconfig_fromgxb output port. the reconfig controller provides one reconfig_fromgxb input port for a multiple of 4 channels. therefore, set the above field to 24 (rounded to the nearest transc eiver block). fo r additional information on starting channe l numbers and logical channel addressing, refer to ?introduction? on page 3?1 . use clock 1 reference clock di vider do not check this option reconfig2 tab settings same as of the fc-4g instantiation shown in table 3?13 basic1 and basic2 tab setting select the word alignment and other ports based on your requirements and complete the megawizard table 3?15. sonet/sdh oc48 prot ocol settings (part 2 of 2) tab page and option setting
3?130 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration select the channel and tx pll select/reconfig option. in the channel and tx pll reconfiguration tab, select reconfig_address_out and reconfig_address_en . select logical_tx_pll_sel and logical_tx_pll_sel_en ports so that you can reuse the mif. (refer to ?how many mifs do i require?? on page 3?123 . section iii ? steps to create mifs this section explains the steps to create all the mifs at one time: 1. go to the assignments menu and select settings , then fitter settings . 2. click the more settings button and set the generate stratix ii gx gxb reconfig mif with pll option to on using the settings option (as shown in figure 3?56 ). 3. create a top-level design file an d include the three instantiations created for ch0 (fc-4g, gige, and sonet/sdh oc48 protocol). connect the pll_inclk_rx_cruclk[] ports to the following clock source: a. pll_inclk_rx_cruclk[0] - 106.25 mhz. assume refclk0 of transceiver bank 13. b. pll_inclk_rx_cruclk[1] - 125 mhz. assume refclk0 of transceiver bank 14. c. pll_inclk_rx_cruclk[2] - 77.76 mhz. assume refclk0 of transceiver bank 15. 4. for this example design, assume that the three clock inputs are provided from the dedicated refclk pins. if you provide input reference clocks through the gl obal clock networks, refer to ?clocking enhancements and requirements? on page 3?90 for usage limitations. 5. assign the tx_dataout and rx_datain pins of the fc-4g, gige, and sonet/sdh oc48 instantiations to transceiver banks 13, 14, and 15, respectively. since you have assigned logical tx pll value to 0 to all these instantiat ions, place these channels in three different transceiver banks to compile successfully (refer to ?case ii: merging transceiver channels listening to one tx pll? on page 3?120 ). the intent of placing these instantiations in different banks is to generate all the mifs at one time.
altera corporation 3?131 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 6. rename the generated mifs to indi cate the protocol for which the mif is configured. section iv ? reset control logic and user logic the reset control logic takes care of resetting the transceiver during system initialization and during reconfiguration (altera recommends a specific reset sequence, refer to ?reset recommendations? on page 3?66 for more information). for the user logic, use different clocks ( tx_clkout for gige protocol and rx_clkout for fc-4g and sonet/sdh oc48) for the parallel data in the receive interface of the alt2gxb. the user logic is not discussed in this section. refer to figure 3?37 on page 3?82 for more information regarding user logic in a similar configuration. section v ? top-level design and sr am object file (.sof) generation follow these steps to generate a sram object file: 1. instantiate the six alt2gxb channels in the top-level design. that is, stamp the fc-4g instance created for logical_tx_pll value 0 three times for ch0, ch2, and ch4. 2. similarly, stamp the instance created for logical_tx_pll value 1 for ch1, ch3, and ch5. 3. add the reset and user logic and connect the signals. in the assignment editor, use the stratix ii gx gxb tx pll reconfig group setting option and assign the tx_dataout of ch0 and ch1 to the same reconfig group (this is required to assign ch0 and ch1 to the same transceiver bank). 4. similarly, assi gn the same reconfig groups for ch2-ch3 and ch4-ch5. case ii: configuring tr ansceiver channels to switch independently between three different protocols this example discusses the steps to reconfigure the three full-duplex channels (ch0, ch1, and ch2) in a transceiver bank between the fc-4g, fc-2g, gige, sonet/sdh oc48 protocol s. in the previous example, the design used only two channels in a transceiver bank. therefore, each channel could use a dedicated tx pll.
3?132 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration in this example, the thre e channels are reconfigured in a transceiver bank. this means that two tx plls are shared between three channels. therefore, if you use a main and al ternate txpll for each channel, you can reconfigure the channel to any two of the four protocols by switching between the two tx plls. figure 3?65 shows the tx pll connections of the tx side. (to simplify the illustration, only the tx side is show n). the figure shows that the default configurations of ch0, ch1, and ch2 are fc-4g, fc-2g, and gige, respectively. figure 3?65. logical tx pll connections with the transceiver channel how many mifs do i require? you will need four mifs for this design. you can generate the mifs for one tx pll and use the logical_tx_pll_sel in the reconfig controller to write the mif contents into the seco nd tx pll. assume that the tx pll configured for fc- 4g data rate is assigned a logical tx pll value of 0 . this means that the other tx pll configured for gige and sonet/sdh pll_inclk_rx_cruclk[2] pll_inclk_rx_cruclk[1] pll_inclk_rx_cruclk[0] 77.76 mhz 125 mhz 106.25 mhz clock mux clock mux 4.25 gbps/ 1.25 gbps/ 2.48 gbps logical txpll0 4.25 gbps/ 1.25 gbps/ 2.48 gbps logical txpll1 tx side of ch0 - default configuration fc 4 tx side of ch1 - default configuration fc 2 logical tx pll select local divider digital + analog logic digital + analog logic local divider logical tx pll select tx side of ch2 - default configuration gige digital + analog logic local divider logical tx pll select alternate txpll set during alt2gxb megawizard instantiation main txpll set during alt2gxb megawizard instantiation
altera corporation 3?133 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration oc48 protocol is assigned a logical tx pll value of 1 . table 3?15 shows the number of mifs required and the lo gical tx pll value assigned for the different configurations. 1 use the same clocking connectio ns and data path for these protocols that were provided in the previous example. the following discus sion of the design is divided into three sections: section i?alt2gxb megawizard settings for the three protocols section ii?alt2gxb_reconfi g megawizard instantiation section iii?using the logical_tx_pll_sel during reconfiguration section i ? alt2gxb megawizard settings for the three protocols in this section, only the alt2gxb megawizard settings relevant to the channel and cmu pll reconfiguration feature are discussed in tables 3?17 through 3?20 . refer to tables 3?13 , 3?14 , and 3?15 for the tab settings that are not specified in this section. table 3?16. mif file for the four configurations number mif logical tx pll value 1fc-4g 0 2fc-2g 0 3gige 1 4sonet/sdh oc48 1 table 3?17. fc-4g protocol settings (part 1 of 2) tab page and option setting general tab settings which protocol you will be using basic which sub protocol you wi ll be using serial loopback operation mode receiver and transmitter what is deserializer block width double what is channel width 40 (8b/10b encoder/decoder in the alt2gxb is not used) what is the data rate 4250 mbps what is the input clock frequency 106.25 mhz
3?134 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration for the fc-2g configuration, use the tx pll that provides fc-4g clock frequency and divide by two with the local divider in the tx channel. copy the instance created for the fc-4g instance. the only change required is in the general tab. what is the data rate division factor 1 select the rxdigitalreset , txdigitalreset , and rxanalogreset ports reconfig tab settings select channel interface this is r equired since the three protocols require different pld widths (refer to table 3?12 ) select channel internals and enable channel and transmitter pll reconfiguration reconfig alt pll tab setting what is the alternate pll reference clock index 1 you used a logical tx pll value of 0 for fc-4g. therefore, this alternate index (for example, gige) should be set to 1 protocol gige data rate 1.25 gbps clock frequency 125 mhz reconfig clks 1 and reconfig2 tab settings use the same clock order as the previous example. refer to table 3?13 table 3?18. fc-2g protocol settings (part 1 of 2) tab page and option setting general tab settings which protocol you will be using basic which sub protocol you wi ll be using serial loopback operation mode receiver and transmitter what is deserializer block width double what is channel width (8b/10b in the alt2gxb) table 3?17. fc-4g protocol settings (part 2 of 2) tab page and option setting
altera corporation 3?135 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration . copy the instance created for fc-4g instance. the only change required is in the general tab. what is the data rate 4250 mbps what is the input clock frequency 106.25 mhz what is the data rate division factor 2 table 3?19. gige protocol settings tab page and option setting general tab settings which protocol you will be using gige what is the input clock frequency 125 mhz reconfig alt pll tab setting what is the alternate pll reference clock index 0 you used a logical tx pll value of 1 for gige. therefore, the alternate index (for fc-4g) should be set to 0. protocol basic data rate 4.25 gbps clock frequency 106.25 mhz reconfig clks 1 and reconfig2 tab settings use the same clock order as the previous example. refer to table 3?13 table 3?20. fc-2g protocol settings (part 1 of 2) tab page and option setting general tab settings which protocol you wi ll be using sonet/sdh which sub protocol y ou will be using oc48 what is the input clock frequency 77.76 mhz reconfig alt pll tab settings table 3?18. fc-2g protocol settings (part 2 of 2) tab page and option setting
3?136 altera corporation stratix ii gx device handbook, volume 2 october 2007 channel and clock multiplier unit (cmu) pll reconfiguration section ii ? alt2gxb_reconfig megawizard instantiation the following are the setting s for the alt2gxb_reconfig megawizard: set the what is the number of channe ls controlled by the reconfig controller option to 12 (this will provide separate reconfig_from_gxb ports for each instance). select the channel and tx pll select/reconfig option. in the channel and tx pll reconfiguration tab, select the reconfig_address_out , reconfig_address_en , logical_tx_pll_sel , and logical_tx_pll_sel_en ports so that you can reuse the mif. (refer to ?how many mifs do i require?? on page 3?132 ). section iii ? using the logical_tx _pll_sel during reconfiguration follow the same procedure as mentioned in ?mif generation for channel and cmu pll reconfiguration? on page 3?111 to create your mifs. in the top-level design, assign the stratix ii gx gxb tx pll reconfig group setting and assign the same reconfig group to the three channels. if you would like to reconfigure ch0 to sonet/sdh oc48 mode, use the following steps: 1. in the megawizard instantiation, set the logical tx pll value of the main txpll for ch0 to 0 . the sonet/sdh oc48 mif contains the logical tx pll value of 1 . to use the sonet/sdh oc48 mif for ch0, set both the logical_tx_pll_sel and logical_tx_pll_sel_en ports to 1 in the reconfig controller. what is the alternate pll reference clock index 0 you used a logical tx pll value of 1 for sonet/sdh oc48. therefore, the alternate index (for fc-4g) should be set to 0 . protocol basic data rate 4.25 gbps clock frequency 106.25 mhz table 3?20. fc-2g protocol settings (part 2 of 2) tab page and option setting
altera corporation 3?137 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration 2. set the reconfig_mode_sel value to 101 (channel and tx pll reconfiguration) and write the sonet/sdh oc48 mif. 1 since ch0 and ch1 share the same tx pll, configuring ch0 affects ch1. you can either conf igure ch1 to go to sonet/sdh oc48 mode or switch ch1 to listen to the gige mode by switching it to listen to the alternate txpll. adaptive equalization (aeq) high-speed interface systems are used at different data rates with multiple backplane environments. these systems require different equalization settings to compensa te for changing data rates and backplane characteristics. manually selecting optimal equalization settings is cumbersome under these changing system characteristics. the adaptive equalization feature solves this problem by enabling the stratix ii gx device to continuously tune the receiver equalization settings based on the frequency content of the incoming signal. five equalizer filters are tuned during this adaptive equalization process. the user logic can dynamically control the aeq hardware through the dynamic reconfigur ation controller. this section explains the method to en able different options to control the aeq hardware. altera assumes that you have prior knowledge about the dynamic reconfiguration controller. for basic information, refer to ?dynamic reconfiguration cont roller architecture? on page 3?2 . conventions used the following conventions are used in this section: alt2gxb_reconfig?refers to the dynamic reconfiguration controller logic generated by the quartus ii al2gxb_reconfig megawizard plug-in manager. alt2gxb_reconfig and dynamic reconfiguration controller are used interchangeably in this section. active channels?channels that have the enable adaptive equalizer control option selected in the alt2gxb megawizard. selecting this option enables the adaptive equalization hardware.
3?138 altera corporation stratix ii gx device handbook, volume 2 october 2007 adaptive equalization (aeq) aeq feature requirements the following are device requirements for the aeq feature: different device families require di fferent silicon revisions, as shown in table 3?21 : the transceiver data rate needs to be > 2.5 gbps the receive data needs to be 8b/10b encoded. not available in pci-express (pipe) functional mode (since the adaptive equalization hardware cannot perform the equalization process when the receive link is under the electrical idle condition) the receiver input signal should have a minimum envelope of 400 mv (differential peak-to-peak). the quartus ii software does not check for this requirement. aeq is supported only in device speed grades c3, c4, or i4. enabling the aeq hardware the aeq hardware is available for each transceiver channel in the stratix ii gx device. to enable the aeq hardware, select the enable adaptive equalizer control option in the reconfig page of the alt2gxb megawizard plug-in manager ( figure 3?66 ). table 3?21. silicon revision requi rements for the aeq feature device family silicon revision (1) 2sgx30 revision a 2sgx60 revision a 2sgx90 revision c 2sgx130 revision b note to table 3?21 : (1) you can identify the silicon revision by looking at the print below the device name in the device package. the third letter from the left indicates the silicon revision. for example, the print aac9x0607a (third letter from left, ?c ?) indicates a rev c silicon.
altera corporation 3?139 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?66. enable the adaptive equalization hardware when you select this option, th e alt2gxb megawizard provides the following additional ports: aeq_fromgxb[] aeq_togxb[] fixedclk the aeq_fromgxb[] and aeq_togxb[] ports provide the interface between the transceiver channel (alt2gxb) and the dynamic reconfiguration controller (alt2gxb _reconfig). for each channel, the width of the aeq_fromgxb[] and aeq_togxb[] ports are 6 bits and 4 bits, respectively. if you have multiple transceiver instances, connect the least significant byte of the aeq_togxb[3:0] and aeq_fromgxb[5:0] ports between the alt2gxb_reconf ig and the transceiver channel
3?140 altera corporation stratix ii gx device handbook, volume 2 october 2007 adaptive equalization (aeq) with logical_channel_address value of 0 . figure 3?67 shows the connections between multiple alt2 gxb instances and the dynamic reconfiguration controller. figure 3?67. interface connection between the al t2gxb and the alt2gxb_reconfig instance the fixedclk port provides the clock input to run the aeq hardware. the range of the input clock frequency to the fixedclk port should be between 2.5 mhz and 125 mhz. to save clock routing resources, you can use the same clock pin to pr ovide input clocks for the fixedclk and reconfig_clk ports. 1 when the transceiver channel is configured for pci-express (pipe) protocol, the fixedclk is used to operate the receiver detect circuitry. in this protocol mode, fixedclk requires a fixed 125 mhz input clock freque ncy. the aeq feature is not available in pci-express (pipe) protocol mode. alt2gxb_ reconfig aeq_togxb[7:0] aeq_fromgxb[11:0] aeq_fromgxb[5:0] aeq_togxb[3:0] aeq_togxb[7:4] aeq_fromgxb[11:6] alt2gxb instance 0 starting channel number=0 alt2gxb instance 1 starting channel number=4
altera corporation 3?141 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration the alt2gxb_reconfig block provid es a simple interface between the user logic and the transceiver channel to control the aeq hardware. figure 3?68 shows the alt2gxb_reconfig megawizard page with different aeq options. figure 3?68. alt2gxb_reconfig with differ ent adaptive equalization control options controlling the aeq hardware the alt2gxb_reconfig provides different options to start and power down the adaptive equalization hard ware. you can select these options by setting different values in the reconfig_mode_sel[] port. to use these options, set the reconfig_mode_sel[] port to the corresponding value shown in table 3?22 .
3?142 altera corporation stratix ii gx device handbook, volume 2 october 2007 adaptive equalization (aeq) the dynamic reconfiguration controller provides the options shown in table 3?22 to control the adaptive equalization operation. enable for a single channel this option, shown in figure 3?68 , provides the flexibility to start the adaptive equalization operation in a specific transceiver channel. to initiate the aeq operation for a single channel, set the logical address of the channel in the logical_channel_address[] port. (for more information, refer to ?example for using logical channel address to perform channel reconfiguration? on page 3?24 ). set the reconfig_mode_sel[3:0] port to 0111 and assert the write_all signal for one reconfig_clk cycle, as shown in figure 3?69 . figure 3?69. aeq write timing diagram on a single channel when the write_all signal is asserted, the dynamic reconfiguration controller writes the initialization and control values into the transceiver registers and initiates the adaptive equalization process. during this initialization process, the dynamic reconfiguration controller powers down the receiver buffer. this results in transient bit errors on the parallel interface on the receive side. the alt2gxb_reconfig de-asserts the busy signal after the write transaction is completed. table 3?22. reconfig_mode_sel port opti ons for the adapt ive equalization feature reconfig_mode_sel[3:0] adapt ive equalization options 0111 enable for a single channel 1000 enable for all channels 1001 power down for a single channel 1010 power down for all channels write_all reconfig_mode_sel[3:0] logical_channel_address[] busy 0111 4 (for logical channel4) alt2gxb_reconfig indicates the completion of the write transation
altera corporation 3?143 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?69 shows the value 4 in the logical_channel_address[] signal as an example. the alt2 gxb_reconfig takes a maximum of approximately 7,000 reconfig_clk cycles to complete the aeq write operation. enable for all channels this option allows you to initiate th e adaptive equalization operation on all the active channels connected to the same dynamic reconfiguration controller. the method to initiate the aeq operation for all channels is similar to ?enable for a single channel? on page 3?142 . set the reconfig_mode_sel[3:0] to 1000 and assert the write_all signal for one reconfig_clk cycle, as shown in figure 3?70 . figure 3?70. aeq write timing di agram on all active channels the dynamic reconfiguration controller initiates the write transaction for all the active channels starting with the lowest logical channel that has the aeq feature enabled. for example, as sume that you have three channels connected to a dynamic reconfiguration controller with logical address values of 0 , 4 , and 8 , respectively. if the logical channels 4 and 8 have the aeq feature enabled, when you use this option, the alt2gxb_reconfig starts the ae q write operation from logical address value of 8 . the alt2gxb_reconfig de-asserts the busy signal after the write transaction is completed for all active channels. the number of reconfig_clk cycles required to complete the aeq write operation in this mode is approximat ely 7,000 multipli ed by the number of active channels. write_all reconfig_mode_sel[3:0] busy 1000 alt2gxb_reconfig indicates the completion of the write transaction on all active channels
3?144 altera corporation stratix ii gx device handbook, volume 2 october 2007 adaptive equalization (aeq) power down options the aeq hardware consumes approxim ately 80 mw power (typical) per channel. therefore, the dynamic re configuration controller provides options to dynamically power down the aeq hardware. the options are: power down for a single channel power down for all channels power down for a single channel when you use this option, the al t2gxb_reconfig controller powers down the aeq hardware in the selected channel specified by the logical_channel_address value. before powering down the aeq hardware, the alt2gxb_reconfig reads the adaptive equalization settings, translates th em to the nearest available manual equalization setting, and automatically writes th e translated manual equalization settings into the transceiver channel. to read the tr anslated manual equalization values, perform a read operation using the pma controls option. the translated ma nual equalization values are available in the corresponding byte positions of the rx_eqctrl_out port. for example, assume that you perform an aeq writ e using this option to power down the aeq hardware in logical chan nel 4. when you perform a read operation using the pma controls option, the translated manual equalization values are available in rx_eqctrl_out port in bits 19 down to 16, as shown in figure 3?71 .
altera corporation 3?145 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration figure 3?71. aeq write timing diagram for power down for a single channel (logical channel 4) for more information about using the pma controls option, refer to ?channel and pma controls reconfiguration? on page 3?20 . the dynamic reconfiguration contro ller takes approximately 700 reconfig_clk cycles to complete the write transaction with this option. during the power down process, there may be bit errors on the receiver output data for a few receive parallel clock cycles. 1 the alt2gxb_reconfig translates the equalization values converged by the aeq hardware and performs a rounding to the nearest manual equalization setting. power down for all channels this option provides the flexibility to power down the aeq hardware in all the active channels connected to the same dynamic reconfiguration controller. the alt2gxb_reconfig performs the translation as explained in ?power down options? on page 3?144 . the dynamic reconfiguration controller powers down the aeq hardware on all the active channels starting with the lo west logical channel. for example, assume that you have three channels with logical address values of 0 , 4 , and 8 , respectively. if only logical channels 4 and 8 have the aeq feature enabled, when you use this option, the alt2gxb_reconfig starts the xxxx wrtie_all reconfig_mode_sel[3:0] busy rx_eqctrl_out[19..16] 1001 alt2gxb _ reconfig indicates that the aeq hardware for logical channel address 4 is powered down valid translated manual equalization settings read 0000 pma read operation 4 (logical channel 4) logical_channel_address[]
3?146 altera corporation stratix ii gx device handbook, volume 2 october 2007 adaptive equalization (aeq) power down operation from logical address value of 4 . to read the translated manual equalization valu es, perform a read operation using the pma controls option. the translated manual equalization values are available in the correspond ing byte positions of the rx_eqctrl_out port, as shown in figure 3?72 . figure 3?72. aeq write timing diagram for power down for all active channels for more information on the byte po sitions of the pma control input and output ports, refer to ?design examples? on page 3?121 . the number of reconfig_clk cycles that the dynamic reconfiguration controller takes is approximately 700 times the number of active channels connected to the dynamic reconfiguration controller. during the power down process, there may be bit errors on the receiver output data for few receive parallel clock cycles. in addition to controlling the aeq hardware, alt2gxb_reconfig supports multiple features; for ex ample, pma controls, channel reconfiguration, etc. therefore, only one operation (selected by reconfig_mode_sel[] ) can be performed at any given time. xxxx xxxx wrtie_all reconfig_mode_sel[3:0] busy rx_eqctrl_out[19..16] rx_eqctrl_out[35..32] 1010 alt2gxb_reconfig indicates that the aeq hardware for all active channels is powered down valid translated manual equalization settings read 0000 pma read operation
altera corporation 3?147 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx dynamic reconfiguration if the aeq hardware is enabled for a channel, you can reconfigure the channel with the manual eq ualization values (using reconfig_mode_sel - 0000 ) only after the aeq hardware is powered down (using reconfig_mode_sel - 1001 or 1010 ). if you perform an unsupported aeq operation, the dynamic reconfiguration controller waits for a pre-defined number of clock cycles for the aeq operation to complete. if the busy signal does not get deasserted within the pre-defined number of reconfig_clk cycles, the dynamic reconfiguration co ntroller de-asserts the busy signal. quartus ii software me rging requirements the quartus ii software has certai n requirements for merging multiple transceiver channel instances in the same transceiver block, as discussed in ?merging transceiver channels with dynamic reconfiguration enabled? on page 3?120 . in addition to the above requirements, when you enable the adaptive equalization option in the alt2gxb megawizard for one transceiver instance, the quartus ii software requir es that you enable this option in the other channels to merge them in the same transceiver block. summary using the dynamic reconfiguration feature, you can reconfigure the analog controls, data rates, and pr otocols of the transceiver without requiring a system power down. thes e features provide a flexible and effective solution for various line card and backplane applications. referenced documents this chapter references the following documents: alt2gxb_reconfig megafunction user guide chapter in volume 2 of the stratix ii gx device handbook stratix ii gx alt2gxb me gafunction user guide chapter in volume 2 of the stratix ii gx de vice handbook. ?stratix ii gx alt2gxb ports list? on page 2?2 in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook stratix ii gx transceiver architecture overview chapter (the reset control and power down section) in volume 2 of the stratix ii gx handbook.
3?148 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history document revision history table 3?23 shows the revision history for this chapter. table 3?23. document revision history date and document version changes made summary of changes october 2007, v1.1 added: ?adaptive equalization (aeq)? ?using dedicated refclks? ? updated: ?reconfig clks 1 tab? ?channel and pma controls reconfiguration? ?example 3? ? updated: figure 3?1 figure 3?2 figure 3?19 figure 3?30 figure 3?31 figure 3?45 figure 3?58 figure 3?59 figure 3?60 figure 3?62 ? updated table 3?2 .? added the ?referenced documents? section. ? minor text edits. ? august 2007, v1.0 moved the ?introduction? section from the stratix ii gx architecture overview chapter to this chapter. ? updated the ?introduction? and ?channel and pma controls reconfiguration? sections. ? initial release of the ?channel and clock multiplier unit (cmu) pll reconfiguration? section. ?
altera corporation 4?1 october 2007 4. stratix ii gx alt2gxb megafunction user guide introduction the megawizard ? plug-in manager in the quartus ? ii software creates or modifies design files that contain cu stom megafunction variations that can then be instantiated in a de sign file. the megawizard plug-in manager provides a megawizard that allows you to specify options for the alt2gxb megafunction. you ca n use the megawizard to set the alt2gxb megafunction features in the design. start the megawizard plug-in manager using one of the following methods: choose the megawizard plug-in manager command (tools menu). when working in the block editor, click megawizard plug-in manager in the symbol dialog box (edit menu). start the stand-alone version of the megawizard plug-in manager by typing the following command at the command prompt: qmegawiz . the alt2gxb megawizard plug-in manager allows you to configure one or more transceive r channels. it also allows you to enable the dynamic reconfiguration feature for these channels, depending on your system requirements. figure 4?1 shows the first page of the megawizard plug-in manager. to generate an alt2gxb custom megafunction variation, select create a new custom megafunction variation . figure 4?1. megawizard plug-in manager (page 1) siigx52003-4.2
4?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode figure 4?2 shows the second page of th e megawizard plug-in manager. select the stratix ii gx device as the device family. figure 4?2. megawizard plug-in manager (page 2) basic mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for basic mode. the megawizard plug-in manager provides a warning if any of the settings you choose are illegal.
altera corporation 4?3 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?3 shows page 3 of the alt2gxb megawizard plug-in manager in basic mode. figure 4?3. megawizard plug-in manager - alt2gxb (general)
4?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode table 4?1 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?1. megawizard plug-in manager opti ons (page 3 for basic mode) (part 1 of 3) alt2gxb setting description reference which protocol will you be using? determines the specific protocol or modes under which the transceiver operates. for the basic mode, you must select the basic protocol. which subprotocol will you be using? in basic mode, the subprotocols are the diagnostic modes. the available options are as follows: no loopback ? this is the normal operation of the transceiver. serial loopback ? this mode loops the user data from the transmitter path back to the receiver path right before the buffers. the serial loopback can be controlled dynamically. parallel loopback/bist ? this mode loops the parallel data from the bist (non prbs) back to the bist verifier in the receiver path. parallel loopback is allowed only in basic double-width mode. reverse serial loopback ? this is a loopback after the receiver?s cdr block to the transmitter buffer. the rx path in the pcs is active but the tx side is not. reverse serial loopback (pre-cdr) ? this is the loopback before the receiver?s cdr block to the transmitter buffer. the rx path in the pcs is active but the tx side is not. prbs/serial loopback ? this is another serial loopback mode, but with the prbs bist block active. the prbs pattern depends on the serdes factor. x4 ? this mode can be used to implement sfi-5 interface. in this mode, all four channels within the transceiver block are clocked from its central clock divider block to minimize the transmitter channel-to-channel skew. loopback modes and built-in self-test modes sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enforce default settings for this protocol this selection is not active in basic mode because there is no pre-defined protocol. what is the operation mode? the available operation modes are receiver only, transmitter only, and receiver and transmitter. what is the number of channels? this option determines how many duplicate channels this alt2gxb instance contains.
altera corporation 4?5 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the deserializer block width? this option sets the transceiver data path width. single width ? this operates from 600 mbps to 3.125 gbps. the features of each block may differ from the double-width mode. double width ? this mode operates from 1 gbps to 6.375 gbps. the features of each block in this mode may differ from the single-width mode. what is the channel width? this opti on determines the transceiver to pld interface width. in single-width mode, selecting 8 or 10 bits bypasses the byte serializer/deserializer. if you select 16 or 20 bits, the byte serializer/deserializer is used. in double-width mode, selecting 16 or 20 bits bypasses the byte serializer/deserializer. any width greater uses the byte serializer/deserializer. byte serializer and deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option allows you to do one of following: enter a data rate and select an input clock frequency through a pull-down menu (with the data rate selection). enter your input clock frequency through a pull-down menu (with the data rate selection) or enter your input clock frequency and select from the available data rates for a clock frequency. what is the data rate? determines the tx and rx pll vco frequency. what is the input clock frequency? determines the input clock frequency you want as a reference clock for the transceiver. what is the data rate division factor? this setting, in conjunction with the selected data rate, determines the effective data rate for the transceiver channel. division fa ctors of 1, 2, and 4 are available. for example, a data rate setting of 3000 mbps and data rate division factor of 2 yields an effective data rate of 1500 mbps. create rx_digitalreset port receiver digital reset port. resets the pcs portion of the receiver. altera ? recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?1. megawizard plug-in manager opti ons (page 3 for basic mode) (part 2 of 3) alt2gxb setting description reference
4?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode create rx_analogreset port receiver analog reset port. reset control and power down? section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?1. megawizard plug-in manager opti ons (page 3 for basic mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?7 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?4 shows page 4 of the alt2gxb megawizard plug-in manager for basic mode. figure 4?4. megawizard plug-in manager - alt2gxb (pll/ports)
4?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode table 4?2 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?2. megawizard plug-in manager opti ons (page 4 for basic mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if cmu pll reconfiguration is enabled, this option is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? transmitter pll bandwidth selection of low, medium, and high. the recommendations will be determined by characterization. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? receiver pll bandwidth selection of low, medium, and high. the recommendations will be determined by characterization. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver clock recovery unit (cru) switchover between lock-to-data and lock-to-reference. (there are additional factors that affect the cru?s transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?9 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicated data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?2. megawizard plug-in manager opti ons (page 4 for basic mode) (part 2 of 3) alt2gxb setting description reference
4?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode create debug_rx_phase_comp _fifo_error output port this optional output port indicates receiver phase compensation fifo over flow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp _fifo_error output port this optional output port indicates transmitter phase compensation fifo over flow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?2. megawizard plug-in manager opti ons (page 4 for basic mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?11 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?5 shows page 5 of the alt2gxb megawizard plug-in manager for basic mode. figure 4?5. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
4?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode table 4?3 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?3. megawizard plug-in manager opti ons (page 5 for basic mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is programmable between 0.85 v and 1.2 v. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. force signal detection this option disabl es the signal detect circuit. this removes the signal detect criterion for the receiver cru lock-to-reference and lock-to-data switchover. this option is available only in pipe mode. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? use this option when the forced signal detection option is off and to set the trip point of the signal detect circuit. this option is available only in pipe mode. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?13 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. create active low cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?3. megawizard plug-in manager opti ons (page 5 for basic mode) (part 2 of 2) alt2gxb setting description reference
4?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode figure 4?6 shows page 6 of the alt2gxb megawizard plug-in manager for basic mode. figure 4?6. megawizard plug-in manager - alt2gxb (tx analog)
altera corporation 4?15 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?4 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?4. megawizard plug-in manager opti ons (page 6 for basic mode) (part 1 of 2) alt2gxb setting description reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. the selections available are 1.2 v and 1.5 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. restrictions apply based on the v cch setting. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode figure 4?7 shows page 7 of the alt2gxb megawizard plug-in manager for basic mode. figure 4?7. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis fi rst post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. table 4?4. megawizard plug-in manager opti ons (page 6 for basic mode) (part 2 of 2) alt2gxb setting description reference
altera corporation 4?17 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?5 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?5. megawizard plug-in manager options (page 7 for basic mode) alt2gxb setting description reference what do you want to be able to dynamically reconfigure in the transceiver? available options are: analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel interface: enables mif-based reconfiguration among modes that have different pld interface signals. channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but have the same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is the logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode figure 4?8 shows page 8 of the alt2gxb megawizard plug-in manager for basic mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?8. megawizard plug-in manager - alt2gxb (reconfig alt pll) table 4?8 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?6. megawizard plug-in manager options (page 8 for basic mode) alt2gxb setting description reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?19 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?9 shows page 9 of the alt2gxb megawizard plug-in manager for basic mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?9. megawizard plug-in manager - alt2gxb (reconfig clks 1)
4?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode table 4?7 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?7. megawizard plug-in manager options (page 9 for basic mode) alt2gxb setting description reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/ or receiver pll, this option allows you to select the clock source for the current configuration. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?21 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?10 shows page 10 of the al t2gxb megawizard plug-in manager for basic mode. this page appears only if the channel internals or the channel interface option is selected in the reconfig page (page 7). figure 4?10. megawizard plug-in m anager - alt2gxb (reconfig 2)
4?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode table 4?8 describes the available options on page 10 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?8. megawizard plug-in manager options (page 10 for basic mode) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?23 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?11 shows page 11 of the megawizard plug-in manager for the basic protocol mode set up. figure 4?11. megawizard plug-in manager - alt2gxb (basic 1)
4?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode table 4?9 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?9. megawizard plug-in manager opti ons (page 11 for basic mode) (part 1 of 2) alt2gxb setting description reference enable byte ordering block this option enables the byte ordering block. for the basic protocol mode, this is only available in double-width mode with the 8b/10b decoder. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what do you want the byte ordering to be based on? this option allows you to trigger the byte ordering block either on the rising edge of rx_syncstatus signal or user-controlled rx_enabyteord signal from the pld. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the byte ordering pattern? enter the 10-bit pattern that the byte ordering block must place in the lsbyte position of the receiver-pld interface bus. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the byte ordering pad pattern? enter the pad pattern that the byte ordering block inserts until the byte ordering pattern can be placed in the lsbyte position. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable 8b/10b decoder/encoder this option enables the 8b/10b encoder and decoder. this option is only available if the channel width is a multiple of 8 bits. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_forcedisp to enable force disparity and use tx_dispval to code up the incoming word using positive or negative disparity this option allows you to force positive or negative disparity on transmitted data in 8b/10b configurations. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable rate match fifo this option enables the rate matcher and is only available with the 8b/10b decoder. rate matcher section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?25 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the 20-bit rate match pattern1? (usually used for +ve disparity pattern) enter the positive disparity rate matcher pattern and control code pattern. the skip pattern is used for insertion or deletion, and the control pattern identifies which group of skip patterns to use for rate matching. if only one disparity is needed for rate matching, you can enter the same pattern for both rate matching patterns (pattern1 and pattern2). rate matcher section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the 20-bit rate match pattern2? (usually used for -ve disparity pattern) enter the negative disparity rate matcher pattern and control code pattern. the skip pattern is used for insertion or deletion, and the control pattern identifies which group of skip patterns to use for rate matching. if only one disparity is needed for rate matching, you can enter the same pattern for both rate matching patterns (pattern1 and pattern2). rate matcher section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip receiver output data bits this option reverses the bit order of the data at the receiver-pld interface at a byte level to support msbit to lsbit transmission protocols. the default transmission or der is lsbit to msbit. flip transmitter input data bits this option reverses the bi t order of the data bits at the input of the transmitter at a byte level to support msbit to lsbit transmission protocols. the default transmission or der is lsbit to msbit. enable transmitter bit reversal this option inverts (flips) the bit order of the data bits at the transmitter pcs-pma interface at a byte level to support msbit to lsbit transmission protocols. the default transmission is lsbit to msbit. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?9. megawizard plug-in manager opti ons (page 11 for basic mode) (part 2 of 2) alt2gxb setting description reference
4?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode figure 4?12 shows page 12 of the megawizard plug-in manager for the basic protocol mode set up. figure 4?12. megawizard plug-in manager - alt2gxb (basic 2)
altera corporation 4?27 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?10 describes the available options on page 12 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?10. megawizard plug-in manager options (page 12 for basic mode) (part 1 of 3) alt2gxb setting description reference use manual word alignment mode this option sets the word aligner in manual alignment mode. (manual alignment, bit-slipping, and the built-in state machine are mutually exclusive options.) word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. when should the word aligner realign? this option sets the behavior of the rx_enapatternalign signal to either edge or level sensitive. altera recommends using edge sensitive for scrambled data (non-8b/10b) traffic and level sensitive for 8b/10b traffic. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use manual bit slipping mode this opti on sets the word aligner to use the bit-slip port to alter the byte boundary one bit at a time. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use the built-in 'synchronization state machine' this option sets the word aligner to use the built-in synchronization state machine. the behavior is similar to the pipe synchronization state machine with adjustable synchronization thresholds. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of bad data words before loss of synch state use this option with the built-in state machine to transition from a synchronized state to an unsynchronized state. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of consecutive valid words before synch state is reached this option sets the word aligner to check for a given number of good code groups. use this option with the built-in state machine in conjunction with the number of valid patterns before synchronization state is reached option to achieve synchronization. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of valid patterns before synch state is reached this option checks for the number of valid alignment patterns seen. use this option with the built-in state machine in conjunction with the number of consecutive valid words before synch state is reached option to achieve synchronization. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode what is the word alignment pattern length? this option sets the word alignment length. the available choices depend on whether 8b/10b is used and which mode (single or double width) is used. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the word alignment pattern? enter the word alignment pattern here. the length of the alignment pattern is based on the word alignment pattern length. in bit-slip mode, this option triggers the rx_patterndetect . word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip word alignment pattern bits this option reverses the bit order of the alignment pattern at a byte level to support msb to lsb transmission protocols. the default transmission order is lsb to msb. enable run-length violation checking with a run length of this option activates the run-length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable word aligner output reverse bit ordering in manual bit-slip mode, this option creates an input port rx_revbitorderwa to dynamically reverse the bit order at the output of the receiver word aligner. in other ba sic modes, this option statically configures t he receiver to always reverse the bit order of the data at the output of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_patterndetect port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?10. megawizard plug-in manager options (page 12 for basic mode) (part 2 of 3) alt2gxb setting description reference
altera corporation 4?29 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create rx_ctrldetect port to indicate 8b/10b decoder has detected a control code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_errdetect port to indicate 8b/10b decoder has detected an error code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_disperr port to indicate 8b/10b decoder has detected a disparity code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_revbyteorderwa to enable receiver symbol swap this option is available only in basic double-width mode. it creates an rx_revbyteorderwa port to dynamically swap the msbyte and lsbyte of the data at the output of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?10. megawizard plug-in manager options (page 12 for basic mode) (part 3 of 3) alt2gxb setting description reference
4?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 basic mode figure 4?13 shows page 13 of the megawizard plug-in manager for the basic protocol mode set up. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for the third party eda synthesis tool to estimate timing and resource utilization for the alt2gxb instance. figure 4?13. megawizard plug-in manager - alt2gxb (eda)
altera corporation 4?31 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?14 shows page 14 (last page) of the megawizard plug-in manager for the basic protocol mode set up. you can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?14. megawizard plug-in manager - alt2gxb (summary) physical interface for pci-express (pipe) mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for the pipe mode. the megawizard plug-in manager provides a warning if any of the settings you choose are illegal. 1 the word aligner and rate matcher operations and patterns are pre-configured for the pipe mode and cannot be altered.
4?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode figure 4?15 shows page 3 of the alt2gxb megawizard plug-in manager for pipe mode. figure 4?15. megawizard plug-in manager - alt2gxb (general)
altera corporation 4?33 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?11 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?11. megawizard plug-in manager options (page 3 for pipe mode) (part 1 of 2) alt2gxb setting description reference which protocol will you be using? determines the specific protocol or modes under which the transceiver operates. for the pipe mode, you must select the pci express (pipe) protocol. which subprotocol will you be using? in pipe mode, the subprotocols are the lane configurations: 1, 4, or 8 modes. pipe mode and clock multiplier unit sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enforce default settings for this protocol selecting this option skips the pci page in the pipe megawizard plug-in manager. the pci page allows you to select the pipe-specific ports for your design. if you select this option, all pipe-specific ports are used. what is the operation mode? only the receiver and transmitter (full duplex) mode is allowed in the pipe mode. receiver only and transmitter only modes are not allowed. what is the number of channels? this determines how many duplicate channels this alt2gxb instance contains. in a 4 subprotocol, the number of channels increments by 4. in a 8 subprotocol, the number of channels increment by 8. what is the deserializer block width? pipe mode only operates in a single-width mode. double-width mode is not allowed. what is the channel width? this opti on determines the transceiver to pld interface width. in pipe mode, 8 bits and 16 bits are allowed. what would you like to base the setting on? this option is not used because the data rate is fixed at 2.5 gbps for pipe mode. what is the data rate? this option is not used because the data rate is fixed at 2.5 gbps for pipe mode. what is the input clock frequency? determines the input reference clock frequency for the transceiver. in pipe mode, only 100 mhz is allowed. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode what is the data rate division factor? this option is not used because the data rate is fixed at 2.5 gbps for pipe mode. create rx_digitalreset port for the digital portion of the receiver receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_analogreset port for the analog portion of the receiver receiver analog reset port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port for the digital portion of the transmitter transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?11. megawizard plug-in manager options (page 3 for pipe mode) (part 2 of 2) alt2gxb setting description reference
altera corporation 4?35 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?16 shows page 4 of the alt2gxb megawizard plug-in manager for pipe mode. figure 4?16. megawizard plug-in manager - alt2gxb (pll/ports) table 4?12 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?12. megawizard plug-in manager options (page 4 for pipe mode) (part 1 of 4) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if cmu pll reconfiguration is enabled, this option is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? this option is not available in pipe mode because the transmitter pll bandwidth is fixed at high.
4?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode what is the receiver pll bandwidth mode? this option is not available in pipe mode because the receiver pll bandwidth is fixed at medium. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver cru switchover between lock-to-data and lock-to-reference. (there are additional factors that affect the cru?s transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?12. megawizard plug-in manager options (page 4 for pipe mode) (part 2 of 4) alt2gxb setting description reference
altera corporation 4?37 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicate data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_rx_phase_comp_fi fo_error output port this optional output port indicates receiver phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp_fi fo_error output port this optional output port indicates transmitter phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?12. megawizard plug-in manager options (page 4 for pipe mode) (part 3 of 4) alt2gxb setting description reference
4?38 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?12. megawizard plug-in manager options (page 4 for pipe mode) (part 4 of 4) alt2gxb setting description reference
altera corporation 4?39 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?17 shows page 5 of the alt2gxb megawizard plug-in manager for pipe mode. figure 4?17. megawizard plug-in manager - alt2gxb (rx analog/cal blk) note (1) note to figure 4?17 : (1) if the equalizer dc gain is controlled by the alt2gxb_reconfig controller, the rx_eqdcgain input to the alt2gxb_reconfig controller should be tied to "01" to be pci e-compliant.
4?40 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode table 4?13 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?13. megawizard plug-in manager options (page 5 for pipe mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. in pipe mode, a dc gain setting of 1 is forced. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is set to 0.85 v. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. force signal detection this option disabl es the signal detect circuit. this removes the signal detect criterion for the receiver cru lock-to-reference and lock-to-data switchover. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? use this option when the forced signal detection option is off and to set the trip point of the signal detect circuit. the levels are to be determined after characterization. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?41 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create active low cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?13. megawizard plug-in manager options (page 5 for pipe mode) (part 2 of 2) alt2gxb setting description reference
4?42 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode figure 4?18 shows page 6 of the alt2gxb megawizard plug-in manager for pipe mode. figure 4?18. megawizard plug-in manager - alt2gxb (tx analog)
altera corporation 4?43 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?14 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?14. megawizard plug-in manager options (page 6 for pipe mode) (part 1 of 2) alt2gxb setting des cription reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. in pipe mode, this value is fixed at 1.2 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? in pipe mode, the transmitter common mode voltage is fixed at 0.6 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. the amount of pre-emphasis is to be determined by characterization. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?44 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode figure 4?19 shows page 7 of the alt2gxb megawizard plug-in manager for pipe mode. figure 4?19. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis first post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. the amount of pre-emphasis is to be determined by characterization. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. the amount of pre-emphasis is to be determined by characterization. table 4?14. megawizard plug-in manager options (page 6 for pipe mode) (part 2 of 2) alt2gxb setting des cription reference
altera corporation 4?45 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?15 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?15. megawizard plug-in manager options (page 7 for pipe mode) alt2gxb setting des cription reference what do you want to be able to dynamically rec onfigure in the transceiver? in 1 mode, the available options are analog controls, enable adaptive equalizer control, channel internals, and channel interface. in 4 and 8 modes, only analog controls and enable adaptive equalizer control are dynamically reconfigurable. analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel channel interface: enables mif-based reconfiguration among modes that have different pld interface signals channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but the same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is t he logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?46 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode figure 4?20 shows page 8 of the alt2gxb megawizard plug-in manager for pci express (pipe) mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?20. megawizard plug-in manager - alt2gxb (reconfig alt pll) table 4?16 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?16. megawizard plug-in manager options (page 8 for pipe mode) alt2gxb setting des cription reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?47 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?21 shows page 9 of the alt2gxb megawizard plug-in manager for pci express (pipe) mode. this page appears only if the channel internals and the enable channel and transmitter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?21. megawizard plug-in manager - alt2gxb (reconfig clks 1)
4?48 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode table 4?17 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?17. megawizard plug-in manager options (page 9 for pipe mode) alt2gxb setting des cription reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/or receiver pll, this option allows you to select the clock source for the current configuration. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock source for the transmitter and/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter and/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?49 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?22 shows page 10 of the megawizard plug-in manager for the pipe protocol selection. this page appears only when the channel internals or channel interface options are selected in the reconfig page (page 7). figure 4?22. megawizard plug-in m anager - alt2gxb (reconfig 2)
4?50 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode table 4?18 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?18. megawizard plug-in manager options (page 10 for pipe mode) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section n the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?51 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?23 shows page 11 of the megawizard plug-in manager for the pipe protocol selection. if the enforce default settings for this protocol option is selected, this page do es not appear in the megawizard. figure 4?23. megawizard plug-in manager - alt2gxb (pci)
4?52 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode table 4?19 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?19. megawizard plug-in manager options (page 11 for pipe mode) (part 1 of 3) alt2gxb setting des cription reference enable rate match fifo this option enables bypassing of the rate match fifo in the receiver data path. low-latency pipe mode n the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable run-length violation checking with a run length of this option activates the run-length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable fast recovery mode this option creates the ntfs fast recovery ip required to meet the pci-e specification in the pld logic array. pci express (pipe) mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_patterndetect output port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_ctrldetect output port to indicate 8b/10b decoder has detected a control code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?53 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create pipestatus output port for pipe interface status signal refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create pipedatavalid output port to indicate valid data from the receiver refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create pipeelecidle output port for electrical idle detect status signal refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create pipephydonestatus output port to indicate pipe completed power state transitions refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create pipe8b / 10binvpolarity to enable polarity inversion in pipe refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_detectrxloop input port as receiver detect or loopback enable, depending on the power state refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_forceelecidle input port to force the transmitter to send electrical idle signals refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?19. megawizard plug-in manager options (page 11 for pipe mode) (part 2 of 3) alt2gxb setting des cription reference
4?54 altera corporation stratix ii gx device handbook, volume 2 october 2007 physical interface for pci-express (pipe) mode create tx_forcedispcompliance input port to force negative running disparity refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create powerdn input port for pipe powerdown directive refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. pipe mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. this feature must not be enabled when pipe8b/10binvpolarity is enabled. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?19. megawizard plug-in manager options (page 11 for pipe mode) (part 3 of 3) alt2gxb setting des cription reference
altera corporation 4?55 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?24 shows page 12 of the megawizard plug-in manager for the pipe protocol selection. the gene rate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for the third party eda synthesis tool to estimate timing and resource utilization for the alt2gxb instance. figure 4?24. megawizard plug-in manager - alt2gxb (eda)
4?56 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode figure 4?25 shows page 13 (the last page) of the megawizard plug-in manager for the pipe protocol set up. yo u can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?25. megawizard plug-in manager - alt2gxb (summary) xaui mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for the xaui mode. the megawizard plug-in manager provides a warning if any of the settings you choose are illegal. 1 the word aligner and rate matcher operations and patterns are pre-configured for the xaui mode and cannot be altered.
altera corporation 4?57 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?26 shows page 3 of the alt2gxb megawizard plug-in manager for xaui mode. figure 4?26. megawizard plug-in manager - alt2gxb (general) table 4?20 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?20. megawizard plug-in manager options (page 3 for xaui mode) (part 1 of 3) alt2gxb setting description reference which protocol will you be using? selects the specific prot ocol or modes under which the transceiver operates. for the xaui or higig, you must select the xaui protocol. which subprotocol will you be using? not applicable to xaui mode.
4?58 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode enforce default settings for this protocol selecting this option skips the xaui page of the xaui megawizard plug-in manager. the xaui page allows you to select the xaui-specific ports for your design. if you select this option, all xaui-specific ports are used. what is the operation mode? only receiver and transmitter (full duplex) is allowed in the xaui protocol. receiver only and transmitter only modes are not allowed. what is the number of channels? this selects how many duplicate channels this alt2gxb instance contains. in xaui mode, the number of channels increments by 4. what is the deserializer block width? xaui mode only operates in a single-width mode. double-width mode is not allowed. what is the channel width? this opti on determines the transceiver to pld interface width. only 16-bi t channel width is allowed in xaui mode. byte serializer and byte deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option is not available. what is the data rate? (1) enter a data rate from 3.125 gbps to 3.75 gbps. what is the input clock frequency? determines the input reference clock frequency for the transceiver. the quartus ii software automatically selects t he input reference clock frequency based on the entered data rate. what is the data rate division factor? this option is not available. create rx_digitalreset port for the digital portion of the receiver receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_analogreset port for the analog portion of the receiver receiver analog reset port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?20. megawizard plug-in manager options (page 3 for xaui mode) (part 2 of 3) alt2gxb setting description reference
altera corporation 4?59 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?27 shows page 4 of the alt2gxb megawizard plug-in manager for xaui mode. figure 4?27. megawizard plug-in manager - alt2gxb (pll/ports) create tx_digitalreset port for the digital portion of the transmitter transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. note to table 4?20 : (1) a data rate higher than 3.125 gbps requires a -3 speed grade device. the higher speed also requires a recompile of the design for different device settings. table 4?20. megawizard plug-in manager options (page 3 for xaui mode) (part 3 of 3) alt2gxb setting description reference
4?60 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode table 4?21 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?21. megawizard plug-in manager options (page 4 for xaui mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? in xaui mode, only high bandwidth is supported for the transmitter pll. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? in xaui mode, only medium bandwidth is supported for the receiver pll and vco. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver cru switchover between lock-to-data and lock-to-reference. (there are additional factor s that affect cru's transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?61 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicate data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?21. megawizard plug-in manager options (page 4 for xaui mode) (part 2 of 3) alt2gxb setting description reference
4?62 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode create debug_rx_phase_comp_fi fo_error output port this optional output port indicates receiver phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp_fi fo_error output port this optional output port indicates transmitter phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?21. megawizard plug-in manager options (page 4 for xaui mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?63 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?28 shows page 5 of the alt2gxb megawizard plug-in manager for xaui mode. figure 4?28. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
4?64 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode table 4?22 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?22. megawizard plug-in manager options (page 5 for xaui mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is set to 0.85 v. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. force signal detection this option is available onl y in pipe mode. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? this option is available only in pipe mode. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?65 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?22. megawizard plug-in manager options (page 5 for xaui mode) (part 2 of 2) alt2gxb setting description reference
4?66 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode figure 4?29 shows page 6 of the alt2gxb megawizard plug-in manager for xaui mode. figure 4?29. megawizard plug-in manager - alt2gxb (tx analog)
altera corporation 4?67 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?23 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?23. megawizard plug-in manager options (page 6 for xaui mode) (part 1 of 2) alt2gxb setting des cription reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. the selections available are 1.2 v and 1.5 v transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. restrictions apply based on the v cch setting. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. the amount of pre-emphasis is to be determined by characterization. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?68 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode figure 4?30 shows page 7 of the alt2gxb megawizard plug-in manager for xaui mode. figure 4?30. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis first post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. the amount of pre-emphasis is to be determined by characterization. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. the amount of pre-emphasis is to be determined by characterization. table 4?23. megawizard plug-in manager options (page 6 for xaui mode) (part 2 of 2) alt2gxb setting des cription reference
altera corporation 4?69 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?24 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?24. megawizard plug-in manager options (page 7 for xaui mode) alt2gxb setting des cription reference what do you want to be able to dynamically rec onfigure in the transceiver? available options are analog controls, enable adaptive equalizer control, and channel internals. analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel internals: enables mif-based reconfiguration to a xaui mode with different internal parameters. note that the enable channel and transmitter pll reconfiguration and use alternate reference clock options are not available in xaui mode. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is t he logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?70 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode figure 4?31 shows page 8 of the alt2gxb megawizard plug-in manager for xaui mode. figure 4?31. megawizard plug-in manager - alt2gxb (loopback)
altera corporation 4?71 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?25 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?25. megawizard plug-in manager options (page 8 for xaui mode) alt2gxb setting des cription reference which loopback option would you like? there are two option available in xaui mode: no loopback and serial loopback. no loopback - this is the default mode. serial loopback - if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. a 1'b1 enables serial loopback and a 1'b0 disables loopback on a channel-by-channel basis. altera recommends controlling all four channels simultaneously. a digital reset must be asserted for the transceiver. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. reverse loopback option this option is not available in xaui mode. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?72 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode figure 4?32 shows page 9 of the alt2gxb megawizard plug-in manager for xaui mode. if the enforce default settings for this protocol option is selected, this page does not appear in the megawizard. figure 4?32. megawizard plug-in manager - alt2gxb (xaui)
altera corporation 4?73 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?26 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?26. megawizard plug-in manager options (page 9 for xaui mode) (part 1 of 2) alt2gxb setting des cription reference enable run-length violation checking with a run length of this option activates the run-length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_patterndetect port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_ctrldetect port to indicate 8b/10b decoder has detected a control code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_errdetect port to indicate 8b/10b decoder has detected an error code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_disperr port to indicate 8b/10b decoder has detected a disparity error refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?74 altera corporation stratix ii gx device handbook, volume 2 october 2007 xaui mode create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?26. megawizard plug-in manager options (page 9 for xaui mode) (part 2 of 2) alt2gxb setting des cription reference
altera corporation 4?75 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?33 shows page 10 of the megawizard plug-in manager for the xaui protocol selection. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for the third party eda synthesis tool to be able to estimate timing and resource utilization for the alt2gxb instance. figure 4?33. megawizard plug-in manager - alt2gxb (eda)
4?76 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode figure 4?34 shows page 11 (the last page) of the megawizard plug-in manager for the xaui protocol set up. you can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?34. megawizard plug-in manager - alt2gxb (summary) gige mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for the gige mode. the megawizard plug-in manager provides a warning if any of the settings you choose are illegal. 1 the word aligner and rate matcher operations and patterns are pre-configured for the gige mode and cannot be altered.
altera corporation 4?77 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?35 shows page 3 of the alt2gxb megawizard plug-in manager for gige mode. figure 4?35. megawizard plug-in manager - alt2gxb (general) table 4?27 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?27. megawizard plug-in manager options (page 3 for gige mode) (part 1 of 3) alt2gxb setting description reference which protocol will you be using? selects the specific prot ocol or modes under which the transceiver operates. for the gige mode, you must select the gige protocol. which subprotocol will you be using? not applicable to gige mode.
4?78 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode enforce default settings for this protocol selecting this option skips the gige page of the gige megawizard plug-in manager. the gige page allows you to select the gige-specific ports for your design. if you select this option, all gige-specific ports are used. what is the operation mode? the transmitte r only and receiver and transmitter (full duplex) modes are allowed in gige protocol. the receiver only mode is not available. what is the number of channels? this selects how many duplicate channels this alt2gxb instance contains. in gige mode, the number of channels increments by 1. what is the deserializer block width? gige mode only operates in a single-width mode. double-width mode is not allowed. what is the channel width? this opti on determines the transceiver to pld interface width. in gige mode, 8 bits are allowed. byte serializer and byte deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option is not used because the data rate is fixed at 1.25 gbps for gige mode. what is the data rate? this option is no t used because the data rate is fixed at 1.25 gbps for gige mode. what is the input clock frequency? determines the input clock frequency or period you want as a reference clock for the transceiver. in gige mode, only 62.5 mhz and 125 mhz are allowed. what is the data rate division factor? this option is not used because the data rate is fixed at 1.25 gbps for gige mode. create rx_digitalreset port for the digital portion of the receiver receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?27. megawizard plug-in manager options (page 3 for gige mode) (part 2 of 3) alt2gxb setting description reference
altera corporation 4?79 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create rx_analogreset port for the analog portion of the receiver receiver analog reset port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port for the digital portion of the receiver transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?27. megawizard plug-in manager options (page 3 for gige mode) (part 3 of 3) alt2gxb setting description reference
4?80 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode figure 4?36 shows page 4 of the alt2gxb megawizard plug-in manager for gige mode. figure 4?36. megawizard plug-in manager - alt2gxb (pll/ports)
altera corporation 4?81 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?28 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?28. megawizard plug-in manager options (page 4 for gige mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if cmu pll reconfiguration is enabled, this option is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? in gige mode, only high bandwidth is supported for the transmitter pll. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? in gige mode, only medium bandwidth is supported for the receiver pll and v co . clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver cru switchover between lock-to-data and lock-to-reference. (there are additional factor s that affect cru's transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?82 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicate data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?28. megawizard plug-in manager options (page 4 for gige mode) (part 2 of 3) alt2gxb setting description reference
altera corporation 4?83 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create debug_rx_phase_comp_fi fo_error output port this optional output port indicates receiver phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp_fi fo_error output port this optional output port indicates transmitter phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?28. megawizard plug-in manager options (page 4 for gige mode) (part 3 of 3) alt2gxb setting description reference
4?84 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode figure 4?37 shows page 5 of the alt2gxb megawizard plug-in manager for gige mode. figure 4?37. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
altera corporation 4?85 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?29 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?29. megawizard plug-in manager options (page 5 for gige mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is set to 0.85 v. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. forced signal detection this option disabl es the signal detect circuit. this removes the signal detect criterion for the receiver cru lock-to-reference and lock-to-data switchover. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? use this option when the forced signal detection option is off and to set the trip point of the signal detect circuit. the levels are to be determined after characterization. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?86 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?29. megawizard plug-in manager options (page 5 for gige mode) (part 2 of 2) alt2gxb setting description reference
altera corporation 4?87 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?38 shows page 6 of the alt2gxb megawizard plug-in manager for gige mode. figure 4?38. megawizard plug-in manager - alt2gxb (tx analog)
4?88 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode table 4?30 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?30. megawizard plug-in manager options (page 6 for gige mode) (part 1 of 2) alt2gxb setting des cription reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. the selections available are 1.2 v and 1.5 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. restrictions apply based on the v cch setting. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. the amount of pre-emphasis is to be determined by characterization. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?89 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?39 shows page 7 of the alt2gxb megawizard plug-in manager for gige mode. figure 4?39. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis first post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. the amount of pre-emphasis is to be determined by characterization. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. the amount of pre-emphasis is to be determined by characterization. table 4?30. megawizard plug-in manager options (page 6 for gige mode) (part 2 of 2) alt2gxb setting des cription reference
4?90 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode table 4?31 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?31. megawizard plug-in manager options (page 7 for gige mode) alt2gxb setting des cription reference what do you want to be able to dynamically rec onfigure in the transceiver? available options are: analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel interface: enables mif-based reconfiguration among modes that have different pld interface signals. channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is t he logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?91 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?40 shows page 8 of the alt2gxb megawizard plug-in manager for gige mode. this page appears only when the channel internals or channel interface options are selected in the reconfig page (page 7). figure 4?40. megawizard plug-in manager - alt2gxb (reconfig alt pll) table 4?32 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?32. megawizard plug-in manager options (page 8 for gige mode) alt2gxb setting des cription reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?92 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode figure 4?41 shows page 9 of the alt2gxb megawizard plug-in manager for gige mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected on the reconfig page (page 7). figure 4?41. megawizard plug-in manager - alt2gxb (reconfig clks 1)
altera corporation 4?93 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?33 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?33. megawizard plug-in manager options (page 9 for gige mode) alt2gxb setting description reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/or receiver pll, this option allows you to select the clock source for the current configuration. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
4?94 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode figure 4?42 shows page 10 of the al t2gxb megawizard plug-in manager for gige mode. this page appears only when the channel internals and channel interface options are selected in the reconfig page (page 7). figure 4?42. megawizard plug-in m anager - alt2gxb (reconfig 2)
altera corporation 4?95 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?34 describes the available options on page 10 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?34. megawizard plug-in manager options (page 10 for gige mode) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?96 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode figure 4?43 shows page 11 of the alt2gxb megawizard plug-in manager for gige mode. figure 4?43. megawizard plug-in manager - alt2gxb (loopback)
altera corporation 4?97 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?35 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?35. megawizard plug-in manager options (page 11 for gige mode) alt2gxb setting des cription reference which loopback option would you like? there are two options in gige mode: no loopback and serial loopback. no loopback - this is the default mode. serial loopback - if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. a 1'b1 enables serial loopback and a 1'b0 disables loopback on a channel-by-channel basis. altera recommends controlling all four channels simultaneously. a digital reset must be asserted for the transceiver. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. reverse loopback option this option is not available in gige mode. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?98 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode figure 4?44 shows page 12 of the al t2gxb megawizard plug-in manager for gige mode. if the enforce default settings for this protocol option is selected, this page do es not appear in the megawizard. figure 4?44. megawizard plug-in manager - alt2gxb (gige)
altera corporation 4?99 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?36 describes the available options on page 12 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?36. megawizard plug-in manager options (page 12 for gige mode) (part 1 of 2) alt2gxb setting des cription reference enable run-length violation checking with a run length of this option activates the run-length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_patterndetect port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_ctrldetect port to indicate 8b/10b decoder has detected a control code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_errdetect port to indicate 8b/10b decoder has detected an error code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_disperr port to indicate 8b/10b decoder has detected a disparity error refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?100 altera corporation stratix ii gx device handbook, volume 2 october 2007 gige mode create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?36. megawizard plug-in manager options (page 12 for gige mode) (part 2 of 2) alt2gxb setting des cription reference
altera corporation 4?101 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?45 shows page 13 of the megawizard plug-in manager for the gige protocol selection. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for third party eda synthesis tool to be able to estima te timing and resource utilization for the alt2gxb instance. figure 4?45. megawizard plug-in manager - alt2gxb (eda)
4?102 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode figure 4?46 shows page 13 (the last page) of the megawizard plug-in manager for the gige protocol set up. you can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?46. megawizard plug-in manager - alt2gxb (summary) sonet/sdh mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for the sonet/sdh mode. the megawizard plug-in manager provides a warning if any of the setti ngs you choose are illegal.
altera corporation 4?103 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?47 shows page 3 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. figure 4?47. megawizard plug-in manager - alt2gxb (general)
4?104 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode table 4?37 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?37. megawizard plug-in manager options (page 3 for sonet/sdh mode) (part 1 of 2) alt2gxb setting description reference which protocol will you be using? selects the specific protocol or modes that the transceiver operates under. for the sonet/sdh mode, you must select the sonet/sdh protocol. which subprotocol will you be using? there are three subprotocols allowed in sonet/sdh mode: oc-48, oc-12, and oc-96. supported data rates are as follows: oc-48 ? 2488.32 mbps oc-12 ? 622 mbps oc-96 ? 4976 mbps enforce default settings for this protocol selecting this option skips the sonet page of the sonet/sdh megawizard plug-in manager. the sonet page allows you to select which sonet/sdh-specific port and word alignment pattern you want to use. if you select this option, all sonet/sdh-specific ports are used and the defaulted alignment pattern is locked at 16'hf628. what is the operation mode? the transmitt er only, receiver only, and receiver and transmitter (full duplex) modes are allowed in the sonet/sdh protocol. what is the number of channels? this selects how many duplicate channels this alt2gxb instance contains. in sonet/sdh mode, the number of channels increments by 1. what is the deserializer block width? this option sets the transceiver data path width. single width ? selected automatically in oc-12 and oc-48 configurations. the transceiver data path width is 8 bits. double width ? selected automatically in oc-96 configurations. the transceiver data path width is 16 bits. what is the channel width? this option se lects the transceiver to pld interface width. depending on the subprotocol selection, choose one of the following: 8 bits for oc-12 16 bits for oc-48 32 bits for oc-96 byte serializer and byte deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option is not used because the data rate is fixed at: 622 mbps for oc-12 2488.32 mbps for oc-48 4976 mbps for oc-96
altera corporation 4?105 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the data rate? this option is not used because the data rate is fixed at: 622 mbps for oc-12 2488.32 mbps for oc-48 4976 mbps for oc-96 what is the input clock frequency? indicates the input refer ence clock frequencies for the transceiver. oc-48 ? 77.76 mhz, 155.52 mhz, 311.04 mhz, and 622.08 mhz are allowed. oc-12 ? 62.2 mhz, 77.76 mhz, 155.52 mhz, 311 mhz, and 622 mhz are allowed oc-96 ? 124.4 mhz is allowed what is the data rate division factor? this option is not used because the data rate is fixed at: 622 mbps for oc-12 2488.32 mbps for oc-48 4976 mbps for oc-96 create rx_digitalreset port for the digital portion of the receiver receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_analogreset port for the analog portion of the receiver receiver analog reset port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port for the digital portion of the transmitter transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?37. megawizard plug-in manager options (page 3 for sonet/sdh mode) (part 2 of 2) alt2gxb setting description reference
4?106 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode figure 4?48 shows page 4 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. figure 4?48. megawizard plug-in manager - alt2gxb (pll/ports)
altera corporation 4?107 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?38 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?38. megawizard plug-in manager options (page 4 for sonet/sdh mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if the cmu pll reconfiguration option is enabled, it is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? this option is not available in sonet/sdh mode because the transmitter pll bandwidth is fixed at high. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? this option is not available in sonet/sdh mode because the receiver pll bandwidth is fixed at medium. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver cru switchover between lock-to-data and lock-to-reference. (there are additional factor s that affect cru's transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?108 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicate data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?38. megawizard plug-in manager options (page 4 for sonet/sdh mode) (part 2 of 3) alt2gxb setting description reference
altera corporation 4?109 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create debug_rx_phase_comp_fi fo_error output port this optional output port indicates receiver phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp_fi fo_error output port this optional output port indicates transmitter phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?38. megawizard plug-in manager options (page 4 for sonet/sdh mode) (part 3 of 3) alt2gxb setting description reference
4?110 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode figure 4?49 shows page 5 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. figure 4?49. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
altera corporation 4?111 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?39 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?39. megawizard plug-in manager options (page 5 for sonet/sdh mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is set to 0.85 v. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. force signal detection this option disabl es the signal detect circuit. this removes the signal detect criterion for the receiver cru lock-to-reference and lock-to-data switchover. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? use this option when the forced signal detection option is off and to set the trip point of the signal detect circuit. the levels are to be determined after characterization. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?112 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create active low cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?39. megawizard plug-in manager options (page 5 for sonet/sdh mode) (part 2 of 2) alt2gxb setting description reference
altera corporation 4?113 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?50 shows page 6 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. figure 4?50. megawizard plug-in manager - alt2gxb (tx analog)
4?114 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode table 4?40 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?40. megawizard plug-in manager options (page 6 for sonet/sdh mode) (part 1 of 2) alt2gxb setting des cription reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. the selections available are 1.2 v and 1.5 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. restrictions apply based on the v cch setting. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. the amount of pre-emphasis is to be determined by characterization. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?115 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?51 shows page 7 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. figure 4?51. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis first post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. the amount of pre-emphasis is to be determined by characterization. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. the amount of pre-emphasis is to be determined by characterization. table 4?40. megawizard plug-in manager options (page 6 for sonet/sdh mode) (part 2 of 2) alt2gxb setting des cription reference
4?116 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode table 4?41 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?41. megawizard plug-in manager op tions (page 7 for sonet/sdh mode) alt2gxb setting des cription reference what do you want to be able to dynamically rec onfigure in the transceiver? available options are: analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel interface: enables mif-based reconfiguration among modes that have different pld interface signals. channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is t he logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?117 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?52 shows page 8 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?52. megawizard plug-in manager - alt2gxb (reconfig alt pll)
4?118 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode table 4?42 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. figure 4?53 shows page 9 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?53. megawizard plug-in manager - alt2gxb (reconfig clks 1) table 4?42. megawizard plug-in manager op tions (page 8 for sonet/sdh mode) alt2gxb setting des cription reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?119 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?43 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?43. megawizard plug-in manager op tions (page 9 for sonet/sdh mode) alt2gxb setting description reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/or receiver pll, this option allows you to select the clock source for the current configuration. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter and/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
4?120 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode figure 4?54 shows page 10 of the al t2gxb megawizard plug-in manager for sonet/sdh mode. this page appears only when the channel internals or channel interface options are selected in the reconfig page (page 7). figure 4?54. megawizard plug-in m anager - alt2gxb (reconfig 2)
altera corporation 4?121 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?44 describes the available options on page 10 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?44. megawizard plug-in manager op tions (page 10 for sonet/sdh mode) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?122 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode figure 4?55 shows page 11 of the alt2gxb megawizard plug-in manager for sonet/sdh mode. figure 4?55. megawizard plug-in manager - alt2gxb (loopback)
altera corporation 4?123 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?45 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?45. megawizard plug-in manager op tions (page 11 for sonet/sdh mode) alt2gxb setting des cription reference which loopback option would you like? there are two options available in sonet/sdh mode: no loopback and serial loopback. no loopback - this is the default mode. serial loopback - if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. a 1'b1 enables serial loopback and a 1'b0 disables loopback on a channel-by-channel basis. altera recommends controlling all four channels simultaneously. a digital reset must be asserted for the transceiver. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. reverse loopback option this option is not available in sonet/sdh mode. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?124 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode figure 4?56 shows page 12 of the al t2gxb megawizard plug-in manager for sonet/sdh mode. if the enforce default settings for this protocol option is selected, this page does not appear in the megawizard. figure 4?56. megawizard plug-in manager - alt2gxb (sonet)
altera corporation 4?125 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?46 describes the available options on page 12 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?46. megawizard plug-in manager options (page 12 for sonet/sdh mode) (part 1 of 3) alt2gxb setting des cription reference what should the word aligner realign? in sonet/sdh mode, the word aligner is defaulted to manual alignment. the re-alignment is also defaulted to occur following a rising edge of the rx_enapatternalign input signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the word alignment pattern length? this option sets the length of the word alignment. the following options are available: oc-12 ? only 16-bit pattern is allowed oc-48 ? only 16-bit pattern is allowed oc-96 ? 16-bit and 32-bit patterns are allowed sonet/sdh mode (oc-12, oc-48, and oc-96) section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the word alignment pattern? enter the word alignment pattern here. by default, the pattern that appears in the megawizard plug-in manager is 0001010001101111 (16'h146f). sonet/sdh mode (oc-12, oc-48, and oc-96) section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip word alignment pattern bits this op tion reverses the order of the alignment pattern at a byte level to support msb to lsb transmission protocols such as sonet/sdh. (this option is used in conjunction with the flip receiver output data bits and flip transmitter input data bits options.) by default, this option is selected in the megawizard plug-in manager. sonet/sdh mode (oc-12, oc-48, and oc-96) section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what do you want the byte ordering to be based on? this option allows you to trigger the byte ordering block either on the rising edge of rx_syncstatus signal or user-controlled rx_enabyteord signal from the pld. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?126 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode enable run-length violation checking with a run-length of when enabled, this option activates the run length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_patterndetect output port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?46. megawizard plug-in manager options (page 12 for sonet/sdh mode) (part 2 of 3) alt2gxb setting des cription reference
altera corporation 4?127 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide flip receiver output data bits this option reverses the bit order of the receiver output data ( rx_dataout ) at a byte level to support msb to lsb transmission protocols such as sonet/sdh. sonet/sdh mode (oc-12, oc-48, and oc-96) section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip transmitter input data bits this opti on reverse the bit order of the transmitter input data ( tx_datain ) at a byte level to support msb to lsb transmission protocols such as sonet/sdh. sonet/sdh mode (oc-12, oc-48, and oc-96) section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?46. megawizard plug-in manager options (page 12 for sonet/sdh mode) (part 3 of 3) alt2gxb setting des cription reference
4?128 altera corporation stratix ii gx device handbook, volume 2 october 2007 sonet/sdh mode figure 4?57 shows page 13 of the megawizard plug-in manager for the sonet/sdh protocol selection. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for third party eda synthesis tool to be able to estima te timing and resource utilization for the alt2gxb instance. figure 4?57. megawizard plug-in manager - alt2gxb (eda)
altera corporation 4?129 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?58 shows page 14 (the last page) of the megawizard plug-in manager for the sonet/sdh protocol set up. you can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?58. megawizard plug-in manager - alt2gxb (summary) (oif) cei phy interface mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for the (oif) cei phy interface mode. the megawizard plug-in manager provides a warning if any of th e settings you choose are illegal.
4?130 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode figure 4?59 shows page 3 of the alt2gxb megawizard plug-in manager for (oif) cei phy interface mode. figure 4?59. megawizard plug-in manager - alt2gxb (general) table 4?47 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?47. megawizard plug-in manager options (page 3 for [oif] cei phy interface mode) (part 1 of 3) alt2gxb setting description reference which protocol will you be using? selects the specific protocol or modes that the transceiver operates under. for the (oif) cei phy interface mode, you must select the (oif) cei phy interface protocol. which subprotocol will you be using? this option does not apply to the (oif) cei phy interface mode.
altera corporation 4?131 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide enforce default settings for this protocol if this option is checked, all (oif) cei phy interface-specific ports are used. what is the operation mode? the transmitt er only, receiver only, and receiver and transmitter (full duplex) modes are allowed in the (oif) cei phy interface mode. what is the number of channels? this selects how many duplicate channels this alt2gxb instance contains. in (oif) cei phy interface mode, the number of channels increments by 1. what is the deserializer block width? the (oif) cei phy interface operates in double-width mode only. single-width mode is not allowed. what is the channel width? this option se lects the transceiver to pld interface width. only 32 bits are allowed in (oif) cei phy interface mode. byte serializer and byte deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option is fixed to data rate in (oif) cei phy interface mode. what is the data rate? this field allows you to enter the data rate. in (oif) cei phy mode, you can enter a data rate between 3125 gbps and 6375 gbps. (oif) cei phy interface mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the input clock frequency? this field allows you to select the available input reference clock frequencies in (oif) cei phy interface mode. (oif) cei phy interface mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the data rate division factor? this option is not available in (oif) cei phy interface mode. create rx_digitalreset port for the digital portion of the receiver receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?47. megawizard plug-in manager options (page 3 for [oif] cei phy interface mode) (part 2 of 3) alt2gxb setting description reference
4?132 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode create rx_analogreset port for the analog portion of the receiver receiver analog reset port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port for the digital portion of the transmitter transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?47. megawizard plug-in manager options (page 3 for [oif] cei phy interface mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?133 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?60 shows page 4 of the alt2gxb megawizard plug-in manager for (oif) cei phy interface mode. figure 4?60. megawizard plug-in manager - alt2gxb (pll/ports)
4?134 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode table 4?48 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?48. megawizard plug-in manager options (page 4 for [oif] cei phy interface mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if cmu pll reconfiguration is enabled, this option is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? in (oif) cei phy interface mode, only medium bandwidth is supported for the transmitter pll. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? in (oif) cei phy interface mode, only medium bandwidth is supported for the receiver pll and vco. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver cru switchover between lock-to-data and lock-to-reference. (there are additional factor s that affect cru's transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?135 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicate data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?48. megawizard plug-in manager options (page 4 for [oif] cei phy interface mode) (part 2 of 3) alt2gxb setting description reference
4?136 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode create debug_rx_phase_comp_fi fo_error output port this optional output port indicates receiver phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp_fi fo_error output port this optional output port indicates transmitter phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?48. megawizard plug-in manager options (page 4 for [oif] cei phy interface mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?137 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?61 shows page 5 of the alt2gxb megawizard plug-in manager for (oif) cei phy interface mode. figure 4?61. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
4?138 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode table 4?49 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?49. megawizard plug-in manager options (page 5 for [oif] cei phy interface mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is set to 0.85 v. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. force signal detection this option disabl es the signal detect circuit. this removes the signal detect criterion for the receiver cru lock-to-reference and lock-to-data switchover. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? use this option when the forced signal detection option is off and to set the trip point of the signal detect circuit. the levels are to be determined after characterization. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?139 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?49. megawizard plug-in manager options (page 5 for [oif] cei phy interface mode) (part 2 of 2) alt2gxb setting description reference
4?140 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode figure 4?62 shows page 6 of the alt2gxb megawizard plug-in manager for (oif) cei phy interface mode. figure 4?62. megawizard plug-in manager - alt2gxb (tx analog)
altera corporation 4?141 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?50 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?50. megawizard plug-in manager options (page 6 for [oif] cei phy interface mode) (part 1 of 2) alt2gxb setting des cription reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. only 1.5 .v is allowed in (oif) cei phy interface mode. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. only 0.6 v is allowed in (oif) cei phy interface mode. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. the amount of pre-emphasis is to be determined by characterization. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?142 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode figure 4?63 shows page 7 of thealt2gxb megawizard plug-in manager for (oif) cei phy interface mode. figure 4?63. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis first post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. the amount of pre-emphasis is to be determined by characterization. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. the amount of pre-emphasis is to be determined by characterization. table 4?50. megawizard plug-in manager options (page 6 for [oif] cei phy interface mode) (part 2 of 2) alt2gxb setting des cription reference
altera corporation 4?143 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?51 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?51. megawizard plug-in manager options (page 7 for [oif] cei phy interface mode) alt2gxb setting des cription reference what do you want to be able to dynamically rec onfigure in the transceiver? available options are: analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel interface: enables mif-based reconfiguration among modes that have different pld interface signals. channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is t he logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?144 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode figure 4?64 shows page 8 of the alt2gxb megawizard plug-in manager for (oif) cei phy interface mode. this page appears only if the channel internals and enable channel and transmitter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?64. megawizard plug-in manager - alt2gxb (reconfig alt pll) table 4?52 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?52. megawizard plug-in manager options (page 8 for [oif] cei phy interface mode) alt2gxb setting description reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?145 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?65 shows page 9 of the alt2gxb megawizard plug-in manager for (oif) cei phy interface mode. this page appears only if the channel internals and enable channel and transmitter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?65. megawizard plug-in manager - alt2gxb (reconfig clks 1)
4?146 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode table 4?53 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?53. megawizard plug-in manager options (page 9 for [oif] cei phy interface mode) alt2gxb setting description reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/or receiver pll, this option allows you to select the clock source for the current configuration. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter and/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?147 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?66 shows page 10 of the megawizard plug-in manager for the (oif) cei phy interface protocol select ion. this page appears only when the channel internals or channel interface option is selected in the reconfig page (page 7). figure 4?66. megawizard plug-in m anager - alt2gxb (reconfig 2)
4?148 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode table 4?54 describes the available options on page 10 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?54. megawizard plug-in manager options (page 10 for [oif] cei phy interface mode) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?149 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?67 shows page 11 of the megawizard plug-in manager for the (oif) cei phy interfac e protocol selection. figure 4?67. megawizard plug-in manager - alt2gxb (loopback)
4?150 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode table 4?55 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?55. megawizard plug-in manager options (page 11 for [oif] cei phy interface mode) alt2gxb setting des cription reference which loopback option would you like? there are two options available in (oif) cei phy interface mode: no loopback and serial loopback. no loopback - this is the default mode. serial loopback - if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. a 1'b1 enables serial loopback and a 1'b0 disables loopback on a channel-by-channel basis. altera recommends controlling all four channels simultaneously. a digital reset must be asserted for the transceiver. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. reverse loopback option this option is not available in (oif) cei phy interface mode. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?151 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?68 shows the cei page of the megawizard plug in manager for the (oif) cei phy interface protocol selection. if the enforce default settings for this protoc ol option is selected, this page does not appear in the megawizard. the use central clock divider to improve transmitter jitter option allows you to set-up bun dled clocking for channels within the same transceiver block to improve transmitter jitter performance. this option is not available if the channel interface or channel internals options with alternate pll or cmu pll reconfiguration are selected. figure 4?68. megawizard plug-in manager - alt2gxb (cei)
4?152 altera corporation stratix ii gx device handbook, volume 2 october 2007 (oif) cei phy interface mode figure 4?69 shows page 13 of the megawizard plug-in manager for the (oif) cei phy interface protocol se lection. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for third party eda synthesis too l to be able to estimate timing and resource utilization for the alt2gxb instance. figure 4?69. megawizard plug-in manager - alt2gxb (eda)
altera corporation 4?153 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?70 shows page 14 (the last page) of the megawizard plug-in manager for the (oif) cei phy interface protocol set up. you can select optional files on this page. afte r you make your selections, click finish to generate the files. figure 4?70. megawizard plug-in manager - alt2gxb (summary) cpri mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for the cpri mode. the megawizard plug-in manager provides a warning if any of the settings you choose are illegal.
4?154 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode figure 4?71 shows page 3 of the alt2gxb megawizard plug-in manager for cpri mode. figure 4?71. megawizard plug-in manager - alt2gxb (general) table 4?56 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?56. megawizard plug-in manager options (page 3 for cpri mode) (part 1 of 3) alt2gxb setting description reference which protocol will you be using? selects the specific prot ocol or modes under which the transceiver operates. for the cpri mode, you must select the cpri protocol. which subprotocol will you be using? this option is not available in cpri mode.
altera corporation 4?155 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide enforce default settings for this protocol this option is not available in cpri mode. what is the operation mode? the transmitt er only, receiver only, and receiver and transmitter (full duplex) modes are allowed in cpri protocol. what is the number of channels? this selects how many duplicate channels this alt2gxb instance contains. in cpri mode, the number of channels increments by 1. a maximum of 16 cpri channels can be instantiated in the largest stratix ii gx device (ep2sgx130g) due to clocking constraints. cpri mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the deserializer block width? cpri mode only operates in a single-width mode. double-width mode is not allowed. what is the channel width? this opti on determines the transceiver to pld interface width. in cpri mode, 8 bits are allowed. byte serializer and byte deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option is forced to data rate . what is the data rate? three cpri data rates are supported: 614 mbps 1228 mbps 2456 mbps. what is the input clock frequency? determines the input clock frequency you want as a reference clock for the transceiver. what is the data rate division factor? this setting, in conjunction with the selected data rate, determines the effective data rate for the transceiver channel. create rx_digitalreset port for the digital portion of the receiver receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?56. megawizard plug-in manager options (page 3 for cpri mode) (part 2 of 3) alt2gxb setting description reference
4?156 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode create rx_analogreset port for the analog portion of the receiver receiver analog reset port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port for the digital portion of the transmitter transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?56. megawizard plug-in manager options (page 3 for cpri mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?157 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?72 shows page 4 of the alt2gxb megawizard plug-in manager for cpri mode. figure 4?72. megawizard plug-in manager - alt2gxb (pll/ports)
4?158 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode table 4?57 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?57. megawizard plug-in manager options (page 4 for cpri mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if cmu pll reconfiguration is enabled, this option is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? in cpri mode, only high bandwidth is supported for the transmitter pll. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? in cpri mode, only medium bandwidth is supported for the receiver pll and v co . clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver cru switchover between lock-to-data and lock-to-reference. (there are additional factor s that affect cru's transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?159 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicate data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?57. megawizard plug-in manager options (page 4 for cpri mode) (part 2 of 3) alt2gxb setting description reference
4?160 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode create debug_rx_phase_comp_fi fo_error output port this optional output port indicates receiver phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp_fi fo_error output port this optional output port indicates transmitter phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?57. megawizard plug-in manager options (page 4 for cpri mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?161 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?73 shows page 5 of the alt2gxb megawizard plug-in manager for cpri mode. figure 4?73. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
4?162 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode table 4?58 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?58. megawizard plug-in manager options (page 5 for cpri mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is set to 0.85 v. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. forced signal detection this option disabl es the signal detect circuit. this removes the signal detect criterion for the receiver cru lock-to-reference and lock-to-data switchover. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? use this option when the forced signal detection option is off and to set the trip point of the signal detect circuit. the levels are to be determined after characterization. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?163 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?58. megawizard plug-in manager options (page 5 for cpri mode) (part 2 of 2) alt2gxb setting description reference
4?164 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode figure 4?74 shows page 6 of the alt2gxb megawizard plug-in manager for cpri mode. figure 4?74. megawizard plug-in manager - alt2gxb (tx analog)
altera corporation 4?165 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?59 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?59. megawizard plug-in manager options (page 6 for cpri mode) (part 1 of 2) alt2gxb setting des cription reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. the selections available are 1.2 v and 1.5 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. restrictions apply based on the v cch setting. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. the amount of pre-emphasis is to be determined by characterization. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?166 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode figure 4?75 shows page 7 of the alt2gxb megawizard plug-in manager for cpri mode. figure 4?75. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis first post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. the amount of pre-emphasis is to be determined by characterization. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. the amount of pre-emphasis is to be determined by characterization. table 4?59. megawizard plug-in manager options (page 6 for cpri mode) (part 2 of 2) alt2gxb setting des cription reference
altera corporation 4?167 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?60 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?60. megawizard plug-in manager options (page 7 for cpri mode) alt2gxb setting des cription reference what do you want to be able to dynamically rec onfigure in the transceiver? available options are: analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel interface: enables mif-based reconfiguration among modes that have different pld interface signals. channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is t he logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?168 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode figure 4?40 shows page 8 of the alt2gxb megawizard plug-in manager for cpri mode. this page appears only when the channel internals or channel interface options are selected in the reconfig page (page 7). figure 4?76. megawizard plug-in manager - alt2gxb (reconfig alt pll) table 4?61 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?61. megawizard plug-in manager options (page 8 for cpri mode) alt2gxb setting des cription reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?169 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?77 shows page 9 of the alt2gxb megawizard plug-in manager for cpri mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected on the reconfig page (page 7). figure 4?77. megawizard plug-in manager - alt2gxb (reconfig clks 1)
4?170 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode table 4?62 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?62. megawizard plug-in manager options (page 9 for cpri mode) alt2gxb setting description reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/or receiver pll, this option allows you to select the clock source for the current configuration. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?171 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?78 shows page 10 of the al t2gxb megawizard plug-in manager for cpri mode. this page appears only when the channel internals or channel interface options are selected in the reconfig page (page 7). figure 4?78. megawizard plug-in m anager - alt2gxb (reconfig 2)
4?172 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode table 4?63 describes the available options on page 10 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?63. megawizard plug-in manager options (page 10 for cpri mode) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?173 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?79 shows page 11 of the alt2gxb megawizard plug-in manager for cpri mode. figure 4?79. megawizard plug-in manager - alt2gxb (loopback)
4?174 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode table 4?64 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?64. megawizard plug-in manager options (page 11 for cpri mode) alt2gxb setting des cription reference which loopback option would you like? there are two options available in cpri mode: no loopback and serial loopback. no loopback - this is the default mode. serial loopback - if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. a 1'b1 enables serial loopback and a 1'b0 disables loopback on a channel-by-channel basis. altera recommends controlling all four channels simultaneously. a digital reset must be asserted for the transceiver. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. reverse loopback option this option is not available in cpri mode. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?175 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?80 shows page 12 of the al t2gxb megawizard plug-in manager for cpri mode. if the enforce default settings for this protocol option is selected, this page do es not appear in the megawizard. figure 4?80. megawizard plug-in manager - alt2gxb (cpri 1)
4?176 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode table 4?65 describes the available options on page 12 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?65. megawizard plug-in manager options (page 12 for cpri mode) (part 1 of 2) alt2gxb setting des cription reference enable byte ordering block this option is not available in cpri mode. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable 8b/10b decoder/encoder this option is forced selected in cpri mode since 8b/10b decoder/encoder is always used. 8b/10 encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_forcedisp to enable force disparity and use tx_dispval to code up the incoming word using positive or negative disparity this option allows you to force positive or negative disparity on transmitted data in 8b/10b configurations. 8b/10 encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable rate match fifo this option is not available in cpri mode since the rate match fifo is always bypassed. rate matcher section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip receiver output data bits this option reverses the bit order of the data at the receiver-pld interface at a byte level to support msbit to lsbit transmission protocols. the default transmission order is lsbit to msbit. flip transmitter input data bits this option reverses the bit order of the data bits at the input of the transmitter at a byte level to support msbit to lsbit transmission protocols. the default transmission order is lsbit to msbit.
altera corporation 4?177 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide enable transmitter bit revers al this option inverts (flips) the bit order of the data bits at the transmitter pcs-pma interface at a byte level to support msbit to lsbit transmission protocols. the default tr ansmission is lsbit to msbit. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?65. megawizard plug-in manager options (page 12 for cpri mode) (part 2 of 2) alt2gxb setting des cription reference
4?178 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode figure 4?81 shows page 13 of the al t2gxb megawizard plug-in manager for cpri mode. figure 4?81. megawizard plug-in manager - alt2gxb (cpri 2)
altera corporation 4?179 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?66 describes the available options on page 13 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?66. megawizard plug-in manager options (page 13 for cpri mode) (part 1 of 3) alt2gxb setting des cription reference use manual word alignment mode this option is not available in cpri mode as the word aligner is synchronization state machine based. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use manual bit slipping mode this option is not available in cpri mode as the word aligner is synchronization state machine based. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use the built-in 'synchronization state machine' this option is forced selected in cpri mode. this option sets the word aligner to use the built-in synchronization state machine. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of bad data words before loss of synch state use this option with the built-in state machine to transition from a synchronized state to an unsynchronized state. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of consecutive valid words before synch state is reached this option sets the word aligner to check for a given number of good code groups. use this option with the built-in synchronization state machine in conjunction with the number of valid patterns before synchronization state is reached option to achieve synchronization. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook number of valid patterns before synch state is reached this option checks for the number of valid alignment patterns seen. use this option with the built-in synchronization state machine in conjunction with the number of consecutive valid words before synch state is reached option to achieve synchronization. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook
4?180 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode what is the word alignment pattern length? this option sets the word alignment length. the available choices are 7 bit and 10 bit. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the word alignment pattern? enter the word alignment pattern here. the length of the alignment pattern is based on the word alignment pattern length. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip word alignment pattern bits this optio n reverses the bit order of the alignment pattern at a byte level to support msb to lsb transmission protocols. the default transmission order is lsb to msb. enable run-length violation checking with a run length of this option activates the run-length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable word aligner output reverse bit ordering this option statically conf igures the receiver to reverse the bit order of the data at the output of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?66. megawizard plug-in manager options (page 13 for cpri mode) (part 2 of 3) alt2gxb setting des cription reference
altera corporation 4?181 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create rx_patterndetect port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_ctrldetect port to indicate 8b/10b decoder has detected a control code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_errdetect port to indicate 8b/10b decoder has detected an error code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_disperr port to indicate 8b/10b decoder has detected a disparity code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_revbyteorderwa to enable receiver symbol swap this option is not available in cp ri mode. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?66. megawizard plug-in manager options (page 13 for cpri mode) (part 3 of 3) alt2gxb setting des cription reference
4?182 altera corporation stratix ii gx device handbook, volume 2 october 2007 cpri mode figure 4?82 shows page 14 of the megawizard plug-in manager for the cpri protocol selection. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for third party eda synthesis tool to be able to estima te timing and resource utilization for the alt2gxb instance. figure 4?82. megawizard plug-in manager - alt2gxb (eda)
altera corporation 4?183 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?83 shows page 15 (the last page) of the megawizard plug-in manager for the cpri protocol set up. yo u can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?83. megawizard plug-in manager - alt2gxb (summary) sdi mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for the sdi mode. the megawizard plug-in manager provides a warning if any of the settings you choose are illegal.
4?184 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode figure 4?84 shows page 3 of the alt2gxb megawizard plug-in manager for sdi mode. figure 4?84. megawizard plug-in manager - alt2gxb (general)
altera corporation 4?185 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?67 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?67. megawizard plug-in manager opti ons (page 3 for sdi mode) (part 1 of 2) alt2gxb setting description reference which protocol will you be using? selects the specific prot ocol or modes under which the transceiver operates. for the sdi mode, you must select the sdi protocol. which subprotocol will you be using? in sdi mode, the two available subprotocols are: 3g: third-generation (3 gbps) sdi at 2970 mbps or 2967 mbps hd: high-definition sdi at 1485 mbps or 1483.5 mbps enforce default settings for this protocol this option is not available in sdi mode. what is the operation mode? the transmitt er only, receiver only, and receiver and transmitter (full duplex) modes are allowed in sdi protocol. what is the number of channels? this selects how many duplicate channels this alt2gxb instance contains. what is the deserializer block width? sdi mode only operates in a single-width mode. double-width mode is not allowed. what is the channel width? this opti on determines the transceiver to pld interface width. in sdi mode, 10-bit and 20-bit channel widths are allowed. in 10-bit configuration, the byte serializer is not used. in 20-bit configuration, the byte serializer is used. byte serializer and byte deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option not available in sdi mode. what is the data rate? this field is automatically set based on the subprotocol (3g or hd) and the input clock frequency selection. what is the input clock frequency? four input reference clock options are available, depending on the subprotocol (3g or hd). for 3g subprotocol the available options are: 148.5 mhz and 297 mhz for 2970 mbps data rate and 148.35 mhz and 296.7 mhz for 2967 mbps data rate for hd subprotocol the available option are: 74.25 mhz and 148.5 mhz for 1485 mbps data rate and 74.175 mhz and 148.35 mhz for 1483.5 mbps data rate
4?186 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode what is the data rate division factor? this option is not available in sdi mode. create rx_digitalreset port for the digital portion of the receiver receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_analogreset port for the analog portion of the receiver receiver analog reset port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port for the digital portion of the receiver transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?67. megawizard plug-in manager opti ons (page 3 for sdi mode) (part 2 of 2) alt2gxb setting description reference
altera corporation 4?187 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?85 shows page 4 of the alt2gxb megawizard plug-in manager for sdi mode. figure 4?85. megawizard plug-in manager - alt2gxb (pll/ports)
4?188 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode table 4?68 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?68. megawizard plug-in manager opti ons (page 4 for sdi mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if cmu pll reconfiguration is enabled, this option is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? three available bandwidth options are high, medium and low. the default transmitter pll bandwidth is high. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? three available bandwidth options are high, medium and low. the default receiver pll bandwidth is medium. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver cru switchover between lock-to-data and lock-to-reference. (there are additional factor s that affect cru's transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?189 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicate data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?68. megawizard plug-in manager opti ons (page 4 for sdi mode) (part 2 of 3) alt2gxb setting description reference
4?190 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode create debug_rx_phase_comp_fi fo_error output port this optional output port indicates receiver phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp_fi fo_error output port this optional output port indicates transmitter phase compensation fifo overflow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?68. megawizard plug-in manager opti ons (page 4 for sdi mode) (part 3 of 3) alt2gxb setting description reference
altera corporation 4?191 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?86 shows page 5 of the alt2gxb megawizard plug-in manager for sdi mode. figure 4?86. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
4?192 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode table 4?69 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?69. megawizard plug-in manager opti ons (page 5 for sdi mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is set to 0.85 v. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. force signal detection this option if force-se lected in sdi mode. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? this option is not available in sd i mode. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?193 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?69. megawizard plug-in manager opti ons (page 5 for sdi mode) (part 2 of 2) alt2gxb setting description reference
4?194 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode figure 4?87 shows page 6 of the alt2gxb megawizard plug-in manager for sdi mode. figure 4?87. megawizard plug-in manager - alt2gxb (tx analog)
altera corporation 4?195 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?70 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?70. megawizard plug-in manager opti ons (page 6 for sdi mode) (part 1 of 2) alt2gxb setting des cription reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. the selections available are 1.2 v and 1.5 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. restrictions apply based on the v cch setting. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. the amount of pre-emphasis is to be determined by characterization. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?196 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode figure 4?75 shows page 7 of the alt2gxb megawizard plug-in manager for sdi mode. figure 4?88. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis first post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. the amount of pre-emphasis is to be determined by characterization. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. the amount of pre-emphasis is to be determined by characterization. table 4?70. megawizard plug-in manager opti ons (page 6 for sdi mode) (part 2 of 2) alt2gxb setting des cription reference
altera corporation 4?197 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?71 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?71. megawizard plug-in manager options (page 7 for sdi mode) alt2gxb setting des cription reference what do you want to be able to dynamically rec onfigure in the transceiver? available options are: analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel interface: enables mif-based reconfiguration among modes that have different pld interface signals. channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is t he logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?198 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode figure 4?89 shows page 8 of the alt2gxb megawizard plug-in manager for sdi mode. this page appears only when the channel internals or channel interface options are selected in the reconfig page (page 7). figure 4?89. megawizard plug-in manager - alt2gxb (reconfig alt pll) table 4?72 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?72. megawizard plug-in manager options (page 8 for sdi mode) alt2gxb setting des cription reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?199 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?90 shows page 9 of the alt2gxb megawizard plug-in manager for sdi mode. this page appears only if the channel internals and enable channel and transm itter pll reconfiguration options are selected on the reconfig page (page 7). figure 4?90. megawizard plug-in manager - alt2gxb (reconfig clks 1)
4?200 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode table 4?73 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?73. megawizard plug-in manager options (page 9 for sdi mode) alt2gxb setting description reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/or receiver pll, this option allows you to select the clock source for the current configuration. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock sources for the transmitter and/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?201 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?91 shows page 10 of the al t2gxb megawizard plug-in manager for sdi mode. this page appears only when the channel internals or channel interface options are selected in the reconfig page (page 7). figure 4?91. megawizard plug-in m anager - alt2gxb (reconfig 2)
4?202 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode table 4?74 describes the available options on page 10 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?74. megawizard plug-in manager options (page 10 for sdi mode) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?203 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?92 shows page 11 of the alt2gxb megawizard plug-in manager for sdi mode. figure 4?92. megawizard plug-in manager - alt2gxb (loopback)
4?204 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode table 4?75 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?75. megawizard plug-in manager options (page 11 for sdi mode) alt2gxb setting des cription reference which loopback option would you like? there are two options available in sdi mode: no loopback and serial loopback. no loopback - this is the default mode. serial loopback - if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. a 1'b1 enables serial loopback and a 1'b0 disables loopback on a channel-by-channel basis. altera recommends controlling all four channels simultaneously. a digital reset must be asserted for the transceiver. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. reverse loopback option this option is not available in sdi mode. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?205 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?93 shows page 12 of the al t2gxb megawizard plug-in manager for sdi mode. if the enforce default setting s for this protocol option is selected, this page do es not appear in the megawizard. figure 4?93. megawizard plug-in manager - alt2gxb (sdi 1)
4?206 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode table 4?74 describes the available options on page 12 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?76. megawizard plug-in manager options (page 12 for sdi mode) (part 1 of 2) alt2gxb setting des cription reference enable byte ordering block this option is not available in sdi mode. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable 8b/10b decoder/encoder this option is force-selected in sdi mode since 8b/10b decoder/encoder is always used. 8b/10 encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_forcedisp to enable force disparity and use tx_dispval to code up the incoming word using positive or negative disparity this option allows you to force positive or negative disparity on transmitted data in 8b/10b configurations. 8b/10 encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable rate match fifo this option is not available in sdi mode since the rate match fifo is always bypassed. rate matcher section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip receiver output data bits this option reverses the bit order of the data at the receiver-pld interface at a byte level to support msbit to lsbit transmission protocols. the default transmission order is lsbit to msbit. flip transmitter input data bits this option reverses the bit order of the data bits at the input of the transmitter at a byte level to support msbit to lsbit transmission protocols. the default transmission order is lsbit to msbit.
altera corporation 4?207 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide enable transmitter bit revers al this option inverts (flips) the bit order of the data bits at the transmitter pcs-pma interface at a byte level to support msbit to lsbit transmission protocols. the default tr ansmission is lsbit to msbit. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?76. megawizard plug-in manager options (page 12 for sdi mode) (part 2 of 2) alt2gxb setting des cription reference
4?208 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode figure 4?94 shows page 13 of the al t2gxb megawizard plug-in manager for sdi mode. figure 4?94. megawizard plug-in manager - alt2gxb (sdi 2)
altera corporation 4?209 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?77 describes the available options on page 13 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?77. megawizard plug-in manager options (page 13 for sdi mode) (part 1 of 3) alt2gxb setting des cription reference use manual word alignment mode this option is not available in sdi mode as the word aligner is synchronization state machine based. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use manual bit slipping mode this option is not available in sdi mode as the word aligner is synchronization state machine based. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use the built-in 'synchronization state machine' this option is force-selected in sdi mode. this option sets the word aligner to use the built-in synchronization state machine. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of bad data words before loss of synch state use this option with the built-in synchronization state machine to transition from a synchronized state to an unsynchronized state. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of consecutive valid words before synch state is reached this option sets the word aligner to check for a given number of good code groups. use this option with the built-in synchronization state machine in conjunction with the number of valid patterns before synchronization state is reached option to achieve synchronization. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook number of valid patterns before synch state is reached this option checks for the number of valid alignment patterns seen. use this option with the built-in synchronization state machine in conjunction with the number of consecutive valid words before synch state is reached option to achieve synchronization. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook
4?210 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode what is the word alignment pattern length? this option sets the word alignment length. the available choices are 7 bit and 10 bit. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the word alignment pattern? enter the word alignment pattern here. the length of the alignment pattern is based on the word alignment pattern length. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip word alignment pattern bits this optio n reverses the bit order of the alignment pattern at a byte level to support msb to lsb transmission protocols. the default transmission order is lsb to msb. enable run-length violation checking with a run length of this option activates the run-length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable word aligner output reverse bit ordering this option statically conf igures the receiver to reverse the bit order of the data at the output of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?77. megawizard plug-in manager options (page 13 for sdi mode) (part 2 of 3) alt2gxb setting des cription reference
altera corporation 4?211 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create rx_patterndetect port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_ctrldetect port to indicate 8b/10b decoder has detected a control code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_errdetect port to indicate 8b/10b decoder has detected an error code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_disperr port to indicate 8b/10b decoder has detected a disparity code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_revbyteorderwa to enable receiver symbol swap this option is not available in sdi mode. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?77. megawizard plug-in manager options (page 13 for sdi mode) (part 3 of 3) alt2gxb setting des cription reference
4?212 altera corporation stratix ii gx device handbook, volume 2 october 2007 sdi mode figure 4?82 shows page 14 of the megawizard plug-in manager for the sdi protocol selection. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for third party eda synthesis tool to be able to estima te timing and resource utilization for the alt2gxb instance. figure 4?95. megawizard plug-in manager - alt2gxb (eda)
altera corporation 4?213 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?83 shows page 15 (the last page) of the megawizard plug-in manager for the sdi protocol set up. you can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?96. megawizard plug-in manager - alt2gxb (summary) serial rapidio mode this section provides descriptions of the options available on the individual pages of the alt2gxb megawizard plug-in manager for serial rapidio mode. the megawi zard plug-in manager provides a warning if any of the setti ngs you choose are illegal.
4?214 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?97 shows page 3 of the alt2gxb megawizard plug-in manager in serial rapidio mode. figure 4?97. megawizard plug-in manager - alt2gxb (general) table 4?78 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?78. megawizard plug-in manager options (p age 3 for serial rapidio mode) (part 1 of 2) alt2gxb setting description reference which protocol will you be using? determines the specific protocol or modes under which the transceiver operates. for serial rapidio mode, you must select the serial rapidio protocol. which subprotocol will you be using? this option is not available in serial rapidio mode. enforce default settings for this protocol this option is not available in serial rapidio mode.
altera corporation 4?215 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide what is the operation mode? the available operation modes are receiver only, transmitter only, and receiver and transmitter. what is the number of channels? this option determines how many duplicate channels this alt2gxb instance contains. what is the deserializer block width? serial rapidio mode only operates in a single-width mode. double-width mode is not allowed. what is the channel width? the channel wi dth is fixed to16 in serial rapidio mode. byte serializer and deserializer sections in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what would you like to base the setting on? this option is not available in serial rapidio mode. what is the data rate? enter 1250 mbps, 2500 mbps, or 3125 mbps depending on your design requirements. what is the input clock frequency? determines the input clock frequency you want as a reference clock for the transceiver. what is the data rate division factor? this option is not available in serial rapidio mode. create rx_digitalreset port receiver digital reset port. resets the pcs portion of the receiver. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_analogreset port receiver analog reset port. reset control and power down? section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_digitalreset port transmitter digital reset port. resets the pcs portion of the transmitter. altera recommends using this port along with logic to implement the recommended reset sequence. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?78. megawizard plug-in manager options (p age 3 for serial rapidio mode) (part 2 of 2) alt2gxb setting description reference
4?216 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?98 shows page 4 of the alt2gxb megawizard plug-in manager for serial rapidio mode. figure 4?98. megawizard plug-in manager - alt2gxb (pll/ports)
altera corporation 4?217 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?79 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?79. megawizard plug-in manager options (p age 4 for serial rapidio mode) (part 1 of 3) alt2gxb setting description reference train receiver pll clock from pll inclk if you turn this option on, your design uses the input reference clock to the transmitter pll to train the receiver pll. this reduces the need to supply a separate receiver pll reference clock. if cmu pll reconfiguration is enabled, this option is automatically enabled by the megawizard plug-in manager. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the gxb transmitter pll bandwidth mode? the quartus ii software automatically selects the high bandwidth setting in serial rapidio mode. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver pll bandwidth mode? the quartus ii software automatically selects the medium bandwidth setting in serial rapidio mode. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the acceptable ppm threshold between the receiver pll vco and the cru clock? this option determines the ppm difference that affects the automatic receiver clock recovery unit (cru) switchover between lock-to-data and lock-to-reference. (there are additional factors that affect the cru's transition.) clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_powerdown port to power down the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create gxb_enable port to enable the quad refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. reset control and power down section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?218 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode create pll_locked port to indicate pll is in lock with the reference input clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock multiplier unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktorefclk port to lock the rx pll to the reference clock refer to the stratix ii gx stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_locktodata port to lock the rx pll to the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_pll_locked port to indicate rx pll is in lock with the reference clock refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_freqlocked port to indicate rx pll is in lock with the received data refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. clock recovery unit section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_signaldetect port to indicated data input signal detection refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. receiver buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?79. megawizard plug-in manager options (p age 4 for serial rapidio mode) (part 2 of 3) alt2gxb setting description reference
altera corporation 4?219 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create debug_rx_phase_comp _fifo_error output port this optional output port indicates receiver phase compensation fifo over flow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. receiver phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create debug_tx_phase_comp _fifo_error output port this optional output port indicates transmitter phase compensation fifo over flow/underrun condition. note that no ppm difference is allowed between fifo read and write clocks. this port should be used for debug purpose only. transmitter phase compensation fifo section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_coreclk port to connect to the read clock of the rx phase compensation fifo this optional input port allows you to clock the read side of the receiver phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_coreclk port to connect to the write clock of the tx phase compensation fifo this optional input port allows you to clock the write side of the transmitter phase compensation fifo with a non-transceiver pld clock. transceiver clocking section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?79. megawizard plug-in manager options (p age 4 for serial rapidio mode) (part 3 of 3) alt2gxb setting description reference
4?220 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?99 shows page 5 of the alt2gxb megawizard plug-in manager for serial rapidio mode. figure 4?99. megawizard plug-in manager - alt2gxb (rx analog/cal blk)
altera corporation 4?221 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?80 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?80. megawizard plug-in manager options (p age 5 for serial rapidio mode) (part 1 of 2) alt2gxb setting description reference enable static equalizer control this option enables the static equalizer settings. if the equalizer settings are not changed through the dynamic reconfiguration controller, the equalizer remains configured to these static settings. enabling the equalizer control enables the equalizer dc gain option. this dc gain option can be used in conjunction with equalizer controls and has three legal settings. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is programmable between 0.85 v and 1.2 v. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. force signal detection this option is availabl e only in pipe mode. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the signal detect and signal loss threshold? use this option when the forced signal detection option is off and to set the trip point of the signal detect circuit. this option is available only in pipe mode. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external receiver termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). if checked, this option turns off the receiver oct. receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the receiver termination resistance? this option selects the receiver termination value. the settings allowed are 100 , 120 , and 150 . receiver buffer section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?222 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode use calibration block this option allows you to select which instance of alt2gxb instantiates the calibration block. only one instance of alt2gxb is required to instantiate the calibration block. calibration blocks section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. create active low cal_blk_powerdown to power down the calibration block refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. calibration blocks section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?80. megawizard plug-in manager options (p age 5 for serial rapidio mode) (part 2 of 2) alt2gxb setting description reference
altera corporation 4?223 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?100 shows page 6 of the alt2gxb megawizard plug-in manager for serial rapidio mode. figure 4?100. megawizard plug-in manager - alt2gxb (tx analog)
4?224 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode table 4?81 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?81. megawizard plug-in manager options (p age 6 for serial rapidio mode) (part 1 of 2) alt2gxb setting description reference what is the transmitter buffer power (v cch )? this setting is for information only and is used to calculate the v od from the buffer power supply (v cch ) and the transmitter termination to derive the proper v od range. the selections available are 1.2 v and 1.5 v. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage setting is between 0.7 v and 0.6 v. restrictions apply based on the v cch setting. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use external transmitter termination this option is available if you want to use an external termination resistor instead of the on-chip termination (oct). checking this option turns off the transmitter oct. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. select the transmitter termination resistance this option selects the transmitter termination value. this option is also used in the calculation of the available v od . transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on v cch and the transmitter termination resistance value. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. pre-emphasis pre-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. transmitter buffer section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
altera corporation 4?225 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?101 shows page 7 of the alt2gxb megawizard plug-in manager for serial rapidio mode. figure 4?101. megawizard plug-in manager - alt2gxb (reconfig) pre-emphasis fi rst post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. pre-emphasis second post-tap setting (% of v od ) this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. table 4?81. megawizard plug-in manager options (p age 6 for serial rapidio mode) (part 2 of 2) alt2gxb setting description reference
4?226 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode table 4?82 describes the available options on page 7 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?82. megawizard plug-in manager options (page 7 for serial rapidio mode) alt2gxb setting description reference what do you want to be able to dynamically reconfigure in the transceiver? available options are: analog controls: dynamically reconfigures the pma control settings like vod, pre-emphasis, equalization, etc. enable adaptive equalizer control: dynamically enables adaptive equalization for the selected receiver channel. channel interface: enables mif-based reconfiguration among modes that have different pld interface signals. channel internals: enables mif-based reconfiguration among modes that have different data paths within the channel but have the same pld interface signals. when this option is enabled, two mutually exclusive options, enable channel and transmitter pll reconfiguration and use alternate reference clock , are available. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the starting channel number? the range for the dynamic reconfiguration starting channel number setting is 0?156, in multiples of 4. it is in multiples of 4 because the dynamic reconfiguration interface is per transceiver block. the range of 0?156 is the logical channel address, based purely on the number of possible alt2gxb instances. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?227 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?102 shows page 8 of the alt2gxb megawizard plug-in manager for serial rapidio mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration option is selected in the reconfig page (page 7). figure 4?102. megawizard plug-in manager - alt2gxb (reconfig alt pll) table 4?83 describes the available options on page 8 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?83. megawizard plug-in manager options (page 8 for serial rapidio mode) alt2gxb setting description reference use alternate transmitter pll and receiver pll selecting this option sets up the transmitter channel to listen to one of the two plls in its transceiver block. the information regarding which pll it listens to is stored in the mif. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
4?228 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?103 shows page 9 of the alt2gxb megawizard plug-in manager for serial rapidio mode. this page appears only if the channel internals and the enable channel and transm itter pll reconfiguration options are selected in the reconfig page (page 7). figure 4?103. megawizard plug-in manager - alt2gxb (reconfig clks 1)
altera corporation 4?229 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?84 describes the available options on page 9 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. figure 4?104 shows page 10 of the alt2gxb megawizard plug-in manager for serial rapidio mode. this page appears only if the channel internals or the channel interface options are selected in the reconfig page (page 7). table 4?84. megawizard plug-in manager options (page 9 for serial rapidio mode) alt2gxb setting description reference what is the main pll logical reference clock index? this option allows you to select the logical index for the pll that you intend to use with the current configuration. this option is meaningful only if you select the use alternate transmitter pll and receiver pll option on the reconfig alt pll page. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how many input clocks? this field allows you to select the number of reference clock inputs needed to meet your cmu pll reconfiguration design goals. a maximum of five input reference clocks are allowed. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the transmitter pll and receiver pll? if you select more than one input reference clock sources for the transmitter and/ or receiver pll, this option allows you to select the clock source for the current configuration. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the selected input clock source for the alternate transmitter pll and receiver pll? if you select the use alternate transmitter pll and receiver pll option, you can select the clock source for the alternate transmitter pll and the receiver pll. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the reconfig protocol driven by clock 0?.4? if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to select the functional mode for the respective reference clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . what is the clock 0?.4 input frequency? if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to select the reference clock frequencies for each clock source. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use clock 1....4 reference clock divider if you select more than one input reference clock source for the transmitter an d/or receiver pll, these options allow you to instruct the megawizard about the refclk pre-divider on input reference clocks. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook.
4?230 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?104. megawizard plug-in manager - alt2gxb (reconfig 2) table 4?85 describes the available options on page 10 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?85. megawizard plug-in manager options (p age 10 for serial rapidio mode) (part 1 of 2) alt2gxb setting description reference how should the receivers be clocked? three options are available: share a single transmitter core clock between receivers use the respective channel transmitter core clock use the respective channel receiver core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . how should the transmitters be clocked? two options are available: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 4?231 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create rx_revbitorderwa input port to use receiver enable bit reversal this optional input port al lows you to dynamically reverse the bit order at the output of the receiver word aligner. word aligner section in the stratix ii gx tr a n s c e i ve r architecture overview chapter in volume 2 of the stratix ii gx device handbook. check a control box to use the corresponding control port you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver to. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . table 4?85. megawizard plug-in manager options (p age 10 for serial rapidio mode) (part 2 of 2) alt2gxb setting description reference
4?232 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?105 shows page 11 of the alt2gxb megawizard plug-in manager for serial rapidio mode. figure 4?105. megawizard plug-in manager - alt2gxb (loopback)
altera corporation 4?233 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?86 describes the available options on page 11 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?86. megawizard plug-in manager opti ons (page 11 for seri al rapidio mode) alt2gxb setting des cription reference which loopback option would you like? there are two options available in rapidio mode: no loopback and serial loopback. no loopback - this is the default mode. serial loopback - if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. a 1'b1 enables serial loopback and a 1'b0 disables loopback on a channel-by-channel basis. a digital reset must be asserted for the transceiver. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. reverse loopback option this option is not available in serial rapidio mode. loopback modes section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?234 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?106 shows page 12 of the megawizard plug-in manager for the serial rapidio protocol set up. figure 4?106. megawizard plug-in manager - alt2gxb (sr i/o 1)
altera corporation 4?235 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?87 describes the available options on page 12 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?87. megawizard plug-in manager opti ons (page 12 for seri al rapidio mode) alt2gxb setting description reference enable byte ordering block this option is not available in serial rapidio mode. byte ordering block section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable 8b/10b decoder/encoder the 8b/10b decoder/encoder is always enabled in serial rapidio mode. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_forcedisp to enable force disparity and use tx_dispval to code up the incoming word using positive or negative disparity this option is not available in serial rapidio mode. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable rate match fifo this option is not available in serial rapidio mode. rate matcher section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip receiver output data bits this option is not available in serial rapidio mode. flip transmitter input data bits this option is not available in serial rapidio mode. enable transmitter bit reversal this option inverts (flips) the bit order of the data bits at the transmitter pcs-pma interface at a byte level to support msbit to lsbit transmission protocols. the default transmission is lsbit to msbit. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_invpolarity to enable word aligner polarity inversion this optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create tx_invpolarity to allow transmitter polarity inversion this optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter pcs-pma interface. 8b/10b encoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?236 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?107 shows page 13 of the megawizard plug-in manager for the serial rapidio protocol set up. figure 4?107. megawizard plug-in manager - alt2gxb (sr i/o 2)
altera corporation 4?237 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide table 4?88 describes the available options on page 13 of the megawizard plug-in manager for your alt2gxb custom megafunction variation. table 4?88. megawizard plug-in manager options (p age 13 for serial rapidio mode) (part 1 of 3) alt2gxb setting description reference use manual word alignment mode this option is not available in serial rapidio mode as the word aligner is synchronization state machine based. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use manual bit slipping mode this option is not available in serial rapidio mode as the word aligner is synchronization state machine based. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. use the built-in 'synchronization state machine' this option is always enabled in serial rapidio mode as the word aligner is synchronization state machine based. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of bad data words before loss of synch state the quartus ii software forces this field to 3 to comply with the serial rapidio specification. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of consecutive valid words before synch state is reached the quartus ii software forces this field to 255 to comply with the serial rapidio specification. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. number of valid patterns before synch state is reached the quartus ii software forces this field to 127 to comply with the serial rapidio specification. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. what is the word alignment pattern length? the quartus ii software only allows a 10-bit wide word alignment pattern. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?238 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode what is the word alignment pattern? the quartus ii software defaults the word alignment pattern to k28.5- (10?b0101111100). word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. flip word alignment pattern bits this option reverses the bit order of the alignment pattern at a byte level to support msb to lsb transmission protocols. the default transmission order is lsb to msb. enable run-length violation checking with a run length of this option activates the run-length violation circuit. you can program the run length at which the circuit triggers the rx_rlv signal. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. enable word aligner output reverse bit ordering in manual bit-slip mode, this option creates an input port rx_revbitorderwa to dynamically reverse the bit order at the output of the receiver word aligner. in other modes, this option statically configures t he receiver to always reverse the bit order of the data at the output of the word aligner. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_syncstatus output port for pattern detector and word aligner refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_patterndetect port to indicate pattern detected refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_ctrldetect port to indicate 8b/10b decoder has detected a control code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?88. megawizard plug-in manager options (p age 13 for serial rapidio mode) (part 2 of 3) alt2gxb setting description reference
altera corporation 4?239 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide create rx_errdetect port to indicate 8b/10b decoder has detected an error code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_disperr port to indicate 8b/10b decoder has detected a disparity code refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook for information about this port. 8b/10b decoder section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. create rx_revbyteorderwa to enable receiver symbol swap this option is not available in serial rapidio mode. word aligner section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook. table 4?88. megawizard plug-in manager options (p age 13 for serial rapidio mode) (part 3 of 3) alt2gxb setting description reference
4?240 altera corporation stratix ii gx device handbook, volume 2 october 2007 serial rapidio mode figure 4?108 shows page 14 of the megawizard plug-in manager for the serial rapidio protocol set up. the generate simulation model creates a behavioral model ( .vo or .vho ) of the transceiver instance for third-party simulators. the generate netlist option generates a netlist for the third party eda synthesis tool to estimate timing and resource utilization for the alt2gxb instance. figure 4?108. megawizard plug-in manager - alt2gxb (eda)
altera corporation 4?241 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide figure 4?109 shows page 15 (last page) of the megawizard plug-in manager for the serial rapidio protocol set up. you can select optional files on this page. after you make your selections, click finish to generate the files. figure 4?109. megawizard plug-in manager - alt2gxb (summary) referenced documents this chapter references the following documents: stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook.
4?242 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history document revision history table 4?89 shows the revision history for this chapter. table 4?89. document revision history (part 1 of 2) date and document version changes made summary of changes october 2007, v4.2 updated the entire chapter. all tables updated. all figures updated. ? new sections added: ?cpri mode? ?sdi mode? ?serial rapidio mode? ? added the ?referenced documents? section. ? august 2007, v4.1 updated the ?which subprotocol will you be using?? section in table 4?1. updated the ?what is the input clock frequency?? section in table 4?32. updated table 4?16. updated ?reference? column in table 4?2. ? updated figure 4?22. ? formerly chapter 3. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. ? february 2007 v4.0 added the ?document revision history? section to this chapter. ? this entire chapter was updated. all the tables were updated and all new graphics were included. ? june 2006, v3.2 updated megawizard plug-in manager figures for page 6 for all modes and page 9 for pipe mode. updated table 3?11 to include enable fast recovery mode option. ? april 2006, v3.1 updated all the megawizard plug-in manager figures to match the quartus ii software gui. updated tables 3?3, 3?8, 3?9, 3?13, 3?20, 3?25, 3?26, 3?29, 3?31, and 3?32. ? february 2006, v3.0 updated technical content throughout chapter. added ?(oif) cei phy interface mode? section. ?
altera corporation 4?243 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide december 2005, v2.0 added xaui, gige, and sonet sections. ? october 2005 v1.0 added chapter to the stratix ii gx device handbook . ? table 4?89. document revision history (part 2 of 2) date and document version changes made summary of changes
4?244 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history
altera corporation 4?245 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb megafunction user guide
4?246 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history
altera corporation 5?1 october 2007 5. stratix ii gx alt2gxb_reconfig megafunction user guide introduction the megawizard ? plug-in manager in the quartus ? ii software creates or modifies design files that contain custom megafunction variations. these auto-generated megawizard files can then be instantiated in a design file. the megawizard plug-in manager prov ides a megawizard that allows you to specify options for the alt2gxb_reconfig megafunction. start the megawizard plug-in manager using one of the following methods: choose the megawizard plug-in manager command (tools menu). when working in the block editor (schematic symbol), click megawizard plug-in manager in the symbol dialog box (edit menu > insert symbol). start the stand-alone version of the megawizard plug-in manager by typing the following command at the command prompt: qmegawiz . dynamic reconfiguration this section provides descriptions of the options available on the individual pages of the alt2gxb_reconfig megawizard plug-in manager. 1 the megawizard plug-in manager provides a warning if any of the settings you choose are illegal. figure 5?1 shows the first page of the megawizard plug-in manager. to generate an alt2gxb_reconfig custom megafunction variation, select create a new custom megafunction variation . click next . figure 5?1. megawizard plug-in manager (page 1) siigx52006-1.4
5?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration figure 5?2 shows the second page of th e megawizard plug-in manager. select the following options (click next when you are done): alt2gxb_reconfig megafunction option, under the i/o folder. stratix ii gx as the device family. your desired type of output file format ( verilog , vhdl , or ahdl ). your desired file name. 1 for the design to compile successfully, you must enable the dynamic reconfiguratio n controller in the alt2gxb instance. figure 5?2. megawizard plug-in ma nager - alt2gxb_reconfig (page 2)
altera corporation 5?3 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb_reconfig megafunction user guide figure 5?3 shows page 3 of the alt2gxb_reconfig megawizard plug-in manager. from the drop-down menu, select the number of channels controlled by the reconfig controller. check off the reconfig controller features that you would li ke to activate; for example, analog controls, channel reconfiguration, change the local divider values of the transmitter or channel and tx pll reconfiguration. figure 5?3. megawizard plug-in manager - alt2g xb_reconfig (reconfi guration settings) table 5?1 describes the available options on page 3 of the megawizard plug-in manager for your alt2gxb_ reconfig custom megafunction variation. select the match project/default option if you want to change the device currently selected device family options. make your selections on page 3 and click next .
5?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration table 5?1. megawizard plug-in manager options (page 3) (part 1 of 2) alt2gxb_reconfig setting description reference what is the number of channels controlled by the reconfig controller? depending on this setting, alt2gxb_reconfig generates the required signal width for the interface signal (reconfig_fromgxb) to alt2gxb and also gives the necessary bus width for all the selected physical media attachment (pma) signals. for this setting, altera ? recommends that if there are multiple controllers for multiple instances of alt2gxb , then the setting is same as the number of channels set in the alt2gxb instance. if a single controller controls multiple instances of alt2gxb , the setting is rounded up to the multiple of the nearest transceiver (for t he number of transceivers needed to fit the channels selected for that instance). depending on the number of channels set, the resource estimate changes because this is a soft implementation that uses fabric logic resources. the resource estimate is shown in the bottom left of page 3 of the megawizard. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 5?5 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb_reconfig megafunction user guide what are the features to be reconfigured by the reconfig controller? three available selections are: analog controls ? allows dynamic reconfiguration of pma settings like e qualization, pre-emphasis, dc gain, and v od channel reconfiguration ? allows dynamic reconfiguration of the tr ansceiver channel from one pre-configured functional mode to another pre-configured functional mode. this includes switching from one protocol to another, as well as a data rate switch within basic mode. for example, dynamic reconfiguration from sonet/sdh to gige mode. data rate division in tx ? allows dynamic switch of the cmu local clock divider. division factors of 1, 2, and 4 are supported. for example, dynamic rate switching of the transmitter from 4 gbps to 2 gbps to 1 gbps. channel and tx pll select/reconfig ? the following three features are available under this option: tx pll reconfiguration ? allows dynamic reconfiguration of the tx pll only. channel and tx pll reconfiguration ? allows dynamic reconfiguration of the transceiver channel from one protocol mode to another and allows reconfiguration of the tx pll. channel reconfiguration with tx pll select ? allows dynamic reconfiguration of the transceiver channel and allows selecting one of the two tx plls that the channel can listen to. enable adaptive equalization control ? this feature is currently not supported. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . table 5?1. megawizard plug-in manager options (page 3) (part 2 of 2) alt2gxb_reconfig setting description reference
5?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration figure 5?4 shows page 4 of the alt2gxb_reconfig megawizard plug-in manager. page 4 appears only if analog controls is selected in the "what are the features to be reconfigured by the reconfig controller?" setting on page 3. figure 5?4. megawizard plug-in manager - alt2gxb_reconfig (a nalog controls) table 5?2 describes the available options on page 4 of the megawizard plug-in manager for your alt2gxb_ reconfig custom megafunction variation. make your selections on page 4 and click next .
altera corporation 5?7 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb_reconfig megafunction user guide table 5?2. megawizard plug-in manager options (page 4) (part 1 of 2) alt2gxb_reconfig setting description reference use the same control signal for all channels (grayed out in figure 5?4 ) in figure 5?4 , this option is grayed out because it is not applicable for a one-channel instance. if the number of channels controll ed by the controller is more than one, this setting is enabled. the setting is checked if the design needs the same control signal written into all channels simultaneously. if the design requires the control signal to write in and read out of individual channels, then the setting is not checked. dynamic reconfiguration setup in the megawizard plug-in manager section in the stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
5?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration write control pma write control signals are as follows: voltage output differential (v od ) ? 3 bits per channel pre-emphasis control pr e-tap ? 4 bits per channel pre-emphasis control 1st post-tap ? 4 bits per channel pre-emphasis control 2nd post-tap ? 4 bits per channel equalizer control ? 4 bits per channel equalizer dc gain ? 2 bits per channel these are optional signals. the signal widths are based on the setting you entered for the ?what is the number of channels controlled by the controller?? option. at least one write signal must be enabled to configure and use the dynamic reconfiguration controller. channels and pma controls reconfiguration section of the stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . read control pma read control signals are: voltage output differential (v od ) pre-emphasis control pr e-tap ? 4 bits per channel pre-emphasis control 1st post-tap ? 4 bits per channel pre-emphasis control 2nd post-tap ? 4 bits per channel equalizer control ? 4 bits per channel equalizer dc gain ? 2 bits per channel these are optional signals. the signal widths are based on the setting you entered for the ?what is the number of channels controlled by the controller?? option. the read out option is enabled for selection if the corresponding write control is selected. the read out option enable is not independent of write control. read and write cannot be performed simultaneously into these pma read control signals and pma write control signals. channels and pma controls reconfiguration section of the stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . table 5?2. megawizard plug-in manager options (page 4) (part 2 of 2) alt2gxb_reconfig setting description reference
altera corporation 5?9 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb_reconfig megafunction user guide figure 5?5 shows page 5 of the alt2gxb_reconfig megawizard plug-in manager. page 5 appears only if channel reconfiguration is selected in the "what are the features to be reconfigured by the reconfig controller?" setting on page 3. figure 5?5. megawizard plug-in manager - alt2gxb_r econfig (channel and tx pll reconfiguration) table 5?3 describes the available options on page 5 of the megawizard plug-in manager for your alt2gxb_ reconfig custom megafunction variation. make your signal select ion on page 5 and click next .
5?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration table 5?3. megawizard plug-in manager options (page 5) (part 1 of 2) alt2gxb_reconfig setting description reference use reconfig_address_out the value on this optional port indicates the address associated with the words (reconfig instructions) in the .mif. each dynamic configurati on feature requires a maximum of 28 or 38 addresses. for example, if the channel reconfiguration feature is selected, the dynamic reconfiguration controller automatically increments the address from 0 to 27. if the channel and tx pll reconfiguration feature is selected, the address is incremented from 0 to 37. therefore, the width of the reconfig_address_out is set to either 5-bits or 6-bits wide, depending on the feature selected. the dynamic reconfiguration controller automatically increments the address at the end of each write cycle. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use reconfig_address_en when high, this optional output status signal indicates that the address to be used in the write cycle has changed. this signal gets asserted when the write transaction is completed ( busy signal de-asserted). stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use reset_reconfig_address when asserted, this opt ional control signal resets the current reconfiguration address to 0. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
altera corporation 5?11 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb_reconfig megafunction user guide use logical_tx_pll_sel this is an optional control signal. the functionality of the signal depends on the feature selected, as shown below: tx pll reconfiguration ? the corresponding tx pll is reconfigured based on the value on this signal. channel and tx pll reconfiguration ? the corresponding tx pll is reconfigured based on the value on this signal. the transceiver channel listens to the tx pll selected by this signal. channel reconfiguration with tx pll select - the transceiver channel listens to the tx pll selected by this signal. channel and cmu pll reconfiguration section in the stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use logical_tx_pll_sel_en this is an optional c ontrol signal. when this signal is enabled in the alt2gxb_reconfig megawizard, the value set on the logical_tx_pll_sel signal is valid only if the logical_tx_pll_sel_en is set to 1 . for more information, refer to the ?logical tx pll select? section in the stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . channel and cmu pll reconfiguration section in the stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . table 5?3. megawizard plug-in manager options (page 5) (part 2 of 2) alt2gxb_reconfig setting description reference
5?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration figure 5?6 shows page 6 of the alt2gxb_reconfig megawizard plug-in manager. page 6 appears only if the data rate division in tx is selected in the "what are the features to be reconfigured by the reconfig controller?" setting on page 3. figure 5?6. megawizard plug-in manager - alt2gxb_r econfig (error checks /data rate switch) table 5?4 describes the available options on page 6 of the megawizard plug-in manager for your alt2gxb_ reconfig custom megafunction variation. make your selections on page 6 and click next .
altera corporation 5?13 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb_reconfig megafunction user guide figure 5?7 shows page 7 (the simulat ion libraries page) of the megawizard plug-in manager fo r the dynamic reconfiguration selection. click next . table 5?4. megawizard plug-in manager options (page 6) alt2gxb_reconfig setting description reference enable illegal mode checking when this option is selected, the alt2gxb_reconfig mega wizard provides the error output port. the dynamic reconfiguration controller checks for spec ific unsupported options within 2 reconfig_clk cycles, de-asserts the busy signal and asserts the error output port for 2 reconfig_clk cycles. the dynamic reconfiguration controller does not execute the unsupported operation. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . enable self recovery when this option is selected, the alt2gxb_reconfig mega wizard provides the error output port. the dynamic reconfiguration controller quits an operation if it did not complete within the expected number of clock cycles. after recovering from the illegal operation, the dynamic reconfiguration controller de-asserts the busy signal and asserts the error output port for 2 reconfig_clk cycles. stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook . use the rate_switch_out port to read out the current data rate division values. this optional output status port reads out the current setting on the cmu local divider. 00 ? division of 1 01 ? division of 2 10 ? division of 4 11 ? illegal value (do not use this value) stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook .
5?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 dynamic reconfiguration figure 5?7. megawizard plug-in manager - al t2gxb_reconfig (sim ulation libraries) table 5?5 describes the available option on page 7 of the megawizard plug-in manager for your alt2gxb_ reconfig custom megafunction variation. make your selections on page 7 and click next table 5?5. megawizard plug-in manager options (page 7) alt2gxb_reconfig setting description generate a netlist for synthesis area and timing estimation selecting this option generates a netlist file that third party synthesis tool s can use to estimate the timing and resource usage
altera corporation 5?15 october 2007 stratix ii gx device handbook, volume 2 stratix ii gx alt2gxb_reconfig megafunction user guide figure 5?8 shows page 8 (the last page) of the megawizard plug-in manager for the dynamic reconfiguration protocol set up. you can select optional files on this page. afte r you make your selections, click finish to generate the files. figure 5?8. megawizard plug-in manager - alt2gxb_reconfig (summary) referenced document this chapter references the following document: stratix ii gx dynamic reconfiguration chapter in volume 2 of the stratix ii gx device handbook
5?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history document revision history table 5?6 shows the revision history for this chapter. table 5?6. document revision history date and document version changes made summary of changes october 2007 v1.4 updated table 5?4 .? updated all the figures in this chapter. ? added ?referenced document? section. ? august 2007 v1.3 updated figures 5?2 through 5?8. ? updated tables 5?1 through 5?4. ? added table 5?5. ? formerly chapter 4. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. ? february 2007 v1.2 modified ?introduction?. removed one sentence. added the ?document revision history? section to this chapter. ? changed alt2gxb_reconfig to alt2gxb_reconfig throughout. per new style guide convention. added more information describing figures 5?2 and 5?3. ? updated ?use reconfig_address_out ? section of table 5?3. ? updated ?use the rate_switch_out port to read out the current data rate division value? section of table 5?4. ? added ?click next ? instructions after each step. ? april 2006, v1.1 updated all the megawizard plug-in manager figures to match the quartus ii software gui. ? february 2006, v1.0 added chapter to the stratix ii gx device handbook. ?
altera corporation 6?1 october 2007 6. specifications & additional information transceiver blocks table 6?1 shows the transceive r blocks for stratix ? ii gx and stratix gx devices and compares their features. table 6?1. stratix ii gx features versus stratix gx features (part 1 of 2) blocks features strati x gx stratix ii gx data rate 500 mbps to 3.1875 gbps 600 mbps to 6.375 gbps data path single width single or double width native protocol suppor t basic, xaui, gige, sonet/sdh basic, xaui, gige, sonet/sdh (oc-12, oc-48, oc-96), pipe, (oif) cei phy interface, cpri, serial rapidio, sdi cmu transmitter pll single transmitter pll for entire transceiver block multiple transmitter plls refclk one reference clock per transceiver block two reference clocks per transceiver block 8b/10b polarity inversion v transmitter buffer low-power mode v tr i - s t a t e v receiver detect v v od and pe v - dynamic signals v - dynamic signals receiver buffer eq v - dynamic signals v - dynamic signals siigx52004-3.1
6?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 transceiver blocks word aligner synchronization sm gige and xaui only available in basic single-width, pipe, xaui, and gige modes 32-bit pattern v 20-bit pattern v 16-bit pattern vv 10-bit pattern vv 8-bit pattern v 7-bit pattern vv bit slip vv rate matcher gige and xaui only available in basic, pipe, xaui, and gige modes byte ordering v loopback serial vv - all modes except pci express (pipe) mode parallel vv - only in basic mode reverse serial vv - no longer dynamic pipe reverse parallel v - pipe mode only post 8b/10b v bist prbs 7 v - only in basic double-width mode prbs 8 (1) v prbs 10 vv - only in basic double-width mode low frequency (2) v high frequency (2) v mixed frequency (2) v incremental (2) vv - only in parallel loopback mode notes to ta b l e 6 ? 1 : (1) non-8b/10b. (2) with 8b/10b encoding. table 6?1. stratix ii gx features versus stratix gx features (part 2 of 2) blocks features strati x gx stratix ii gx
altera corporation 6?3 october 2007 stratix ii gx device handbook, volume 2 specifications & additional information 8b/10b code this section provides information about the data and control codes for stratix ii gx devices. code notation the 8b/10b data and control codes ar e referred to as dx.y and kx.y, respectively. the 8-bit byte (h g f e d c b a, where h is the msb and a is the lsb) is broken up into two grou ps, x and y, where x is the five lower bits (e d c b a) and y is the upper three bits (h g f). figure 6?1 shows the designation for 3c hex. figure 6?1. sample notation for 3c hex there are 256 dx.y and 12 kx.y valid 8-bit codes. these codes have two 10-bit equivalent codes associated with each 8-bit code. the 10-bit codes have either a neutral disparity or a non-neutral disparity. with neutral disparity, two neutral disparity 10-bit codes are associated with an 8-bit code. with non-neutral disparity 10-bi t code, a positive and a negative disparity code are associated with the 8-bit code. the positive disparity 10-bit code is associated in the rd- column. the negative disparity 10-bit code is associated in the rd+ column. disparity calculation the running disparity is calculated based on the sub-blocks of the 10-bit code. the 10-bit code is divided into two sub blocks, a 6-bit sub-block (abcdei) and a 4-bit sub-block (fghj), as shown in figure 6?2 . figure 6?2. 10-bit grouping of 6-bit and 4-bit sub-blocks 0 0 1 1 1 1 y = 1 x = 28 0 0 hgf edcba d28.1 (3c hex) = 0 0 1 11 1 1 0 0 jhgf iedcb 0 a d28.1 (3c hex) = 10-bit code 10-bit code 4-bit block 4-bit block 6-bit block 6-bit block
6?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 8b/10b code the running disparity at the beginning of the 6-bit sub-block is running disparity at the end of the previous 10-bit code. the running disparity of the 4-bit sub-block is the running disparity of the end of the 6-bit sub-block. the running disparity of th e end of the 4-bit sub-block is the running disparity of the 10-bit code (refer to figure 6?3 ). figure 6?3. running dispar ity between sub-blocks the running disparity calculation rules are as follows: the current running disparity at the end of a sub-block is positive if any of the following is true: the sub-block contains more ones than zeros the 6-bit sub-block is 6'b000111 the 4-bit sub-block is 4'b0011 the current running disparity at the end of a sub-block is negative if any of the following is true: the sub-block contains more zeros than ones the 6-bit sub-block is 6'b111000 the 4-bit sub-block is 4'b1100 if those conditions are not met, the running disparity at the end of the sub-block is the same as at the beginning of the sub-block. supported codes the 8b/10b scheme defines the 12 control codes listed in table 6?2 for synchronization, alignment, and general application purposes. 0 0 1 11 1 1 0 0 jhgf iedcb 0 a d28.1 (3c hex) = 10-bit code 10-bit code 4-bit block 4-bit block 6-bit block 6-bit block table 6?2. supported k codes (part 1 of 2) k code octal value 8-bit code hgf_edcba 10-bit code rd- abcdei_fghj 10-bit code rd+ abcdei_fghj k28.0 1c 8?b000_11100 10?b001111_0100 10?b110000_1011 k28.1 3c 8?b001_11100 10?b001111_1001 10?b110000_0110 k28.2 5c 8?b010_11100 10?b001111_0101 10?b110000_1010
altera corporation 6?5 october 2007 stratix ii gx device handbook, volume 2 specifications & additional information table 6?3 shows the valid data code-groups. k28.3 7c 8?b011_11100 10?b001111_0011 10?b110000_1100 k28.4 9c 8?b100_11100 10?b001111_0010 10?b110000_1101 k28.5 (1) bc 8?b101_11100 10?b001111_1010 10?b110000_0101 k28.6 dc 8?b110_11100 10?b001111_0110 10?b110000_1001 k28.7 fc 8?b111_11100 10?b001111_1000 10?b110000_0111 k23.7 f7 8?b111_10111 10?b111010_1000 10?b000101_0111 k27.7 fb 8?b111_11011 10?b110110_1000 10?b001001_0111 k29.7 fd 8?b111_11101 10?b101110_1000 10?b010001_0111 k30.7 fe 8?b111_11110 10?b011110_1000 10?b100001_0111 note to ta b l e 6 ? 2 : (1) k28.5 is a comma code used for word alignment and indicat es an idle state. table 6?2. supported k codes (part 2 of 2) k code octal value 8-bit code hgf_edcba 10-bit code rd- abcdei_fghj 10-bit code rd+ abcdei_fghj table 6?3. valid data code-groups (part 1 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj d0.0 00 000 00000 100111 0100 011000 1011 d1.0 01 000 00001 011101 0100 100010 1011 d2.0 02 000 00010 101101 0100 010010 1011 d3.0 03 000 00011 110001 1011 110001 0100 d4.0 04 000 00100 110101 0100 001010 1011 d5.0 05 000 00101 101001 1011 101001 0100 d6.0 06 000 00110 011001 1011 011001 0100 d7.0 07 000 00111 111000 1011 000111 0100 d8.0 08 000 01000 111001 0100 000110 1011 d9.0 09 000 01001 100101 1011 100101 0100 d10.0 0a 000 01010 010101 1011 010101 0100 d11.0 0b 000 01011 110100 1011 110100 0100 d12.0 0c 000 01100 001101 1011 001101 0100 d13.0 0d 000 01101 101100 1011 101100 0100 d14.0 0e 000 01110 011100 1011 011100 0100 d15.0 0f 000 01111 010111 0100 101000 1011
6?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 8b/10b code d16.0 10 000 10000 011011 0100 100100 1011 d17.0 11 000 10001 100011 1011 100011 0100 d18.0 12 000 10010 010011 1011 010011 0100 d19.0 13 000 10011 110010 1011 110010 0100 d20.0 14 000 10100 001011 1011 001011 0100 d21.0 15 000 10101 101010 1011 101010 0100 d22.0 16 000 10110 011010 1011 011010 0100 d23.0 17 000 10111 111010 0100 000101 1011 d24.0 18 000 11000 110011 0100 001100 1011 d25.0 19 000 11001 100110 1011 100110 0100 d26.0 1a 000 11010 010110 1011 010110 0100 d27.0 1b 000 11011 110110 0100 001001 1011 d28.0 1c 000 11100 001110 1011 001110 0100 d29.0 1d 000 11101 101110 0100 010001 1011 d30.0 1e 000 11110 011110 0100 100001 1011 d31.0 1f 000 11111 101011 0100 010100 1011 d0.1 20 001 00000 100111 1001 011000 1001 d1.1 21 001 00001 011101 1001 100010 1001 d2.1 22 001 00010 101101 1001 010010 1001 d3.1 23 001 00011 110001 1001 110001 1001 d4.1 24 001 00100 110101 1001 001010 1001 d5.1 25 001 00101 101001 1001 101001 1001 d6.1 26 001 00110 011001 1001 011001 1001 d7.1 27 001 00111 111000 1001 000111 1001 d8.1 28 001 01000 111001 1001 000110 1001 d9.1 29 001 01001 100101 1001 100101 1001 d10.1 2a 001 01010 010101 1001 010101 1001 d11.1 2b 001 01011 110100 1001 110100 1001 d12.1 2c 001 01100 001101 1001 001101 1001 d13.1 2d 001 01101 101100 1001 101100 1001 d14.1 2e 001 01110 011100 1001 011100 1001 d15.1 2f 001 01111 010111 1001 101000 1001 d16.1 30 001 10000 011011 1001 100100 1001 table 6?3. valid data code-groups (part 2 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj
altera corporation 6?7 october 2007 stratix ii gx device handbook, volume 2 specifications & additional information d17.1 31 001 10001 100011 1001 100011 1001 d18.1 32 001 10010 010011 1001 010011 1001 d19.1 33 001 10011 110010 1001 110010 1001 d20.1 34 001 10100 001011 1001 001011 1001 d21.1 35 001 10101 101010 1001 101010 1001 d22.1 36 001 10110 011010 1001 011010 1001 d23.1 37 001 10111 111010 1001 000101 1001 d24.1 38 001 11000 110011 1001 001100 1001 d25.1 39 001 11001 100110 1001 100110 1001 d26.1 3a 001 11010 010110 1001 010110 1001 d27.1 3b 001 11011 110110 1001 001001 1001 d28.1 3c 001 11100 001110 1001 001110 1001 d29.1 3d 001 11101 101110 1001 010001 1001 d30.1 3e 001 11110 011110 1001 100001 1001 d31.1 3f 001 11111 101011 1001 010100 1001 d0.2 40 010 00000 100111 0101 011000 0101 d1.2 41 010 00001 011101 0101 100010 0101 d2.2 42 010 00010 101101 0101 010010 0101 d3.2 43 010 00011 110001 0101 110001 0101 d4.2 44 010 00100 110101 0101 001010 0101 d5.2 45 010 00101 101001 0101 101001 0101 d6.2 46 010 00110 011001 0101 011001 0101 d7.2 47 010 00111 111000 0101 000111 0101 d8.2 48 010 01000 111001 0101 000110 0101 d9.2 49 010 01001 100101 0101 100101 0101 d10.2 4a 010 01010 010101 0101 010101 0101 d11.2 4b 010 01011 110100 0101 110100 0101 d12.2 4c 010 01100 001101 0101 001101 0101 d13.2 4d 010 01101 101100 0101 101100 0101 d14.2 4e 010 01110 011100 0101 011100 0101 d15.2 4f 010 01111 010111 0101 101000 0101 d16.2 50 010 10000 011011 0101 100100 0101 d17.2 51 010 10001 100011 0101 100011 0101 table 6?3. valid data code-groups (part 3 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj
6?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 8b/10b code d18.2 52 010 10010 010011 0101 010011 0101 d19.2 53 010 10011 110010 0101 110010 0101 d20.2 54 010 10100 001011 0101 001011 0101 d21.2 55 010 10101 101010 0101 101010 0101 d22.2 56 010 10110 011010 0101 011010 0101 d23.2 57 010 10111 111010 0101 000101 0101 d24.2 58 010 11000 110011 0101 001100 0101 d25.2 59 010 11001 100110 0101 100110 0101 d26.2 5a 010 11010 010110 0101 010110 0101 d27.2 5b 010 11011 110110 0101 001001 0101 d28.2 5c 010 11100 001110 0101 001110 0101 d29.2 5d 010 11101 101110 0101 010001 0101 d30.2 5e 010 11110 011110 0101 100001 0101 d31.2 5f 010 11111 101011 0101 010100 0101 d0.3 60 011 00000 100111 0011 011000 1100 d1.3 61 011 00001 011101 0011 100010 1100 d2.3 62 011 00010 101101 0011 010010 1100 d3.3 63 011 00011 110001 1100 110001 0011 d4.3 64 011 00100 110101 0011 001010 1100 d5.3 65 011 00101 101001 1100 101001 0011 d6.3 66 011 00110 011001 1100 011001 0011 d7.3 67 011 00111 111000 1100 000111 0011 d8.3 68 011 01000 111001 0011 000110 1100 d9.3 69 011 01001 100101 1100 100101 0011 d10.3 6a 011 01010 010101 1100 010101 0011 d11.3 6b 011 01011 110100 1100 110100 0011 d12.3 6c 011 01100 001101 1100 001101 0011 d13.3 6d 011 01101 101100 1100 101100 0011 d14.3 6e 011 01110 011100 1100 011100 0011 d15.3 6f 011 01111 010111 0011 101000 1100 d16.3 70 011 10000 011011 0011 100100 1100 d17.3 71 011 10001 100011 1100 100011 0011 d18.3 72 011 10010 010011 1100 010011 0011 table 6?3. valid data code-groups (part 4 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj
altera corporation 6?9 october 2007 stratix ii gx device handbook, volume 2 specifications & additional information d19.3 73 011 10011 110010 1100 110010 0011 d20.3 74 011 10100 001011 1100 001011 0011 d21.3 75 011 10101 101010 1100 101010 0011 d22.3 76 011 10110 011010 1100 011010 0011 d23.3 77 011 10111 111010 0011 000101 1100 d24.3 78 011 11000 110011 0011 001100 1100 d25.3 79 011 11001 100110 1100 100110 0011 d26.3 7a 011 11010 010110 1100 010110 0011 d27.3 7b 011 11011 110110 0011 001001 1100 d28.3 7c 011 11100 001110 1100 001110 0011 d29.3 7d 011 11101 101110 0011 010001 1100 d30.3 7e 011 11110 011110 0011 100001 1100 d31.3 7f 011 11111 101011 0011 010100 1100 d0.4 80 100 00000 100111 0010 011000 1101 d1.4 81 100 00001 011101 0010 100010 1101 d2.4 82 100 00010 101101 0010 010010 1101 d3.4 83 100 00011 110001 1101 110001 0010 d4.4 84 100 00100 110101 0010 001010 1101 d5.4 85 100 00101 101001 1101 101001 0010 d6.4 86 100 00110 011001 1101 011001 0010 d7.4 87 100 00111 111000 1101 000111 0010 d8.4 88 100 01000 111001 0010 000110 1101 d9.4 89 100 01001 100101 1101 100101 0010 d10.4 8a 100 01010 010101 1101 010101 0010 d11.4 8b 100 01011 110100 1101 110100 0010 d12.4 8c 100 01100 001101 1101 001101 0010 d13.4 8d 100 01101 101100 1101 101100 0010 d14.4 8e 100 01110 011100 1101 011100 0010 d15.4 8f 100 01111 010111 0010 101000 1101 d16.4 90 100 10000 011011 0010 100100 1101 d17.4 91 100 10001 100011 1101 100011 0010 d18.4 92 100 10010 010011 1101 010011 0010 d19.4 93 100 10011 110010 1101 110010 0010 table 6?3. valid data code-groups (part 5 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj
6?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 8b/10b code d20.4 94 100 10100 001011 1101 001011 0010 d21.4 95 100 10101 101010 1101 101010 0010 d22.4 96 100 10110 011010 1101 011010 0010 d23.4 97 100 10111 111010 0010 000101 1101 d24.4 98 100 11000 110011 0010 001100 1101 d25.4 99 100 11001 100110 1101 100110 0010 d26.4 9a 100 11010 010110 1101 010110 0010 d27.4 9b 100 11011 110110 0010 001001 1101 d28.4 9c 100 11100 001110 1101 001110 0010 d29.4 9d 100 11101 101110 0010 010001 1101 d30.4 9e 100 11110 011110 0010 100001 1101 d31.4 9f 100 11111 101011 0010 010100 1101 d0.5 a0 101 00000 100111 1010 011000 1010 d1.5 a1 101 00001 011101 1010 100010 1010 d2.5 a2 101 00010 101101 1010 010010 1010 d3.5 a3 101 00011 110001 1010 110001 1010 d4.5 a4 101 00100 110101 1010 001010 1010 d5.5 a5 101 00101 101001 1010 101001 1010 d6.5 a6 101 00110 011001 1010 011001 1010 d7.5 a7 101 00111 111000 1010 000111 1010 d8.5 a8 101 01000 111001 1010 000110 1010 d9.5 a9 101 01001 100101 1010 100101 1010 d10.5 aa 101 01010 010101 1010 010101 1010 d11.5 ab 101 01011 110100 1010 110100 1010 d12.5 ac 101 01100 001101 1010 001101 1010 d13.5 ad 101 01101 101100 1010 101100 1010 d14.5 ae 101 01110 011100 1010 011100 1010 d15.5 af 101 01111 010111 1010 101000 1010 d16.5 b0 101 10000 011011 1010 100100 1010 d17.5 b1 101 10001 100011 1010 100011 1010 d18.5 b2 101 10010 010011 1010 010011 1010 d19.5 b3 101 10011 110010 1010 110010 1010 d20.5 b4 101 10100 001011 1010 001011 1010 table 6?3. valid data code-groups (part 6 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj
altera corporation 6?11 october 2007 stratix ii gx device handbook, volume 2 specifications & additional information d21.5 b5 101 10101 101010 1010 101010 1010 d22.5 b6 101 10110 011010 1010 011010 1010 d23.5 b7 101 10111 111010 1010 000101 1010 d24.5 b8 101 11000 110011 1010 001100 1010 d25.5 b9 101 11001 100110 1010 100110 1010 d26.5 ba 101 11010 010110 1010 010110 1010 d27.5 bb 101 11011 110110 1010 001001 1010 d28.5 bc 101 11100 001110 1010 001110 1010 d29.5 bd 101 11101 101110 1010 010001 1010 d30.5 be 101 11110 011110 1010 100001 1010 d31.5 bf 101 11111 101011 1010 010100 1010 d0.6 c0 110 00000 100111 0110 011000 0110 d1.6 c1 110 00001 011101 0110 100010 0110 d2.6 c2 110 00010 101101 0110 010010 0110 d3.6 c3 110 00011 110001 0110 110001 0110 d4.6 c4 110 00100 110101 0110 001010 0110 d5.6 c5 110 00101 101001 0110 101001 0110 d6.6 c6 110 00110 011001 0110 011001 0110 d7.6 c7 110 00111 111000 0110 000111 0110 d8.6 c8 110 01000 111001 0110 000110 0110 d9.6 c9 110 01001 100101 0110 100101 0110 d10.6 ca 110 01010 010101 0110 010101 0110 d11.6 cb 110 01011 110100 0110 110100 0110 d12.6 cc 110 01100 001101 0110 001101 0110 d13.6 cd 110 01101 101100 0110 101100 0110 d14.6 ce 110 01110 011100 0110 011100 0110 d15.6 cf 110 01111 010111 0110 101000 0110 d16.6 d0 110 10000 011011 0110 100100 0110 d17.6 d1 110 10001 100011 0110 100011 0110 d18.6 d2 110 10010 010011 0110 010011 0110 d19.6 d3 110 10011 110010 0110 110010 0110 d20.6 d4 110 10100 001011 0110 001011 0110 d21.6 d5 110 10101 101010 0110 101010 0110 table 6?3. valid data code-groups (part 7 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj
6?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 8b/10b code d22.6 d6 110 10110 011010 0110 011010 0110 d23.6 d7 110 10111 111010 0110 000101 0110 d24.6 d8 110 11000 110011 0110 001100 0110 d25.6 d9 110 11001 100110 0110 100110 0110 d26.6 da 110 11010 010110 0110 010110 0110 d27.6 db 110 11011 110110 0110 001001 0110 d28.6 dc 110 11100 001110 0110 001110 0110 d29.6 dd 110 11101 101110 0110 010001 0110 d30.6 de 110 11110 011110 0110 100001 0110 d31.6 df 110 11111 101011 0110 010100 0110 d0.7 e0 111 00000 100111 0001 011000 1110 d1.7 e1 111 00001 011101 0001 100010 1110 d2.7 e2 111 00010 101101 0001 010010 1110 d3.7 e3 111 00011 110001 1110 110001 0001 d4.7 e4 111 00100 110101 0001 001010 1110 d5.7 e5 111 00101 101001 1110 101001 0001 d6.7 e6 111 00110 011001 1110 011001 0001 d7.7 e7 111 00111 111000 1110 000111 0001 d8.7 e8 111 01000 111001 0001 000110 1110 d9.7 e9 111 01001 100101 1110 100101 0001 d10.7 ea 111 01010 010101 1110 010101 0001 d11.7 eb 111 01011 110100 1110 110100 1000 d12.7 ec 111 01100 001101 1110 001101 0001 d13.7 ed 111 01101 101100 1110 101100 1000 d14.7 ee 111 01110 011100 1110 011100 1000 d15.7 ef 111 01111 010111 0001 101000 1110 d16.7 f0 111 10000 011011 0001 100100 1110 d17.7 f1 111 10001 100011 0111 100011 0001 d18.7 f2 111 10010 010011 0111 010011 0001 d19.7 f3 111 10011 110010 1110 110010 0001 d20.7 f4 111 10100 001011 0111 001011 0001 d21.7 f5 111 10101 101010 1110 101010 0001 d22.7 f6 111 10110 011010 1110 011010 0001 table 6?3. valid data code-groups (part 8 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj
altera corporation 6?13 october 2007 stratix ii gx device handbook, volume 2 specifications & additional information document revision history table 6?4 shows the revision history for this chapter. d23.7 f7 111 10111 111010 0001 000101 1110 d24.7 f8 111 11000 110011 0001 001100 1110 d25.7 f9 111 11001 100110 1110 100110 0001 d26.7 fa 111 11010 010110 1110 010110 0001 d27.7 fb 111 11011 110110 0001 001001 1110 d28.7 fc 111 11100 001110 1110 001110 0001 d29.7 fd 111 11101 101110 0001 010001 1110 d30.7 fe 111 11110 011110 0001 100001 1110 d31.7 ff 111 11111 101011 0001 010100 1110 table 6?3. valid data code-groups (part 9 of 9) code-group name octet value octet bits hgf edcba current rd- current rd+ abcdei fghj abcdei fghj table 6?4. document revision history date and document version changes made summary of changes october 2007 v3.1 updated table 6?1 .? no change formerly chapter 5. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? february 2007 v3.0 removed the stratix ii gx feature versus protocol mode matrix table. ? added the ?document revision history? section to this chapter. ? updated table 6?1. ? february 2006, v2.1 changed to chapter 5. updated tables 5?1 and 5?2. ? december 2005, v2.0 removed ?appendix? from chapter title. updated tables 5?1 and 5?2. ? october 2005 v1.0 added chapter to the stratix ii gx device handbook . ?
6?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history
altera corporation section ii?1 preliminary section ii. clock management this section provides information on clock management in stratix ? ii gx devices. it describes the enhanced and fast phase-locked loops (plls) that support clock management and synthe sis for on-chip clock management, external system clock management , and high-speed i/o interfaces. this section includes the following chapter: chapter 7, plls in stratix ii and stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section ii?2 altera corporation preliminary clock management stratix ii gx device handbook, volume 2
altera corporation 7?1 october 2007 7. plls in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx device phase-locked loops (plls) provide robust clock management and synthe sis for device clock management, external system clock management , and high-speed i/o interfaces. stratix ii devices have up to 12 plls, and stratix ii gx devices have up to 8 plls. stratix ii and stratix ii gx plls are highly versatile and can be used as a zero delay buffer, a jitter attenuator, low skew fan out buffer, or a frequency synthesizer. stratix ii and stratix ii gx devices feature both enhanced plls and fast plls. stratix ii and stratix ii gx de vices have up to four enhanced plls. stratix ii devices have up to eight fast plls and stratix ii gx devices have up to four plls. both enhanced and fast plls are feature rich, supporting advanced capabilities such as clock switchover, reconfigurable phase shift, pll reconfiguration, and reconfigurable bandwidth. plls can be used for general-purpos e clock management, suppo rting multiplication, phase shifting, and programmable du ty cycle. in addition, enhanced plls support external clock feedback mode, spread-spectrum clocking, and counter cascading. fast plls of fer high speed outputs to manage the high-speed differential i/o interfaces. stratix ii and stratix ii gx devices also support a power-down mode where clock networks that are not bein g used can easily be turned off, reducing the overall power consumpt ion of the device. in addition, stratix ii and stratix ii gx plls support dynamic selection of the pll input clock from up to five possible so urces, giving you the flexibility to choose from multiple (up to four) cl ock sources to feed the primary and secondary clock input ports. the altera ? quartus ? ii software enables the plls and their features without requiring any external devices. sii52001-4.5
7?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 introduction tables 7?1 and 7?2 show the plls available for each stratix ii and stratix ii gx device, respectively. table 7?1. stratix ii devi ce pll availability note (1) device fast plls enhanced plls 1 2 3 4 7 8 9 10 5 6 11 12 ep2s15 vvvv vv ep2s30 vvvv vv ep2s60 vvvvv vv v vvvv ep2s90 (2) vvvvv vv v vvvv ep2s130 (3) vvvvvvvvvvvv ep2s180 vvvvvvvvvvvv notes for ta b l e 7 ? 1 : (1) the ep2s60 device in the 1,020-pin package contains 12 plls. ep2s60 devices in the 484-pin and 672-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (2) ep2s90 devices in the 1020-pin and 1508-pin packages co ntain 12 plls. ep2s90 devices in the 484-pin and 780-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (3) ep2s130 devices in the 1020-pin and 1508-pin packages contain 12 plls. the ep2s130 device in the 780-pin package contains fast plls 1?4 and enhanced plls 5 and 6. table 7?2. stratix ii gx de vice pll availability note (1) device fast plls enhanced plls 123 (3) 4 (3) 789 (3) 10 (3) 5 6 11 12 ep2sgx30 (2) vv vv ep2sgx60 (2) vv v v vvvv ep2sgx90 vv v v vvvv ep2sgx130 vv vv vvvv notes for ta b l e 7 ? 2 : (1) the global or regional clocks in a fast pll?s transceive r block can drive the fast pll input. a pin or other pll must drive the global or regional source. th e source cannot be driven by internal ly generated logic before driving the fast pll. (2) ep2sgx30c and ep2sgx60c devices only have two fast p lls (plls 1 and 2), but the connectivity from these two plls to the global and regional clock networ ks remains the same as shown in this table. (3) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. however, these plls are listed in table 7?2 because the stratix ii gx pll numbering scheme is cons istent with stratix and stratix ii devices.
altera corporation 7?3 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 7?3 shows the enhanced pll and fast pll features in stratix ii and stratix ii gx devices. figure 7?1 shows a top-level diagram of stratix ii device and pll locations. figure 7?2 shows a top-level diagram of stratix ii device and pll locations. see ?clock control block? on page 7?86 for more detail on pll connections to global and regional clocks networks. table 7?3. stratix ii and stra tix ii gx pll features feature enhanced pll fast pll clock multiplication and division m/(n post-scale counter) (1) m/(n post-scale counter) (2) phase shift down to 125-ps increments (3) down to 125-ps increments (3) clock switchover vv (4) pll reconfiguration vv reconfigurable bandwidth vv spread-spectrum clocking v programmable duty cycle vv number of clock outputs per pll (5) 64 number of dedicated external clock outputs per pll three differential or six single-ended (6) number of feedback clock inputs per pll 1 (7) notes to ta b l e 7 ? 3 : (1) for enhanced plls, m and n range from 1 to 512 with 50% duty cycle. post-scale counters range from 1 to 512 with 50% duty cycle. for non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256. (2) for fast plls, n can range from 1 to 4. the post-scale and m counters range from 1 to 32. for non-50% duty-cycle clock outputs, post-scale counters range from 1 to 16. (3) the smallest phase shift is determined by the voltage controlled osc illator (vco) period divided by eight. the supported phase-shift range is from 125 to 250 ps. st ratix ii and stratix ii gx devices can shift all output frequencies in increments of at least 45 . smaller degree increments are possible depending on the frequency and divide parameters. for non-50% duty cycle clock ou tputs post-scale counters range from 1 to 256. (4) stratix ii and stratix ii gx fast plls only support manual clock switchover. (5) the clock outputs can be driven to internal clock networks or to a pin. (6) the pll clock outputs of the fast plls can drive to any i/o pin to be used as an external clock output. for high-speed differential i/o pins, the device uses a da ta channel to generate the transmitter output clock ( txclkout ) . (7) if the design uses external feedback input pins, you will lose one (or two, if f bin is differential) dedicated output clock pin.
7?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 introduction figure 7?1. stratix ii pll locations fpll7clk fpll10clk fpll9clk clk8-11 fpll8clk clk0-3 7 1 2 8 10 4 3 9 5 12 6 clk4-7 clk12-15 11 rclk0-3 rclk4-7 gclk0-3 gclk8-11 rclk20-23 rclk28-31 rclk24-27 gclk12-15 gclk4-7 rclk8-11 rclk12-15 q1 q4 q2 q3 rclk16-19 fast plls fast plls fast plls fast plls enhanced pll enhanced pll enhanced pll enhanced pll
altera corporation 7?5 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?2. stratix ii gx pll locations enhanced plls stratix ii and stratix ii gx devices contain up to four enhanced plls with advanced clock manageme nt features. the main goal of a pll is to synchronize the phase and frequency of an internal and external clock to an input reference clock. there ar e a number of components that comprise a pll to achiev e this phase alignment. enhanced pll hardware overview stratix ii and stratix ii gx plls alig n the rising edge of the reference input clock to a feedback clock using the phase-frequency detector (pfd). the falling edges are determined by the duty-cycle specifications. the pfd produces an up or down signal that determines whether the vco needs to operate at a higher or lower frequency. fpll7clk fpll8clk clk[3..0] 7 1 2 8 5 11 6 12 clk [ 7..4 ] clk[15..12] plls
7?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 enhanced plls the pfd output is applied to the charge pump and loop filter, which produces a control voltage for setti ng the vco frequency. if the pfd produces an up signal, then the vco frequency increases. a down signal decreases the vco frequency. the pfd outputs these up and down signals to a charge pump. if the charge pump receives an up signal, current is driven into the loop filter. conversely, if it receives a down signal, current is drawn from the loop filter. the loop filter converts these up an d down signals to a voltage that is used to bias the vco. the loop filt er also removes glitches from the charge pump and prevents voltage ov er-shoot, which filters the jitter on the vco. the voltage from the loop filter de termines how fast the vco operates. the vco is implemented as a four-stage differential ring oscillator. a divide counter ( m ) is inserted in the feedback loop to increase the vco frequency above the input reference frequency. vco frequency (f vco ) is equal to ( m ) times the input reference clock (f ref ). the input reference clock (f ref ) to the pfd is equal to the input clock (f in ) divided by the pre- scale counter ( n ). therefore, the feedback clock (f fb ) applied to one input of the pfd is locked to the f ref that is applied to the other input of the pfd. the vco output can feed up to six post-scale counters ( c0 , c1 , c2 , c3 , c4 , and c5 ). these post-scale counters al low a number of harmonically related frequencies to be produced within the pll. figure 7?3 shows a simplified block diagram of the major components of the stratix ii and stratix ii gx enhanced pll. figure 7?4 shows the enhanced pll?s outputs and dedicated clock outputs.
altera corporation 7?7 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?3. stratix ii and st ratix ii gx enhanced pll notes to figure 7?3 : (1) each clock source can come from any of the four clock pins located on the same side of the device as the pll. (2) plls 5, 6, 11, and 12 each have six single-ended de dicated clock outputs or three differential dedicated clock outputs. (3) if the design uses external feedback in put pins, you will lose one (or two, if f bin is differential) dedicated output clock pin. every stratix ii and stratix ii gx device has at least two enhanced plls with one single-ended or differential external feedback input per pll. (4) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. charge pump vco c2 c3 c4 c0 8 4 6 4 global clocks c1 lock detect to i/o or general routing inclk[3..0] fbin global or regional clock pfd c5 from adjacent pll m n spread spectrum i/o buffers (2) (3) loop filter & filter post-scale counters clock switchover circuitry phase frequency detector vco phase selection selectable at each pll output port vco phase selection affecting all outputs shaded portions of the pll are reconfigurable regional clocks 8 6 (1) (4)
7?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 enhanced plls external clock outputs enhanced plls 5, 6, 11, and 12 each support up to six single-ended clock outputs (or three differential pairs). see figure 7?4 . figure 7?4. external clock outputs for enhanced plls 5, 6, 11 and 12 notes to figure 7?4 : (1) these clock output pins can be fed by any one of the c[5..0] counters. (2) these clock output pins are used as either external clock outputs or for external feedback. if the design uses external feedback input pins, you will lose one (or two, if f bin is differential) dedicated output clock pin. (3) these external clock enable signals are available only when using the altclkctrl megafunction. any of the six output counters c[5..0] can feed the dedicated external clock outputs, as shown in figure 7?5 . therefore, one counter or frequency can drive all output pins available from a given pll. the dedicated output clock pins ( pll_out ) from each enhanced pll are powered by a separate power pin (e.g., vcc_pll5_out , vcc_pll6_out , etc.), reducing the overal l output jitter by providing improved isolation from switching i/o pins. enhanced pll c0 c1 c2 c4 c5 c3 extclken0 extclken1 pll#_out0p (1) pll#_out0n (1) extclken2 extclken3 pll#_out1p (1) pll#_out1n (1) extclken4 extclken5 pll#_out2p (1), (2) pll#_out2n (1), (2) (3) (3) (3) (3) (3) (3)
altera corporation 7?9 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?5. external clock output co nnectivity to pll output counter s for enhanced plls 5, 6, 11 and 12 note (1) note to figure 7?5 : (1) the design can use each external clock output pin as a general-purpose output pin from the logic array. these pins are multiplexed with i/o element (ioe) outputs. each pin of a single-ended output pair can either be in phase or 180 out of phase. the quartus ii software places the not gate in the design into the ioe to implement 180 phase with resp ect to the other pin in the pair. the clock output pi n pairs support the same i/o standards as standard output pins (in the top and bottom banks) as well as lvds, lvpecl, differential hstl, and differential sstl. see table 7?6 , in the ?enhanced pll pins? section on page 7?12 to determine which i/o standards the enhanced pll cloc k pins support. when in single-ended or differential mode, one power pin supports six single-ended or three differential ou tputs. both outputs use the same i/o standard in single-ended mode to maintain performance. you can also use the external clock ou tput pins as user outp ut pins if external enhanced pll clocking is not needed. the enhanced pll can also drive out to any regular i/o pin through the global or regional clock network. enhanced pll software overview stratix ii and stratix ii gx enhanced plls are enabled in the quartus ii software by using the altpll megafunction. figure 7?6 shows the available ports (as they are named in the quartus ii altpll megafunction) of the stratix ii an d stratix ii gx enhanced pll. c0 c1 c3 c4 c5 c6 from internal logic or ioe 6 6 6 to i/o pins (1 ) multiplexer selection set in configuration file
7?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 enhanced plls figure 7?6. enhanced pll ports notes to figure 7?6 : (1) enhanced and fast plls share this input pin. (2) these are either single-e nded or differential pins. (3) the primary and secondary clock input can be fed from an y one of four clock pins locate d on the same side of the device as the pll. (4) can drive to the global or regional clock netw orks or the dedicated external clock output pins. (5) these dedicated output clocks are fed by the c[5..0] counters. tables 7?4 and 7?5 describe all the e nhanced pll ports. clkswitch scandata scanclk pllena c[5..0] locked physical pin clkloss areset pfdena signal driven by internal logic signal driven to internal logic internal clock signal scandone pll_out0p scandataout fbin clkbad[1..0] (1) (2), (3) pll_out0n pll_out1p pll_out1n pll_out2p pll_out2n (5) scanwrite scanread (5) (5) (5) (5) (5) activeclock inclk0 inclk1 (4) (2), (3) table 7?4. enhanced pll input signals (part 1 of 2) port description source destination inclk0 primary clock input to the pll. pin or another pll n counter inclk1 secondary clock input to the pll. pin or another pll n counter fbin external feedback input to the pll. pin pfd pllena enable pin for enabling or disabling all or a set of plls. active high. pin general pll control signal clkswitch switch-over signal used to initiate external clock switch-over control. active high. logic array pll switch-over circuit
altera corporation 7?11 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices areset signal used to reset the pll which resynchronizes all the counter outputs. active high. logic array general pll control signal pfdena enables the outputs from the phase frequency detector. active high. logic array pfd scanclk serial clock signal for the real-time pll reconfiguration feature. logic array reconfiguration circuit scandata serial input data stream for the real- time pll reconfiguration feature. logic array reconfiguration circuit scanwrite enables writing the data in the scan chain into the pll. active high. logic array reconfiguration circuit scanread enables scan data to be written into the scan chain. active high. logic array reconfiguration circuit table 7?5. enhanced pll output signals (part 1 of 2) port description source destination c[5..0] pll output counters driving regional, global or external clocks. pll counter internal or external clock pll_out [2..0]p pll_out [2..0]n these are three differential or six single-ended external clock output pins fed from the c[5..0] pll counters, and every output can be driven by any counter. p and n are the positive ( p ) and negative ( n ) pins for differential pins. pll counter pin(s) clkloss signal indicating the switch-over circuit detected a switch-over condition. pll switch-over circuit logic array clkbad[1..0] signals indicating which reference clock is no longer toggling. clkbad1 indicates inclk1 status, clkbad0 indicates inclk0 status. 1= good; 0=bad pll switch-over circuit logic array locked lock or gated lock output from lock detect circuit. active high. pll lock detect logic array activeclock signal to indicate which clock ( 0 = inclk0 or 1 = inclk1 ) is driving the pll. if this signal is low, inclk0 drives the pll, if this signal is high, inclk1 drives the pll pll clock multiplexer logic array table 7?4. enhanced pll input signals (part 2 of 2) port description source destination
7?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 enhanced plls enhanced pll pins table 7?6 lists the i/o standards support by the enhanced pll clock outputs. scandataout output of the last shift register in the scan chain. pll scan chain logic array scandone signal indicating when the pll has completed reconfiguration. 1 to 0 transition indicates that the pll has been reconfigured. pll scan chain logic array table 7?5. enhanced pll output signals (part 2 of 2) port description source destination table 7?6. i/o standards supported for enhanced pll pins (part 1 of 2) note (1) i/o standard input output inclk fbin extclk lv t t l v v v lv c m o s v v v 2.5 v v v v 1.8 v v v v 1.5 v v v v 3.3-v pci v v v 3.3-v pci-x v v v sstl-2 class i v v v sstl-2 class ii v v v sstl-18 class i v v v sstl-18 class ii v v v 1.8-v hstl class i v v v 1.8-v hstl class ii v v v 1.5-v hstl class i v v v 1.5-v hstl class ii v v v 1.2-v hstl class i v v v 1.2-v hstl class ii v v v
altera corporation 7?13 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 7?7 shows the physical pins and th eir purpose for the stratix ii and stratix ii gx enhanced plls. for inclk port connections to pins see ?clock control block? on page 7?86 . differential sstl-2 class i v v v differential sstl-2 class ii v v v differential sstl-18 class i v v v differential sstl-18 class ii v v v 1.8-v differential hstl class i v v v 1.8-v differential hstl class ii v v v 1.5-v differential hstl class i v v v 1.5-v differential hstl class ii v v v lv d s v v v hypertransport technology differential lvpecl vv v note to ta b l e 7 ? 6 : (1) the enhanced pll external clock output bank does not allow a mixture of both single-ended and differential i/o standards. table 7?6. i/o standards supported for enhanced pll pins (part 2 of 2) note (1) i/o standard input output inclk fbin extclk table 7?7. stratix ii and st ratix ii gx enhanced pll pins (part 1 of 3) note (1) pin description clk4p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk5p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk6p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk7p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk12p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. clk13p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. clk14p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. clk15p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. pll5_fbp/n single-ended or differential pins that can drive the fbin port for pll 5.
7?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 enhanced plls pll6_fbp/n single-ended or differential pins that can drive the fbin port for pll 6. pll11_fbp/n single-ended or differential pins that can drive the fbin port for pll 11. pll12_fbp/n single-ended or differential pins that can drive the fbin port for pll 12. pll_ena dedicated input pin that drives the pllena port of all or a set of plls. if you do not use this pin, connect it to ground. pll5_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 5. pll6_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 6. pll11_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 11. pll12_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 12. vcca_pll5 analog power for pll 5. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll5 analog ground for pll 5. you can connect this pin to the gnd plane on the board. vcca_pll6 analog power for pll 6. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll6 analog ground for pll 6. you can connect this pin to the gnd plane on the board. vcca_pll11 analog power for pll 11. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll11 analog ground for pll 11. you can connect this pin to the gnd plane on the board. vcca_pll12 analog power for pll 12. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll12 analog ground for pll 12. you can connect this pin to the gnd plane on the board. vccd_pll digital power for plls. you must connect this pin to 1.2 v, even if the pll is not used. vcc_pll5_out external clock output v ccio power for pll5_out0p , pll5_out0n , pll5_out1p , pll5_out1n , pll5_out2p , and pll5_out2n outputs from pll 5. vcc_pll6_out external clock output v ccio power for pll6_out0p , pll6_out0n , pll6_out1p , pll6_out1n and pll6_out2p , pll6_out2n outputs from pll 6. vcc_pll11_out external clock output v ccio power for pll11_out0p , pll11_out0n , pll11_out1p , pll11_out1n and pll11_out2p , pll11_out2n outputs from pll 11. table 7?7. stratix ii and st ratix ii gx enhanced pll pins (part 2 of 3) note (1) pin description
altera corporation 7?15 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices fast plls stratix ii devices contain up to eight fast plls and stratix ii gx devices contain up to four fast plls. fast pl ls have high-speed differential i/o interface capability along wi th general-purpose features. fast pll hardware overview figure 7?7 shows a diagram of the fast pll. figure 7?7. stratix ii and stratix ii gx fast pll block diagram notes to figure 7?7 : (1) stratix ii and stratix ii gx fast plls only support manual clock switchover. (2) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. (3) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes. stratix ii devices only support one rate of data transfer per fast p ll in high-speed differential i/o support mode. (4) this signal is a high-speed differential i/o support serdes control signal. (5) if the design enables this 2 counter, then the device can use a vco frequency range of 150 to 520 mhz. vcc_pll12_out external clock output v ccio power for pll12_out0p , pll12_out0n , pll12_out1p , pll12_out1n and pll12_out2p , pll12_out2n outputs from pll 12. note to ta b l e 7 ? 7 : (1) the negative leg pins ( clkn , pll_fbn , and pll_outn ) are only required with differential signaling. table 7?7. stratix ii and st ratix ii gx enhanced pll pins (part 3 of 3) note (1) pin description charge pump vco c1 8 8 4 4 8 clock input pfd c0 m loop filter phase frequency detector vco phase selection selectable at each pll output port post-scale counters global clocks diffioclk0 (3) loaden0 (4) diffioclk1 (3) loaden1 (4) regional clocks to dpa block global or regional clock (2) global or regional clock (2) c2 c3 n 4 clock (1) switchover circuitry shaded portions of the pll are reconfigurable k (5)
7?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast plls external clock outputs each fast pll supports differential or single-ended outputs for source-synchronous transmitters or for general-purpose external clocks. there are no dedicated external clock output pins. the fast pll global or regional outputs can drive any i/o pin as an external clock output pin. the i/o standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast pll in that bank. f for more information, see the selectable i/o standards in stratix ii and stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook ). fast pll software overview stratix ii and stratix ii gx fast plls are enabled in the quartus ii software by using the altpll megafunction. figure 7?8 shows the available ports (as they are named in the quartus ii altpll megafunction) of the stratix ii or stratix ii gx fast pll. figure 7?8. stratix ii and stratix ii gx fast pll port s and physical destinations notes to figure 7?8 : (1) this input pin is either si ngle-ended or differential. (2) this input pin is shared by all enhanced and fast plls. tables 7?8 and 7?9 show the description of all fast pll ports. inclk0 inclk1 scanwrite pfdena pllena c[3..0] locked physical pin scandataout signal driven by internal logic signal driven to internal logic internal clock signal scandone (1) areset scanclk scandata scanread (1) (2) table 7?8. fast pll input signals (part 1 of 2) name description source destination inclk0 primary clock input to the fast pll. pin or another pll n counter inclk1 secondary clock input to the fast pll. pin or another pll n counter
altera corporation 7?17 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices pllena enable pin for enabling or disabling all or a set of plls. active high. pin pll control signal clkswitch switch-over signal used to initiate external clock switch-over control. active high. logic array reconfiguration circuit areset enables the up/down outputs from the phase-frequency detector. active high. logic array pll control signal pfdena enables the up/down outputs from the phase-frequency detector. active high. logic array pfd scanclk serial clock signal for the real-time pll control feature. logic array reconfiguration circuit scandata serial input data stream for the real-time pll control feature. logic array reconfiguration circuit scanwrite enables writing the data in the scan chain into the pll active high. logic array reconfiguration circuit scanread enables scan data to be written into the scan chain active high. logic array reconfiguration circuit table 7?9. fast pll output signals name description source destination c[3..0] pll outputs driving regional or global clock. pll counter internal clock locked lock or gated lock output from lock detect circuit. active high. pll lock detect logic array scandataout output of the last shift register in the scan chain. pll scan chain logic array scandone signal indicating when the pll has completed reconfiguration. 1 to 0 transition indicates the pll has been reconfigured. pll scan chain logic array table 7?8. fast pll input signals (part 2 of 2) name description source destination
7?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast plls fast pll pins table 7?10 shows the i/o standards supported by the fast pll input pins. table 7?10. i/o standards supported for st ratix ii and stratix ii gx fast pll pins i/o standard inclk lv t t l v lv c m o s v 2.5 v v 1.8 v v 1.5 v v 3.3-v pci 3.3-v pci-x sstl-2 class i v sstl-2 class ii v sstl-18 class i v sstl-18 class ii v 1.8-v hstl class i v 1.8-v hstl class ii v 1.5-v hstl class i v 1.5-v hstl class ii v differential sstl-2 class i differential sstl-2 class ii differential sstl-18 class i differential sstl-18 class ii 1.8-v differential hstl class i 1.8-v differential hstl class ii 1.5-v differential hstl class i 1.5-v differential hstl class ii lv d s v hypertransport technology v differential lvpecl
altera corporation 7?19 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 7?11 shows the physical pins and th eir purpose for the fast plls. for inclk port connections to pins, see ?clocking? on page 7?62 . table 7?11. fast pll pins (part 1 of 2) note (1) pin description clk0p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk1p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk2p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk3p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk8p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. clk9p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. clk10p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. clk11p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. fpll7clkp/n single-ended or differential pins that can drive the inclk port for pll 7. fpll8clkp/n single-ended or differential pins that can drive the inclk port for pll 8. fpll9clkp/n single-ended or differential pins that can drive the inclk port for pll 9 . fpll10clkp/n single-ended or differential pins that can drive the inclk port for pll 10. pll_ena dedicated input pin that drives the pllena port of all or a set of plls. if you do not use this pin, connect it to gnd. vccd_pll digital power for plls. you must connect this pin to 1.2 v, even if the pll is not used. vcca_pll1 analog power for pll 1. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll1 analog ground for pll 1. your can connect this pin to the gnd plane on the board. vcca_pll2 analog power for pll 2. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll2 analog ground for pll 2. you can connect this pin to the gnd plane on the board. vcca_pll3 analog power for pll 3. you must connect this pin to 1.2 v, even if the pll is not used . gnda_pll3 analog ground for pll 3. you can connect this pin to the gnd plane on the board. vcca_pll4 analog power for pll 4. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll4 analog ground for pll 4. you can connect this pin to the gnd plane on the board. gnda_pll7 analog ground for pll 7. you can connect this pin to the gnd plane on the board. vcca_pll8 analog power for pll 8. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll8 analog ground for pll 8. you can connect this pin to the gnd plane on the board. vcca_pll9 analog power for pll 9. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll9 analog ground for pll 9. you can connect this pin to the gnd plane on the board. vcca_pll10 analog power for pll 10. you must connect this pin to 1.2 v, even if the pll is not used.
7?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock feedback modes clock feedback modes stratix ii and stratix ii gx plls support up to five different clock feedback modes. each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. each pll must be driven by one of its own dedicated clock input pins for proper clock compensation. the clock in put pin connections for ea ch pll are listed in table 7?20 on page 7?70 . table 7?12 shows which modes are supported by which pll type. source-synchronous mode if data and clock arrive at the same time at the input pins, they are guaranteed to keep the same phase re lationship at the clock and data ports of any ioe input register. figure 7?9 shows an example waveform of the clock and data in this mode. this mode is reco mmended for source- synchronous data transfers. data and clock signals at the ioe experience similar buffer delays as long as the same i/o standard is used. gnda_pll10 analog ground for pll 10. you can connect this pin to the gnd plane on the board. note to ta b l e 7 ? 11 : (1) the negative leg pins ( clkn and fpll_clkn ) are only required with differential signaling. table 7?11. fast pll pins (part 2 of 2) note (1) pin description table 7?12. clock feedback mode availability clock feedback mode mode available in enhanced plls fast plls source synchronous mode yes yes no compensation mode yes yes normal mode yes yes zero delay buffer mode yes no external feedback mode yes no
altera corporation 7?21 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?9. phase relationship between clock and data in source-synchronous mode in source-synchronous mode, enhanced plls compensate for clock delay to the top and bottom io registers and fast plls compensate for clock delay to the side io registers. whil e implementing source-synchronous receivers in these io banks, use the corresponding pll type for best matching between clock and data de lays (from input pins to register ports). 1 set the input pin to the register delay chain within the ioe to zero in the quartus ii software for all data pins clocked by a source-synchronous mode pll. no compensation mode in this mode, the pll does not comp ensate for any clock networks. this provides better jitter performance be cause the clock f eedback into the pfd does not pass through as much ci rcuitry. both the pll internal and external clock outputs are phase shifted with respect to the pll clock input. figure 7?10 shows an example waveform of the pll clocks? phase relationship in this mode. data pin inclk data at register clock at register
7?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock feedback modes figure 7?10. phase relationship between pll clocks in no compensation mode notes to figure 7?10 . (1) internal clocks fed by the pll are phase-aligned to each other. (2) the pll clock outputs can lead or lag the pll input clocks. normal mode an internal clock in normal mode is phase-aligned to th e input clock pin. the external clock output pin will have a phase delay relative to the clock input pin if connected in this mode. in normal mode, the delay introduced by the gclk or rclk network is fully compensated. figure 7?11 shows an example waveform of the pll clocks? phase relationship in this mode. pll reference clock at the input pin pll clock at the register clock port (1) , (2) external pll clock outputs (2) phase aligned
altera corporation 7?23 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?11. phase relationship betw een pll clocks in normal mode note to figure 7?11 : (1) the external clock output can lead or lag the pll internal clock signals. zero delay buffer mode in the zero delay buffer mode, th e external clock output pin is phase-aligned with the cl ock input pin for zero delay through the device. figure 7?12 shows an example waveform of the pll clocks? phase relationship in this mode. when using this mode, altera requires that you use the same i/o standard on the in put clock, and outp ut clocks. when using single-ended i/o standards, the inclk port of the pll must be fed by the dedicated clkp input pin. pll clock at the register clock port external pll clock outputs (1) phase aligned pll reference clock at the input pin
7?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock feedback modes figure 7?12. phase relationship between pll clocks in zero delay buffer mode note to figure 7?12 : (1) the internal pll clock output can lead or lag the external pll clock outputs. external feedback mode in the external feedback mode, th e external feedback input pin, fbin , is phase-aligned with the clock input pin, (see figure 7?13 ). aligning these clocks allows you to remove clock de lay and skew between devices. this mode is possible on all enhanced plls. plls 5, 6, 11, and 12 support feedback for one of the dedicate d external outputs, either one single-ended or one differential pair. in this mode, one c counter feeds back to the pll fbin input, becoming part of the feedback loop. in this mode, you will be using one of the de dicated external clock outputs (two if a differential i/o standard is used) as the pll fbin input pin. when using this mode, altera requires that you use the same i/o standard on the input clock, feedback input, and output clocks. when using single-ended i/o standards, the inclk port of the pll must be fed by the dedicated clkp input pin. pll clock at the register clock port external pll clock outputs (1) phase aligned pll reference clock at the input pin
altera corporation 7?25 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?13. phase relationship between pll clocks in external feedback mode note to figure 7?13 : (1) the pll clock outputs can lead or lag the f bin clock input. hardware features stratix ii and stratix ii gx plls support a number of features for general-purpose clock management. this section discusses clock multiplication and division im plementation, ph ase-shifting implementations and prog rammable duty cycles. table 7?13 shows which feature is available in which type of stratix ii or stratix ii gx pll. external pll clock outputs (1) pll clock at the register clock port (1) f bin clock input phase aligned pll reference clock at the input pin table 7?13. stratix ii and stratix ii gx pll hardware features (part 1 of 2) hardware features availability enhanced pll fast pll clock multiplication and division m ( n post-scale counter) m ( n post-scale counter) m counter value ranges from 1 through 512 ranges from 1 through 32 n counter value ranges from 1 through 512 ranges from 1 through 4 post-scale counter values ranges from 1 through 512 (1) ranges from 1 through 32 (2)
7?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 hardware features clock multiplication and division each stratix ii pll provides clock synthesis for pll output ports using m /( n post-scale counter) scaling factors. the input clock is divided by a pre-scale factor, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter that di vides down the high-frequency vco. for multiple pll outputs with differen t frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. for example, if output frequencies required from one pll are 33 and 66 mhz, then the quartus ii software sets the vco to 660 mhz (the least common multiple of 33 and 66 mhz within the vco range). then, the post-scale counters scal e down the vco frequency for each output port. there is one pre-scale counter, n , and one multiply counter, m , per pll, with a range of 1 to 512 for both m and n in enhanced plls. for fast plls, m ranges from 1 to 32 while n ranges from 1 to 4. there are six generic post-scale counters in enhanced plls that can feed region al clocks, global clocks, or external clock outputs, all ranging from 1 to 512 with a 50% duty cycle setting for each pll. the post-scale counters range from 1 to 256 with any non-50% duty cycle settin g. in fast plls, there are four post-scale counters ( c0 , c1 , c2 , c3 ) for the regional and global clock output ports. all post-scale counte rs range from 1 to 32 with a 50% duty cycle setting. for non-50% duty cycle clock outputs, the post-scale counters range from 1 to 16. if the desi gn uses a high-speed i/o interface, you can connect the dedicated dffioclk clock output port to allow the high-speed vco frequency to drive the serializer/deserializer (serdes). phase shift down to 125-ps increments (3) down to 125-ps increments (3) programmable duty cycle yes yes notes to table 7?13 : (1) post-scale counters range from 1 through 512 if the output clock uses a 50% duty cycle. for any output clocks using a non-50% duty cycle, the post-scale counters range from 1 through 256. (2) post-scale counters range from 1 through 32 if the output clock uses a 50% duty cycle. for any output clocks using a non-50% duty cycle, the post-scale counters range from 1 through 16. (3) the smallest phase shift is determin ed by the vco period divided by 8. fo r degree increments, the stratix ii device can shift all output frequencies in increments of at least 45 . smaller degree increments are possible depending on the frequency and divide parameters. table 7?13. stratix ii and stratix ii gx pll hardware features (part 2 of 2) hardware features availability enhanced pll fast pll
altera corporation 7?27 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices the quartus ii software automatically chooses the appropriate scaling factors according to the input freque ncy, multiplication, and division values entered into the altpll megafunction. phase-shift implementation phase shift is used to implement a robust solution for clock delays in stratix ii and stratix ii gx devices. phase shift is implemented by using a combination of the vco phase output and the counter starting time. the vco phase output and counter starting time is the most accurate method of inserting delays, since it is purely based on counter settings, which are independent of process, voltage, and temperature. 1 stratix ii and stratix ii gx plls do not support programmable delay elements because thes e delay elements require considerable area on the die and are sensitive to process, voltage, and temperature. you can phase shift the output clocks from the stratix ii or stratix ii gx enhanced pll in either: fine resolution using vco phase taps coarse resolution usin g counter starting time the vco phase tap and coun ter starting time is implemented by allowing any of the output counters ( c[5..0] or m ) to use any of the eight phases of the vco as the reference clock. this allows you to adjust the delay time with a fine resolution. the minimum delay time that you can insert using this method is defined by: where f ref is input reference clock frequency. for example, if f ref is 100 mhz, n is 1, and m is 8, then f vco is 800 mhz and f ine equals 156.25 ps. this phase shif t is defined by the pll operating frequency, which is governed by the reference clock frequency and the counter settings. you can also delay the start of the counters for a predetermined number of counter clocks. you ca n express phase shift as: fine = t vco = = 1 8 1 8 f vco n 8 mf ref coarse = = c ? 1 f (c ? 1) n mf ref v co
7?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 hardware features where c is the count value set for the coun ter delay time, (this is the initial setting in the pll usage section of the compilation report in the quartus ii software). if the initial value is 1, c ? 1 = 0 phase shift. figure 7?14 shows an example of phase sh ift insertion using the fine resolution using vco phase taps meth od. the eight phases from the vco are shown and labeled for reference. for this example, clk0 is based off the 0 phase from the vco and has the c value for the counter set to one. the clk1 signal is divided by four, two vco clocks for high time and two vco clocks for low time. clk1 is based off the 135 phase tap from the vco and also has the c value for the counter set to one. the clk1 signal is also divided by 4. in this ca se, the two clocks are offset by 3 fine . clk2 is based off the 0phase from the vco but has the c value for the counter set to three. this creates a delay of 2 coarse , (two complete vco periods). figure 7?14. delay insertion using vco phase output and counter delay time you can use the coarse and fine ph ase shifts as described above to implement clock delays in stratix ii and stratix ii gx devices. the phase-shift parameters are set in the quartus ii software. t d0-1 t d0-2 1/8 t vco t vco 0 90 135 180 225 270 315 clk0 clk1 clk2 45
altera corporation 7?29 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices programmable duty cycle the programmable duty cycle allows enhanced and fast plls to generate clock outputs with a variable duty cy cle. this feature is supported on each enhanced and fast pll post-scale counter c[] . the duty cycle setting is achieved by a low and high time count setting for the post-scale counters. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. the post-scale counter value determines th e precision of the duty cycle. the precision is defined by 50% divided by the post-scale counter value. the closest value to 100 % is not achievable for a given counter value. for example, if the c0 counter is ten, then steps of 5% are possible for duty cycle choices between 5 to 90%. if the device uses external feedback , you must set the duty cycle for the counter driving the fbin pin to 50%. combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. advanced clear and enable control there are several control signals for cl earing and enabling plls and their outputs. you can use these signals to control pll resynchronization and gate pll output clocks for low-power applications. enhanced lock detect circuit the lock output indicates that the pll has locked onto the reference clock. without any additional ci rcuitry, the lock signal may toggle as the pll begins tracking the refere nce clock. you may need to gate the lock signal for use as a system control. either a gated lock signal or an ungated lock signal from the locked port can drive the logic array or an output pin. the stratix ii and stratix ii gx enhanced and fast plls include a programmable counter that holds the lock signal low for a user-selected number of input clock tr ansitions. this allows the pll to lock before enabling the lock signal. you can use the quartus ii software to set the 20-bit counter value.
7?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 hardware features figure 7?15 shows the timing waveform for the lock and gated lock signals. figure 7?15. timing waveform for lock and gated lock signals the device resets and enables both the counter and the pll simultaneously when the pllena signal is asserted or the areset signal is de-asserted. enhanced plls and fast plls support this feature. to ensure correct circuit operation, and to ensure that the output clocks have the correct phase relationship with respect to the input clock, altera recommends that the input clock be ru nning before the stratix ii device is finished configuring. pll_ena the pll_ena pin is a dedicated pin that enables or disables all plls on the stratix ii or stratix ii gx device. when the pll_ena pin is low, the clock output ports are driven low and all the plls go out of lock. when the pll_ena pin goes high again, the plls relock and resynchronize to the input clocks. you can choose which plls are controlled by the pllena signal by connecting the pllena input port of the altpll megafunction to the common pll_ena input pin. also, whenever the pll loses lock for any reason (be it excessive inclk jitter, clock switchover, pll reconfiguration, power supply noise, etc.), the pll must be reset with the areset signal to guaran tee correct phase relationship between the pll output clocks. if the ph ase relationship between the input clock versus outp ut clock, and between different output clocks from the pll is not im portant in your design, the pll need not be reset. filter counter reaches value count pll_ena reference clock feedback clock lock gated lock
altera corporation 7?31 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices the level of the vccsel pin selects the pll_ena input buffer power. therefore, if vccsel is high, the pll_ena pin?s 1.8/1.5-v input buffer is powered by v ccio of the bank that pll_ena resides in. if vccsel is low ( gnd ), the pll_ena pin?s 3.3/2.5-v input buffer is powered by v ccpd . f for more information on the vccsel pin, refer to the configuring stratix ii and stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook) . pfdena the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you disa ble the pfd, the vco operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. the system continues running when the pll goes out of lock or the input clock is disabled. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. you ca n either use your own control signal or clkloss or gated locked status signals, to trigger pfdena . areset the areset signal is the reset or resynchronization input for each pll. the device input pins or internal logic can drive these input signals. when driven high, the pll counters reset, clearing the pll output and placing the pll out of lock. the vco is set back to its nominal setting (~700 mhz). when driven low again, the pll will resynchronize to its input as it relocks. if the target vco frequency is below this nominal frequency, then the output frequency starts at a higher value than desired as the pll locks. the areset signal should be asserted ev ery time the pll loses lock to guarantee correct phase relationship between the pll input clock and output clocks. users should include the areset signal in designs if any of the following conditions are true: pll reconfiguration or clock swit chover enabled in the design. phase relationships between the pl l input clock and output clocks need to be maintained after a loss of lock condition. if the input clock to the pll is not toggling or is unstable upon power up, assert the areset signal after the input cl ock is toggling, making sure to stay within the input jitter specification. 1 altera recommends that you use the areset and locked signals in your designs to control and observe the status of your pll.
7?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 advanced features clkena if the system cannot tolerate the high er output frequencies when using pfdena higher value, the clkena signals can disable the output clocks until the pll locks. the clkena signals control the regional, global, and external clock outputs. the clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. see figure 7?56 in the ?clock control block? section on page 7?86 of this document for more information on the clkena signals. advanced features stratix ii and stratix ii gx plls offer a variety of advanced features, such as counter cascading, clock switchover, pll reconfiguration, reconfigurable bandwidth, an d spread-spectrum clocking. table 7?14 shows which advanced features are avai lable in which type of stratix ii or stratix ii gx pll. counter cascading the stratix ii and stratix ii gx enha nced pll supports counter cascading to create post-scale counters larger than 512. this is implemented by feeding the output of one counter into the input of the next counter in a cascade chain, as shown in figure 7?16 . table 7?14. stratix ii and stratix ii gx pll advanced features advanced feature availability enhanced plls fast plls (1) counter cascading v clock switchover vv pll reconfiguration vv reconfigurable bandwidth vv spread-spectrum clocking v note to table 7?14 : (1) stratix ii and stratix ii gx fast plls only support manual clock switchover, not automatic clock switchover.
altera corporation 7?33 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?16. counter cascading when cascading counters to implem ent a larger division of the high-frequency vco clock, the cascaded counters behave as one counter with the product of the in dividual counter settings. for example, if c0 = 4 and c1 = 2, then the cascaded value is c0 c1 = 8. 1 the stratix ii and stratix ii gx fast plls does not support counter cascading. counter cascading is set in the config uration file, meaning they can not be cascaded using pll reconfiguration. clock switchover the clock switchover feature allo ws the pll to switch between two reference input clocks. use this feature for clock re dundancy or for a dual clock domain application such as in a system that turns on the redundant clock if the prim ary clock stops running. the design can perform clock switchover automatically, when the cloc k is no longer toggling, or based on a user control signal, clkswitch . 1 enhanced plls support both au tomatic and manual switchover, while fast plls only support manual switchover. automatic clock switchover stratix ii and stratix ii gx device plls support a fully configurable clock switchover capability. figure 7?17 shows the block diagram of the switch-over circuit built into the enha nced pll. when the primary clock signal is not present, the clock sens e block automatically switches from c0 c1 c2 c5 c3 c4 vco output vco output vco output vco output vco output vco output
7?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 advanced features the primary to the secondary clock fo r pll reference. the design sends out the clk0 _ bad, clk1 _ bad , and the clk _ loss signals from the pll to implement a custom switchover circuit. figure 7?17. automatic clock swit chover circuit block diagram there are two possible ways to use the clock switchover feature. use the switchover circuitry for switching from a primary to secondary input of the same frequency. for example, in applications that require a redundant clock wi th the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input shown on the bottom of figure 7?17 . in this case, the secondary clock becomes the reference clock for the pll. this automatic switchover feature only works for switching from the prim ary to secondary clock. use the clkswitch input for user- or system-controlled switch conditions. this is possible for same-frequency switchover or to switch between inputs of different frequencies. for example, if inclk0 is 66 mhz and inclk1 is 100 mhz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. this feature is useful when clock sources can originate from multi ple cards on the backplane, requiring a system-controlled swit chover between frequencies of operation. you should choose the secondary clock frequency so the switch-over state machine clock sense n counter pfd clkswitch provides manual switchover support. clkloss activeclock clk0_bad clk0_bad muxout clksw inclk0 inclk1 refclk fbclk
altera corporation 7?35 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices vco operates within the recommen ded range of 500 to 1,000 mhz. you should also set the m and n counters accordingly to keep the vco operating frequency in the recommended range. figure 7?18 shows an example waveform of the switchover feature when using the automatic clkloss detection. here, the inclk0 signal gets stuck low. after the inclk0 signal is stuck at lo w for approximately two clock cycles, the clock se nse circuitry drives the clk0 _ bad signal high. also, because the reference cloc k signal is no t toggling, the clk _ loss signal goes low, indicating a switch condition. then, the switchover state machine controls the multiplexer through the clksw signal to switch to the secondary clock.
7?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 advanced features figure 7?18. automatic switchover upon clock loss detection notes to figure 7?18 : (1) the number of clock edges before allowing switchover is determined by the counter setting. (2) switchover is enabled on the falling edge of inclk1 . (3) the rising edge of fbclk causes the vco frequency to decrease. (4) the rising edge of refclk starts the pll lock process agai n, and the vco fr equency increases. inclk0 inclk1 muxout refclk fbclk clk0bad clk1bad lock activeclock clkloss pll clock output (1) (2) (3) (4)
altera corporation 7?37 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices the switch-over state machine has two counters that count the edges of the primary and the secondary clocks; counter0 counts the number of inclk0 edges and counter1 counts the number of inclk1 edges. the counters get reset to zero when the count values reach 1, 1; 1, 2; 2, 1; or 2, 2 for i nclock0 and i nclock1 , respectively. for example, if counter0 counts two edges, its coun t is set to two and if counter1 counts two edges before the counter0 sees another edge, they are both reset to 0. if for some reason one of the counters counts to three, it means the other clock missed an edge. the clkbad0 or clkbad1 signal goes high, and the switchover circuitry signals a switch condition. see figure 7?19 . figure 7?19. clock-edge dete ction for switchover manual override when using automatic switchover, you can switch input clocks by using the manual override feature with the clkswitch input. 1 the manual override feature available in automatic clock switchover is different from manual clock switchover. figure 7?20 shows an example of a waveform illustrating the switchover feature when controlled by clkswitch . in this case, both clock sources are functional and inclk0 is selected as the primary clock. clkswitch goes high, which starts the switchover sequence. on the falling edge of inclk0 , the counter?s reference clock, muxout , is gated off to prevent any clock glitching. on the falling edge of inclk1 , the reference clock multiplexer switches from inclk0 to inclk1 as the pll reference. this is also when the clksw signal changes to indicate which clock is selected as primary and which is secondary. the clkloss signal mirrors the clkswitch signal and activeclock mirrors clksw in this mode. since both clocks are still functional during the manual switch, neither clk_bad signal goes high. since the inclk0 inclk1 clkbad0 count of three on single clock indicates other missed edge. reset
7?38 altera corporation stratix ii gx device handbook, volume 2 october 2007 advanced features switchover circuit is edge-sensi tive, the falling edge of the clkswitch signal does not cause the ci rcuit to switch back from inclk1 to inclk0 . when the clkswitch signal goes high again, the process repeats. clkswitch and automatic switch only work if the clock being switched to is available. if the clock is not available, the state machine waits until the clock is available. figure 7?20. clock switchover using the clkswitch control figure 7?21 shows a simulation of using switchover for two different reference frequencies. in this example simulation, the reference clock is either 100 or 66 mhz. th e pll begins with f in = 100 mhz and is allowed to lock. at 20 s, the clock is switched to th e secondary clock, which is at 66 mhz. inclk0 inclk1 muxout clkswtch activeclock clkloss clk0bad clk1bad
altera corporation 7?39 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?21. switchover simulation note (1) note to figure 7?21 : (1) this simulation was performed un der the following conditions: the n counter is set to 2, the m counter is set to 16, and the output counter is set to 8. therefore, the vco operates at 800 mhz for the 100-mhz input references and at 528 mhz for the 66-mhz reference input. lock signal-based switchover the lock circuitry can initiate the auto matic switchover. this is useful for cases where the input clock is still cl ocking, but its characteristics have changed so that the pll is not locked to it. the switchover enable is based on both the gated and ungated lock sign als. if the ungated lock is low, the switchover is not enabled until the gated lock has reached its terminal count. you must activate the switchover enable if the gated lock is high, but the ungated lock goes low. the sw itchover timing for this mode is similar to the waveform shown in figure 7?20 for clkswitch control, except the switchover enable replaces clkswitch . figure 7?17 shows the switchover enable circuit when controlled by lock and gated lock. figure 7?22. switchover enable circuit pll output frequency (x10 mhz) time ( s) 0 1 2 3 4 5 6 7 8 9 10 5 10152025303540 0 lock gated lock switchover enable
7?40 altera corporation stratix ii gx device handbook, volume 2 october 2007 advanced features manual clock switchover stratix ii and stratix ii gx enhanc ed and fast plls support manual switchover, where the clkswitch signal controls whether inclk0 or inclk1 is the input clock to the pll. if clkswitch is low, then inclk0 is selected; if clkswitch is high, then inclk1 is selected. figure 7?23 shows the block diagram of the manual switchover circuit in fast plls. the block diagram of the manual switchover circuit in enhanced plls is shown in figure 7?23 . figure 7?23. manual clock switchov er circuitry in fast plls figure 7?24 shows an example of a waveform illustrating the switchover feature when controlled by clkswitch . in this case, both clock sources are functional and inclk0 is selected as the primary clock. clkswitch goes high, which starts the switch-over sequence. on the falling edge of inclk0 , the counter?s reference clock, muxout , is gated off to prevent any clock glitching. on the rising edge of inclk1 , the reference clock multiplex switches from inclk0 to inclk1 as the pll reference. when the clkswitch signal goes low, the process repeats, causing the circuit to switch back from inclk1 to inclk0 . figure 7?24. manual switchover n counter pfd fbcl k clkswitch inclk0 inclk1 muxout refclk inclk0 inclk1 clkswitch muxout
altera corporation 7?41 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices software support table 7?15 summarizes the signals used for clock switchover. all the switchover ports shown in table 7?15 are supported in the altpll megafunction in the quartus ii software. the altpll megafunction supports two me thods for clock switchover: when selecting an enhanced pll, you can enable both the automatic and the manual switchover, making all the clock switchover ports available. when selecting a fast pll, you can use only enable the manual clock switchover option to select between inclk0 or inclk1 . the clkloss , activeclock and the clkbad0 , and clkbad1 signals are not available when manual switchover is selected. if the primary and secondary cloc k frequencies are different, the quartus ii software selects the proper parameters to keep the vco within the recommended frequency range. table 7?15. altpll megafunction clock switchover signals port description source destination inclk0 reference clk0 to the pll. i/o pin clock switchover circuit inclk1 reference clk1 to the pll. i/o pin clock switchover circuit clkbad0 (1) signal indicating that inclk0 is no longer toggling. clock switchover circuit logic array clkbad1 (1) signal indicating that inclk1 is no longer toggling. clock switchover circuit logic array clkswitch switchover signal used to initiate clock switchover asynchronously. when used in manual switchover, cl kswitch is used as a select signal between inclk0 and inclk1 clswitch = 0 inclk0 is selected and vice versa. logic array or i/o pin clock switchover circuit clkloss (1) signal indicating that the switchover circuit detected a switch condition. clock switchover circuit logic array locked signal indicating that the pll has lost lock. pll clock switchover circuit activeclock (1) signal to indicate which clock (0 = inclk0 , 1= inclk1 ) is driving the pll. pll logic array note for ta b l e 7 ? 1 5 : (1) these ports are only available for enhanced plls an d in auto mode and when using automatic switchover.
7?42 altera corporation stratix ii gx device handbook, volume 2 october 2007 advanced features f for more information on pll software support in the quartus ii software, see the altpll megafunction user guide . guidelines use the following guidelines to design with clock switchover in plls. when using automatic switchover, the clkswitch signal has a minimum pulse width based on the two reference clock periods. the clkswitch pulse width must be greater than or equal to the period of the current reference clock (t from_clk ) multiplied by two plus the rounded-up version of the ratio of the two reference clock periods. for example, if t to_clk is equal to t from_clk , then the clkswitch pulse width should be at least three ti mes the period of the clock pulse. t clkswitchch min t from_clk [2 + int round_up (t to_clk t from_clk )] applications that require a cloc k switchover feature and a small frequency drift should use a low-bandwidth pll. the low-bandwidth pll reacts slower than a high-bandwidth pll to reference input clock changes. when the switchover happens, a low-bandwidth pll propagates th e stopping of the clock to the output slower than a high-band width pll. a low-bandwidth pll filters out jitter on the reference clock. however, be aware that the low-bandwidth pll also increases lock time. stratix ii and stratix ii gx device plls can use both the automatic clock switchover and the clkswitch input simultaneously. therefore, the switchover circuitry can automatically switch from the primary to the secondary clock. on ce the primary clock stabilizes again, the clkswitch signal can switch back to the primary clock. during switchover, the pll_vco continues to run and slows down, generating frequency drift on the pll outputs. the clkswitch signal controls switchover with its rising edge only. if the clock switchover event is gl itch-free, after the switch occurs, there is still a finite resynchronizat ion period to lock onto a new clock as the vco ramps up. the exact amou nt of time it takes for the pll to relock is dependent on the pll configuration. use the pll programmable bandwidth feature to adjust the relock time. if the phase relationship betwee n the input clock to the pll and output clock from the pll is im portant in your design, assert areset for 10ns after performing a clock switchover. wait for the locked signal (or gated lock) to go high before re-enabling the output clocks from the pll.
altera corporation 7?43 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?25 shows how the vco frequency gradually decreases when the primary clock is lost an d then increases as the vco locks on to the secondary clock. after the vco locks on to the secondary clock, some overshoot can occur (an over-frequency condition) in the vco frequency. figure 7?25. vco switchover operating frequency disable the system during switchover if it is not tolerant to frequency variations during the pll resync hronization period. there are two ways to disable the system. first, the system may require some time to stop before switchover occurs. the switchover circuitry includes an optional five-bit counter to de lay when the reference clock is switched. you have the option to cont rol the time-out setting on this counter (up to 32 cycles of latency) before the clock source switches. you can use these cycles for disaster recovery. the clock output frequency varies slightly during those 32 cycles since the vco can still drift without an input clock. programmable bandwidth can control the pll response to limit dr ift during this 32 cycle period. a second option available is the ab ility to use the pfd enable signal ( pfdena ) along with user-defined control logic. in this case you can use clk0 _ bad and clk1 _ bad status signals to turn off the pfd so the vco maintains its last frequency. you can also use the state machine to switch over to the second ary clock. upon re-enabling the pfd, output clock enable signals ( clkena ) can disable clock outputs during the switchover and resynchr onization period. once the lock indication is stable, the system can re-enable the output clock(s). f vco primary clock stops running switchover occurs frequency overshoot vco tracks secondary cloc k
7?44 altera corporation stratix ii gx device handbook, volume 2 october 2007 reconfigurable bandwidth reconfigurable bandwidth stratix ii and stratix ii gx enhanced and fast plls provide advanced control of the pll bandwidth us ing the pll loop?s programmable characteristics, including loop filter and charge pump. background pll bandwidth is the measure of the pll?s ability to track the input clock and jitter. the closed-loop gain 3-db frequency in the pll determines the pll bandwidth. the bandwidth is approximately the unity gain point for open loop pll response. as figure 7?26 shows, these points correspond to approximately the same frequency. figure 7?26. open- and closed-loop response bode plots increasing the pll's bandwidth in effect pushes the open loop response out. gain gain 0 db frequency frequency open-loop reponse bode plot closed-loop reponse bode plot
altera corporation 7?45 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices a high-bandwidth pll provid es a fast lock time and tracks jitter on the reference clock source, passing it through to the pll output. a low-bandwidth pll filters out reference clock, but increases lock time. stratix ii and stratix ii gx enhanced and fast plls allow you to control the bandwidth over a finite range to customize the pll characteristics for a particular applicatio n. the programmable bandwidth feature in stratix ii and stratix ii gx plls benefits applications requiring clock switchover (e.g., tdma frequency hopping wireless, and redundant clocking). the bandwidth and stability of such a system is determined by the charge pump current, the loop filter resis tor value, the high -frequency capacitor value (in the loop filter), and the m -counter value. you can use the quartus ii software to control these factors and to set the bandwidth to the desired value within a given range. you can set the bandwidth to the appropriate value to balance the need for jitter filtering and lock time. figures 7?27 and 7?28 show the output of a low- and high-bandwidth pll, respectively, as it locks onto the input clock.
7?46 altera corporation stratix ii gx device handbook, volume 2 october 2007 reconfigurable bandwidth figure 7?27. low-bandwidth pll lock time 05 15 10 time ( s) frequency (mhz) 120 125 130 135 140 145 150 155 160 lock time = 8 s
altera corporation 7?47 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?28. high-bandwidth pll lock time a high-bandwidth pll can benefit a sy stem that has two cascaded plls. if the first pll us es spread spectrum (as user-induced jitter), the second pll can track the jitter that is fe eding it by using a high-bandwidth setting. a low-bandwidth pll can, in this case, lose lock due to the spread-spectrum-induced jitter on the input clock. a low-bandwidth pll benefits a system using clock switchover. when the clock switchover happens, the pll input temporarily stops. a low-bandwidth pll would react more slowly to changes to its input clock and take longer to drift to a lo wer frequency (caused by the input stopping) than a hi gh-bandwidth pll. figures 7?29 and 7?30 demonstrate this property. the two plots show the effects of clock switchover with a low- or high -bandwidth pll. when the clock switchover happens, the output of the low-bandwidth pll (see figure 7?29 ) drifts to a lower frequency more slowly than the high-bandwidth pl l output (see figure 7?30 ). 0 120 125 130 135 140 145 150 155 160 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time ( s) frequency (mhz) lock time = 4 s
7?48 altera corporation stratix ii gx device handbook, volume 2 october 2007 reconfigurable bandwidth figure 7?29. effect of low bandwidth on clock switchover 0 150 152 154 156 158 160 162 164 5 10152025303540 time ( s) frequency (mhz) initial lock input clock stops re-lock switchover
altera corporation 7?49 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?30. effect of high bandwidth on clock switchover implementation traditionally, external components such as the vco or loop filter control a pll?s bandwidth. most loop filters are made up of passive components such as resistors and capacitors that take up unnecessary board space and increase cost. with stratix ii and stra tix ii gx plls, all the components are contained within the device to increase performance and decrease cost. stratix ii and stratix ii gx device plls implement reconfigurable bandwidth by giving you control of the charge pump current and loop filter resistor (r) and high-frequency capacitor c h values (see table 7?16 ). the stratix ii and stratix ii gx devi ce enhanced pll bandwidth ranges from 130 khz to 16.9 mhz. the stratix i i and stratix ii gx device fast pll bandwidth ranges from 1.16 to 28 mhz. 0 125 130 135 140 145 150 155 160 2 4 6 8 10 12 14 16 18 20 time ( s) frequency (mhz) initial lock input clock stops re-lock switchover
7?50 altera corporation stratix ii gx device handbook, volume 2 october 2007 reconfigurable bandwidth the charge pump current directly affects the pll bandwidth. the higher the charge pump current, the higher the pll bandwidth. you can choose from a fixed set of values for the charge pump current. figure 7?31 shows the loop filter and the components th at can be set through the quartus ii software. the components are the loop filter resistor, r, and the high frequency capacitor, c h , and the charge pump current, i up or i dn . figure 7?31. loop filter programmable components software support the quartus ii software provides two levels of bandwidth control. megafunction-based bandwidth setting the first level of programmable bandwidth allows you to enter a value for the desired bandwidth directly in to the quartus ii software using the altpll megafunction. you can also set the bandwidth parameter in the altpll megafunction to the desired ba ndwidth. the quartus ii software selects the best bandwidth parameters available to match your bandwidth request. if the individual bandwidth setting request is not available, the quartus ii software se lects the closest achievable value. advanced bandwidth setting an advanced level of control is also possible using advanced loop filter parameters. you can dynamically change the charge pump current, loop filter resistor value, and the loop fi lter (high frequency) capacitor value. i up i dn c h pfd r c
altera corporation 7?51 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices the parameters for these changes are: charge _ pump _ current , loop _ filter _ r , and loop _ filter _ c . each parameter supports the specific range of values listed in table 7?16 . f for more information on quartus ii software support of reconfigurable bandwidth, see the design example: dynami c pll reconfiguration section in volume 3, ve r i f i c a t i o n , of the quartus ii develo pment software handbook . pll reconfiguration plls use several divide counters and different vco phase taps to perform frequency synthesis and phase shifts. in stratix ii and stratix ii gx enhanced and fast plls, the counter value and phase are configurable in real time. in addition , you can change th e loop filter and charge pump components, which affect the pll bandwidth, on the fly. you can control these pll components to update the output clock frequency, pll bandwidth, and phase-sh ift variation in real time, without the need to reconfig ure the entire fpga. f for more information on pll reconfiguration, see an 367: implementing pll reconfiguration in stratix ii devices . spread- spectrum clocking digital cloc ks are square waves with short rise times and a 50% duty cycle. these high-speed clocks concentrate a sign ificant amount of energy in a narrow bandwidth at the target frequency and at the higher frequency harmonics. this results in high energy peaks and increased electromagnetic interferen ce (emi). the radiated noise from the energy peaks travels in free air and, if not minimized, can lead to corrupted data and intermittent system errors, whic h can jeopardize system reliability. traditional methods for limiting emi include shielding, filtering, and multi-layer printed circuit boards (pcbs). however, these methods significantly increase the overall system cost and sometimes are not table 7?16. advanced loop filter parameters parameter values resistor values (k ) (1) high-frequency capacit ance values (pf) (1) charge pump current settings ( ?) (1) note to table 7?16 : (1) for more information, see an 367: implementing pll reconfiguration in stratix ii devices .
7?52 altera corporation stratix ii gx device handbook, volume 2 october 2007 spread-spectrum clocking enough to meet emi compliance. sp read-spectrum technology provides you with a simple and effective technique for reducing emi without additional cost and the trou ble of re-designing a board. spread-spectrum technology modulates the target frequency over a small range. for example, if a 100-mhz signal has a 0.5% down-spread modulation, then the frequency is swept from 99.5 to 100 mhz. figure 7?32 gives a graphical representation of the energy present in a spread-spectrum signal vs. a non-spre ad spectrum-signal. it is apparent that instead of concentrating the en ergy at the target frequency, the energy is re-distributed across a wider band of frequencies, which reduces peak energy. not only is there a reduction in the fundamental peak emi components, but there is also a reduction in emi of the higher order harmonics. since some regulations focus on peak emi emissions, rather than average emi emissions, spread-spectrum technology is a valuable method of emi reduction. figure 7?32. spread-spectrum signal energy ve rsus non-spread-spectrum signal energy spread-spectrum technology would benefit a design with high emi emissions and/or strict emi requir ements. device-generated emi is dependent on frequency and output voltage swing amplitude and edge rate. for example, a design using lvds already has low emi emissions = 0.5 % = ~5 db amplitude (db) frequency (mhz) spread-spectrum signal non-spread-spectrum signal
altera corporation 7?53 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices because of the low-voltage swing. th e differential lvds signal also allows for emi rejection within the si gnal. therefore, this situation may not require spread-spectrum technology. 1 spread-spectrum clocking is only supported in stratix ii enhanced plls, not fast plls. implementation stratix ii and stratix ii gx device enhanced plls feature spread-spectrum technology to reduce the emis emitted from the device. the enhanced pll provides approximately 0.5% down spread using a triangular, also known as linear, mo dulation profile. the modulation frequency is programmable and ra nges from approximately 100 to 500 khz. the spread percentage is based on the clock input to the pll and the m and n settings. spread-spectrum technology reduces the peak energy by four to six db at the target fr equency. however, this number is dependent on bandwidth and the m and n counter values and can vary from design to design. spread percentage, also known as mo dulation width, is defined as the percentage that the design modulates the target frequency. a negative (?) percentage indicates a down spread, a positive (+) percentage indicates an up spread, and a ( ) indicates a center spread. modulation frequency is the frequency of the spreading sign al, or how fast the signal sweeps from the minimum to the maximum frequency. down-spread modulation shifts the target freq uency down by half the spread percentage, centering the modulated waveforms on a new target frequency. the m and n counter values are toggled at the same time between two fixed values. the loop fi lter then slowly changes the vco frequency to provide the spreading effect, which results in a triangular modulation. an additional spread-spect rum counter (shown in figure 7?33 ) sets the modulation frequency. figure 7?33 shows how spread-spectrum technology is implemented in the stratix ii and stratix ii gx device enhanced pll.
7?54 altera corporation stratix ii gx device handbook, volume 2 october 2007 spread-spectrum clocking figure 7?33. stratix ii and stratix ii gx spread-spectrum ci rcuit block diagram figure 7?34 shows a vco frequency waveform when toggling between different counter values. since the enhanced pll switches between two different m and n values, the result is a straight line between two frequencies, which gives a linear modulation. the magnitude of modulation is determined by the ratio of two m / n sets. the percent spread is determined by: percent spread = (f vcomax -f vcomin )/f vcomax =1 [( m 2 n 1 )/( m 1 n 2 )]. the maximum and minimum vco frequency is defined as: f vcomax =( m 1 / n 1 )f ref f vcomin =( m 2 / n 2 )f ref figure 7?34. vco frequency modulation waveform n n count1 n count2 pfd up down spread- spectrum counter m m count1 m count2 refclk count2 values count1 values vco frequency
altera corporation 7?55 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices software support you can enter the desired down-spread percentage and modulation frequency in the altpll megafunction through the quartus ii software. alternatively, the downspread parameter in the altpll megafunction can be set to the desired down-spread percentage. timing analysis ensures the design operates at the maximum spread frequency and meets all timing requirements. f for more information on pll software support in the quartus ii software, see the altpll megafunction user guide . guidelines if the design cascades plls, the source (upstream) pll should have a low-bandwidth setting, while the destination (downstream) pll should have a high-bandwidth setting. the upstream pll must have a low-bandwidth setting because a pll do es not generate jitter higher than its bandwidth. the downstream pll mu st have a high bandwidth setting to track the jitter. the design must use the spread-spectrum feature in a low-bandwidth pll, and, theref ore, the quartus ii software automatically sets the spread-s pectrum pll bandwidth to low. 1 if the programmable or reconfig urable bandwidth features are used, then you cannot use spread spectrum. stratix ii and stratix ii gx devices can accept a spread-spectrum input with typical modulation frequenc ies. however, the device cannot automatically detect that the input is a spread-spectrum signal. instead, the input signal looks like determin istic jitter at the input of the downstream pll. spread spectrum can have a minor effect on the output clock by increasing the period jitter. period jitt er is the deviation of a clock?s cycle time from its previous cycle position . period jitter measures the variation of the clock output tran sition from its ideal po sition over consecutive edges. with down-spread modulation, the pe ak of the modulated waveform is the actual target frequency. therefore, the system never exceeds the maximum clock speed. to maintain reliable communication, the entire system and subsystem should use the stratix ii and strati x ii gx device as the clock source. communication could fail if the stratix ii or stratix ii gx logic array is clocked by the spread-spectrum clock, but the data it receives from another devi ce is not clocked by the spread spectrum.
7?56 altera corporation stratix ii gx device handbook, volume 2 october 2007 board layout since spread spectrum affects the m counter values, all spread-spectrum pll outputs are effected. therefore, if only one spread-spectrum signal is needed, the clock signal should use a separate pll without other outputs from that pll. no special considerations are needed when using spread spectrum with the clock switchover feature. this is because the clock switchover feature does not affect the m and n counter values, which are the counter values switching when using spread spectrum. board layout the enhanced and fast pll circuits in stratix ii and stratix ii gx devices contain analog components embedded in a digital device. these analog components have separate power an d ground pins to minimize noise generated by the digital components. stratix ii and stratix ii gx enhanced and fast plls use separate v cc and ground pins to isolate circuitry and improve noise resistance. v cca and gnda each enhanced and fast pll uses separate v cc and ground pin pairs for their analog circuitry. the analog ci rcuit power and ground pin for each pll is called vcca_pll < pll number > and gnda_pll < pll number >. connect the v cca power pin to a 1.2-v power supply, even if you do not use the pll. isolate the power connected to v cca from the power to the rest of the stratix ii or stratix ii gx device or any other digital device on the board. you can use one of three different methods of isolating the v cca pin: separate v cca power planes, a partitioned v cca island within the v ccint plane, and thick v cca traces. separate v cca power plane a mixed signal system is already partitioned into analog and digital sections, each with its own power plan es on the board. to isolate the v cca pin using a separate v cca power plane, connect the v cca pin to the analog 1.2-v power plane. partitioned v cca island within v ccint plane fully digital systems do not have a separate analog power plane on the board. since it is expensive to add ne w planes to the board, you can create islands for vcca_pll . figure 7?35 shows an example board layout with an analog power island. the dielectric boundary that creates the island should be 25 mils thick. figure 7?36 shows a partitioned plane within v ccint for v cca .
altera corporation 7?57 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?35. v ccint plane partitioned for v cca island thick v cca trace because of board constraints, you may not be able to partition a v cca island. instead, run a thick trac e from the power supply to each v cca pin. the traces should be at least 20 mils thick. in each of these three cases, you should filter each vcca_pll pin with a decoupling circuit, as shown in figure 7?36 . place a ferrite bead that exhibits high impedance at freque ncies of 50 mhz or higher and a 10- f tantalum parallel capacitor where the power enters the board. decouple each vcca_pll pin with a 0.1- f and 0.001- f parallel combination of ceramic capacitors located as close as possible to the stratix ii or stratix ii gx device. you can connect the gnda_pll pins directly to the same ground plane as the device?s digital ground.
7?58 altera corporation stratix ii gx device handbook, volume 2 october 2007 board layout figure 7?36. pll power schematic for stratix ii and stra tix ii gx plls note to figure 7?36 (1) applies to plls 1 through 12. v ccd the digital power and ground pins are labeled vccd_pll < pll number > and gnd . the vccd pin supplies the power for the digital circuitry in the pll. connect these vccd pins to the quietest digi tal supply on the board. in most systems, this is the digital 1.2-v supply supplied to the device?s v ccint pins. connect the vccd pins to a power supply even if you do not use the pll. when connecting the v ccd pins to v ccint , you do not need any filtering or isolation. you can connect the gnd pins directly to the same ground plane as the device?s digital ground. see figure 7?36 . external clock output power enhanced plls 5, 6, 11, and 12 also have isolated power pins for their dedicated external clock outputs ( vcc_pll5_out , vcc_pll6_out , vcc_pll11_out and vcc_pll12_out , respectively). since the vcca_pll # gnda_pll # vccd_pll # gnd 1.2-v supply repeat for each pll power & ground set stratix ii device ferrite bead 0.1 f 0.001 f gnd gnd 10 f gnd gnd (1) (1) v ccint
altera corporation 7?59 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices dedicated external clock outputs fr om a particular enhanced pll are powered by separate power pins, they are less susceptibl e to noise. they also reduce the overall jitter of th e output clock by providing improved isolation from switching i/o pins. 1 i/o pins that reside in pll ba nks 9 through 12 are powered by the vcc_pll < 5, 6, 11, or 12 > _out pins, respectively. the ep2s60f484, ep2s60f780, ep 2s90h484, ep2s90f780, and ep2s130f780 devices do not support plls 11 and 12. therefore, any i/o pins that reside in bank 11 are powered by the vccio3 pin, and any i/o pins that reside in bank 12 are powered by the vccio8 pin. the vcc_pll_out pins can by powered by 3. 3, 2.5, 1.8, or 1.5 v, depending on the i/o standard for th e clock output from a particular enhanced pll, as shown in figure 7?37 .
7?60 altera corporation stratix ii gx device handbook, volume 2 october 2007 board layout figure 7?37. external clock output pi n association with output power filter each isolated power pin with a decoupling circuit shown in figure 7?38 . decouple the isolated power pi ns with parallel combination of 0.1- and 0.001- f ceramic capacitors located as close as possible to the stratix ii or stratix ii gx device. vcc_pll5_out pll5_out0p pll5_out0n pll5_out1p pll5_out1n pll5_out2p pll5_out2n
altera corporation 7?61 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?38. stratix ii and strati x ii gx pll external cl ock output power ball connection note (1) note to figure 7?38 : (1) applies only to enhanced plls 5, 6, 11, and 12. guidelines use the following guidelines for optimal jitter performance on the external clock outputs from enhanced pl ls 5, 6, 11, and 12. if all outputs are running at the same frequency, these guidelines ar e not necessary to improve performance. use phase shift to ensure edges are not coincident on all the clock outputs. use phase shift to skew clock edges with respect to each other for best jitter performance. if you cannot drive multiple clocks of different frequencies and phase shifts or isolate banks, you should control the drive capability on the lower-frequency clock. reducing how much current the output buffer has to supply can reduce the noise. minimi ze capacitive load on the slower frequency output and configure the output buffer to lower current strength. the higher-frequency outp ut should have an improved performance, but this may degrade the performance of your lower- frequency clock output. vcc_pll#_out (1) vcc_pll#_out (1) v ccio supply stratix ii or stratix ii gx device 0.1 f 0.001 f gnd gnd 0.1 f 0.001 f gnd gnd
7?62 altera corporation stratix ii gx device handbook, volume 2 october 2007 pll specifications pll specifications f see the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook (or the stratix ii device handbook ) for information on pll timing specifications clocking stratix ii and stratix ii gx devices pr ovide a hierarchical clock structure and multiple plls with ad vanced features. the large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast plls provides a complete clock-management solution. global and hierarchical clocking stratix ii and stratix ii gx devices provide 16 dedicated global clock networks and 32 regional clock networ ks. these clocks are organized into a hierarchical clock structure that al lows for 24 unique clock sources per device quadrant with low skew and delay. this hierarchical clocking scheme provides up to 48 unique clock domains within the entire stratix ii or stratix ii gx device. table 7?17 lists the clock resources available on stratix ii devices. there are 16 dedicated clock pins ( clk[15..0] ) on stratix ii and stratix ii gx devices to drive either th e global or region al clock networks. four clock pins drive each side of the stratix ii device, as shown in figures 7?39 and 7?40 . enhanced and fast pll outputs can also drive the global and regional clock networks. table 7?17. clock resource availability in st ratix ii and stratix ii gx devices (part 1 of 2) description stratix ii device availability stratix ii gx device availability number of clock input pins 24 12 number of global clock networks 16 16 number of regional clock networks 32 32 global clock input sources clock input pins, pll outputs, logic array clock input pins, pll outputs, logic array, inter-transceiver clocks regional clock input sources clock input pins, pll outputs, logic array clock input pins, pll outputs, logic array, inter-transceiver clocks number of unique clock sources in a quadrant 24 (16 global clocks and 8 regional clocks) 24 (16 gclk and 8 rclk clocks) number of unique clock sources in the entire device 48 (16 global clocks and 32 regional clocks) 48 (16 gclk and 32 rclk clocks)
altera corporation 7?63 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices global clock network global clocks drive throughout the entire device, feeding all device quadrants. all resources within the device ioes, adaptive logic modules (alms), digital signal processing (d sp) blocks, and all memory blocks can use the global clock networks as clock sources. these resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed by an external pin. internal logic can also drive the global clock networks for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. figure 7?39 shows the 16 dedicated clk pins driving global clock networks. figure 7?39. global clocking note (1) note to figure 7?39 : (1) stratix ii gx devices do not have plls 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11. power-down mode global clock networks, regional clock networks, dual-regional clock region gclk, rclk networks, dual-regional clock region clocking regions for high fan-out applications quadrant region, dual-regional, entire device via global clock or regional clock networks quadrant region, dual-regional, entire device via gclk or rclk networks table 7?17. clock resource availability in st ratix ii and stratix ii gx devices (part 2 of 2) description stratix ii device availability stratix ii gx device availability 11 5 7 1 2 8 12 6 10 4 3 9 gclk0-3 gclk4-7 gclk8-11 gclk12 - 15 clk12-15 clk4-7 clk0-3 clk8-11 16 16 16 16
7?64 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking regional clock network eight regional clock networks within each quadrant of the stratix ii and stratix ii gx device are driven by the dedicated clk[15..0] input pins or from pll outputs. the regional clock networks only pertain to the quadrant they drive into. the regional clock networks provide the lowest clock delay and skew for logic cont ained within a single quadrant. internal logic can also drive the regi onal clock networks for internally generated regional clocks and asynch ronous clears, clock enables, or other control signals with large fanout.the clk clock pins symmetrically drive the rclk networks within a particular quadra nt, as shown in figure 7?40 . refer to table 7?18 on page 7?67 and table 7?19 on page 7?68 for rclk connections from clk pins and plls. figure 7?40. regional clocking note (1) note to figure 7?40 : (1) stratix ii gx devices do not have plls 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11. clock sources per region each stratix ii and stratix ii gx device has 16 global clock networks and 32 regional clock networks that prov ide 48 unique clock domains for the entire device. there are 24 unique clocks available in each quadrant (16 global clocks and 8 regional clocks) as the input resources for registers (see figure 7?41 ). 11 5 7 1 2 8 6 10 4 3 9 rclk0-3 rclk4-7 rclk8-11 rclk12-15 rclk20-23 rclk24-27 rclk28-31 clk12-15 clk4-7 clk0 -3 clk8-11 rclk16-19 q1 q4 q2 q3 12
altera corporation 7?65 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?41. hierarchical clock networks per quadrant stratix ii and stratix ii gx clock netw orks provide three different clocking regions: entire device clock region quadrant cl ock region dual-regional clock region these clock network option s provide more flexibility for routing signals that have high fan-out to improve th e interface timing. by having various sized clock regions, it is possible to prioritize the number of registers the network can reach versus the total delay of the network. in the first clock scheme, a source (not necessarily a clock signal) drives a global clock network that can be rout ed through the entire device. this has the maximum delay for a low skew high fan-out signal but allows the signal to reach every block within the device. this is a good option for routing global resets or clear signals. in the second clock scheme, a source drives a single-quadrant region. this represents the fastest, low-skew, high-fan-out signal-routing resource within a quadrant. the limitation to this resource is that it only covers a single quadrant. in the third clock scheme, a single source (clock pin or pll output) can generate a dual-regional clock by driving two regional clock network lines (one from each quadrant). this allows logic that spans multiple quadrants to utilize the same low-skew clock. the routing of this signal on an entire side has approximately the same speed as in a quadrant clock region. the internal logic-array rout ing that can drive a regional clock also supports this feature. this means internal logic can drive a clock [23..0] column i/o cell io_clk[7..0] lab row clock [5..0] row i/o cell io_clk[7..0] global clock network [15..0] regional clock network [7..0] clocks available to a quadrant or half-quadrant
7?66 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking dual-regional clock network. corner fast pll output s only span one quadrant and hence cannot form a dual-regional clock network. figure 7?42 shows this feature pictorially. figure 7?42. stratix ii and stratix ii gx dual-regional clock region the 16 clock input pins, enhanced or fa st pll outputs, and internal logic array can be the clock input sources to drive onto either global or regional clock networks. the clkn pins also drive the global clock network as shown in table 7?22 on page 7?72 . tables 7?18 and 7?19 for the connectivity between clk pins as well as the gl obal and regional clock networks. clock inputs the clock input pins clk[15..0] are also used for high fan-out control signals, such as asynchronous clears, presets, clock enables, or protocol signals such as trdy and irdy for pci through global or regional clock networks. internal logic array each global and regional clock networ k can also be driven by logic-array routing to enable internal logic to dr ive a high fan-out, low-skew signal. pll outputs all clock networks can be driven by the pll counter outputs. clock pins or pll outputs can drive half of the device to create dual-reginal clocking regions for improved i/o interface timing.
altera corporation 7?67 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 7?18 shows the connection of the clock pins to the global clock resources. the reason for the higher level of connectivity is to support user controllable global clock multiplexing. table 7?18. clock input pin connecti vity to global clock networks clock resource clk(p) (pin) 0123456789101112131415 gclk0 v v gclk1 v v gclk2 v v gclk3 v v gclk4 v v gclk5 v v gclk6 v v gclk7 v v gclk8 v (1) v (1) gclk9 v (1) v (1) gclk10 v (1) v (1) gclk11 v (1) v (1) gclk12 v v gclk13 v v gclk14 v v gclk15 v v note to table 7?18 : (1) clock pins 8, 9, 10, and 11 are not available in stratix ii gx devices. therefore, these connections do not exist in stratix ii gx devices.
7?68 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking table 7?19 summarizes the connectivity be tween the clock pins and the regional clock networks. here, each cl ock pin can drive two regional clock networks, facilitating stitching of the clock networks to support the ability to drive two quadrants wi th the same clock or signal. table 7?19. clock input pin connectivity to regional clock networks (part 1 of 2) clock resource clk(p) (pin) 0123456789101112131415 rclk0 v rclk1 v rclk2 v rclk3 v rclk4 v rclk5 v rclk6 v rclk7 v rclk8 v rclk9 v rclk10 v rclk11 v rclk12 v rclk13 v rclk14 v rclk15 v rclk16 v (1) rclk17 v (1) rclk18 v (1) rclk19 v (1) rclk20 v (1) rclk21 v (1) rclk22 v (1)
altera corporation 7?69 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices clock input connections four clk pins drive each enhanced pll. you can use any of the pins for clock switchover inputs into the pll. the clk pins are the primary clock source for clock switchover, which is controlled in the quartus ii software. enhanced plls 5, 6, 11, an d 12 also have feedback input pins, as shown in table 7?20 . input clocks for fast plls 1, 2, 3, and 4 come from clk pins. a multiplexer chooses one of two possible clk pins to drive each pll. this multiplexer is not a clock switchover multiplexer and is only used for clock input connectivity. either an fpllclk input pin or a clk pin can drive the fast plls in the corners (7, 8, 9, and 10) when used for general-purpose applications. clk pins cannot drive these fast plls in high-speed differential i/o mode. rclk23 v (1) rclk24 v rclk25 v rclk26 v rclk27 v rclk28 v rclk29 v rclk30 v rclk31 v note to table 7?19 : (1) clock pins 8, 9, 10, and 11 are not available in stratix ii gx devices. therefore, these connections do not exist in stratix ii gx devices. table 7?19. clock input pin connectivity to regional clock networks (part 2 of 2) clock resource clk(p) (pin) 0123456789101112131415
7?70 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking tables 7?20 and 7?21 show which plls are availa ble in each stratix ii and stratix ii gx device, respectively, and which input clock pin drives which plls. table 7?20. stratix ii device plls and pll clock pin drivers (part 1 of 2) input pin all devices ep2s60 to ep2s180 devices fast plls enhanced plls fast plls enhanced plls 12345678 9101112 clk0 v v v (1) v (1) clk1 (2) v v v (1) v (1) clk2 v v v (1) v (1) clk3 (2) v v v (1) v (1) clk4 vv clk5 vv clk6 v v clk7 v v clk8 v v v (1) v (1) clk9 (2) vv v (1) v (1) clk10 v v v (1) v (1) clk11 (2) v v v (1) v (1) clk12 vv clk13 v v clk14 v v clk15 v v pll5_fb v pll6_fb v pll11_fb v pll12_fb v pll_ena v v v v v v v v v v v v fpll7clk (2) v fpll8clk (2) v fpll9clk (2) v
altera corporation 7?71 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices fpll10clk (2) v notes to table 7?20 : (1) clock connection is available. for more information on the maximum frequency, contact altera applications. (2) this is a dedicated high-speed cl ock input. for more information on the maximum frequency, contact altera applications. table 7?21. stratix ii gx device plls and pll clock pin drivers (part 1 of 2) input pin all devices ep2sgx60 to ep2sgx130 devices fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12 clk0 v v v (2) v (2) clk1 (2) v v v (2) v (2) clk2 v v v (2) v (2) clk3 (2) v v v (2) v (2) clk4 vv clk5 vv clk6 v v clk7 v v clk8 (4) clk9 (3) , (4) clk10 (4) clk11 (3) , (4) clk12 vv clk13 v v clk14 v v clk15 v v pll5_fb v pll6_fb v pll11_fb v table 7?20. stratix ii device plls and pll clock pin drivers (part 2 of 2) input pin all devices ep2s60 to ep2s180 devices fast plls enhanced plls fast plls enhanced plls 12345678 9101112
7?72 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking clk(n) pin connectivity to global clock networks in stratix ii and stratix ii gx devices, the clk(n) pins can also feed the global clock network. table 7?22 shows the clk(n) pin connectivity to global clock networks. pll12_fb v pll_ena v v v v v v v v fpll7clk (3) v fpll8clk (3) v fpll9clk (3) fpll10clk (3) notes to table 7?21 : (1) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. (2) clock connection is available. for more information on the maximum frequency, contact altera applications. (3) this is a dedicated high-speed cl ock input. for more information on the maximum frequency, contact altera applications. (4) input pins clk[11..8] are not available in stratix ii gx devices. table 7?21. stratix ii gx device plls and pll clock pin drivers (part 2 of 2) input pin all devices ep2sgx60 to ep2sgx130 devices fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12 table 7?22. clk(n) pin connectivity to global clock network clock resource clk(n) pin 4 5 6 7 12 13 14 15 gclk4 v gclk5 v gclk6 v gclk7 v gclk12 v gclk13 v gclk14 v gclk15 v
altera corporation 7?73 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices clock source control for enhanced plls the clock input multiplexer for enhanced plls is shown in figure 7?43 . this block allows selection of th e pll clock reference from several different sources. the clock source to an enhanced pll can come from any one of four clock input pins clk[3..0] , or from a logic-array clock, provided the logic array clock is driv en by an output from another pll, a pin-driven dedicated global or region al clock, or through a clock control block, provided the clock control bloc k is fed by an ou tput from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot dr ive the pll. the clock input pin connections to the respective enhanced plls are shown in table 7?20 above. the multiplexer select lines ar e set in the configuration file only. once programmed, this block cannot be changed without loading a new configuration file. the quartus ii software automatically sets the multiplexer select signals depending on the clock sources that a user selects in the design. figure 7?43. enhanced pll clock input multiplex logic note to figure 7?43 : (1) the input clock multiplexing is controll ed through a configuration file only and cannot be dynamically controlled in user mode. clock source control for fast plls each center fast pll has five clock input sources, four from clock input pins, and one from a logic array signal , provided the logic array signal is driven by an output from another p ll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. when using cl ock input pins as the clock source, you can perform manual clock switchov er among the input clock sources. (1) clk[3..0] core_inclk inclk1 inclk0 to the clock switchover bloc k (1) 4 4
7?74 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking the clock input multipl exer control signals for performing clock switchover are from core signals. figure 7?44 shows the clock input multiplexer control circuit for a center fast pll. figure 7?44. center fast pll cloc k input multiplexer control note to figure 7?44 : (1) the input clock multiplexing is controll ed through a configuration file only and cannot be dynamically controlled in user mode. each corner fast pll has three clock input sources, one from a dedicated corner clock input pin, one from a ce nter clock input pin, and one from a logic array clock, provided the logic a rray signal is driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pl l or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. figure 7?45 shows a block diagram showin g the clock input multiplexer control circuit for a corner fast pll. only the corner fpllclk pin is fully compensated. figure 7?45. corner fast pll cloc k input multiplexer control note to figure 7?45 : (1) the input clock multiplexing is controll ed through a configuration file only and cannot be dynamically controlled in user mode. 4 inclk0 inclk1 to the cloc k switchover block (1) (1) clk[3..0] core_inclk core_inclk 4 inclk0 inclk1 to the cloc k switchover block (1) (1) fpllclk center clocks core_inclk core_inclk
altera corporation 7?75 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices delay compensatio n for fast plls each center fast pll can be fed by any one of four possible input clock pins. among the four clock inpu t signals, only two are fully compensated, i.e., the clock delay to th e fast pll matches the delay in the data input path when used in the lvds receiver mode. the two clock inputs that match the data input path are located right next to the fast pll. the two clock inputs that do not match the data input path are located next to the neighboring fast pll. figure 7?46 shows the above description for the left-side center fast pll pair. if the pll is used in non-lvds modes, then any of the four dedicated clock inputs can be used and are compensated. fast pll 1 and pll 2 can choose among clk[3..0] as the clock input source. however, for fast pll 1, only clk0 and clk1 have their delay matched to the data input path delay when used in the lvds receiver mode operation. the delay from clk2 or clk3 to fast pll 1 does not match the data input delay. for fast pll 2, only clk2 and clk3 have their delay matched to the data input path delay in lvds receiver mode operation. the delay from clk0 or clk1 to fast pll 2 does not match the data input delay. the same arrangement applies to the right side center fast pll pair. for corner fast plls, only the corner fpllclk pins are fully compensated. for lvds receiver operation, it is recommended to use the delay compensated clock pins only. figure 7?46. delay compensated clock input pins for center fast pll pair clk0 clk1 clk2 clk3 fast pll 1 fast pll 2
7?76 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking clock output connections enhanced plls have outputs for eigh t regional clock outputs and four global clock outputs. there is line sharing between clock pins, global and regional clock networks and all pll outputs. see tables 7?18 through 7?23 and figures 7?47 through 7?53 to validate your clocking scheme. the quartus ii software automatically maps to regional and global clocks to avoid any restrictions . enhanced plls 5, 6, 11, and 12 drive out to single-ended pins as shown in table 7?23 . you can connect each fast pl l 1, 2, 3, or 4 output ( c0 , c1 , c2 , and c3 ) to either a global or a regional clock. there is line sharing between clock pins, fpllclk pins, global and regional clock networks, and all pll outputs. the quartus ii software will automatically map to regional and global clocks to avoid any restrictions. figure 7?47 shows the clock input and ou tput connections from the enhanced plls. 1 ep2s15, ep2s30, and ep2sgx30 devices have only two enhanced plls (5, 6), but the co nnectivity from these two plls to the global or regional cloc k networks remains the same. the ep2s60 device in the 1,020- pin package contains 12 plls. ep2s60 devices in the 484-pin and 672-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. ep2s90 devices in the 1020-pin and 1508-pin packages contain 12 plls. ep2s90 devices in th e 484-pin and 780-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. ep2s130 devices in the 1020-pin and 1508-pin packages contain 12 plls. the ep2s130 device in the 780-pin package contains fast plls 1?4 and enha nced plls 5 and 6.
altera corporation 7?77 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?47. stratix ii and stratix ii gx top and bottom enhanced plls, clock pin and logic array signal connectivity to global and regional clock networks notes (1) and (2) note to figure 7?47 : (1) the redundant connection dots facilitate stitching of the clock networks to support the ability to drive two quadrants with the same clock. (2) the enhanced plls can also be driven through the global or regional clock networks. the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pl l or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. g15 g14 g13 g12 rclk31 rclk30 rclk29 rclk28 rclk27 rclk26 rclk25 rclk24 g7 g6 g5 g4 rclk15 rclk14 rclk13 rclk12 rclk11 rclk10 rclk9 rclk8 pll 6 clk7 clk6 clk5 clk4 pll 12 pll 5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 clk14 clk15 clk13 clk12 pll 11 pll11_fb pll5_out[2..0]p pll5_out[2..0]n pll11_out[2..0]p pll11_out[2..0]n pll12_out[2..0]p pll12_out[2..0]n pll6_out[2..0]p pll6_out[2..0]n pll5_fb pll12_fb pll6_fb global clocks regional clocks regional clocks
7?78 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking tables 7?23 and 7?24 show the global and regional clocks that the pll outputs drive. table 7?23. stratix ii global and regional cl ock outputs from plls (part 1 of 3) clock network pll number and type ep2s15 through ep2s30 devices ep2s60 through ep2s180 devices fast plls enhanced plls fast plls enhanced plls 123456789101112 gclk0 v v v v gclk1 v v v v gclk2 v v v v gclk3 v v v v gclk4 v v gclk5 vv gclk6 v v gclk7 v v gclk8 v v v v gclk9 vv vv gclk10 v v v v gclk11 v v v v gclk12 v v gclk13 vv gclk14 vv gclk15 vv rclk0 v v v rclk1 v v v rclk2 v v v rclk3 v v v rclk4 v v v rclk5 v v v rclk6 v v v rclk7 v v v rclk8 v v rclk9 v v
altera corporation 7?79 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices rclk10 v v rclk11 v v rclk12 v v rclk13 v v rclk14 v v rclk15 vv rclk16 vv v rclk17 v v v rclk18 v v v rclk19 v v v rclk20 v v v rclk21 vv v rclk22 v v v rclk23 v v v rclk24 v v rclk25 v v rclk26 v v rclk27 v v rclk28 v v rclk29 vv rclk30 v v rclk31 v v external clock output pll5_out[3..0]p/ n v pll6_out[3..0]p/ n v table 7?23. stratix ii global and regional cl ock outputs from plls (part 2 of 3) clock network pll number and type ep2s15 through ep2s30 devices ep2s60 through ep2s180 devices fast plls enhanced plls fast plls enhanced plls 123456789101112
7?80 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking pll11_out[3..0]p /n v pll12_out[3..0]p /n v table 7?24. stratix ii gx global and regional clock output s from plls (part 1 of 3) clock network pll number and type ep2sgx30 devices ep2sgx60 through ep2sgx130 devices notes (2) , (3) , and (4) fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12 gclk0 v v v v gclk1 v v v v gclk2 v v v v gclk3 v v v v gclk4 v v gclk5 vv gclk6 v v gclk7 v v gclk8 gclk9 gclk10 gclk11 gclk12 v v gclk13 vv gclk14 vv gclk15 vv table 7?23. stratix ii global and regional cl ock outputs from plls (part 3 of 3) clock network pll number and type ep2s15 through ep2s30 devices ep2s60 through ep2s180 devices fast plls enhanced plls fast plls enhanced plls 123456789101112
altera corporation 7?81 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices rclk0 v v v rclk1 v v v rclk2 v v v rclk3 v v v rclk4 v v v rclk5 v v v rclk6 v v v rclk7 v v v rclk8 v v rclk9 v v rclk10 v v rclk11 v v rclk12 v v rclk13 v v rclk14 v v rclk15 vv rclk16 rclk17 rclk18 rclk19 rclk20 rclk21 rclk22 rclk23 rclk24 v v rclk25 v v rclk26 v v rclk27 v v table 7?24. stratix ii gx global and regional clock output s from plls (part 2 of 3) clock network pll number and type ep2sgx30 devices ep2sgx60 through ep2sgx130 devices notes (2) , (3) , and (4) fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12
7?82 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking the fast plls also drive high-speed serdes clocks for differential i/o interfacing. for information on these fpllclk pins, contact altera applications. rclk28 v v rclk29 vv rclk30 v v rclk31 v v external clock output pll5_out[3..0]p /n v pll6_out[3..0]p /n v pll11_out[3..0] p/n v pll12_out[3..0] p/n v note to table 7?24 : (1) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. (2) the ep2s60 device in the 1,020-pin package contains 12 plls. ep2s60 devices in the 484-pin and 672-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (3) ep2s90 devices in the 1020-pin and 1508-pin packages cont ain 12 plls. ep2s90 devices in the 484-pin and 780-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (4) ep2s130 devices in the 1020-pin and 1508-pin packages contain 12 plls. the ep2s130 device in the 780-pin package contains fast plls 1?4 and enhanced plls 5 and 6. table 7?24. stratix ii gx global and regional clock output s from plls (part 3 of 3) clock network pll number and type ep2sgx30 devices ep2sgx60 through ep2sgx130 devices notes (2) , (3) , and (4) fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12
altera corporation 7?83 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figures 7?48 through 7?51 show the global and re gional clock input and output connections from the stratix ii fast plls. figure 7?48. stratix ii cent er fast plls, clock pin and logic array signal connectivity to global and regional clock networks notes (1) and (2) note to figure 7?48 : (1) the redundant connection do ts facilitate stitching of the clock networks to support the ability to drive two qua drants with the same clock. (2) the global or regional clocks in a fast pll's quadrant can drive the fast pll input. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 1 rck0 rck2 rck1 rck3 gck0 gck2 gck9 gck11 gck1 gck3 gck8 gck10 rck4 rck6 rck5 rck7 rck17 rck16 rck18 rck19 rck21 rck23 rck20 rck22 c0 c1 c2 c3 fast pll 2 logic array signal input to clock network clk0 clk1 clk2 clk3 c0 c1 c2 c3 fast pll 4 c0 c1 c2 c3 fast pll 3 clk11 clk10 clk9 clk8
7?84 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking figure 7?49. stratix ii gx center fas t plls, clock pin and logic array si gnal connectivity to global and regional clock networks notes (1) and (2) note to figure 7?49 : (1) the redundant connection dots facilitate stitching of the clock networks to support the ability to drive two quadrants with the same clock. (2) the global or regional clocks in a fast pll's quadrant can drive the fast pll input. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pl l or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 1 rck0 rck2 rck1 rck3 gck0 gck2 gck1 gck3 rck4 rck6 rck5 rck7 c0 c1 c2 c3 fast pll 2 logic array signal inpu t to clock network clk0 clk1 clk2 clk3
altera corporation 7?85 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 7?50. stratix ii corner fast p lls, clock pin and logic array signal connectivity to global and regional clock networks note (1) note to figure 7?50 : (1) the corner fplls can also be driven throu gh the global or regional clock networks. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 7 rck0 rck2 rck1 rck3 gck0 gck2 gck9 gck11 gck1 gck3 gck8 gck10 rck4 rck6 rck5 rck7 rck17 rck16 rck18 rck19 rck21 rck23 rck20 rck22 c0 c1 c2 c3 fast pll 8 c0 c1 c2 c3 fast pll 10 c0 c1 c2 c3 fast pll 9 fpll7clk fpll 8clk fpll10cl k fpll 9cl k
7?86 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock control block figure 7?51. stratix ii gx co rner fast plls, clock pin and logic array signal connectivity to global and regional clock networks note (1) note to figure 7?51 : (1) the corner fplls can also be driven throu gh the global or regional clock networks. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. clock control block each global and regional clock ha s its own clock control block. the control block has two functions: clock source selection (dynamic selection for global clocks) clock power-down (dynamic clock enable or disable) c0 c1 c2 c3 fast pll 7 rck0 rck2 rck1 rck3 gck0 gck2 gck1 gck3 rck4 rck6 rck5 rck7 c0 c1 c2 c3 fast pll 8 fpll 7clk fpll 8clk
altera corporation 7?87 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices figures 7?52 and 7?53 show the global clock an d regional clock select blocks, respectively. figure 7?52. stratix ii global clock control block notes to figure 7?52 : (1) these clock select signals can only be dynamically controlled through internal logic when the device is operating in user mode. (2) these clock select signals can only be set through a configuration file and cannot be dynamically controlled during user-mode operation. clkp pins pll counter outputs internal logic static cloc k select (2) clkselect[1..0] this multiplexer supports user-controllable dynamic switching (1) 2 2 2 clkn pin enable/ disable gclk internal logic
7?88 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock control block figure 7?53. regional clock control block notes to figure 7?53 : (1) these clock select signals can only be dynamically controlled through a configuration file and ca nnot be dynamically controlled during user-mode operation. (2) only the clk n pins on the top and bottom for th e device feed to regional clock select blocks. for the global clock select block, the clock source selection can be controlled either statically or dyna mically. you have the option to statically select the clock source in configuration file generated by the quartus ii software, or you can cont rol the selection dynamically by using internal logic to drive the multiplexer select inputs. when selecting statically, the clock source can be set to any of the inputs to the select multiplexer. when selecting the clock source dynamically, you can either select two pll outputs (such as clk0 or clk1 ), or a combination of clock pins or pll outputs. when using the altclkctrl megafunction to implement clock source (dynamics) selection, the inputs from the clock pins feed the inclock[0..1] ports of the multiplexer, while the pll outputs feed the inclock[2..3] ports. you can choose from among these inputs using the clkselect[1..0] signal. for the regional clock select block, the clock source selection can only be controlled statically using configuration bits. any of the inputs to the clock select multiplexer can be set as the clock source. the stratix ii and stratix ii gx clock networks can be disabled (powered down) by both static and dynamic approaches. when a clock net is powered down, all the logic fed by the clock net is in an off-state, thereby reducing the overall power consumption of the device. clkp pin pll counter outputs internal logic clkn pin enable/ disable rclk internal logic static clock select (1 ) 2 (2) (3)
altera corporation 7?89 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices the global and regional clock networks that are not used are automatically powered down through configuration bit settings in the configuration file (sram object file ( .sof ) or programmer object file ( .pof )) generated by the quartus ii software. the dynamic clock enable or disable feature allows the internal logic to control power up or down synchronously on gclk and rclk nets, including dual-regional clock regions. this function is independent of the pll and is applied directly on the clock network, as shown in figure 7?52 on page 7?87 and figure 7?53 on page 7?88 . the input clock sources and the clkena signals for the global and regional clock network multiplexers can be set through the quartus ii software using the altclkctrl megafunction. the dedicated external clock output pins can also be enabled or disabled using the altclkctrl megafunction. figure 7?54 shows the external pll output clock control block. figure 7?54. stratix ii ex ternal pll output clock control block notes to figure 7?54 : (1) these clock select signals can only be set through a configuration file and cannot be dynamically controlled during user mode operation. (2) the clock control block feed s to a multiplexer within the pll_out pin?s ioe. the pll_out pin is a dual-purpose pin. therefore, this multiplexer selects either an internal signal or the output of the clock control block. pll counter outputs (c[5..0]) enable/ disable pll_out pin internal logic static clock select ioe (1 ) static clock select (1) 6 internal logic (2)
7?90 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock control block clkena signals figure 7?55 shows how clkena is implemented. figure 7?55. clkena implementation in stratix ii devices, the clkena signals are supported at the clock network level. this allows you to gate off the clock even when a pll is not being used. the clkena signals can also be used to control the dedicated external clocks from enhanced plls. upon re -enabling, the pll does not need a resynchronization or relo ck period unless the pll is using external feedback mode. figure 7?56 shows the waveform example for a clock output enable. clkena is synchronous to the falling edge of the counter output. figure 7?56. clkena signals note to figure 7?56 (1) the clkena signals can be used to enable or disable the global and regional networks or the pll_out pins. dq clkena clkena_out clk_out clk counter output clkena clkout
altera corporation 7?91 october 2007 stratix ii gx device handbook, volume 2 plls in stratix ii and stratix ii gx devices the pll can remain locked independent of the clkena signals since the loop-related counters are not affe cted. this feature is useful for applications that require a low power or sleep mode. upon re-enabling, the pll does not need a resynchr onization or relock period. the clkena signal can also disable clock output s if the system is not tolerant to frequency overshoot during resynchronization. conclusion stratix ii and stratix ii gx device enhanced and fast plls provide you with complete control of device cloc ks and system timing. these plls are capable of offering flexible system -level clock mana gement that was previously only available in discrete pll devices. the embedded plls meet and exceed the features offered by these high-end discrete devices, reducing the need for other ti ming devices in the system. referenced documents this chapter references the following documents: altpll megafunction user guide an 367: implementing pll reconf iguration in stratix ii devices configuring stratix ii an d stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook) dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook (or the stratix ii device handbook ) selectable i/o standards in stratix ii and stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook ) verification , volume 3 of the quartus ii development software handbook document revision history table 7?25 shows the revision history for this chapter. table 7?25. document revision history (part 1 of 2) date and document version changes made summary of changes october 2007, v4.5 updated ?external clock outputs? section. ? added the ?referenced documents? section. ? minor text edis. ?
7?92 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history no change for the stratix ii gx device handbook only: formerly chapter 6. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 updated table 7?6. ? updated notes to: figure 7?7 figure 7?47 figure 7?48 figure 7?49 figure 7?50 figure 7?51 ? updated the ?clock source control for enhanced plls? section. ? updated the ?clock source control for fast plls? section. ? february 2007 v4.3 added ?document revision histor y? section to this chap- ter. ? deleted paragraph beginning with ?the stratix ii gx plls have the ability...? in the ?enhanced lock detect circuit? section. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 5. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook .? table 7?25. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation section iii?1 preliminary section iii. memory this section provides information on the trimatrix? embedded memory blocks internal to stratix ? ii gx devices and the supported external memory interfaces. this section contains the following chapters: chapter 8, trimatrix embedded me mory blocks in stratix ii and stratix ii gx devices chapter 9, external memory interfac es in stratix ii and stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section iii?2 altera corporation preliminary memory stratix ii gx device handbook, volume 2
altera corporation 8?1 october 2007 8. trimatrix embedded memory blocks in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx devices feature the trimatrix? memory structure, consisting of three si zes of embedded ram blocks that efficiently address the memory needs of fpga designs. trimatrix memory includes 512-bit m 512 blocks, 4-kbit m4k blocks, and 512-kbit m-ram blocks, which are each configurable to support many features. trimatrix memory provides up to 9 megabits of ram at up to 550 mhz operation, and up to 16 tera bits per second of total memory bandwidth per device. this chapter describes trimatrix memory blocks, modes, and features. trimatrix memory overview the trimatrix architecture provid es complex memory functions for different applications in fpga desi gns. for example, m512 blocks are used for first-in first-out (fifo) functions and clock domain buffering where memory bandwidth is critical; m4k blocks are ideal for applications requiring medium-sized memory, such as asynchronous transfer mode (atm) cell processing ; and m-ram blocks are suitable for large buffering applications, such as internet protocol (ip) packet buffering and system cache. the trimatrix memory blocks support various memory configurations, including single-port, simple dual-p ort, true dual-port (also known as bidirectional dual-port), shift register, and read-only memory (rom) modes. the trimatrix memory archit ecture also includes advanced features and capabilities, such as pa rity-bit support, byte enable support, pack mode support, address clock en able support, mixed port width support, and mixed clock mode support. when applied to input registers, the asynchronous clear signal for the trimatrix embedded memory immediately clears the input registers. however, the output of the memory block does not show the effects until the next clock edge. when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. sii52002-4.5
8?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 trimatrix memory overview table 8?1 summarizes the features supported by the three sizes of trimatrix memory. table 8?1. summary of trimatrix memory features feature m512 blocks m4k blocks m-ram blocks maximum performance 500 mhz 550 mhz 420 mhz total ram bits (including parity bits) 576 4,608 589,824 configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 8k 64 8k 72 4k 128 4k 144 parity bits vvv byte enable vvv pack mode vv address clock enable vv single-port memory vvv simple dual-port memory vvv true dual-port memory vv embedded shift register vv rom vv fifo buffer vvv simple dual-port mixed width support vvv true dual-port mixed width support vv memory initialization file (. mif ) vv mixed-clock mode vvv power-up condition outputs cleared outputs cleared outputs unknown register clears output registers only output registers only output registers only same-port read-during-write new data available at positive clock edge new data available at positive clock edge new data available at positive clock edge mixed-port read-during-write outputs set to unknown or old data outputs set to unknown or old data unknown output
altera corporation 8?3 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices tables 8?2 and 8?3 show the capacity and dis tribution of the trimatrix memory blocks in each stratix ii and stratix ii gx family member, respectively. parity bit support all trimatrix memory blocks (m51 2, m4k, and m-ram) support one parity bit for each byte. parity bits add to the amount of me mory in each random access memory (ram) block. for example, the m512 block has 576 bits, 64 of which are optionally used for parity bit storag e. the parity bit, along with logic implemented in adaptive logic modules (alms), implements parity checking for error detection to ensure data integrity. parity-size data words can also be used for other purp oses such as storing user-specified control bits. table 8?2. trimatrix memory capacity a nd distribution in stratix ii devices device m512 columns/blocks m4k columns/blocks m-ram blocks total ram bits ep2s15 4/104 3/78 0 419,328 ep2s30 6/202 4/144 1 1,369,728 ep2s60 7/329 5/255 2 2,544,192 ep2s90 8/488 6/408 4 4,520,448 ep2s130 9/699 7/609 6 6,747,840 ep2s180 11/930 8/768 9 9,383,040 table 8?3. trimatrix memory capacity and distribution in stratix ii gx devices device m512 columns/blocks m4k columns/blocks m-ram blocks total ram bits ep2sgx30c ep2sgx30d 6/202 4/144 1 1,369,728 ep2sgx60c ep2sgx60d ep2sgx60e 7/329 5/255 2 2,544,192 ep2sgx90e ep2sgx90f 8/488 6/408 4 4,520,448 ep2sgx130g 9/699 7/609 6 6,747,840
8?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 trimatrix memory overview f refer to the using parity to detect memory errors white paper for more information on using the parity bit to detect memory errors. byte enable support all trimatrix memory blocks support byte enables that mask the input data so that only specific bytes, nibbl es, or bits of data are written. the unwritten bytes or bits retain the prev ious written value. the write enable ( wren ) signals, along with the byte enable ( byteena ) signals, control the ram blocks? write operations. the de fault value for the byte enable signals is high (enabled), in which case writing is controlled only by the write enable signals. there is no clear port to the byte enable registers. m512 blocks m512 blocks support byte enables for data widths of 16 and 18 bits only. for memory block configurations with widths of less than two bytes (16/18), the byte-enable feature is not supported. for memory configurations less than two bytes wi de, the write enable or clock enable signals can optionally be used to control the write operation. table 8?4 summarizes the byte selection. m4k blocks m4k blocks support byte enables for any combination of data widths of 16, 18, 32, and 36 bits only. for memory block configurations with widths of less than two bytes (16/18), the byte-enable feature is not supported. for memory configurations less than two bytes wide, the write enable or clock enable signals can optionally be used to control the write operation. table 8?4. byte enable for stratix ii and stratix ii gx m512 blocks note (1) byteena[1..0] data 16 data 18 [0] = 1 [7..0] [8..0] [1] = 1 [15..8] [17..9] note to ta b l e 8 ? 4 : (1) any combination of byte enables is possible.
altera corporation 8?5 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices table 8?5 summarizes the byte selection. m-ram blocks m-ram blocks support byte enables fo r any combination of data widths of 16, 18, 32, 36, 64, and 72 bits. fo r memory block configurations with widths of less than two bytes (16/ 18), the byte-enable feature is not supported. in the 128 and 144 simple dual-port modes, the two sets of byte enable signals ( byteena_a and byteena_b ) combine to form the necessary 16 byte enables. in 128 an d 144 modes, byte enables are only supported when using single clock mode. however, the quartus ii software can implement byte enables in other clocking modes for 128 or 144 widths but will use twice as many m-ram resources. if clock enables are used in 128 or 144 mode, you must use the same clock enable setting for both the a and b ports. table 8?6 summarizes the byte selection for m-ram blocks. table 8?5. byte enable for stratix ii and stratix ii gx m4k blocks note (1) byteena [3..0] data 16 data 18 data 32 data 36 [0] = 1 [7..0] [8..0] [7..0] [8..0] [1] = 1 [15..8] [17..9] [15..8] [17..9] [2] = 1 - - [23..16] [26..18] [3] = 1 - - [31..24] [35..27] note to ta b l e 8 ? 5 : (1) any combination of byte enables is possible. table 8?6. byte enable for stratix ii and stratix ii gx m-ram blocks note (1) byteena data 16 data 18 data 32 data 36 data 64 data 72 [0] = 1 [7..0] [8..0] [7..0] [8..0] [7..0] [8..0] [1] = 1 [15..8] [17..9] [15..8] [17..9] [15..8] [17..9] [2] = 1 - - [23..16] [26..18] [23..16] [26..18] [3] = 1 - - [31..24] [35..27] [31..24] [35..27] [4] = 1 - - - - [39..32] [44..36] [5] = 1 - - - - [47..40] [53..45] [6] = 1 - - - - [55..48] [62..54] [7] = 1 - - - - [63..56] [71..63] note to ta b l e 8 ? 6 : (1) any combination of byte enables is possible.
8?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 trimatrix memory overview table 8?7 summarizes the byte selection for 144 mode. byte enable functional waveform figure 8?1 shows how the write enable ( wren ) and byte enable ( byteena ) signals control the operations of the ram. when a byte enable bit is de-asserted during a write cycle, the corresponding data byte output appe ars as a ?don't care? or unknown value. when a byte enable bit is asserted during a write cycle, the corresponding data byte output will be the newly written data. table 8?7. stratix ii and stratix ii gx m- ram combined byte selection for 144 mode note (1) byteena data 128 data 144 [0] = 1 [7..0] [8..0] [1] = 1 [15..8] [17..9] [2] = 1 [23..16] [26..18] [3] = 1 [31..24] [35..27] [4] = 1 [39..32] [44..36] [5] = 1 [47..40] [53..45] [6] = 1 [55..48] [62..54] [7] = 1 [63..56] [71..63] [8] = 1 [71..64] [80..72] [9] = 1 [79..72] [89..73] [10] = 1 [87..80] [98..90] [11] = 1 [95..88] [107..99] [12] = 1 [103..96] [116..108] [13] = 1 [111..104] [125..117] [14] = 1 [119..112] [134..126] [15] = 1 [127..120] [143..135] note to ta b l e 8 ? 7 : (1) any combination of byte enables is possible.
altera corporation 8?7 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?1. stratix ii and st ratix ii gx byte enable functional waveform 1 for more information about mram and byte enable for the stratix ii device family, refer to the stratix ii fpga errata sheet at the altera web site at www.altera.com . pack mode support stratix ii and stratix ii gx m4k and m-ram memory blocks support pack mode. in m4k and m-ram me mory blocks, two single-port memory blocks can be implemented in a single block under the following conditions: each of the two independent block si zes is equal to or less than half of the m4k or m-ram block size. each of the single-port memory blocks is configured in single-clock mode. thus, each of the single-port memory blocks access up to half of the m4k or m-ram memory resources such as clock, clock enables, and asynchronous clear signals. refer to ?single-port mode? on page 8?10 and ?single-clock mode? on page 8?28 for more information. inclock wren address data q (asynch) byteena xxxx abcd xxxx xx 10 01 11 xx an a0 a1 a2 a0 a1 a2 abcd ffff ffff abff ffff ffcd contents at a0 contents at a1 contents at a2 doutn abxx xxcd abcd abff ffcd abcd
8?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 trimatrix memory overview address clock enable support stratix ii and stratix ii gx m4k and m-ram memory blocks support address clock enable, which is used to hold the previous address value for as long as the signal is enabled. when the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. figure 8?2 shows an address clock enable block diagram. placed in the address register, the address signal ou tput by the address register is fed back to the input of the register via a multiplexer. the multiplexer output is selected by the address clock enable ( addressstall ) signal. address latching is enabled when the addressstall signal turns high. the output of the address register is th en continuously fed into the input of the register; therefore, the address value can be held until the addressstall signal turns low. figure 8?2. stratix ii and st ratix ii gx address clock enable block diagram address clock enable is typically used for cache memory applications, which require one port for read and another port for write. the default value for the address clock enable signals is low (disabled). figures 8?3 and 8?4 show the address clock enable waveform during the read and write cycles, respectively. address[0] address[n] addressstall clock 1 0 address[0] register address[n] register address[n] address[0] 1 0
altera corporation 8?9 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?3. stratix ii and stratix ii gx address clock enable during read cycle waveform figure 8?4. stratix ii and st ratix ii gx address clock enable during write cycle waveform memory modes stratix ii and stratix ii gx trimatrix memory blocks include input registers that synchronize writes, and output registers to pipeline data to improve system performance. all tr imatrix memory blocks are fully synchronous, meaning that all inputs are registered, but outputs can be either registered or unregistered. inclock rden rdaddress q (synch) a0 a1 a2 a3 a4 a5 a6 q (asynch) an a0 a4 a5 latched address (inside memory) dout0 dout1 dout1 dout4 dout1 dout4 dout5 addressstall a1 doutn-1 dout1 doutn doutn dout1 dout0 dout1 inclock wren wraddress a0 a1 a2 a3 a4 a5 a6 an a0 a4 a5 latched address (inside memory) addressstall a1 data 00 01 02 03 04 05 06 contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 xx 04 xx 00 03 01 xx 02 xx xx xx 05
8?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 memory modes 1 trimatrix memory does not support asynchronous memory (unregistered inputs). depending on which trimatrix memory block you use, the memory has various modes, including: single-port simple dual-port true dual-port (bidirectional dual-port) shift-register rom fifo 1 violating the setup or hold time on the memory block address registers could corrupt memory contents. this applies to both read and write operations. single-port mode all trimatrix memory blocks support the single-port mode that supports non-simultaneous read and write operations. figure 8?5 shows the single-port memory configur ation for trimatrix memory. figure 8?5. single-port memory note (1) note to figure 8?5 : (1) two single-port memory blocks can be implemented in a si ngle m4k or m-ram block. m4k and m-ram memory blocks can al so be halved and used for two independent single-port ram blocks. the altera ? quartus ? ii software automatically uses this single-port memory pa cking when running low on memory resources. to force two single-port memories into one m4k or m-ram block, first ensure that each of the two independent ram blocks is equal to or less than half the size of the m4k or m-ram block. secondly, assign both single-port rams to the same m4k or m-ram block. data[ ] address[ ] wren byteena[] addressstall inclock inclocken outaclr outclocken outclock q[]
altera corporation 8?11 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices in single-port ram configuration, the outputs can only be in read-during-write mode, which means that during the write operation, data written to the ram flows thro ugh to the ram outputs. when the output registers are bypassed, the new da ta is available on the rising edge of the same clock cycle on wh ich it was written. refer to ?read-during- write operation at the same address? on page 8?33 for more information about read-during-write mode. table 8?8 shows the port width configurations for trimatrix blocks in single-port mode. figure 8?6 shows timing waveforms for read and write operations in single-port mode. figure 8?6. stratix ii and st ratix ii gx single-port timing waveforms note to figure 8?6 : (1) the crosses in the data waveform during read mean ?don?t care.? table 8?8. stratix ii and stratix ii gx po rt width configur ations for m512, m4k, and m-ram blocks (single-port mode) m512 blocks m4k blocks m-ram blocks port width configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 inclock wren address q (synch) an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) din-1 din din4 din5 din6 data din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5 (1)
8?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 memory modes simple dual-port mode all trimatrix memory blocks support simple dual-port mode which supports a simultaneous read and write operation. figure 8?7 shows the simple dual-port memory configuration for trimatrix memory. figure 8?7. stratix ii and stratix ii gx simple dual-port memory note (1) note to figure 8?7 : (1) simple dual-port ram supports input/output clock mode in addition to the read/write clock mode shown. data[ ] wraddress[ ] wren byteena[] wr_addressstall wrclock wrclocken rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken rd_aclr
altera corporation 8?13 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices trimatrix memory supports mixed-width configurations, allowing different read and write port widths. tables 8?9 through 8?11 show the mixed width configurations for th e m512, m4k, and m-ram blocks, respectively. table 8?9. stratix ii and stratix ii gx m512 block mixed-width configurations (sim ple dual-port mode) read port write port 512 1 256 2 128 4 64 8 32 16 64 9 32 18 512 1 vvvvv 256 2 vvvvv 128 4 vvvvv 64 8 vvvvv 32 16 vvvvv 64 9 vv 32 18 vv table 8?10. stratix ii and stra tix ii gx m4k block mi xed-width configurations (simple dual-port mode) read port write port 4k 1 2k 2 1k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvvvvv 2k 2 vvvvvv 1k 4 vvvvvv 512 8 vvvvvv 256 16 vvvvvv 128 32 vvvvvv 512 9 vvv 256 18 vvv 128 36 vvv
8?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 memory modes in simple dual-port mode, m512 and m4k blocks have one write enable and one read enable signal. howeve r, m-ram blocks contain only a write-enable signal, which is held high to perform a write operation. m-ram blocks are always enabled for read operations. if the read address and the write address select the same address location during a write operation, m-ram bl ock output is unknown. trimatrix memory blocks do not support a clear port on the write enable and read enable registers. when th e read enable is deactivated, the current data is retained at the output ports. if the read enable is activated during a write operation with the sa me address location selected, the simple dual-port ram output is either unknown or can be set to output the old data stored at the memory address. refer to ?read-during-write operation at the same address? on page 8?33 for more information. figure 8?8 shows timing waveforms for read and write operations in simple dual-port mode. table 8?11. stratix ii and stratix ii gx m-ra m block mixed-width configurations (sim ple dual-port mode) read port write port 64k 9 32k 18 18k 36 8k 72 4k 144 64k 9 vvv v 32k 18 vvv v 18k 36 vvv v 8k 72 vvv v 4k 144 v
altera corporation 8?15 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?8. stratix ii and stra tix ii gx simple dual -port timing waveforms notes to figure 8?8 : (1) the crosses in the data waveform during read mean ?don?t care.? (2) the read enable rden signal is not available in m-ram blocks. the m-ram block in simple dual-port mode always reads out the data stored at the current read address location. true dual-port mode stratix ii and stratix ii gx m4k and m-ram memory blocks support the true dual-port mode. true dual-port mode supports any combination of two-port operations: two reads, two wr ites, or one read and one write at two different clock frequencies. figure 8?9 shows stratix ii and stratix ii gx true dual-port memory configuration. figure 8?9. stratix ii and stratix ii gx true dual-port memory note (1) note to figure 8?9 : (1) true dual-port memory supports input/output clock mode in addition to the independent clock mode shown. wrclock wren wraddress q (synch) rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden (2) rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 din-1 din din4 din5 din6 data (1) data_a[ ] address_a[ ] wren_a byteena_a[] addressstall_a clock_a enable_a aclr_a q_a[] data_b[ ] address_b[] wren_b byteena_b[] addressstall_b clock_b enable_b aclr_b q_b[]
8?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 memory modes the widest bit configuration of the m4k and m-ram blocks in true dual- port mode is as follows: 256 16-bit (18-bit wi th parity) (m4k) 8k 64-bit (72-bit wi th parity) (m-ram) the 128 32-bit (36-bit with parity) configuration of the m4k block and the 4k 128-bit (144-bit with parity) configuration of the m-ram block are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. because true dual-port ram has outputs on two port s, the maximum width of the true dual-port ram equals half of the total number of output drivers. table 8?12 lists the possible m4k block mixed-port width configurations. table 8?13 lists the possible m-ram block mixed-port width configurations. table 8?12. stratix ii and stra tix ii gx m4k block mixed-port wi dth configurations (true dual-port) read port write port 4k 1 2k 2 1k 4 512 8 256 16 512 9 256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv table 8?13. stratix ii and st ratix ii gx m-ram bl ock mixed-port width configurations (true dual-port) read port write port 64k 9 32k 18 18k 36 8k 72 64k 9 v vvv 32k 18 v vvv 18k 36 v vvv 8k 72 v vvv
altera corporation 8?17 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices in true dual-port configuration, the ram outputs can only be configured for read-during-write mode. this means that during write operation, data being written to the a or b port of the ram flows through to the a or b outputs, respectively. when th e output registers are bypassed, the new data is available on the rising ed ge of the same clock cycle on which it was written. refer to ?read-during-write operation at the same address? on page 8?33 for waveforms and information on mixed-port read-during-write mode. potential write contentions must be resolved external to the ram because writing to the same address location at both ports results in unknown data storage at that location. for a valid write operation to the same address of the m-ram block, the rising edge of the write clock for port a must occur following the maximum writ e cycle time interval after the rising edge of the write clock for port b. data is written on the rising edge of the write clock for the m-ram block. because data is written into the m512 and m4k blocks at the falling edge of the write clock, the rising edge of the write clock for port a should occur following half of the maximum write cycle time interval after the falling edge of the write clock for port b. if this timing is not met, the data stored in that particular address will be invalid. f refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for the maximum synchronous write cycle time.
8?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 memory modes figure 8?10 shows true dual-port timi ng waveforms for the write operation at port a and the read operation at port b. figure 8?10. stratix ii and stratix ii gx true dual-port timing waveforms note to figure 8?10 : (1) the crosses in the data_a waveform during write mean ?don?t care.? shift-register mode all stratix ii memory blocks su pport the shift register mode. embedded memory block configurations can implement shift registers for digital signal processing (dsp) applications, such as finite impulse response (fir) filters, pseudo-ran dom number generators, multi-channel filtering, and auto-correlation and cr oss-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flip-flops that quickly exhaust many logic cells for large shift registers. a more efficient alternative is to use embedded memory as a shift-register block, which saves logic cell and routing resources. the size of a (w m n) shift regist er is determined by the input data width (w), the length of the taps (m ), and the number of taps (n), and must be less than or equal to the maxi mum number of memory bits in the respective block: 576 bits for the m512 block, 4,608 bits for the m4k block, and 589,824 bits for the mram block. in addition, the size of w n must be less than or equal to the maximu m width of the respective block: 18 clk_a wren_a address_a q_a (synch) q_b (synch) clk_b an-1 an a0 a1 a2 a3 a4 a5 a6 q_b (asynch) wren_b address_b bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 q_a (asynch) din-1 din din4 din5 din6 data_a (1) din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5 dout1 dout2 dout1
altera corporation 8?19 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices bits for the m512 block, 36 bits for the m4k block, and 144 bits for the mram block. if a larger shift register is required, the memory blocks can be cascaded. in m512 and m4k blocks, data is writte n into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. the shift-register mode logic automatically controls the positive and negative edge clocking to shift the da ta in one clock cycle. the mram block performs reads an d writes on the rising edge. figure 8?11 shows the trimatrix memory block in the shift-register mode. figure 8?11. stratix ii and stratix ii gx shift-register memory configuration w w m n shift register m-bit shift register m-bit shift register m-bit shift register m-bit shift register w w w w w w w n number of tap s
8?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock modes rom mode m512 and m4k memory blocks support rom mode. a memory initialization file ( .mif ) initializes the rom conten ts of these blocks. the address lines of the rom are registered. the outputs can be registered or unregistered. the rom read operation is identical to the read operation in the single-port ram configuration. fifo buffers mode trimatrix memory blocks support th e fifo mode. m512 memory blocks are ideal for designs with many sh allow fifo buffers. all memory configurations have synchronous in puts; however, the fifo buffer outputs are always combinational. si multaneous read and write from an empty fifo buffer is not supported. f refer to the single- and dual-clock fifo megafunctions user guide and fifo partitioner megafunction user guide for more information on fifo buffers. clock modes depending on which trimatrix memory mode is selected, the following clock modes are available: independent input/output read/write single-clock table 8?14 shows these clock modes support ed by all trimatrix blocks when configured as respective memory modes. table 8?14. stratix ii and st ratix ii gx trimatri x memory clock modes clocking modes true dual-port mode simple dual-port mode single-port mode independent v input/output vvv read/write v single clock vvv
altera corporation 8?21 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices independent clock mode the trimatrix memory blocks can implement independent clock mode for true dual-port memory. in this mo de, a separate clock is available for each port (a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port also supports independent clock enables for port a and b registers. asynchronous clear signals for the registers, however, are supported.
8?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock modes figure 8?12 shows a trimatrix memory block in independent clock mode. figure 8?12. stratix ii and stra tix ii gx trimatrix me mory block in independent clock mode note (1) note to figure 8?12 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this appl ies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out enable_a clock_a d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b enable_b clock_b addressstall_a address clock enable a address clock addressstall_b enable b
altera corporation 8?23 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices input/output clock mode stratix ii and stratix ii gx trimatrix memory blocks can implement input/output clock mode for true and simple dual-port memory. on each of the two ports, a and b, one clock controls all registers for the following inputs into the memory bl ock: data input, write enable, and address. the other clock controls the blocks? data output registers. each memory block port also supports independent cl ock enables for input and output registers. asynchronous clear signals for the registers, however, are not supported. figures 8?13 through 8?15 show the memory block in input/output clock mode for true dual-port, simple dual-port, and single-port modes, respectively.
8?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock modes figure 8?13. stratix ii and stratix ii gx input/output clock mode in true dual-port mode note (1) note to figure 8?13 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this appl ies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out inclocken inclock d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b outclocken outclock addressstall_a address clock enable a address clock addressstall_b enable b
altera corporation 8?25 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?14. stratix ii and stratix ii gx input/o utput clock mode in simple dual-port mode note (1) notes to figure 8?14 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) the read enable rden signal is not available in the m-ram block. an m-ram block in simple dual-port mode is always reading out the data stored at the current read address location. (3) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack? interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclocken inclocken inclock outclock wren rden 6 lab row clocks to multitrack interconnect (3 ) d ena q byteena[ ] byte enable write pulse generator (2) rd_addressstall wr_addressstall read address clock enable write address clock enable
8?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock modes figure 8?15. stratix ii and stratix ii gx inpu t/output clock mode in single-port mode note (1) notes to figure 8?15 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. read/write clock mode stratix ii and stratix ii gx trimatri x memory blocks can implement read/write clock mode for simple dual-port memory. this mode uses up to two clocks. the write clock controls the bloc ks? data inputs, write address, and write enable signals. the read clock controls the data output, read address, and read enable si gnals. the memory blocks support independent clock enables for each clock for the read- and write-side registers. asynchronous clear signals for the registers, however, are not supported. figure 8?16 shows a memory block in read/write clock mode. 6 d ena q d ena q d ena q d ena q data[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out outclocken inclocken inclock outclock wren 6 lab row clocks to multitrack interconnect (2 ) d ena q byteena[ ] byte enable write pulse generator addressstall address clock enable
altera corporation 8?27 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?16. stratix ii and strati x ii gx read/write clock mode note (1) notes to figure 8?16 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) the read enable rden signal is not available in the m-ram block. an m-ram block in simple dual-port mode is always reading the data stored at the current read address location. (3) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out rdclocken wrclocken wrclock rdclock wren rden 6 lab row clocks to multitrack interconnect (3 ) d ena q byteena[ ] byte enable write pulse generator (2) rd_addressstall wr_addressstall read address clock enable write address clock enable
8?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock modes single-clock mode stratix ii and stratix ii gx trimat rix memory blocks implement single-clock mode for true dual-port, simple dual-port, and single-port memory. in this mode, a single clock, together with clock enable, is used to control all registers of the memory block. asynchronous clear signals for the registers, however, are not supported. figures 8?17 through 8?19 show the memory block in single-clock mode for true dual-port, simple dual-port, and single-port modes, respectively.
altera corporation 8?29 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?17. stratix ii and stratix ii gx si ngle-clock mode in true dual-port mode note (1) note to figure 8?17 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this appl ies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out enable clock d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b a ddressstall_a address clock enable a address clock addressstall_b enable b
8?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 clock modes figure 8?18. stratix ii andstratix ii gx single-c lock mode in simple dual-port mode note (1) notes to figure 8?18 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) the read enable rden signal is not available in the m-ram block. an m-ram block in simple dual-port mode is always reading the data stored at the current read address location. (3) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out enable clock wren rden 6 lab row clocks to multitrack interconnect (3 ) d ena q byteena[ ] byte enable write pulse generator (2) rd_addressstall wr_addressstall read address clock enable write address clock enable
altera corporation 8?31 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?19. stratix ii and stratix ii gx si ngle-clock mode in single-port mode note (1) notes to figure 8?19 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. designing with trimatrix memory when instantiating trimatrix memory, it is important to understand the features that set it apart from othe r memory architectures. the following sections describe the unique attributes and functionality of trimatrix memory. selecting trimatri x memory blocks the quartus ii software automatically partitions user-defined memory into embedded memory blocks using the most efficient size combinations. the memory can also be manually assigned to a specific block size or a mixture of block sizes. table 8?1 on page 8?2 is a guide for selecting a trimatrix memory block size based on supported features. 6 d ena q d ena q d ena q d ena q data[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out enable clock wren 6 lab row clocks to multitrack interconnect (2 ) d ena q byteena[ ] byte enable write pulse generator addressstall address clock enable
8?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 designing with trimatrix memory f refer to an 207: trimatrix memory selection using the quartus ii software for more information on selectin g the appropriate memory block. synchronous and pseudo-asynchronous modes the trimatrix memory architecture implements sync hronous ram by registering the input and output sign als to the ram block. the inputs to all trimatrix memory blocks are registered providing synchronous write cycles, while the output registers can be bypassed. in a synchronous operation, ram generates its own self-timed strobe write enable signal derived from the global or regional clock. in contrast, a circuit using asynchronous ram must generate th e ram write enable signal while ensuring that its data and address signals meet setup and hold time specifications relative to the write enable signal. during a synchronous operation, the ram is used in pipelined mode (inputs and outputs registered) or flow-through mode (onl y inputs registered). however, in an asynchronous memory, neither the input nor the output is registered. while stratix ii and stratix ii gx devices do not support asynchronous memory, they do support a pseudo-a synchronous read where the output data is available during the clock cy cle when the read address is driven into it. pseudo-asynchronous reading is possible in the simple and true dual-port modes of the m512 and m4k bl ocks by clocking the read enable and read address registers on the ne gative clock edge and bypassing the output registers. f refer to an 210: converting memory from asynchronous to synchronous for stratix and stratix gx designs for more information. power-up conditions and memory initialization upon power up, trimatrix memory is in an idle state. the m512 and m4k block outputs always power-up to zero, regardless of whether the output registers are used or bypassed. even if an mif is used to pre-load the contents of the ram block, the outputs will still power-up as cleared. for example, if address 0 is pre-initialized to ff, the m512 and m4k blocks power up with the output at 00. m-ram blocks do not support mifs; ther efore, they cannot be pre-loaded with data upon power up. m-ram blocks asynchronous outputs and memory controls always power up to an unknown state. if m-ram block outputs are registered, the registers power up as cleared. when a read is performed immediately after power up, the output from the read operation will be undefined since th e m-ram contents are not initialized. the read operation will continue to be undefined for a given address until a write operation is performed for that address.
altera corporation 8?33 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices read-during- write operation at the same address the ?same-port read-during-write mode? on page 8?33 and ?mixed- port read-during-write mode? on page 8?34 sections describe the functionality of the various ram conf igurations when reading from an address during a write operation at that same address. there are two read-during-write data flows: same-port and mixed-port. figure 8?20 shows the difference between these flows. figure 8?20. stratix ii and stratix ii gx read-during-write data flow same-port read-during-write mode for read-during-write operation of a single-port ram or the same port of a true dual-port ram, the new data is available on the rising edge of the same clock cycle on which it was written. this behavior is valid on all memory block sizes. figure 8?21 shows a sample functional waveform. when using byte enables in true dual-port ram mode, the outputs for the masked bytes on the same port are unknown (refer to figure 8?1 on page 8?7 ). the non-masked bytes ar e read out as shown in figure 8?21 . port a data in port b data in port a data out port b data out mixed-port data flow same-port data flow
8?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 read-during-write operation at the same address figure 8?21. stratix ii and stratix ii g x same-port read-during-write functionality note (1) note to figure 8?21 : (1) outputs are not registered. mixed-port read-during-write mode this mode is used when a ram in simple or true dual-port mode has one port reading and the other port writin g to the same addr ess location with the same clock. the read_during_write_mode_mixed_ports parameter for m512 and m4k memory blocks determines wh ether to output the old data at the address or a ?don?t care? value. setting this parameter to old_data outputs the old data at that addr ess. setting this parameter to dont_care outputs a ?don?t care? or unknown value. figures 8?22 and 8?23 show sample functional waveforms where b oth ports have the same address. these figures assume that the outputs are not registered. the dont_care setting allows memory implementation in any trimatrix memory block, whereas the old_data setting restricts memory implementation to only m512 or m4k memory blocks. selecting dont_care gives the compiler more flex ibility when placing memory functions into trimatrix memory. the ram outputs are unknown for a mixed-port read-during-write operation of the same address location of an m-ram block, as shown in figure 8?23 . inclock data wren q a b a old
altera corporation 8?35 october 2007 stratix ii gx device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 8?22. stratix ii and stratix ii g x mixed-port read-during-write: old_data figure 8?23. stratix ii and stratix ii g x mixed-port read-during-write: dont_care mixed-port read-during-write is not supported when two different clocks are used in a dual-port ram. the output value is unknown during a mixed-port read-during-write operation. conclusion the trimatrix memory structure of stratix ii and stratix ii gx devices provides an enhanced ram architectu re with high memory bandwidth. it addresses the needs of different memory applications in fpga designs with features such as different me mory block sizes and modes, byte enables, parity bit storage, address clock enables, mixed clock mode, shift register mode, mixed-port width support, and true dual-port mode. inclock data_a wren_a q_b ab a old wren_b b address q address_a and address_b inclock data_a wren_a q_b ab wren_b b address q address_a and address_b unknown
8?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 referenced documents referenced documents this chapter references the following documents: an 207: trimatrix memory selection using the quartus ii software an 210: converting memory from asynchronous to synchronous for stratix and stratix gx designs fifo partitioner megafunction user guide single- and dual-clock fifo megafunctions user guide stratix ii device family data sheet (volume 1) of the stratix ii device handbook stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook using parity to de tect memory errors white paper document revision history table 8?15 shows the revision history for this chapter. table 8?15. document revision history date and document version changes made summary of changes october 2007, v4.5 added ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 7. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 added note to ?byte enable functional waveform? section. ? updated ?byte enable support? section. ? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 6. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook .?
altera corporation 9?1 october 2007 9. external memory interfaces in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx devices su pport a broad range of external memory interfaces such as doub le data rate (ddr) sdram, ddr2 sdram, rldram ii, qdrii sram, and single data rate (sdr) sdram. its dedicated phase-shift circuitry al lows the stratix ii or stratix ii gx device to interface with an external memory at twice the system clock speed (up to 300 mhz/600 megabits per second (mbps) with rldram ii). in addition to external memory interfaces, you can also use the dedicated phase-shift circuitry fo r other applications that require a shifted input signal. typical i/o architectures transmit a single data word on each positive clock edge and are limited to the associated clock speed. to achieve a 400-mbps transfer rate, a sdr system requires a 400-mhz clock. many new applications have introduced a ddr i/o architecture as an alternative to sdr architectures. whil e sdr architectures capture data on one edge of a clock, the ddr archit ectures captures data on both the rising and falling edges of the clock, doubling the throughput for a given clock frequency and accelerating pe rformance. for example, a 200-mhz clock can capture a 400-mbps data stream, enhancing system performance and simplifying board design. most new memory architectures us e a ddr i/o interface. although stratix ii and stratix ii gx devices also support the mature and well established sdr external memory, th is chapter focuses on ddr memory standards. these ddr memory standards cover a broad range of applications for embedded processor systems, image processing, storage, communications, and networking. stratix ii devices offer external memo ry support in every i/o bank. the side i/o banks support the pll-base d interfaces running at up to 200 mhz, while the top and bottom i/o banks support pll- and dll-based interfaces. figure 9?1 shows stratix ii device memory support. sii52003-4.5
9?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 introduction figure 9?1. external memory support bank 3 bank 4 bank 11 bank 9 pll11 pll5 pll7 pll1 pll2 pll4 pll3 pll10 support pll- and dll-based implementations support pll-based implementation support pll-based implementation support pll- and dll-based implementations vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 bank 8 bank 7 bank 12 bank 10 pll12 pll6 pll8 pll9 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 vref3b 2 vref2b2 vref1b2 vref0b2 bank 2 vref3b1 vref2b1 vref1b1 vref0b1 bank 1 vref1b 5 vref2b5 vref3b5 vref4b5 bank 5 vref1b6 vref2b6 vref3b6 vref4b6 bank 6 vref4b2 vref0b5 vref4b1 vref0b6 dqs4t dqs3t dqs2t dqs1t dqs0t dqs4b dqs3b dqs2b dqs1b dqs0b dqs8b dqs7b dqs6b dqs5b dqs8t dqs7t dqs6t dqs5t
altera corporation 9?3 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices table 9?1 summarizes the maximum clock rate stratix ii and stratix ii gx devices can support with external memory devices. this chapter describes the hardware features in stratix ii and stratix ii gx devices that facilitate the high-speed memory interfacing for each ddr memory standard. this chapter focuses primarily on the dll-based implementation. the pll-based im plementation is described in application notes. it then lists the stratix ii and stratix ii gx feature enhancements from stratix device s and briefly explains how each memory standard uses the stratix ii and stratix ii gx features. f you can use this document wi th the following documents: an 325: interfacing rldram ii wi th stratix ii & stratix gx devices an 326: interfacing qdrii & qdrii+ sram with stratix ii, stratix, & stratix gx devices an 327: interfacing ddr sdram with stratix ii devices an 328: interfacing ddr2 sdra m with stratix ii devices table 9?1. stratix ii and stra tix ii gx maximum clock rate suppor t for external memory interfaces notes (1) , (2) memory standards ?3 speed grade (mhz) ?4 speed grade (mhz) ?5 speed grade (mhz) dll-based pll-based dll-based pll-based dll-based pll-based ddr2 sdram (3) , (5) 333 200 267 167 233 167 ddr sdram (3) 200 150 200 133 200 100 rldram ii 300 200 250 (4) 175 200 175 qdrii sram 300 200 250 167 250 167 qdrii+ sram 300 (6) 250 (6) 250 (6) notes to ta b l e 9 ? 1 : (1) memory interface timing specifications are dependent on the memory, board, physical interface, and core logic. refer to each memory interface application note for more details on how each specification was generated. (2) the respective altera megacore function and the ep 2s60f1020c3 timing information featured in the quartus ? ii software version 6.0 was used to define these clock rates. (3) this applies for interfaces with both modules and components. (4) you must underclock a 300-mhz rldram ii device to achieve this clock rate. (5) to achieve speeds greater than 267 mhz (533 mbps) up to 333 mhz (667 mbps), you must use the altera ddr2 sdram controller megacore function that features a new dy namic auto-calibration circuit in the data path for resynchronization. for more informat ion, see the altera web site at www.altera.com . for interfaces running at 267 mhz or below, continue to use the static resynchron ization data path currently supported by the released version of the megacore function. (6) the lowest frequency at which a qdrii+ sram device can operate is 238 mhz. therefore, the pll-based implementation does not supp ort the qdrii+ sram interface.
9?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 external memory standards external memory standards the following sections briefly descri be the external memory standards supported by stratix ii and stratix ii gx devices. altera offers a complete solution for these memories, includ ing clear-text data path, memory controller, and timing analysis. ddr and ddr2 sdram ddr sdram is a memory architecture that transmits and receives data at twice the clock speed. these devices transfer data on both the rising and falling edge of the clock signal . ddr2 sdram is a second generation memory based on the ddr sdram architecture and transfers data to stratix ii and stratix ii gx devices at up to 333 mhz/667 mbps. stratix ii and stratix ii gx devices can support ddr sdram at up to 200 mhz/400 mbps. for pll-based im plementations, stratix ii and stratix ii gx devices support ddr and ddr2 sdram up to 150 mhz and 200 mhz, respectively. interface pins ddr and ddr2 sdram devices use inte rface pins such as data (dq), data strobe (dqs), clock, command, and address pins. data is sent and captured at twice the system clock rate by transferring data on the clock?s positive and negative edge. the commands and addresses still only use one active (positive) edge of a clock. ddr and ddr2 sdram use single-ended data strobes (dqs). ddr2 sdram can also use optional differential data strobes (dqs and dqs#). however, stratix ii and stratix ii gx devices do not use the op tional differential data strobes for ddr2 sdram interfaces since dqs an d dqsn pins in stratix ii and stratix ii gx devices are not differential. you can leave the ddr sdram memory dqs# pin unconnected. only the shifted dqs signal from the dqs logic block is used to capture data. ddr and ddr2 sdram 16 devices use two dqs pins, and each dqs pin is associated with eight dq pins. however, this is not the same as the 16/18 mode in stratix ii and stratix ii gx devices (see ?data and data strobe pins? on page 9?14 ). to support a 16 ddr sdram device, you need to configure stratix ii and stratix ii gx devices to use two sets of dq pins in 8/9 mode. similarly if your 32 memory device uses four dqs pins where each dqs pin is associated with eight dq pins, you need to configure stratix ii and stratix ii gx devices to use four sets of dqs/dq groups in 8/9 mode. connect the memory device?s dq and dqs pins to stratix ii and stratix ii gx dq and dqs pins, respectively, as listed in stratix ii and stratix ii gx pin tables. ddr and ddr 2 sdram also uses active-high data mask, dm, pins for writes. you can connect the memory?s dm pins
altera corporation 9?5 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices to any of stratix ii and stratix ii gx i/o pins in the same bank as the dq pins of the fpga. there is one dm pin per dqs/dq group in a ddr or ddr2 sdram device. you can also use i/o pins in banks 1, 2, 5, or 6 to interface with ddr and ddr2 sdram devices. these banks do not have dedicated circuitry, though, and can only support ddr sd ram at speeds up to 150 mhz and ddr2 sdram at speeds up to 200 mhz. ddr2 sdram interfaces using these banks are supported using th e sstl-18 class i i/o standard. f for more information, see an 327: interfacing ddr sdram with stratix ii devices and an 328: interfacing ddr2 sdram with stratix ii devices . if the ddr or ddr2 sdram device supports error correction coding (ecc), the design will use an extr a dqs/dq group for the ecc pins. you can use any of the user i/o pins for commands and addresses to the ddr and ddr2 sdram. you may need to generate these signals from the system clock?s negative edge. the clocks to the sdram device are ca lled ck and ck# pins. use any of the user i/o pins via the ddr regi sters to generate the ck and ck# signals to meet the ddr sdram or ddr2 sdram device?s t dqss requirement. the memory device?s t dqss specification requires that the write dqs signal?s positive edge must be within 25% of the positive edge of the ddr sdram or ddr2 sdram clock input. us ing regular i/o pins for ck and ck# also ensures th at any pvt variations on the dqs signals are tracked the same wa y by these ck and ck# pins. figure 9?2 shows a diagram that illustrate s how to generate these clocks.
9?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 external memory standards figure 9?2. clock generation for exter nal memory interfaces in strati x ii and stratix ii gx devices notes to figure 9?2 : (1) ck and ck# are the clocks to the memory devices. (2) dk and dk# are for rldram ii interfaces. you can generate dk# and dk from separate pins if the difference of the quartus ii software?s reported clock-to-out time for these pins meets the rldram ii device?s t ckdk specification. read and write operations when reading from the memory, ddr and ddr2 sdram devices send the data edge-aligned with respect to the data strobe. to properly read the data in, the data strobe needs to be ce nter-aligned with respect to the data inside the fpga. stratix ii and stratix ii gx devices feature dedicated circuitry to shift this data strobe to the middle of the data window. figure 9?3 shows an example of how the memory sends ou t the data and data strobe for a burst-of-two operation. q d q d le ioe v cc v cc ck# (1 ) dk# (2 ) ck (1) dk (2) q d q d clk v cc v cc gnd gnd
altera corporation 9?7 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 9?3. example of a 90 shift on the dqs signal notes (1) , (2) notes to figure 9?3 : (1) rldram ii and qdrii sram memory interfaces do not have preamble and postamble specifications. (2) ddr2 sdram does not support a burst length of two. (3) the phase shift required for your system should be based on your timing analysis and may not be 90. during write operations to a ddr or ddr2 sdram device, the fpga needs to send the data to the memory center-aligned with respect to the data strobe. stratix ii and stratix ii g x devices use a pll to center-align the data by generating a 0 phase-shif ted system clock for the write data strobes and a ?90 phase-shifted write clock for the write data pins for ddr and ddr2 sdram. figure 9?4 shows an example of the relationship between the data and da ta strobe during a burst-of-four write. dqs at fpga pin dq at fpga pin dqs at ioe registers dq at ioe registers 90? degree dq pin to r egister delay dqs pin to r egister delay preamble postamble (3)
9?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 external memory standards figure 9?4. dq and dqs relationship during a ddr and ddr2 sdram write notes (1) , (2) notes to figure 9?4 : (1) this example shows a write for a burst length of four. ddr sdram also supports burst lengths of two. (2) the write clock signals never go to hi-z state on rldram ii and qdrii sram memory interfaces because they use free-running clocks. however, the general timing relationship between data and the read clock shown in this figure still applies. f for more information on ddr sdram and ddr2 sdram specifications, refer to jedec standard publications jesd79c and jesd79-2, respectively, from www.jedec.org , or see an 327: interfacing ddr sdram with stratix ii devices and an 327: interfacing ddr sdram with stratix ii devices . rldram ii rldram ii provides fast random acce ss as well as high bandwidth and high density, making this memory technology ideal for high-speed network and communication data storage applications. the fast random access speeds in rldram ii device s make them a viable alternative to sram devices at a lower cost. additionally, rldram ii devices have minimal latency to support designs th at require fast response times. interface pins rldram ii devices use interface pins such as data, clock, command, and address pins. there are two types of rldram ii memory: common i/o (cio) and separate i/o (sio). the data pins in a rldram ii cio device are bidirectional while the data pins in a rldram ii sio device are unidirectional. instead of bidirectional data strobes, rldram ii uses differential free-running read and wr ite clocks to accompany the data. as in ddr or ddr2 sdram, data is sent and captured at twice the system clock rate by transferring data on th e clock?s positive and negative edge. the commands and addresses still only use one active (positive) edge of a clock. if the data pins are bidirectional, as in rldram ii cio devices, connect them to stratix ii and stratix ii gx dq pins. if the data pins are unidirectional, as in rldram ii si o devices, connect the rldram ii device q ports to the stratix ii and stratix ii gx device dq pins and dqs at fpga pin dq at fpga pin
altera corporation 9?9 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices connect the d ports to any user i/o pins in i/o banks 3, 4, 7, or 8 for optimal performance. rldram ii also uses active-high data mask, dm, pins for writes. you can connect dm pins to any of the i/o pins in the same bank as the dq pins of the fpga when interfacing with rldram ii cio devices to any of the i/ o pins in the same bank as the d pins when interfacing with rldram ii sio devices. there is one dm pin per rldram ii device. you can also use i/o pins in banks 1, 2, 5, or 6 to interface with rldram ii devices. however, these ba nks do not have dedicated circuitry and can only su pport rldram ii devices at speeds up to 200 mhz. rldram ii interfaces using these banks are supported using the 1.8-v hstl class i i/o support. connect the rldram ii device?s read clock pins (qk) to stratix ii or stratix ii gx dqs pins. because of software requirements, you must configure the dqs signals as bidirectional pins. however, since qk pins are output-only pins from the memo ry, rldram ii memory interfacing in stratix ii and stratix ii gx devices requires that you ground the dqs pin output enables. stratix ii and st ratix ii gx devices use the shifted qk signal from the dqs logic block to capture data. you can leave the qk# signal of the rldram ii device un connected, as dqs and dqsn in stratix ii and stratix ii gx device s are not differential pins. rldram ii devices also have inpu t clocks (ck and ck#) and write clocks (dk and dk#). you can use any of the user i/o pins for commands and addresses. rldram ii also offers qvld pins to indicate the read data availability. connect the qvld pins to the stra tix ii or stratix ii gx dqvld pins, listed in the pin table. 1 because the quartus ii software treats the dqvld pins like dq pins, you should ensure that th e dqvld pin is assigned to the pin table?s recommended pin. read and write operations when reading from the rldram ii device, data is sent edge-aligned with the read clock qk and qk#. when writing to the rldram ii device, data must be center-aligned with the write clock (dk and dk#). the rldram ii interface uses the same scheme as in ddr or ddr2 sdram interfaces, where the dedicated circuitry is used during reads to center-align the data and the read clock inside the fpga and the pll center-aligns the data and write clock outputs. the data and clock relationship for reads and writes in rldram ii is similar to those in ddr and ddr2 sdram as shown in figures 9?3 and 9?4 .
9?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 external memory standards f for details on rldram ii, see an 325: interfacing rldram ii with stratix ii & stratix gx devices . qdrii sram qdrii sram is the second generati on of qdr sram devices. both devices can transfer four words per clock cycle, fulfilling the requirements facing next-generation communications system designers. qdrii sram devices provide concurrent reads and writes, zero latency, and increased data throughput, allowing simultaneous access to the same address location. qdrii sram is avai lable in burst-of-2 and burst-of-4 devices. burst-of-2 devices support tw o-word data transfer on all read and write transactions, and burst-of-4 devices support four-word data transfer interface pins qdrii sram uses two separate, unidir ectional data ports for read and write operations, enabling qdr data transfer. qdrii sram uses shared address lines for reads and writes. qdrii sram burst-of-two devices sample the read address on the rising edge of the clock and sample the write address on the falling edge of the clock while qdrii sram burst-of-four devices sample both read and write addresses on the clock?s rising edge. connect the memory device?s q ports (read data) to the stratix ii or stratix ii gx dq pins. yo u can use any of the stratix ii or stratix ii gx device user i/o pins in i/o banks 3, 4, 7, or 8 for the d ports (write data), commands, and addresses. the control signals are sampled on the rising edge of the clock. you can also use i/o pins in banks 1, 2, 5, or 6 to interface with qdrii sram de vices. however, these banks do not have dedicated circuitry and can only support qdrii sram devices at speeds up to 200 mhz. qdrii sram in terfaces using these banks are supported using the 1.8-v hstl class i i/o support. qdrii sram uses the fo llowing clock signals: input clocks k and k# output clocks c and c# echo clocks cq and cq# clocks c#, k#, and cq# are logical complements of clocks c, k, and cq, respectively. clocks c, c#, k, and k# are inputs to the qdrii sram while clocks cq and cq# are outputs fr om the qdrii sram. stratix ii and stratix ii gx devices use single-clock mode for single-device qdrii sram interfacing where the k and k# are used for write operations, and cq and cq# are used for read operat ions. you should use both c or c# and k or k# clocks when interfacing with a bank of multiple qdrii sram devices with a single controller.
altera corporation 9?11 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices you can generate c, c#, k, and k# cl ocks using any of the i/o registers via the ddr registers. because of stri ct skew requirements between k and k# signals, use adjacent pins to generate the clock pair. connect cq and cq# pins to the stratix ii or stratix ii gx dqs and dqsn pins for dll-based implementation s. you must configure dqs and dqsn as bidirectional pins. howe ver, since cq and cq# pins are output-only pins from the memory, th e stratix ii or stratix ii gx device qdrii sram memory interface requir es that you ground the dqs and dqsn output enable. to capture data presented by the memory, connect the shifted cq signal to the input la tch and connect the active-high input registers and the shifted cq# signal is connected to the active-low input register. for pll-based implementation s, connect qk to the input of the read pll and leave qk# unconnected. read and write operations figure 9?5 shows the data and clock relationships in qdrii sram devices at the memory pins during re ads. data is output one-and-a-half clock cycles after a read command is latched into memory. qdrii sram devices send data within a t co time after each rising edge of the read clock c or c# in multi-clock mode, or the input clock k or k# in single clock mode. data is valid until t doh time after each rising edge of the read clock c or c# in multi-clock mode or the input clock k or k# in single clock mode. the cq and cq# clocks are edge-a ligned with the read data signal. these clocks accompany the read data for data capture in stratix ii and stratix ii gx devices.
9?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 external memory standards figure 9?5. data and clock relations hip during a qd rii sram read note (1) notes to figure 9?5 : (1) this relationship is at the memory device. the timing parameter nomencla ture is based on the cypress qdrii sram data sheet for cy7c1313v18. (2) t co is the data clock-to-out time and t doh is the data output hold time between burst. (3) t clz and t chz are bus turn-on and turn -off times respectively. (4) t cqd is the skew between the rising edge of cq or cq# and the data edges. (5) t ccqo and t cqoh are skew measurements between the c or c# clocks (or the k or k# clocks in single-clock mode) and the cq or cq# clocks. when reading from the qdrii sram, da ta is sent edge-aligned with the rising edge of the echo clocks cq and cq#. both cq and cq# are shifted inside the fpga using dqs and dqsn logic blocks to capture the data in the ddr ioe registers in dll-based implementations. in pll-based implementations, cq feeds a pll, wh ich generates the clock to capture the data in the ddr ioe registers. when writing to qdrii sram devices, data is generated by the write clock while the k clock is 90 shifted from the write clock, creating a center-aligned arrangement. read and write operations occur during the same clock cycle on independent read and write data pa ths along with th e cycle-shared address bus. performing concurrent re ads and writes does not change the functionality of either transaction. if a read request occurs simultaneously with a write request at the same addr ess, the new data on d is forwarded to q. therefore, latency is not required to access valid data. f for more information on qdrii sram, go to www.qdrsram.com or see an 326: interfacing qdrii & qdrii+ sr am with stratix ii, stratix, & stratix gx devices . qa qa + 1 qa + 2 qa + 3 c/k c#/k# cq cq# q t co (2) t co (2) t clz (3) t ccqo (5) t cqoh (5) t cqd (4) t cqd (4) t doh (2) t chz (3)
altera corporation 9?13 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices stratix ii and stratix ii gx ddr memory support overview this section describes stratix ii and stratix ii gx features that enable high-speed memory interfacing. it first describe s stratix ii and stratix ii gx memory pins and then th e dqs phase-shift circuitry and the ddr i/o registers. table 9?2 shows the i/o standard associated with the external memory interfaces. stratix ii and stratix ii gx devices suppo rt the data strobe or read clock signal (dqs) used in ddr sdra m, ddr2 sdram, rldram ii, and qdrii sram devices with dedicated ci rcuitry. stratix ii and stratix ii gx devices also support the dqsn signal (the dqs complement signal) for external memory types that requ ire them, for example qdrii sram. dqs and dqsn signals are usually asso ciated with a group of data (dq) pins. however, these are not differential buffers and cannot be used in ddr2 sdram or rldram ii interfaces. 1 you can also interface with these external memory devices without the use of dedicated circ uitry at a lower performance. f for more information, see the appr opriate stratix ii or stratix ii gx memory interfaces applic ation note available at www.altera.com . stratix ii and stratix ii gx devices cont ain dedicated circuitry to shift the incoming dqs signals by 0, 22.5, 30, 36, 45, 60, 67.5, 72, 90, 108, 120, or 144, depending on the delay-locked loop (dll) mode. there are four dll modes. the dqs phase-shift circuitry uses a frequency reference to dynamically generate control signals for the delay chains in each of the dqs and dqsn pins, allo wing it to compensate for process, table 9?2. external memory support in stratix ii and strati x ii gx devices memory standard i/o standard ddr sdram sstl-2 class ii ddr2 sdram sstl-18 class ii (1) rldram ii (2) 1.8-v hstl class i or ii (1) qdrii sram (2) 1.8-v hstl class i or ii (1) notes to ta b l e 9 ? 2 : (1) stratix ii and stratix ii gx devices support 1.8-v hstl/sstl-18 class i and ii i/o standards in i/o banks 3, 4, 7, and 8. in i/o banks 1, 2, 5, and 6, class i is supported for both input and output operat ions, while class ii is only supported for input operations for these i/o standards. (2) for maximum performance, altera recommends using the 1.8-v hstl i/o standard. rldram ii and qdrii sram de vices also support the 1.5-v hstl i/o standard.
9?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview voltage, and temperature (pvt) variat ions. this phase-shift circuitry has been enhanced in stratix ii and stratix ii gx devices to support more phase-shift options with less jitter. besides the dqs dedicated phase-shift circuitry, each dqs and dqsn pin has its own dqs logic block that sets the delay for the signal input to the pin. using the dqs dedicated phase- shift circuitry wi th the dqs logic block allows for phase-shift fine-tun ing. additionally, every ioe in a stratix ii or stratix ii gx device contains six registers and one latch to achieve ddr operation. ddr memory interface pins stratix ii and stratix ii gx devices use data (dq), data strobe (dqs and dqsn), and clock pins to inte rface with external memory. figure 9?6 shows the dq, dqs, and dqsn pins in the stratix ii or stratix ii gx i/o banks on the top of the device. a similar arrangement is repeated at the bottom of the device. figure 9?6. dq and dqs pins per i/o bank data and data strobe pins stratix ii and stratix ii gx data pins for the ddr memory interfaces are called dq pins. stratix ii and stratix ii gx devices can use either bidirectional data strobes or unidirectional read clocks. depending on the external memory interface, either th e memory device?s read data strobes or read clocks feed the stratix ii or stratix ii gx dqs (and dqsn) pins. pll 11 pll 5 i/o bank 11 i/o bank 3 i/o bank 9 i/o bank 4 dqs phase shift circuitry dq pins dq pins dqs pin dqsn pin dqsn pin dqs pin up to 8 sets of dq & dqs pins up to 10 sets of dq & dqs pins
altera corporation 9?15 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices stratix ii and stratix ii gx dqs pins connect to the dqs pins in ddr and ddr2 sdram interfaces or to the qk pi ns in rldram ii interfaces. the dqsn pins are not used in these in terfaces. connect the stratix ii or stratix ii gx dqs and dqsn pins to the qdrii sram cq and cq# pins, respectively. in every stratix ii or stratix ii gx device, the i/o banks at the top (i/o banks 3 and 4) and bottom (i/o banks 7 and 8) of the device support ddr memory up to 300 mhz/600 mbps (wit h rldram ii). these i/o banks support dqs signals and its comple ment dqsn signals with dq bus modes of 4, 8/9, 16/18, or 32/36. in 4 mode, each dqs/dqsn pin drives up to four dq pins within that group. in 8/9 mode, each dqs/dqsn pin drives up to nine dq pins within that group to support one parity bit and the eight data bits. if the parity bit or any data bit is not used , the extra dq pins can be used as regular user i/o pins. similarly, wi th 16/18 and 32/36 modes, each dqs/dqsn pin drives up to 18 and 36 dq pins respectively. there are two parity bits in the 16/18 mode and four parity bits in the 32/36 mode. tables 9?3 through 9?6 show the number of dqs/dq groups and non-dqs /dq supported in each stratix ii or stratix ii gx density/package combination, respectively, for dll-based implementations. table 9?3. stratix ii dqs and dq bus mode support (part 1 of 2) note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2s15 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 ep2s30 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 ep2s60 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 ep2s90 484-pin hybrid fineline bga 8 4 0 0 780-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 ep2s130 780-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4
9?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview ep2s180 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 note to ta b l e 9 ? 3 : (1) check the pin table for each dq s/dq group in the different modes. table 9?3. stratix ii dqs and dq bus mode support (part 2 of 2) note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups table 9?4. stratix ii non-dqs and dq bus mode support note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2s15 484-pin fineline bga 13 7 3 1 672-pin fineline bga 24 9 4 2 ep2s30 484-pin fineline bga 13 7 3 1 672-pin fineline bga 36 15 7 3 ep2s60 484-pin fineline bga 13 7 3 1 672-pin fineline bga 36 15 7 3 1,020-pin fineline bga 51 26 13 6 ep2s90 780-pin fineline bga 40 24 12 6 1,020-pin fineline bga 51 25 12 6 1,508-pin fineline bga 51 25 12 6 ep2s130 780-pin fineline bga 40 24 12 6 1,020-pin fineline bga 51 25 12 6 1,508-pin fineline bga 51 25 12 6 ep2s180 1,020-pin fineline bga 51 25 12 6 1,508-pin fineline bga 51 25 12 6 note to ta b l e 9 ? 4 : (1) check the pin table for each dq s/dq group in the different modes.
altera corporation 9?17 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices 1 to support the rldram ii qvld pin, some of the unused 4 dqs pins, whose dq pins were combined to make the bigger 8/9, 16/18, or 32/36 groups, are listed as dqvld pins in the stratix ii or stratix ii gx pin table. dqvld pins are for input-only operations. the signal coming into this pin can be captured by the shifted dqs signal like any of the dq pins. table 9?5. stratix ii gx dq s and dq bus mode support note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2sgx30c ep2sgx30d 780-pin fineline bga 18 8 4 0 ep2sgx60c ep2sgx60d 780-pin fineline bga 18 8 4 0 ep2sgx60e 1,152-pin fineline bga 36 18 8 4 ep2sgx90e 1,152-pin fineline bga 36 18 8 4 ep2sgx90f 1,508-pin fineline bga 36 18 8 4 ep2sgx130g 1,508-pin fineline bga 36 18 8 4 note to ta b l e 9 ? 5 : (1) check the pin table for each dq s/dq group in the different modes. table 9?6. stratix ii gx non-dqs and dq bus mode support note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2sgx30 780-pin fineline bga 18 8 4 2 ep2sgx60 780-pin fineline bga 18 8 4 2 1,152-pin fineline bga 25 13 6 3 ep2sgx90 1,152-pin fineline bga 25 13 6 3 1,508-pin fineline bga 25 12 6 3 ep2sgx130 1,508-pin fineline bga 25 12 6 3 note to ta b l e 9 ? 6 : (1) check the pin table for each dq s/dq group in the different modes.
9?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview the dqs pins are listed in the stra tix ii or stratix ii gx pin tables as dqs[17..0]t or dqs[17..0]b . the t denotes pins on the top of the device and the b denotes pins on the bottom of the device. the complement dqsn pins are marked as dqsn[17..0]t or dqsn[17..0]b . the corresponding dq pins are marked as dq[17..0]t[3..0] , where [17..0] indicates which dqs group the pins belong to. similarly, the corr esponding dqvld pins are marked as dqvld[8..0]t , where [8..0] indicates which dqs group the pins belong to. the numbering scheme starts from right to left on the package bottom view. when not used as dq, dq s, or dqsn pins, these pins are available as regular i/o pins. figure 9?7 shows the dqs pins in stratix ii or stratix ii gx i/o banks. 1 the quartus ii software treats dq vld pins as regular dq pins. therefore, you must ensure that the dqvld pin assigned in your design corresponds to the pin table?s recommended dqvld pins. figure 9?7. dqs pins in stratix ii and stratix ii gx i/o banks notes (1) , (2) , (3) notes to figure 9?7 : (1) there are up to 18 pairs of dqs and dqsn pins on both the top and bottom of the device. see table 9?3 for the exact number of dqs and dqsn pin pairs in each device package. (2) see table 9?7 for the available dqs and dqsn pins in each mode and package. (3) each dqs pin has a complement dqsn pin. dqs and dqsn pins are not differential. the dq pin numbering is based on 4 mode. there are up to 8 dqs/dq groups in 4 mode in i/o banks 3 and 8 and up to 10 dqs/dq groups in 4 mode in i/o banks 4 and 7. in 8/9 mode, two adjacent 4 dqs/dq groups plus one parity pin are comb ined; one pair of dqs/dqsn pins from the combined groups can drive all the dq and parity pins. since there is an even number of dqs/dq groups in an i/o bank, combining groups is efficient. similarly, in 16/18 mode, four adjacent 4 dqs/dq groups plus two parity pins are combined and one pair of dqs/dqsn pins from the combined groups can dr ive all the dq and parity pins. in pll 11 pll 5 i/o bank 11 i/o bank 3 i/o bank 9 i/o bank 4 dqs phase shift circuitry dq pins dq pins dqs pin dqsn pin dqsn pin dqs pin up to 8 sets of dq & dqs pins up to 10 sets of dq & dqs pins
altera corporation 9?19 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices 32/36 mode, eight adjacent dqs/dq groups are combined and one pair of dqs/dqsn pins can drive al l the dq and parity pins in the combined groups. table 9?7 shows which dqs and dqsn pins are available in each mode and package in the stratix ii or stratix ii gx device family. 1 on the top and bottom side of the device, the dq and dqs pins must be configured as bidirectional ddr pins to enable the dqs phase-shift circuitry. the dqsn pins can be configured as input, output, or bidirectional pins. you can use the altdq and altdqs megafunctions to configure the dq and dqs/dqsn paths, respectively. however, altera highly recommends that you use the respective altera me mory controller ip tool bench for your external memory interfac e data paths. the data path is clear-text and free to use. you are responsible for your own timing analysis if you use your own data path. if you only want to use the dq and/or dqs pins as inputs, you need to set the output enable of the dq and/or dqs pins to ground. stratix ii or stratix ii gx side i/o banks (i/o banks 1, 2, 5, and 6) support all the memory interfaces supported in the top and bottom i/o banks. for optimal performance, use the altera memory contro ller ip tool bench to pick the data and strobe pins for these interfaces. since these i/o banks do not have any dedicated circuitry for memory interfacing, they can support ddr sdram at speeds up to 150 mhz and other ddr memories at speeds up to 200 mhz. you need to use the sstl-18 class i i/o standard when interfacing with ddr 2 sdram devices using pins in i/o bank 1, 2, 5, or 6. these i/o banks do not support the sstl-18 class ii and table 9?7. available dqs and dqsn pins in each mode and package note (1) mode package 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga 4 7, 9, 11, 13 odd-numbered pins only all dqs and dqsn pins 8/9 7,11 3, 7, 11, 15 even-numbered pins only 16/18 n/a 5, 13 3, 7, 11, 15 32/36 n/a n/a 5, 13 note to ta b l e 9 ? 7 : (1) the numbers correspond to the dqs and dqsn pin numberin g in the stratix ii or strati x ii gx pin table. there are two sets of dqs/dq groups, one corr esponding with the top side of the device and one with the bottom side of the device.
9?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview 1.8-v hstl class ii i/o standards on output and bidirectional pins, but you can use sstl-18 class i or 1.8- v hstl class i i/o standards for memory interfaces. 1 the altera memory controller ip tool bench generates the optimal pin constraints that allow you to interface these memories at high frequency. table 9?8 shows the maximum clock rate supported for the ddr sdram interface in the stratix ii or st ratix ii gx device side i/o banks. clock pins you can use any of the ddr i/o registers to generate clocks to the memory device. for better performanc e, use the same i/o bank as the data and address/command pins. command and address pins you can use any of the user i/o pins in the top or bottom bank of the device for commands and addresses. for better performance, use the same i/o bank as the data pins. other pins (parity, dm, ecc and qvld pins) you can use any of the dq pins for the parity pins in stratix ii and stratix ii gx devices. the stratix ii or stratix ii gx device family has support for parity in the 8/9, 16/18, and 32/36 mode. there is one parity bit available per 8 bits of data pins. the data mask, dm, pins are only required when writing to ddr sdram, ddr2 sdram, and rldram ii devices. a low signal on the dm pins indicates that the write is valid. if the dm signal is high, the memory will mask the dq signals. you can use any of the i/o pins in the same bank as the dq pins (or th e rldram ii sio?s and qdrii sram?s d pins) for the dm signals. each gr oup of dqs and dq signals in ddr table 9?8. maximum clock rate for ddr and ddr2 sdram in stratix ii or stratix ii gx side i/o banks stratix ii or stratix ii gx device speed grade ddr sdram (mhz) ddr2 sdram (mhz) qdrii sram (mhz) rldram ii (mhz) -3 150 200 200 200 -4 133 167 167 175 -5 133 167 167 175
altera corporation 9?21 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices and ddr2 sdram devices requires a dm pin. there is one dm pin per rldram ii device. the ddr i/o output registers, clocked by the ?90 shifted clock, creates the dm sign als, similar to dq output signals. 1 perform timing analysis to calc ulate your write-clock phase shift. some ddr sdram and ddr2 sdram devices support error correction coding (ecc), which is a method of detecting and automatically correcting errors in data transmissi on. in a 72-bit ddr sdram interface, there are eight ecc pins in addition to the 64 data pins. connect the ddr and ddr2 sdram ecc pins to a stratix ii or stratix ii gx device dqs/dq group. the memory controller needs extra logic to encode and decode the ecc data. qvld pins are used in rldram ii interfacing to indicate the read data availability. there is one qvld pin per rldram ii device. a high on qvld indicates that the memory is outputting the data requested. similar to dq inputs, th is signal is edge-aligned with qk/qk# signals and is sent half a clock cycle before data starts coming out of the memory. you need to connect qvld pins to the dqvld pin on the stratix ii or stratix ii gx device. the dqvld pin ca n be used as a regular user i/o pin if not used for qvld. because the quartus ii software does not differentiate dqvld pins from dq pins, you must ensure that your design uses the pin table?s recommended dqvld pin. dqs phase-shift circuitry the stratix ii or stratix ii gx phase- shift circuitry and the dqs logic block control the dqs and dqsn pins. each stratix ii or stratix ii gx device contains two phase-shifting ci rcuits. there is on e circuit for i/o banks 3 and 4, and another circuit for i/o banks 7 and 8. the phase- shifting circuit on the top of the de vice can control all the dqs and dqsn pins in the top i/o banks and the phas e-shifting circuit on the bottom of the device can control all the dqs and dqsn pins in the bottom i/o banks. figure 9?8 shows the dqs and dqsn pin connections to the dqs logic block and the dqs phase-shift circuitry.
9?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview figure 9?8. dqs and dqsn pins and the dqs phase-shift circuitry note (1) notes to figure 9?8 : (1) there are up to 18 pairs of dqs and dqsn pins availabl e on the top or the bottom of the stratix ii or stratix ii gx device, up to 8 on the left side of th e dqs phase-shift circuitry (i/o banks 3 and 8), and up to 10 on the right side (i/o bank 4 and 7). (2) clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase-shift circuitry on the bottom of the device. you can also use a phase-locked loop (pll) clock output as a reference clock to the phase-shift circuitry. the refe rence clock can also be used in the logic array. (3) you can only use pll 5 to feed the dqs phase-shift circ uitry on the top of the device and pll 6 to feed the dqs phase-shift circuitry on the bottom of the device. figure 9?9 shows the connections between the dqs phase-shift circuitry and the dqs logic block. dqs pin dqsn pin dqsn pin dqs pin dqs pin dqsn pin dqs pin dqsn pin from pll 5 (3) clk[15..12]p (2) to ioe to ioe to ioe to ioe to ioe to ioe to ioe t t t t t t t to ioe dqs phase-shift circuitry t dqs logi c blocks
altera corporation 9?23 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 9?9. dqs phase-shift circu itry and dqs logic block connections note (1) notes to figure 9?9 : (1) all features of the dqs phase-shift circuitry and the dqs logic block are accessible from the altdqs megafunction in the quartus ii software. you should, h owever, use altera?s memory controller ip tool bench to generate the data path for your memory interface. (2) dqs logic block is available on every dqs and dqsn pin. (3) there is one dqs phase-shift circuit on the top and bottom side of the device. (4) the input reference clock can come from clk[15..12]p or pll 5 for the dqs phase-shift circuitry on the top side of the device or from clk[7..4]p or pll 6 for the dqs phase-shift circui try on the bottom side of the device. (5) each individual dqs and dqsn pair can have indi vidual dqs delay settings to and from the logic array. (6) this register is one of the dqs ioe input registers. 6 6 phase offset control 6 phase offset settings from the logic array phase offset settings input reference clock (4) upndn clock enable dll 6 addnsub phase comparator delay chains up/down counter dq dq en en update enable circuitry 6 6 6 6 6 6 dqs delay settings to and from the logic array (5) dqs delay settings from the dqs phase-shift circuitry dqs or dqsn dqs delay chain bypass dqs logic block (2) dqs logic block (2) dqs logic block (2) dqs phase-shift circuitry (3) dqs or dqsn dqs or dqsn not postamble circuitry gated_dqs control dqs bus prn clrn q dff reset enablen a b v cc dqs' sclr (6)
9?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview the phase-shift circuitry is only used during read transactions where the dqs and dqsn pins are acting as inpu t clocks or strobes. the phase-shift circuitry can shift the incoming dqs signal by 0, 22.5, 30, 36, 45, 60, 67.5, 72, 90, 108, 120, or 144. the sh ifted dqs signal is then used as clocks at the dq ioe input registers. figure 9?3 shows an example where the dqs signal is shifted by 90. the dqs signals goes through the 90 shift delay set by the dqs phase-shift circuitry and the dqs lo gic block and some routing delay from the dqs pin to the dq ioe registers. the dq signals only goes through routing delay from the dq pin to the dq ioe registers and maintains the 90 relationship between the dqs and dq signals at the dq ioe registers since the software will automatically set delay chains to match the routing delay between the pins and the ioe registers for the dq and dqs input paths. all 18 dqs and dqsn pins on either the top or bottom of the device can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency. for example you can have a 90 phase shift on dqs0t and have a 60 phase shift on dqs1t both referenced from a 200-mhz clock. n ot all phase-shift combinations are supported, however. the ph ase shifts on the same side of the device must all be a multiple of 22.5 (up to 90) , a multiple of 30 (up to 120), or a multiple of 36 (up to 144). in order to generate the correct phase shift with the dll used, you must provide a clock signal of the same fr equency as the dqs signal to the dqs phase-shift circuitry. any of the clk[15..12]p clock pins can feed the phase circuitry on the top of the device (i/o banks 3 and 4) or any of the clk[7..4]p clock pins can feed the phase circuitry on the bottom of the device (i/o banks 7 and 8). stratix i i and stratix ii gx devices can also use plls 5 or 6 as the reference cloc k to the dqs phase-shift circuitry on the top or bottom of the device, resp ectively. pll 5 is connected to the dqs phase-shift circuitry on the top side of the device and pll 6 is connected to the dqs phase-shift circ uitry on the bottom side of the device. both the top and bottom phase- shift circuits need unique clock pins or pll cloc k outputs for the reference clock. 1 when you have a pll dedicated only to generate the dll input reference clock, you must set the pll mode to ?no compensation? or the quartus ? ii software will change it automatically. because there are no other pll outputs used, the pll doesn?t need to compensate for any clock paths.
altera corporation 9?25 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices dll the dqs phase-shift circuitry uses a delay-locked loop (dll) to dynamically measure the clock period needed by the dqs/dqsn pin (see figure 9?10 ). the dqs phase-shift circuitry then uses the clock period to generate the correct phase shift. the dll in the stratix ii or stratix ii gx dqs phase-shift circuitry can oper ate between 100 and 400 mhz. the phase-shift circuitry needs a maximum of 256 clock cycles to calculate the correct input clock period. data sent during these clock cycles may not be properly captured. 1 although the dll can run up to 400 mhz, other factors may prevent you from interfacing with a 400-mhz external memory device. 1 you can still use the dqs phase-shift circuitry for any memory interfaces that are less than 100 mhz. the dqs signal will be shifted by 2.5 ns and you can ad d more shift by using the phase offset module. even if the dqs sign al is not shifted exactly to the middle of the dq valid window, the ioe should still be able to capture the data in this low frequency application. there are four different frequency modes for the stratix ii or stratix ii gx dll. each frequency mode provides different phase shift, as shown in table 9?9 . in frequency mode 0, stratix ii devices use a 6-bit setting to implement the phase-shift delay. in frequency modes 1, 2, and 3, stratix ii devices only use a 5-bit setting to implement the phase-shift delay. the dll can be reset from either the logic array or a user i/o pin. this signal is not shown in figure 9?10 . each time the dll is reset, you must wait for 256 clock cycles before you can capture the data properly. table 9?9. stratix ii and strati x ii gs dll frequency modes frequency mode frequency range (mhz) available phase shift number of delay chains 0 100?175 30, 60, 90, 120 12 1 150?230 22.5, 45, 67.5, 90 16 2 200?310 30, 60, 90, 120 12 3 240?400 (c3 speed grade) 240?350 (c4 and c5 speed grades) 36, 72, 108, 144 10
9?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview 1 the input reference clock for the dqs phase-shift circuitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference cl ock for the dqs phase-shift circuitry on the bottom side of the device can come from clk[7..4]p or pll 6. table 9?10 lists the maximum delay in th e fast timing model for the stratix ii dqs delay buffer. multiply th e number of delay buffers that you are using in the dqs logic block to ge t the maximum delay achievable in your system. for example, if you im plement a 90 phase shift at 200 mhz, you use three delay buffers in mode 2. the maximum achievable delay from the dqs block is th en 3 .416 ps = 1.248 ns. table 9?10. dqs delay buffer maximum delay in fast timing model frequency mode maximum delay per delay buffer (fast timing model) unit 0 0.833 ns 1, 2, 3 0.416 ns
altera corporation 9?27 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 9?10. simplified diagram of the dqs phase-shift circuitry note (1) notes to figure 9?10 : (1) all features of the dqs phase-shift circuitry are accessi ble from the altdqs megafunction in the quartus ii software. you should; however, use altera?s memory controller ip tool bench to generate the data path for your memory interface. (2) the input reference clock for the dqs phase-shift circ uitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference clock for the dqs phase-shift circuitry on the bottom side of the device can come from clk[7..4]p or pll 6. (3) phase offset settings can only go to the dqs logic blocks. (4) dqs delay settings can go to the logic array and/or to the dqs logic block. the input reference clock goes into the dll to a chain of up to 16 delay elements. the phase comparator compar es the signal co ming out of the end of the delay element chain to th e input reference clock. the phase comparator then issues the upndn signal to the up/down counter. this signal increments or decrements a six-bit delay setting (dqs delay settings) that will increase or de crease the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay elem ent chain in phase. the dqs delay settings contain the cont rol bits to shift the signal on the input dqs pin by the amount set in the altdqs megafunction. for the 0 shift, both the dll and the dqs logi c block are bypassed. since stratix ii and stratix ii gx dqs and dq pins are designed such that the pin to ioe delays are matched, the skew between the dq and dqs pin at the dq ioe registers is negligible when the 0 sh ift is implemented. you can feed the dqs delay settings to the dqs lo gic block and the logic array. 6 6 6 phase offset control 6 phase offset settings from the logic array phase offset settings (3) dqs delay settings (4) input reference clock (2) upndn clock enable dll 6 addnsub phase comparator delay chains up/down counter
9?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview phase offset control the dqs phase-shift circuitry also cont ains a phase offset control module that can add or subtract a phase offs et amount from the dqs delay setting (phase offset settings from the logic array in figure 9?10 ). you should use the phase offset control module for maki ng small shifts to the input signal and use the dqs phase-shift circuitry fo r larger signal shifts. for example, if you need the input signal to be shifted by 75, you can set the altdqs megafunction to generate a 72 phase shift with a phase offset of +3. you can either use a static phase of fset or a dynamic phase offset to implement the additional phase shift. the availabl e additional phase shift is implemented in 2s -complement between se ttings ?64 to +63 for frequency mode 0, and between settings ?32 to +31 for frequency modes 1, 2, and 3. however, the dqs dela y settings are at the maximum at setting 64 for frequency mode 0, an d at the maximum at setting 32 for frequency modes 1, 2, and 3. therefore, the actual physical offset setting range will be 64 or 32 subtracted by the dqs delay settings from the dll. for example, if the dll determines that to achieve 30 you will need a dqs delay setting of 28, you can subtract up to 28 phase offset settings and you can add up to 36 phase offset settings to achieve the optimal delay. 1 each phase offset setting transl ates to a certain delay, as specified in the dc & switching charact eristics of stratix iii devices chapter in volume 2 of the stratix iii device handbook . when using the static phase offset , you can specify the phase offset amount in the altdqs megafunction as a positive number for addition or a negative number for subtraction. you can also have a dynamic phase offset that is always added to, su btracted from, or both added to and subtracted from the dll phase shift. when you always add or subtract, you can dynamically input the phase offset amount into the dll_offset[5..0] port. when you want to both add and subtract dynamically, you control the addnsub signal in ad dition to the dll_offset[5..0] signals. dqs logic block each dqs and dqsn pin is connected to a separate dqs logic block (see figure 9?11 ). the logic block contains dqs delay chains and postamble circuitry.
altera corporation 9?29 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices 1 the input reference clock for the dqs phase-shift circuitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference cl ock for the dqs phase-shift circuitry on the bottom side of the device can come from clk[7..4]p or pll 6. figure 9?11. simplified diagra m of the dqs logic block note (1) notes to figure 9?11 : (1) all features of the dqs logic block are accessible from the altdqs megafunction in the quartus ii software. you should; however, use altera?s memory controller ip tool be nch to generate the data path for your memory interface. (2) the input reference clock for the dqs phase-shift circ uitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference clock for the dqs ph ase-shift circuitry on the top side of the device can come from clk[7..4]p or pll 6. (3) this register is one of the dqs ioe input registers. dq dq en en update enable circuitry 6 6 6 6 6 6 dqs delay settings from the dqs phase- shift circuitry dqs or dqsn pin input reference clock (2) dqs delay chain bypass phase offset settings 6 6 not postamble circuitry gated_dqs control dqs bus prn clrn q dff reset enablen a b v cc dqs' sclr (3)
9?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview dqs delay chains the dqs delay chains consist of a set of variable delay elements to allow the input dqs and dqsn signals to be shifted by the amou nt given by the dqs phase-shift circuitry or the logic array. there are four delay elements in the dqs delay chain; the first de lay chain closest to the dqs pin can either be shifted by the dqs delay sett ings or by the sum of the dqs delay setting and the phase-offset setting. the number of delay chains used is transparent to the users because the altdqs megafunction automatically sets it. the dqs delay settings can come from the dqs phase-shift circuitry on the same side of the device as the target dqs logic block or from the logic array. when you apply a 0 shift in the altdqs megafunction, the dqs delay chains are bypassed. the delay elements in the dqs logic block mimic the delay elements in the dll. when the dll is not used to control the dqs delay chains, you can input your own 6- or 5-bit settings using the dqs_delayctrlin[5..0] signals available in the altdqs megafunction. these settings control 1, 2, 3, or all 4 dela y elements in the dqs delay chains. the amount of delay is equal to the sum of the delay element?s intrinsic delay and the prod uct of the number of delay steps and the value of the delay steps. both the dqs delay settings and the ph ase-offset settings pass through a latch before going into the dqs delay chains. the latches are controlled by the update enable circuitry to al low enough time for any changes in the dqs delay setting bits to arrive to all the delay elements. this allows them to be adjusted at the same time . the update enable circuitry enables the latch to allow enough time for the dqs delay settings to travel from the dqs phase-shift circuitry to all th e dqs logic blocks before the next change. it uses the input reference cl ock to generate the update enable output. the altdqs megafunction uses this circuit by default. see figure 9?12 for an example waveform of the update enable circuitry output. the shifted dqs signal then goes to the dqs bus to clock the ioe input registers of the dq pins. it can also go into the logic array for resynchronization purposes. the shifte d dqsn signal can only go to the active-low input register in the dq ioe and is only used for qdrii sram interfaces.
altera corporation 9?31 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 9?12. dqs update enable waveform dqs postamble circuitry for external memory interfaces that use a bidirectional read strobe like ddr and ddr2 sdram, the dqs signal is low before going to or coming from a high-impedance state. see figure 9?3 . the state where dqs is low, just after a high-impedance state, is called the preamble and the state where dqs is low, just before it re turns to a high-impedance state, is called the postamble. there are prea mble and postamble specifications for both read and write operations in ddr and ddr2 sdram. the dqs postamble circuitry ensures data is not lost when there is noise on the dqs line at the end of a read postambl e time. it is to be used with one of the dqs ioe input registers such that the dqs postamble control signal can ground the shifted dqs signal used to clock the dq input registers at the end of a read operation. this en sures that any glitches on the dqs input signals at the end of the read postamble time do not affect the dq ioe registers. f see an 327: interfacing ddr sd ram with stratix ii devices and an 328: interfacing ddr2 sdram with stratix ii devices for more details. ddr registers each ioe in a stratix ii or stratix ii gx device contains six registers and one latch. two registers and a latch ar e used for input, two registers are used for output, and two registers are used for output enable control. the second output enable register provides the write preamble for the dqs strobe in the ddr external memory interfaces. this ac tive low output enable register extends the high-impedance state of the pin by a half clock cycle to provide the external memory?s dqs write preamble time specification. figure 9?13 shows the six register s and the latch in the stratix ii or stratix ii gx ioe and figure 9?14 shows how the second oe register extends the dqs high-impedance state by half a clock cycle during a write operation. update enable circuitry output system clock dqs delay settings (updated every 8 cycles) dll counter update (every eight cycles) 6 bit dll counter update (every eight cycles)
9?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview figure 9?13. bidirectional ddr i/o path in stratix ii and stratix ii gx devices note (1) notes to figure 9?13 : (1) all control signals can be inverted at the ioe. the si gnal names used here match with quartus ii software naming convention. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before input to the a oe register during compilation. (3) the a oe register generates the enable signal for general-purpose ddr i/o applications. (4) this select line is to choose whether the oe signal should be delayed by half-a-clock cycle. (5) the b oe register generates the delayed enable signal for the write strobes or write cloc ks for memory interfaces. (6) the tristate enable is by default active low. you can, however, design it to be active high. the combinational control path for the tristate is not shown in this diagram. (7) you can also have combinational output to th e i/o pin; this path is not shown in the diagram. (8) on the top and bottom i/o banks, the cl ock to this register can be an inverted register a?s clock or a separate clock (inverted or non-inverted). on the side i/o banks, you can only use the inverted register a?s clock for this port. d q dff d q ena d q dff input re g ister b i input re g ister a i latch c dq dff dq dff 0 1 output re g ister a o output re g ister b o dq dff dq dff or2 tri i/o pin (7 ) oe re g ister b oe oe re g ister a oe lo g ic array dataout_l dataout_h outclock datain_h datain_l oe inclock ne g _re g _out i 0 (5) (4) (6) (3) combout 1 (2) latch tchla (8)
altera corporation 9?33 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 9?14. extending the oe disable by ha lf-a-clock cycle for a write transaction note (1) note to figure 9?14 : (1) the waveform reflects the so ftware simulation result. the oe signal is an active low on the device. however, the quartus ii software implements this signal as an active high and automatically adds an inverter before the a oe register d input. figures 9?15 and 9?16 summarize the ioe registers used for the dq and dqs signals. d0 d0 d2 d1 d1 d3 d2 d3 preamble postamble system clock (outclock for dqs) oe for dqs (from logic array) datain_h (from logic array) datain_l (from logic array) oe for dq (from logic array) write clock (outclock for dq, ? 90 phase shifted from system clock) dqs dq delay by half a clock cycle 90?
9?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview figure 9?15. dq configurat ion in stratix ii or stratix ii gx ioe note (1) notes to figure 9?15 : (1) you can use the altdq megafunction to generate the dq signals. you should, however, use altera?s memory controller ip tool bench to generate the data path for your memory interface. the signal names used here match with quartus ii software naming convention. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before the oe register a oe during compilation. (3) the outclock signal for ddr, ddr2 sdram, and qdrii sram inte rfaces has a 90 phase-shift relationship with the system clock. for 300-mhz rldram ii interfaces with ep2s60f1020c3, altera recommends a 75 phase-shift relationship. (4) the shifted dqs or dqsn signal can clock this regist er. only use the dqsn signal for qdrii sram interfaces. (5) the shifted dqs signal must be invert ed before going to the dq ioe. the inversion is automatic if you use the altdq megafunction to generate the dq signals. connect this port to the combout port in the altdqs megafunction. (6) on the top and bottom i/o banks, the cl ock to this register can be an inverted register a?s clock or a separate clock (inverted or non-inverted). on the side i/o banks, you can only use the inverted register a?s clock for this port. d q dff d q la tch ena d q dff input re g ister a i input re g ister b i latch c dq dff dq dff 0 1 dq dff tri dq pin oe re g ister a oe output re g ister a o output re g ister b o lo g ic array latch dataout_l dataout_h outclock (3) datain_h datain_l oe inclock (from dqs bus) ne g _re g _out i (5) (4) (2) (6)
altera corporation 9?35 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 9?16. dqs configur ation in stratix ii or stratix ii gx ioe note (1) notes to figure 9?16 : (1) you can use the altdqs megafunction to generate th e dqs signals. you should, however, use altera?s memory controller ip tool bench to generate the data path for your memory interface. the signal names used here match with quartus ii software naming convention. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before oe register a oe during compilation. in rldram ii and qdrii sram, the oe signal is always disabled. (3) the select line can be chosen in the altdqs megafunction. (4) the datain_l and datain_h pins are usually connected to ground and v cc , respectively. (5) dqs postamble circuitry and handling is not shown in this diagram. for more information, see an 327: interfacing ddr sdram with stratix ii devices and an 328: interfacing ddr2 sdram with stratix ii devices . (6) dqs logic blocks are only available with dqs and dqsn pins. (7) you must invert this signal before it reaches the dq ioe. this signal is automatically inverted if you use the altdq megafunction to generate the dq signals. connect this port to the inclock port in the altdq megafunction. dq dff dq dff 0 1 output re g ister b o output re g ister a o oe re g ister b oe oe re g ister a oe dq dff dq dff or2 tri dqs pin (5 ) lo g ic array system clock datain_l (4) datain_h (4) oe (3) combout (7) (2) 0 1
9?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx ddr memory support overview for interfaces to ddr sdram, ddr 2 sdram, and rldram ii, the stratix ii or stratix ii gx ddr ioe structure requires you to invert the incoming dqs signal to ensure proper data transfer. this is not required for qdrii sram interfaces if the cq signal is wired to the dqs pin and the cq# signal is wired to the dqsn pin. the altdq megafunction, by default, adds the inverter to the inclock port when it generates dq blocks. the megafunction also includes an option to remove the inverter for qdrii sram interfaces. as shown in figure 9?13 , the inclock signal?s rising edge clocks the a i register, inclock signal?s falling edge clocks the b i register, and latch c i is opened when inclock is 1. in a ddr memory read operation, the last data coincides with dqs being low. if you do not invert the dqs pin, you will not get this last data as the latch does not open until the next ri sing edge of the dqs signal. figure 9?17 shows waveforms of the circuit shown in figure 9?15 . the first set of waveforms in figure 9?17 shows the edge-aligned relationship between the dq and dqs signals at the stratix ii or stratix ii gx device pins. the second set of waveforms in figure 9?17 shows what happens if the shifted dq s signal is not inverted; the last data, d n , does not get latched into the logi c array as dqs goes to tristate after the read postamble time. the third set of waveforms in figure 9?17 shows a proper read operation with the dqs signal inverted after the 90 shift; the last data, d n , does get latched. in this case the outputs of register a i and latch c i , which correspond to dataout_h and dataout_l ports, are now switched because of the dqs inversion. register a i , register b i , and latch c i refer to the nomenclature in figure 9?15 .
altera corporation 9?37 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 9?17. dq captures with non- inverted and inverted shifted dqs dq at the pin dqs shifted by 90? output of register a 1 (dataout_h) output of latch c 1 (dataout_l) output of register b 1 dqs inverted and shifted by 90? output of register a 1 (dataout_h) output of latch c 1 (dataout_l) output of register b 1 dqs at the pin shifted dqs signal is not inverted shifted dqs signal is inverted dq & dqs signals d n ? 1 d n ? 2 d n ? 2 d n ? 2 d n ? 1 d n d n d n ? 3 d n ? 1 d n ? 1 d n
9?38 altera corporation stratix ii gx device handbook, volume 2 october 2007 enhancements in stratix ii and stratix ii gx devices pll when using the stratix ii and stratix ii gx top and bottom i/o banks (i/o banks 3, 4, 7, or 8) to interface with a ddr memory, at least one pll with two outputs is needed to generate the system clock and the write clock. the system clock generates the dqs write signals, commands, and addresses. the write clock is either shifted by ?90 or 90 from the system clock and is used to generate the dq signals during writes. for ddr and ddr2 sdram interfaces above 200 mhz, altera also recommends a second read pll to help ease resynchronization. when using the stratix ii and stratix ii g x side i/o banks 1, 2, 5, or 6 to interface with ddr sdram devices, two plls may be needed per i/o bank for best performance. since the side i/o banks do not have dedicated circuitry, one pll captur es data from the ddr sdram and another pll generates the write sign als, commands, and addresses to the ddr sdram device. stratix ii and stratix ii gx side i/o banks can support ddr sdram up to 150 mhz. enhancements in stratix ii and stratix ii gx devices stratix ii and stratix ii gx external memory interfaces support differs from stratix external memory interf aces support in the following ways: a pll output can now be used as the input reference clock to the dll. the shifted dqs signal can now go into the logic array. the dll in stratix ii and stratix ii gx devices has more phase-shift options than in stratix devices. it also has the option to add phase offset settings. stratix ii and stratix ii gx devices have dqs logic blocks with each dqs pin that helps with fine tuning the phase shift. the dqs delay settings can be routed from the dll into the logic array. you can also bypass the dll and send the dqs delay settings from the logic array to the dqs logic block. stratix ii and stratix ii gx devices support dqsn pins. the dqs/dq groups now support 4, 9, 18, and 36 bus modes. the dqs pins have been enhanced with the dqs postamble circuitry. conclusion stratix ii and stratix ii gx devices support sdr sdram, ddr sdram, ddr2 sdram, rldram ii, and qd rii sram external memories. stratix ii and stratix ii gx devices feature high-speed interfaces that transfer data between external me mory devices at up to 300 mhz/600 mbps. dqs phase-shift circuitry an d dqs logic blocks within the stratix ii and stratix ii gx devices allo w you to fine-tune the phase shifts for the input clocks or strobes to pr operly align clock edges as needed to capture data.
altera corporation 9?39 october 2007 stratix ii gx device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices referenced documents this chapter references the following documents: an 325: interfacing rldram ii with stratix ii & stratix gx devices an 326: interfacing qdrii & qdrii+ sr am with stratix i i, stratix, & stratix gx devices an 327: interfacing ddr sdra m with stratix ii devices an 328: interfacing ddr2 sd ram with stratix ii devices dc & switching characterist ics of stratix iii devices chapter in volume 2 of the stratix iii device handbook document revision history table 9?11 shows the revision history for this chapter. table 9?11. document revision history date and document version changes made summary of changes october 2007, v4.5 added the ?referenced documents? section. ? minor text edits. no change for the stratix ii gx device handbook only: formerly chapter 8. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 updated the ?phase offset control? section. ? updated figure 9?2 .? updated ta b l e 9 ? 1 .? added table 9?4 and table 9?6 .? updated note (1) to figure 9?10 .? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 7. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005 v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ?
9?40 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history
altera corporation section iv?1 preliminary section iv. i/o standards this section provides information on stratix ? ii gx single-ended, voltage-referenced, and diff erential i/o standards. this section contains the following chapters: chapter 10, selectable i/o standards in stratix ii and stratix ii gx devices chapter 11, high-speed differenti al i/o interfaces with dpa in stratix ii & stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section iv?2 altera corporation preliminary i/o standards stratix ii gx device handbook, volume 2
altera corporation 10?1 october 2007 10. selectable i/o standards in stratix ii and stratix ii gx devices introduction this chapter provides guidelines for using industry i/o standards in stratix ? ii and stratix ii gx devices, including: i/o features i/o standards external memory interfaces i/o banks design considerations stratix ii and stratix ii gx i/o features stratix ii and the stratix ii gx devices contain an abundance of adaptive logic modules (alms), embedded memory, high-bandwidth digital signal processing (dsp) blocks, and extensive routing resources, all of which can operate at very high core speed. stratix ii and stratix ii gx devices i /o structure is designed to ensure that these internal capabilities are fully utilized. there are numerous i/o features to assist in high-speed data transfer into and out of the device including: single-ended, non-voltage-referenc ed and voltage-referenced i/o standards high-speed differential i/o standards featuring serializer/deserializer (serdes), dynamic phase alignment (dpa), capable of 1 gigabit per second (gbps) performance for low-voltage differential signaling (lvds), hy pertransport technology, hstl, sstl, and lvpecl 1 hstl and sstl i/o standards are used only for pll clock inputs and outputs in diff erential mode. lvpecl is supported on clock input and outputs of the top and bottom i/o banks. double data rate (ddr) i/o pins programmable output drive streng th for voltage-referenced and non-voltage-referenced si ngle-ended i/o standards programmable bus-hold programmable pull-up resistor open-drain output on-chip series termination on-chip parallel termination sii52004-4.6
10?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support on-chip differential termination peripheral component interco nnect (pci) clamping diode hot socketing f for a detailed description of each i/o feature, refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook. stratix ii and stratix ii gx i/o standards support stratix ii and stratix ii gx devices suppo rt a wide range of industry i/o standards. table 10?1 shows which i/o standards stratix ii devices support as well as typical applications. table 10?1. stratix ii and st ratix ii gx i/o standard applications (part 1 of 2) i/o standard application lvttl general purpose lvcmos general purpose 2.5 v general purpose 1.8 v general purpose 1.5 v general purpose 3.3-v pci pc and embedded system 3.3-v pci-x pc and embedded system sstl-2 class i ddr sdram sstl-2 class ii ddr sdram sstl-18 class i ddr2 sdram sstl-18 class ii ddr2 sdram 1.8-v hstl class i qdrii sram/rldram ii/sram 1.8-v hstl class ii qdrii sram/rldram ii/sram 1.5-v hstl class i qdrii sram/sram 1.5-v hstl class ii qdrii sram/sram 1.2-v hstl general purpose differential sstl-2 class i ddr sdram differential sstl-2 class ii ddr sdram differential sstl-18 class i ddr2 sdram differential sstl-18 class ii ddr2 sdram 1.8-v differential hstl class i clock interfaces 1.8-v differential hstl class ii clock interfaces
altera corporation 10?3 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices single-ended i/o standards in non-voltage-referenced single-ended i/o standards, the voltage at the input must be above a set voltage to be considered ?on? (high, or logic value 1) or below another voltage to be considered ?off? (low, or logic value 0). voltages between the limits are undefined logically, and may fall into either a logic value 0 or 1. the non-voltage-referenced single-ended i/o standards supported by stratix ii and stratix ii gx devices are: low-voltage transistor-transistor logic (lvttl) low-voltage complementary metal-oxide semiconductor (lvcmos) 1.5 v 1.8 v 2.5 v 3.3-v pci 3.3-v pci-x voltage-referenced, single-ended i/o standards provide faster data rates. these standards use a constant reference voltage at the input levels. the incoming signals are compared with this constant voltage and the difference between the two defines ?on? and ?off? states. 1 stratix ii and stratix ii gx devices support stub series terminated logic (sstl) and high-speed transceiver logic (hstl) voltage-referenced i/o standards. lvttl the lvttl standard is formulated under eia/jedec standard, jesd8-b (revision of jesd8-a): interface standard for nominal 3-v/3.3-v supply digital integrated circuits. the standard defines dc interface parameters for di gital circuits operating from a 3.0- or 3.3-v power supply and driving or being driven by lvttl-compatible devices. th e 3.3-v lvttl standard is a 1.5-v differential hstl class i clock interfaces 1.5-v differential hstl class ii clock interfaces lvds high-speed communications hypertransport? technology pcb interfaces differential lvpecl video graphics and clock distribution table 10?1. stratix ii and st ratix ii gx i/o standard applications (part 2 of 2) i/o standard application
10?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support general-purpose, single-ended standard used for 3.3-v applications. this i/o standard does not requir e input reference voltages (v ref ) or termination voltages (v tt ). 1 stratix ii and stratix ii gx devices support both input and output levels for 3.3-v lvttl operation. stratix ii stratix ii gx devices support a v ccio voltage level of 3.3 v 5% as specified as the narrow rang e for the voltage supply by the eia/jedec standard. lvcmos the lvcmos standard is formulated under eia/jedec standard, jesd8-b (revision of jesd8-a): interface standard for nominal 3-v/3.3-v supply digital integrated circuits. the standard defines dc interface parameters for di gital circuits operating from a 3.0- or 3.3-v power supply and driving or being driven by lvcmos-compatible devices. the 3.3-v lvcmos i/o standard is a general-purpose, single-ended stan dard used for 3.3-v applications. while lvcmos has its own output specification, it specifies the same input voltage requiremen ts as lvttl. these i/o standards do not require v ref or v tt . 1 stratix ii and stratix ii gx devices support both input and output levels for 3.3-v lvcmos operation. stratix ii and stratix ii gx devices support a v ccio voltage level of 3.3 v 5% as specified as the narrow ra nge for the voltage supply by the eia/jedec standard. 2.5 v the 2.5-v i/o standard is formul ated under eia/jedec standard, eia/jesd8-5: 2.5-v 0.2-v (norma l range), and 1.8-v ? 2.7-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuit. the standard defines the dc inte rface parameters for high-speed, low-voltage, non-terminated digital circuits driving or being driven by other 2.5-v devices. this standard is a general-purpose, single-ended standard used for 2.5-v applications. it does not require the use of a v ref or a v tt .
altera corporation 10?5 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices 1 stratix ii and stratix ii gx devices support both input and output levels for 2.5-v operation with v ccio voltage level support of 2.5 v 5%, which is narrower than defined in the normal range of the eia/jedec standard. 1.8 v the 1.8-v i/o standard is formul ated under eia/jedec standard, eia/jesd8-7: 1.8-v 0.15-v (normal range), and 1.2-v ? 1.95-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuit. the standard defines the dc inte rface parameters for high-speed, low-voltage, non-terminated digital circuits driving or being driven by other 1.8-v devices. this standard is a general-purpose, single-ended standard used for 1.8-v applications. it does not require the use of a v ref or a v tt . 1 stratix ii and stratix ii gx devices support both input and output levels for 1.8-v operation with v ccio voltage level support of 1.8 v 5%, which is narrower than defined in the normal range of the eia/jedec standard. 1.5 v the 1.5-v i/o standard is formul ated under eia/jedec standard, jesd8-11: 1.5-v 0.1-v (normal range) and 0.9-v ? 1.6-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuit. the standard defines the dc inte rface parameters for high-speed, low-voltage, non-terminated digital circuits driving or being driven by other 1.5-v devices. this standard is a general-purpose, single-ended standard used for 1.5-v applications. it does not require the use of a v ref or a v tt . 1 stratix ii and stratix ii gx devices support both input and output levels for 1.5-v operation v ccio voltage level support of 1.5 v 5%, which is narrower th an defined in the normal range of the eia/jedec standard. 3.3-v pci the 3.3-v pci i/o standard is formulated under pci local bus specification revision 2.2 developed by the pci special interest group (sig).
10?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support the pci local bus specification is used for applications that interface to the pci local bus, which provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. the conventional pci specification revision 2.2 define s the pci hardware environment including the protocol, electrical, mechanical, and configuration specifications for the pci devices an d expansion boards. this standard requires 3.3-v v ccio. stratix ii and stratix ii gx devices are fully compliant with the 3.3-v pci local bus specification revision 2.2 and meet 64-bit/66-mhz operating frequency and timing requirements. 1 the 3.3-v pci standard does not require input reference voltages or board terminations. stratix ii and stratix ii gx devices support both input and output levels. 3.3-v pci-x the 3.3-v pci-x i/o standard is formulated under pci-x local bus specification revision 1.0a developed by the pci sig. the pci-x 1.0 standard is used for a pplications that interface to the pci local bus. the standard enables the design of systems and devices that operate at clock speeds up to 133 mhz, or 1 gbps for a 64-bit bus. the pci-x 1.0 protocol enhancements enab le devices to operate much more efficiently, providing more usable bandwidth at any clock frequency. by using the pci-x 1.0 standard, you can design devices to meet pci-x 1.0 requirements and operate as conven tional 33- and 66-mhz pci devices when installed in those systems. this standard requires 3.3-v v ccio . stratix ii and stratix ii gx devices are fully compliant with the 3.3-v pci-x specification revision 1.0a and meet the 133-mhz operating frequency and timing requirements. the 3.3-v pci-x standard does not require input reference voltages or board terminations. 1 stratix ii and stratix ii gx devices support both input and output levels operation. sstl-2 class i and sstl-2 class ii the 2.5-v sstl-2 standard is fo rmulated under jedec standard, jesd8-9a: stub series terminat ed logic for 2.5-v (sstl_2). the sstl-2 i/o standard is a 2.5-v memory bus standard used for applications such as high-speed ddr sdram interfaces. this standard defines the input and output specificat ions for devices that operate in the sstl-2 logic switching range of 0.0 to 2.5 v. this standard improves
altera corporation 10?7 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices operation in conditions where a bus must be isolated from large stubs. sstl-2 requires a 1.25-v v ref and a 1.25-v v tt to which the series and termination resistors are connected ( figures 10?1 and 10?2 ). 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 10?1. 2.5-v sstl class i termination figure 10?2. 2.5-v sstl class ii termination sstl-18 class i and sstl-18 class ii the 1.8-v sstl-18 standard is fo rmulated under jedec standard, jesd8-15: stub series terminat ed logic for 1.8-v (sstl_18). the sstl-18 i/o standard is a 1.8- v memory bus standard used for applications such as high-speed ddr 2 sdram interfaces. this standard is similar to sstl-2 and defines input and output specifications for devices that are designed to operate in the sstl-18 logic switching range 0.0 to 1.8 v. sstl-18 requires a 0.9-v v ref and a 0.9-v v tt to which the series and termination resistors are connected. there are no class definitions for the sstl-18 standard in the jedec specification. the specification of this i/o standard is based on an environment that consists of both series and parallel terminating resistors. altera provides solutions to two derived applications in jedec specification, and names them class i and class ii to be consistent with other sstl standards. figures 10?3 and 10?4 show sstl-18 class i and ii termination, respectively. ou tp u t bu ffer in p u t bu ffe r v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v output buffer input buffe r v tt = 1.25 v 50 v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v
10?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 10?3. 1.8-v sstl class i termination figure 10?4. 1.8-v sstl class ii termination 1.8-v hstl class i and 1.8-v hstl class ii the hstl standard is a techno logy-independent i/o standard developed by jedec to provide voltage scalability. it is used for applications designed to operate in th e 0.0- to 1.8-v hstl logic switching range such as quad data rate (qdr) memory clock interfaces. although jedec specifies a maximum v ccio value of 1.6 v, there are various memory chip vendors with hstl standards that require a v ccio of 1.8 v. stratix ii and stratix ii gx devices support interfaces to chips with v ccio of 1.8 v for hstl. figures 10?5 and 10?6 show the nominal v ref and v tt required to track the higher value of v ccio . the value of v ref is selected to provide optimum noise margin in the system. 1 stratix ii and stratix ii gx devices support both input and output levels operation. output buffer input buffe r v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v output buffer input buffe r v tt = 0.9 v 50 v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v
altera corporation 10?9 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figure 10?5. 1.8-v hstl class i termination figure 10?6. 1.8-v hstl class ii termination 1.5-v hstl class i and 1.5-v hstl class ii the 1.5-v hstl standard is for mulated under eia/jedec standard, eia/jesd8-6: a 1.5-v output buff er supply voltage based interface standard for digital integrated circuits. the 1.5-v hstl i/o standard is used for applications designed to operate in the 0.0- to 1.5-v hstl logic nomi nal switching range. this standard defines single-ended input and output specifications for all hstl-compliant digital integrated ci rcuits. the 1.5-v hstl i/o standard in stratix ii and stratix ii gx devices are compatible with the 1.8-v hstl i/o standard in apex? 20ke, ap ex 20kc, and in stratix ii and stratix ii gx devices themselves beca use the input and output voltage thresholds are compatible ( figures 10?7 and 10?8 ). 1 stratix ii and stratix ii gx devices support both input and output levels with v ref and v tt . output buffer input buffe r v tt = 0.9 v 50 z = 50 v ref = 0.9 v output buffer input buffe r v tt = 0.9 v 50 z = 50 v ref = 0.9 v v tt = 0.9 v 50
10?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support figure 10?7. 1.5-v hstl class i termination figure 10?8. 1.5-v hstl class ii termination 1.2-v hstl although there is no eia/jedec stan dard available for the 1.2-v hstl standard, altera supports it for applications that operate in the 0.0 to 1.2-v hstl logic nominal switching ra nge. 1.2-v hstl can be terminated through series or parallel on-chip termination (oct). figure 10?9 shows the termination scheme. figure 10?9. 1.2-v hstl termination differential i/o standards differential i/o standards are used to achieve even faster data rates with higher noise immunity. apart from lvds, lvpecl, and hypertransport technology, stratix ii and stratix ii gx devices also support differential versions of sstl and hstl standards. output buffer input buffe r v tt = 0.75 v 50 z = 50 v ref = 0.75 v output buffer input buffe r v tt = 0.75 v 50 v tt = 0.75 v 50 z = 50 v ref = 0.75 v ou tp u t bu ffer in p u t bu ffe r z = 50 v ref = 0.6 v oct
altera corporation 10?11 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices f for detailed information on differential i/o standards, refer to the high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . differential sstl-2 class i and differential sstl-2 class ii the 2.5-v differential sstl-2 stan dard is formulated under jedec standard, jesd8-9a: stub series te rminated logic for 2.5-v (sstl_2). this i/o standard is a 2.5-v standa rd used for applications such as high-speed ddr sdram clock interfaces. this standard supports differential signals in systems using the sstl-2 standard and supplements the sstl-2 standard for differential clocks. stratix ii and stratix ii gx devices support both input and output levels. figures 10?10 and 10?11 shows details on differ ential sstl-2 termination. 1 stratix ii and stratix ii gx devices support differential sstl-2 i/o standards in pseudo-differential mode, which is implemented by using two sstl-2 single-ended buffers. the quartus ? ii software only supports pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software do es not support pseudo-differential sstl-2 i/o standards on the left an d right i/o banks, you can implement these standards at these banks. you ne ed to create two pins in the designs and configure the pins with single-e nded sstl-2 standards. however, this is limited only to pins that su pport the differential pin-pair i/o function and is dependent on the si ngle-ended sstl-2 standards support at these banks.
10?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support figure 10?10. differential sstl- 2 class i termination figure 10?11. differential sstl- 2 class ii termination differential sstl-18 class i and differential sstl-18 class ii the 1.8-v differential sstl-18 stan dard is formulated under jedec standard, jesd8-15: stub series te rminated logic for 1.8-v (sstl_18). the differential sstl- 18 i/o standard is a 1. 8-v standard used for applications such as high-speed ddr 2 sdram interfaces. this standard supports differential signals in syst ems using the sstl-18 standard and supplements the sstl-18 standard for differential clocks. 1 stratix ii and stratix ii gx devices support both input and output levels operation. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 25 25 differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 50 50 v tt = 1.25 v v tt = 1.25 v 25 25
altera corporation 10?13 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figures 10?12 and 10?13 shows details on differential sstl-18 termination. stratix ii and stratix ii g x devices support differential sstl- 18 i/o standards in pseudo-differential mode, which is implemented by using two sstl-18 single-ended buffers. the quartus ii software only support s pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software do es not support pseudo-differential sstl-18 i/o standards on the left and right i/o banks, you can implement these standards at these bank s. you need to create two pins in the designs and configure the pins wi th single-ended sstl-18 standards. however, this is limited only to pins that support the differential pin-pair i/o function and is dependent on the single-ended sstl-18 standards support at these banks. figure 10?12. differential sstl- 18 class i termination differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 25 25
10?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support figure 10?13. differential sstl- 18 class ii termination 1.8-v differential hstl class i and 1.8-v differential hstl class ii the 1.8-v differential hstl specification is the same as the 1.8-v single-ended hstl specification. it is used for applications designed to operate in the 0.0- to 1.8-v hstl logic switching range such as qdr memory clock interfaces. stratix ii and stratix ii gx devices support both input and output levels operation. figures 10?14 and 10?15 show details on 1.8-v differential hstl termination. stratix ii and stratix ii gx devices support 1.8-v differential hstl i/o standards in pseudo-differential mode, which is implemented by using two 1.8-v hstl sing le-ended buffers. the quartus ii software only support s pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software does not support 1.8-v pseudo-differential hstl i/o standards on left/right i/o banks, you can implement these standards at these bank s. you need to create two pins in the designs and configure the pins with single-ended 1.8-v hstl standards. however, this is limited only to pins that support the differential pin-pair i/o function an d is dependent on the single-ended 1.8-v hstl standards support at these banks. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 50 50 v tt = 0.9 v v tt = 0.9 v 25 25
altera corporation 10?15 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figure 10?14. 1.8-v differential hstl class i termination figure 10?15. 1.8-v differential hstl class ii termination 1.5-v differential hstl class i and 1.5-v differential hstl class ii the 1.5-v differential hstl standa rd is formulated under eia/jedec standard, eia/jesd8-6: a 1.5-v output buffer supply voltage based interface standard for digi tal integrated circuits. the 1.5-v differential hstl specification is the same as the 1.5-v single-ended hstl specification. it is used for applications designed to operate in the 0.0- to 1.5-v hstl logic switching range, such as qdr memory clock interfaces. stratix ii and stratix ii gx devices support both input and output levels operation. figures 10?16 and 10?17 show details on the 1.5-v differential hstl termination. stratix ii and stratix ii gx devices support 1.5-v differential hstl i/o standards in pseudo-differential mode, which is implemented by using two 1.5-v hstl sing le-ended buffers. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 50 50 v tt = 0.9 v v tt = 0.9 v
10?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support the quartus ii software only support s pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software does not support 1.5-v pseudo-differential hstl i/o standards on left/right i/o banks, you can implement these standards at these bank s. you need to create two pins in the designs and configure the pins with single-ended 1.5-v hstl standards. however, this is limited only to pins that support the differential pin-pair i/o function an d is dependent on the single-ended 1.8-v hstl standards support at these banks. figure 10?16. 1.5-v differential hstl class i termination differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v
altera corporation 10?17 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figure 10?17. 1.5-v differential hstl class ii termination lvds the lvds standard is formulated under ansi/tia/eia standard, ansi/tia/eia-644: electrical ch aracteristics of low voltage differential signalin g interface circuits. the lvds i/o standard is a differen tial high-speed, low-voltage swing, low-power, general-purpose i/o interface standard. in stratix ii devices, the lvds i/o standard requires a 2.5-v v ccio level for the side i/o pins in banks 1, 2, 5, and 6. the to p and bottom banks have different v ccio requirements for the lvds i/o stan dard. the lvds clock i/o pins in banks 9 through 12 require a 3.3-v v ccio level. within these banks, the pll[5,6,11,12]_out[1,2] pins support output only lvds operations. the pll[5,6,11,12]_fb/out2 pins support lvds input or output operations but cannot be configured for bidirectional lvds operations. the lvds clock input pins in banks 4, 5, 7, and 8 use v ccint and have no dependency on the v ccio voltage level. this standard is used in applications requiring high-ba ndwidth data transfer, backplane drivers, and clock distribution . the ansi/tia/eia-644 standard specifies lvds transmitters and receivers capable of operating at recommended maximum data signalin g rates of 655 megabit per second (mbps). however, devices can operat e at slower speeds if needed, and there is a theoretical maximum of 1.923 gbps. stratix ii and stratix ii gx devices are capable of running at a ma ximum data rate of 1 gbps and still meet the ansi/tia /eia-644 standard. because of the low-voltage swing of the lvds i/o standard, the electromagnetic interfer ence (emi) effects are much smaller than complementary metal-oxide semiconductor (cmos), transistor-to-transistor logic (ttl) , and positive (or psuedo) emitter coupled logic (pecl). this low emi makes lvds ideal for applications differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v 50 50 v tt = 0.75 v v tt = 0.75 v
10?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii g x i/o standards support with low emi requirements or nois e immunity requirements. the lvds standard does not require an input reference voltage. however, it does require a 100- termination resistor between the two signals at the input buffer. stratixii and stratixiigx devices provide an optional 100- differential lvds termination resi stor in the device using on-chip differential termination. stratix ii and stratix ii gx devices support both input and output levels operation. differential lvpecl the low-voltage positive (or pseudo) emitter coupled logic (lvpecl) standard is a differential interf ace standard requiring a 3.3-v v ccio . the standard is used in applications involving video graphics, telecommunications, data communicati ons, and clock distribution. the high-speed, low-voltage swing lvpecl i/o standard uses a positive power supply and is similar to lvds. however, lvpecl has a larger differential output voltage swing th an lvds. the lvpecl standard does not require an input reference voltage, but it does require a 100- termination resistor between the two signals at the input buffer. figures 10?18 and 10?19 show two alternate termination schemes for lvpecl. 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 10?18. lvpecl dc coupled termination figure 10?19. lvpecl ac coupled termination output buffer input buffer 100 z = 50 z = 50 output buffer input buffe r 100 z = 50 z = 50 v ccio v ccio r2 r2 r1 r1 10 to 100 nf 10 to 100 nf
altera corporation 10?19 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices hypertransport technology the hypertransport standard is formulated by the hypertransport consortium. the hypertransport i/o standard is a differential high-speed, high-performance i/o interface stan dard requiring a 2.5- or 3.3-v v ccio . this standard is used in applications such as high-performance networking, telecommunications, embedded systems, consumer electronics, and internet connectivi ty devices. the hypertransport i/o standard is a point-to-point standard in which each hypertransport bus consists of two point-to-point unidirecti onal links. each link is 2 to 32 bits. the hypertransport standard does not require an input reference voltage. however, it does require a 100- termination resistor between the two signals at the input buffer. figure 10?20 shows hypertransport termination. stratix ii and stratix ii gx devices include an optional 100- differential hypertransport terminat ion resistor in the device using on-chip differential termination. 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 10?20. hypertransport termination stratix ii and stratix ii gx external memory interface the increasing demand for higher-per formance data processing systems often requires memory-intensive applications. stratix ii and stratix ii gx devices can interface with many types of external memory. f refer to the external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the external memory interfaces in strati x ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on the external memory interface support in st ratix ii or stratix ii gx devices. output buffer input buffer 100 z = 50 z = 50
10?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx i/o banks stratix ii and stratix ii gx i/o banks stratix ii devices have eight gene ral i/o banks and four enhanced phase-locked loop (pll) exte rnal clock output banks ( figure 10?21 ) . i/o banks 1, 2, 5, and 6 are on the left or right sides of the device and i/o banks 3, 4, and 7 through 12 are at the top or bottom of the device. figure 10?21. stratix ii i/o banks notes (1) , (2) , (3) , (4) , (5) , (6) , (7) notes to figure 10?21 : (1) figure 10?21 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. refer to the pin list and quartus ii software for exact locations. (2) depending on the size of the device, differe nt device members have different numbers of v ref groups. (3) banks 9 through 12 are enhanced pll external cloc k output banks. these pll banks utilize the adjacent v ref group when voltage-referenced standards ar e implemented. for example, if an sstl input is implemented in pll bank 10, the voltage level at vrefb7 is the reference voltage level for the sstl input. (4) differential hstl and differential sstl standards are available for bidirectional operations on dqs pin and input-only operations on pll clock input pins; lvds, lvpecl, and hypertransport standards are available for input-only operations on pll clock input pins. refer to the ?differential i/o standards? on page 10?10 for more details. (5) quartus ii software does not support differential sstl an d differential hstl standard s at left/right i/o banks. refer to the ?differential i/o standards? on page 10?10 if you need to implement these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. (7) plls 7, 8, 9 10, 11, and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. bank 3 bank 4 bank 11 bank 9 pll11 pll5 pll7 pll1 pll2 pll4 pll3 pll10 i/o banks 7, 8, 10 & 12 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. i/o banks 3, 4, 9 & 11 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 bank 8 bank 7 bank 12 bank 10 pll12 pll6 pll8 pll9 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 vref3b 2 vref2b2 vref1b2 vref0b2 bank 2 vref3b1 vref2b1 vref1b1 vref0b1 bank 1 vref1b 5 vref2b5 vref3b5 vref4b5 bank 5 vref1b6 vref2b6 vref3b6 vref4b6 bank 6 vref4b2 vref0b5 vref4b1 vref0b6 dqs4t dqs3t dqs2t dqs1t dqs0t dqs4b dqs3b dqs2b dqs1b dqs0b dqs8b dqs7b dqs6b dqs5b dqs8t dqs7t dqs6t dqs5t this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. i/o banks 1, 2, 5 & 6 support lvttl, lvcmos, 2.5-v, 1.8-v, 1.5-v, sstl-2, sstl-18 class i, hstl-18 class i, hstl-15 class i, lvds, and hypertransport standards for input and output operations. hstl-18 class ii, hstl-15-class ii, sstl-18 class ii standards are only supported for input operations.
altera corporation 10?21 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices stratix ii gx devices have 6 general i/o banks and 4 enhanced phase-locked loop (pll) exte rnal clock output banks ( figure 10?22 ). i/o banks 9 through 12 are enhanced pll ex ternal clock output banks located on the top and bottom of the device. figure 10?22. stratix ii gx i/o banks notes (1) , (2) , (3) , (4) notes to figure 10?22 : (1) figure 10?22 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. it is a graphical representation only. (2) depending on size of the de vice, different device members have different number of v ref groups. refer to the pin list and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) horizontal i/o banks feature transceiver and dpa circuitry for high speed differential i/o standards. refer to the high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook , or the stratix ii gx transceiver user guide (volume 1) of the stratix ii gx device handbook for more information on differential i/o standards. (5) quartus ii software does not support differential sstl an d differential hstl standard s at left/right i/o banks. refer to the ?differential i/o standards? on page 10?10 if you need to implement these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2sgx60c/d/e, ep2sgx90e/f, and ep2sgx130g. (7) plls 7,8,11, and 12 are available only in ep2sgx60c/d/e, ep2sgxe/f, and ep2sgx130g. i/o b a nk s 3, 4, 9 & 11 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion. all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion at i/o ba nk s 9 & 1 0 . i/o b a nk s 7, 8, 1 0 a n d 12 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion. all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s at i/o ba nk 1 0 a n d 12. i/o b a nk s 1, & 2, s u pp o rt lvttl, lv c mos, 2.5 -v, 1.9 -]v, 1.5 -v, sstl -2, sstl-18 c l ass i, lv d s, pse u d o- d i ffere n t i a l sstl -2, pse u d o- d i ffere n t i a l sstl-18 c l ass i sta n dards , hstl-18 c l ass i, a n d hstl-15 c l ass i f o r b o t h in p u t a n d ou tp u t o perat ion s . hstl, sstl-18 c l ass ii, pse u d o- d i ffere n t i a l hstl, pse u d o- d i ffere n t i a l sstl-18 c l ass ii, hstl-15 c l ass ii, a n d hstl-18 c l ass ii sta n dards are only s u pp o rted f o r in p u t o perat ion s . (4) dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 pll11 vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 bank 9 bank 11 vref0b2 vref1b2 vref2b2 pll1 pll2 bank 1 bank 2 bank 3 bank 4 bank 8 bank 7 pll7 pll8 pll12 pll5 thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) pll6 bank 12 bank 10 vref0b1 vref1b1 vref2b1 vref3b1 vref4b1 bank 15 bank 16 bank 14 bank 13 bank 17 dqsx8 dqsx8 dqsx8 dqsx8 vref4b2 vref3b2
10?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx i/o banks programmable i/o standards stratix ii and stratix ii gx device programmable i/o standards deliver high-speed and high-performance so lutions in many complex design systems. this section discusses the i/o standard support in the i/o banks of stratix ii and stratix ii gx devices. regular i/o pins most stratix ii and stratix ii gx devi ce pins are multi-function pins. these pins support regular inputs an d outputs as their primary function, and offer an optional func tion such as dqs, differential pin-pair, or pll external clock outputs. for example, you can configure a multi-function pin in the enhanced pll external cl ock output bank as a pll external clock output when it is not used as a regular i/o pin. 1 i/o pins that reside in pll ba nks 9 through 12 are powered by the vcc_pll < 5, 6, 11, or 12 > _out pins, respectively. the ep2s60f484, ep2s60f780, ep 2s90h484, ep2s90f780, and ep2s130f780 devices do not support plls 11 and 12. therefore, any i/o pins that reside in bank 11 are powered by the vccio3 pin, and any i/o pins that reside in bank 12 are powered by the vccio8 pin. table 10?2 shows the i/o standards supported when a pin is used as a regular i/o pin in the i/o banks of stratix ii and stratix ii gx devices. table 10?2. stratix ii and stratix ii gx regu lar i/o standards support (part 1 of 2) i/o standard general i/o bank enhanced pll external clock output bank (2) 123 45 (1) 6 (1) 789101112 lv t t l v v v v v v v v v v v v lv c m o s v v v v v v v v v v v v 2.5 v v v v v v v v v v v v v 1.8 v v v v v v v v v v v v v 1.5 v vvv vvvvvvv vv 3.3-v pci v v v v v v v v 3.3-v pci-x vv vvvvvv sstl-2 class i v v v v v v v v v v v v sstl-2 class ii vvv vvvvvvv vv
altera corporation 10?23 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices sstl-18 class i v v v v v v v v v v v v sstl-18 class ii (3) (3) vv (3) (3) v v v v v v 1.8-v hstl class i vv v v vv v v v v v v 1.8-v hstl class ii (3) (3) v v (3) (3) v v v v v v 1.5-v hstl class i vv v v vv v v v v v v 1.5-v hstl class ii (3) (3) v v (3) (3) v v v v v v 1.2-v hstl vv v differential sstl-2 class i (4) (4) (5) (5) (4) (4) (5) (5) differential sstl-2 class ii (4) (4) (5) (5) (4) (4) (5) (5) differential sstl-18 class i (4) (4) (5) (5) (4) (4) (5) (5) differential sstl-18 class ii (4) (4) (5) (5) (4) (4) (5) (5) 1.8-v differential hstl class i (4) (4) (5) (5) (4) (4) (5) (5) 1.8-v differential hstl class ii (4) (4) (5) (5) (4) (4) (5) (5) 1.5-v differential hstl class i (4) (4) (5) (5) (4) (4) (5) (5) 1.5-v differential hstl class ii (4) (4) (5) (5) (4) (4) (5) (5) lv d s v v (6) (6) v v (6) (6) vvvv hypertransport technology v v v v differential lvpecl (6) (6) (6) (6) vvvv notes to table 10?2 : (1) this bank is not available in stratix ii gx devices. (2) a mixture of single-ended and differential i/o standard s is not allowed in enhanced pll external clock output bank. (3) this i/o standard is only supported for the input operation in this i/o bank. (4) although the quartus ii software does not support pseu do-differential sstl/hstl i/o standards on the left and right i/o banks, you can implement these standards at these banks. refer to the ?differential i/o standards? on page 10?10 for details. (5) this i/o standard is supported for bo th input and output operations for pins that support the dqs function. refer to the ?differential i/o standards? on page 10?10 for details. (6) this i/o standard is only supported for the input operation for pins that support pll inclk function in this i/o bank. table 10?2. stratix ii and stratix ii gx regu lar i/o standards support (part 2 of 2) i/o standard general i/o bank enhanced pll external clock output bank (2) 123 45 (1) 6 (1) 789101112
10?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx i/o banks clock i/o pins the pll clock i/o pins co nsist of clock inputs ( inclk ), external feedback inputs ( fbin ), and external clock outputs ( extclk ). clock inputs are located at the left and right i/o banks (banks 1, 2, 5, and 6) to support fast plls, and at the top and bottom i/o banks (banks 3, 4, 7, and 8) to support enhanced plls. both exte rnal clock output s and external feedback inputs are located at enhanc ed pll external clock output banks (banks 9, 10, 11, and 12) to support enhanced plls. table 10?3 shows the pll clock i/o support in the i/o banks of stratix ii and stratix ii gx devices. table 10?3. i/o standards suppor ted for stratix ii and strati x ii gx pll pins (part 1 of 2) i/o standard (2) enhanced pll (1) fast pll input output input inclk fbin extclk inclk lv t t l v v v v lv c m o s v v v v 2.5 v v v v v 1.8 v v v v v 1.5 v v v v v 3.3-v pci v v v 3.3-v pci-x v v v sstl-2 class i v v v v sstl-2 class ii v v v v sstl-18 class i v v v v sstl-18 class ii v v v v 1.8-v hstl class i v v v v 1.8-v hstl class ii v v v v 1.5-v hstl class i v v v v 1.5-v hstl class ii v v v v differential sstl-2 class i v v v differential sstl-2 class ii v v v differential sstl-18 class i v v v differential sstl-18 class ii v v v
altera corporation 10?25 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices f for more information, refer to the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the plls in stratix ii & straix ii gx devices chapter in volume 2 of the stratix ii gx device handbook. voltage levels stratix ii device specify a range of allowed voltage levels for supported i/o standards. table 10?4 shows only typical values for input and output v ccio , v ref , as well as the board v tt . 1.8-v differential hstl class i v v v 1.8-v differential hstl class ii v v v 1.5-v differential hstl class i v v v 1.5-v differential hstl class ii v v v lv d s v v v v hypertransport technology v differential lvpecl vv v note to table 10?3 : (1) the enhanced pll external clock output bank does not allow a mixture of both single-ended and differential i/o standards. (2) altera does not support 1.2-v hstl fo r pll input pins on column i/o pins. table 10?3. i/o standards suppor ted for stratix ii and strati x ii gx pll pins (part 2 of 2) i/o standard (2) enhanced pll (1) fast pll input output input inclk fbin extclk inclk table 10?4. stratix ii and stra tix ii gx i/o standards and voltage levels (part 1 of 3) note (1) i/o standard stratix ii and stratix ii gx v ccio (v) v ref (v) v tt (v) input operation o utput operation input termination top and bottom i/o banks left and right i/o banks (3) top and bottom i/o banks left and right i/o banks (3) lvttl 3.3/2.5 3.3/2.5 3.3 3.3 na na lvcmos 3.3/2.5 3.3/2.5 3.3 3.3 na na
10?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 stratix ii and stratix ii gx i/o banks 2.5 v 3.3/2.5 3.3/2.5 2.5 2.5 na na 1.8 v 1.8/1.5 1.8/1.5 1.8 1.8 na na 1.5 v 1.8/1.5 1.8/1.5 1.5 1.5 na na 3.3-v pci 3.3 na 3.3 na na na 3.3-v pci-x 3.3 na 3.3 na na na sstl-2 class i 2.5 2.5 2.5 2.5 1.25 1.25 sstl-2 class ii 2.5 2.5 2.5 2.5 1.25 1.25 sstl-18 class i 1.8 1.8 1.8 1.8 0.90 0.90 sstl-18 class ii 1.8 1.8 1.8 na 0.90 0.90 1.8-v hstl class i 1.8 1.8 1.8 1.8 0.90 0.90 1.8-v hstl class ii 1.8 1.8 1.8 na 0.90 0.90 1.5-v hstl class i 1.5 1.5 1.5 1.5 0.75 0.75 1.5-v hstl class ii 1.5 1.5 1.5 na 0.75 0.75 1.2-v hstl (4) 1.2 na 1.2 na 0.6 na differential sstl-2 class i 2.5 2.5 2.5 2.5 1.25 1.25 differential sstl-2 class ii 2.5 2.5 2.5 2.5 1.25 1.25 differential sstl-18 class i 1.8 1.8 1.8 1.8 0.90 0.90 differential sstl-18 class ii 1.8 1.8 1.8 na 0.90 0.90 1.8-v differential hstl class i 1.8 1.8 1.8 na 0.90 0.90 1.8-v differential hstl class ii 1.8 1.8 1.8 na 0.90 0.90 1.5-v differential hstl class i 1.5 1.5 1.5 na 0.75 0.75 1.5-v differential hstl class ii 1.5 1.5 1.5 na 0.75 0.75 lv d s (2) 3.3/2.5/1.8/1.5 2.5 3.3 2.5 na na table 10?4. stratix ii and stra tix ii gx i/o standards and voltage levels (part 2 of 3) note (1) i/o standard stratix ii and stratix ii gx v ccio (v) v ref (v) v tt (v) input operation o utput operation input termination top and bottom i/o banks left and right i/o banks (3) top and bottom i/o banks left and right i/o banks (3)
altera corporation 10?27 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices f refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook for detailed electrical characteristics of each i/o standard. on-chip termination stratix ii and stratix ii gx devices feature on-chip termination to provide i/o impedance matching and termin ation capabilities. apart from maintaining signal integrity, this feature also minimizes the need for external resistor netw orks, thereby saving board space and reducing costs. stratix ii and stratix ii gx devices su pport on-chip series (r s ) and parallel (r t ) termination for single-ended i/o standards and on-chip differential termination (r d ) for differential i/o standards. this section discusses the on-chip series termination support. f for more information on differential on-chip termination, refer to the high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook. hypertransport technology na 2.5 na 2.5 na na differential lvpecl (2) 3.3/2.5/1.8/1.5 na 3.3 na na na notes to table 10?4 : (1) any input pins with pci-cl amping diode will clamp the v ccio to 3.3 v. (2) lvds and lvpecl output operation in the top and bottom banks is only supported in pll banks 9-12. the v ccio level for differential output operatio n in the pll banks is 3.3 v. the v ccio level for output operation in the left and right i/o banks is 2.5 v. (3) the right i/o bank does not apply to the stratix ii gx. the right i/o bank on stra tix ii gx devices consists of transceivers. (4) 1.2-v hstl is only support ed in i/o banks 4,7, and 8. table 10?4. stratix ii and stra tix ii gx i/o standards and voltage levels (part 3 of 3) note (1) i/o standard stratix ii and stratix ii gx v ccio (v) v ref (v) v tt (v) input operation o utput operation input termination top and bottom i/o banks left and right i/o banks (3) top and bottom i/o banks left and right i/o banks (3)
10?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 on-chip termination the stratix ii and stratix ii gx devices supports i/o driver on-chip series (r s ) and parallel (r t ) termination through drive strength control for single-ended i/os. there are three ways to implement the r s and (r t ) in stratix ii and stratix ii gx devices: r s without calibration for both row i/os and column i/os r s with calibration only for column i/os r t with calibration only for column i/os on-chip series termina tion without calibration stratix ii and stratix ii gx devices support driver impedance matching to provide the i/o driver with controlled output impedance that closely matches the impedance of the transmis sion line. as a re sult, reflections can be significantly reduced. stratix ii and stratix ii gx devices support on-chip series termination for si ngle-ended i/o standards (see figure 10?23 ). the r s shown in figure 10?23 is the intrinsic impedance of transistors. the typical r s values are 25 and 50 . once matching impedance is selected, current drive strength is no longer selectable. 1 on-chip series termination withou t calibration is supported on output pins or on the output function of bidirectional pins. figure 10?23. stratix ii and stratix ii gx on -chip series term ination without calibration stratix ii driver series impedance receiving device v ccio r s r s z o gnd
altera corporation 10?29 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices table 10?5 shows the list of output standards that support on-chip series termination without calibration. to use on-chip termination for the sstl class i standard, users should select the 50- on-chip series terminatio n setting for replacing the external 25- r s (to match the 50- transmission line). for the sstl class ii standard, users should select the 25- on-chip series termination setting (to match the 50- transmission line and the near end 50- pull-up to v tt ). table 10?5. selectable i/o drivers with on-chip series termination without calibration i/o standard on-chip series termination setting row i/o column i/o unit 3.3-v lvttl 50 50 25 25 3.3-v lvcmos 50 50 25 25 2.5-v lvttl 50 50 25 25 2.5-v lvcmos 50 50 25 25 1.8-v lvttl 50 50 25 1.8-v lvcmos 50 50 25 1.5-v lvttl 50 50 1.5-v lvcmos 50 50 sstl-2 class i 50 50 sstl-2 class ii 25 25 sstl-18 class i 50 50 sstl-18 class ii 25 1.8-v hstl class i 50 50 1.8-v hstl class ii 25 1.5-v hstl class i 50 50 1.2-v hstl (1) 50 note to table 10?5 : (1) 1.2-v hstl is only support ed in i/o banks 4,7, and 8.
10?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 on-chip termination f for more information on tolerance sp ecifications for on-chip termination without calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . on-chip series termin ation with calibration stratix ii and stratix ii gx devices su pport on-chip series termination with calibration in column i/os in top and bottom banks. every column i/o buffer consists of a gr oup of transistors in para llel. each transistor can be individually enabled or disabled. the on-chip series termination calibration circuit compares the total impedance of the transistor group to the external 25- or 50- resistors connected to the rup and rdn pins, and dynamically enables or disables th e transistors until they match (as shown in figure 10?24 ). the r s shown in figure 10?24 is the intrinsic impedance of transistors. calibrat ion happens at the end of device configuration. once the calibration ci rcuit finds the correct impedance, it powers down and stops changing th e characteristics of the drivers. 1 on-chip series termination with calibration is supported on output pins or on the output function of bidirectional pins. figure 10?24. stratix ii and stratix ii gx on-chip series termination with calibration stratix ii driver series impedance receiving device v ccio r s r s z o gnd
altera corporation 10?31 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices table 10?6 shows the list of output standards that support on-chip series termination with calibration. on-chip parallel termin ation with calibration stratix ii and stratix ii gx devices su pport on-chip parallel termination with calibration in column i/os in top and bottom banks. every column i/o buffer consists of a gr oup of transistors in para llel. each transistor can be individually enabled or disabled. the on-chip parallel termination calibration circuit compares the total impedance of the transistor group to table 10?6. selectable i/o drivers with on-chip series termination with calibration i/o standard on-chip series termination setting (column i/o) unit 3.3-v lvttl 50 25 3.3-v lvcmos 50 25 2.5-v lvttl 50 25 2.5-v lvcmos 50 25 1.8-v lvttl 50 25 1.8-v lvcmos 50 25 1.5 lvttl 50 1.5 lvcmos 50 sstl-2 class i 50 sstl-2 class ii 25 sstl-18 class i 50 sstl-18 class ii 25 1.8-v hstl class i 50 1.8-v hstl class ii 25 1.5-v hstl class i 50 1.2-v hstl (1) 50 note to table 10?6 : (1) 1.2-v hstl is only support ed in i/o banks 4,7, and 8.
10?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 on-chip termination the external 50- resistors connected to the rup and rdn pins and dynamically enables or disables th e transistors until they match. calibration happens at the end of th e device configuration. once the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. there are two separate sets of calibration circuits in the stratix ii and stratix ii gx devices: one calibration circuit for top banks 3 and 4 one calibration circuit fo r bottom banks 7 and 8 calibration circuits rely on the external pull-up reference resistor (r up ) and pull-down reference resistor (r dn ) to achieve accurate on-chip series and parallel termination. there is one pair of rup and rdn pins in bank 4 for the calibration circuit for top i/o ba nks 3 and 4. similarly, there is one pair of rup and rdn pins in bank 7 for the calibration circuit for bottom i/o banks 7 and 8. two banks share the same calibration circuitry, so they must have the same v ccio voltage if both banks enable on-chip series or parallel termination with calibration. if banks 3 and 4 have different v ccio voltages, only bank 4 can enable on-c hip series or parallel termination with calibration because the rup and rdn pins are located in bank 4. bank 3 still can use on-chip series termination, but without calibration. the same rule applies to banks 7 and 8. table 10?7. selectable i/o drivers with on-chip parallel termination with calibration i/o standard on-chip parallel termination setting (column i/o) unit sstl-2 class i 50 sstl-2 class ii 50 sstl-18 class i 50 sstl-18 class ii 50 1.8-v hstl class i 50 1.8-v hstl class ii 50 1.5-v hstl class i 50 1.5-v hstl class ii 50 1.2-v hstl (1) 50 note to table 10?7 : (1) 1.2-v hstl is only support ed in i/o banks 4,7, and 8.
altera corporation 10?33 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices 1 on-chip parallel termination with calibration is only supported for input pins. pins configured as bidirectional do not support on-chip parallel termination. the rup and rdn pins are dual-purpose i/os , which means they can be used as regular i/os if the calibratio n circuit is not used. when used for calibration, the rup pin is connected to v ccio through an external 25- or 50- resistor for an on-chip se ries termination value of 25 or 50 , respectively. the rdn pin is connected to gnd through an external 25- or 50- resistor for an on-chip se ries termination value of 25 or 50 , respectively. for on-chip pa rallel termination, the rup pin is connected to v ccio through an external 50- resistor, and rdn is connected to gnd through an external 50- resistor. f for more information on tolerance sp ecifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . design considerations while stratix ii and stratix ii gx device s feature various i/o capabilities for high-performance and high-speed system designs, there are several other considerations that require attention to ensure the success of those designs. i/o termination i/o termination requirements for single-ended and differential i/o standards are discussed in this section. single-ended i/o standards although single-ended, non-voltage- referenced i/o standards do not require termination, impedance ma tching is necessary to reduce reflections and improv e signal integrity. voltage-referenced i/o standards require both an input reference voltage, v ref, and a termination voltage, v tt . the reference voltage of the receiving device tracks the terminatio n voltage of the transmitting device. each voltage-referenced i/o standard requires a unique termination setup. for example, a prop er resistive signal termination scheme is critical in sstl standards to produce a reliable ddr memory system with superior noise margin.
10?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 design considerations stratix ii and stratix ii gx on-chip series and parallel termination provides the convenience of no exte rnal components. external pull-up resistors can be used to terminate the voltage-referenced i/o standards such as sstl-2 and hstl. 1 refer to the ?stratix ii and stratix ii gx i/o standards support? on page 10?2 for more information on the termination scheme of various single-ended i/o standards. differential i/o standards differential i/o standards typically require a termination resistor between the two signals at the receiver. the termination resistor must match the differential load impe dance of the bus. stratix ii and stratix ii gx devices provide an option al differential on-chip resistor when using lvds and hypertransport standards. i/o banks restrictions each i/o bank can simultaneously support multiple i/o standards. the following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced i/o standards in stratix ii and stratix ii gx devices. non-voltage-referenced standards each stratix ii and stratix ii gx device i/o bank has its own v ccio pins and supports only one v ccio , either 1.5, 1.8, 2.5, or 3.3 v. an i/o bank can simultaneously support any number of input signals wi th different i/o standard assignments, as shown in table 10?8 . for output signals, a single i/o ba nk supports non-voltage-referenced output signals that are drivin g at the same voltage as v ccio . since an i/o bank can only have one v ccio value, it can only drive out that one value for non-voltage-referenced signals. for example, an i/o bank with a 2.5-v v ccio setting can support 2.5-v standard inputs and outputs and 3.3-v lvcmos inputs (not output or bidirectional pins). table 10?8. acceptable input level s for lvttl and lvcmos (part 1 of 2) bank v ccio (v) acceptable input levels (v) 3.3 2.5 1.8 1.5 3.3 vv (1) 2.5 v v
altera corporation 10?35 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices voltage-referenced standards to accommodate voltage-referenced i/o standards, each stratix ii or stratix ii gx device?s i/o bank supports multiple v ref pins feeding a common v ref bus. the number of available v ref pins increases as device density increases. if these pins are not used as v ref pins, they cannot be used as generic i/o pins. however, each bank can only have a single v ccio voltage level and a single v ref voltage level at a given time. an i/o bank featuring single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same v ref setting. because of performance reasons, volt age-referenced input standards use their own v ccio level as the power source. for example, you can only place 1.5-v hstl input pins in an i/o bank with a 1.5-v v ccio . 1 refer to the ?stratix ii and stratix ii gx i/o banks? on page 10?20 for details on input v ccio for voltage-referenced standards. voltage-referenced bidirectional and output signals must be the same as the i/o bank?s v ccio voltage. for example, you can only place sstl-2 output pins in an i /o bank with a 2.5-v v ccio . 1 refer to the ?i/o placement guid elines? on page 10?36 for details on voltage-referenced i/o standards placement. 1.8 v (2) v (2) v v (1) 1.5 v (2) v (2) v v notes to ta b l e 1 0 ? 8 : (1) because the input signal does not drive to the rail, the input buffer does not completely shut off, and th e i/o current is slightly higher than the default value. (2) these input values overdrive the inpu t buffer, so the pin leakage current is slightly higher than the default value. to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and select the allow lvttl and lvcmos input levels to overdrive input buffer option in the quartus ii software. table 10?8. acceptable input level s for lvttl and lvcmos (part 2 of 2) bank v ccio (v) acceptable input levels (v) 3.3 2.5 1.8 1.5
10?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 design considerations mixing voltage-referenced and no n-voltage-referenced standards an i/o bank can support both non-voltage-referenced and voltage-referenced pins by applying each of the rule sets individually. for example, an i/o bank can support ss tl-18 inputs and 1.8-v inputs and outputs with a 1.8-v v ccio and a 0.9-v v ref . similarly, an i/o bank can support 1.5-v standards, 2.5-v (input s, but not outputs), and hstl i/o standards with a 1.5-v v ccio and 0.75-v v ref . i/o placement guidelines the i/o placement guidelines help to reduce noise issues that may be associated with a design such that stratix ii and stratix ii gx fpgas can maintain an acceptable noise level on the v ccio supply. because stratix ii and stratix ii gx devices require each bank to be powered separately for v ccio , these noise issues have no effect when crossing bank boundaries and, as such, these rules need not be applied. this section provides i/o placemen t guidelines for the programmable i/o standards supported by stratix ii and stratix ii gx devices and includes essential information for designing systems using their devices? selectable i/o capabilities. v ref pin placement restrictions there are at least two dedicated v ref pins per i/o bank to drive the v ref bus. larger stratix ii and stratix ii gx devices have more v ref pins per i/o bank. all v ref pins within one i/o bank are shorted together at device die level. there are limits to the number of pins that a v ref pin can support. for example, each output pin adds some noise to the v ref level and an excessive number of outputs make the level too unstable to be used for incoming signals. restrictions on the placement of si ngle-ended voltage-referenced i/o pads with respect to v ref pins help maintain an acceptable noise level on the v ccio supply and prevent output switching noise from shifting the v ref rail. input pins each v ref pin supports a maximum of 40 input pads.
altera corporation 10?37 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices output pins when a voltage-referenced input or bidirectional pad does not exist in a bank, the number of output pads that can be used in that bank depends on the total number of available pads in that same bank. however, when a voltage-referenced input exists, a de sign can use up to 20 output pads per v ref pin in a bank. bidirectional pins bidirectional pads must satisfy both input and output guidelines simultaneously. the general formulas for input and output rules are shown in table 10?9 . if the same output enable (oe) controls all the bidirectional pads (bidirectional pads in the same oe group are driving in and out at the same time) and there are no other outputs or voltage-referenced inputs in the bank, then the voltage-referenced input is never active at the same time as an output. ther efore, the output limitation rule does not apply. however, since th e bidirectional pads are linked to the same oe, the bidirectional pads wi ll all act as inputs at the same time. therefore, there is a limit of 40 input pads, as follows: + 40 per v ref pin if any of the bidirectional pads are controlled by different oe and there are no other outputs or voltage-referenced inputs in the bank, then one group of bidirectional pads can be used as inputs and another group is used as outputs. in such cases, the formula for the output rule is simplified, as follows: < total number of bidirectional pins > ? < total number of pins from smallest oe group > 20 per v ref pin table 10?9. bidirectional pin limitation formulas rules formulas input + 40 per v ref pin output + ? 20 per v ref pin
10?38 altera corporation stratix ii gx device handbook, volume 2 october 2007 design considerations consider a case where eight bidirectional pads are controlled by oe1, eight bidirectional pads are controlled by oe2, six bidirectional pads are controlled by oe3, and there are no other outputs or voltage-referenced inputs in the bank. while this totals 22 bidirectional pads, it is safely allowable because there would be a possible maximum of 16 outputs per v ref pin, assuming the worst case where oe1 and oe2 are active an d oe3 is inactive. this is useful for ddr sdram applications. when at least one additional volt age-referenced input and no other outputs exist in the same v ref group, the bidirectional pad limitation must simultaneously adhere to the in put and output limitations. the input rule becomes: < total number of bidirectional pins > + < total number of v ref input pins > 40 per v ref pin whereas the output rule is simplified as: < total number of bidirectional pins > 20 per v ref pin when at least one additi onal output exists but no voltage-referenced inputs exist, the output rule becomes: < total number of bidirectional pins > + < total number of output pins > ? < total number of pins from smallest oe group > 20 per v ref pin when additional voltage-referenced inputs and other outputs exist in the same v ref group, then the bidirect ional pad limitation must again simultaneously adhere to the input and output limitations. the input rule is: < total number of bidirectional pins > + < total number of v ref input pins > 40 per v ref pin whereas the output rule is given as: < total number of bidirectional pins > + < total number of output pins > ? < total number of pins from smallest oe group > 20 per v ref pin i/o pin placement with respect to high-speed differential i/o pins regardless of whether or not the serd es circuitry is utilized, there is a restriction on the placement of single -ended output pins with respect to high-speed differential i/o pins. as shown in figure 10?25 , all
altera corporation 10?39 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices single-ended outputs must be placed at least one lab row away from the differential i/o pins. there are no restrictions on the placement of single-ended input pins with respect to differential i/o pins. single-ended input pins may be pl aced within the same lab row as differential i/o pins. however, the si ngle-ended input?s ioe register is not available. the input must be implemented within the core logic. this single-ended output pin placement restriction only applies when using the lvds or hypertransport i /o standards in the left and right i/o banks. there are no restrictions for single-ended output pin placement with respect to differentia l clock pins in the top and bottom i/o banks. figure 10?25. single-ended output pin placem ent with respect to differential i/o pins dc guidelines power budgets are essential to ensure the reliability and functionality of a system application. you are often required to perform power dissipation analysis on each device in the system to come out with the total power dissipated in that system , which is composed of a static component and a dynamic component. the static power consumption of a de vice is the total dc current flowing from v ccio to ground. single-ended output pi n differential i/o pin single_ended input single-ended outputs not allowed row boundary
10?40 altera corporation stratix ii gx device handbook, volume 2 october 2007 design considerations for any ten consecutive pads in an i/o bank of stratix ii and stratix ii gx devices, altera recommends a maxi mum current of 250 ma, as shown in figure 10?26 , because the placement of v ccio /ground (gnd) bumps are regular, 10 i/o pins per pair of powe r pins. this limit is on the static power consumed by an i/o standard, as shown in table 10?10 . limiting static power is a way to improve reliability over the lifetime of the device. figure 10?26. dc current density restriction notes (1) , (2) notes to figure 10?26 : (1) the consecutive pads do not cross i/o banks. (2) v ref pins do not affect dc current calculation because there are no v ref pads. i/o pin sequence of an i/o bank any 10 consecutive output pins pin+9 pin pin 250ma i vcc gnd vcc
altera corporation 10?41 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices table 10?10 shows the i/o standard dc current specification. table 10?10. stratix ii and stratix ii gx i/o standar d dc current specification (part 1 of 2) note (1) i/o standard i pin (ma), top and bottom i/o banks i pin (ma), left and right i/o banks (2) lv t t l (3) (3) lv c m o s (3) (3) 2.5 v (3) (3) 1.8 v (3) (3) 1.5 v (3) (3) 3.3-v pci 1.5 na 3.3-v pci-x 1.5 na sstl-2 class i 12 (4) 12 (4) sstl-2 class ii 24 (4) 16 (4) sstl-18 class i 12 (4) 10 (4) sstl-18 class ii 20 (4) na 1.8-v hstl class i 12 (4) 12 1.8-v hstl class ii 20 (4) na 1.5-v hstl class i 12 (4) 8 1.5-v hstl class ii 20 (4) na differential sstl-2 class i 12 12 differential sstl-2 class ii 24 16 differential sstl-18 class i 12 10 differential sstl-18 class ii 20 na 1.8-v differential hstl class i 12 12 1.8-v differential hstl class ii 20 na 1.5-v differential hstl class i 12 8 1.5-v differential hstl class ii 20 na
10?42 altera corporation stratix ii gx device handbook, volume 2 october 2007 conclusion table 10?10 only shows the limit on the static power consumed by an i/o standard. the amount of power used at any moment could be much higher, and is based on the switching activities. conclusion stratix ii and stratix ii gx devices pr ovide i/o capabilities that allow you to work in compliance with cu rrent and emerging i/o standards and requirements. with the stratix ii or st ratix ii gx devices features, such as programmable driver strength, you ca n reduce board design interface costs and increase the development flexibility. references refer to the following references for more information: interface standard for nominal 3v/ 3.3-v supply digital integrated circuits, jesd8-b, electronic indu stries association, september 1999. 2.5-v +/- 0.2v (normal range) and 1.8-v to 2.7v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-5, electronic industries association, october 1995. 1.8-v +/- 0.15 v (normal range) and 1.2 v - 1.95 v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-7, electronic industries association, february 1997. 1.5-v +/- 0.1 v (normal range) and 0.9 v - 1.6 v (wide range) power supply voltage and interface standa rd for non-terminated digital integrated circuits, jesd8-11, elec tronic industries association, october 2000. notes to table 10?10 : (1) the current value obtained for differential hstl and diff erential sstl standards is per pin and not per differential pair, as opposed to the per-pair current va lue of lvds and hypertransport standards. (2) this does not apply to the right i/o banks of stratix ii gx devices. stratix ii gx devices have transceivers on the right i/o banks. (3) the dc power specification of each i/o standard depend s on the current sourcing and sinking capabilities of the i/o buffer programmed with that standard, as well as the load being driven. lvttl, lvcmos, 2.5-v, 1.8-v, and 1.5-v outputs are not included in the static power calculat ions because they normally do not have resistor loads in real applications. the voltage swing is rail-to-rail with capa citive load only. there is no dc current in the system. (4) this i pin value represents the dc current specification for the default current strength of the i/o standard. the i pin varies with programmable drive strength and is the same as the drive strength as set in quartus ii software. refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook for a detailed description of the programmable drive strength feature of voltage-referenced i/o standards. table 10?10. stratix ii and stratix ii gx i/o standar d dc current specification (part 2 of 2) note (1) i/o standard i pin (ma), top and bottom i/o banks i pin (ma), left and right i/o banks (2)
altera corporation 10?43 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices pci local bus specification, revision 2.2, pci special interest group, december 1998. pci-x local bus specification, revision 1.0a, pci special interest group. stub series terminated logic for 2.5-v (sstl-2), jesd8-9a, electronic industries as sociation, december 2000. stub series terminated logic for 1.8 v (sstl-18), preliminary jc42.3, electronic industries association. high-speed transceiver logic (h stl)?a 1.5-v output buffer supply voltage based interface st andard for digital integrated circuits, eia/jesd8-6, electronic industries association, august 1995. electrical characterist ics of low voltage differential signaling (lvds) interface circuits, ansi/t ia/eia-644, american national standards institute/telecommunications industry/electronic industries association, october 1995. referenced documents this chapter references the following documents: dc & switching characteristics chapter in volume 1 of the stratix ii device handbook dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook plls in stratix ii & straix ii gx devices chapter in volume 2 of the stratix ii gx device handbook stratix ii architecture chapter in volume 1 of the stratix ii device handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii gx transceiver user guide (volume 1) of the stratix ii gx device handbook
10?44 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history document revision history table 10?11 shows the revision history for this chapter. table 10?11. document revision history (part 1 of 2) date and document version changes made summary of changes october 2007 v4.6 updated figure 10?22 .? updated note 4 to table 10?2 .? added ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 9. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007 v4.5 added a note to the ?on-chip series termination with calibration? section. ? added a note to the ?on-chip series termination without calibration? section ? updated note to the ?stratix ii and stratix ii gx i/o features? section. ? updated the ?lvds? section. ? updated note to ?1.5 v? section ? updated note (1) for table 10?4 updated note (2) for table 10?3 ? updated table 10?2, column heading for columns 9 and 10. ? updated table 10?10. ? fixed typo in the ?stratix ii and stratix ii gx i/o features? section ? february 2007 v4.4 added the ?document revi sion history? section to this chapter. ? august 2006 v4.3 updated table 9?2, table 9?4, table 9?5, table 9?6, and table 9?7. ? april 2006 v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 8. chapter number change only due to chapter addition to section i in february 2006; no content change. ?
altera corporation 10?45 october 2007 stratix ii gx device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices december 2005 v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ? table 10?11. document revision history (part 2 of 2) date and document version changes made summary of changes
10?46 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history
altera corporation 11?1 october 2007 11. high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices introduction stratix ? ii and stratix ? ii gx device family offers up to 1-gbps differential i/o capabilities to support source-synchronous communication protocols such as hypertransport? technology, rapid i/o, xsbi, and spi. stratix ii and stratix ii gx devices have the following dedicated circuitry for high-speed differ ential i/o support: differential i/o buffer transmit serializer receive deserializer data realignment circuit dynamic phase aligner (dpa) synchronizer (fifo buffer) analog plls (fast plls) for high-speed differential interfaces, stratix ii and stratix ii gx devices can accommodate different differential i/o standards, including the following: lvds hypertransport technology hstl sstl lvpecl 1 hstl, sstl, and lvpecl i/o standards can be used only for pll clock inputs and outputs in differential mode. i/o banks stratix ii and stratix ii gx inputs and outputs are partitioned into banks located on the periphery of the die. the inputs and outputs that support lvds and hypertransport technology are located in row i/o banks, two on the left and two on the right side of the stratix ii device and two on the left side of the stratix ii gx devi ce. lvpecl, hstl, and sstl standards are supported on certain top and bottom banks of the die (banks 9 to 12) when used as differential clock in puts/outputs. differential hstl and sstl standards can be supported on ba nks 3, 4, 7, and 8 if the pins on these banks are used as dqs/dqsn pins. figures 11?1 and 11?2 show where the banks and the plls are located on the die. sii52005-2.3
11?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 i/o banks figure 11?1. strati x ii i/o banks note (1) , (2) , (3) , (4) , (5) , (6) , and (7) notes to figure 11?1 : (1) figure 11?1 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. see the pin list and quartus ii software for exact locations. (2) depending on the size of the device, differe nt device members have different numbers of v ref groups. (3) banks 9 through 12 are enhanced pll external cloc k output banks. these pll banks utilize the adjacent v ref group when voltage-referenced standards ar e implemented. for example, if an sstl input is implemented in pll bank 10, the voltage level at vrefb7 is the reference voltage level for the sstl input. (4) differential hstl and differential sstl standards are available for bidirectional operations on dqs pin and input-only operations on pll clock input pins; lvds, lvpecl, and hypertransport standards are available for input-only operations on p ll clock input pins. see the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook for more details. (5) quartus ii software does not support differential sstl and differential hstl standards at left/right i/o banks. see the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook if you need to implement these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. (7) plls 7, 8, 9, 10, 11, and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. bank 3 bank 4 bank 11 bank 9 pll11 pll5 pll7 pll1 pll2 pll4 pll3 pll10 i/o banks 7, 8, 10 & 12 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. i/o banks 3, 4, 9 & 11 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 bank 8 bank 7 bank 12 bank 10 pll12 pll6 pll8 pll9 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 vref3b 2 vref2b2 vref1b2 vref0b2 bank 2 vref3b1 vref2b1 vref1b1 vref0b1 bank 1 vref1b 5 vref2b5 vref3b5 vref4b5 bank 5 vref1b6 vref2b6 vref3b6 vref4b6 bank 6 vref4b2 vref0b5 vref4b1 vref0b6 dqs4t dqs3t dqs2t dqs1t dqs0t dqs4b dqs3b dqs2b dqs1b dqs0b dqs8b dqs7b dqs6b dqs5b dqs8t dqs7t dqs6t dqs5t this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. i/o banks 1, 2, 5 & 6 support lvttl, lvcmos, 2.5-v, 1.8-v, 1.5-v, sstl-2, sstl-18 class i, hstl-18 class i, hstl-15 class i, lvds, and hypertransport standards for input and output operations. hstl-18 class ii, hstl-15-class ii, sstl-18 class ii standards are only supported for input operations.
altera corporation 11?3 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices figure 11?2. stratix ii gx i/o banks note (1) , (2) , (3) , (4) , (5) , (6) , and (7) notes to figure 11?2 : (1) figure 11?2 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. it is a graphical representation only. (2) depending on size of the de vice, different device members have different number of v ref groups. refer to the pin list and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) horizontal i/o banks feature transceiver and dpa ci rcuitry for high speed differential i/o standards. (5) quartus ii software does not support differential sstl an d differential hstl standard s at left/right i/o banks. refer to the ?differential pin placement guidelines? on page 11?21 if you need to implement these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2sgx60c/d/e, ep2sgx90e/f, and ep2sgx130g. (7) plls 7, 8, 11, and 12 are available only in ep2sgx60c/d/e, ep2sgxe/f, and ep2sgx130g. i/o b a nk s 3, 4, 9, a n d 11 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion s . all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s at i/o ba nk s 9 a n d 11. i/o ba nk s 7, 8, 1 0 a n d 12 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion s . all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s at i/o ba nk s 1 0 a n d 12. i/o ba nk s 1 & 2 s u pp o rt lvttl, lv c mos, 2.5 v, 1.8 v, 1.5 v, sstl-2, sstl-18 c l ass i, lv d s, pse u d o- d i ffere n t i a l sstl-2, pse u d o- d i ffere n t i a l sstl-18 c l ass i sta n dards , hstl-18 c l ass i, a n d hstl-15 c l ass i f o r b o t h in p u t a n d ou tp u t o perat ion s . hstl, sstl-18 c l ass ii, pse u d o- d i ffere n t i a l hstl, pse u d o- d i ffere n t i a l sstl-18 c l ass ii, hstl-15 c l ass ii, a n d hstl-18 c l ass ii sta n dards are only s u pp o rted f o r in p u t o perat ion s . (4) dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 pll11 vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 pll12 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 bank 11 vref3b2 vref4b2 vref0b1 vref2b1 vref3b1 vref4b1 pll1 pll2 bank 1 bank 2 bank 3 bank 4 bank 12 bank 8 bank 7 pll7 pll8 pll6 pll5 bank 9 bank 10 vref1b1 vref0b2 vref1b2 vref2b2 dqs 8 dqs 8 thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) 13 14 17 16 15
11?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 i/o banks table 11?1 lists the differential i/o standards supported by each bank. table 11?2 shows the total number of diff erential channels available in stratix ii devices. the available chan nels are divided evenly between the left and right banks of the die. non-dedicated clocks in the left and right banks can also be used as data re ceiver channels. the total number of receiver channels includes these fo ur non-dedicated clock channels. pin migration is available for different size devices in the same package. table 11?1. supported differential i/o types bank row i/o (banks 1, 2, 5 and 6) (2) column i/o (banks, 3, 4 and 7 through 12) type clock inputs clock outputs data or regular i/o pins clock inputs clock outputs data or regular i/o pins differential hstl vv (1) differential sstl vv (1) lvpecl vv lv d s vvvvv hypertransport technology vvv note to ta b l e 11 ? 1 : (1) used as both inputs and outputs on the dqs/dqsn pins. (2) banks 5 and 6 are not available in stratix ii gx devices. table 11?2. differential channels in stratix ii devices (part 1 of 2) notes (1) , (2) , and (3) device 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga within the 1,508-pin fin ep2s15 38 transmitters 42 receivers 38 transmitters 42 receivers ep2s30 38 transmitters 42 receivers 58 transmitters 62 receivers ep2s60 38 transmitters 42 receivers 58 transmitters 62 receivers 84 transmitters 84 receivers ep2s90 38 transmitters 42 receivers 64 transmitters 68 receivers 90 transmitters 94 receivers 118 transmitters 118 receivers ep2s130 64 transmitters 68 receivers 88 transmitters 92 receivers 156 transmitters 156 receivers
altera corporation 11?5 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices table 11?3 shows the total number of diff erential channels available in stratix ii gx devices. non-dedicated clocks in the left bank can also be used as data receiver channels. the total number of receiver channels includes these four non-dedicated clock channels. pin migration is available for different size devices in the same package. ep2s180 88 transmitters 92 receivers 156 transmitters 156 receivers notes to ta b l e 11 ? 2 : (1) pin count does not includ e dedicated pll input pins. (2) the total number of receiver channels includes the four non-dedicated clock channels that can optionally be used as data channels. (3) within the 1,508-pin fineline bga package, 92 receiver cha nnels and 92 transmitter channels are vertically migratable. table 11?2. differential channels in stratix ii devices (part 2 of 2) notes (1) , (2) , and (3) device 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga within the 1,508-pin fin table 11?3. differential channels in stratix ii gx devices notes (1) , (2) , (3) device 780-pin fineline bga 1,152-pin fineline bga 1,508-pin fineline bga ep2sgx30 29 transmitters 31receivers ep2sgx60 29 transmitters 31 receivers 42 transmitters 42 receivers ep2sgx90 45 transmitters 47 receivers 59 transmitters 59 receivers ep2sgx130 71 transmitters 73 receivers notes to ta b l e 11 ? 3 : (1) pin count does not include dedicated pll input pins. (2) the total number of receiver channe ls includes the four non-dedicated clock channels that can optionally be used as data channels. (3) ep2sgx30cf780 devices with four transceiver channels are vertically migratable to ep2sgx60cf780 devices with four transceiver channels. ep2sgx30df780 devices with eight transceiver channels are vertically migratable to ep2sgx60df780 devices with eight transceiver channels. ep2sgx60ef1152 devices with 12 transceiver channels are vertically migratable to ep2sgx90ef1152 devices with 12 transceiver channels. ep2sgx90ff1508 devices with 16 transceiver channels are vertically migratable to ep2sgx130gf1508 devices with 20 transceiver channels.
11?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 differential transmitter differential transmitter the stratix ii and stratix ii gx tran smitter has dedicated circuitry to provide support for lvds and hypert ransport signaling. the dedicated circuitry consists of a differential bu ffer, a serializer, and a shared fast pll. the differential buffer can drive out lvds or hypertransport signal levels that are statically set in the quartus ? ii software. the serializer takes data from a parallel bus up to 10 bits wide from the internal logic, clocks it into the load registers, and serializes it using the shift registers before sending the data to the differen tial buffer. the most significant bit (msb) is transmitted first. the load and shift registers are clocked by the diffioclk (a fast pll clock running at th e serial rate) and controlled by the load enable signal generated fr om the fast pll. the serialization factor can be statically set to 4, 5, 6, 7, 8, 9, or 10 using the quartus ii software. the load enable signal is automatically generated by the fast pll and is derived from the serialization factor setting. figure 11?3 is a block diagram of the stratix ii transmitter. figure 11?3. transmitter block diagram each stratix ii and stratix ii gx transmitter data channel can be configured to operate as a transmitter clock output. this flexibility allows the designer to place the output cloc k near the data outputs to simplify board layout and reduce clock-to-data skew. different applications often require specific clock to data alignments or specific data rate to clock rate factors. the transmitter can output a cl ock signal at the same rate as the data with a maximum frequency of 717 mhz. the output clock can also be divided by a factor of 2, 4, 8, or 10, depending on the serialization factor. the phase of the clock in relati on to the data can be set at 0 or 180 (edge or center aligned). the fast pll provides additional support for internal logic serializer fast pll diffioclk load_en 10 tx_ou t
altera corporation 11?7 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices other phase shifts in 45 increments. th ese settings are made statically in the quartus ii megawizard ? software. figure 11?4 shows the transmitter in clock output mode. figure 11?4. transmitter in clock output mode the serializer can be bypassed to support ddr ( 2) and sdr ( 1) operations. the i/o element (ioe) contai ns two data output registers that each can operate in either ddr or sdr mode. the clock source for the registers in the ioe can come from any routing resource, from the fast pll, or from the enhanced pll. figure 11?5 shows the bypass path. figure 11?5. serializer bypass transmitter circuit diffioclk load_en parallel series internal lo g ic tx_outcloc k ioe serializer internal lo g ic ioe su pp o rts s d r, dd r, o r non-r eg i stered data p at h not used (connection exists) tx_out
11?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 differential receiver differential receiver the receiver has dedicated circuitry to support high-speed lvds and hypertransport signaling, along with enhanced data reception. each receiver consists of a differential buffer, dynamic phase aligner (dpa), synchronization fifo buffer, data realignment circuit, deserializer, and a shared fast pll. the differential buff er receives lvds or hypertransport signal levels, which are statically set by the quartus ii software. the dpa block aligns the incoming data to on e of eight clock phases to maximize the receiver?s skew margin. the dpa circuit can be bypassed on a channel-by-channel basis if it is not needed. set the dpa bypass statically in the quartus ii megawizard plug-in manager or dynamically by using the optional rx_dpll_enable port. the synchronizer circuit is a 1-bit wi de by 6-bit deep fifo buffer that compensates for any phase differen ce between the dpa block and the deserializer. if necessary, the data re alignment circuit inserts a single bit of latency in the serial bit stream to align the word boundary. the deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logi c. the data path in the receiver is clocked by either the diffioclk signal or the dpa recovered clock. the deserialization factor can be statically se t to 4, 5, 6, 7, 8, 9, or 10 by using the quartus ii software. the fast pll automatically generates the load enable signal, which is derived from the deserialization factor setting. figure 11?6 shows a block diagram of the receiver. figure 11?6. receiver block diagram dq 8 10 ? + data retimed_data dpa_clk ei g h t ph ase c lo c k s ded i cated r ece iv er in terface d pa by pass mul t i p l e x er up t o 1 g bps dpa fast pll diffioclk load_en rx_inclk synchronizer internal lo g ic re g ional or global cloc k data reali g nment circuitry
altera corporation 11?9 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices the deserializer, like the serializer, can also be bypassed to support ddr ( 2) and sdr ( 1) operations. the dpa and data realignment circuit cannot be used when the deserializer is bypassed. the ioe contains two data input registers that can operate in ddr or sdr mode. the clock source for the registers in the ioe can come from any routing resource, from the fast pll, or from the enhanced pll. figure 11?7 shows the bypass path. figure 11?7. deserializer bypass receiver data realignment circuit the data realignment circuit aligns the word boundary of the incoming data by inserting bit latencies in to the serial stream. an optional rx_channel_data_align port controls the bit insertion of each receiver independently controlled from the internal logic. the data slips one bit for every pulse on the rx_channel_data_align port. the following are requirements for the rx_channel_data_align port: the minimum pulse width is one peri od of the parallel clock in the logic array. the minimum low time between pulses is one period of parallel clock. there is no maximum high or low time. valid data is available two parallel clock cycles after the rising edge of rx_channel_data_align . rx_in ioe deserializer dpa circuitry pld logic array i o e s upports s d r, dd r, or non- r egistered data p ath
11?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 differential receiver figure 11?8 shows receiver output ( rx_out ) after one bit slip pulse with the deserialization factor set to 4. figure 11?8. data realignment timing the data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. the programma ble bit rollover point can be from 1 to 11 bit-times independent of the deserialization factor. an optional status port, rx_cda_max , is available to the fpga from each channel to indicate when the preset rollover point is reached. figure 11?9 illustrates a preset value of four bit-times before rollover occurs. the rx_cda_max signal pulses for one rx_outclk cycle to indicate that the rollover has occurred. figure 11?9. receiver data re-alignment rollover dynamic phase aligner the dpa block takes in high-speed serial data from the differential input buffer and selects one of eight phase clocks to sample the data. the dpa chooses a phase closest to the phase of the serial data. the maximum phase offset between the data and the phase-aligned clock is 1/8 ui, which is the maximum quantization error of the dpa. the eight phases rx_in rx_outclock rx_channel_data_ali g n rx_out inclk 3 3210 321x xx21 0321 2 1 0 3 2 1 0 3 2 1 0 rx_outclk rx_channel_data_align rx_cda_max inclk
altera corporation 11?11 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices are equally divided, giving a 45-degree resolution. figure 11?10 shows the possible phase relationships between the dpa clocks and the incoming serial data. figure 11?10. dpa clock phase to data bit relationship each dpa block continuously monitors the phase of the incoming data stream and selects a new clock phase if needed. the selection of a new clock phase can be prevented by the optional rx_dpll_hold port, which is available for each channel. the dpa block requires a training patte rn and a training sequence of at least 256 repetitions of the training pattern. the training pattern is not fixed, so you can use any training patte rn with at least one transition on each channel. an optional output port, rx_dpa_locked , is available to the internal logic, to indicate when the dpa block has settled on the closest phase to the incoming data phase. the rx_dpa_locked de-asserts, depending on what is selected in the quartus ii megawizard plug-in, when either a new phase is selected, or when the dpa has moved two phases in the same direction. the data may still be valid even when the rx_dpa_locked is deasserted. use data checkers to validate the data when rx_dpa_locked is deasserted. an independent reset port, rx_reset , is available to reset the dpa circuitry. the dpa circuit must be retrained after reset. 45? 90? 135? 180? 225? 270? 315? 0.125t vco t vco 0? rx_in d0 d1 d2 d3 d4 dn
11?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 differential i/o termination synchronizer the synchronizer is a 1-bit 6-bit deep fifo buffer that compensates for the phase difference between the recovered clock from the dpa circuit and the diffioclk that clocks the rest of th e logic in the receiver. the synchronizer can only compensate for phase differences, not frequency differences between the data and the receiver?s inclk . an optional port, rx_fifo_reset , is available to the internal logic to reset the synchronizer. the synchronizer is au tomatically reset when the dpa first locks to the incoming data. altera ? recommends using rx_fifo_reset to reset the synchronizer when the dpa signals a loss-of-lock condition beyond the initial locking condition. differential i/o termination stratix ii and stratix ii gx devices provide an on-chip 100- differential termination option on each differential receiver channel for lvds and hypertransport standards. the on-chip termination eliminates the need to supply an external termination resistor, simplifying the board design and reducing reflections caused by stubs between the buffer and the termination resistor. you can enable on-chip termination in the quartus ii assignments editor. differential on-c hip termination is supported across the full range of supported differential data rates. f for more information, refer to the high-speed i/o specifications section of the dc & switching characteristic s chapter in volume 1 of the stratix ii device handbook or the high-speed i/o spec ifications section of the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . figure 11?11 illustrates on-chip termination. figure 11?11. on-chip diff erential termination on-chip differential termination is su pported on all row i/o pins and on clock pins clk[0, 2, 8, 10] . the clock pins clk[1, 3, 9, 11] , and fpll[7..10]clk , and the clocks in the top and bottom i/o banks ( clk[4..7, 12..15] ) do not support differential on-chip termination. lvds/ht transmitter stratix ii differential receiver with on-chi p 100 termination r d z 0 = 50 z 0 = 50
altera corporation 11?13 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices fast pll the high-speed differential i/o receiv er and transmitter channels use the fast pll to generate the parallel global clocks ( rx- or tx- clock) and high-speed clocks ( diffioclk ). figure 11?12 shows the locations of the fast plls. the fast pll vco operates at the clock frequency of the data rate. each fast pll offers a single se rial data rate support, but up to two separate serialization and/or deserial ization factors (from the c0 and c1 fast pll clock outputs) can be used. clock switchover and dynamic fast pll reconfiguration is available in high-speed differential i/o support mode. f for additional information on the fast pll, refer to the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook or the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . figure 11?12 shows a block diagram of the fast pll in high-speed differential i/o support mode. figure 11?12. fast pll block diagram notes to figure 11?12 : (1) stratix ii fast plls only support manual clock switchover. (2) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or pin-driven dedicated global or regional clock. (3) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes. stratix ii devices only support one rate of data transfer per fast p ll in high-speed differential i/o support mode. (4) this signal is a high-speed differential i/o support serdes control signal. (5) if the design enables this 2 counter, the devi ce can use a vco frequency range of 150 to 520 mhz. char g e pump vco c1 8 8 4 4 8 clock input pfd c0 m loop filter ph ase f re qu e n c y detect o r v c o ph ase s e l ect ion s e l ectab l e at eac h pll ou tp u t po rt po st -s ca l e c oun ters global clocks diffioclk0 (3) loaden0 (4) diffioclk1 (3) loaden1 (4) re g ional clocks to dpa block global or re g ional clock (2) global or re g ional clock (2) c2 c3 n 4 clock (1) switchover circuitry sh aded po rt ion s o f t h e pll are r ec on f i g u rab l e k (5)
11?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking clocking the fast plls feed in to the different ial receiver and transmitter channels through the lvds/dpa clock network. the center fast plls can independently feed the banks above and below them. the corner plls can feed only the banks adjacent to them. figures 11?13 and 11?14 show the lvds and dpa clock networks of the stratix ii devices. figure 11?13. fast pll and lvds/d pa clock for ep2s15, ep2s30, and ep2s60 devices note (1) note to figure 11?13 : (1) figure 11?13 applies to ep2s60 devices in the 484 and 672 pin packages. 4 2 2 2 2 4 4 4 4 4 4 4 quadrant quadrant quadrant quadrant lvds clock fast pll 1 fast pll 2 dpa clock lvds clock dpa clock lvds clock fast pll 4 fast pll 3 dpa clock lvds clock dpa clock
altera corporation 11?15 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices figure 11?14. fast pll and lvds/dpa clocks for ep2s60, ep2s90, ep2s130 and ep2s180 devices note (1) note to figure 11?14 : (1) figure 11?14 applies only to the ep2s60 in the 1020 stratix ii gx device. figures 11?15 and 11?16 show the fast pll and lvds/dpa clock of the stratix ii gx devices. figure 11?15. fast pll and lvds/d pa clock for ep2sgx30c/d and ep2sgx60c/d devices lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock lvds clock dpa clock fast pll 4 fast pll 7 fast pll 10 fast pll 3 lvds clock dpa clock quadrant quadrant quadrant quadrant 4 4 2 4 4 4 4 2 2 2 2 2 fast pll 8 fast pll 9 2 2 4 2 2 4 4 4 quadrant quadrant quadrant quadrant lvds clock fast pll 1 fast pll 2 dpa clock lvds clock dpa clock no fast plls on ri g ht side of stratix ii gx devices
11?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking figure 11?16. fast pll and lvds/dpa clocks for ep2sgx60e, ep2sgx90 and ep2sgx130 devices source synchronous timing budget this section discusses the timing budget, waveforms, and specifications for source-synchronous signaling in stratix ii and stratix ii gx devices. lvds and hypertransport i/o standards enable high-speed data transmission. this high da ta transmission rate results in better overall system performance. to take advantage of fast system performance, it is important to understand how to anal yze timing for these high-speed signals. timing analysis for the differential block is different from traditional synchronous timi ng analysis techniques. rather than focusing on cloc k-to-output and setup times, source-synchronous timing analysis is based on the skew between the data and the clock signals. high-sp eed differential da ta transmission requires the use of timing paramete rs provided by ic vendors and is strongly influenced by board skew, cable skew, and clock jitter. this section defines the source-synchronous differential data orientation timing parameters, the timing budg et definitions for stratix ii and stratix ii gx devices, and how to us e these timing parameters to determine a design's maximum performance. quadrant quadrant quadrant quadrant no fast plls on ri g ht side of stratix ii gx devices lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock fast pll 7 4 4 2 4 2 2 fast pll 8 2
altera corporation 11?17 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices differential data orientation there is a set relationship between an external clock and the incoming data. for operation at 1 gbps and serdes factor of 10, the external clock is multiplied by 10, and phase-alignment can be set in the pll to coincide with the sampling window of each data bit. the data is sampled on the falling edge of the multiplied clock. figure 11?17 shows the data bit orientation of the 10 mode. figure 11?17. bit orientation in the quartus ii software differential i/o bit position data synchronization is necessary fo r successful data transmission at high frequencies. figure 11?18 shows the data bit orientation for a channel operation. these figures are based on the following: serdes factor equals cl ock multiplication factor edge alignment is selected for phase alignment implemented in hard serdes for other serialization fa ctors use the quartus ii so ftware tools and find the bit position within the word. the bit positions after deserialization are listed in table 11?4 . figure 11?18 also shows a functional waveform. timing waveforms may produce different results. altera recommends performing a timing simulation to predict actual device behavior. n-1 n-0 9 8 7 6 5 4 3 2 1 0 10 lvds bits msb lsb inclock/outclock data in high-frequency clock
11?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking figure 11?18. bit order for one channel of differential data previous cycle 76543 21 0 msb lsb tx_outclock tx_out xxxxxxxx xxxxxxxx current cycle next cycle transmitter channel operation (x 8 mode) xxxxxxxx rx_inclock rx_in 76543210 xxxxxxxxxxx xxxxx receiver channel operation (x 8 mode) rx_inclock rx_in rx_outclock rx_out [3..0] xx x x x x xx x xx x receiver channel operation (x4 mode) 3 210 x x x x x x x x x x x x 3210 rx_outclock rx_out [ 7..0 ] x x x x x x x x x x x x x x x x x x x x 7 6 5 4 3 2 1 0 x x x x
altera corporation 11?19 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices table 11?4 shows the conventions for differential bit naming for 18 differential channels. the msb and lsb positions increase with the number of channels used in a system. receiver skew margin for non-dpa changes in system environment, su ch as temperature, media (cable, connector, or pcb) loading effect, the receiver's setup and hold times, and internal skew, reduce the sampling window for the receiver. the timing margin between the receiver?s clock input and the data input sampling window is called receiver skew margin (rskm). figure 11?19 shows the relationship between the rskm and the receiver?s sampling window. table 11?4. lvds bit naming receiver channel data number internal 8-bit parallel data msb position lsb position 170 2158 32316 43124 53932 64740 75548 86356 97164 10 79 72 11 87 80 12 95 88 13 103 96 14 111 104 15 119 112 16 127 120 17 135 128 18 143 136
11?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 clocking tccs, rskm, and the sampling wind ow specifications are used for high-speed source-synchronous differential signals without dpa. when using dpa, these specifications are exchanged for the simpler single dpa jitter tolerance specification. for inst ance, the receiver skew is why each input with dpa selects a different phas e of the clock, th us removing the requirement for this margin. figure 11?19. differential high-speed timing diagram and timing budget for non-dpa rskm tui time unit interval (tui) rskm tccs internal clock fallin g ed g e t sw (min) bit n t sw (max) bit n rskm tccs t swbegin t swend samplin g window tccs 2 receiver input data transmitter output data internal clock synchronization external clock receiver input data internal clock external input clock timing budget timing diagram clock placement samplin g window (sw) rskm tccs
altera corporation 11?21 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices differential pin placement guidelines in order to ensure proper high-s peed operation, differential pin placement guidelines have been es tablished. the quartus ii compiler automatically checks that these guidelines are followed and will issue an error message if these guidelines are not met. pll driving distance information is separated into guidel ines with and without dpa usage. high-speed differential i/o s and single-ended i/os when a differential channel or channe ls of side banks are used (with or without dpa), you must adhere to th e guidelines described in the following sections. single-ended i/os are allowed in the same bank as the lvds channels (with or without dpa) as long as the single-ended i/o standard uses the same v ccio as the lvds bank. single-ended inputs can be in the same lab row. outputs cannot be on the same lab row with lvds i/os. if input registers are used in the ioe, single-ended inputs cannot be in the same lab row as an lvds serdes block. lvds (non-serdes) i/os are allo wed in the same row as lvds serdes but the use of ioe registers are not allowed. single-ended outputs are limited to 120 ma drive strength on lvds banks (with or without dpa). lvttl equation for maximum number of i/os in an lvds bank: ? 120 ma = (number of lvttl outputs) (drive strength of each lvttl output) sstl-2 equation: ? 120 ma = (number of sstl-2 i/os ) (drive strength of each output) 2 lvttl and sstl-2 mix equation: ? 120 ma= (total drive strength of all lvttl outputs) + (total drive strength of all sstl2 outputs) 2 single-ended inputs can be in the same lab row as a differential channel using the serdes circuitry; however, ioe input registers are not available for the single-ended i/os placed in the same lab row as differential i/os. the same rule for input registers applies for non- serdes differential inputs placed within the same lab row as a serdes differential channel. the input register must be implemented within the core logic. the same rule for input registers applies for non-serdes differential inputs placed within the same lab row as a serdes differential channel.
11?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 differential pin placement guidelines single-ended output pins must be at least one lab row away from differential output pins, as shown in figure 11?20 . figure 11?20. single-ended output pi n placement with respect to differential i/o pins dpa usage guidelines the stratix ii and stratix ii gx device have differential receivers and transmitters on the row banks of the device. each receiver has a dedicated dpa circuit to align the phase of the clock to the data phase of its associated channel. when a channel or channels of left or right banks are used in dpa mode, the guidelines listed below must be adhered to. fast pll/dpa channel driving distance each fast pll can drive up to 25 contiguous rows in dpa mode in a single bank (not including the re ference clock row). the unbonded serdes i/o rows are included in the 25 row calculation. these channels can be anywhere in the bank, their distance from the pll is not relevant, but the channels must be within 25 rows of each other. single-ended output pi n differential i/o pin single_ended input single-ended outputs not allowed row boundary
altera corporation 11?23 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices unused channels can be within the 25 row span, but all used channels must be in dpa mode from the same fast pll. center fast plls can drive two i/o banks simultaneously, up to 50 channels (25 on the upper bank and 25 on the lower bank) as shown in figure 11?21 . if one center fast pll drives dpa channels in the upper and lower banks, the other center fast pll cannot be used for dpa. figure 11?21. driving capabilitie s of a center fast pll ref clk ref clk dpa dpa dpa dpa dpa dpa dpa dpa dpa dpa fast pll fast pll ref clk center pll used for dpa center pll used for dpa ref clk top channels driven by center pll bottom channels driven by center pll
11?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 differential pin placement guidelines using corner and center fast plls if a differential bank is being dr iven by two fast plls, where the corner pll is driving one group and the center fast pll is driving another group, there must be at le ast 1 row of separation between the two groups of dpa channels (see figure 11?22 ). the two groups can operate at independent frequencies. not all the channels are bonded out of the die. each lab row is cons idered a channel, whether or not it has i/o support. no separation is necessary if a single fast pll is driving dpa channels as well as no n-dpa channels as long as the dpa channels are contiguous. figure 11?22. usage of corner and center fast plls driving dpa channels in a single bank ref clk ref clk diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o fast pll fast pll ref clk center pll unused one unused channel for buffer corner pll used for dpa ref clk channels driven by center pll channels driven by corner pll
altera corporation 11?25 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices using both center fast plls both center fast plls can be used for dpa as long as they drive dpa channels in their adjace nt quadrant only. see figure 11?23 . both center fast plls cannot be us ed for dpa if one of the fast plls drives the top and bottom banks, or if they are driving cross banks (e.g., the lower fast pll drives the top bank and the top fast pll drives the lower bank). figure 11?23. center fast pll usage when driving dpa channels ref clk ref clk dpa dpa dpa dpa dpa dpa dpa dpa dpa dpa fast pll fast pll ref clk center pll driving top bank center pll driving lower bank ref clk channels driven by the lower center pl l channels driven by the upper center pl l
11?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 differential pin placement guidelines non-dpa differential i/o usage guidelines when a differential channel or channels of left or right banks are used in non-dpa mode, you must adhere to th e guidelines in the following sections. fast pll/differential i/o driving distance as shown in figure 11?24 , each fast pll can drive all the channels in the entire bank. figure 11?24. fast pll driving capability when driving non-dpa differential channels fast pll diff i/o diff i/o fast pll ref clk diff i/o diff i/o diff i/o diff i/o ref clk diff i/o diff i/o diff i/o diff i/o diff i/o each pll can driv e the entire bank ref clk ref clk center pll corner pll
altera corporation 11?27 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices using corner and center fast plls the corner and center fast plls can be used as long as the channels driven by separate fast plls do no t have their transmitter or receiver channels interleaved. figure 11?25 shows illegal placement of differential channels when using corner and center fast plls. if one fast pll is driving transmitter channels only, and the other fast pll drives receiver channels only, the channels driven by those fast plls can overlap each other. center fast plls can be used for both transmitter and receiver channels. figure 11?25. illegal placement of interlaced duplex channels in an i/o bank board design considerations this section explains how to achiev e the optimal performance from the stratix ii and stratix ii gx high-sp eed i/o block and en sure first-time success in implementing a functional design with optimal signal quality. f for more information on board layout recommendations and i/o pin terminations, refer to an 224: high-speed board layout guidelines . fast pll diff i/o diff i/o fast pll ref clk diff i/o diff i/o diff i/o diff i/o ref clk diff i/o diff i/o diff i/o diff i/o diff i/o ref clk ref clk center pll corner pll interleaved duplex channel is not allowed duplex channel driven by center pll duplex channel driven by corner pll
11?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 conclusion to achieve the best performance fr om the device, pay attention to the impedances of traces and connectors, differential routing, and termination techniques. f use this section together with the stratix ii device family data sheet in volume 1 of the stratix ii device handbook . the stratix ii and stratix ii gx high-s peed module generates signals that travel over the media at frequencies as high as one gbps. board designers should use the following guidelines: base board designs on controlled differential impedance. calculate and compare all parameters such as trace width, trac e thickness, and the distance between two differential traces. place external reference resistors as close to receiver input pins as possible. use surface mount components. avoid 90 or 45 corners. use high-performance connectors such as hmzd or vhdm connectors for backplane designs. two suppliers of high- performance connectors are teradyne corp ( www.teradyne.com ) and tyco international ltd. ( www.tyco.com ). design backplane and card traces so that trace impedance matches the connector?s or the termination?s impedance. keep an equal number of vias for both signal traces. create equal trace lengths to avoi d skew between signals. unequal trace lengths also result in misplaced crossing points and system margins when the tccs value increases. limit vias, because they caus e impedance discontinuities. use the common bypass capacitor va lues such as 0.001, 0.01, and 0.1 f to decouple the fast pll power and ground planes. you can also use 0.0047 f and 0.047 f. keep switching ttl signals away fr om differential signals to avoid possible noise coupling. do not route ttl clock signals to areas under or above the differential signals. route signals on adjacent laye rs orthogonally to each other. conclusion stratix ii and stratix ii gx high-speed differential inputs and outputs, with their dpa and data realignmen t circuitry, allo w users to build a robust multi-gigabit system. the dpa circuitry allows users to compensate for any timing skews resu lting from physical layouts. the data realignment circuitry allows th e devices to align the data packet between the transmitter and receiv er. together wi th the on-chip differential termination, stratix ii and stratix ii gx devices can be used as a single-chip solution for high-speed a pplications.
altera corporation 11?29 october 2007 stratix ii gx device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices referenced documents this chapter references the following documents: an 224: high-speed board layout guidelines dc & switching characteristic s chapter in volume 1 of the stratix ii device handbook dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook selectable i/o standards in st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook stratix ii device family data sheet in volume 1 of the stratix ii device handbook document revision history table 11?5 shows the revision history for this chapter. table 11?5. document revision history (part 1 of 2) date and document version changes made summary of changes october 2007, v2.3 updated figure 11?2 .? added ?referenced documents? section. ? minor text edits. ? august 2007, v2.2 added figure 11?9 .? updated ?receiver data realignment circuit? .? for the stratix ii gx device handbook only: formerly chapter 10. t he chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. ? may 2007, v2.1 updated entire chapter to include stratix ii gx information. ? changed chapter part number. ? fixed two types in ?high-speed differential i/os and single-ended i/os? section ?
11?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history february 2007 v2.0 this chapter changed from high-speed, source- synchronous differential i/o interfaces in stratix ii gx devices to ?high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices?. ? added the ?document revision history? section to this chapter. ? added ?and stratix ii gx? after each instance of ?stratix ii?. ? updated figures 10?4, 10?20, 10?22. ? updated note (4) of figure 10?2. ? updated table 10?1. ? updated the following sections: ?i/o banks? ?differential i/o termination? ?fast pll ? ?differential i/o bit position? ?dpa usage guidelines? ?fast pll/dpa channel driving distance? ? updated note (1) of tables 10?2 and 10?3. ? added note (5) to figure 10?11. ? added table 10?3. ? added figures 10?14, 10?15, 10?19. ? deleted old section called high-speed differential i/os and single-ended i/os and added a new ?high-speed differential i/os and single-ended i/os? section. ? deleted dpa and single-ended i/os section. ? updated title and added note (1) to figure 10?12. ? added note (1) to figure 10?13. ? april 2006, v1.2 updated all the megawizard plug-in manager figures to match the quartus ii software gui. updated ?dedicated source-synchronous circuitry? section, including table 10?3. ? february 2006, v1.1 updated chapter number from 9 to 10. updated figures 10?11 and 10?12. ? october 2005 v1.0 added chapter to the stratix ii gx device handbook . ? table 11?5. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation section v?1 preliminary section v. digital signal processing (dsp) this section provides information for design and optimization of digital signal processing (dsp) functions an d arithmetic operations in the on- chip dsp blocks. this section contains the following chapter: chapter 12, dsp blocks in st ratix ii & stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section v?2 altera corporation preliminary digital signal processing (dsp) stratix ii gx device handbook, volume 2
altera corporation 12?1 october 2007 12. dsp blocks in stratix ii & stratix ii gx devices introduction stratix ? ii and stratix ii gx devices have dedicated digital signal processing (dsp) blocks optimized fo r dsp applications requiring high data throughput. these dsp blocks combined with the flexibility of programmable logic devices (plds), provide you with the ability to implement various high performanc e dsp functions easily. complex systems such as cdma2000, voice over internet protocol (voip), high- definition television (hdtv) requ ire high performance dsp blocks to process data. these system designs typically use dsp blocks as finite impulse response (fir) filters, comple x fir filters, fast fourier transform (fft) functions, discrete cosine transform (dct) functions, and correlators. stratix ii and stratix ii gx dsp bloc ks consist of a combination of dedicated blocks that perform mult iplication, addition, subtraction, accumulation, and summation operations. you can configure these blocks to implement arithmetic functions like multipliers, multiply-adders and multiply-accumulators which are necessary for most dsp functions. along with the dsp blocks, the trimatrix tm memory structures in stratix ii and stratix ii gx devices also support various soft multiplier implementations. the combination of soft multipliers and dedicated dsp blocks increases the number of multi pliers available in stratix ii and stratix ii gx devices and provides you with a wide variety of implementation options and flexibility when designing your systems. f see the stratix ii device family data sheet in volume 1 of the stratix ii device handbook or the stratix ii gx device family data sheet in volume 1 of the stratix ii gx device handbook for more information on stratix ii and stratix ii gx devices, respectively. dsp block overview each stratix ii and stratix ii gx device has two to four columns of dsp blocks that efficientl y implement multiplication, multiply-accumulate (mac) and multiply-add functions. figure 12?1 shows the arrangement of one of the dsp block columns wi th the surrounding labs. each dsp block can be configured to support: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier sii52006-2.2
12?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 dsp block overview figure 12?1. dsp blocks arranged in columns with adjacent labs the multipliers then feed an adder or accumulator block within the dsp block. stratix ii and stratix ii gx device multipliers support rounding and saturation on q1.15 input form ats. the dsp block also has input registers that can be configured to operate in a shift register chain for efficient implementation of functions like fir filters. the accumulator within the dsp block can be initialized to any value and supports rounding and saturation on q1.15 input formats to the multiplier. a single dsp block can be broken down to operate different configuration modes simultaneously. 1 for more information on q1.15 formatting, see ?saturation and rounding? on page 12?13 . dsp block column dsp block 4 lab rows
altera corporation 12?3 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices the number of dsp blocks per co lumn and the number of columns available increases with device density. table 12?1 shows the number of dsp blocks in each stratix ii device and the multipliers that you can implement. table 12?2 shows the number of dsp blocks in each stratix ii gx device and the multipliers that you can implement. table 12?1. number of dsp blocks in stratix ii devices note (1) device dsp blocks 9 9 multipliers 18 18 multipliers 36 36 multipliers ep2s15 12 96 48 12 ep2s30 16 128 64 16 ep2s60 36 288 144 36 ep2s90 48 384 192 48 ep2s130 63 504 252 63 ep2s180 96 768 384 96 note to table 12?1 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers. table 12?2. number of dsp blocks in stratix ii gx devices note (1) device dsp blocks 9 9 multipliers 18 18 multipliers 36 36 multipliers ep2sgx30c ep2sgx30d 16 128 64 16 ep2sgx60c ep2sgx60d ep2sgx60e 36 288 144 36 ep2sgx90e ep2sgx90f 48 384 192 48 ep2sgx130g 63 504 252 63 note to table 12?2 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers.
12?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 dsp block overview in addition to the dsp block multiplie rs, you can use the stratix ii or stratix ii gx device?s trimatrix memory blocks for soft multipliers. the availability of soft multipliers in creases the number of multipliers available within the device. table 12?3 shows the total number of multipliers available in stratix ii devices using dsp blocks and soft multipliers. table 12?3. number of multipliers in stratix ii devices device dsp blocks (18 18) soft multipliers (16 16) (1) , (2) total multipliers (3) , (4) ep2s15 48 100 148 (3.08) ep2s30 64 189 253 (3.95) ep2s60 144 325 469 (3.26) ep2s90 192 509 701 (3.65) ep2s130 252 750 1,002 (3.98) ep2s130 384 962 1,346 (3.51) notes to ta b l e 1 2 ? 3 : (1) soft multipliers implemented in sum of multiplication mode. ram blocks are configured with 18-bit data widths and sum of coefficients up to 18-bits. (2) soft multipliers are only implemented in m4k and m512 trimatrix memory blocks, not m-ram blocks. (3) the number in parentheses represents the increase factor, which is the total number of multipliers with soft multipliers divided by the number of 18 18 multipliers supported by dsp blocks only. (4) the total number of multipliers may vary according to the multiplier mode used.
altera corporation 12?5 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices table 12?4 shows the total number of multi pliers available in stratix ii gx devices using dsp blocks and soft multipliers. f refer to the stratix ii architectur e chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook for more information on stratix ii or stratix ii gx trimatrix memory blocks. refer to an 306: implementing multipliers in fpga devices for more information on soft multipliers. table 12?4. number of multipliers in stratix ii gx devices device dsp blocks (18 18) soft multipliers (16 16) (1) , (2) total multipliers (3) , (4) ep2sgx30c ep2sgx30d 64 189 253 (3.95) ep2sgx60c ep2sgx60d ep2sgx60e 144 325 469 (3.26) ep2sgx90e ep2sgx90f 192 509 701 (3.65) ep2sgx130g 252 750 1,002 (3.98) notes to ta b l e 1 2 ? 4 : (1) soft multipliers implemented in sum of multiplication mode. ram blocks are configured with 18-bit data widths and sum of coefficients up to 18-bits. (2) soft multipliers are only implemented in m4k and m512 trimatrix memory blocks, not m-ram blocks. (3) the number in parentheses represents the increase factor, which is the total number of multipliers with soft multipliers divided by the number of 18 18 multipliers supported by dsp blocks only. (4) the total number of multipliers may vary according to the multiplier mode used.
12?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 dsp block overview figure 12?2 shows the dsp block configured for 18 18 multiplier mode. figure 12?3 shows the 9 9 multiplier configuration of the dsp block. figure 12?2. dsp block in 18 18 mode adder/ subtractor/ accumulator 1 adder multiplier block prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena summation block adder output block adder/ subtractor/ accumulator 2 q1.15 round/ saturate q1.15 round/ saturate q1.15 round/ saturate q1.15 round/ saturate to multitrack interconnect clrn dq ena from the row interface block optional serial shift register inputs from previous dsp block optional serial shift register outputs to next dsp block in the column optional input register stage with parallel input or shift register configuration optional pipline register stage summation stage for adding four multipliers together optional stage configurable as accumulator or dynamic adder/subtractor output selection multiplexer q1.15 round/ saturate q1.15 round/ saturate
altera corporation 12?7 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?3. dsp block in 9 9 mode clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1a summation summation clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1b clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2a clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2b clrn dq ena clrn dq ena clrn dq ena output selection multiplexer to multitrack interconnect
12?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 architecture architecture the dsp block consists of the following elements: a multiplier block an adder/subtractor/accumulator block a summation block input and output interfaces input and output registers multiplier block each multiplier block has the following elements: input registers a multiplier block a rounding and/or saturation stage for q1.15 input formats a pipeline output register
altera corporation 12?9 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?4 shows the multiplier block architecture. figure 12?4. multiplier block architecture notes to figure 12?4 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) you can send these signals through either one or two pipeline registers. (3) the rounding and/or saturation is only supported in 18 18-bit signed multiplication for q1.15 inputs. input registers each multiplier operand can feed an input register or directly to the multiplier. the following dsp block signals control each input register within the dsp block: clock[3..0] ena[3..0] aclr[3..0] the input registers feed the multip lier and drive two dedicated shift output lines, shiftouta and shiftoutb . the dedicated shift outputs from one multiplier block directly f eed input registers of the adjacent multiplier below it within the same ds p block or the first multiplier in the next dsp block to form a shift register chain, as shown in figure 12?5 . the clrn dq ena data a data b shiftoutb shiftouta shiftina shiftinb aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) clrn dq ena clrn dq ena sourcea sourceb q1.15 round/ saturate mult_saturate (1) mult_round (1) data out (2) multiplier block (3) dsp block pipeline register output register clrn dq ena mult_is_saturated
12?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 architecture dedicated shift register chain spans a single column but longer shift register chains requiring multiple columns can be implemented using regular fpga routing resources. therefor e, this shift register chain can be of any length up to 768 registers in the largest member of the stratix ii or stratix ii gx device family. shift registers are useful in dsp functions like fir filters. when implementing 9 9 and 18 18 multip liers, you do not need external logic to create the shift register chai n because the input shift registers are internal to the dsp block. this impl ementation signific antly reduces the le resources required, avoids routing congestion, and results in predictable timing. stratix ii and stratix ii gx dsp blocks allow you to dynamically select whether a particular multiplier operan d is fed by regular data input or the dedicated shift register input using the sourcea and sourceb signals. a logic 1 value on the sourcea signal indicates that data a is fed by the dedicated scan-chain; a logic 0 value indicates that it is fed by regular data input. this feature allows the implementation of a dynamically loadable shift register where the shift register operates normally using the scan-chains and can also be loaded dynamically in parallel using the data input value.
altera corporation 12?11 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?5. shift register chain note (1) note to figure 12?5 : (1) either data a or data b input can be set to a pa rallel input for constant co efficient multiplication. clrn dq ena data a data b a[n] b[n] clrn dq ena clrn dq ena shiftouta shiftoutb a[n ? 1] b[n ? 1] clrn dq ena clrn dq ena a[n ? 2] b[n ? 2] clrn dq ena clrn dq ena dsp block 0 dsp block 1 q1.15 round/ saturate q1.15 round/ saturate shiftouta shiftoutb shiftouta shiftoutb q1.15 round/ saturate clrn dq ena clrn dq ena
12?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 architecture table 12?5 shows the summary of input register modes for the dsp block. multiplier stage the multiplier stage supports 9 9, 18 18, or 36 36 multipliers as well as other smaller multipliers in between these configurations. see ?operational modes? on page 12?21 for details. depending on the data width of the multiplier, a sing le dsp block can perform many multiplications in parallel. each multiplier operand can be a un ique signed or unsigned number. two signals, signa and signb , control the representation of each operand respectively. a logic 1 value on the signa signal indicates that data a is a signed number while a logic 0 value indicates an unsigned number. table 12?6 shows the sign of the mul tiplication result for the various operand sign repres entations. the result of the multiplication is signed if any one of the operands is a signed value. there is only one signa and one signb signal for each dsp block. therefore, all of the data a inputs feeding the same dsp block must have the same sign representati on. similarly, all of the data b inputs feeding the same dsp block must have the same si gn representation . the multiplier offers full precision regardless of the sign representation. 1 when the signa and signb signals are unus ed, the quartus ? ii software sets the multiplier to perform unsigned multiplication by default. table 12?5. input register modes register input mode 9 9 18 18 36 36 parallel input vvv shift register input vv table 12?6. multiplier sign representation data a (signa value) data b (signb value) result unsigned (logic 0) unsigned (logic 0) unsigned unsigned (logic 0) signed (logic 1) signed signed (logic 1) unsigned (logic 0) signed signed (logic 1) signed (logic 1) signed
altera corporation 12?13 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices saturation and rounding the dsp blocks have hardware suppo rt to perform optional saturation and rounding after each 18 18 mult iplier for q1.15 input formats. 1 designs must use 18 18 multip liers for the saturation and rounding options because the q1. 15 input format requires 16-bit input widths. 1 q1.15 input format multiplication requires signed multipliers. the most significant bit (msb) in the q1.15 input format represents the value?s sign bit. use signed multipliers to ensure the proper sign extension during multiplication. the q1.15 format uses 16 bits to re present each fixed point input. the msb is the sign bit, and the remain ing 15-bits are used to represent the value after the decimal place (or the fr actional value). this q1.15 value is equivalent to an integer number representation of the 16-bits divided by 2 15 , as shown in the following equations. all q1.15 numbers are between ?1 and 1. when performing multiplication, even though the q1.15 input only uses 16 of the 18 multiplier inputs, the enti re 18-bit input bus is transmitted to the multiplier. this is like a 1.17 inpu t, where the two least significant bits (lsbs) are always 0. the multiplier outp ut will be a 2.34 value (36 bits total) before performing any rounding or saturation. the two ms bs are sign bits. since the output only requires one sign bit, you can ignore one of the two msbs, resulting in a q1.34 value before rounding or saturation. when the design performs saturati on, the multiplier output gets saturated to 0x7fffffff in a 1.31 format. this uses bits [34..3] of the overall 36-bit multiplier output. the three lsbs are set to 0. the dsp block obtains the mult_is_saturated or accum_is_saturated overflow signal value from the lsb of the multiplier or accumulator output. ther efore, whenever saturation occurs, the lsb of the multiplier or ac cumulator output will send a 1 to the ?? 1 2 = 1 100 0000 0000 0000 = 0x4000 2 15 1 8 = 0 001 0000 0000 0000 = 0x1000 2 15
12?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 architecture mult_is_saturated or accum_is_saturated overflow signal. at all other times, this overflow signal is 0 when saturation is enabled or reflects the value of the lsb of th e multiplier or accumulator output. when the design performs rounding , it adds 0x00008000 in 1.31 format to the multiplier output, and it only uses bits [34..15] of the overall 36-bit multiplier output. adding 0x00008000 in 1.31 format to the 36-bit multiplier result is equivalent to ad ding 0x0 0004 0000 in 2.34 format. the 16 lsbs are set to 0. figure 12?6 shows which bits are used when the design performs rounding and sa turation for the multiplication.
altera corporation 12?15 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?6. rounding and saturation bits note to figure 12?6 : (1) both sign bits are the same. the design only uses one sign bit, and the other one is ignored. if the design performs a multiply_accumulate or multiply_add operation, the multiplier output is input to the adder/subtractor/accumula tor blocks as a 2.31 value, and the three lsbs are 0. 1 sign bit 2 lsbs 15 bits 2 sign bits (1) 3 lsbs 31 bits 1 sign bit 2 lsbs 15 bits 15 bits 19 lsbs are ignored 18 bits 2 sign bits (1) 3 lsbs 31 bits 2 sign bits (1) 2 sign bits (1) 3 lsbs 31 bits 18 18 36 111 1 1 100 0 00 0 00 0 00 00 00 00 00 00 00 00 000 0 0 01 0 00 00 00 00 00 00 0 0 00 00 00 00 00 00 0000 0 000 0 18 18 multiplication saturated output result rounded output result + =
12?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 architecture pipeline registers the output from the multiplier can feed a pipeline register or this register can be bypassed. pipeline registers may be implemented for any multiplier size and increase the dsp block?s maximum performance, especially when using the subsequent dsp block adder stages. pipeline registers split up the long signal path between the adder/subtractor/accumulator bloc k and the adder /output block, creating two shorter paths. adder/output block the adder/output block ha s the following elements: an adder/subtractor/accumulator block a summation block an output select multiplexer output registers figure 12?7 shows the adder/output block architecture. the adder/output block can be configured as: an output interface an accumulator which ca n be optionally loaded a one-level adder a two-level adder with dynamic addition/subtraction control on the first-level adder the final stage of a 36-bit multiplier, 9 9 complex multiplier, or 18 18 complex multiplier the output select multiplexer sets the output configuration of the dsp block. the output registers can be us ed to register the output of the adder/output block. 1 the adder/output block cannot be used independently from the multiplier.
altera corporation 12?17 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?7. adder/output block architecture note (1) notes to figure 12?7 : (1) the adder/output block is in 18 18 mode. in 9 9 mode, there are four adder/subtractor blocks and two summation blocks. (2) you can send these signals through a pipeline regi ster. the pipeline length can be set to 1 or 2. (3) q1.15 inputs are not available in 9 9 or 36 36 modes. adder/subtractor/accumulator block the adder/subtractor/accumulator block is the first level adder stage of the adder/output block. this block ca n be configured as an accumulator or as an adder/subtractor. adder/ subtractor/ accumulator 1 summation result a / accum_sload_upper_data result b result d addnsub1 (2) addnsub3 (2) signa (2) signb (2) accum_sload1 (2) accumulator feedback overflow0 adder/ output select multiplexer output registers subtractor/ accumulator 2 accumulator feedback overflow1 adder1_round (2) adder3_round (2) accum_sload0 (2) output register bloc k q1.15 rounding q1.15 rounding result c / accum_sload_upper_data (3) (3)
12?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 architecture accumulator when the adder/subtractor/accumu lator is configured as an accumulator, the output of the adder/output block feeds back to the accumulator as shown in figure 12?7 . the accumulator can be set up to perform addition only, subtraction only or the addnsub signal can be used to dynamically control the accu mulation direction. a logic 1 value on the addnsub signal indicates that the accumulator is performing addition while a logic 0 value indicates subtraction. each accumulator can be cleared by ei ther clearing the dsp block output register or by using the accum_sload signal. the accumulator clear using the accum_sload signal is independent from the resetting of the output registers so the accumulation can be cleared and a new one can begin without losing any clock cycles. the accum_sload signal controls a feedback multiplexer that specifie s that the output of the multiplier should be summed with a zero instea d of the accumulator feedback path. the accumulator can also be initiali zed/preloaded with a non-zero value using the accum_sload signal and the accum_sload_upper_data bus with one clock cycle latency. prel oading the accumulator is done by adding the result of the multiplie r with the value specified on the accum_sload_upper_data bus. as in the case of the accumulator clearing, the accum_sload signal specifies to the feedback multiplexer that the accum_sload_upper_data signal should feed the accumulator instead of the accu mulator feedback signal. the accum_sload_upper_data signal only loads the upper 36-bits of the accumulator. to load the entire accumulator, the value for the lower 16-bits must be sent through the mult iplier feeding that accumulator with the multiplier set to perform a multiplication by one. the overflow signal will go high on the positive edge of the clock when the accumulator detects an overflow or underflow. the overflow signal will stay high for only one clock cycl e after an overflow or underflow is detected even if the overflow or underflow condition is still present. a latch external to the dsp block has to be used to preserve the overflow signal indefinitely or until the latch is cleared. the dsp blocks support q1.15 input fo rmat saturation and rounding in each accumulator. the following signals are available that can control if saturation or rounding or both is performed to the output of the accumulator: accum_round accum_saturation accum_is_saturated output
altera corporation 12?19 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices each dsp block has two sets of accum_round and accum_saturation signals which control if rounding or saturation is performed on the accumulator output respectively (one set of signals for each accumulator). rounding and saturation of the accumulator output is only available when implementing an 16 16 multiplier-accumulator to conform to the bit widths required fo r q1.15 input format computation. a logic 1 value on the accum_round and accum_saturation signal indicates that rounding or saturation is performed while a logic 0 indicates that no rounding or saturati on is performed. a logic 1 value on the accum_is_saturated output signal tells you that saturation has occurred to the result of the accumulator. figure 12?10 shows the dsp block configured to perform multiplier- accumulator operations. adder/subtractor the addnsub1 or addnsub3 signals specify whether you are performing addition or subtraction. a logic 1 value on the addnsub1 or addnsub3 signals indicates that the adder/subtra ctor is performing addition while a logic 0 value indicates subtraction. these signals can be dynamically controlled using logic external to th e dsp block. if the first stage is configured as a subtractor, the output is a ? b and c ? d. the adder/subtractor block share the same signa and signb signals as the multiplier block. the signa and signb signals can be pipelined with a latency of one or two clock cycles or not. the dsp blocks support q1.15 input format rounding (not saturation) after each adder/subtractor. the addnsub1_round and addnsub3_round signals determine if roun ding is performed to the output of the adder/subtractor. the addnsub1_round signal controls the rounding of the top adder/subtractor and the addnsub3_round signal controls the rounding of the bottom adder/subtra ctor. rounding of the adder output is only available when implementing an 16 16 multiplier-adder to conform to the bit widths required fo r q1.15 input format computation. a logic 1 value on the addnsub_round signal indicates that rounding is performed while a logic 0 indicates that no rounding is performed. summation block the output of the adder/subtractor block feeds an optional summation block, which is an adder block that sums the outputs of both adder/subtractor bl ocks. the summation block is used when more than two multiplier results are summed. this is useful in applications such as fir filtering.
12?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 architecture output select multiplexer the outputs of the different elemen ts of the adder/output block are routed through an output select multiplexer. depending on the operational mode of the dsp block, the output multiplexer selects whether the outputs of the dsp blocks comes from the outputs of the multiplier block, th e outputs of the adder/subt ractor/accumulator, or the output of the summation block. the output select multiplier configuration is set automatically by software, based on the dsp block operational mode you specify. output registers you can use the output registers to register the dsp block output. the following signals can control each output register within the dsp block: clock[3..0] ena[3..0] aclr[3..0] the output registers can be used in any dsp block operational mode. 1 the output registers form part of the accumulator in the multiply-accumulate mode. f refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook for more information on the dsp block routing and interface.
altera corporation 12?21 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices operational modes the dsp block can be used in one of four basic operational modes, or a combination of two modes, depend ing on the application needs. table 12?7 shows the four basic operational modes and the number of multipliers that can be implemen ted within a single dsp block depending on the mode. the quartus ii software includes mega functions used to control the mode of operation of the multipliers. after you make the appropriate parameter settings using the megafunction?s megawizard ? plug-in manager, the quartus ii software automatical ly configures the dsp block. stratix ii and stratix ii gx dsp blocks can operate in different modes simultaneously. for example, a single dsp block can be broken down to operate a 9 9 multiplier as well as an 18 18 multiplier-adder where both multiplier's input a and input b have the same sign representations. this increases dsp block resource efficiency and allows you to implement more multipliers within a stratix ii or stratix ii gx device. the quartus ii software automatically places multipliers that can share the same dsp block resources within the same block. additionally, you can set up each stratix ii or stratix ii gx dsp block to dynamically switch between the following three modes: up to four 18-bit independent multipliers up to two 18-bit multiplier-accumulators one 36-bit multiplier table 12?7. dsp block operational modes mode number of multipliers 9 9 18 18 36 36 simple multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier multiply accumulate - two 52-bit multiply- accumulate blocks - two-multiplier adder four two-multiplier adder (two 9 9 complex multiply) two two-multiplier adder (one 18 18 complex multiply) - four-multiplier adder two four-multiplier adder one four-multiplier adder -
12?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 operational modes each half of a stratix ii or stratix ii gx dsp block has separate mode control signals, which allows you to implement multiple 18-bit multipliers or multiplier-accumulators within the same dsp block and dynamically switch them independen tly (if they are in separate dsp block halves). if the design requires a 36-bit multiplier, you must switch the entire dsp block to accommodate th e it since the multiplier requires the entire dsp block. the smallest input bit width that supports dynamic mode switching is 18 bits. simple multiplier mode in simple multiplier mode, the dsp block performs individual multiplication operations for general-purpose multipliers and for applications such as computing eq ualizer coefficient updates which require many individual multiplication operations. 9- and 18-bit multipliers each dsp block multiplier can be configured for 9- or 18-bit multiplication. a single dsp block can support up to eight individual 9 9 multipliers or up to four individual 18 18 multipliers. for operand widths up to 9-bits, a 9 9 multiplier will be implemented and for operand widths from 10- to 18-bits, an 18 18 multiplier will be implemented. figure 12?8 shows the dsp block in the simple multiplier operation mode.
altera corporation 12?23 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?8. simple multiplier mode notes to figure 12?8 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) this signal has the same latency as the data path. (3) the rounding and saturation is only supported in 18- 18-bit signed multiplication for q1.15 inputs. the multiplier operands can accept sign ed integers, unsign ed integers or a combination of both. the signa and signb signals can be changed dynamically and can be registered in the dsp block. additionally, the multiplier inputs and result can be registered independently. the pipeline registers within the dsp block can be used to pipeline the multiplier result, increasing the perf ormance of the dsp block. 36-bit multiplier the 36-bit multiplier is also a simple multiplier mode but uses the entire dsp block, including the adder/ output block to implement the 36 36-bit multiplication operation. th e device inputs 18-bit sections of the 36-bit input into the four 18-bit multipliers. the adder/output block adds the partial produc ts obtained from the multipliers using the summation block. pipeline registers can be used between the multiplier stage and the summation block to sp eed up the multiplication. the 36 36-bit multiplier supports signed, unsigned as well as mixed sign multiplication. figure 12?9 shows the dsp bl ock configured to implement a 36-bit multiplier. clrn dq ena data a data b shiftoutb shiftouta shiftina shiftinb aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) clrn dq ena clrn dq ena sourcea sourceb q1.15 round/ saturate mult_saturate (1) mult_round (1) output register data out mult_is_saturated (2 ) (3) clrn dq ena clrn dq ena multiplier block dsp block
12?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 operational modes figure 12?9. 36-bit multiplier notes to figure 12?9 : (1) these signals are either not registered or registered once to match the pipeline. (2) these signals are either not registered, registered once , or registered twice to match the data path pipeline. clrn dq ena a[17..0] a[17..0] b[17..0] b[17..0] a[35..18] a[35..18] b[35..18] b[35..18] aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena data out 36 36 multiplier adder signa ( 2 ) signb ( 2 ) 18 18 18 18 18 18 18 18
altera corporation 12?25 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices the 36-bit multiplier is useful for appl ications requiring more than 18-bit precision, for example, for mantissa multiplication of precision floating- point arithmetic applications. multiply accumulate mode in multiply accumulate mode, the output of the multiplier stage feeds the adder/output block which is configured as an accumulator or subtractor. figure 12?10 shows the dsp block configured to operate in multiply accumulate mode. figure 12?10. multiply accumulate mode notes to figure 12?10 : (1) the signa and signb signals are the same in the multipli er stage and the adder/output block. (2) these signals are not registered or regist ered once to match the data path pipeline. (3) you can send these signals through either one or two pipeline registers. (4) these signals match the latency of the data path. a single dsp block can implemen t up to two independent 18-bit multiplier accumula tors. the quartus ii soft ware implements smaller multiplier accumulators by tying the un used lower-order bits of the 18-bit multiplier to ground. the multiplier accumulator output ca n be up to 52-bits wide to account for a 36-bit multiplier result with 16-bi ts of accumulation. in this mode, the dsp block uses outp ut registers and the accum_sload and overflow clrn dq ena clrn dq ena data a data b data out overflow shiftoutb shiftouta shiftina shiftinb clrn dq ena clrn dq ena accumulator accum_sload (3) dq ena q1.15 round/ saturate accum_sload_upper_data (3) q1.15 round/ saturate mult_saturate (2) mult_round (2) accum_saturate (3) accum_round (3) addnsub (3) signa (1) , (3) signb (1) , (3) signa (1) , (2) signb (1) , (2) aclr[3..0] clock[3..0] ena[3..0] mult_is_saturated (4) accum_is_saturated (4 ) dq ena dq ena dq ena
12?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 operational modes signals. the accum_sload signal can be used to clear the accumulator so that a new accumulation operation can begin without losing any clock cycles. this signal can be unregistered or registered once or twice. the accum_sload signal can also be used to preload the accumulator with a value specified on the accum_sload_upper_data signal with a one clock cycle penalty. the accum_sload_upper_data signal only loads the upper 36-bits (bits [51..16] of the accumulator). to load the entire accumulator, the value for the lower 16-bits (bits [15..0] ) must be sent through the multiplier feeding that ac cumulator with the multiplier set to perform a multiplication by one. bits [17..16] are overlapped by both the accum_sload_upper_data signal and the multiplier output. either one of these signals can be used to load bits [17..16] . the overflow signal indicates an overflow or underflow in the accumulator. this signal gets upda ted every clock cycle due to a new accumulation operation every cycle. to preserve the sign al, an external latch can be used. the addnsub signal can be used to specify if an accumulation or subtraction is performed dynamically. 1 the dsp block can implement just an accumulator (without multiplication) by specifying a multiply by one at the multiplier stage followed by an accumula tor to force the quartus ii software to implement the func tion within the dsp block. multiply add mode in multiply add mode, the output of the multiplier stage feeds the adder/output block which is configured as an adder or subtractor to sum or subtract the outputs of two or mo re multipliers. the dsp block can be configured to implement either a tw o-multiply add (where the outputs of two multipliers are added/subtracted together) or a four-multiply add function (where the outputs of four multipliers are added or subtracted together). 1 the adder block within the dsp bl ock can only be used if it follows multiplication operations. two-multiplier adder in the two-multiplier adder configuration, the dsp block can implement four 9-bit or smaller multiplier adde rs or two 18-bit multiplier adders. the adders can be configured to take the sum of both multiplier outputs or the difference of both multiplier ou tputs. you have the option to vary the summation/subtraction operation dynamically. these multiply add functions are useful for applications such as ffts and complex fir filters. figure 12?11 shows the dsp block configured in the two-multiplier adder mode.
altera corporation 12?27 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?11. two-multiplier adder mode notes to figure 12?11 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) you can send these signals through a pipeline regi ster. the pipeline length can be set to 1 or 2. (3) these signals match the latency of the data path. complex multiply the dsp block can be configured to implement complex multipliers using the two-multiplier adder mode. a si ngle dsp block can implement one 18 18-bit complex multiplier or two 9 9-bit complex multipliers. a complex multiplicatio n can be written as: ( a + j b ) ( c + j d ) = (( a c ) ? ( b d )) + j (( a d ) + ( b c )) to implement this complex multiplication within the dsp block, the real part (( a c ) ? ( b d )) is implemented using two multipliers feeding one subtractor block while the imaginary part (( a d ) + ( b c )) is implemented using another two multipliers feedin g an adder block, for data up to 18-bits. figure 12?12 shows an 18-bit complex multiplication. for data widths up to 9-bits, a dsp block can perform two separate complex adder/ subtractor/ accumulator 1 prn clrn dq ena q1.15 round/ saturate data a 1 data b 1 shiftinb shiftina clrn dq ena clrn dq ena shiftouta shiftoutb clrn dq ena data out 1 aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) mult_saturate (1) mult_round (1) signa (2) signb (2) addnsub_round (2) addnsub1 (2) mult1_is_saturated (3 ) mult0_is_saturated (3 ) q1.15 rounding prn clrn dq ena q1.15 round/ saturate data a 2 data b 2 dq ena clrn dq ena dq ena dq ena dq ena dq ena
12?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 operational modes multiplication operations using eight 9-bit multipliers feeding four adder/subtractor/accumulator bloc ks. resources external to the dsp block must be used to route the correct real and imaginary input components to the appropriate multipli er inputs to perform the correct computation for the comple x multiplication operation. figure 12?12. complex multiplier us ing two-multiplier adder mode four-multiplier adder in the four-multiplier adder configur ation, the dsp block can implement one 18 18 or two individual 9 9 multiplier adders. these modes are useful for implementing one-dimensional and two-dimensional filtering applications. the four-multiplier adder is performed in two addition stages. the outputs of two of the four multipliers are initially summed in the two first-stage adder/ subtractor/accumulator blocks. the results of these two adder/subtractor/accumulator blocks are then summed in the final stage summation block to prod uce the final four-multiplier adder result. figure 12?13 shows the dsp block configured in the four- multiplier adder mode. subtractor 36 36 18 18 18 37 a 18 (real part) adder 36 36 18 18 37 (imaginary part) 18 18 18 dsp block (a c) ? (b d) (a d) + (b c) 18 18 18 b d a d b c c
altera corporation 12?29 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?13. four-multiplier adder mode notes to figure 12?13 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) you should send these signals through the pipeline register to match the latency of the data path. (3) these signals match the latency of the data path. (4) the rounding and saturation is only supported in 18- 18-bit signed multiplication for q1.15 inputs. signa (2) signb (2) addnsub1/3_round (2) addnsub3 (2) addnsub1 (2) adder adder/ subtractor/ accumulator 1 prn clrn dq ena q1.15 round/ saturate data a 1 data b 1 shiftinb shiftina clrn dq ena clrn dq ena aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) mult_saturate (1) mult_round (1) mult1_is_saturated (3) mult0_is_saturated (3 ) q1.15 rounding prn clrn dq ena prn clrn dq ena shiftouta shiftoutb data a 2 data b 2 dq ena clrn dq ena adder/ subtractor/ accumulator 1 data a 1 data b 1 clrn dq ena clrn dq ena clrn dq ena data out 1 mult1_is_saturated (3) mult0_is_saturated (3) q1.15 rounding data a 2 data b 2 dq ena clrn dq ena prn clrn dq ena q1.15 round/ saturate prn clrn dq ena prn clrn dq ena q1.15 round/ saturate prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena q1.15 round/ saturate prn clrn dq ena (4) (4) (4) (4) (4) (4)
12?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 operational modes fir filter the four-multiplier adder mode can be used to implement fir filter and complex fir filter applications. to do this, the dsp block is set up in a four-multiplier adder mode with one se t of input registers configured as shift registers using the dedicated shift register chain. the set of input registers configured as shift registers will contain the input data while the inputs configured as regular inputs will hold the filter coefficients. figure 12?14 shows the dsp block configured in the four-multiplier adder mode using input shift registers.
altera corporation 12?31 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices figure 12?14. fir filter implemented us ing the four-multiplier adder m ode with input shift registers data a coefficient 0 clrn dq ena clrn dq ena clrn dq ena a[ n ] coefficient 0 (to adder) coefficient 1 clrn dq ena clrn dq ena clrn dq ena a[ n ? 1] coefficient 1 (to adder) coefficient 2 clrn dq ena clrn dq ena clrn dq ena a[ n ? 2] coefficient 2 (to adder) 18 18 18 18
12?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 software support the built-in input shift register chai n within the dsp block eliminates the need for shift registers externally to the dsp block in logic elements (les). this architecture feature simplifies the filter design and improves the filter performance because all the filter circuitry is localized within the dsp block. 1 input shift registers for the 36-bi t simple multiplier mode have to be implemented using external registers to the dsp block. a single dsp block can implement a fo ur tap 18-bit fir filter. for filters larger than four taps, the dsp blocks can be cascaded with additional adder stages implemented using les. software support altera provides two distinct method s for implementing various modes of the dsp block in your design: instan tiation and inferenc e. both methods use the following three quartus ii megafunctions: lpm_mult altmult_add altmult_accum you can instantiate the megafunction s in the quartus ii software to use the dsp block. alternatively, with in ference, you can create a hdl design an synthesize it using a third-party synthesis tool like leonardospectrum or synplify or quartus ii native sy nthesis that infers the appropriate megafunction by recognizing multipliers, multiplier adders, and multiplier accumula tors. using either method, the quartus ii software maps the functionality to the ds p blocks during compilation. f see quartus ii on-line help for inst ructions on using the megafunctions and the megawizard plug-in manager. f for more information, see the synthesis section in design and synthesis (volume 1) of the quartus ii development software handbook . conclusion the stratix ii and stratix ii gx de vice dsp blocks are optimized to support dsp applications requiring high data throughput such as fir filters, fft functions and encoders. th ese dsp blocks are flexible and can be configured to implement one of several operational modes to suit a particular application. the built-in shift register chain, adder/subtractor/accumulator block and the su mmation block minimizes the amount of external logic requir ed to implement these functions, resulting in efficient resource utilization and improved performance and data throughput fo r dsp applications. the quartus ii
altera corporation 12?33 october 2007 stratix ii gx device handbook, volume 2 dsp blocks in stratix ii & stratix ii gx devices software, together with the leonardospectrum ? and synplify software provide a complete and easy-to-us e flow for implementing these multiplier functions in the dsp blocks. referenced documents this chapter references the following documents: an 306: implementing mult ipliers in fpga devices design and synthesis (volume 1) of the quartus ii development software handbook stratix ii architectur e chapter in volume 1 of the stratix ii device handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii device family data sheet in volume 1 of the stratix ii device handbook stratix ii gx device family data sheet in volume 1 of the stratix ii gx device handbook document revision history table 12?8 shows the revision history for this chapter. table 12?8. document revision history date and document version changes made summary of changes october 2007 v2.2 added the ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 11. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? february 2007 v2.1 added the ?document revision history? section to this chapter. ? no change formerly chapter 10. chapter number change only due to chapter addition to section i in february 2006; no content change. ? october 2005 v2.0 added chapter to the stratix ii gx device handbook . ?
12?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history
altera corporation section vi?1 preliminary section vi. configuration& remote system upgrades this section provides configuration information for all of the supported configuration schemes for stratix ? ii gx devices. these configuration schemes use either a microprocessor, configuration device, or download cable. there is detailed information on how to design with altera enhanced configuration devices which includes information on how to manage multiple configuration files and access the on-chip flash memory space. the last chapter shows designers how to perform remote and local upgrades for their designs. this section contains the following chapters: chapter 13, configuring stratix ii & stratix ii gx devices chapter 14, remote system upgrades with stratix ii & stratix ii gx devices chapter 15, ieee 1149.1 (jtag) boun dary-scan testing for stratix ii & stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section vi?2 altera corporation preliminary configuration& remote system upgrades stratix ii gx device handbook, volume 2
altera corporation 13?1 october 2007 13. configuring stratix ii & stratix ii gx devices introduction stratix ? ii and stratix ii gx devices use sram cells to store configuration data. because sram memory is vola tile, configuration data must be downloaded to stratix ii and stratix i i gx devices each time the device powers up. stratix ii and stratix ii gx devices can be configured using one of five configuration schemes: the fast passive parallel (fpp), active serial (as), passive serial (ps), passive parallel asynchronous (ppa), and joint test action group (jtag) conf iguration schemes. all configuration schemes use either an external controller (for example, a max ? ii device or microprocessor) or a configuration device. configuration devices the altera enhanced configuratio n devices (epc16, epc8, and epc4) support a single-device configuration solution for high-density devices and can be used in the fpp and ps configuration schemes. they are isp-capable through its jtag interf ace. the enhanced configuration devices are divided into two major blocks, the controller and the flash memory. f for information on enhanced conf iguration devices, refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook . the altera serial configuration de vices (epcs64, ep cs16, and epcs4) support a single-device configuration solution for stratix ii and stratix ii gx devices and are used in the as configuration scheme. serial configuration devices offer a low cost, low pin count configuration solution. f for information on serial configuration devices, refer to the serial configuration devices (epcs1, epcs 4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . the epc2 configuration devices provide configuration support for the ps configuration scheme. the epc2 device is isp-capable through its jtag interface. the epc2 device can be cascaded to hold large configuration files. f for more information on epc2 configuration devices, refer to the configuration devices for sram -based lut devices data sheet chapter in volume 2 of the configuration handbook . sii52007-4.5
13?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 introduction the configuration scheme is selected by driving the stratix ii or stratix ii gx device msel pins either high or low as shown in table 13?1 . the msel pins are powered by the v ccio power supply of the bank they reside in. the msel[3..0] pins have 9-k internal pull-down resistors that are always active. during power-on reset (por) and during reconfiguration, the msel pins have to be at lvttl v il and v ih levels to be considered a logic low and logic high. 1 to avoid any problems with detecting an incorrect configuration scheme, hard-wire the msel[] pins to v ccpd and gnd, without any pull-up or pull-down re sistors. do not drive the msel[] pins by a microprocessor or another device. table 13?1. stratix ii and stratix ii gx configuration schemes (part 1 of 2) configuration scheme msel3 msel2 msel1 msel0 fast passive parallel (fpp) 0000 passive parallel asynchronous (ppa) 0001 passive serial (ps) 0010 remote system upgrade fpp (1) 0100 remote system upgrade ppa (1) 0101 remote system upgrade ps (1) 0110 fast as (40 mhz) (2) 1000 remote system upgrade fast as (40 mhz) (2) 1001 fpp with decompression and/or design security feature enabled (3) 1011 remote system upgrade fpp with decompression and/or design security feature enabled (1) , (3) 1100 as (20 mhz) (2) 1101 remote system upgrade as (20 mhz) (2) 1110 jtag-based configuration (5) (4) (4) (4) (4)
altera corporation 13?3 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices stratix ii and stratix ii gx devices offer design security, decompression, and remote system upgrade features. design security using configuration bitstream encryption is available in stratix ii and stratix ii gx devices, which protects your designs. stratix ii and stratix ii gx devices can receive a compressed configuration bi t stream and decompress this data in real-time, reducing storage requ irements and configuration time. you can make real-time system upgrades from remote locations of your stratix ii and stratix ii gx designs with the remote system upgrade feature. table 13?2 and table 13?3 show the uncompressed configuration file sizes for stratix ii and stratix ii gx devices, respectively. notes to table 13?1 : (1) these schemes require that you drive the runlu pin to specify either remote update or local update. for more information about remote system upgrades in stratix ii devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . (2) only the epcs16 and epcs64 devices support up to a 40 mhz dclk . other epcs devices support up to a 20 mhz dclk . refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet for more information. (3) these modes are only supported when using a max ii device or a microprocessor with flash memory for configuration. in these modes, the host system must output a dclk that is 4 the data rate. (4) do not leave the msel pins floating. connect them to v ccpd or ground. these pins support the non-jtag configuration scheme used in production. if only jtag configuration is used, you should connect the msel pins to ground. (5) jtag-based configuration takes precedence ov er other configuration schemes, which means msel pin settings are ignored. table 13?1. stratix ii and stratix ii gx configuration schemes (part 2 of 2) configuration scheme msel3 msel2 msel1 msel0 table 13?2. stratix ii uncompressed .rbf sizes notes (1) , (2) device data size (bits) data size (mbytes) ep2s15 4,721,544 0.590 ep2s30 9,640,672 1.205 ep2s60 16,951,824 2.119 ep2s90 25,699,104 3.212 ep2s130 37,325,760 4.666 ep2s180 49,814,760 6.227 notes to ta b l e 1 3 ? 2 : (1) these values are final. (2) .rbf : raw binary file.
13?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 configuration features use the data in table 13?2 to estimate the file size before design compilation. different configuration file formats, such as a hexidecimal ( .hex ) or tabular text file ( .ttf ) format, will have different file sizes. however, for any specific version of the quartus ? ii software, any design targeted for the same device will have the same uncompressed configuration file size. if you are using compression, the file size can vary after each compilation because the compression ratio is dependent on the design. this chapter explains the stratix ii and stratix ii gx device configuration features and describes how to co nfigure stratix ii and stratix ii gx devices using the supported configuration schemes. this chapter provides configuration pin descriptions and the stratix ii and stratix ii gx device configuration file fo rmats. in this chapter, the generic term device(s) includes all stratix ii and stratix ii gx devices. f for more information on setting device configuration options or creating configuration files, refer to software settings in volume 2 of the configuration handbook . configuration features stratix ii and stratix ii gx devices offer configuration data decompression to reduce configuration f ile storage, design security using data encryption to protect your design s, and remote system upgrades to allow for remotely updating your stratix ii and stratix ii gx designs. table 13?4 summarizes which configuration fe atures can be used in each configuration scheme. table 13?3. stratix ii gx uncompressed .rbf sizes note (1) device data size (bits) data size (mbytes) ep2sgx30c ep2sgx30d 9,640,672 1.205 ep2sgx60c ep2sgx60d ep2sgx60e 16,951,824 2.119 ep2sgx90e ep2sgx90f 25,699,104 3.212 ep2sgx130g 37,325,760 4.666 note to table 13?3 : (1) .rbf : raw binary file.
altera corporation 13?5 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices configuration data decompression stratix ii and stratix ii gx devices support configuration data decompression, which saves configur ation memory space and time. this feature allows you to store comp ressed configuration data in configuration devices or other memory and transmit this compressed bit stream to stratix ii and stratix ii gx devices. during configuration, stratix ii and stratix ii gx devices automatically recognize the compressed file format and decompress es the bit stream in real time and programs its sram cells. 1 data indicates that compression typically reduces configuration bit stream size by 35 to 55 % . stratix ii and stratix ii gx devices support decompression in the fpp (when using a max ii device/micro processor + flas h), as, and ps configuration schemes. decompression is not supported in the ppa configuration scheme nor in jtag-based configuration. table 13?4. stratix ii and stratix i i gx configuration features configuration scheme configuration method desi gn security decompression remote system upgrade fpp max ii device or a microprocessor with flash memory v (1) v (1) v enhanced configuration device v (2) v as serial configuration device vvv (3) ps max ii device or a microprocessor with flash memory vvv enhanced configuration device v v v download cable vv ppa max ii device or a microprocessor with flash memory v jtag max ii device or a microprocessor with flash memory notes to table 13?4 : (1) in these modes, the host system must send a dclk that is 4 the data rate. (2) the enhanced configuration device decompression feature is available, while the stratix ii and stratix ii gx decompression feature is not available. (3) only remote update mode is supported when using the as configuration scheme. local update mode is not supported.
13?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 configuration features 1 when using fpp mode, the inte lligent host must provide a dclk that is 4 the data rate. therefore, the configuration data must be valid for four dclk cycles. the decompression feature supported by stratix ii and stratix ii gx devices is different from the decompression feature in enhanced configuration devices (epc16, epc8, and epc4 devices), although they both use the same compression al gorithm. the data decompression feature in the enhanced configurat ion devices allows them to store compressed data and decompress the bi tstream before transmitting it to the target devices. when using stratix ii and stratix ii gx devices in fpp mode with enhanced configuration devices, the decompression feature is available only in the enhanced config uration device, not the stratix ii or stratix ii gx device. in ps mode, use the stratix ii or stratix ii gx decompression feature because sending compressed configuration data reduces configuration time. do not use both the stratix i i or stratix ii gx device and the enhanced configuration device decompression features simultaneously. the compression algorithm is not intended to be recursive and could expand the configuration file in stead of compressing it further. when you enable compression, th e quartus ii software generates configuration files with compressed configuration data. this compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time need ed to transmit the bitstream to the stratix ii or stratix ii gx device. the time required by a stratix ii or stratix ii gx device to decompress a configuration file is less than the time needed to transmit the co nfiguration data to the device. there are two ways to enable compression for stratix ii and stratix ii gx bitstreams: before design compilation (in the compiler settings menu) and after design compilation (in the convert programming files window). to enable compression in the project?s compiler settings, select device under the assignments menu to bring up the settings window. after selecting your stratix ii or stratix ii gx device, open the device & pin options window, and in the general settings tab enable the check box for generate compressed bitstreams (as shown in figure 13?1 ).
altera corporation 13?7 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices figure 13?1. enabling compression for strati x ii and stratix ii gx bitstreams in compiler settings compression can also be enabled when creating programming files from the convert programming files window. 1. click convert programming files (file menu). 2. select the programming file type (pof, sram hexout, rbf, or ttf). 3. for pof output files, select a configuration device. 4. in the input files to convert box, select sof data . 5. select add file and add a stratix ii or stratix ii gx device sof(s).
13?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 configuration features 6. select the name of the file you added to the sof data area and click properties . 7. check the compression check box. when multiple stratix ii or strati x ii gx devices are cascaded, you can selectively enable the compression feat ure for each device in the chain if you are using a serial configuration scheme. figure 13?2 depicts a chain of two stratix ii or stratix ii gx devices. the first stratix ii or stratix ii gx device has compression enabled and therefore receives a compressed bit stream from the configuration de vice. the second stratix ii or stratix ii gx device has the compression feature disabled and receives uncompressed data. in a multi-device fpp configuration chain all stratix ii or stratix ii gx devices in the chain must either enable of disable the decompression feature. you can not selectively enable the compression feature for each device in the chain because of the data and dclk relationship. figure 13?2. compressed and uncompressed configuration data in the same configuration file you can generate programming files for this setup from the convert programming files window (file menu) in the quartus ii software. design security using config uration bitstream encryption stratix ii and stratix ii gx devices are th e industry?s first devices with the ability to decrypt a configuratio n bitstream using the advanced encryption standard (aes) algorith m?the most advanced encryption algorithm available today. when usin g the design security feature, a nce gnd nceo de c ompression controller stratix ii or stratix ii gx fpga nce nceo n.c. s er i a l c on f i g u rat ion data c om pressed u n c om pressed c on f i g u rat ion data c on f i g u rat ion data serial or enhanced confi g uration device stratix ii or stratix ii gx fpga
altera corporation 13?9 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices 128-bit security key is stored in the stratix ii or stratix ii gx device. in order to successfully configure a strati x ii or stratix ii gx device that has the design security feature enabled, it must be configured with a configuration file that wa s encrypted using the same 128-bit security key. the security key can be stored in non- volatile memory inside the stratix ii or stratix ii gx device. this non-volatile memory does not require any external devices, such as a battery back-up, for storage. 1 when using a serial configuration scheme such as passive serial (ps) or active serial (as), config uration time is the same whether or not the design security feature is enabled. if the fast passive parallel (fpp) scheme is used with the design security or decompression feature, a 4 dclk is required. this results in a slower configuration time when compared to the configuration time of an fpga that has neither the design security, nor decompression feature enabled. for more information about this feature, contact al tera applications group. remote system upgrade stratix ii and stratix ii gx devices feature remote and local update. f for more information about this feature, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook power-on reset circuit the por circuit keeps the entire syst em in reset until the power supply voltage levels have stabilized on power-up. upon power-up, the device does not release nstatus until v ccint , v ccpd , and v ccio of banks 3, 4, 7, and 8 are above the device?s por trip point. on power down, v ccint is monitored for brown-out conditions. the passive serial (ps) mode ( msel[3,2,1,0] = 0010 ) and the fast passive parallel (fpp) mode ( msel[3,2,1,0] = 0000 ) always set bank 3 to use the lower por trip point consistent with 1.8- and 1.5-v signaling, regardless of the vccsel setting. for all other configuration modes, vccsel selects the por trip-point level. refer to the section ?vccsel pin? on page 13?10 for more details. in stratix ii devices, a pin-selectable option porsel is provided that allows you to select between a typi cal por time setting of 12 ms or 100 ms. in both cases, you can extend the por time by using an external component to assert the nstatus pin low.
13?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 configuration features v ccpd pins stratix ii and stratix ii gx devices also offer a new power supply, v ccpd , which must be connected to 3.3-v in order to power the 3.3-v/2.5-v buffer available on the configurat ion input pins and jtag pins. v ccpd applies to all the jtag input pins ( tck , tms , tdi , and trst ) and the configuration pins when vccsel is connected to ground. refer to table 13?5 for information on the pins affected by vccsel . 1 v ccpd must ramp-up from 0-v to 3.3-v within 100 ms. if v ccpd is not ramped up within this sp ecified time, your stratix ii or stratix ii gx device will not configure successfully. if your system does not allow for a v ccpd ramp-up time of 100 ms or less, you must hold nconfig low until all power supplies are stable. vccsel pin the vccsel pin selects the type of input buffer used on configuration input pins and it selects the por trip point voltage level for v ccio bank 3 powered by vccio3 pins. 1 for more information, refer to table 13?24 on page 13?105 . the configuration input pins and the pll_ena pin ( table 13?5 ) have a dual buffer design. these pins have a 3.3-v/2.5-v input buffer and a 1.8-v/1.5-v input buffer. the vccsel input pin selects which input buffer is used during configuratio n. the 3.3-v/2.5-v input buffer is powered by v ccpd , while the 1.8-v/1.5-v input buffer is powered by v ccio . after configuration, the dual-p urpose configuration pins are powered by the v ccio pins of the bank in which they reside. table 13?5 shows the pins affected by vccsel .
altera corporation 13?11 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices vccsel is sampled during power-up. therefore, the vccsel setting cannot change on the fly or during a reconfiguration. the vccsel input buffer is powered by v ccint and has an internal 5-k pull-down resistor that is always active. 1 vccsel must be hardwired to v ccpd or gnd. a logic high selects the 1.8-v/1.5-v input buffer, and a logic low selects the 3.3-v/2.5-v input buffer. vccsel should be set to comply with the logic levels driven out of the configuration device or max ii device or a microprocessor with flash memory. vccsel also sets the por trip point for i/ o bank 3 to ensure that this i/o bank has powered up to the appropriate voltage levels before configuration begins. for pa ssive serial (ps) mode ( msel[3..0] = 0010 ) and for fast passive parallel (fpp) mode ( msel[3..0] = 0000 ) the por circuitry selects the trip point associ ated with 1.5-v/1.8-v signaling. for all other configuration modes defined by msel[3..0] settings (other table 13?5. pins affected by the voltage level at vccsel pin vccsel = low (connected to gnd) vccsel = high (connected to v ccpd ) nstatus (when used as an input) 3.3/2.5-v input buffer is selected. input buffer is powered by v ccpd . 1.8/1.5-v input buffer is selected. input buffer is powered by v ccio of the i/o bank. these input buffers are 3.3 v tolerant. nconfig conf_done (when used as an input) data[7..0] nce dclk (when used as an input) cs nws nrs ncs clkusr dev_oe dev_clrn runlu pll_ena
13?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 configuration features than 00x0 (msel[1] = x , ?don't care?), vccsel=gnd selects the higher i/o bank 3 por trip point for 2.5-v/3.3-v signaling and vccsel=vccpd selects the lower i/o bank 3 por trip point associated with 1.5-v/1.8-v signaling. for all configuration modes with msel[3..0] not equal to 00x0 (msel[1] = x , ?don't care?), if vccio of configuration bank 3 is powered by 1.8-v or 1.5-v and vccsel = gnd , the voltage supplied to this i/o bank(s) may never reach the por trip point, which prevents the device from beginning configuration. if the vccio of i/o bank 3 is powered by 1.5- or 1.8-v and the configuration signals used require 3.3- or 2.5-v signaling, you should set vccsel to vccpd to enable the 1.8-/1.5-v inpu t buffers for configuration. the 1.8-v/1.5-v input buffers are 3.3-v tolerant. 1 the fast passive parallel (fpp) and passive serial (ps) modes always enable bank 3 to use the por trip point to be consistent with 1.8- and 1.5-v signal ing, regardless of the vccsel setting. table 13?6 shows how you should set vccsel depending on the configuration mode, the voltage level on vccio3 pins that power bank 3, and the supported config uration input voltages. table 13?6. supported v ccsel setting based on mode, vccio3, and input configuration voltage configuration mode v ccio (bank 3) supported configuration input voltages v ccsel all modes 3.3-v/2.5-v 3.3-v/2.5-v gnd all modes 1.8-v/1.5-v 3.3-v/2.5-v v ccpd (1) all modes 1.8-v/1.5-v 1.8-v/1.5-v v ccpd ? 3.3-v/2.5-v 1.8-v/1.5-v not supported note to table 13?6 : (1) the vccsel pin can also be connected to gnd for ps ( msel[3..0]=0010 ) and fpp ( msel[3..0]=0000 ) modes.
altera corporation 13?13 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices table 13?7 shows the configuration mode support for banks 4, 7, and 8. output configuration pins you must verify that the configurat ion output pins for your chosen configuration modes meet the v ih of the configuration device. refer to table 13?22 on page 13?94 for a consolidated list of configuration output pins. the v ih of 3.3 v or 2.5 v configuration devices will not be met when the v ccio of the output configuration pins are 1.8 v or 1.5 v. level shifters will be required to meet the input high level voltage threshold v ih . note that as mode is only applicable for 3.3-v configurations. if i/o bank 3 is less than 3.3 v, level shifte rs are required on the output pins ( dclk , ncso , asdo ) from the stratix ii or stratix ii gx device back to the epcs device. table 13?7. stratix ii conf iguration mode support for banks 4, 7 and 8 configuration mode configuration voltage/v ccio support for banks 4, 7, and 8 3.3/3.3 1.8/1.8 3.3/1.8 vccsel = gnd vccsel = vccpd vccsel = gnd fast passive parallel y y y passive parallel asynchronous y y y passive serial y y y remote system upgrade fpp y y y remote system upgrade ppa y y y remote system upgrade ps y y y fast as (40 mhz) y y y remote system upgrade fast as (40 mhz) y y y fpp with decompression and/or design security yyy remote system upgrade fpp with decompression and/or design security feature enabled yyy as (20 mhz) y y y remote system upgrade as (20 mhz) y y y
13?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration the key is to ensure the vccio voltage of bank 3 is high enough to trip the vccio3 por trip point on power-up. also, to make sure the configuration device meets the v ih for the configuration input pins based on the selected input buffer. fast passive parallel configuration fast passive parallel (fpp) configuration in stratix ii and stratix ii gx devices is designed to meet the co ntinuously increasing demand for faster configuration times. stratix ii and stratix ii gx devices are designed with the capability of rece iving byte-wide configuration data per clock cycle. table 13?8 shows the msel pin settings when using the ffp configuration scheme. fpp configuration of stratix ii and st ratix ii gx devices can be performed using an intelligent host, such as a max ii device, a microprocessor, or an altera enhanced co nfiguration device. table 13?8. stratix ii and stratix ii gx msel pin settings for fpp c onfiguration schemes notes (1) , (2) , and (3) configuration scheme m sel3 msel2 msel1 msel0 fpp when not using remote system upgrade or decompression and/or design security feature 0000 fpp when using remote system upgrade (4) 0100 fpp with decompression and/or design security feature enabled (5) 1011 fpp when using remote system upgrade and decompression and/or design security feature (4) , (5) 1100 notes to table 13?8 : (1) you must verify the configuration output pins for your chosen configura iton modes meet the v ih of the configuration device. refer to table 13?22 for a consolidated list of configuration output pins. (2) the v ih of 3.3-v or 2.5-v configuration devices will not be met when the vccio of the output configuration pins is 1.8-v or 1.5-v. level shifters will be required to meet the input high level voltage threshold v ih . (3) the vccsel signal does not control tdo or nceo . during configuration, these pins drive out voltage levels corresponding to the vccio supply voltage that powers the i/o bank containing the pin. for more information about multi-volt support, incl uding information about using tdo and nceo in multi-volt systems, refer to the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . (4) these schemes require that you drive the runlu pin to specify either remote update or local update. for more information about remote system upgrad e in stratix ii devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . (5) these modes are only supported when using a max ii device or a microprocessor with flash memory for configuration. in these modes, the host system must output a dclk that is 4 the data rate.
altera corporation 13?15 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices fpp configuration using a max ii device as an external host fpp configuration using compression and an external host provides the fastest method to configure stratix ii and stratix ii gx devices. in the fpp configuration scheme, a max ii device can be used as an intelligent host that controls the transfer of configur ation data from a storage device, such as flash memory, to the target st ratix ii or stratix ii gx device. configuration data can be stored in rbf, hex, or ttf format. when using the max ii devices as an intellig ent host, a design that controls the configuration process, such as fetchi ng the data from flash memory and sending it to the device, must be stored in the max ii device. 1 if you are using the stratix ii or stratix ii gx decompression and/or design security feature, th e external host must be able to send a dclk frequency that is 4 the data rate. the 4 dclk signal does not require an addi tional pin and is sent on the dclk pin. the maximum dclk frequency is 100 mhz, which results in a maximum data rate of 200 mbps. if you are not using the stratix ii or stratix ii gx decompression or design se curity features, the data rate is 8 the dclk frequency. figure 13?3 shows the configuration inte rface connections between the stratix ii or stratix ii gx device and a max ii device for single device configuration. figure 13?3. single device fpp confi guration using an external host note to figure 13?3 : (1) the pull-up resistor sho uld be connected to a supply that provides an acceptable input signal for the device. v cc should be high enough to meet the v ih specification of the i/o on the device and the external host. external host (max ii device or microprocessor) conf_done nstatus nce data[7..0] nconfig stratix ii device memory addr data[7..0] gnd msel[3..0] v cc (1) v cc (1) gnd dclk nceo n.c. 10 k 10 k
13?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration upon power-up, the stratix ii and stratix ii gx devices go through a power-on reset (por). the por delay is dependent on the porsel pin setting; when porsel is driven low, the por time is approximately 100 ms, if porsel is driven high, the por ti me is approximately 12 ms. during por, the device resets, holds nstatus low, and tri-states all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins have weak pull-up resistors, which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. 1 you can hold nconfig low in order to stop device configuration. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in the reset stage. to initiate configuration, the max ii device must drive the nconfig pin from low-to-high. 1 v ccint , v ccio , and v ccpd of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k pull-up resistor. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins. when nstatus is pulled high, the max ii device places the configuration data one byte at a time on the data[7..0] pins. 1 stratix ii and stratix ii gx devices receive configuration data on the data[7..0] pins and the clock is received on the dclk pin. data is latched into the device on the rising edge of dclk . if you are using the stratix ii or stra tix ii gx decompression and/or design security feature, configuration data is latched on the rising edge of every fourth dclk cycle. after the configuration data is latched in, it is processed during the following three dclk cycles.
altera corporation 13?17 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices data is continuously clocked into the target device until conf_done goes high. the conf_done pin goes high one byte early in parallel configuration (fpp and ppa) modes. the last byte is required for serial configuration (as and ps) modes. after the device has received the next to last byte of the configuration data successfully, it releases the open-drain conf_done pin, which is pulled hi gh by an external 10-k pull-up resistor. a low- to-high transition on conf_done indicates configuration is complete and initialization of the device can begin. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used, the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initialization. therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. driving dclk to the device after configuration is complete does not affect device operation. you can also synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr does not affect the configuration process. the conf_done pin goes high one byte early in parallel configuration (fpp and ppa) modes. the last byte is required for serial configuration (as and ps) modes. after the conf_done pin transitions high, clkusr is enabled after the time specified as t cd2cu . after this time peri od elapses, stratix ii and stratix ii gx devices require 299 cl ock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. this enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used, it is high because of an external 10-k pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled high. the max ii device must be able to detect this low-to-high tran sition, which signals the device has
13?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration entered user mode. when initialization is complete, the device enters user mode. in user-mode, the user i/o pi ns no longer have weak pull-up resistors and function as assigned in your design. to ensure dclk and data[7..0] are not left floating at the end of configuration, the max ii device must drive them either high or low, whichever is convenient on your board. the data[7..0] pins are available as user i/o pins after conf iguration. when you select the fpp scheme in the quartus ii software, as a default, these i/o pins are tri-stated in user mode. to change this default option in the quartus ii software, select the pins tab of the device & pin options dialog box. the configuration clock ( dclk ) speed must be below the specified frequency to ensure correct configuration. no maximum dclk period exists, which means you can pause configuration by halting dclk for an indefinite amount of time. 1 if you are using the stratix ii or stratix ii gx decompression and/or design security feature and need to stop dclk , it can only be stopped three clock cycles after the last data byte was latched into the stratix ii or stratix ii gx device. by stopping dclk , the configuration circuit allows enough clock cycles to process the last byte of latched configuration data. when the clock restarts, the max ii device must provide data on the data[7..0] pins prior to sending the first dclk rising edge. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device & pin options (dialog box) is turned on, the device releases nstatus after a reset time-out period (maximum of 100 s). after nstatus is released and pull ed high by a pull-up resistor, the max ii device can try to reconfigure the target device without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to- high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the conf_done pin must be monitored by the max ii device to detect errors and determine when programming completes. if all configuration data is sent, but the conf_done or init_done signals have not gone high, the max ii device will reconfigure the target device.
altera corporation 13?19 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices 1 if the optional clkusr pin is used and nconfig is pulled low to restart configuration during device initialization, you need to ensure clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, initiating a reconfiguration is done by transitioning the nconfig pin low-to-high. the nconfig pin should be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 13?4 shows how to configure multiple devices using a max ii device. this circuit is similar to the fpp configuration circuit for a single device, except the stratix ii or st ratix ii gx devices are cascaded for multi-device configuration. figure 13?4. multi-device fpp confi guration using an external host note to figure 13?4 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o standard on the device and the external host. in multi-device fpp configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins co nfiguration within one clock cycle; therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in conf_done nstatus nce data[7..0] nconfig stratix ii or stratix ii gx device 1 stratix ii or stratix ii gx device 2 memory addr data[7..0] gnd v cc (1) v cc (1) dclk nceo conf_done nstatus nce data[7..0] nconfig dclk nceo n.c. 10 k 10 k external host (max ii device or microprocessor) msel[3..0] gnd msel[3..0] gnd
13?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration the chain. the configuration signal s may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. all nstatus and conf_done pins are tied together and if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart config uration after error option is turned on, the devices release their nstatus pins after a reset time-out period (maximum of 100 s). after all nstatus pins are released and pulled high, the max ii device can try to reconfigure the chain without pulsing nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (wit h a low pulse of at least 2 s) on nconfig to restart the configuration process. in a multi-device fpp configuration chain, all stratix ii or stratix ii gx devices in the chain must either enable or disable the decompression and/or design security feature. you can not selectively enable the decompression and/or design security feature for each device in the chain because of the data and dclk relationship. if the chain contains devices that do not support design security, you should use a serial configuration scheme. if a system has multiple devices that contain the same configuration data, tie all device nce inputs to gnd, and leave nceo pins floating. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in the chain. configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices start and complete conf iguration at the same time. figure 13?5 shows multi-device fpp configuration when both stratix ii or stratix ii gx devices are receiving the same configuration data.
altera corporation 13?21 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices figure 13?5. multiple-device fpp con figuration using an external host when both devices receive the same data notes to figure 13?5 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. (2) the nceo pins of both stratix ii or stratix ii gx devices are left unconnected when configuring the same configuration data into multiple devices. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices that support fpp configuration, such as stratix devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, tie all of the device conf_done and nstatus pins together. f for more information on configuring multiple altera devices in the same configuration chain, refer to configuring mixed altera fpga chains in volume 2 of the configuration handbook. fpp configuration timing figure 13?6 shows the timing waveform for fpp configuration when using a max ii device as an extern al host. this waveform shows the timing when the decompression and th e design security feature are not enabled. conf_done nstatus nce data[7..0] nconfig stratix ii device memory addr data[7..0] gnd v cc (1) v cc (1) dclk nceo n.c. (2) conf_done nstatus nce data[7..0] nconfig stratix ii device gnd dclk nceo n.c. (2 ) 10 k 10 k external host (max ii device or microprocessor) msel[3..0] gnd msel[3..0] gnd
13?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration figure 13?6. fpp configuration timing waveform notes (1) , (2) notes to figure 13?6 : (1) this timing waveform should be used when the de compression and design security feature are not used. (2) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (3) upon power-up, the stratix ii or stratix ii gx device holds nstatus low for the time of the por delay. (4) upon power-up, before and during configuration, conf_done is low. (5) dclk should not be left floating after co nfiguration. it should be driven high or low, whichever is more convenient. (6) d ata[7..0] are available as user i/o pins after configuration and the state of these pins depends on the dual-purpose pin settings. table 13?9 defines the timing parameters for stratix ii and stratix ii gx devices for fpp configuration when the decompression and the design security features are not enabled. nconfig nstatus (3) conf_done (4) dclk data[7..0] user i/o init_done byte 0 byte 1 byte 2 byte 3 byte n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck hi g h-z user mode (5) (5) user mode table 13?9. fpp timing parameters for stratix ii and stratix ii gx devices (part 1 of 2) notes (1) , (2) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (3) s t cf2st1 nconfig high to nstatus high 100 (3) s t cf2ck nconfig high to first rising edge on dclk 100 s t st2ck nstatus high to first rising edge of dclk 2 s
altera corporation 13?23 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices t dsu data setup time before rising edge on dclk 5 ns t dh data hold time after rising edge on dclk 0 ns t ch dclk high time 4 ns t cl dclk low time 4 ns t clk dclk period 10 ns f max dclk frequency 100 mhz t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (4) 20 100 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 clkusr period) notes to table 13?9 : (1) this information is preliminary. (2) these timing parameters should be used when the decompression and de sign security feature are not used. (3) this value is obtainable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (4) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device. table 13?9. fpp timing parameters for stratix ii and stratix ii gx devices (part 2 of 2) notes (1) , (2) symbol parameter min max units
13?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration figure 13?7 shows the timing waveform for fpp configuration when using a max ii device as an extern al host. this waveform shows the timing when the decompression and/or the design security feature are enabled. figure 13?7. fpp configuration timing waveform wi th decompression or design security feature enabled notes (1) , (2) notes to figure 13?7 : (1) this timing waveform should be used when the deco mpression and/or design security feature are used. (2) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (3) upon power-up, the stratix ii or stratix ii gx device holds nstatus low for the time of the por delay. (4) upon power-up, before and during configuration, conf_done is low. (5) dclk should not be left floating after co nfiguration. it should be driven high or low, whichever is more convenient. (6) data[7..0] are available as user i/o pins after configuration and the state of these pins depends on the dual-purpose pin settings. (7) if needed, dclk can be paused by holding it low. when dclk restarts, the external host must provide data on the data[7..0] pins prior to sending the first dclk rising edge. nconfig nstatus conf_done dclk data[7..0] user i/o init_done t cd2um t cf2st1 t cf2cd t cfg t cf2ck t t cf2st0 t st2ck hi g h-z user mode (3) (4) 12341234 1 byte 0 byte 1 byte 2 4 t dsu t dh status t dh t c h t c l t c lk byte n (6) (6) (5) (5) user mode
altera corporation 13?25 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices table 13?10 defines the timing parameters for stratix ii and stratix ii gx devices for fpp configuration when the decompression and/or the design security feature are enabled. f device configuration options and how to create configuration files are discussed further in the software settings chapter in the configuration handbook. table 13?10. fpp timing parameters for stratix ii and stratix ii gx devices with decompression or design security feature enabled note (1) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (2) s t cf2st1 nconfig high to nstatus high 100 (2) s t cf2ck nconfig high to first rising edge on dclk 100 s t st2ck nstatus high to first rising edge of dclk 2 s t dsu data setup time before rising edge on dclk 5 ns t dh data hold time after rising edge on dclk 30 ns t ch dclk high time 4 ns t cl dclk low time 4 ns t clk dclk period 10 ns f max dclk frequency 100 mhz t data data rate 200 mbps t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (3) 20 100 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 clkusr period) notes to table 13?10 : (1) these timing parameters should be used when the decompression and design security feature are used. (2) this value is obtainable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (3) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device.
13?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration fpp configuration using a microprocessor in the fpp configuration scheme, a microprocessor can control the transfer of configuration data from a storage device, such as flash memory, to the target stratix ii or stratix ii gx device. 1 all information in ?fpp configuration using a max ii device as an external host? on page 13?15 is also applicable when using a microprocessor as an external host. refer to that section for all configuration and timing information. fpp configuration using an enhanced configuration device in the fpp configuration scheme, an enhanced configurat ion device sends a byte of configuration data every dclk cycle to the stratix ii or stratix ii gx device. configuration data is stored in the configuration device. 1 when configuring your stratix ii or stratix ii gx device using fpp mode and an enhanced conf iguration device, the enhanced configuration device decompress ion feature is available while the stratix ii and stratix ii gx decompression and design security features are not. figure 13?8 shows the configuration interface connections between a stratix ii or stratix ii gx device and the enhanced configuration device for single device configuration. 1 the figures in this chapter only show the configuration-related pins and the configuration pin connections between the configuration device and the device. f for more information on the enhanc ed configuration device and flash interface pins, such as pgm[2..0] , exclk , porsel , a[20..0] , and dq[15..0] , refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook.
altera corporation 13?27 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices figure 13?8. single device fpp configuration using an enhanced configuration device notes to figure 13?8 : (1) the pull-up resistor sh ould be connected to the same supply voltage as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. this means an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if intern al pull-up resistors are used, external pull-up resistors should not be used on th ese pins. the internal pull-up resistors are used by default in the quartus ii soft ware. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. f the value of the internal pull-up resi stors on the enhanced configuration devices can be found in the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook. when using enhanced configuratio n devices, you can connect the device?s nconfig pin to ninit_conf pin of the enhanced configuration device, which allows the init_conf jtag instruction to initiate device configuration. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. an internal pull-up resistor on the ninit_conf pin is always active in the enhanced configuration devices, which means an external pull-up resistor should not be used if nconfig is tied to ninit_conf . upon power-up, the stratix ii or stratix ii gx device goes through a por. the por delay is dependent on the porsel pin setting; when porsel is driven low, the por time is approximately 100 ms, if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state all user i/o pins. the stratix ii device enhanced confi g uration device dclk data[7..0] oe ncs ninit_conf (2) dclk data[7..0] nstatus conf_done nconfig v cc v cc gnd gnd (1) (1) nce (3) (3) nceo n.c. msel[3..0] 10 k 10 k (3) (3)
13?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration configuration device also goes through a por delay to allow the power supply to stabilize. the por time for enhanced configuration devices can be set to either 100 ms or 2 ms, depending on its porsel pin setting. if the porsel pin is connected to gnd, the por delay is 100 ms. if the porsel pin is connected to v cc , the por delay is 2 ms. during this time, the configuration device drives its oe pin low. this low signal delays configuration because the oe pin is connected to the target device?s nstatus pin. 1 when selecting a por time, you need to ensure that the device completes power-up before the enhanced configuration device exits por. altera recommends that you use a 12-ms por time for the stratix ii or stratix ii g x device, and use a 100-ms por time for the enhanced configuration device. when both devices complete por, they release their open-drain oe or nstatus pin, which is then pulled high by a pull-up resistor. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors, which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the stratix ii device handbook or the stratix ii gx device handbook . when the power supplies have reached the appropriate operating voltages, the target device senses the low-to-high transition on nconfig and initiates the configuration cycle. the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. the beginning of configuration can be delayed by holding the nconfig or nstatus pin low. 1 v ccint , v ccio and v ccpd of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when nconfig goes high, the device comes out of reset and releases the nstatus pin, which is pulled high by a pull-up resistor. enhanced configuration devices have an optional internal pull-up resistor on the oe pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used, an external 10-k pull-up resistor on the oe-nstatus line is required. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins.
altera corporation 13?29 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices when nstatus is pulled high, the configuration device?s oe pin also goes high and the configuration device clocks data out to the device using the stratix ii or stratix ii gx device?s internal oscillator. the stratix ii and stratix ii gx devices receive configuration data on the data[7..0] pins and the clock is received on the dclk pin. a byte of data is latched into the device on each rising edge of dclk . after the device has received all configuration data successfully, it releases the open-drain conf_done pin which is pulled high by a pull-up resistor. because conf_done is tied to the configuration device?s ncs pin, the configuration device is disabled when conf_done goes high. enhanced configuration devices have an optional internal pull-up resistor on the ncs pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used, an external 10-k pull-up resistor on the ncs - conf_done line is required. a low to high transition on conf_done indicates configuration is comp lete and initialization of the device can begin. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used, the stratix ii or stratix ii gx device provides itself with enough clock cycl es for proper initialization. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr will not affect the configuration process. after all configuration data has been accepted and conf_done goes high, clkusr will be enabled after the time specified as t cd2cu . after this time period elapses, stratix ii and strati x ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used, it will be hi gh due to an external 10-k pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin will go low. when initialization is complete, the init_done pin will be released and pulled high. in user-mode, the user
13?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration i/o pins will no longer have weak pu ll-up resistors and will function as assigned in your design. the enhanced configuration device will drive dclk low and data[7..0] high at the end of configuration. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. since the nstatus pin is tied to oe , the configuration device will also be reset. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device & pin options dialog box) is turned on, the device will automatically initiate reconfiguration if an error occurs. the stratix ii or stratix ii gx device releases its nstatus pin after a reset time-out period (maximum of 100 s). when the nstatus pin is released and pulled high by a pull-up resistor, the configuration device reconfigures the chain. if this option is turned off, th e external system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configuration. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . in addition, if the configuration device sends all of its data and then detects that conf_done has not gone high, it re cognizes that the device has not configured successfully. enha nced configuration devices wait for 64 dclk cycles after the last configuration bit was sent for conf_done to reach a high state. in this case, the configuration device pulls its oe pin low, which in turn drives the target device?s nstatus pin low. if the auto-restart configuration after error option is set in the software, the target device resets and then releases its nstatus pin after a reset time-out period (maximum of 100 s). when nstatus returns to a logic high level, the configuration device will try to reconfigure the device. when conf_done is sensed low after configuration, the configuration device recognizes that the target device has not configured successfully. therefore, your system should not pull conf_done low to delay initialization. instead, you should use the clkusr option to synchronize the initialization of multiple devices that are not in the same configuration chain. devices in th e same configuration chain will initialize together if their conf_done pins are tied together. 1 if the optional clkusr pin is used and nconfig is pulled low to restart configuration during device initialization, ensure clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, a reconfiguration can be initiated by pulling the nconfig pin low. the nconfig pin should be low for at least 2s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. because conf_done is
altera corporation 13?31 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices pulled low, this activates the configuration device because it sees its ncs pin drive low. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 13?9 shows how to configure multiple stratix ii or stratix ii gx devices with an enhanced configuration device. this circuit is similar to the configuration device circuit for a single device, except the stratix ii or stratix ii gx devices are cascaded for multi-device configuration. figure 13?9. multi-device fpp configurati on using an enhanced configuration device notes to figure 13?9 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active. this means an external p ull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-up resistors on configuration device option when generating programming files. 1 enhanced configuration devices cannot be cascaded. when performing multi-device configuration, you must generate the configuration device?s pof from ea ch project?s sof. you can combine multiple sofs using the convert programming files window in the quartus ii software. f for more information on how to create configuration files for multi-device configuration chains, refer to software settings in volume 2 of the configuration handbook . ncs data[7..0] oe ninit_conf (2) gnd gnd gnd 10 k dclk v cc (1) (3) 10 k v cc (1) (3) enhanced confi g uration device conf_done data[7..0] nstatus nconfig dclk msel[3..0] nce nceo stratix ii device 1 conf_done data[7..0] nstatus nconfig dclk msel[3..0] nce n.c. nceo stratix ii device 2 (3) (3)
13?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 fast passive parallel configuration in multi-device fpp configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in the chain. pay special attention to the co nfiguration signals because they may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. when configuring multiple devices, co nfiguration does not begin until all devices release their oe or nstatus pins. similarly, since all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this low signal drives the oe pin low on the enhanced configuration device and drives nstatus low on all devices, which causes them to enter a reset state. this behavior is similar to a single device detecting an error. if the auto-restart config uration after error option is turned on, the devices will automatically initiate reconfiguration if an error occurs. the devices will release their nstatus pins after a reset time-out period (maximum of 100 s). when all the nstatus pins are released and pulled high, the configuration device trie s to reconfigure the chain. if the auto-restart configuration after error option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configurat ion. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . your system may have multiple devices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left fl oating. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in the chain. configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices will start and complete configuration at the same time. figure 13?10 shows multi-device fpp config uration when both stratix ii or stratix ii gx devices are receiv ing the same configuration data.
altera corporation 13?33 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices figure 13?10. multiple-device fpp co nfiguration using an enhanced c onfiguration device when both devices receive the same data notes to figure 13?10 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active. this means an external p ull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) the nceo pins of both devices are left unconnected when conf iguring the same configuration data into multiple devices. you can use a single enhanced config uration chain to configure multiple stratix ii or stratix ii gx devices with other altera devices that support fpp configuration, such as stratix and stratix gx devices. to ensure that all devices in the chain complete config uration at the same time or that an error flagged by one device initiates re configuration in all devices, all of the device conf_done and nstatus pins must be tied together. f for more information on configuring multiple altera devices in the same configuration chain, refer to configuring mixed al tera fpga chains in the configuration handbook . ncs data[7..0] oe ninit_conf (2) gnd gnd gnd 10 k dclk v cc (1) (3) 10 k v cc (1) (3) enhanced confi g uration device conf_done data[7..0] nstatus nconfig dclk nce nceo stratix ii device conf_done data[7..0] nstatus nconfig dclk msel[3..0] nce n.c. nceo stratix ii device (4) gnd n.c. (4) (3) (3) msel[3..0]
13?34 altera corporation stratix ii gx device handbook, volume 2 october 2007 active serial configuration (serial configuration devices) figure 13?11 shows the timing waveform for the fpp configuration scheme using an enhanced configuration device. figure 13?11. stratix ii and stratix ii g x fpp configuration using an enhanc ed configuration device timing waveform note to figure 13?11 : (1) the initialization clock can come from the stratix ii or stratix ii g x device?s internal oscillator or the clkusr pin. f for timing information, refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook . f device configuration options and how to create configuration files are discussed further in the software settings section in volume 2 of the configuration handbook . active serial configuration (serial configuration devices) in the as configuration scheme, stratix ii and stratix ii gx devices are configured using a serial configur ation device. these configuration devices are low-cost devices with no n-volatile memory that feature a simple four-pin interface and a smal l form factor. these features make serial configuration devices an ideal low-cost configuration solution. note that as mode is only applicable for 3.3-v configurations. if i/o bank 3 is less than 3.3 v, level shifte rs are required on the output pins ( dclk , ncso , asdo ) from the stratix ii or stratix ii gx device back to the epcs device. 1 if vccio in bank 3 is set to 1.8 v , an external voltage level translator is needed to meet the v ih of the epcs device (3.3 v). tri-state user mode t loe t lc t hc t ce t oe byte byte 2 n byte 1 driven hi g h tri-state oe/nstatus ncs/conf_done dclk data[7..0] user i/o init_done ninit_conf or vcc/nconfig t cd2um (1)
altera corporation 13?35 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices f for more information on serial configuration devices, refer to the serial configuration devices (epcs1, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook . serial configuration devices provide a serial interface to access configuration data. during device configuration, stratix ii and stratix ii gx devices read configuratio n data via the serial interface, decompress data if necessary, and configure their sram cells. this scheme is referred to as the as conf iguration scheme because the device controls the configuratio n interface. this scheme contrasts with the ps configuration scheme, where the configuration device controls the interface. 1 the stratix ii and stratix ii gx decompression and design security features are fully av ailable when configuring your stratix ii or stratix ii gx device using as mode. table 13?11 shows the msel pin settings when using the as configuration scheme. serial configuration devices have a four-pin interface: serial clock input ( dclk ), serial data output ( data ), as data input ( asdi ), and an active-low chip select ( ncs ). this four-pin interface connects to stratix ii and stratix ii gx device pins, as shown in figure 13?12 . table 13?11. stratix ii and stratix ii gx msel pin settings for as configuration schemes note (2) configuration scheme m sel3 msel2 msel1 msel0 fast as (40 mhz) (1) 1000 remote system upgrade fast as (40 mhz) (1) 1001 as (20 mhz) (1) 1101 remote system upgrade as (20 mhz) (1) 1110 notes to ta b l e 1 3 ? 11 : (1) only the epcs16 and epcs64 devices support a dclk up to 40 mhz clock; other epcs devices support a dclk up to 20 mhz. refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook for more information. (2) note that as mode is only applicable fo r 3.3-v configuration. if i/o bank 3 is less than 3.3-v, level shifters are required on the output pins (dclk,ncso, and asdo) from the stratix ii or stratix ii gx device back to the epcs device.
13?36 altera corporation stratix ii gx device handbook, volume 2 october 2007 active serial configuration (serial configuration devices) figure 13?12. single device as configuration notes to figure 13?12 : (1) connect the pull-up re sistors to a 3.3-v supply. (2) stratix ii and stratix ii gx devices use the asdo to asdi path to control the configuration device. (3) if using an epcs4 device, msel[3..0] should be set to 1101. refer to table 13?11 for more details. upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus and conf_done low, and tri-state all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook and the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. after por, the stratix ii and stratix ii gx devices release nstatus , which is pulled high by an external 10-k pull-up resistor, and enters configuration mode. data dclk ncs asdi data0 dclk ncso asdo serial confi g uration device stratix ii or stratix ii gx fpga 10 k 10 k v cc 10 k v cc v cc gnd nceo nce nstatus nconfig conf_done (2) msel1 msel0 gnd n.c. (1) (1) (1) msel3 msel2 v cc (3) (3) (3) (3)
altera corporation 13?37 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. the serial clock ( dclk ) generated by the stratix ii and stratix ii gx devices controls the entire configuration cycle and provides the timing for the serial interface. stratix ii and stratix ii gx devices use an internal oscillator to generate dclk . using the msel[] pins, you can select to use either a 40- or 20-mhz oscillator. 1 only the epcs16 and ep cs64 devices support a dclk up to 40-mhz clock; other epcs devices support a dclk up to 20-mhz. refer to the serial configuration devices data sheet for more information. the epcs4 device only supports the smallest stratix ii (ep2s15) device, which is when the sof compression is enabled. because of its insu fficient memory capacity, the epcs1 device does not support any stratix ii devices. table 13?12 shows the active serial dclk output frequencies. in both as and fast as configuration schemes, the serial configuration device latches input and control signals on the rising edge of dclk and drives out configuration data on the falling edge. stratix ii and stratix ii gx devices drive out control signals on the falling edge of dclk and latch configuration data on the falling edge of dclk . in configuration mode, stratix ii and stratix ii gx devices enable the serial configuration device by driving the ncso output pin low, which connects to the chip select ( ncs ) pin of the configuration device. the stratix ii and stratix ii gx devices use the serial clock ( dclk ) and serial data output ( asdo ) pins to send operation commands and/or read address signals to the serial conf iguration device. the configuration device provides data on its serial data output ( data ) pin, which connects to the data0 input of the stratix ii and stratix ii gx devices. table 13?12. active serial dclk output frequency oscillator minimum typical maximum units 40 mhz (1) 20 26 40 mhz 20 mhz 10 13 20 mhz note to table 13?12 : (1) only the epcs16 and epcs64 devices support a dclk up to 40-mhz clock; other epcs devices support a dclk up to 20-mhz. refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs16, and epcs128) data sheet chapter in volume 2 of the configuration handbook for more information.
13?38 altera corporation stratix ii gx device handbook, volume 2 october 2007 active serial configuration (serial configuration devices) after all configuration bits are receiv ed by the stratix ii or stratix ii gx device, it releases the open-drain conf_done pin, which is pulled high by an external 10-k resistor. initialization begins only after the conf_done signal reaches a logic high level. all as configuration pins, data0 , dclk , ncso , and asdo , have weak internal pull-up resistors that are always active. after configurat ion, these pins are set as input tri-stated and are driven high by the weak internal pull-up resistors. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the 10-mhz (typical ) internal oscill ator (separate from the active serial internal oscillator) or the optional clkusr pin. by default, the internal oscillator is th e clock source for initialization. if the internal oscillator is us ed, the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initiali zation. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. when you enable the user supplied start-up clock option, the clkusr pin is the initialization clock source. supplying a clock on clkusr will not affect the configuration process. after all co nfiguration data has been accepted and conf_done goes high, clkusr is enabled after 600 ns. after this time period elapses, stratix ii and stratix ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used, it will be hi gh due to an external 10-k pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled hi gh. this low-to-hi gh transition signals that the device has entered user mode. when initialization is complete, the device enters user mode. in user mode, the user i/o pins no longer have weak pull-up resistor s and function as assigned in your design. if an error occurs during configurat ion, stratix ii and stratix ii gx devices assert the nstatus signal low, indicating a data frame error, and the conf_done signal stays low. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the
altera corporation 13?39 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices device & pin options dialog box) is turned on, the stratix ii or stratix ii gx device resets the configuration device by pulsing ncso , releases nstatus after a reset time-out period (maximum of 100 s), and retries configuration. if this option is turned off, the sy stem must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configuration. when the stratix ii or stratix ii gx device is in user mode, you can initiate reconfiguration by pulling the nconfig pin low. the nconfig pin should be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the stratix ii or stratix ii gx device, reconfiguration begins. you can configure multiple stratix i i or stratix ii gx devices using a single serial configuration device. you can cascade multiple stratix ii or stratix ii gx devices using the chip-enable ( nce ) and chip-enable-out ( nceo ) pins. the first device in the chain must have its nce pin connected to ground. you must connect its nceo pin to the nce pin of the next device in the chain. when the first de vice captures all of its configuration data from the bit stream, it drives the nceo pin low, enabling the next device in the chain. you must leave the nceo pin of the last device unconnected. the nconfig , nstatus , conf_done , dclk , and data0 pins of each device in the chain are connected (refer to figure 13?13 ). this first stratix ii or st ratix ii gx device in the chain is the configuration master and controls configuration of the entire chain. you must connect its msel pins to select the as config uration scheme. the remaining stratix ii or stratix ii gx devices are configuration slaves and you must connect their msel pins to select the ps configuration scheme. any other altera device that supports ps configuration can also be part of the chain as a configuration slave. figure 13?13 shows the pin connections for this setup.
13?40 altera corporation stratix ii gx device handbook, volume 2 october 2007 active serial configuration (serial configuration devices) figure 13?13. multi-device as configuration notes to figure 13?13 : (1) connect the pull-up resistors to a 3.3-v supply. (2) if using an epcs4 device, msel[3..0] should be set to 1101. refer to tab le 13?11 for more details. as shown in figure 13?13 , the nstatus and conf_done pins on all target devices are connected together with external pull-up resistors. these pins are open-drain bidirectio nal pins on the devices. when the first device asserts nceo (after receiving all of it s configuration data), it releases its conf_done pin. but the subsequent devices in the chain keep this shared conf_done line low until they have received their configuration data. when all target devices in the chain have received their configuration data and have released conf_done , the pull-up resistor drives a high level on this line and all devices simultaneously enter initialization mode. if an error occurs at any po int during configuration, the nstatus line is driven low by the failing device. if you enable the auto-restart configuration after error option, reconf iguration of the entire chain begins after a reset time-out period (a maximum of 100 s). if the auto-restart configuration after error option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low to restart configuration. the external system can pulse nconfig if it is under system control rather than tied to v cc . 1 while you can cascade stratix ii or stratix ii gx devices, serial configuration devices cannot be cascaded or chained together. data dclk ncs asdi data0 dclk ncso asdo serial confi g uration device stratix ii or stratix ii gx fpga master stratix ii or stratix ii gx fpga slave 10 k 10 k v cc v cc gnd nceo nce nstatus conf_done data0 dclk nceo nce nstatus conf_done 10 k v cc nconfig nconfig n.c. (1) (1) (1) msel1 msel0 gnd msel3 msel2 v cc (2) (2) (2) (2) msel1 msel0 gnd msel3 msel2 v c c
altera corporation 13?41 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices if the configuration bit stream size exceeds the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. when configuring multiple devices, the size of the bitstream is the sum of the individual devices? configuration bitstreams. a system may have multiple devices that contain the sa me configuration data. in active serial chains, this can be implemented by storing two copies of the sof in the serial conf iguration device. the first copy would configure the master stratix ii or stratix ii gx device, and the second copy would configure all remaining sl ave devices concurrently. all slave devices must be the same density and package. the setup is similar to figure 13?13 , where the master is set up in active serial mode and the slave devices are set up in passive serial mode. to configure four identical stratix i i or stratix ii gx devices with the same sof, you could set up the ch ain similar to the example shown in figure 13?14 . the first device is the master device and its msel pins should be set to select as configuration. the other three slave devices are set up for concurrent configuration and its msel pins should be set to select ps configuration. the nceo pin from the master device drives the nce input pins on all three slave devices, and the data and dclk pins connect in parallel to all four devices. during the first configuration cycle, the master device reads its configuration data from the serial configuration device while holding nceo high. after completing its configuration cycle, the master drives nce low and transmits the second copy of the configuration data to all three slave devices, configuring them simultaneously.
13?42 altera corporation stratix ii gx device handbook, volume 2 october 2007 active serial configuration (serial configuration devices) figure 13?14. multi-device as configuration when devices receive the same data notes to figure 13?14 : (1) connect the pull-up resistors to a 3.3-v supply. (2) if using an epcs4 device, msel[3..0] should be set to 1101. refer to table 13?11 for more details. data dclk ncs asdi data0 dclk ncso asdo serial confi g uration device stratix ii fpga master 10 k 10 k v cc v cc gnd nceo nce nstatus conf_done data0 dclk stratix ii fpga slave nceo nce nstatus conf_done 10 k v cc nconfig nconfig n.c. (1) (1) (1) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v c c data0 dclk stratix ii fpga slave nceo nce nstatus conf_done nconfig n.c. msel1 msel0 gnd msel3 msel2 v c c data0 dclk stratix ii fpga slave nceo nce nstatus conf_done nconfig n.c. msel1 msel0 gnd msel3 msel2 v cc (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2)
altera corporation 13?43 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices estimating active serial configuration time active serial configuration time is dominated by the time it takes to transfer data from the serial config uration device to the stratix ii device. this serial interface is clocked by the stratix ii dclk output (generated from an internal osci llator). as listed in table 13?12 on page 13?37 , the dclk minimum frequency when choosing to use the 40-mhz oscillator is 20 mhz (50 ns). therefore, the maxim um configuration time estimate for an ep2s15 device (5 mbits of uncompressed data) is: rbf size (minimum dclk period / 1 bit per dclk cycle) = estimated maximum configuration time 5 mbits (50 ns / 1 bit) = 250 ms to estimate the typical configuration time, use the typical dclk period as listed in table 13?12 . with a typical dclk period of 38.46 ns, the typical configuration time is 192 ms. enabling compression reduces the amount of configuration data that is transm itted to the stratix ii or stratix ii gx device, which also reduces configuration time. on average, compression reduces configuration time by 50 % . programming serial configuration devices serial configuration devices are non-volatile, flash-memory-based devices. you can program these devices in-system using the usb-blaster ? or byteblaster ? ii download cable. alternatively, you can program them using the altera programming unit (apu), supported third-party programmers, or a micropro cessor with the srunner software driver. you can perform in-system programmin g of serial configuration devices via the as programming interface. during in-system programming, the download cable disables device access to the as interface by driving the nce pin high. stratix ii and stratix ii gx devices are also held in reset by a low level on nconfig . after programming is complete, the download cable releases nce and nconfig , allowing the pull-down and pull-up resistors to drive gnd and v cc , respectively. figure 13?15 shows the download cable connections to the serial configuration device. f for more information on the usb blaster download cable, refer to the usb-blaster download cable user guide . for more information on the byteblaster ii cable, refer to the byteblaster ii downlo ad cable user guide .
13?44 altera corporation stratix ii gx device handbook, volume 2 october 2007 active serial configuration (serial configuration devices) figure 13?15. in-system programming of serial configuration devices notes to figure 13?15 : (1) connect these pull-up resistors to 3.3-v supply. (2) power up the byteblaster ii cable's v cc with a 3.3-v supply. (3) if using an epcs4 device, msel[3..0] should be set to 1101 . refer to table 13?11 for more details. you can program serial configuration devices with the quartus ii software with the altera programming hardware (apu) and the appropriate configuration device pr ogramming adapter. the epcs1 and epcs4 devices are offered in an eight- pin small outline in tegrated circuit (soic) package. in production environments, seri al configuration devices can be programmed using multiple methods. altera programming hardware or other third-party programming hardware can be used to program blank serial configuration devices before th ey are mounted onto printed circuit boards (pcbs). alternatively, you ca n use an on-board microprocessor to program the serial configuration device in-system using c-based software drivers provided by altera. data dclk ncs asdi data0 dclk ncso nce nconfig nstatus nceo conf_done asdo v cc v cc v cc v cc 10 k 10 k 10 k 10 k stratix ii fpga serial confi g uration device pin 1 u sb bl aster o r by te bl aser ii 1 0 -pin m a l e h eader n.c. (1) (1) (1) (2) msel1 msel0 gnd msel3 msel2 v cc (3) (3) (3) (3)
altera corporation 13?45 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices a serial configuration device can be programmed in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming, which can be easily customized to fi t in different embedded systems. srunner is able to read a raw programming data (. rpd ) file and write to the serial configuration devices. the serial configuration device programming time using srunner is comparable to the programming time with the quartus ii software. f for more information about srunner, refer to an 418: srunner: an embedded solution for serial configuration device programming and the source code on the altera web site at www.altera.com . f for more information on programmin g serial configuration devices, refer to the serial configuration devices (e pcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in the configuration handbook . figure 13?16 shows the timing waveform for the as configuration scheme using a serial configuration device. figure 13?16. as configuration timing note to figure 13?16 : (1) the initialization clock can come from the stratix ii or stratix ii g x device?s internal oscillator or the clkusr pin. read address bit n ? 1 bit n bit 1 bit 0 nstatus nconfig conf_done ncso dclk asdo data0 init_done user i/o user mode t c f2st1 t d h t d s u t c h t c l t cd2um (1)
13?46 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration table 13?13 shows the as timing parameters for stratix ii devices. passive serial configuration ps configuration of stratix ii and st ratix ii gx devices can be performed using an intelligent host, such as a max ii device or microprocessor with flash memory, an altera configuration device, or a download cable. in the ps scheme, an external host (max ii device, embedded processor, configuration device, or host pc) co ntrols configuration. configuration data is clocked into the target stra tix ii or stratix ii gx device via the data0 pin at each rising edge of dclk . 1 the stratix ii and stratix ii gx decompression and design security features are fully av ailable when configuring your stratix ii or stratix ii gx device using ps mode. table 13?14 shows the msel pin settings when using the ps configuration scheme. table 13?13. as timing parameters for stratix ii devices symbol parameter condition minimum typical maximum t cf2st1 nconfig high to nstatus high 100 t dsu data setup time before falling edge on dclk 7 t dh data hold time after falling edge on dclk 0 t ch dclk high time 10 t cl dclk low time 10 t cd2um conf_done high to user mode 20 100 table 13?14. stratix ii and stratix ii gx msel pin settings for ps configuration schemes configuration scheme m sel3 msel2 msel1 msel0 ps 0010 ps when using remote system upgrade (1) 0110 note to table 13?14 : (1) this scheme requires that you drive the runlu pin to specify either remote update or local update. for more inform ation about remote system upgrade in stratix ii devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx de vice handbook .
altera corporation 13?47 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices ps configuration using a max ii device as an external host in the ps configuration scheme, a max ii device can be used as an intelligent host that controls the tr ansfer of configuration data from a storage device, such as flash me mory, to the target stratix ii or stratix ii gx device. configuration data can be stored in rbf, hex, or ttf format. figure 13?17 shows the configuration interface connections between a stratix ii or stratix ii gx device and a max ii device for single device configuration. figure 13?17. single device ps confi guration using an external host note to figure 13?17 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for the device. v cc should be high enough to meet the v ih specification of the i/o on the device and the external host. upon power-up, stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting; when porsel is driven low, the por time is approximately 100 ms, if porsel is driven high, the por time is approximately 12 ms. during por, the device resets, holds nstatus low, and tri-states all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. 1 you can hold nconfig low in order to stop device configuration. external host (max ii device or microprocessor) conf_done nstatus nce data0 nconfig stratix ii device memory addr data0 gnd vcc vcc 10 k 10 k dclk nceo n.c. (1) (1) msel1 msel0 gnd msel3 msel2 v cc
13?48 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the stratix ii device handbook or the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration, and initialization. while nconfig or nstatus are low, the device is in reset. to initiate configuration, the max ii device must generate a low-to-high transition on the nconfig pin. 1 v ccint , v ccio , and v ccpd of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k pull-up resistor. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins. when nstatus is pulled high, the max ii device shou ld place the configuration data one bit at a time on the data0 pin. if you are using configuration data in rbf, hex, or ttf format, you must send th e least significant bit (lsb) of each data byte first. for example, if the rbf contains the byte sequence 02 1b ee 01 fa , the serial bitstream you shou ld transmit to the device is 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111 . the stratix ii and stratix ii gx devices receive configuration data on the data0 pin and the clock is received on the dclk pin. data is latched into the device on the rising edge of dclk . data is continuously clocked into the target device until conf_done goes high. after the device has received all configuration data successfully, it releases the open-drain conf_done pin, which is pulled hi gh by an external 10-k pull-up resistor. a low-to-h igh transition on conf_done indicates configuration is complete and initialization of the device can begin. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used, the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initialization. therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. driving dclk to the device after configuration is complete does not affect device operation.
altera corporation 13?49 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr will not affect the configuration process. after all configuration data has been accepted and conf_done goes high, clkusr will be enabled after the time specified as t cd2cu . after this time period elapses, stratix i i and stratix ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used it will be high due to an external 10-k pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin will go low. when initialization is complete, the init_done pin will be released and pulled high. the max ii device must be able to detect this low-to-high transition which signals the device has entered user mode. when initialization is complete, the device enters user mode. in user-mode, the user i/o pins will no longer have weak pull-up resistors and will function as assigned in your design. to ensure dclk and data0 are not left floating at the end of configuration, the max ii device must drive them either high or low, whichever is convenient on your board. the data[0] pin is available as a user i/o pin after configuration. wh en the ps scheme is chosen in the quartus ii software, as a default this i/o pin is tri-stated in user mode and should be driven by the max ii de vice. to change th is default option in the quartus ii software, select the dual-purpose pins tab of the device & pin options dialog box. the configuration clock ( dclk ) speed must be below the specified frequency to ensure correct configuration. no maximum dclk period exists, which means you can pause configuration by halting dclk for an indefinite amount of time. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device & pin options dialog box) is turned on, the stratix ii or stratix ii gx device releases nstatus after a reset time-out period (maxi mum of 100 s). after nstatus is released and
13?50 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration pulled high by a pull-up resistor, th e max ii device can try to reconfigure the target device without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the conf_done pin must be monitored by the max ii device to detect errors and determine when programming completes. if all configuration data is sent, but conf_done or init_done have not gone high, the ma x ii device must reconfigure the target device. 1 if the optional clkusr pin is being used and nconfig is pulled low to restart configuration duri ng device initialization, you need to ensure that clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, you can initiate a reconfiguration by transitioning the nconfig pin low-to-high. the nconfig pin must be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 13?18 shows how to configure multiple devices using a max ii device. this circuit is similar to the ps configuration circuit for a single device, except stratix ii or strati x ii gx devices are cascaded for multi-device configuration.
altera corporation 13?51 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices figure 13?18. multi-device ps confi guration using an external host note to figure 13?18 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. in multi-device ps configuration the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device's nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device's nce pin, which prompts the second device to begin configuration. the second device in the chain begins co nfiguration within one clock cycle. therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. conf_done nstatus nce data 0 nconfig stratix ii or stratix ii gx device 1 stratix ii or stratix ii gx device 2 memory addr data0 gnd v cc (1) v cc (1) 10 k 10 k dclk conf_done nstatus nce data0 nconfig dclk nceo nceo n.c. external host (max ii device or microprocessor) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
13?52 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration if the auto-restart config uration after error option is turned on, the devices release their nstatus pins after a reset time-out period (maximum of 100 s). after all nstatus pins are released and pulled high, the max ii device can try to reconfigure the chain without needing to pulse nconfig low. if this option is turn ed off, the max ii device must generate a low-to-high transition (wit h a low pulse of at least 2 s) on nconfig to restart the configuration process. in your system, you can have multi ple devices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left fl oating. all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices will start and complete configuration at the same time. figure 13?19 shows multi-device ps configuration wh en both stratix ii or stratix ii gx devices are receiving the same configuration data. figure 13?19. multiple-device ps configuration when both devices receive the same data notes to figure 13?19 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. (2) the nceo pins of both devices are left unconnected when conf iguring the same configuration data into multiple devices. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. conf_done nstatus nce data 0 nconfig stratix ii device memory addr data0 gnd vcc (1) vcc (1) 10 k 10 k dclk conf_done nstatus nce data0 nconfig dclk nceo nceo n.c. stratix ii device external host (max ii device or microprocessor) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc n.c. gnd (2) (2)
altera corporation 13?53 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . ps configuration timing figure 13?20 shows the timing waveform for ps configuration when using a max ii device as an external host. figure 13?20. ps configuration timing waveform note (1) notes to figure 13?20 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, the stratix ii or stratix ii gx device holds nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) dclk should not be left floating after configuration. it shou ld be driven high or low, wh ichever is more convenient. data[0] is available as a user i/o pin after configuration an d the state of this pin depends on the dual-purpose pin settings. table 13?15 defines the timing parameters for stratix ii and stratix ii gx devices for ps configuration. nconfig nstatus (2) conf_done (3) dclk data user i/o init_done bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck hi g h-z user mode (4) (4) table 13?15. ps timing parameters for strati x ii and stratix ii gx devices (part 1 of 2) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns
13?54 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration f device configuration options and how to create configuration files are discussed further in software settings in volume 2 of the configuration handbook . an example ps design that uses a max ii device as the external host for configuration will be availabl e when devices are available. ps configuration using a microprocessor in the ps configuration scheme, a micr oprocessor can control the transfer of configuration data from a storage device, such as flash memory, to the target stratix ii or stratix ii gx device. t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (1) s t cf2st1 nconfig high to nstatus high 100 (1) s t cf2ck nconfig high to first rising edge on dclk 100 s t st2ck nstatus high to first rising edge of dclk 2 s t dsu data setup time before rising edge on dclk 5 ns t dh data hold time after rising edge on dclk 0 ns t ch dclk high time 4 ns t cl dclk low time 4 ns t clk dclk period 10 ns f max dclk frequency 100 mhz t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (2) 20 100 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 clkusr period) notes to table 13?15 : (1) this value is applicable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (2) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting the device. table 13?15. ps timing parameters for strati x ii and stratix ii gx devices (part 2 of 2) symbol parameter min max units
altera corporation 13?55 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices 1 all information in the ?ps configuration using a max ii device as an external host? section is also applicable when using a microprocessor as an external host. refer to that section for all configuration and timing information. ps configuration using a configuration device you can use an altera configuratio n device, such as an enhanced configuration device, to configure stratix ii and stratix ii gx devices using a serial configuration bitstream. configuration data is stored in the configuration device. figure 13?21 shows the configuration interface connections between a stratix ii or stratix ii gx device and a configuration device. 1 the figures in this chapter only show the configuration-related pins and the configuration pin connections between the configuration device and the device. f for more information on the enhanc ed configuration device and flash interface pins (such as pgm[2..0] , exclk , porsel , a[20..0] , and dq[15..0] ), refer to the enhanced configuration devices ( epc4, epc8, epc16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook .
13?56 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration figure 13?21. single device ps configuratio n using an enhanced configuration device notes to figure 13?21 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. f the value of the internal pull-up resi stors on the enhanced configuration devices can be found in the operating conditions table of the enhanced configuration devices ( epc4, epc8, & epc16 ) d ata sheet chapter in volume 2 of the configuration handbook or the configuration devices for sram-based lut devices data sheet chapter in volume 2 of the configuration handbook . when using enhanced co nfiguration devices, nconfig of the device can be connected to ninit_conf of the configuration device, which allows the init_conf jtag instruction to initiate device configuration. the ninit_conf pin does not need to be connect ed if its functionality is not used. an internal pull -up resistor on the ninit_conf pin is always active in enhanced configuration devices, which means an external pull-up resistor should not be used if nconfig is tied to ninit_conf . upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state al l user i/o pins. the configuration device also goes through a por delay to allow the power supply to stabilize. the por time for epc2 devices is 200 ms (maximum). the por time for enhanced configur ation devices can be set to either stratix ii device dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig vcc vcc gnd (1) (1) nce (3) (3) nceo n.c. enhanced confi g uration device (3) (3) 10 k 10 k msel1 msel0 gnd msel3 msel2 v cc
altera corporation 13?57 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices 100 ms or 2 ms, depending on its porsel pin setting. if the porsel pin is connected to gnd, the por delay is 100 ms. if the porsel pin is connected to v cc , the por delay is 2 ms. during this time, the configuration device drives its oe pin low. this low signal delays configuration because the oe pin is connected to the target device?s nstatus pin. 1 when selecting a por time, you need to ensure that the device completes power-up before the enhanced configuration device exits por. altera recommends that you choose a por time for the stratix ii or stratix ii gx device of 12 ms, while selecting a por time for the enhanced co nfiguration device of 100 ms. when both devices complete por, they release their open-drain oe or nstatus pin, which is then pulled high by a pull-up resistor. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 2 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 2 of the stratix ii gx device handbook . when the power supplies have reached the appropriate operating voltages, the target device senses the low-to-high transition on nconfig and initiates the configuration cycle. the configuration cycle consists of three stages: reset, configurat ion, and initialization. while nconfig or nstatus are low, the device is in reset. the beginning of configuration can be delayed by holding the nconfig or nstatus pin low. 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. when nconfig goes high, the device comes out of reset and releases the nstatus pin, which is pulled high by a pull-up resistor. enhanced configuration and epc2 devices have an optional internal pull-up resistor on the oe pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used, an external 10-k pull-up resistor on the oe - nstatus line is required. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins.
13?58 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration when nstatus is pulled high, oe of the configuration device also goes high and the configuration device clocks data out serially to the device using the stratix ii or stratix ii gx device?s internal oscillator. the stratix ii and stratix ii gx devices receive configuration data on the data0 pin and the clock is received on the dclk pin. data is latched into the device on the rising edge of dclk . after the device has received all configuration data successfully, it releases the open-drain conf_done pin, which is pulled high by a pull-up resistor. since conf_done is tied to the configuration device?s ncs pin, the configuration device is disabled when conf_done goes high. enhanced configuration and epc2 devices have an optional internal pull-up resistor on the ncs pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used , an external 10-k pull-up resistor on the ncs - conf_done line is required. a low-to-high transition on conf_done indicates configuration is complete and initialization of the device can begin. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if you are using internal oscillator, the stratix ii or stratix ii gx device supplies itself with enough clock cycles for proper initialization. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. you can turn on the enable user-supplied start-up clock ( clkusr ) option in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr will not affect the configuration process. after all configuration data has been accepted and conf_done goes high, clkusr will be enabled after the time specified as t cd2cu . after this time period elapses, the stra tix ii and stratix ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if you are using the init_done pin, it will be high due to an external 10-k pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled hi gh. this low-to-hi gh transition signals that the device has entered us er mode. in user-mode, the user i/o
altera corporation 13?59 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices pins will no longer have weak pull-up resistors and will function as assigned in your design. enhanced configuration devices and epc2 devices drive dclk low and data0 high at the end of configuration. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. since the nstatus pin is tied to oe , the configuration device will also be reset. if the auto-restart configuration after error option, available in the quartus ii software, from the general tab of the device & pin options dialog box is turned on, the device automatically initiates reconfiguration if an error occurs. the stratix ii and stratix ii gx devices release the nstatus pin after a reset time-out period (maximum of 100 s). when the nstatus pin is released and pulled high by a pull-up resistor, the configuration device reconfigures the chain. if this option is turned off, the exte rnal system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configuration. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . in addition, if the configuration device sends all of its data and then detects that conf_done has not gone high, it re cognizes that the device has not configured successfully. enha nced configuration devices wait for 64 dclk cycles after the last configuration bit was sent for conf_done to reach a high state. epc2 devices wait for 16 dclk cycles. in this case, the configuration device pulls its oe pin low, driving the target device?s nstatus pin low. if the auto-restart configuration after error option is set in the software, the target device resets and then releases its nstatus pin after a reset time-out peri od (maximum of 100 s). when nstatus returns to a logic high level, the conf iguration device tries to reconfigure the device. when conf_done is sensed low after configuration, the configuration device recognizes that the target device has not configured successfully. therefore, your system should not pull conf_done low to delay initialization. instead, use the clkusr option to synchronize the initialization of multiple devices that are not in the same configuration chain. devices in the same configurat ion chain will initialize together if their conf_done pins are tied together. 1 if you are using the optional clkusr pin and nconfig is pulled low to restart configuration duri ng device initialization, you need to ensure that clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, pulling the nconfig pin low initiates a reconfiguration. the nconfig pin should be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. because conf_done is pulled low, this
13?60 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration activates the configuration device because it sees its ncs pin drive low. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 13?22 shows how to configure multip le devices with an enhanced configuration device. this circuit is similar to the configuration device circuit for a single device, except stratix ii or stratix ii gx devices are cascaded for multi-device configuration. figure 13?22. multi-device ps c onfiguration using an enhanc ed configuration device notes to figure 13?22 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. 1 enhanced configuration devices cannot be cascaded. when performing multi-device configuration, you must generate the configuration device's pof from each project?s sof. you can combine multiple sofs using the convert programming files window in the quartus ii software. f for more information on how to create configuration files for multi-device configuratio n chains, refer to the software settings chapter of the configuration handbook. enhanced confi g uration device dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig vcc vcc gnd nce dclk data0 nstatus conf_done nconfig nce nceo (1) (1) (3) nceo stratix ii or stratix ii gx device 2 stratix ii or stratix ii gx device 1 (3) n.c. 10 k 10 k (3) (3) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 13?61 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices in multi-device ps configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, prompting the second device to begin configuration. all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buff ering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. when configuring multiple devices, co nfiguration does not begin until all devices release their oe or nstatus pins. similarly, since all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this low signal drives the oe pin low on the enhanced configuration device and drives nstatus low on all devices, causing them to enter a reset state. this behavior is similar to a single device detecting an error. if the auto-restart configuration after error option is turned on, the devices will automatically initiate reconfiguration if an error occurs. the devices will release their nstatus pins after a reset time-out period (maximum of 100 s). when all the nstatus pins are released and pulled high, the configuration device trie s to reconfigure the chain. if the auto-restart configuration after error option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configurat ion. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . the enhanced configuration devices al so support parallel configuration of up to eight devices. the n-bit ( n = 1, 2, 4, or 8) ps configuration mode allows enhanced configuration device s to concurrently configure devices or a chain of devices. in addition, thes e devices do not have to be the same device family or density as they can be any combination of altera devices. an individual enhanced configuration device data line is available for each targeted device. each data line can also feed a daisy chain of devices. figure 13?23 shows how to concurrently configure multiple devices using an enhanced configuration device.
13?62 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration figure 13?23. concurrent ps configura tion of multiple devices using an enhanced configuration device notes to figure 13?23 : (1) the pull-up resistor sh ould be connected to the same supply voltage as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if it s functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if intern al pull-up resistors are used, external pull-up resistors should not be used on th ese pins. the internal pull-up resistors are used by default in the quartus ii soft ware. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. dclk data 0 nstatus conf_done nconfig v cc gnd (3) nce (3) stratix ii device 1 v cc dclk data 0 nconfig nce dclk data0 gnd gnd dclk data 0 oe (3) ncs (3) ninit_conf (2) data 1 data[2..6] nstatus conf_done nstatus conf_done nconfig nce data 7 10 k 10 k stratix ii device 2 stratix ii device 8 n.c. nceo n.c. nceo n.c. nceo (1) (1) enhanced confi g uration device msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 13?63 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices the quartus ii software only allo ws the selection of n-bit ps configuration modes, where n must be 1, 2, 4, or 8. however, you can use these modes to configure any number of devices from 1 to 8. when configuring sram-based devices using n-bit ps modes, use table 13?16 to select the appropriate configuration mode for the fastest configuration times. for example, if you configure three devices, you would use the 4-bit ps mode. for the data0 , data1 , and data2 lines, the corresponding sof data is transmitted from the config uration device to the device. for data3 , you can leave the corresponding bit3 line blank in the quartus ii software. on the pcb, leave the data3 line from the enhanced configuration device unconnected. alternatively, you can daisy chain two devices to one data line while the other data lines drive one device each. for example, you could use the 2-bit ps mode to drive two devices with data bit0 (two ep2s15 devices) and the third device (ep2s30 device) with data bit1. this 2-bit ps configuration scheme requires less space in the configuration flash memory, but can increase the total system configuration time. a system may have multiple devices that contain the sa me configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left floating. a ll other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent cl ock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices will start and complete table 13?16. recommended configurat ion using n-bit ps modes number of devices (1) recommended configuration mode 11-bit ps 22-bit ps 34-bit ps 44-bit ps 58-bit ps 68-bit ps 78-bit ps 88-bit ps note to table 13?16 : (1) assume that each data line is only configuring on e device, not a daisy chain of devices.
13?64 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration configuration at the same time. figure 13?24 shows multi-device ps configuration when the stratix ii or stratix ii gx devices are receiving the same configuration data. figure 13?24. multiple-device ps configuration usi ng an enhanced configuration device when devices receive the same data notes to figure 13?24 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) the nceo pins of all devices are left unco nnected when configuring the same configuration data into multiple devices. dclk data 0 nconfig v cc gnd (3) nce (3) v cc dclk data 0 nstatus conf_done nconfig nce nstatus conf_done dclk data0 nconfig nce gnd gnd stratix ii or stratix ii gx device 1 stratix ii or stratix ii gx device 2 last stratix ii or stratix ii gx device dclk data 0 oe ncs ninit_conf (2) nstatus conf_done n.c. nceo n.c. nceo n.c. nceo (4) (4) (4) (1) (1) 10 k 10 k (3) (3) enhanced confi g uration device msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 13?65 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices you can cascade several epc2 devices to configure multiple stratix ii or stratix ii gx devices. the first configuration device in the chain is the master configuration device, while the subsequent devices are the slave devices. the master configuration device sends dclk to the stratix ii or stratix ii gx devices and to the slave co nfiguration devices. the first epc device?s ncs pin is connected to the conf_done pins of the devices, while its ncasc pin is connected to ncs of the next configuration device in the chain. the last device?s ncs input comes from the previous device, while its ncasc pin is left floating. when all data from the first configuration device is sent, it drives ncasc low, which in turn drives ncs on the next configuration device. a configuration device requires less than one clock cycle to activate a subsequent configuration device, so the data stream is uninterrupted. 1 enhanced configuration devices cannot be cascaded. because all nstatus and conf_done pins are tied together, if any device detects an error, the master configur ation device stops configuration for the entire chain and the entire chain must be reconfigured. for example, if the master configuration device does not detect conf_done going high at the end of configuration, it resets the entire chain by pulling its oe pin low. this low signal drives the oe pin low on the slave configuration device(s) and drives nstatus low on all devices, causing them to enter a reset state. this behavior is similar to the device detecting an error in the configuration data.
13?66 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration figure 13?25 shows how to configure multiple devices using cascaded epc2 devices. figure 13?25. multi-device ps configur ation using cascaded epc2 devices notes to figure 13?25 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin (available on enhanced conf iguration devices and epc2 device s only) has an internal pull-up resistor that is always active, meaning an extern al pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. (3) the enhanced configuration devices? and epc2 devices? oe and ncs pins have internal programmable pull-up resistors. external 10-k pull-up resistors should be us ed. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. when using enhanced configuration devices or epc2 devices, nconfig of the device can be connected to ninit_conf of the configuration device, allowing the init_conf jtag instruction to initiate device configuration. the ninit_conf pin does not need to be connected if its functionality is not used. an in ternal pull-up resistor on the ninit_conf pin is always active in the enhanced configuration devices and the epc2 devices, which means that you should n?t be using an external pull-up resistor if nconfig is tied to ninit_conf . if you are using multiple epc2 devices to configure a stratix ii or stratix ii gx device(s), only the first epc2 has its ninit_conf pin tied to the device?s nconfig pin. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. epc2/epc1 device 1 dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig vcc vcc gnd nce vcc dclk data ncs oe dclk data0 nstatus conf_done nconfig nce nceo (2) ncasc stratix ii device 1 (1) (1) (1) (3) nceo ninit_conf stratix ii device 2 (3) n.c. epc2/epc1 device 2 10 k 10 k 10 k (3) (3) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 13?67 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in the configuration handbook . figure 13?26 shows the timing waveform fo r the ps config uration scheme using a configuration device. figure 13?26. stratix ii and stratix ii gx ps configuration usi ng a configuration device timing waveform note to figure 13?26 : (1) the initialization clock can come from the stratix ii or stratix ii g x device?s internal oscillator or the clkusr pin. f for timing information, refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet chapter in volume 2 of the configuration handbook or the configuration devices for sram-based lut devices data sheet chapter in volume 2 of the configuration handbook . f device configuration options and how to create configuration files are discussed further in the software settings chapter in volume 2 of the configuration handbook . ps configuration using a download cable in this section, the generic term ?d ownload cable? includes the altera usb-blaster ? universal serial bus (usb) port download cable, masterblaster ? serial/usb communications cable, byteblaster ? ii parallel port download cable, and the byteblaster mv parallel port download cable. in ps configuration with a download ca ble, an intelligen t host (such as a pc) transfers data from a storage device to the device via the usb blaster, masterblaster, byteblaster ii, or byteblastermv cable. dd d d 0 1 2 3 d n tri-state user mode ( 1 ) t oezx t por t ch t cl t dsu t co t dh tri-state oe/nstatus ncs/conf_done dclk data user i/o init_done ninit_conf or vcc/nconfig
13?68 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins an d dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook and the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook. the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. to initiate configuration in this scheme, the download cable generates a low-to-high transition on the nconfig pin. 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k pull-up resistor. once nstatus is released the device is ready to receive configuration data and the configuration stage begins. the programming hardware or download cable then plac es the configuration data one bit at a time on the device?s data0 pin. the configuration data is clocked into the target device until conf_done goes high. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. when using a download cable, setting the auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the quartus ii software when an error occurs. additionally, the enable user-supplied start-up clock ( clkusr ) option has no affect on the device initialization since this option is disabled in the sof when programming the device using the quartus ii programmer and download ca ble. therefore, if you turn on the clkusr option, you do not need to provide a clock on clkusr when you are configuring the device with the quartus ii programmer and a
altera corporation 13?69 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices download cable. figure 13?27 shows ps configuration for stratix ii or stratix ii gx devices using a usb blaster, masterblaster, byteblaster ii, or byteblastermv cable. figure 13?27. ps configuration using a usb blaster, masterblas ter, byteblaster ii or byteblastermv cable notes to figure 13?27 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii or byteblastermv cable. (2) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this ensures that data0 and dclk are not left floating after conf iguration. for example, if you are also using a configuration de vice, the pull-up resistors on data0 and dclk are not needed. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. you can use a download cable to configure multiple stratix ii or stratix ii gx devices by connecting each device?s nceo pin to the subsequent device?s nce pin. the first device?s nce pin is connected to gnd while its nceo pin is connected to the nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. al l other config uration pins, nconfig , nstatus , dclk , data0 , and conf_done are connected to every device in the chain. because all conf_done pins are tied together, all devices in the chain initialize and enter user mode at the same time. d ownlo ad cab l e 1 0 -pin m a l e h eader (ps mo de ) v cc (1) v cc (1) v cc v cc (1) v cc (1) v cc (1) stratix ii or stratix ii gx device dclk nconfig conf_done shield gnd 10 k 10 k 10 k 10 k 10 k nstatus data0 pin 1 nce gnd gnd v io (3) (2) (2) nceo n.c. msel1 msel0 gnd msel3 msel2 v cc
13?70 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration in addition, because the nstatus pins are tied together, the entire chain halts configuration if any de vice detects an error. the auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the quartus ii software when an error occurs. figure 13?28 shows how to configure multiple stratix ii or stratix ii gx devices with a download cable. figure 13?28. multi-device ps configur ation using a usb blaster, mast erblaster, byteblaster ii or byteblastermv cable notes to figure 13?28 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii or byteblastermv cable. (2) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after co nfiguration. for example, if you are also using a configuration device, the pull-up resistors on data0 and dclk are not needed. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. stratix ii or stratix ii gx device 1 stratix ii or stratix ii gx device 2 nce nconfig conf_done dclk nce nconfig conf_done dclk nceo gnd (ps mo de ) v cc v cc (1) v cc (1) v cc (1) v cc (1) v cc (1) nstatus nstatus data0 data0 gnd 10 k 10 k 10 k 10 k 10 k pin 1 d ownlo ad cab l e 1 0 -pin m a l e h eader nceo n.c. gnd v io (3 ) (2) (2) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 13?71 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices if you are using a download cable to configure device(s) on a board that also has configuration devices, elec trically isolate the configuration device from the target device(s) an d cable. one way of isolating the configuration device is to add logic, such as a multiplexer, that can select between the configuration device and the cable. the multiplexer chip allows bidirectional transfers on the nstatus and conf_done signals. another option is to add switch es to the five common signals ( nconfig , nstatus , dclk , data0 , and conf_done ) between the cable and the configuration device. the last option is to remove the configuration device from the board when config uring the device with the cable. figure 13?29 shows a combination of a configuration device and a download cable to configure an device.
13?72 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive serial configuration figure 13?29. ps configuration with a download cable and configurat ion device circuit notes to figure 13?29 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. (3) you should not attempt configuration with a download cable while a configuration device is connected to a stratix ii or stratix ii gx device. instead, you should either remove the configuration device from its socket when using the download cable or place a switch on the five common signals between the download cable and the configuration device. (4) the ninit_conf pin (available on enhanced conf iguration devices and epc2 device s only) has an internal pull-up resistor that is always active. this means an exte rnal pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. (5) the enhanced configuration devices? and epc2 devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-u p resistors are used, external pull-up resistors should not be used on these pins. the internal pull-up resistors are used by default in the quartu s ii software. to turn off the internal pull-up resistors, check the disable ncs and oe pull-up resistors on configuration device option when generating programming files. f for more information on how to use the usb blaster, masterblaster, byteblaster ii or byteblastermv cables , refer to the following data sheets: usb blaster download cable user guide masterblaster serial /usb communications cable user guide byteblaster ii download cable user guide byteblastermv download cable user guide stratix ii or stratix ii gx device nce nconfig conf_done dclk nceo gnd d ownlo ad cab l e 1 0 -pin m a l e h eader (ps mo de ) v cc v cc v cc (1) v cc (1) nstatus data0 gnd 10 k 10 k 10 k pin 1 confi g uration device (3) (3) (3) (3) (3) gn d vio (2) n.c. (1) (4) (5) (5) dclk data oe ncs ninit_conf (4) (5) (5) msel1 msel0 gnd msel3 msel2 v cc
altera corporation 13?73 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices passive parallel asynchronous configuration passive parallel asynchronous (ppa) configuration uses an intelligent host, such as a microprocessor, to transfer configuration data from a storage device, such as flash me mory, to the target stratix ii or stratix ii gx device. configuration data can be stored in rbf, hex, or ttf format. the host system outputs byte-wide data and the accompanying strobe signals to the device. when using ppa, pull the dclk pin high through a 10-k pull- up resistor to prevent unused conf iguration input pins from floating. 1 you cannot use the stratix ii or stratix ii gx decompression and design security features if you are configuring your stratix ii or stratix ii gx device using ppa mode. table 13?17 shows the msel pin settings when using the ps configuration scheme. figure 13?30 shows the configuration inte rface connections between the device and a microprocessor for single device ppa configuration. the microprocessor or an optional addr ess decoder can control the device?s chip select pins, ncs and cs . the address decoder allows the microprocessor to select the stratix ii or stratix ii gx device by accessing a particular address, which simplifies the configuration process. hold the ncs and cs pins active during configuration and initialization. table 13?17. stratix ii and stratix ii gx msel pin settings for ppa configuration schemes configuration schem e msel3 msel2 msel1 msel0 ppa 0001 remote system upgrade ppa (1) 0101 note to table 13?17 : (1) this scheme requires that you drive the runlu pin to specify either remote update or local update. for more information about remote system upgrades in stratix ii and stratix ii gx devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook .
13?74 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive parallel asynchronous configuration figure 13?30. single device ppa confi guration using a microprocessor notes to figure 13?30 : (1) if not used, the cs pin can be connected to v cc directly. if not used, the ncs pin can be connected to gnd directly. (2) the pull-up resistor should be connected to a supply that provides an acceptable input signal for the device. v cc should be high enough to meet the v ih specification of the i/o on the device and the external host. during ppa configuration, it is only required to use either the ncs or cs pin. therefore, if you are using only one chip-select input, the other must be tied to the active state. for example, ncs can be tied to ground while cs is toggled to control configuration. the device?s ncs or cs pins can be toggled during ppa configuration if the design meets the specifications set for t cssu , t wsp , and t csh listed in table 13?18 . upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins an d dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. msel3 msel2 msel1 msel0 stratix ii or stratix ii gx device dclk 10 k 10 k 10 k ncs cs conf_done nstatus nce data[7..0] nws nrs nconfig rdynbsy address decoder v cc v cc v cc addr microprocessor v cc memory addr data[7..0] gnd nceo n.c. (2) (2) (2) (1) (1) gnd
altera corporation 13?75 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices 1 you can hold nconfig low in order to stop device configuration. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook and the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. to initiate configuration, the microprocessor must generate a low-to-high transition on the nconfig pin. 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k pull-up resistor. once nstatus is released the device is ready to receive configuration data and the configuration stage begins. when nstatus is pulled high, the microprocessor should then assert the target device?s ncs pin low and/or cs pin high. next, the microprocessor places an 8-bit configuration word (one byte ) on the target device?s data[7..0] pins and pulses the nws pin low. on the rising edge of nws , the target device latches in a byte of configuration data and drives its rdynbsy signal low, which indicates it is processing the byte of configuration data. the microprocessor can then perform other system functions while the stratix ii or stratix ii gx device is processing the byte of configuration data. during the time rdynbsy is low, the stratix ii or stratix ii gx device internally processes the configuration data using its internal oscillator (typically 100 mhz). when the device is ready for the next byte of configuration data, it will drive rdynbsy high. if the microprocessor senses a high signal when it polls rdynbsy , the microprocessor sends the next byte of configuration data to the device. alternatively, the nrs signal can be strobed low, causing the rdynbsy signal to appear on data7 . because rdynbsy does not need to be monitored, this pin doesn?t need to be connected to the microprocessor. do not drive data onto the data bus while nrs is low because it will cause contention on the data7 pin. if you are not using the nrs pin to monitor configuration, it should be tied high.
13?76 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive parallel asynchronous configuration to simplify configuration and save an i/o port, the microprocessor can wait for the total time of t busy (max) + t rdy2ws + t w2sb before sending the next data byte. in this set-up, nrs should be ti ed high and rdynbsy does not need to be connected to the microprocessor. the t busy , t rdy2ws , and t w2sb timing specifications are listed in table 13?18 on page 13?82 . next, the microprocessor checks nstatus and conf_done . if nstatus is not low and conf_done is not high, the microprocessor sends the next data byte. however, if nstatus is not low and all the configuration data has been received, the device is ready for initialization. the conf_done pin will go high one byte early in parallel configuration (fpp and ppa) modes. the last byte is required for serial configuration (as and ps) modes. a low-to-high transition on conf_done indicates configuration is complete and initialization of the device can begin. the open-drain conf_done pin is pulled high by an external 10-k pull-up resistor. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used , the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initialization. therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. suppl ying a clock on clkusr does not affect the configuration process. after conf_done goes high, clkusr is enabled after the time specified as t cd2cu . after this time period elapses, the stratix ii and stratix ii gx devices re quire 299 clock cycles to initialize properly and enter user mode. stratix ii devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. this enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used it is high because of an external 10-k pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the
altera corporation 13?77 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices init_done pin is released and pulled high. the microprocessor must be able to detect this low-to-high tran sition that signals the device has entered user mode. when initialization is complete, the device enters user mode. in user-mode, the user i/o pi ns no longer have weak pull-up resistors and function as assigned in your design. to ensure data[7..0] is not left floating at the end of configuration, the microprocessor must drive them either high or low, whichever is convenient on your board. after configuration, the ncs , cs , nrs , nws , rdynbsy , and data[7..0] pins can be used as user i/o pins. when choosing the ppa scheme in the quartus ii software as a default, these i/o pins are tri-stated in user mode and should be driven by the microprocessor. to change this default option in the quartus ii software, select the dual-purpose pins tab of the device & pin options dialog box. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the microproce ssor that there is an error. if the auto-restart configuration after error option-available in the quartus ii software from the general tab of the device & pin options dialog box-is turned on, the device releases nstatus after a reset time-out period (maximum of 100 s). after nstatus is released and pulled high by a pull-up resistor, the microprocessor can try to reconf igure the target device without needing to pulse nconfig low. if this option is turned off, the microprocessor must generate a low-to -high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the microprocessor can also monitor the conf_done and init_done pins to ensure successful configuration. to detect errors and determine when programming completes, monitor the conf_done pin with the microprocessor. if the microprocessor sends all configuration data but conf_done or init_done has not gone high, the microprocessor must reconfigure the target device. 1 if you are using the optional clkusr pin and nconfig is pulled low to restart configuration during device initialization, ensure clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, a reconfiguration can be initiated by transitioning the nconfig pin low-to-high. the nconfig pin should go low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins.
13?78 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive parallel asynchronous configuration figure 13?31 shows how to configure multiple stratix ii or stratix ii gx devices using a microprocessor. this circuit is similar to the ppa configuration circuit for a single device, except the devices are cascaded for multi-device configuration. figure 13?31. multi-device ppa confi guration using a microprocessor notes to figure 13?31 : (1) if not used, the cs pin can be connected to v cc directly. if not used, the ncs pin can be connected to gnd directly. (2) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. in multi-device ppa configuration the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins co nfiguration within one clock cycle. therefore, the transfer of data destinations is transparent to the microprocessor. each device?s rdynbsy pin can have a sepa rate input to the microprocessor. alternatively, if the mi croprocessor is pin limited, all the rdynbsy pins can feed an and gate and the output of the and gate can feed the microprocessor. for example, if you have two devices in a ppa gnd v cc address decoder addr addr memory data[7..0] ncs cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy ncs cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy microprocessor data[7..0] v cc data[7..0] nceo n.c. nceo (2) (2) dclk v cc (2) dclk (2) v cc 10 k stratix ii device 1 stratix ii device 2 (1) (1) msel3 msel2 msel1 msel0 vcc gnd 10 k 10 k 10 k
altera corporation 13?79 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices configuration chain, the second device?s rdynbsy pin will be high during the time that the first device is being configured. when the first device has been successfully configured, it will drive nceo low to activate the next device in the chain and drive its rdynbsy pin high. therefore, since rdynbsy signal is driven high before configuration and after configuration before entering user-mode, the device being configured will govern the output of the and gate. the nrs signal can be used in multi-device ppa chain because the stratix ii and stratix ii gx devices tri-state the data[7..0] pins before configuration and after configuration before entering user-mode to avoid contention. therefore, only the device that is currently being configured responds to the nrs strobe by asserting data7 . all other configuration pins ( nconfig , nstatus , data[7..0] , ncs , cs , nws , nrs and conf_done ) are connected to every device in the chain. it is not necessary to tie ncs and cs together for every device in the chain, as each device?s ncs and cs input can be driven by a separate source. configuration signals may require buffering to ensure signal integrity and prevent clock skew pr oblems. ensure that the data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart config uration after error option is turned on, the devices release their nstatus pins after a reset time-out period (maximum of 100 s). after all nstatus pins are released and pulled high, the microprocessor can try to reconfigure the chai n without needing to pulse nconfig low. if this option is tu rned off, the microprocessor must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. in your system, you may have multi ple devices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left fl oating. all other configuration pins ( nconfig , nstatus , data[7..0] , ncs , cs , nws , nrs and conf_done ) are connected to every device in the chain. configuration signals may require buffering to ensure signal integrity and prevent clock skew pr oblems. ensure that the data lines are buffered for every fourth device. devices must be the same density and package.
13?80 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive parallel asynchronous configuration all devices start and complete configuration at the same time. figure 13?32 shows multi-device ppa configuration when both devices are receiving the same configuration data. figure 13?32. multiple-device ppa conf iguration using a microprocessor when both devices receive the same data notes to figure 13?32 : (1) if not used, the cs pin can be connected to v cc directly. if not used, the ncs pin can be connected to gnd directly. (2) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. (3) the nceo pins of both devices are left unconnected when conf iguring the same configuration data into multiple devices. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices that support ppa configuration, such as stratix, mercury ? , apex ? 20k, acex ? 1k, and flex ? 10ke devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . gnd v cc address decoder addr addr memory data[7..0] ncs (1) cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy ncs (1) cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy microprocessor data[7..0] v cc data[7..0] nceo n.c. (3) nceo (2) (2) dclk v cc (2) dclk (2) v cc stratix ii device stratix ii device 10 k 10 k 10 k 10 k (3) gnd msel3 msel2 msel1 msel0 vcc gnd msel3 msel2 msel1 msel0 vcc gnd
altera corporation 13?81 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices ppa configuration timing figure 13?33 shows the timing waveform for the ppa configuration scheme using a microprocessor. figure 13?33. stratix ii and stratix ii gx ppa c onfiguration timing waveform using nws note (1) notes to figure 13?33 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, stratix ii and stratix ii gx devices hold nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) the user can toggle ncs or cs during configuration if the design meets the specification for t cssu , t wsp , and t csh . (5) data[7..0] , cs , ncs , nws , nrs , and rdynbsy are available as user i/o pins after configuration and the state of theses pins depends on the dual-purpose pin settings. byte 0 byte 1 t dh t wsp t cf2ws nconfig nstatus ( 2) conf_done ( 3) data[7..0] (4) cs (4) ncs nws rdynbsy byte n ? 1 byte n t busy t ws2b t rdy2ws t cfg t status user i/os init_done hi g h-z t cf2st0 t cf2cd ( 5) ( 5) ( 5) ( 5) t cf2st1 t dsu t cssu t csh t cd2um (5) user-mode hi g h-z
13?82 altera corporation stratix ii gx device handbook, volume 2 october 2007 passive parallel asynchronous configuration figure 13?34 shows the timing waveform for the ppa configuration scheme when using a strobed nrs and nws signal. figure 13?34. stratix ii and stratix ii gx ppa conf iguration timing waveform using nrs and nws note (1) notes to figure 13?34 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, stratix ii and stratix ii gx devices hold nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) the user can toggle ncs or cs during configuration if the design meets the specification for t cssu , t wsp , and t csh . (5) data[7..0] , cs , ncs , nws , nrs , and rdynbsy are available as user i/o pins after configuration and the state of theses pins depends on the dual-purpose pin settings. (6) data7 is a bidirectional pin. it is an in put for configuration data input, but it is an output to show the status of rdynbsy . table 13?18 defines the timing parameters for stratix ii and stratix ii gx devices for ppa configuration. byte 0 byte 1 byte n nconfig (2) nstatus (3) conf_done (4) ncs (4) cs data[7..0] nws nrs init_done user i/o (6) data7/rdynbsy t cssu t cfg t wsp t ws2rs t dh t busy t csh t dsu t cf2ws (5) (5) (5) (5) t cd2um t rs2ws t cf2st1 t cf2scd t status t ws2rs t ws2b t rdy2ws (5) (5) user-mode hi g h-z t rsd7 table 13?18. ppa timing parameters for stratix ii and stratix ii gx devices (part 1 of 2) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns
altera corporation 13?83 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices f device configuration options and how to create configuration files are discussed further in the software settings chapter in volume 2 the configuration handbook . t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (1) s t cf2st1 nconfig high to nstatus high 100 (1) s t cssu chip select setup time before rising edge on nws 10 ns t csh chip select hold time after rising edge on nws 0 ns t cf2ws nconfig high to first rising edge on nws 100 s t st2ws nstatus high to first rising edge on nws 2s t dsu data setup time before rising edge on nws 10 ns t dh data hold time after rising edge on nws 0 ns t wsp nws low pulse width 15 ns t ws2b nws rising edge to rdynbsy low 20 ns t busy rdynbsy low pulse width 745ns t rdy2ws rdynbsy rising edge to nws rising edge 15 ns t ws2rs nws rising edge to nrs falling edge 15 ns t rs2ws nrs rising edge to nws rising edge 15 ns t rsd7 nrs falling edge to data7 valid with rdynbsy signal 20 ns t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (2) 20 100 s t cd2cu conf_done high to clkusr enabled 40 ns t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 clkusr period) notes to table 13?18 : (1) this value is obtainable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (2) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device. table 13?18. ppa timing parameters for stratix ii and stratix ii gx devices (part 2 of 2) symbol parameter min max units
13?84 altera corporation stratix ii gx device handbook, volume 2 october 2007 jtag configuration jtag configuration the jtag has developed a specification for boundary-scan testing. this boundary-scan test (bst) architecture offers the capability to efficiently test components on pcbs with tight lead spacing. the bst architecture can test pin connections without usin g physical test probes and capture functional data while a device is operating normally. the jtag circuitry can also be used to shift configurat ion data into the device. the quartus ii software automatically generates so fs that can be used for jtag configuration with a download cable in the quartus ii software programmer. f for more information on jtag boundary-scan testing, refer to the following documents: ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook jam programming support - jtag technologies stratix ii and stratix ii gx devices are designed such that jtag instructions have precedence over any device configuration modes. therefore, jtag configuration can ta ke place without waiting for other configuration modes to complete. for example, if you attempt jtag configuration of stratix ii or stratix ii gx devices during ps configuration, ps config uration is terminated and jtag configuration begins. 1 you cannot use the stratix ii and stratix ii gx decompression or design security features if you are configuring your stratix ii or stratix ii gx device when using jtag-based configuration. a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms , and trst pins have weak internal pull-up resistors (typically 25 k ). the tdo output pin is powered by v ccio in i/o bank 4. all of the jtag input pins are powered by the 3.3-v v ccpd pin. all user i/o pins ar e tri-stated during jtag configuration. table 13?19 explains each jtag pin?s function. 1 the tdo output is powered by the v ccio power supply of i/o bank 4.
altera corporation 13?85 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices f for recommendations on how to conn ect a jtag chain with multiple voltages across the devices in the chain, refer to the ieee 1149.1 (jtag) boundary-scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the ieee 1149.1 (jtag) boundary-scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . during jtag configuration, data can be downloaded to the device on the pcb through the usb blaster, masterblaster, byteblaster ii, or byteblastermv download cable. configuring devices through a cable is similar to programming devices in-system, except the trst pin should be connected to v cc . this ensures that the tap controller is not reset. figure 13?35 shows jtag configuration of a single stratix ii or stratix ii gx device. table 13?19. dedicated jtag pins pin name pin type description tdi test data input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disa bled by connecting this pin to v cc . tdo test data output serial data output pin for instruct ions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. if the jtag ci rcuitry is not used, leave the tdo pin unconnected. tms test mode select input pin that provides the cont rol signal to determine the transitions of the tap controller state machine. transitions wi thin the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . tck test clock input the clock input to the bst circ uitry. some operations occur at the rising edge, while others occur at the falling edge. if t he jtag interface is not required on the board, the jtag circuitry can be disa bled by connecting this pin to gnd. trst test reset input (optional) active-low input to asynchronously reset the boundary-scan circuit. the trst pin is optional according to ieee std. 1149 .1. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to gnd.
13?86 altera corporation stratix ii gx device handbook, volume 2 october 2007 jtag configuration figure 13?35. jtag configurat ion of a single device using a download cable notes to figure 13?35 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii, or byteblastermv cable. (2) the nconfig , msel[3..0] pins should be connected to support a non- jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel[3..0] to ground. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. (4) nce must be connected to gnd or driven low for successful jtag configuration. to configure a single device in a jt ag chain, the programming software places all other devices in bypass mode. in bypass mode, devices pass programming data from the tdi pin to the tdo pin through a single bypass register without being affected internally. this scheme enables the programming software to program or verify the target device. configuration data driven into the device appears on the tdo pin one clock cycle later. the quartus ii software verifies su ccessful jtag configuration upon completion. at the end of configuratio n, the software checks the state of conf_done through the jtag port. when quartus ii generates a (. jam ) file for a multi-device chain, it contai ns instructions so that all the devices in the chain will be initialized at the same time. if conf_done is not high, the quartus ii software indicates that configuration has failed. if nce (4) msel[3..0] nconfig conf_done vcc (1) vcc gnd vcc gnd vcc (2) (2) vcc (1) 10 k 10 k 10 k 10 k nstatus pin 1 d ownlo ad cab l e 1 0 -pin m a l e h eader (jtag mo de ) (to p vi e w) gnd tck tdo tms tdi 10 k gnd vio (3) (1) (1) stratix ii device nce0 n.c. trst vcc
altera corporation 13?87 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices conf_done is high, the software indicates that configuration was successful. after the configuration bit stream is transmitted serially via the jtag tdi port, the tck port is clocked an ad ditional 299 cycles to perform device initialization. stratix ii and stratix ii gx devices have dedicated jtag pins that always function as jtag pins. not only can you perform jtag testing on stratix ii and stratix ii gx devices before and after, but also during configuration. while other device families do not support jtag testing during configuration, stratix ii and stratix ii gx devices support the bypass, idcode, and sample instructions during configuration without interrupting configuration. all other jtag instructions may only be issued by first interrupting config uration and reprogramming i/o pins using the config_io instruction. the config_io instruction allows i/o buffers to be configured via the jtag port and when issued, interrup ts configuration. this instruction allows you to perform board-level testing prior to configuring the stratix ii or stratix ii gx device or waiting for a configuration device to complete configuration. once conf iguration has been interrupted and jtag testing is complete, the part must be reconfigured via jtag ( pulse_config instruction) or by pulsing nconfig low. the chip-wide reset ( dev_clrn ) and chip-wide output enable ( dev_oe ) pins on stratix ii and stratix ii gx devices do not affect jtag boundary-scan or programming operatio ns. toggling these pins does not affect jtag operations (other than the usual boundary-scan operation). when designing a board for jtag configuration of stratix ii or stratix ii gx devices, consider the dedicated configuration pins. table 13?20 shows how these pins should be connected during jtag configuration. when programming a jtag device chai n, one jtag-compatible header is connected to several devices. the number of devices in the jtag chain is limited only by the drive capability of the download cable. when four or more devices are connected in a jtag chain, altera recommends buffering the tck , tdi , and tms pins with an on-board buffer.
13?88 altera corporation stratix ii gx device handbook, volume 2 october 2007 jtag configuration table 13?20. dedicated configurati on pin connections during jtag configuration signal description nce on all stratix ii or stratix ii gx devices in the chain, nce should be driven low by connecting it to ground, pulling it low via a resistor, or driving it by some c ontrol circuitry. for devices that are also in multi-device fpp, as, ps, or ppa configuration chains, the nce pins should be connected to gnd during jtag configuration or jtag configured in the same order as the configuration chain. nceo on all stratix ii or stratix ii gx devices in the chain, nceo can be left floating or connected to the nce of the next device. msel these pins must not be left floating. these pins support whichever non-jtag configurati on is used in production. if only jtag configuration is used, tie these pins to ground. nconfig driven high by connecting to v cc , pulling up via a resistor, or driven high by some control circuitry. nstatus pull to v cc via a 10-k resistor. when configuring multiple devices in the same jtag chain, each nstatus pin should be pulled up to v cc individually. conf_done pull to v cc via a 10-k resistor. when configuring multiple devices in the same jtag chain, each conf_done pin should be pulled up to v cc individually. conf_done going high at the end of jtag configuration indicates successful configuration. dclk should not be left floating. drive low or high, whichever is more convenient on your board.
altera corporation 13?89 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices jtag-chain device programming is ideal when the system contains multiple devices, or when testing your system using jtag bst circuitry. figure 13?36 shows multi-device jtag configuration. figure 13?36. jtag configuration of mult iple devices using a download cable notes to figure 13?36 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii or byteblastermv cable. (2) the nconfig, msel[3..0] pins should be connected to support a no n-jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel[3..0] to ground. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. (4) nce must be connected to gnd or driven low for successful jtag configuration. the nce pin must be connected to gnd or driven low during jtag configuration. in multi-device fpp, as, ps, and ppa configuration chains, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. in addition, the conf_done and nstatus signals are all shared in multi-device fpp, as, ps, or ppa configuration chains so the devices can enter user mode at the same time af ter configuration is complete. when the conf_done and nstatus signals are shared among all the devices, every device must be configured when jtag configuration is performed. if you only use jtag configuration, altera recommends that you connect the circuitry as shown in figure 13?36 , where each of the conf_done and nstatus signals are isolated, so that ea ch device can enter user mode individually. tms tck d ownlo ad cab l e 1 0 -pin m a l e h eader (jtag mo de ) tdi tdo vcc vcc vcc pin 1 nstatus nconfig msel[3..0] nce (4) vcc conf_done vcc tms tck tdi tdo nstatus nconfig msel0 msel[3..0] nce (4) vcc conf_done vcc tms tck tdi tdo nstatus nconfig msel0 msel[3..0] nce (4) vcc conf_done vcc (1) (2) (2) (2) (2) (2) (2) (2) (2) vio (3) stratix ii device stratix ii device stratix ii device trst trst trst vcc vcc vcc 10 k 10 k (1) (1) 10 k 10 k 10 k 10 k (1) (1) (1) (1) (1) 10 k 1 k 10 k
13?90 altera corporation stratix ii gx device handbook, volume 2 october 2007 jtag configuration after the first device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. therefore, if these devices are also in a jtag chain, make sure the nce pins are connected to gnd during jtag configuration or that the devices are jtag configured in the same order as the configuration chain. as long as the devices are jtag configured in the same order as the multi-device configuration chain, the nceo of the previous device will drive nce of the next device low when it has successfully been jtag configured. other altera devices that have jtag support can be placed in the same jtag chain for device prog ramming and configuration. 1 stratix, stratix ii, stratix ii gx, cyclone ? , and cyclone ii devices must be within the first 17 devices in a jtag chain. all of these devices have the same jtag controller. if any of the stratix, stratix ii, stratix ii gx, cyclone, and cyclone ii devices are in the 18th or after they will fail configuration. this does not affect signaltap ? ii. f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in the configuration handbook .
altera corporation 13?91 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices figure 13?37 shows jtag configuration of a stratix ii or stratix ii gx device with a microprocessor. figure 13?37. jtag configurat ion of a single device using a microprocessor notes to figure 13?37 : (1) the pull-up resistor sho uld be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on the device. (2) the nconfig , msel[3..0] pins should be connected to support a non-jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel[3..0] to ground. pull dclk either high or low, whichever is convenient on your board. (3) nce must be connected to gnd or driven low for successful jtag configuration. jam stapl jam stapl, jedec standard jesd-71, is a standard file format for in-system programmability (isp ) purposes. jam stapl supports programming or configuration of programmable devices and testing of electronic systems, usin g the ieee 1149.1 jtag in terface. jam stapl is a freely licensed open standard. the jam player provides an interfac e for manipulating the ieee std. 1149.1 jtag tap state machine. f for more information on jtag and jam stapl in embedded environments, refer to an 122: using jam stap l for isp & icr via an embedded processor . to download the jam player, visit the altera web site at www.altera.com . trst tdi tck tms tdo microprocessor memory addr data stratix ii device nstatus conf_done v cc v cc 1 k 1 k (1) (1) (3) nce nconfig n.c. gnd (2) (2) v cc nceo msel[3..0]
13?92 altera corporation stratix ii gx device handbook, volume 2 october 2007 device configuration pins device configuration pins the following tables describe the conne ctions and functionality of all the configuration related pins on the stratix ii and stratix ii gx devices. table 13?21 summarizes the stratix ii pin configuration. table 13?21. stratix ii configurat ion pin summary (part 1 of 2) note (1) bank description input/output dedica ted powered by configuration mode 3 pgm[2..0] output (2) ps, fpp, ppa, ru, lu 3 asdo output (2) as 3 ncso output (2) as 3 crc_error output (2) optional, all modes 3 data0 input (3) all modes except jtag 3 data[7..1] input (3) fpp, ppa 3 data7 bidirectional (2) , (3) ppa 3 rdynbsy output (2) ppa 3 init_done output pull-up optional, all modes 3 nstatus bidirectional yes pull-up all modes 3 nce input yes (3) all modes 3 dclk input yes (3) ps, fpp output (2) as 3 conf_done bidirectional yes pull-up all modes 8 tdi input yes vccpd jtag 8 tms input yes vccpd jtag 8 tck input yes vccpd jtag 8 trst input yes vccpd jtag 8 nconfig input yes (3) all modes 8 vccsel input yes vccint all modes 8 cs input (3) ppa 8 clkusr input (3) optional 8 nws input (3) ppa 8 nrs input (3) ppa 8 runlu input (3) ps, fpp, ppa, ru, lu 8 ncs input (3) ppa 7 porsel input yes vccint all modes 7 nio_pullup input yes vccint all modes
altera corporation 13?93 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices figure 13?38 shows the i/o bank locations. figure 13?38. stratix ii i/o bank numbers 7 pll_ena input yes (3) optional 7 nceo output yes (2) , (4) all modes 4 msel[3..0] input yes vccint all modes 4 tdo output yes (2) , (4) jtag notes to table 13?21 : (1) total number of pins is 41, tota l number of dedicated pins is 19. (2) all outputs are powered by vccio except as noted. (3) all inputs are powered by vccio or vccpd , based on the vccsel setting, except as noted. (4) an external pull-up resistor may be required for this conf iguration pin because of the multivolt i/o interface. refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook for pull-up or level shifter recommendations for nceo and tdo . table 13?21. stratix ii configurat ion pin summary (part 2 of 2) note (1) bank description input/output dedica ted powered by configuration mode bank 2 bank 5 bank 1 bank 6 bank 3 bank 4 bank 8 bank 7 stratix ii device i/o bank numbers
13?94 altera corporation stratix ii gx device handbook, volume 2 october 2007 device configuration pins table 13?22 describes the dedicated configuration pins, which are required to be connected properly on your board for successful configuration. some of these pins may not be required for your configuration schemes. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 1 of 10) pin name user mode configuration scheme pin type description v ccpd n/a all power dedicated power pin. this pin is used to power the i/o pre-drivers, the jtag input pins, and the configuration input pins that are affected by the voltage level of vccsel . this pin must be connected to 3.3-v. v ccpd must ramp-up from 0-v to 3.3-v within 100 ms. if v ccpd is not ramped up within this specified time, your stratix ii or stratix ii gx device will not configure successfu lly. if your system does not allow for a v ccpd ramp-up time of 100 ms or less, you must hold nconfig low until all power supplies are stable. vccsel n/a all input dedicated input that selects which input buffer is used on the pll_ena pin and the configuration input pins; nconfig , dclk (when used as an input), nstatus (when used as an input), conf_done (when used as an input), dev_oe , dev_clrn , data[7..0] , runlu , nce , nws , nrs , cs , ncs , and clkusr . the 3.3-v/2.5-v input buffer is powered by v ccpd , while the 1.8- v/1.5-v input buffer is powered by v ccio . the vccsel input buffer has an internal 5-k pull-down resistor that is always active. the vccsel input buffer is powered by v ccint and must be hardwired to v ccpd or ground. a logic high selects the 1.8-v/1.5-v input buffer, and a logic low selects the 3.3-v/2.5-v input buffer. for more information, refer to the ?vccsel pin? section.
altera corporation 13?95 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices porsel n/a all input dedicated input which selects between a por time of 12 ms or 100 ms. a logic high (1.5 v, 1.8 v, 2.5 v, 3.3 v) selects a por time of about 12 ms and a logic low selects por time of about 100 ms. the porsel input buffer is powered by v ccint and has an internal 5-k pull-down resistor that is always active. the porsel pin should be tied directly to v ccpd or gnd. nio_pullup n/a all input dedicated input that chooses whether the internal pull-up resistors on the user i/o pins and dual-purpose i/o pins ( ncso , nasdo , data[7..0] , nws , nrs , rdynbsy , ncs , cs , runlu , pgm[] , clkusr , init_done , dev_oe , dev_clr ) are on or off before and during configuration. a logic high (1.5 v, 1.8 v, 2.5 v, 3.3 v) turns off the weak internal pull-up resistors, while a logic low turns them on. the nio-pullup input buffer is powered by v ccpd and has an internal 5-k pull-down resistor that is always active. the nio-pullup can be tied directly to v ccpd or use a 1-k pull-up resistor or tied directly to gnd. msel[3..0] n/a all input 4-bit configuration input that sets the stratix ii and stratix ii gx device configuration scheme. refer to ta b l e 1 3 ? 1 for the appropriate connections. these pins must be hard-wired to v ccpd or gnd. the msel[3..0] pins have internal 5-k pull-down resistors that are always active. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 2 of 10) pin name user mode configuration scheme pin type description
13?96 altera corporation stratix ii gx device handbook, volume 2 october 2007 device configuration pins nconfig n/a all input configuration control input. pulling this pin low during user-mode will cause the device to lose its configuration data, enter a reset state, tri-state all i/o pins. returning this pin to a logic high level will initiate a reconfiguration. if your configuration scheme uses an enhanced configuration device or epc2 device, nconfig can be tied directly to v cc or to the configuration device?s ninit_conf pin. nstatus n/a all bidirectional open-drain the device drives nstatus low immediately after power-up and releases it after the por time. status output. if an error occurs during configuration, nstatus is pulled low by the target device. status input. if an external source drives the nstatus pin low during configuration or initialization, the target device enters an error state. driving nstatus low after configuration and initialization does not affect the configured device. if a configuration device is used, driving nstatus low will cause the configuration device to attempt to configure the device, but since the device ignores transitions on nstatus in user-mode, the device does not reconfigure. to initiate a reconfiguration, nconfig must be pulled low. the enhanced configuration devices? and epc2 devices? oe and ncs pins have optional internal programmable pull-up resistors. if internal pull-up resistors on the enhanced configuration device are used, external 10-k pull-up resistors should not be used on these pins. when using epc2 devices, only external 10-k pull-up resistors should be used. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 3 of 10) pin name user mode configuration scheme pin type description
altera corporation 13?97 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices nstatus (continued) if vccpd and vccio are not fully powered up, the following could occur: vccpd and vccio are powered high enough for the nstatus buffer to function properly, and nstatus is driven low. when vccpd and vccio are ramped up, por trips, and nstatus is released after por expires. vccpd and vccio are not powered high enough for the nstatus buffer to function properly. in this situation, nstatus might appear logic high, triggering a configuration attempt that would fail because por did not yet trip. when vccpd and vccio are powered up, nstatus is pulled low because por did not yet trip. when por trips after vccpd and vccio are powered up, nstatus is released and pulled high. at that point, reconfiguration is triggered and the device is configured. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 4 of 10) pin name user mode configuration scheme pin type description
13?98 altera corporation stratix ii gx device handbook, volume 2 october 2007 device configuration pins conf_done n/a all bidirectional open-drain status output. the target device drives the conf_done pin low before and during configuration. once al l configuration data is received without error and the initialization cycle starts, the target device releases conf_done . status input. after all data is received and conf_done goes high, the target device initializes and enters user mode. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. driving conf_done low after configuration and initialization does not affect the configured device. the enhanced configuration devices? and epc2 devices? oe and ncs pins have optional internal programmable pull-up resistors. if internal pull-up resistors on the enhanced configuration device are used, external 10-k pull-up resistors should not be used on these pins. when using epc2 devices, only external 10-k pull-up resistors should be used. nce n/a all input active-low chip enable. the nce pin activates the device with a low signal to allow configuration. the nce pin must be held low during configuration, initialization, and user mode. in single device configuration, it should be tied low. in multi-device configuration, nce of the first device is tied low while its nceo pin is connected to nce of the next device in the chain. the nce pin must also be held low for successful jtag programming of the device. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 5 of 10) pin name user mode configuration scheme pin type description
altera corporation 13?99 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices nceo n/a all output output that drives low when device configuration is complete. in single device configuration, this pin is left floating. in multi-device configuration, this pin feeds the next device?s nce pin. the nceo of the last device in the chain is left floating. the nceo pin is powered by v ccio in i/o bank 7. for recommendations on how to connect nceo in a chain with multiple voltages across the devices in the chain, refer to the stratix ii architecture chapter in volume 1 of the stratix ii handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . asdo n/a in as mode i/o in non-as mode as output control signal from the stratix ii or stratix ii gx device to the serial configuration device in as mode used to read out configuration data. in as mode, asdo has an internal pull-up resistor that is always active. ncso n/a in as mode i/o in non-as mode as output output control signal from the stratix ii or stratix ii gx device to the serial configuration device in as mode that enables the configuration device. in as mode, ncso has an internal pull-up resistor that is always active. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 6 of 10) pin name user mode configuration scheme pin type description
13?100 altera corporation stratix ii gx device handbook, volume 2 october 2007 device configuration pins dclk n/a synchronous configuration schemes (ps, fpp, as) input (ps, fpp) output (as) in ps and fpp configuration, dclk is the clock input used to clock data from an external source into the target device. data is latched into the device on the rising edge of dclk . in as mode, dclk is an output from the stratix ii or stratix ii gx device that provides timing for the configuration interface. in as mode, dclk has an internal pull-up resistor (typically 25 k ) that is always active. in ppa mode, dclk should be tied high to v cc to prevent this pin from floating. after configuration, this pin is tri-stated. in schemes that use a configuration device, dclk will be driven low after configuration is done. in schemes that use a control host, dclk should be driven either high or low, whichever is more convenient. toggling this pin after configuration does not affect the configured device. data0 i/o ps, fpp, ppa, as input data input. in serial configuration modes, bit-wide configuration data is presented to the target device on the data0 pin. the v ih and v il levels for this pin are dependent on the input buffer selected by the vccsel pin. refer to the section ?vccsel pin? on page 13?10 for more information. in as mode, data0 has an internal pull-up resistor that is always active. after configuration, data0 is available as a user i/o pin and the state of this pin depends on the dual-purpose pin settings. after configuration, epc1 and epc1441 devices tri-state this pin, while enhanced configuration and epc2 devices drive this pin high. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 7 of 10) pin name user mode configuration scheme pin type description
altera corporation 13?101 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices data[7..1] i/o parallel configuration schemes (fpp and ppa) inputs data inputs. byte-wide configuration data is presented to the target device on data[7..0] . the v ih and v il levels for this pin are dependent on the input buffer selected by the vccsel pin. refer to the section ?vccsel pin? on page 13?10 for more information. in serial configuration schemes, they function as user i/o pins during configuration, which means they are tri-stated. after ppa or fpp configuration, data[7..1] are available as user i/o pins and the state of these pin depends on the dual-purpose pin settings. data7 i/o ppa bidirectional in the ppa configuration scheme, the data7 pin presents the rdynbsy signal after the nrs signal has been strobed low. the v ih and v il levels for this pin are dependent on the input buffer selected by the vccsel pin. refer to the section ?vccsel pin? on page 13?10 for more information. in serial configuration schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, data7 is available as a user i/o and the state of this pin depends on the dual-purpose pin settings. nws i/o ppa input write strobe input. a low-to-high transition causes the device to latch a byte of data on the data[7..0] pins. in non-ppa schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, nws is available as a user i/o pins and the state of this pin depends on the dual-purpose pin settings. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 8 of 10) pin name user mode configuration scheme pin type description
13?102 altera corporation stratix ii gx device handbook, volume 2 october 2007 device configuration pins nrs i/o ppa input read strobe input. a low input directs the device to drive the rdynbsy signal on the data7 pin. if the nrs pin is not used in ppa mode, it should be tied high. in non-ppa schemes, it functions as a user i/o during configuration, which means it is tri-stated. after ppa configuration, nrs is available as a user i/o pin and the state of this pin depends on the dual-purpose pin settings. rdynbsy i/o ppa output ready output. a high output indicates that the target device is ready to accept another data byte. a low output indicates that the target device is busy and not ready to receive another data byte. in ppa configuration schemes, this pin will drive out high after power-up, before configuration and after configuration before entering user-mode. in non-ppa schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, rdynbsy is available as a user i/o pin and the state of this pin depends on the dual-purpose pin settings. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 9 of 10) pin name user mode configuration scheme pin type description
altera corporation 13?103 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices ncs/cs i/o ppa input chip-select inputs. a low on ncs and a high on cs select the target device for configuration. the ncs and cs pins must be held active during configuration and initialization. during the ppa configuration mode, it is only required to use either the ncs or cs pin. therefore, if only one ch ip-select input is used, the other must be tied to the active state. for example, ncs can be tied to ground while cs is toggled to control configuration. in non-ppa schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, ncs and cs are available as user i/o pins and the state of these pins depends on the dual-purpose pin settings. runlu n/a if using remote system upgrade i/o if not remote system upgrade in fpp, ps or ppa input input that selects between remote update and local update. a logic high (1.5-v, 1.8-v, 2.5-v, 3.3-v) selects remote update and a logic low selects local update. when not using remote update or local update configuration modes, this pin is available as general-purpose user i/o pin. when using remote system upgrade in as more, the runlu pin is available as a general-purpose i/o pin. pgm[2..0] n/a if using remote system upgrade i/o if not using remote system upgrade in fpp, ps or ppa output these output pins select one of eight pages in the memory (either flash or enhanced configuration device) when using a remote system upgrade mode. when not using remote update or local update configuration modes, these pins are available as general-purpose user i/o pins. when using remote system upgrade in as more, the pgm[] pins are available as general-purpose i/o pins. table 13?22. dedicated configuration pins on the st ratix ii and stratix ii gx device (part 10 of 10) pin name user mode configuration scheme pin type description
13?104 altera corporation stratix ii gx device handbook, volume 2 october 2007 device configuration pins table 13?23 describes the optional configur ation pins. if these optional configuration pins are not enabled in the quartus ii software, they are available as general-purpose user i/o pins. therefore, during configuration, these pins function as user i/o pins and are tri-stated with weak pull-up resistors. table 13?23. optional configuration pins pin name user mode pi n type description clkusr n/a if option is on. i/o if option is off. input optional user-supplied cl ock input synchronizes the initialization of one or more devices. this pin is enabled by turning on the enable user-supplied start-up clock ( clkusr ) option in the quartus ii software. init_done n/a if option is on. i/o if option is off. output open-drain status pin can be used to indicate when the device has initialized and is in user mode. when nconfig is low and during the beginning of configuration, the init_done pin is tri-stated and pulled high due to an external 10-k pull-up resistor. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin will go low. when initialization is complete, the init_done pin will be released and pulled high and the device enters user mode. thus, the monitoring circuitry must be able to detect a low-to-high transition. this pin is enabled by turning on the enable init_done output option in the quartus ii software. dev_oe n/a if option is on. i/o if option is off. input optional pin that allows the user to override all tri-states on the device. when this pin is driven low, all i/o pins are tri-stated; when this pin is driven high, all i/o pins behave as programmed. this pin is enabled by turning on the enable device-wide output enable ( dev_oe ) option in the quartus ii software. dev_clrn n/a if option is on. i/o if option is off. input optional pin that allows you to override all clears on all device registers. when this pin is driven low, all registers are cleared; when th is pin is driven high, all registers behave as progra mmed. this pin is enabled by turning on the enable device-wide reset ( dev_clrn ) option in the quartus ii software.
altera corporation 13?105 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices table 13?24 describes the dedicated jtag pins. jtag pins must be kept stable before and during configuratio n to prevent accidental loading of jtag instructions. the tdi , tms, and trst have weak internal pull-up resistors (typically 25 k ) while tck has a weak internal pull-down resistor. if you plan to use the signaltap embedded logic array analyzer, you need to connect the jtag pins of the stratix ii or stratix ii gx device to a jtag header on your board. table 13?24. dedicated jtag pins (part 1 of 2) pin name user mode pin type description tdi n/a input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . the tdi pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . tdo n/a output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. the tdo pin is powered by v ccio in i/o bank 4. for recommendations on connecting a jtag chain with multiple voltages across the devices in the chain, refer to the ieee 1149.1 (jtag) boundary scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook or the ieee 1149.1 (jtag) boundary scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . if the jtag circuitry is not us ed, leave the tdo pin unconnected. tms n/a input input pin that provides the control signal to determine the transitions of the tap controller state machine. transiti ons within the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . the tms pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc .
13?106 altera corporation stratix ii gx device handbook, volume 2 october 2007 conclusion conclusion stratix ii and stratix ii gx devices can be configured in a number of different schemes to fit your system?s need. in additi on, configuration bitstream encryption, configuration data decompression, and remote system upgrade support supplement the stratix ii and stratix ii gx configuration solution. referenced documents this chapter references the following documents: an 122: using jam stapl for isp & icr via an embedded processor an 418: srunner: an embedded solution for serial conf iguration device programming byteblaster ii download cable user guide byteblastermv download cable user guide configuration devices for sram-b ased lut devices data sheet chapter in volume 2 of the configuration handbook . configuring mixed altera fpga chains in volume 2 of the configuration handbook dc & switching characteristics chapter in volume 1 of the stratix ii device handbook dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook enhanced configuration devices (e pc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook jam programming support - jtag technologies masterblaster serial /usb communications cable user guide tck n/a input the clock input to the bst circuitr y. some operations occur at the rising edge, while others occur at the falling edge. the tck pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting tck to gnd. trst n/a input active-low input to asynchronous ly reset the boundary-scan circuit. the trst pin is optional according to ieee std. 1149.1. the trst pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting the trst pin to gnd. table 13?24. dedicated jtag pins (part 2 of 2) pin name user mode pin type description
altera corporation 13?107 october 2007 stratix ii gx device handbook, volume 2 configuring stratix ii & stratix ii gx devices remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . usb-blaster download cable user guide serial configuration devices (epc s1, epcs4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . software settings in volume 2 of the configuration handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii device handbook stratix ii gx device handbook document revision history table 13?25 shows the revision hi story for this chapter. table 13?25. document revision history (part 1 of 2) date and document version changes made summary of changes october 2007, v4.5 updated handnote in ?configuration data decompression? section. ? updated notes in: table 13?3 table 13?10 table 13?12 table 13?15 table 13?18 ? updated tdo row for tables 13?19 and 13?24 . ? added the ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 12. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ?
13?108 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history may 2007, v4.4 updated ?power-on reset circuit? section updated ?vccsel pin? section updated ?configuration data decompression? section updated ?active serial configuration (serial configuration devices)? section updated ?output configuration pins? section ? added notes to ?fpp configuration using a max ii device as an external host? and ?passive parallel asynchronous configuration? section. ? updated table 13?5 updated table 13?6 updated table 13?8 updated table 13?11 ? removed table 7-7. ? added new ?output configuration pins? section. ? corrected typo in ?configuration devices? section. ? corrected conf_done in table 13?22. ? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 11. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ? table 13?25. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation 14?1 october 2007 14. remote system upgrades with stratix ii & stratix ii gx devices introduction system designers today face difficult challenges such as shortened design cycles, evolving standards, and system deployments in remote locations. stratix ? ii and stratix ii gx fpgas help overcome these challenges with their inherent re-programmability and dedicated circuitry to perform remote system upgrades. remote syst em upgrades help deliver feature enhancements and bug fixes without costly recalls, reduce time-to- market, and extend product life. stratix ii and stratix ii gx fpgas feature dedicated remote system upgrade circuitry. soft logic (either the nios ? embedded processor or user logic) implemented in a stratix ii or stratix ii gx device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. the dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. this dedicated remote system upgrade circuitry is unique to stratix, strati x ii, and stratix ii gx fpgas and helps to avoid system downtime. remote system upgrade is supported in all stratix ii and stratix ii gx configuration schemes: fast passive parallel (fpp), active serial (as), passive serial (ps), and passive parallel asynchronous (ppa). remote system upgrade can also be implemen ted in conjunction with advanced stratix ii and stratix ii gx features such as real-time decompression of configuration data and design securi ty using the advanced encryption standard (aes) for secure an d efficient field upgrades. this chapter describes the function ality and implementation of the dedicated remote system upgrade circuitry. it also defines several concepts related to remote syst em upgrade, including factory configuration, application configuration, remote update mode, local update mode, the user watchdog ti mer, and page mode operation. additionally, this chapter provides design guidelines for implementing remote system upgrade with the various supported configuration schemes. sii52008-4.5
14?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 functional description functional description the dedicated remote system upgrade circuitry in stratix ii and stratix ii gx fpgas manages remote configuration and provides error detection, recovery, and status informat ion. user logic or a nios processor implemented in the fpga logic arra y provides access to the remote configuration data source and an interface to the system?s configuration memory. stratix ii and stratix ii gx fpga?s remote system upgrade process involves the following steps: 1. a nios processor (or user logic) implemented in the fpga logic array receives new configuration data from a remote location. the connection to the remote source is a communication protocol such as the transmission control pro tocol/internet protocol (tcp/ip), peripheral component interconnect (pci), user datagram protocol (udp), universal asyn chronous receiver/tran smitter (uart), or a proprietary interface. 2. the nios processor (or user logic) stores this new configuration data in non-volatile configuratio n memory. the non-volatile configuration memory can be any standard flash memory used in conjunction with an intellig ent host (for example, a max ? device or microprocessor), the serial config uration device, or the enhanced configuration device. 3. the nios processor (or user logic) initiates a reconfiguration cycle with the new or updated configuration data. 4. the dedicated remote system upgr ade circuitry detects and recovers from any error(s) that might occur during or after the reconfiguration cycle, and provides error status information to the user design.
altera corporation 14?3 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices figure 14?1 shows the steps required for performing remote configuration updates. (the numbers in the figure below coincide with the steps above.) figure 14?1. functional diagram of stratix ii or stratix ii gx remote system upgrade stratix ii and stratix ii gx fpgas support remote system upgrade in the fpp, as, ps, and ppa configuration schemes. serial configuration devices use the as scheme to configure stratix ii and stratix ii gx fpgas. a max ii device (or microprocessor and flash configuration schemes) uses fpp, ps, or ppa sc hemes to configure stratix ii and stratix ii gx fpgas. enhanced configuration devices use the fpp or ps configuration schemes to configure stratix ii and stratix ii gx fpgas. 1 the jtag-based configuration scheme does not support remote system upgrade. development location memory stratix ii/stratix ii gx device confi g uration stratix ii/stratix ii gx device control module data data data confi g uration 1 2 3
14?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 functional description figure 14?2 shows the block diag rams for implementi ng remote system upgrade with the various stratix ii and stratix ii gx configuration schemes. figure 14?2. remote system upgrade block diagrams for various stratix ii and strati x ii gs configuration schemes 1 for the active serial configuration scheme, the remote system upgrade only supports single device configurations. you must set the mode select pins ( msel[3..0] ) and the runlu pin to select the configuration scheme and remote system upgrade mode best suited for your system. table 14?1 lists the pin settings for stratix ii and stratix ii gx fpgas. standard config uration mode refers to normal fpga configuration mode with no support for remote system upgrades, and the remote system upgrade circuitry is disabled. the following sections describe the local update and rem ote update remote system upgrade modes. stratix ii/stratix ii gx device processor flash memory stratix ii device enhanced configuration device enhanced confi g uration device max ii device & flash memory max ii device flash memory stratix ii/stratix ii gx device stratix ii/stratix ii gx device serial configuration device serial confi g uration device or user lo g ic nios processor or user lo g ic nios processor or user lo g ic nios processor external processor & flash memory
altera corporation 14?5 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices f for more information on standard configuration schemes supported in stratix ii and stratix ii gx fpgas, see the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook and the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . configuration image types and pages when using remote system upgrade, fpga configuration bitstreams are classified as factory configuration images or application configuration images. an image, also referred to as a configuration, is a design loaded into the fpga that performs certain user-defined functi ons. each fpga in your system requires one factor y image and one or more application table 14?1. stratix ii and st ratix ii gx remote system upgrade modes configuration schem e msel[3..0] runlu remote system upgrade mode fpp 0000 - standard 0100 (1) 0 local update 0100 (1) 1 remote update fpp with decompression and/or design security feature enabled (2) 1011 - standard 1100 (1) 0 local update 1100 (1) 1 remote update fast as (40 mhz) (3) 1000 - standard 1001 1 remote update as (20 mhz) (3) 1101 - standard 1110 1 remote update ps 0010 - standard 0110 (1) 0 local update 0110 (1) 1 remote update ppa 0001 - standard 0101 (1) 0 local update 0101 (1) 1 remote update notes to table 14?1 : (1) these schemes require that you drive the runlu pin to specify either remote update or local update mode. as schemes only support the remote update mode. (2) these modes are only supported when using a max ii de vice or microprocessor and flash for configuration. in these modes, the host system must output a dclk that is 4 x the data rate. (3) the epcs16 and epcs64 serial configuration devices su pport a dclk up to 40 mhz; other epcs devices support a dclk up to 20 mhz. see the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook for more information.
14?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 functional description images. the factory im age is a user-defined fall-back, or safe, configuration and is responsible for administering remote updates in conjunction with the dedicated circuitry. application images implement user-defined functionality in the target fpga. a remote system update involves storing a new application configuration image or updating an existing one via the remote communication interface. after an application configuration image is stored or updated remotely, the user design in the fpga initiates a reconfiguration cycle with the new image. any errors during or after this cycle are detected by the dedicated remote system upgrad e circuitry and cause the fpga to automatically revert to the factor y image. the factory image then performs error processing and re covery. while error processing functionality is limited to the factor y configuration, both factory and application configurations can download and store remote updates and initiate system reconfiguration. stratix ii and stratix ii gx fpgas select between the different configuration images stored in the system configuration memory using the page address pins or start address registers. a page is a section of the configuration memory space that co ntains one configuration image for each fpga in the system . one page stores one system configuration, regardless of the number of fpgas in the system. page address pins select the configuration image within an enhanced configuration device or flash memory (max ii device or microprocessor setup). page start address regist ers are used when stratix ii and stratix ii gx fpgas are configured in as mode with serial configuration devices. figure 14?3 illustrates page mode operation in stratix ii and stratix ii gx fpgas.
altera corporation 14?7 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices figure 14?3. page mode operation in st ratix ii & stratix ii gx fpgas stratix ii and stratix ii gx devices drive out three page address pins, pgm[2..0] , to the max ii device or microprocessor or enhanced configuration device. these page pins select between eight configuration pages. page zero ( pgm[2..0] = 000 ) must contain the factory configuration, and the other seven pa ges are application configurations. the pgm[] pins are pointers to the start address and length of each page, and the max ii device, microprocess or, and enhanced configuration devices perform this translation. 1 when implementing remote system upgrade with an intelligent-host-based configuration, your max ii device or microprocessor should emulate the page mode feature supported by the enhanced configuration device, which translates pgm pointers to a memory address in the configuration memory. your max ii device or microprocessor must provide a similar translation feature. f for more information about the enha nced configuration device page mode feature, refer to the dyna mic configuration (page mode) implementation section of the enhanced configuration devices (epc4, epc8 & epc16) data sheet chapter in volume 2 of the configuration handbook . when implementing remote system upgrade with as configuration, a dedicated 7-bit page start address register inside stratix ii and stratix ii gx fpgas determines the start addresses for configuration pages within the serial configuration device. the pgm[6..0] registers form bits [22..16] of the 24-bit start address while the other 17 bits are confi g uration memory sof n pa g e n sof 0 pa g e 0 stratix ii/ stratix ii gx device data[ ] p age s e l ect pin s o r s tart a ddress r eg i ster pgm[ ] c on f i g u rat ion data
14?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 remote system upgrade modes set to zero: stadd[23..0] = {1'b0, pgm[6..0], 16'b0} . during as configuration, stratix ii and strati x ii gx fpgas use this 24-bit page start address to obtain configuration data from the serial configuration devices. remote system upgrade modes remote system upgrade has two mode s of operation: remote update mode and local update mode. the remote and local update modes allow you to determine the functionality of your system upon power up and offer different features. the runlu input pin selects between the remote update (logic high) and local update (logic low) modes. overview in remote update mode, stratix ii and stratix ii gx fpgas load the factory configuration image upon po wer up. the user-defined factory configuration should determine which application configuration is to be loaded and trigger a reconfiguration cycle. remote update mode allows up to eight configuration images (o ne factory plus seven application images) when used with the max i i device or microprocessor and flash-based configuration or an enhanced configuration device. when used with serial configuration devices, the remote update mode allows an application co nfiguration to start at any flash sector boundary. this translates to a maximum of 128 pages in the epcs64 and 32 pages in the epcs16 device, where the minimum size of each page is 512 kbits. additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration. local update mode is a simplified version of the remote update mode. in this mode, stratix ii and stratix ii gx fpgas directly load the application configuration, bypassing the factory conf iguration. this mode is useful if your system is required to boot into user mode with minimal startup time. it is also useful du ring system prototyping, as it allows you to verify functionality of the appl ication configuration. in local update mode, a maximum of two configuration images or pages is supported: one factory configur ation, located at page address pgm[2..0] = 000 , and one application config uration, located at page address pgm[2..0] = 001 . because the page address of the application configuration is fixed, the local update mode does not require the factory configuration image to determine which application is to be loaded. if any errors are encountered while load ing the application configuration, stratix ii and stratix ii gx fpgas revert to the factory configuration. the user watchdog timer feature is not supported in this mode.
altera corporation 14?9 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices 1 also, local update mode does not support as configuration with the serial configuration devices because these devices don?t support a dynamic pointer to pa ge 001 start address location. table 14?2 details the differences between remote and local update modes. remote update mode when stratix ii and stratix ii gx fp gas are first powered up in remote update mode, it loads the factory configuration located at page zero (page address pins pgm[2..0] = "000" ; page registers pgm[6..0] = "0000000" ). you should always store the factory configuration image for your system at page address zero. a factory configuration image is a bitstream for the fpga(s) in your sy stem that is pr ogrammed during production and is the fall-back image when errors occur. this image is stored in non-volatile memory and is never updated or modified using table 14?2. differences between remote and local update modes features remote update mode local update mode runlu input pin setting 1 0 page selection upon power up pgm[2..0] = 000 (factory) pgm[2..0] = 001 (application) supported configurations max ii device or microprocessor-based configuration, serial configuration, and enhanced configuration devices (fpp, ps, as, ppa) max ii device or microprocessor-based configuration and enhanced configuration devices (fpp, ps, ppa) number of pages supported eight pages for external host or controller based configuration; up to 128 pages (512 kbits/page) for serial configuration device two pages user watchdog timer available disabled remote system upgrade control and status register read/write access allowed in factory configuration. read access in application configuration only status register read access allowed in local update mode (factory and application configurations). write access to control register is disabled
14?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 remote system upgrade modes remote access. this corresponds to pgm[2..0] = 000 of the enhanced configuration device or standard flash memory, and start address location 0x000000 in the seri al configuration device. the factory image is user design ed and contains soft logic to: process any errors based on status information from the dedicated remote system upgrade circuitry communicate with the remote host and receive new application configurations, and store this new configuration data in the local non-volatile memory device determine which application configuration is to be loaded into the fpga enable or disable the user watchdog timer and load its time-out value (optional) instruct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle figure 14?4 shows the transitions betwee n the factory and application configurations in remote update mode. figure 14?4. transitions between confi gurations in remote update mode set control register and reconfigure set control register and reconfigure reload a different application reload a different application application n configuration application 1 configuration factory configuration (page 0) configuration error configuration error power up configuration error
altera corporation 14?11 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices after power up or a configuration error, the factory configuration logic should write the remote system upgr ade control register to specify the page address of the application conf iguration to be loaded. the factory configuration should also specify whether or not to enable the user watchdog timer for the application configuration and, if enabled, specify the timer setting. the user watchdog timer ensures that the application configuration is valid and functional. after confirmi ng the system is healthy, the user-designed application configuration should reset the timer periodically during user-mode operatio n of an applicatio n configuration. this timer reset logic should be a user-designed hardware and/or software health monitoring signal that indicates error-free system operation. if the user application configuration detects a functional problem or if the system hangs, the timer is not reset in time and the dedicated circuitry update s the remote system upgrade status register, triggering the device to load the factory configuration. the user watchdog timer is automatically di sabled for factory configurations. 1 only valid application configurations designed for remote update mode include the logic to reset the timer in user mode. 1 for more information about the user watchdog timer, see ?user watchdog timer? on page 14?20 . if there is an error while loading the application configuration, the remote system upgrade status register is wri tten by the stratix ii or stratix ii gx fpga?s dedicated remote system upgrade circuitry, specifying the cause of the reconfiguration. actions that cause the remote system upgrade status register to be written are: nstatus driven low externally internal crc error user watchdog timer time out a configuration reset (logic array nconfig signal or external nconfig pin assertion) stratix ii and stratix ii gx fpgas automatically load the factory configuration located at page address zero. this user-designed factory configuration should read the remote system upgrade status register to determine the reason for reconfiguration. the factory configuration should then take appropriate error re covery steps and write to the remote system upgrade control register to determine the next application configuration to be loaded.
14?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 remote system upgrade modes when stratix ii or stratix ii gx devices successfully load the application configuration, they enter into user mode. in user mode, the soft logic (nios processor or state machine and the remote communication interface) assists the stratix ii or stra tix ii gx device in determining when a remote system update is arrivi ng. when a remote system update arrives, the soft logic receives th e incoming data, writes it to the configuration memory device, and triggers the device to load the factory configuration. the factory configuration reads the remote system upgrade status register, determines the valid application configuration to load, writes the remote system upgrad e control register accordingly, and initiates system reconfiguration. stratix ii and stratix ii gx fpgas suppo rt the remote update mode in the as, fpp, ps, and ppa configuration schemes. in the fpp, ps, and ppa schemes, the max ii device, microprocessor, or enhanced configuration device should sample the pgm[2..0] outputs from the stratix ii or stratix ii gx fpga and transmit the appropriate configuration image. in the as scheme, the stratix ii or stratix ii gx device uses the page addresses to read configuration data out of the serial configuration device. local update mode local update mode is a simplified version of the remote update mode. this feature allows systems to lo ad an application configuration immediately upon power up without loading the factory configuration first. local update mode does not require the factory configuration to determine which application configuration to load, because only one application configuration is allowed (at page address one ( pgm [2..0] = 001 ). you can update this application configuration remotely. if an error occurs while loading the application configuration, the factory configuration is automatically loaded. upon power up or nconfig assertion, the dedicated remote system upgrade circuitry dr ives out ?001? on the pgm[] pins selecting the application configuration stored in page one. if the device encounters any errors during the configuration cycle, the remote system upgrade circuitry retries configuration by driving pgm[2..0] to zero ( pgm[2..0] = 000 ) to select the factory configuration image. the error conditions that trigger a return to the factory configuration are: an internal crc error an external error signal ( nstatus detected low)
altera corporation 14?13 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices when the remote system upgrade circuitry detects an external configuration reset ( nconfig pulsed low) or internal configuration reset (logic array nconfig assertion), the device attempts to reload the application configuration from page one. figure 14?5 shows the transitions between configurations in local update mode. figure 14?5. transitions between confi gurations in local update mode stratix ii and stratix ii gx fpgas suppo rt local update mode in the fpp, ps, and ppa configuration schemes. in these schemes, the max ii device, microprocessor, or enhanced configuration device should sample the pgm[2..0] outputs from the stratix ii or stratix ii gx fpga and transmit the appropriate configuration image. local update mode is not supported with the as conf iguration scheme, (or serial configuration device), because the stratix ii or stratix ii gx fpga cannot determine the start address of the application configuration page upon power up. while the factory configuration is always located at memory address 0x000000, the applicat ion configuration can be located at any other sector boundary within the serial configuration device. the start address depends on the size of the factory configuration and is user selectable. hence, only remote update mode is supported in the as configuration scheme. application confi g uration (pa g e 001) core or external nconfig assertion confi g uration error core or external nconfig assertion pow er up o r n c onfig assert ion factory confi g uration (pa g e 000) confi g uration error
14?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 dedicated remote system upgrade circuitry 1 local update mode is not supported in the as configuration scheme (with a serial configuration device). local update mode supports read ac cess to the remote system upgrade status register. the factory configurat ion image can use this error status information to determine if a new a pplication configuration must be downloaded from the remote source . after a remote update, the user design should assert the logic array configuration reset ( nconfig ) signal to load the new application configuration. the device does not support write ac cess to the remote system upgrade control register in local update mode. write access is not required because this mode only supports one applicat ion configuration (eliminating the need to write in a page address) and does not support the user watchdog timer (eliminating the need to enable or disable the timer or specify its time-out value). 1 the user watchdog timer is disabled in local update mode. 1 write access to the remote system upgrade control register is disabled in local update mode. however, the device supports read access to obtain error status information. dedicated remote system upgrade circuitry this section explains the implementation of the stratix ii or stratix ii gx remote system upgrade dedicated circuitry. the remote system upgrade circuitry is implemented in hard logic. this dedicated circuitry interfaces to the user-defined factory applicatio n configurations implemented in the fpga logic array to provide the complete remote configuration solution. the remote system upgrade circuitry contains the remote system upgrade registers, a watchdog timer, and a state machine that controls those components. figure 14?6 shows the remote system upgrade block?s data path.
altera corporation 14?15 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices figure 14?6. remote system upgrade circuit data path remote system upgrade registers the remote system upgrade block contai ns a series of registers that store the page addresses, watchdog timer settings, and stat us information. these registers are detailed in table 14?3 . logic array shift register status re g ister (sr) bit [4..0] control re g ister bit [20..0] din capture dout bit [4..0] lo g ic clkout ru_shiftnld ru_captnupdt ru_clk ru_din ru_nconfig ru_nrstimer user watchdo g timer ru_dout capture clkin update lo g ic capture din bit [20..0] dout update update re g ister bit [20..0] timeout rsu state machine internal oscillator table 14?3. remote system upgrade registers (part 1 of 2) register description shift register this register is ac cessible by the logic array and allows the update, status, and control registers to be written and sampled by user logi c. write access is enabled in remote update mode for factory configurations to allow writ es to the update register. write access is disabled in local update mode and for all applicat ion configurations in remote update mode. control register this register cont ains the current page address, the user watchdog timer settings, and one bit specifying whether the current configuration is a factory configuration or an application configuration. during a read operation in an appl ication configuration, this register is read into the shift register. when a reconfiguration cycle is initiated, the contents of the update register are written into the control register.
14?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 dedicated remote system upgrade circuitry the remote system upgrade control and status registers are clocked by the 10-mhz internal oscillator (the same oscillator that controls the user watchdog timer). however, the remote system upgrade shift and update registers are clocked by the user clock input ( ru_clk ). remote system upgr ade control register the remote system upgrade control register stores the application configuration page address and user watchdog timer settings. the control register functionality depe nds on the remote system upgrade mode selection. in remote update mode, the control register page address bits are set to all zeros ( 7'b0 = 0000_000 ) at power up in order to load the factory configuration. however, in local update mode the control register page address bits power up as ( 7'b1 = 0000_001 ) in order to select the application configuration. additionally, the control register cannot be updated in local update mode, whereas a factory configuration in remote update mode has write access to this register. the control register bit positions are shown in figure 14?7 and defined in table 14?4 . in the figure, the numbers show the bit position of a setting within a register. for example, bit number 8 is the enable bit for the watchdog timer. figure 14?7. remote system upgrade control register update register this register contains data similar to that in the control register. however, it can only be updated by the factory configuration by shifting data into the shift register and issuing an update operation. when a reconfiguration cycle is triggered by the factory configuration, the control register is updated with the contents of the update register. during a read in a factory configuration, this register is read into the shift register. status register this register is written to by the remo te system upgrade circuitry on every reconfiguration to record the cause of the reconfiguration. this in formation is used by the factory configuration to determine the appropriate action following a re configuration. during a capture cycle, this register is read into the shift register. table 14?3. remote system upgrade registers (part 2 of 2) register description wd_timer[11..0] wd_en pgm[6..3] pgm[2..0] anf 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
altera corporation 14?17 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices the application-not-factory ( anf ) bit indicates whether the current configuration loaded in the stratix ii or stratix ii gx device is the factory configuration or an applic ation configuration. this bit is set high at power up in local update mode, and is set low by the remote system upgrade circuitry when an error conditio n causes a fall-back to factory configuration. when the anf bit is high, the control register access is limited to read operations. when the anf bit is low, the register allows write operations and disa bles the watchdog timer. 1 in remote update mode, factory configuration design should set this bit high (1'b1) when updati ng the contents of the update register with applic ation page address and watchdog timer settings. table 14?4. remote system upgrade control register contents control register bit remote system upgrade mode value definition anf (1) local update remote update 1?b1 1'b0 application not factory pgm[2..0] local update remote update (fpp, ps, ppa) 3'b001 3'b000 page mode select remote update (as) 3'b000 as configuration start address ( stadd [ 18..16 ]) pgm[6..3] local update remote update (fpp, ps, ppa) 4'b0000 4'b0000 not used remote update (as) 4'b0000 as configuration start address ( stadd[22..19] ) wd_en remote update 1'b0 user watchdog timer enable bit wd_timer[11..0] remote update 12'b000000000000 user watchdog time-out value (most significant 12 bits of 29-bit count value: { wd_timer[11..0] , 17'b0} ) note to table 14?4 : (1) in remote update mode, the remote co nfiguration block does not update the anf bit automatically (you can update it manually). in local update mo de, the remote configuration updates the anf bit with 0 in the factory page and 1 in the application page.
14?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 dedicated remote system upgrade circuitry remote system upgrade status register the remote system upgrade status re gister specifies the reconfiguration trigger condition. the various trig ger and error conditions include: crc (cyclic redundancy check) error during application configuration nstatus assertion by an external device due to an error fpga logic array triggered a reconfiguration cycle, possibly after downloading a new applicat ion configuration image external configuration reset ( nconfig ) assertion user watchdog timer time out figure 14?8 and table 14?5 specify the contents of the status register. the numbers in the figure show the bit positions within a 5-bit register. figure 14?8. remote system upgrade status register table 14?5. remote system upgr ade status register contents status register bit definition por reset value crc (from configuration) crc error caused reconfiguration 1 bit '0' nstatus nstatus caused reconfiguration 1 bit '0' core (1) core_nconfig device logic array caused reconfiguration 1 bit '0' nconfig nconfig caused reconfiguration 1 bit '0' wd watchdog timer caused reconfiguration 1 bit '0' note to table 14?5 : (1) logic array reconfiguration forces the system to load the application configuration data into the stratix ii or stratix ii gx device. this occurs after the factory configuration specifies the appropriate application configuration page address by updating the update register. wd 4 crc 0 nconfig 3 nstatus 1 core_nconfig 2
altera corporation 14?19 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices remote system upgrade state machine the remote system upgrade control and update registers have identical bit definitions, but serve different roles (see table 14?3 on page 14?15 ). while both registers can only be upda ted when the fpga is loaded with a factory configuration image, the update register writes are controlled by the user logic, and the control register writes are controlled by the remote system upgrade state machine. in factory configurations, the user logic should send the anf bit (set high), the page address, and watchdog timer settings for the next application configuration bit to the update register. when the logic array configuration reset ( ru_nconfig ) goes high, the remote system upgrade state machine updates the control register with the contents of the update register and initiates system reconfiguration from the new application page. in the event of an error or reconfiguration trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (page zero or page one, based on mode and error condition) by setting the control register accordingly. table 14?6 lists the contents of the control register after such an event occurs for all possible error or trigger conditions. the remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition but before the factory configuration is loaded. table 14?6. control register contents after an error or reconfiguration trigger condition reconfiguration error/trigger control register setting remote update local update nconfig reset all bits are 0 pgm[6..0] = 7'b0000001 anf = 1 all other bits are 0 nstatus error all bits are 0 all bits are 0 core triggered reconfiguration update register pgm[6..0] = 7'b0000001 anf = 1 all other bits are 0 crc error all bits are 0 all bits are 0 wd time out all bits are 0 all bits are 0
14?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 dedicated remote system upgrade circuitry read operations during factory configuration access the contents of the update register. this feature is used by the user logic to verify that the page address and watchdog timer sett ings were written correctly. read operations in application configurations access the contents of the control register. this information is used by the user logic in the application configuration. user watchdog timer the user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. the system uses the timer to detect functional errors after an application configuration is successfully loaded into the fpga. the user watchdog timer is a counter that counts down from the initial value loaded into the remote system upgrade control register by the factory configuration. the counter is 29-bits-wide and has a maximum count value of 2 29 . when specifying the user watchdog timer value, specify only the most significant 12 bits. the granularity of the timer setting is 2 15 cycles. the cycle time is ba sed on the frequency of the 10-mhz internal oscillator. table 14?7 specifies the operating range of the 10-mhz internal oscillator. the user watchdog timer begins counting once the application configuration enters fpga user mode. this timer must be periodically reloaded or reset by the application configuration before the timer expires by asserting ru_nrstimer . if the application configuration does not reload the user watchdog timer before the count expires, a time-out signal is generated by the remote system upgrade dedicated circuitry. the time-out signal tells the remote syst em upgrade circuitry to set the user watchdog timer status bit ( wd ) in the remote system upgrade status register and reconfigures the device by loading the factory configuration. the user watchdog timer is not enable d during the configuration cycle of the fpga. errors during configuration are detected by the crc engine. also, the timer is disabled for factor y configurations. functional errors should not exist in the factory configuration since it is stored and validated during production an d is never updated remotely. table 14?7. 10-mhz internal oscillator specifications minimum typical maximum units 56.510mhz
altera corporation 14?21 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices 1 the user watchdog timer is disa bled in factory configurations and during the configuration cycle of the application configuration. it is enabled af ter the application configuration enters user mode. interface signals between remote system upgrade circuitry and fpga logic array the dedicated remote system upgrade circuitry drives (or receives) seven signals to (or from) the fpga logic arra y. the fpga logic array uses these signals to read and write the remote system upgrade control, status, and update registers using the remote system upgrade shift register. table 14?8 lists each of these seven signals and describes their functionality. except for ru_nrstimer and ru_captnupdt , the logic array signals are enabled for both remote and local update modes and for both factory and application configurations. ru_nrstimer is only valid for application configurations in remote update mode , since local update configurations and factory configurations have the user watchdog timer disabled. when ru_captnupdt is low, the device can write to the update register only for factory configurations in remote update mode, since this is the only case where the update register is writ ten to by the user logic. when the ru_nconfig signal goes high, the contents of the update register are written into the control register for controlling the next configuration cycle. table 14?8. interface signals between remote system upgrade circuitry and fpga logic array (part 1 of 3) signal name signal direction description ru_nrstimer input to remote system upgrade block (driven by fpga logic array) request from the application conf iguration to reset the user watchdog timer with its initial coun t. a falling edge of this signal triggers a reset of the user watchdog timer. ru_nconfig input to remote system upgrade block (driven by fpga logic array) when driven low, this signal triggers the device to reconfigure. if asserted by the factory configuration in remote update mode, the application configuration specified in the remote update control register is loaded. if requested by the application configuration in remote update mode, the factory configuration is loaded. in the local updated mode, the application configuration is loaded whenever this signal is asserted.
14?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 dedicated remote system upgrade circuitry ru_clk input to remote system upgrade block (driven by fpga logic array) clocks the remote system upgrade shift register and update register so that the contents of the status, control, and update registers can be read, and so that the contents of the update register can be loaded. the shift register latches data on the rising edge of this clock signal. ru_shiftnld input to remote system upgrade block (driven by fpga logic array) this pin determines if the shi ft register contents are shifted over during the next clock edge or loaded in/out. when this signal is driven high (1'b1), the remote system upgrade shift register shifts data left on each rising edge of ru_clk . when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven low (1'b0), the remote system upgrade update register is updated with the contents of the shift register on the rising edge of ru_clk . when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven high (1'b1), the remote system upgrade shift register captures t he status register and either the control or update register (depending on whether the current configuration is application or factory, respectively) on the rising edge of ru_clk . ru_captnupdt input to remote system upgrade block (driven by fpga logic array) this pin determines if the cont ents of the shift register are captured or updated on the next clock edge. when the ru_shiftnld signal is driven high (1'b1), this input signal has no function. when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven high (1'b1), the remote system upgrade shift register captures t he status register and either the control or update register (depending on whether the current configuration is application or factory, respectively) on the rising edge of ru_clk . when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven low (1'b0), the remote system upgrade update register is updated with the contents of the shift register on the rising edge of ru_clk . in local update mode, a low input on ru_captnupdt has no function, because the update r egister cannot be updated in this mode. table 14?8. interface signals between remote system upgrade circuitry and fpga logic array (part 2 of 3) signal name signal direction description
altera corporation 14?23 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices remote system upgrade pin descriptions table 14?9 describes the dedicated remote system upgrade configuration pins. f for descriptions of all the configuration pins, refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook and the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . ru_din input to remote system upgrade block (driven by fpga logic array) data to be written to the remote system upgrade shift register on the rising edge of ru_clk . to load data into the shift register, ru_shiftnld must be asserted. ru_dout output from remote system upgrade block (driven to fpga logic array) output data from the remote system upgrade shift register to be read by logic array logic. ne w data arrives on each rising edge of ru_clk . table 14?8. interface signals between remote system upgrade circuitry and fpga logic array (part 3 of 3) signal name signal direction description
14?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 quartus ii software support quartus ii software support implementation in your design re quires an remote system upgrade interface between the fpga logic array and remote system upgrade circuitry. you also need to generate configuration files for production and remote programming of the syst em configuration memory. the quartus ? ii software provides these features. the two implementation options, altremote_update megafunction and remote system upgrade atom, are for the interface between the remote system upgrade circuitry and the fpga logic array interface. altremote_update megafunction the altremote_update megafunction provides a memory-like interface to the remote system upgr ade circuitry and handles the shift register read/write protocol in fpga logic. this implementation is suitable for designs that implement the factory configuration functions using a nios processor in the fpga. table 14?9. stratix ii and st ratix ii gx remote system upgrade pins pin name user mode configuration scheme pin type description runlu n/a if using remote system upgrade in fpp, ps, as, or ppa modes. i/o if not using these modes. remote configuration in fpp, ps, or ppa input input that selects between remote update and local update. a logic high (1.5-v, 1.8- v, 2.5-v, 3.3-v) selects remote update, and a logic low selects local update. when not using remote update or local update configuration modes, this pin is available as a general-purpose user i/o pin. when using remote configuration in as mode, set the runlu pin to high because as does not support local update. pgm[2..0] n/a if using remote system upgrade in fpp, ps, or ppa modes. i/o if not using these modes. remote configuration in fpp, ps or ppa output these output pins select one of eight pages in the memory (either flash or enhanced configuration device) when using remote update mode. when not using remote update or local update configuration modes, these pins are available as general-purpose user i/o pins.
altera corporation 14?25 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices tables 14?10 and 14?11 describe the input and output ports available on the altremote_update megafunction. table 14?12 shows the param[2..0] bit settings. table 14?10. input ports of the altr emote_update megafunct ion (part 1 of 2) port name require d source description clock y logic array clock input to the altremote_update block. all operations are performed with respects to the rising edge of this clock. reset y logic array asynchronous reset, which is used to initialize the remote update block. to ensure proper operation, the remote update block must be reset before first accessing the remote update block. this signal is not affected by the bu sy signal and will reset the remote update block even if busy is logic high. this means that if the reset signal is driven logic high during writing of a parameter, the parameter will not be properly written to the remote update block. reconfig y logic array when driven logic high, reconfigurat ion of the device is initiated using the current parameter settings in the remote update block. if busy is asserted, this signal is ignored. this is to ensure all parameters are completely written before reconfiguration begins. reset_timer n logic array this signal is required if you ar e using the watchdog timer feature. a logic high resets the internal watchdog timer. this signal is not affected by the busy signal and can reset the timer even when the remote update block is busy. if this port is left connected, the default value is 0. read_param n logic array once read_param is sampled as a logic high, the busy signal is asserted. while the parameter is being read, the busy signal remains asserted, and inputs on param[] are ignored. once the busy signal is deactivated, the next parameter can be read. if this port is left unconnected, the default value is 0. write_param n logic array this signal is required if you intend on writing parameters to the remote update block. when driven logic high, the parameter specified on the param[] port should be written to the remote update block with the value on data_in[] . the number of valid bits on data_in[] is dependent on the parameter type. this signal is sampled on the rising edge of clock and should only be asserted for one clock cycle to prevent the parameter from being re-read on subsequent clock cycles. once write_param is sampled as a logic high, the busy signal is asserted. while the parameter is being written, the busy signal remains asserted, and inputs on param[] and data_in[] are ignored. once the busy signal is deactivated, the next parameter can be written. this signal is only valid when the current_configuration parameter is factory since parameters cannot be written in application configurations. if th is port is left unconnected, the default value is 0.
14?26 altera corporation stratix ii gx device handbook, volume 2 october 2007 quartus ii software support param[2..0] n logic array 3-bit bus that selects which parameter should be read or written. if this port is left unconnected, the default value is 0. data_in[11..0] n logic array this signal is required if you intend on writing parameters to the remote update block 12-bit bus used when writing parameters, which specifies the parameter value. the parameter value is requested using the param[] input and by driving the write_param signal logic high, at wh ich point the busy signal goes logic high and the value of t he parameter is captured from this bus. for some parameters, not all 12 bits are used, in which case only the least significant bi ts are used. this port is ignored if the current_configuration parameter is set to an application configuration since writing of parameters is only allowed in the factory configuration. if this port is left unconnected, the default value is 0. note to table 14?10 : (1) logic array source means that you can drive the port from internal logic or any general-purpose i/o pin. table 14?11. output ports of the altr emote_update megafunction (part 1 of 2) port name required destination description busy y logic array when this signal is a logi c high, the remote update block is busy either reading or writing a parameter. when the remote update block is busy, it ignores its data_in[] , param[] , and reconfig inputs. this signal goes high when read_param or write_param is asserted and remains asserted until the operation is complete. pgm_out[2..0] y pgm[2..0] pins 3-bit bus that specifies the page pointer of the configuration data to be loaded when the device is reconfigured. this port must be connected to the pgm[] output pins, which should be connected to the external configuration device. table 14?10. input ports of the altr emote_update megafunct ion (part 2 of 2) port name require d source description
altera corporation 14?27 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices data_out[11..0] n logic array 12-bit bus used when readi ng parameters, which reads out the parameter value. the parameter value is requested using the param[] input and by driving the read_param signal logic high, at which point the busy signal goes logic high. when the busy signal goes low, the value of the parameter is driven out on this bus. the data_out[] port is only valid after a read_param has been issued and once the busy signal is deasserted. at any other time, its output values are invalid. for example, even though the data_out[] port may toggle during a writing of a parameter, these values are not a valid representation of what was actually written to the remote update block. for some parameters, not all 12 bits are used, in which case only the least significant bits are used. note to table 14?11 : (1) logic array destination means that you can drive the port to internal logic or any general-purpose i/o pin. table 14?12. parameter settings for the altremote_update megafunction (part 1 of 2) selected parameter param[2..0] bit setting width of parameter value por reset value description status register contents 000 5 5 bit '0 specifies the reason for re-configuration, which could be caused by a crc error during configuration, nstatus being pulled low due to an error, the device core caused an error, nconfig pulled low, or the watchdog timer timed-out. this parameter can only be read. watchdog timeout value 010 12 12 bits '0 user watchdog timer time-out value. writing of this parameter is only allowed when in the factory configuration. watchdog enable 011 1 1 bit '0 user watchdog timer enable. writing of this parameter is only allowed when in the factory configuration page select 100 3 (fpp, ps, ppa) 3 bit '001' - local configuration page mode selection. writing of this parameter is only allowed when in the factory configuration. 3 bit '000' - remote configuration 7 (as) 7 bit '0000000' - remote configuration table 14?11. output ports of the altr emote_update megafunction (part 2 of 2) port name required destination description
14?28 altera corporation stratix ii gx device handbook, volume 2 october 2007 system design guidelines remote system upgrade atom the remote system upgrade atom is a wysiwyg atom or primitive that can be instantiated in your design. the primitive is used to access the remote system upgrade shift register , logic array reset, and watchdog timer reset signals. the ports on this primitive are the same as those listed in table 14?8 . this implementation is suitable for designs that implement the factory configuration functions using state machines (without a processor). system design guidelines the following general guidelines are applicable when implementing remote system upgrade in stratix ii and stratix ii gx fpgas. guidelines for specific configuration schemes are also discussed in this section. after downloading a new applicatio n configuration, the soft logic implemented in the fpga can validate the integrity of the data received over the remote communica tion interface. this optional step helps avoid configuration attempts with bad or incomplete configuration data. however, in th e event that bad or incomplete configuration data is sent to the fpga, it detects the data corruption using the crc signature attached to each configuration frame. the auto-reconfigure on configurat ion error option bit is ignored when remote system upgrade is enab led in your system. this option is always enabled in remote conf iguration designs, allowing your system to return to the safe factor y configuration in the event of an application configuration error or user watchdog timer time out. current configuration (anf) 101 1 1 bit '0' - factory specifies whether the current configuration is factory or and application configuration. this parameter can only be read. 1 bit '1' - application illegal values 001 110 111 table 14?12. parameter settings for the altremote_update megafunction (part 2 of 2) selected parameter param[2..0] bit setting width of parameter value por reset value description
altera corporation 14?29 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices remote system upgrade with serial configuration devices remote system upgrade support in the as configuration scheme is similar to support in other schemes, with the following exceptions: the remote system upgrade block provides the as configuration controller inside the stratix ii or stra tix ii gx fpga with a 7-bit page start address ( pgm[6..0] ) instead of driving the 3-bit page mode pins ( pgm[2..0] ) used in fpp, ps, and ppa configuration schemes. this 7-bit address forms the 24- bit configuration start address ( stadd[23..0] ). table 14?13 illustrates the start address generation using the pa ge address registers. the configuration start address for factory configuration is always set to 24'b0. pgm[2..0] pins on stratix ii devices are not used in as configuration schemes and can not be used as regular i/o pins. the nios asmi peripheral can be used to update configuration data within the serial configuration device. remote system upgrade with a max ii device or microprocessor and flash device this setup requires the max ii device or microprocessor to support page addressing. max ii or microprocess or devices implementing remote system upgrade should emulate the e nhanced configurat ion device page mode feature. the pgm[2..0] output pins from the stratix ii or stratix ii gx device must be sampled to determine which configuration image is to be loaded into the fpga. if the fpga does not release conf_done after all data has been sent, the max ii microprocessor should reset th e fpga back to the factory image by pulsing its nstatus pin low. table 14?13. as configuration start address generation serial configuration device serial configuration device density (mb) add[23] pgm[6..0] (add[22..16]) add[15..0] epcs64 64 0 msb[6..0] all 0s epcs16 16 0 00, msb[4..0] all 0s epcs4 4 0 0000, msb[2..0] all 0s
14?30 altera corporation stratix ii gx device handbook, volume 2 october 2007 system design guidelines the max ii device or microprocessor and flash configuration can use fpp, ps, or ppa. decompression and design security features are supported in the fpp (requires 4 dclk) and ps modes only. figure 14?9 shows a system block diagram for remote system upgrade with the max ii device or microprocessor and flash. figure 14?9. system block diagram for remote system upgrade with max ii device or microprocessor and flash device notes to figure 14?9 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for the device. (2) connect runlu to gnd or v cc to select between remote and local update modes. (3) connect msel[3..0] to 0100 to enable remote update remote system upgrade mode. remote system upgrade with enhanced configuration devices enhanced configuration devices support remote system upgrade with fpp or ps configuration scheme s. the stratix ii or stratix ii gx decompression and design security features are only supported in the ps mode. the enhanced configuration device?s decompression feature is supported in both ps and fpp schemes. in remote update mode, neither the factory configuration nor the application configurations should alter the enhanced configuration device?s option bits or the page 000 factory configuration data. this ensures that an error during remote update can always be resolved by reverting to the factory configuration located at page 000. external host (max ii device or microprocessor) conf_done nstatus nce data[7..0] nconfig stratix ii/stratix ii gx device memory addr data[7..0] gnd msel[3..0] v cc (1) v cc (1) dclk nceo n.c. 10 k 10 k pgm[2..0] runlu (2) (3)
altera corporation 14?31 october 2007 stratix ii gx device handbook, volume 2 remote system upgrades with stratix ii & stratix ii gx devices the enhanced configuration device features an error checking mechanism to detect instances when the fpga fails to detect the configuration preamble. in th ese instances, the enhanced configuration device pulses the nstatus signal low, and the remote system upgrade circuitry attempts to load the factory configuration. figure 14?10 shows a system block diagram for remote system upgrade with enhanced configuration devices. figure 14?10. system block diagram fo r remote system upgrade with enhanced configuration devices notes to figure 14?10 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for the device. (2) connect runlu to gnd or v cc to select between remote and local update modes. (3) connect msel[3..0] to 0100 to enable remote update remote system upgrade mode. conclusion stratix ii and stratix ii gx devices offer remote system upgrade capability, where you can upgrade a system in real-time through any network. remote system upgrade he lps to deliver feature enhancements and bug fixes without costly recalls, reduces time to market, and extends product life cycles. the dedicated re mote system upgrade circuitry in stratix ii and stratix ii gx devices pr ovides error detection, recovery, and status information to ensure reliable reconfiguration. referenced documents this chapter references the following documents: configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook stratix ii/stratix ii gx device enhanced confi g uration device dclk data[7..0] oe ncs ninit_conf (2) dclk data[7..0] nstatus conf_done nconfig v cc v cc gnd (1) (1) nce (3) (3) nceo n.c. runlu msel[3..0] 10 k 10 k (3) (3) pgm[2..0] pgm[2..0] external flash interface (2) (3)
14?32 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook enhanced configuration devices (e pc4, epc8 & epc16) data sheet chapter in volume 2 of the configuration handbook serial configuration devices (epc s1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook document revision history table 14?14 shows the revision hi story for this chapter. table 14?14. document revision history date and document version changes made summary of changes october 2007, v4.5 updated ta b l e 1 4 ? 7 .? added the ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 13. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 updated note to ?functional description? section. ? minor text edit to ?remote system upgrade with serial configuration devices? section. ? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 12. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ?
altera corporation 15?1 october 2007 15. ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices introduction as printed circuit boards (pcbs) become more complex, the need for thorough testing becomes increasi ngly important. advances in surface-mount packaging and pcb ma nufacturing have resulted in smaller boards, making traditional te st methods (such as ; external test probes and ?bed-of-nails? test fixture) harder to implement. as a result, cost savings from pcb space reductions increases the cost for traditional testing methods. in the 1980s, the joint test action gr oup (jtag) developed a specification for boundary-scan testing that was la ter standardized as the ieee std. 1149.1 specification. this boundary-sca n test (bst) architecture offers the capability to test efficiently componen ts on pcbs with tight lead spacing. this bst architecture tests pin connections without using physical test probes and captures functional data while a device is operating normally. boundary-scan cells in a device can force signals onto pins or capture data from pin or logic array signals. forced test data is serially shifted into the boundary-scan cells. captured data is serially shifted out and externally compared to expected results. figure 15?1 illustrates the concept of bst. figure 15?1. ieee std. 1149.1 boundary-scan testing core logic serial data in boundary-scan cell ic core logic serial data out jtag device 1 jtag device 2 pin signal tested connection sii52009-3.3
15?2 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 bst architecture this chapter discusses how to use th e ieee std. 1149.1 bst circuitry in stratix ? ii and stratix gx devices, including: ieee std. 1149.1 bst architecture ieee std. 1149.1 boun dary-scan register ieee std. 1149.1 bst operation control i/o voltage support in jtag chain ieee std. 1149.1 bst circuitry utilization ieee std. 1149.1 bst circuitry disabling ieee std. 1149.1 bst guidelines boundary-scan description language (bsdl) support in addition to bst, you can use the ieee std. 1149.1 controller for stratix ii and stratix ii gx device in-circuit re configuration (icr). however, this chapter only discusses the bst feature of the ieee std. 1149.1 circuitry. f for information on configuring strati x ii devices via the ieee std. 1149.1 circuitry, refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook , or the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . 1 when configuring via ijag make sure that stratix ii, stratix ii gx, stratix, cyclone ? ii, and cyclone devices are within the first 17 devices in a jt ag chain. all of these devices have the same jtag controller. if any of the stratix ii, stratix ii gx, stratix, cyclone ii, and cyclone devices are in the 18th or further position, configurat ion fails. this does not affect signaltap ? ii or boundary-scan testing. ieee std. 1149.1 bst architecture a stratix ii and stratix ii gx device operating in ieee std. 1149.1 bst mode uses four required pins, tdi , tdo , tms and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms and trst pins have weak internal pull-ups. the tdo output pin is powered by v ccio in i/o bank 4. all of the jtag input pins are powered by the 3.3-v v ccpd supply. all user i/o pins are tri-stated during jtag configuration. 1 for recommendations on how to connect a jtag chain with multiple voltages across the de vices in the chain, refer to ?i/o voltage support in jtag chain? on page 15?17 .
altera corporation 15?3 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices table 15?1 summarizes the functions of each of these pins. the ieee std. 1149.1 bst circuitry requires the following registers: the instruction register determines the action to be performed and the data register to be accessed. the bypass register is a 1-bit-long data register that provides a minimum-length serial path between tdi and tdo . the boundary-scan register is a sh ift register composed of all the boundary-scan cells of the device. table 15?1. ieee std. 1149.1 pin descriptions pin description function tdi test data input serial input pin for instruct ions as well as test and programming data. data is shifted in on the rising edge of tck . tdo test data output serial data output pin for inst ructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. tms test mode select input pin that provides the c ontrol signal to determine the transitions of the test access port (tap) controller state machine. transitions within the state machine occur at the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . tck test clock input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. trst test reset input (optional) active-low input to asynchronous ly reset the boundary-scan circuit. this pin should be driven low when not in boundary-scan operation and for non-jtag users the pin s hould be permanently tied to gnd.
15?4 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 boundary-scan register figure 15?2 shows a functional model of the ieee std. 1149.1 circuitry. figure 15?2. ieee std. 1149.1 circuitry note to figure 15?2 : (1) refer to the appropriate device data sheet for register lengths. ieee std. 1149.1 boundary-scan testing is controlled by a test access port (tap) controller. for more information on the tap controller, refer to ?ieee std. 1149.1 bst operation control? on page 15?7 . the tms and tck pins operate the tap controller, and the tdi and tdo pins provide the serial path for the data registers. the tdi pin also provides data to the instruction register, which then ge nerates control logic for the data registers. ieee std. 1149.1 boundary-scan register the boundary-scan register is a large serial shift register that uses the tdi pin as an input and the tdo pin as an output. the boundary-scan register consists of 3-bit peripheral elements that are associated with stratix ii or stratix ii gx i/o pins. you can use th e boundary-scan register to test external pin connec tions or to capture internal data. a updateir clockir shiftir updatedr clockdr shiftdr tdi instruction register bypass register boundary-scan register instruction decode tms tclk ta p controller icr registers tdo data registers device id register trst (1) (1) (1)
altera corporation 15?5 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices f refer to the configuration & testing chapter in volume 1 of the stratix ii device handbook , or the configuration & testing chapter in volume 1 of the stratix ii gx device handbook for the stratix ii family device boundary-scan register lengths. figure 15?3 shows how test data is serially shifted around the periphery of the ieee std. 1149.1 device. figure 15?3. boundary-scan register boundary-scan cells of a stratix ii or stratix ii gx device i/o pin the stratix ii or the stratix ii gx devi ce 3-bit boundary-scan cell (bsc) consists of a set of capture register s and a set of update registers. the capture registers can connect to internal device data via the outj , oej , and pin_in signals, while the update registers connect to external data through the pin_out , and pin_oe signals. the global control signals for the ieee std. 1149.1 bst registers (such as shift, clock, and update) are generated internally by the tap controller. the mode signal is generated by a decode of the instruction register. the data signal path for the boundary-scan register ru ns from the serial data in (sdi) signal to the serial data out (sdo) signal. th e scan register begins at the tdi pin and ends at the tdo pin of the device. tck trst (1) tms tap controller tdi internal lo g ic tdo e ac h per i p h era l e l e m e n t i s e i t h er a n i/o p in, ded i cated in p u t p in, o r ded i cated c on f i g u rat ion p in.
15?6 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 boundary-scan register figure 15?4 shows the stratix ii and stratix ii gx device?s user i/o boundary-scan cell. figure 15?4. stratix ii and stratix ii gx device's user i/o bsc with ieee std. 1149.1 bst circuitry table 15?2 describes the capture and update register capabilities of all boundary-scan cells within stratix ii and stratix ii gx devices. 0 1 dq output dq oe dq input dq input dq output dq oe from or to device i/o cell circuitry and/or logic array 0 1 0 1 0 1 0 1 0 1 0 1 pin_out inj oej outj v cc sdo pin shift sdi clock update highz mode pin_oe pin_in output buffer capture registers update registers global signals table 15?2. stratix ii and stratix ii gx device b oundary scan cell descriptions (part 1 of 2) note (1) pin type captures drives comments output capture register oe capture register input capture register output update register oe update register input update register user i/o pins outj oej pin_in pin_out pin_oe inj na dedicated clock input 01 pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to clock network or logic array
altera corporation 15?7 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices ieee std. 1149.1 bst operation control stratix ii and stratix ii gx devices im plement the following ieee std. 1149.1 bst instructions: sample/preload instruction mode is used to take snapshot of the device data without interrupt ing normal device operations extest instruction mode is used to check external pin connections between devices bypass instruction mode is used when an instruction code consisting of all ones is load ed into the instruction register idcode instruction mode is used to identify the devices in an ieee std. 1149.1 chain usercode instruction mode is used to examine the user electronic signature within the device al ong an ieee std. 1149.1 chain. dedicated input (3) 01 pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to control logic dedicated bidirectional (open drain) (4) 0 oej pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to configuration control dedicated bidirectional (5) outj oej pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to configuration control and outj drives to output buffer dedicated output (6) outj 00n.c. (2) n.c. (2) n.c. (2) outj drives to output buffer notes to table 15?2 : (1) tdi , tdo , tms , tck , all v cc and gnd pin types, vref , and temp_diode pins do not have bscs. (2) no connect (n.c.). (3) this includes pins pll_ena , nconfig , msel0 , msel1 , msel2 , msel3 , nce , vccsel , porsel , and nio_pullup . (4) this includes pins conf_done and nstatus . (5) this includes pin dclk . (6) this includes pin nceo . table 15?2. stratix ii and stratix ii gx device b oundary scan cell descriptions (part 2 of 2) note (1) pin type captures drives comments output capture register oe capture register input capture register output update register oe update register input update register
15?8 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 bst operation control clamp instruction mode is used to allow the state of the signals driven from the pins to be de termined from the boundary-scan register while the bypass register is selected as the serial path between the tdi and tdo ports highz instruction mode sets all of th e user i/o pins to an inactive drive state the bst instruction length is 10 bits. these instructions are described later in this chapter. f for summaries of the bst instructions and their instruction codes, refer to the configuration & testing chapter in volume 1 of the stratix ii device handbook , or the configuration & testing chapter in volume 1 of the stratix ii gx device handbook . the ieee std. 1149.1 tap controller, a 16-state state machine clocked on the rising edge of tck , uses the tms pin to control ieee std. 1149.1 operation in the device. figure 15?5 shows the tap controller state machine.
altera corporation 15?9 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices figure 15?5. ieee std. 1149.1 tap controller state machine when the tap controller is in the test_logic/reset state, the bst circuitry is disabled, the device is in normal operation, and the instruction register is initialized with idcode as the initial instruction. at device power-up, the tap controller starts in this test_logic/reset state. in addition, forcing the tap controller to the test_logic/reset state is done by holding tms high for five tck clock cycles or by holding the trst pin low. once in the test_logic/reset state, the tap controller remains in this state as long as tms is held high (while tck is clocked) or trst is held low. select_dr_scan capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr shift_ir exit1_ir pause_ir exit2_ir update_ir tms = 0 tms = 0 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 run_test/ idle tms = 0 test_logic/ reset tms = 1 tms = 0 tms = 1 tms = 1 tms = 1 tms = 1 capture_ir select_ir_sca n
15?10 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 bst operation control figure 15?6 shows the timing requirements for the ieee std. 1149.1 signals. figure 15?6. ieee std. 1149.1 timing waveforms to start ieee std. 1149.1 operation, select an instruction mode by advancing the tap controller to the shift instruction register ( shift_ir ) state and shift in the appropriate instruction code on the tdi pin. the waveform diagram in figure 15?7 represents the entry of the instruction code into the instruction register. figure 15?7 shows the values of tck , tms , tdi , tdo , and the states of the tap controller. from the reset state, tms is clocked with the pattern 01100 to advance the tap controller to shift_ir . figure 15?7. selecting the instruction mode tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz tck tms tdi tdo ta p _ s tat e shift_ir run_test/idle select_ir_scan select_dr_scan test_logic/reset capture_ir exit1_ir
altera corporation 15?11 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices the tdo pin is tri-stated in all states except in the shift_ir and shift_dr states. the tdo pin is activated at the first falling edge of tck after entering either of the shift states and is tri-stated at the first falling edge of tck after leaving either of the shift states. when the shift_ir state is activated, tdo is no longer tri-stated, and the initial state of the instruction register is shifted out on the falling edge of tck . tdo continues to shift out the contents of the instruction register as long as the shift_ir state is active. the tap controller remains in the shift_ir state as long as tms remains low. during the shift_ir state, an instruction code is entered by shifting data on the tdi pin on the rising edge of tck . the last bit of the instruction code is clocked at the same time that the next state, exit1_ir , is activated. set tms high to activate the exit1_ir state. once in the exit1_ir state, tdo becomes tri-stated again. tdo is always tri-stated except in the shift_ir and shift_dr states. after an instruction code is entered correctly, the tap controller advances to serially shift test data in one of thr ee modes. the three serially shift test data instruction modes are discussed on the following pages: ?sample/preload instruction mode? on page 15?11 ?extest instruction mode? on page 15?13 ?bypass instruction mode? on page 15?15 sample/preload instruction mode the sample/preload instruction mode allows you to take a snapshot of device data without interrupting norm al device operation. however, this instruction is most ofte n used to preload the test data into the update registers prior to loading the extest instruction. figure 15?8 shows the capture, shift, and update phases of the sample / preload mode.
15?12 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 bst operation control figure 15?8. ieee std. 1149.1 bst sample/preload mode 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdo sdi shift clock update 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej sdi shift clock update mode sdo inj capture registers update registers capture phase in the capture phase, the signals at the pin, oej and outj, are load ed into the capture registers. the clock signals is supplied by the tap controller?s clockdr output. the data retained in these registers consists of signals from normal device operation. shift and update phases in the shift phas e, the previously captured signals at the pin, oej and outj, are shifted out of the boundary-scan register via the tdo pin using clock. as data is shifted out, the patterns for the next test can be shifted in via the tdi pin. in the update phase, data is transferred from the capture to the update registers using the update clock. the data stored in the update registers can be used for the ex test instruction.
altera corporation 15?13 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices during the capture phase, multiplex ers preceding the capture registers select the active device data signals. this data is then clocked into the capture registers. the multiplexers at the outputs of the update registers also select active device data to pr event functional interruptions to the device. during the shift phase, the bo undary-scan shift register is formed by clocking data through capture registers around the device periphery and then out of the tdo pin. the device can simultaneously shift new test data into tdi and replace the contents of th e capture registers. during the update phase, data in the capture re gisters is transferred to the update registers. this data can then be used in the extest instruction mode. refer to ?extest instruction mode? on page 15?13 for more information. figure 15?9 shows the sample/preload waveforms. the sample/preload instruction code is shifted in through the tdi pin. the tap controller advances to the capture_dr state and then to the shift_dr state, where it remains if tms is held low. the data that was present in the capture registers after the capture phase is shifted out of the tdo pin. new test data shifted into the tdi pin appears at the tdo pin after being clocked through the entire boundary-scan register. figure 15?9 shows that the instruction code at tdi does not appear at the tdo pin until after the capture register data is shifted out. if tms is held high on two consecutive tck clock cycles, the tap controller advances to the update_dr state for the update phase. figure 15?9. sample/preload shi ft data register waveforms extest instruction mode the extest instruction mode is used primarily to check external pin connections between devices. unlike the sample/preload mode, extest allows test data to be forced onto the pin signals. by forcing known logic high and low levels on output pins, opens and shorts can be detected at pins of any device in the scan chain. data stored in boundary-scan register is shifted out of tdo. after boundary-scan register data has been shifted out, data entered into tdi will shift out of tdo. update_ir shift_dr exit1_dr select_dr capture_dr exit1_ir update_dr shift_ir instruction code tck tms tdi tdo tap_state
15?14 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 bst operation control figure 15?10 shows the capture, shift, and update phases of the extest mode. figure 15?10. ieee std. 1149.1 bst extest mode 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdi shift clock update sdo 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdi shift clock update sdo capture phase in the capture phase, the signals at the pin, oej and outj, are loaded into the capture registers. the clock signals is supplied by the tap controller?s clockdr output. previously retained data in the update registers drive the pin_in, inj, and allows the i/o pin to tri-state or drive a signal out. a ?1? in the oej update register tri-states the output buffer. shift and update phases in the shift pha se, the previously captured signals at the pin, oej and outj, are shifted out of the boundary-scan register via the tdo pin using clock. as data is shifted out, the patterns for the next test can be shifted in via the tdi pin. in the update phase, data is transferred from the capture registers to the update registers using the update clock. the update registers then drive the pin_in, inj, and allow the i/o pin to tri-state or drive a signal out.
altera corporation 15?15 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices extest selects data differently than sample/preload . extest chooses data from the update registers as the source of the output and output enable signals. once the extest instruction code is entered, the multiplexers select the update register data. thus, data stored in these registers from a previous extest or sample/preload test cycle can be forced onto the pin signals. in the capt ure phase, the results of this test data are stored in the capture registers and then shifted out of tdo during the shift phase. new test data can then be stored in the update registers during the update phase. the extest waveform diagram in figure 15?11 resembles the sample/preload waveform diagram, except for the instruction code. the data shifted out of tdo consists of the data that was present in the capture registers after the capture phase. new test data shifted into the tdi pin appears at the tdo pin after being clocked through the entire boundary-scan register. figure 15?11. extest shift data register waveforms bypass instruction mode the bypass mode is activated when an instruction code of all ones is loaded in the instruction register. the waveforms in figure 15?12 show how scan data passes through a device once the tap controller is in the shift_dr state. in this state, data si gnals are clocked into the bypass register from tdi on the rising edge of tck and out of tdo on the falling edge of the same clock pulse. data stored in boundary-scan register is shifted out of tdo. after boundary-scan register data has been shifted out, data entered into tdi will shift out of tdo. update_ir shift_dr exit1_dr select_dr capture_dr exit1_ir update_dr shift_ir instruction code tck tms tdi tdo tap_state
15?16 altera corporation stratix ii gx device handbook, volume 2 october 2007 ieee std. 1149.1 bst operation control figure 15?12. bypass shift data register waveforms idcode instruction mode the idcode instruction mode is used to identify the devices in an ieee std. 1149.1 chain. when idcode is selected, the device identification register is loaded with the 32-bit ve ndor-defined identification code. the device id register is connected between the tdi and tdo ports, and the device idcode is shifted out. f for more information on the idcode for stratix ii and stratix ii gx devices refer to the configuration & testing chapter in volume 1 of the stratix ii device handbook , or the configuration & testing chapter in volume 1 of the stratix ii gx device handbook. usercode instruction mode the usercode instruction mode is used to examine the user electronic signature (ues) within the devices alon g an ieee std. 1149.1 chain. when this instruction is selected, the device identification register is connected between the tdi and tdo ports. the user-defined ues is shifted into the device id register in parallel from the 32-bit usercode register. the ues is then shifted out through the device id register. 1 the ues value is not user defined until after the device is configured. before configuration, the ues value is set to the default value. data shifted into tdi on the rising edge of tck is shifted out of tdo on the falling edge of the same tck pulse. update_ir select_dr_scan capture_dr exit1_ir exit1_dr update_dr shift_dr instruction code tck tms tdi tdo tap_state shift_ir bit 2 bit 3 bit 1 bit 2 bit 4 bit 1
altera corporation 15?17 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices clamp instruction mode the clamp instruction mode is used to allow the state of the signals driven from the pins to be determin ed from the boundary-scan register while the bypass register is select ed as the serial path between the tdi and tdo ports. the state of all signals driven from the pins are completely defined by the data held in the boundary-scan register. 1 if you are testing after configuring the device, the programmable weak pull -up resister or the bus hold feature overrides the clamp value (the value stored in the update register of the boundary-scan cell) at the pin. highz instruction mode the highz instruction mode sets all of th e user i/o pins to an inactive drive state. these pins are tri-stated until a new jtag instruction is executed. when this instruction is lo aded into the instruction register, the bypass register is connected between the tdi and tdo ports. 1 if you are testing after configuring the device, the programmable weak pull -up resistor or the bus hold feature overrides the highz value at the pin. i/o voltage support in jtag chain the jtag chain supports several devices. however, you should use caution if the chain contains devices that have different v ccio levels. the output voltage level of the tdo pin must meet the specifications of the tdi pin it drives. the tdi pin is powered by v ccpd (3.3 v). for stratix ii and stratix ii gx devices, the v ccio power supply of bank 4 powers the tdo pin. table 15?3 shows board design recommendations to ensure proper jtag chain operation. you can interface the tdi and tdo lines of the devices that have different v ccio levels by inserting a level shifter between the devices. if possible, you should build the jtag chain in such a way that a device with a higher v ccio level drives to a device with an equal or lower v ccio level. this way, a level shifter is used only to shift the tdo level to a level acceptable to the jtag tester. figure 15?13 shows the jtag chain of mixed voltages and how a level shifter is inserted in the chain.
15?18 altera corporation stratix ii gx device handbook, volume 2 october 2007 i/o voltage support in jtag chain figure 15?13. jtag chai n of mixed voltages table 15?3. supported tdo/tdi voltage combinations device tdi input buffer power stratix ii and stratix ii gx tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v stratix ii and stratix ii gx always v ccpd (3.3v) v (1) v (2) v (3) level shifter required non-stratix ii vcc = 3.3 v v (1) v (2) v (3) level shifter required vcc = 2.5 v v (1) , (4) v (2) v (3) level shifter required vcc = 1.8 v v (1) , (4) v (2) , (5) v level shifter required vcc = 1.5 v v (1) , (4) v (2) , (5) v (6) v notes to table 15?3 : (1) the tdo output buffer meets v oh (min) = 2.4 v. (2) the tdo output buffer meets v oh (min) = 2.0 v. (3) an external 250- pull-up resistor is not required, but recommende d if signal levels on the board are not optimal. (4) input buffer must be 3.3-v tolerant. (5) input buffer must be 2.5-v tolerant. (6) input buffer must be 1.8-v tolerant. 3.3 v v ccio level shifter 2.5 v v ccio 1.8 v v ccio 1.5 v v ccio tester tdo tdi must be 3.3 v tolerant. shift tdo to level accepted by tester if necessary. must be 1.8 v tolerant. must be 2.5 v tolerant.
altera corporation 15?19 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices using ieee std. 1149.1 bst circuitry stratix ii and stratix ii gx devices have dedicated jtag pins and the ieee std. 1149.1 bst circ uitry is enabled upon device power-up. not only can you perform bst on stratix ii and stratix ii gx fpgas before and after, but also during configuratio n. stratix ii and stratix ii gx fpgas support the bypass , idcode and sample instructions during configuration without interrupting conf iguration. to send all other jtag instructions, you must interrupt configuration using the config_io instruction. the config_io instruction allows you to configure i/o buffers via the jtag port, and when issued, interrupts configuration. this instruction allows you to perform board-level testing prior to configuring the stratix ii or the stratix ii gx fpga or you can wait for the configuration device to complete configuration. on ce configuration is interrupted and jtag bst is complete, you must reconfigure the part via jtag ( pulse_config instruction) or by pulsing nconfig low. 1 when you perform jtag boundary-scan testing before configuration, the nconfig pin must be held low. the chip-wide reset ( dev_clrn ) and chip-wide output enable ( dev_oe ) pins on stratix ii and stratix ii gx devices do not affect jtag boundary-scan or configuration operat ions. toggling these pins does not disrupt bst operation (other than the expected bst behavior). when you design a board for jtag configuration of stratix ii or stratix ii gx devices, you need to consider the conn ections for the dedicated configuration pins. f for more information on using the ie ee std.1149.1 circuitry for device configuration, refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . bst for configured devices for a configured device, the input buffers are turned off by default for i/o pins that are set as output only in the design file. you cannot sample on the configured device output pins with the default bsdl file when the input buffers are turned off. you can set the quartus ii software to always enable the input buffers on a configured device so it behaves the same as an unconfigured device for boundary-scan testing, allowing sample function on output pins in the de sign. this aspect can cause slight increase in standby current because th e unused input buff er is always on. in the quartus ii software, do the following: 1. choose settings (assignments menu).
15?20 altera corporation stratix ii gx device handbook, volume 2 october 2007 disabling ieee std. 1149.1 bst circuitry 2. click assembler . 3. turn on always enable input buffers . disabling ieee std. 1149.1 bst circuitry the ieee std. 1149.1 bst circuitry fo r stratix ii and stratix ii gx devices is enabled upon device power-up. because the ieee std. 1149.1 bst circuitry is used for bst or in-circuit reconfiguration, you must enable the circuitry only at specific times as mentioned in, ?using ieee std. 1149.1 bst circuitry? on page 15?19 . 1 if you are not using the ieee std. 1149.1 circuitry in stratix ii or stratix ii gx, then you should pe rmanently disable the circuitry to ensure that you do not inadve rtently enable when it is not required. table 15?4 shows the pin connections necessary for disabling the ieee std. 1149.1 circuitry in stratix ii and stratix ii gx devices. guidelines for ieee std. 1149.1 boundary-scan testing use the following guidelines when performing boundary-scan testing with ieee std. 1149.1 devices: if the ?10...? pattern does not shift out of the instruction register via the tdo pin during the firs t clock cycle of the shift_ir state, the tap controller did not reach the proper state. to solve this problem, try one of the following procedures: verify that the tap controller has reached the shift_ir state correctly. to advance the tap controller to the shift_ir state, return to the reset state and send the code 01100 to the tms pin. table 15?4. disabling ieee std. 1149.1 circuitry jtag pins (1) connection for disabling tms v cc tck gnd tdi v cc tdo leave open trst gnd note to table 15?4 : (1) there is no software option to disable jtag in stratix ii or stratix ii gx devices. the jtag pins are dedicated.
altera corporation 15?21 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices check the connections to the v cc , gnd, jtag, and dedicated configuration pins on the device. perform a sample/preload test cycle prior to the first extest test cycle to ensure that known data is present at the device pins when you enter the extest mode. if the oej update register contains a 0, the data in the outj update register is driven out. the state must be known and correct to avoid contention with other devices in the system. do not perform extest testing during icr. this instruction is supported before or after icr, but not during icr. use the config_io instruction to interrupt configuration and then perform testing, or wait for configuration to complete. if performing testing before configuration, hold nconfig pin low. after configuration, an y pins in a differential pin pair cannot be tested. therefore, performing bst after configuration requires editing of bsc group defi nitions that correspond to these differential pin pairs. the bsc group should be redefined as an internal cell. 1 refer to the boundary-scan description language (bsdl) file for more information on editing. f for more information on boundary scan testing, contact altera applications group. boundary-scan description language (bsdl) support the boundary-scan description lang uage (bsdl), a subset of vhdl, provides a syntax that allows you to de scribe the features of an ieee std. 1149.1 bst-capable device that can be tested. test software development systems then use the bsdl files for test generation, analysis, and failure diagnostics. f for more information, or to receive bsdl files for ieee std. 1149.1-compliant stratix ii and stratix i i gx devices, visit the altera web site at www.altera.com . conclusion the ieee std. 1149.1 bst circuitry av ailable in stratix ii and stratix ii gx devices provides a cost-effective and efficient way to test systems that contain devices with tight lead spacin g. circuit boards with altera and other ieee std. 1149.1-comp liant devices can use the extest , sample/preload , and bypass modes to create serial patterns that internally test the pin connections between devices and check device operation.
15?22 altera corporation stratix ii gx device handbook, volume 2 october 2007 references references bleeker, h., p. van den eijnden, and f. de jong. boundary-scan test: a practical approach . eindhoven, the netherla nds: kluwer academic publishers, 1993. institute of electrical and electronics engineers, inc. ieee standard test access port and boundary-scan architecture (ieee std 1149.1-2001). new york: institute of electrical and electronics engineers, inc., 2001. maunder, c. m., and r. e. tulloss. the test access port and boundary-scan architecture . los alamitos: ieee comp uter society press, 1990. referenced documents this chapter references the following documents: configuration & testing chapter in volume 1 of the stratix ii device handbook configuration & testing chapter in volume 1 of the stratix ii gx device handbook configuring stratix ii & stratix ii gx de vices chapter in volume 2 of the stratix ii device handbook configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook document revision history table 15?5 shows the revision history for this chapter. table 15?5. document revision history (part 1 of 2) date and document version changes made summary of changes october 2007, v3.3 added ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 14. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? february 2007 v3.2 added the ?document revision history? section to this chapter. ? april 2006, v3.1 chapter updated as part of the stratix ii device handbook update. ?
altera corporation 15?23 october 2007 stratix ii gx device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testing for stratix ii & stratix ii gx devices no change formerly chapter 13. chapter number change only due to chapter addition to section i in february 2006; no content change. ? october 2005 v3.0 added chapter to the stratix ii gx device handbook . ? table 15?5. document revision history (part 2 of 2) date and document version changes made summary of changes
15?24 altera corporation stratix ii gx device handbook, volume 2 october 2007 document revision history
altera corporation section vii?1 preliminary section vii. pcb layout guidelines this section provides informatio n for board layout designers to successfully layout th eir boards for stratix ? ii gx devices. these chapters contain the required pcb layout guidelines and package specifications. this section contains the following chapters: chapter 16, package information for stratix ii & stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section vii?2 altera corporation preliminary pcb layout guidelines stratix ii gx device handbook, volume 2
altera corporation 16?1 may 2007 16. package information for stratix ii & stratix ii gx devices introduction this chapter provides pack age information for altera ? stratix ? ii and stratix ii gx devices, including: device and package cross reference thermal resistance values package outlines tables 16?1 and 16?2 show which altera stratix ii and stratix ii gx devices, respectively, are available in fineline bga ? (fbga) packages. table 16?1. stratix ii devices in fbga packages device package pins ep2s15 flip-chip fbga 484 flip-chip fbga 672 ep2s30 flip-chip fbga 484 flip-chip fbga 672 ep2s60 flip-chip fbga 484 flip-chip fbga 672 flip-chip fbga 1,020 ep2s90 flip-chip fbga 484 flip-chip fbga 780 flip-chip fbga 1,020 flip-chip fbga 1,508 ep2s130 flip-chip fbga 780 flip-chip fbga 1,020 flip-chip fbga 1,508 ep2s180 flip-chip fbga 1,020 flip-chip fbga 1,508 sii52010-4.3
16?2 altera corporation stratix ii gx device handbook, volume 2 may 2007 thermal resistance thermal resistance thermal resistance values for stratix ii devices are provided for a board that meets jdec specifications and for a typical board. the following values are provided: ja (c/w) still air?junction-to-ambi ent thermal resistance with no air flow when a heat sink is not used. ja (c/w) 100 ft./min.?junction-to-ambient thermal resistance with 100 ft./min. airflow when a heat sink is not used. ja (c/w) 200 ft./min.?junction-to-ambient thermal resistance with 200 ft./min. airflow when a heat sink is not used. ja (c/w) 400 ft./min.?junction-to-ambient thermal resistance with 400 ft./min. airflow when a heat sink is not used. jc ?junction-to-case thermal resistance for device. jb ?junction-to-board thermal resistance for device. tables 16?3 provides ja (junction-to-ambient thermal resistance), jc (junction-to-case thermal resistance), and jb (junction-to-board thermal resistance) values for stratix ii devices on a board meeting jedec specifications for thermal resistance calculation. the jedec board specifications require two signal an d two power/ground planes and are available at www.jedec.org . table 16?2. stratix ii gx devices in fbga packages device package pins ep2sgx30 flip-chip fbga 780 ep2sgx60 flip-chip fbga 780 flip-chip fbga 1,152 ep2sgx90 flip-chip fbga 1,152 flip-chip fbga 1,508 ep2sgx130 flip-chip fbga 1,508 table 16?3. stratix ii device thermal resistance for b oards meeting jedec spec ifications (part 1 of 2) device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) jb ( c/w) ep2s15 484 fbga 13.1 11.1 9.6 8.3 0.36 4.19 672 fbga 12.2 10.2 8.8 7.6 0.36 4.09 ep2s30 484 fbga 12.6 10.6 9.1 7.9 0.21 3.72 672 fbga 11.7 9.7 8.3 7.1 0.21 3.35
altera corporation 16?3 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices table 16?4 provides ja (junction-to-ambient thermal resistance), jc (junction-to-case thermal resistance), and jb (junction-to-board thermal resistance) values for stratix ii devices on a board with the information shown in table 16?5 . ep2s60 484 fbga 12.3 10.3 8.8 7.5 0.13 3.38 672 fbga 11.4 9.4 7.8 6.7 0.13 2.95 1,020 fbga 10.4 8.4 7.0 5.9 0.13 2.67 ep2s90 484 hybrid fbga 12.0 9.9 8.3 7.1 0.07 3.73 780 fbga 10.8 8.8 7.3 6.1 0.09 2.59 1,020 fbga 9.2 8.2 6.8 5.7 0.10 2.41 1,508 fbga 9.3 7.4 6.1 5.0 0.10 2.24 ep2s130 780 fbga 10.1 8.7 7.2 6.0 0.07 2.44 1,020 fbga 9.5 8.1 6.7 5.5 0.07 2.24 1,508 fbga 8.6 7.3 6.0 4.8 0.07 2.08 ep2s180 1,020 fbga 9.0 7.9 6.5 5.4 0.05 2.10 1,508 fbga 8.1 7.1 5.8 4.7 0.05 1.94 table 16?3. stratix ii device thermal resistance for b oards meeting jedec spec ifications (part 2 of 2) device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) jb ( c/w) table 16?4. stratix ii device thermal resi stance for typical board (part 1 of 2) device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) jb ( c/w) ep2s15 484 fbga 12.6 9.9 8.1 6.7 0.36 2.48 672 fbga 11.4 8.8 7.2 5.9 0.36 2.41 ep2s30 484 fbga 12.3 9.6 7.8 6.4 0.21 2.02 672 fbga 11.1 8.5 6.9 5.6 0.21 1.95 ep2s60 484 fbga 12.1 9.4 7.6 6.3 0.13 1.74 672 fbga 10.9 8.3 6.6 5.4 0.13 1.56 1,020 fbga 9.6 7.1 5.6 4.5 0.13 1.33 ep2s90 484 hybrid fbga 11.2 8.9 7.2 5.9 0.07 2.48 780 fbga 10.0 7.6 6.1 4.9 0.09 1.22 1,020 fbga 9.2 6.9 5.5 4.4 0.10 1.16 1,508 fbga 8.2 6.0 4.7 3.7 0.10 1.15
16?4 altera corporation stratix ii gx device handbook, volume 2 may 2007 thermal resistance table 16?6 provides ja (junction-to-ambient thermal resistance) and jc (junction-to-case thermal resistance) values for stratix ii devices. ep2s130 780 fbga 9.3 7.5 6.0 4.8 0.07 1.12 1,020 fbga 8.5 6.8 5.3 4.2 0.07 1.03 1,508 fbga 7.5 5.8 4.6 3.6 0.07 1.02 ep2s180 1,020 fbga 8.0 6.7 5.3 4.2 0.05 0.93 1,508 fbga 7.1 5.7 4.5 3.5 0.05 0.91 table 16?4. stratix ii device thermal resi stance for typical board (part 2 of 2) device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) jb ( c/w) table 16?5. board specifications notes (1) , (2) pin count package signal layers power/ground layers size (mm) 1,508 fbga 12 12 100 100 1,020 fbga 10 10 93 93 780 fbga 9 9 89 89 672 fbga 8 8 87 87 484 fbga 7 7 83 83 notes to ta b l e 1 6 ? 5 : (1) power layer cu thickness 35 um, cu 90%. (2) signal layer cu thickness 17 um, cu 15%. table 16?6. stratix ii gx de vice thermal resistance device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) ep2sgx30 780 fbga 11.1 8.6 7.2 6.0 0.24 ep2sgx60 780 fbga 10.9 8.4 6.9 5.8 0.15 1,152 fbga 9.9 7.5 6.1 5.0 0.15 ep2sgx90 1,152 fbga 9.6 7.3 5.9 4.9 0.11 1,508 fbga 9.0 6.7 5.4 4.4 0.11 ep2sgx130 1,508 fbga 8.3 6.6 5.3 4.3 0.10
altera corporation 16?5 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices package outlines the package outlines are listed in or der of ascending pin count. altera package outlines meet the requirements of jedec publication no. 95. 484-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m ? 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on the package surface. tables 16?7 and 16?8 show the package information and package outline figure references, respectively , for the 484-pin fbga packaging. table 16?7. 484-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aaj-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 5.8 g moisture sensitivity level p rinted on moisture barrier bag table 16?8. 484-pin fbga package outline dimensions (part 1 of 2) symbol millimeter min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 23.00 bsc e 23.00 bsc
16?6 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 16?1 shows a package outline for the 484-pin fineline bga packaging. figure 16?1. 484-pin fbga package outline 672-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. b 0.50 0.60 0.70 e 1.00 bsc table 16?8. 484-pin fbga package outline dimensions (part 2 of 2) symbol millimeter min. nom. max. d a1 a3 a2 a e e e b pin a1 id pin a1 corner bottom view top view
altera corporation 16?7 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices tables 16?9 and 16?10 show the package inform ation and package outline figure references, respectively , for the 672-pin fbga packaging. table 16?9. 672-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aal-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 7.7 g moisture sensitivity level printed on moisture barrier bag table 16?10. 672-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 27.00 bsc e 27.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
16?8 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 16?2 shows a package outline for the 672-pin fineline bga packaging. figure 16?2. 672-pin fbga package outline e d e e a1 a2 b a3 a pin a1 id pin a1 corner bottom view top view
altera corporation 16?9 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 780-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 16?11 and 16?12 show the package information and package outline figure references, respective ly, for the 780-pin fbga packaging. table 16?11. 780-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aam-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 8.9 g moisture sensitivity level printed on moisture barrier bag table 16?12. 780-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 29.00 bsc e 29.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
16?10 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 16?3 shows a package outline for the 780-pin fineline bga packaging. figure 16?3. 780-pin fbga package outline pin a1 id pin a1 corner bottom view top view e d e e a1 a2 b a3 a
altera corporation 16?11 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 1,020-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 16?13 and 16?14 show the package information and package outline figure references, respective ly, for the 1,020-pin fbga packaging. table 16?13. 1,020-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aap-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 11.5 g moisture sensitivity level printed on moisture barrier bag table 16?14. 1,020-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 33.00 bsc e 33.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
16?12 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 16?4 shows a package outline fo r the 1,020-pin fineline bga packaging. figure 16?4. 1,020-pin fbga package outline d e pin a1 id b e e a3 a1 a2 pin a1 corner a bottom view top view
altera corporation 16?13 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 1,152-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 16?15 and 16?16 show the package information and package outline figure references, respective ly, for the 1,152-pin fbga packaging. table 16?15. 1,152-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aar-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 12.0 g moisture sensitivity level printed on moisture barrier bag table 16?16. 1,152-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 35.00 bsc e 35.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
16?14 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 16?5 shows a package outline fo r the 1,152-pin fineline bga packaging. figure 16?5. 1,152-pin fbga package outline bottom view top view e d pin a1 id a2 a3 a1 a pin a1 corner e b e
altera corporation 16?15 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 1,508-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 16?17 and 16?18 show the package information and package outline figure references, respective ly, for the 1,508-pin fbga packaging. table 16?17. 1,508-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aau-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 14.6 g moisture sensitivity level printed on moisture barrier bag table 16?18. 1,508-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 40.00 bsc e 40.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
16?16 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 16?6 shows a package outline fo r the 1,508-pin fineline bga packaging. figure 16?6. 1,508-pin fbga package outline pin a1 corner b e e d pin a1 id a2 a3 a1 a e top view bottom view
altera corporation 16?17 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices document revision history table 16?19 shows the revision hi story for this chapter. table 16?19. document revision history date and document version changes made summary of changes no change for the stratix ii gx device handbook only: formerly chapter 15. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.3 minor change to table 16?3 .? february 2007 v4.2 added the ?document revision history? section to this chapter. ? no change formerly chapter 14. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook .?
16?18 altera corporation stratix ii gx device handbook, volume 2 may 2007 document revision history

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