ds-11802 four quadrant multiplying sin/cos dac, microprocessor compatible, 16-bit hybrid description the ds-11802 is a small size, high accuracy, 16-bit digital-to-sine/cosine converter. available in accuracies up to 1 arc minute, the ds-11802 is con- tained in a 28-pin ddip and requires +15 vdc and -15 vdc power supplies. the reference input is buffered through an op-amp to minimize load- ing on the input signal and can accept up to 10 v peak. the ds-11802 is pin programmable for gains of 0.5, 1.0, and 2.0. two registers for the input of the 16-bit (cmos/ttl) natur- al binary angle data allow for compat- ibility with an 8-bit or 16-bit data bus. internally, the ds-11802 has a multi- plying digital-to-sin/cos converter consisting of two function generators and a quadrant select network. quadrant information is available from the two most significant bits (msbs). the two function generators use the remaining angular data along with the buffered reference voltage. similar to a multiplying dac (digital- to-analog converter), the ds-11802 uses high-accuracy resistive ladder networks and solid-state switching to control the attenuation of the refer- ence voltage. the output buffer ampli- fiers allow for up to 2 ma output drive. applications due to the high accuracy, high reliabil- ity, small size, low power consumption and mil-prf-38534 processing avail- able, the ds-11802 is suitable for industrial and military ground or avion- ic applications. possible applications include digital remote positioning, resolver angle simulation, flight train- ers, flight instrumentation, radar and navigational systems, and ppi dis- plays including moving target indica- tors. other applications are syn- chro/resolver system development and testing, and wraparound test of synchro/resolver-to-digital converters. features ? 28-pin ceramic ddip package ? 1 arc minute accuracy ? 0.03% radius accuracy ? microprocessor compatible - 8- and 16-bit ? double-buffered inputs ? pin-programmable gain - 0.5, 1.0 or 2.0 ? buffered reference input ? dc-coupled reference and outputs ? requires only 15 v power supplies ? ttl and cmos compatible ? pin-for-pin replacement for natels hdsc2306 9 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 10 19 25 gnd 20 23 24 21 28 26 27 v in gc1 gc2 reference conditioner bit16 (lsb) cos q sin q buffer amplifiers 16-bit high accuracy multiplying digital to sin / cos converter 16-bit holding register bit 1 (msb) q1 d d q16 ck 8-bit input register ck ck 8-bit input register input buffers Cv s +v s hbe (msb) b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 (lsb) b16 lbe ldc 22 tp1 ? 1996, 1999 data device corporation figure 1. ds-11802 block diagram
analog output gain control and phasing the ds-11802 is pin-programmable for gains of 0.5, 1.0 and 2.0. table 2 details the programming of gain control pins 23 (gc1) and 24 (gc2). when both pins are left unconnected or open, the gain of the converter is 2.0. the output signal would be: 2 vin sin q and 2 vin cos q . when gc2 is connected to gnd and gc1 is left open, the converter gain is 1.0. when gc1 is connected to gnd and gc2 is left open, the converter gain is 0.5. when looking at the equivalent gain circuit (see figure 2) the gain of the converter can be modified by adding a resistor between gc1 or gc2 and gnd. 2 8 msbs enter high byte input register. high byte register remains unaffected. 8 lsbs enter low byte input register. low byte register remains unaffected. data from input regis- ters transferred to holding register. data in holding regis- ter remains unaffected. logic 1 logic 0 logic 1 logic 0 logic 1 logic 0 register controls hbe (high byte enable) lbe (low byte enable) ldc (load converter) no external logic volt- ages required. cmos transient pro- tected. for less than 16 bits, unused pins can be left unconnected. pins not used can be left unconnected. digital inputs logic voltage levels logic 0 logic 1 loading input current data bits (b1-b16) hbe, lbe, ldc analog outputs sin q cos q converter gain (k) radius accuracy output current output impedance zero offset (dc) offset drift output settling time op amp buffer 0 to 10 vp ac or dc dc to 1000 hz 1 m w min analog input (v in ) voltage frequency range input resistance 16 bits 4 arc-minutes 2 arc-minutes 1 arc-minutes digital angular resolution accuracy remarks value parameter table 1. ds-11802 specifications for 10 v pk output. 15 v dc 10% 25 ma max 80 db typ power supplies supply voltages (vs) supply current supply rejection before data transfer. before input data changes. 200 h sec min 200 h sec min register controls (continued) data set-up time data hold time absolute maximum ratings reference input: -vs to +vs power supply voltage (vs): 18 v dc digital inputs: -0.3 v dc to +6.5 v dc physical characteristics type size weight remarks value parameter table 1. ds-11802 specifications (continued) bit 1 = msb, bit 16 = lsb accuracy applies over operating temperature range. k ? v in ? sin q k ? v in ? cos q 0.5 0.2% 1.0 0.2% 2.0 0.2% 0.1% 2 ma rms < 1 ohm 10 mv typical 25 mv max 25 m v/c 30 m sec max to accuracy of con- verter 10 vp ac or dc 10 vp ac or dc pin 23 connected to gnd. pin 24 no connection. pin 24 connected to gnd. pin 23 no connection. pin 23 and 24 floating. guaranteed, but not tested. op amp output. for any digital step change. 28 pin double dip 0.6 x 1.4 x 0.2 in. (15 x 36 x 5) mm 0.5 oz (15 gm) max gc1 (pin 23) gc2 (pin 24) gain (k) open open 2.0 gnd open 0.5 open gnd 1.0 table 2. gain control pins 0c to +70c -40c to +85c -55c to +125c -65c to +135c -0.3 v dc to 0.8 v dc 2.4 v dc to 5.5 v dc 0.1 ttl load 15 m a typ, active pull-down to gnd -15 m a typ, active pull-up to internal logic supply tempeature ranges operating case -3xx and -8xx -5xx and -2xx -1xx and -4xx storage users are cautioned against using a large value resistor to modify the gain, as the temperature coefficient of the exter- nal resistor will not be matched with the tcr of the internal resistor. the internal gain resistors have an accuracy of 0.05%. figure 3 illustrates the output phasing between the reference voltage vin and the analog output signals as a function of the digital angle and the converter gain k (0.5, 1.0, or 2.0).
data transfer from an 8-bit data bus applications with a 8-bit data bus require two-byte loading of the digital input (see figure 4). figure 5 shows the timing for two-byte data transfers. digital interface the ds-11802 has double-buffered input registers which allow easy implementation of an interface with 8-bit or 16-bit data buses. the ds-11802 can also be set up for asynchronous data inputs. if the lbe, hbe and ldc input pins are left open, the internal pull-up circuitry will set these pins to a high state and the information at the data inputs (b1-b16) is continuously convert- ed to sin q and cos q at the analog outputs. for applications requiring less than 16-bit resolution, the unused data bit pins can be left open. the data bits (b1-b16) are internally pulled-down to apply a logic 0 to unconnected data inputs. 3 90 180 270 360 q (degrees) in phase with v in 0 sin q cos q - v max + v max sin output = k ? vin ? (1+n) sin q cos output = k ? vin ? (1+n) cos q where: k is the gain of the converter. n is the scale factor variation as a function of digital angle( 0.2%) figure 3. output phasing 1 12 4 3 2 5 6 7 8 11 13 14 15 16 17 18 lbe hbe ldc load converter load msbs load lsbs ds-11802 (msb) (lsb) d7 d1 d2 d3 d4 d5 d6 d0 hbe lbe data bus 19 9 10 24 22 20 23 21k 2.33k 2.92k 8.75k internal reference gc2 gc1 v in tp1 figure 2. reference conditioner figure 4. data transfer from 8-bit bus pulse width 800 ns min pulse width 600ns min data transferred to holding registers 8 msbs transferred to input registers data changing data steady (lsbs) data set up data hold 200ns min (msbs) 8 lsbs transferred to input registers data lbe ldc hbe data hold 200 ns min pulse width 800 ns min figure 5. timing for 8-bit bus transfer
digital-to-resolver/synchro converters the output of the ds-11802 is a single-ended sin/cos. figure 8 illustrates a schematic for a 4-wire digital-to-resolver converter (s1, s2, s3, and s4) using external power amplifiers and transformers. figure 9 illustrates a schematic for 3-wire digital-to-synchro converter (s1, s2, and s3) using an additional power stage and external transformers. a benefit to the designs shown in figures 8 and 9 is the abili- ty to keep the converters near the digital data and control sig- nals, and to mount the power amplifiers and transformers in a better thermal location. this would isolate heat dissipating cir- cuits from high-accuracy computing circuits. 1. the ldc is low (logic 0) so that the contents of the holding reg- ister are latched and will remain unaffected by the changes on the input registers. 2. when the lbe is set high (logic 1) the 8 lsbs (b9-b16) are transferred to the low byte. the lbe must remain high for a min- imum of 800 nsec after the data is stable. the data should remain stable for 200 nsec after the lbe is set low (logic 0). 3. when the hbe is set high (logic 1) the 8 msbs (b1-b8) are transferred to the low byte. the hbe must remain high for a min- imum of 800 nsec after the data is stable. the data should remain stable for 200 nsec after the hbe is set low (logic 0). 4. when the ldc is set high (logic 1) the data is transferred from the two input registers to the holding register. the ldc should be held high for 600 nsec minimum. once the ldc is set low, the cycle can begin again. note: lbe, hbe, and ldc are level-actuated functions. refer to table 3 for bit values. 4 b1 b2 b3 b4 b5 b6 b13 b12 b11 b10 b9 b8 b7 b14 b15 b16 (lsb) (msb) 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 ds-11802 lbe hbe ldc load converter not connected or load data pulse 10 9 19 figure 6. data transfer from 16-bit bus 600 ns min data transferred to holding registers data changing data steady all 16 bits data transferred to input registers data hbe lbe ldc 200 ns min 200 ns min 800 ns min figure 7. timing for 16-bit bus transfer note: hbe enables the msbs and lbe enables the lsbs. 10800.0 5400.0 2700.0 1350.0 675.0 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 180.0 90.0 45.0 22.5 11.25 5.625 2.813 1.406 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 1 msb 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 min/bit deg/bit bit table 3. digital angle inputs data transfer from a 16-bit data bus applications interfacing with a 16-bit data bus require only single byte loading (see figure 6). lbe and hbe are either uncon- nected or tied together and pulsed high to load data. as shown in the timing diagram (see figure 7) 200 nsec after the data has been stable, the ldc is set high (logic 1) to trans- fer the data to the holding register. since ldc is level actuated, it must remain high for the time specified (600 nsec).
low frequency sine wave oscillator the ds-11802 can be used to create a low frequency sine wave oscillator with very low distortion (see figure 10). the output amplitude is determined by the amplitude of the dc reference input and the gain control pin configuration. when using a 16-bit counter and a square wave of 65,536 hz (2n, where n = 16 bit resolution) the output will be at 1 hz. 5 reference input digital input ds-11802 16-bit counter dc reference (v ref ) square wave oscillator k v ref sin q sine wave output k v ref cos q quadrature output figure 10. low frequency sinewave oscillator ds-11802 sin q cos q 1:n s1 s3 s2 28 21 p.a. p.a. 1: ? 3 2 n r l r h 1:n v in digital angle q interface controls 20 r l r h 1:n v in digital angle q interface controls ds-11802 sin q cos q 1:n 1:n s3 s1 s2 s4 28 21 p.a. p.a. 20 figure 9. 3-wire digital-to-synchro converter figure 8. 4-wire digital-to-resolver converter power supply decoupling decoupling capacitors are recommended on the +vs and -vs . supplies. a 1 m f tantalum capacitor in parallel with a 0.01 m f ceramic capacitor should be mounted as close to the supply as possible.
6 figure 11. ds-11802 mechanical outline table 4. ds-11802 pinouts pin function pin function 1 b1 15 b13 2 b2 16 b14 3 b3 17 b15 4 b4 18 b16 5 b5 19 ldc 6 b6 20 v in 7 b7 21 cos q 8 b8 22 tp1 9 hbe 23 gc1 10 lbe 24 gc2 11 b9 25 gnd 12 b10 26 -vs 13 b11 27 +vs 14 b12 28 sin q 1.400 (35.56) .015 .18 (4.57) .594 (15.1) .600 (15.2) .010 (.254) .050 typ (1.25) .150 min (3.81) .050 (1.27) .015 .100 (2.54) .002 .020 (.51) .002 pin #1 i.d. .002 tolerances .xx = .02 ( .50) .xxx = .005 ( .25) notes: 1. case is electrically floating 2. pins are alloy 42 with gold plated 60 m inch min over 100 m inch nickel 3. case & lid are 91% pure alumina ceramic 4. dimensions shown in inches and (mm). 1 14 15 28 top view side view side view
ordering information ds-11802dx-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above accuracy: 3 = 4 minutes 4 = 2 minutes 5 = 1 minute process requirements*: 0 = standard ddc processing, no burn-in (see table below.) 2 = b* 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data frequency range: 4 = dc to 1 khz * for availability of fully compliant mil-prf-38534 parts, please contact the ddc office nearest you. **standard ddc processing with burn-in and full temperature test see table below. 7 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal 2009, 2010, 2017, and 2032 inspection condition(s) method(s) test mil-std-883 standard ddc processing
8 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. a-03/98-1m printed in the u.s.a. ilc data device corporation registered to iso 9001 file no. a5976 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7389 or 7413 headquarters - tel: (631) 567-5600 ext. 7389 or 7413, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com
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