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? products and specifications discussed herein are for evaluation and reference puroposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron's production and data sheet specifications. 1 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?2000, micron technology, inc. 16mb: 256k x 72 pipelined zbt sram advance ? 16mb zbt ? sram features ? high frequency and 100 percent bus utilization fast cycle times: 6ns, 7.5ns, and 10ns single +3.3v 5% or +2.5v 5% power supply (v dd ) separate +3.3v or +2.5v isolated output buffer supply (v dd q) advanced control logic for minimum control signal interface individual byte write controls may be tied low single r/w# (read/write) control pin cke# pin to enable clock and suspend operations three chip enables for simple depth expansion clock-controlled and registered addresses, data i/os and control signals internally self-timed, fully coherent write internally self-timed, registered outputs to eliminate the need to control oe# snooze mode for reduced-power standby common data inputs and data outputs linear or interleaved burst modes burst feature (optional) options marking* timing (access/cycle/mhz) 3.5ns/6ns/166 mhz -6 4.2ns/7.5ns/133 mhz -7.5 5ns/10ns/100 mhz -10 configurations 3.3v v dd , 3.3v or 2.5v i/o 256k x 72 mt55l256y72p 2.5v v dd , 2.5v i/o 256k x 72 mt55v256v72p package 221-pin fbga g 209-pin pbga h part number example: mt55l256y72pt-7.5 *part marking for the fbga device may be found on micron?s web site at http://www.micron.com/support . mt55l256y72p, mt55v256v72p 3.3v v dd , 3.3v or 2.5v i/o; 2.5v v dd 2.5v i/o 221-pin fbga 209-pin pbga general description the micron ? zero bus turnaround ? (zbt ? ) sram family employs high-speed, low-power cmos designs using an advanced cmos process. micron?s 16mb zbt srams integrate a 256k x 72 sram core with advanced synchronous peripheral cir- cuitry and a 2-bit burst counter. these srams are optimized for 100 percent bus utilization, eliminating any turnaround cycles for read to write, or write to read, transitions. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (clk). the synchronous inputs include all addresses, all data inputs, chip enable (ce#), two addi- tional chip enables for easy depth expansion (ce2, ce2#), cycle start input (adv/ld#), synchronous clock enable (cke#), byte write enables (bwa#, bwb#, bwc#, bwd#, bwe#, bwf#, bwg#, and bwh#) and read/write (r/w#). asynchronous inputs include the output enable (oe#, which may be tied low for control signal mini-
2 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?2000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram general description (continued) mization), clock (clk) and snooze enable (zz, which may be tied low if unused). there is also a burst mode pin (mode) that selects between interleaved and linear burst modes. mode may be tied high, low or left unconnected if burst is unused. the data-out (q), enabled by oe#, is registered by the rising edge of clk. write cycles can be from one to four bytes wide as controlled by the write control inputs. all read, write and deselect cycles are initiated by the adv/ld# input. subsequent burst addresses can be internally generated as controlled by the burst advance pin (adv/ld#). use of burst mode is optional. it is allowable to give an address for each individual read and write cycle. burst cycles wrap around after the fourth access from a base address. to allow for continuous, 100 percent use of the data bus, the pipelined zbt sram uses a late late write cycle. for example, if a write cycle begins in clock cycle one, the address is present on rising edge one. byte writes need to be asserted on the same cycle as the address. the data associated with the address is required two cycles later, or on the rising edge of clock cycle three. address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during a byte write cycle, bwa# controls dqa pins; bwb# controls dqb pins; bwc# controls dqc pins; bwd# controls dqd pins; bwe# controls dqe pins; bwf# controls dqf pins; bwg# controls dqg pins; and bwh# controls dqh pins. cycle types can only be defined when an address is loaded, i.e., when adv/ld# is low. parity/ecc bits are only available on the x36 versions. micron?s 16mb zbt srams operate from a +3.3v or +2.5v v dd power supply, and all 3.3v v dd inputs and outputs are lvttl-compatible. users can implement either a 3.3v or 2.5v i/o for the +3.3v v dd or a 2.5v i/o for the +2.5v v dd . the device is ideally suited for systems requiring high bandwidth and zero bus turn- around delays. please refer to micron?s web site ( www.micron.com/ sram ) for the latest data sheet. k mode 18 bwa# bwb# bwc# bwd# r/w# ce# ce2 ce2# oe# read logic dqs d a t a s t e e r i n g o u t p u t b u f f e r s 256k x 8 x 4 (x72) memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic 18 18 16 18 burst logic sa0' sa1' d1 d0 q1 q0 sa0 sa1 k 18 adv/ld# adv/ld# e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk cke# write drivers sa0, sa1, sa note: functional block diagrams illustrate simplified device operation. see truth table, pin descriptions and timing diagrams for detailed information. functional block diagram 256k x 72
3 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram pin layout (top view) 221-pin fbga note : pins 11b and 3b reserved for address expansion; 32mb and 64mb respectively. 12345678910111213 a dqa dqa v ss sa ce2 sa adv/ sa ce2# sa v ss dqe dqe ld# b dqa dqa v dd q bwb# bwa# nc bwe# sa bwe# bwf# v dd dqe dqe c dqa dqa v ss bwc# bwd# nc ce# nc bwh# bwg# v ss dqe dqe d dqa dqa dqa v dd nc nc oe#/g# nc nc v dd q dqe dqe dqe e dqb dqb dqb v ss v ss v ss nc v ss v ss v ss dqf dqf dqf f dqb dqb v dd qv dd v dd v dd nc v dd v dd v dd v dd q dqf dqf g dqb dqb v ss v ss v ss v ss nc v ss v ss v ss v ss dqf dqf h dqb dqb v dd qv dd v dd v dd v dd v dd v dd v dd v dd q dqf dqf j nc nc clk nc v ss v ss cke# v ss v ss nc nc nc nc k dqc dqc v dd qv dd v dd v dd v dd v dd v dd v dd v dd dqg dqg l dqc dqc v ss v ss v ss v ss v ss v ss v ss v ss v ss dqg dqg m dqc dqc v dd qv dd v dd v dd nc v dd v dd v dd v dd dqg dqg n dqc dqc dqc v ss v ss v ss zz v ss v ss v ss dqg dqg dqg p dqd dqd dqd v dd nc nc mode/ nc nc v dd dqh dqh dqh lbo# r dqd dqd v ss nc sa nc sa nc sa nc v ss dqh dqh t dqd dqd v dd q sa sa sa sa1 sa sa sa v dd q dqh dqh u dqd dqd v ss tms tdi sa sa0 sa tdo tck v ss dqh dqh
4 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram fbga pin descriptions x72 symbol type description 7r sa0 input synchronous address inputs: these inputs are registered and must 7p sa1 meet the setup and hold times around the rising edge of clk. sa0 3a, 4a, 10a, 11a, sa and sa1 are the two least significant bits (lsb) of the address field and 4b, 5b, 9b, 10b, 4p, set the internal burst counter if burst is desired. 5p, 9p, 10p, 4r, 5r, 9r, 10r 3f bwa# input synchronous byte write enables: these active low inputs allow 3g bwb# individual bytes to be written when a write cycle is active and must 3j bwc# meet the setup and hold times around the rising edge of clk. byte 3k bwd# writes need to be asserted on the same cycle as the address. bwa# 11f bwe# controls dqa pins; bwb# controls dqb pins; bwc# controls dqc pins; 11g bwf# bwd# controls dqd pins; bwe# controls dqe pins; bwf# controls dqf 11j bwg# pins; bwg# controls dqg pins; bwh# controls dqh pins. 11k bwh# 7b clk input clock: this signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock ? s rising edge. 6c ce# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). 6b ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. 6a ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. 9a oe# input output enable: this active low, asynchronous input enables the data (g#) i/o output drivers. g# is the jedec-standard term for oe#. 8a adv/ld# input synchronous address advance/load: when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when adv/ld# is high, r/w# is ignored. a low on adv/ld# clocks a new address at the clk rising edge. 8b cke# input synchronous clock enable: this active low input permits clk to propagate throughout the device. when cke is high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. 7a r/w# input read/write: this input determines the cycle type when adv/ld# is low and is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus-width writes occur if all byte write enables are low. 5a mode input mode: this input selects the burst sequence. a low on this pin selects (lbo#) linear burst. nc or high on this pin selects interleaved burst. do not alter input state while device is operating. lbo# is the jedec-standard term for mode.
5 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram fbga pin descriptions (continued) x72 symbol type description 8r tms input ieee 1149.1 test inputs: jedec-standard 2.5v i/o levels. these pins may 8p di be left not connected if the jtag function is not used in the circuit. 6r tck (a) 1a, 2a, 1b, 2b, dqa input/ sram data i/os: byte ? a ? is associated with dqa pins; byte ? b ? is 1c, 2c, 3c, 1d, 2d output associated with dqb pins; byte ? c ? is associated with dqc pins; byte (b) 3d, 1e, 2e, 3e, dqb ? d ? is associated with dqd pins; byte ? e ? is associated with dqe pins; 1f, 2f, 1g, 2g, 1h byte ? f ? is associated with dqf pins; byte ? g ? is associated with dqg (c) 2h, 1j, 2j, 1k, dqc pins; byte ? h ? is associated with dqh pins. input data must meet setup 2k, 1l, 2l, 3l, 1m and hold times around the rising edge clk. (d) 2m, 3m 1n, 2n, dqd 3n, 1p, 2p, 1r, 2r (e) 12a, 13a, 12b, dqe 13b, 11c, 12c, 13c, 11d, 12d (f) 13d, 11e, 12e, dqf 13e, 12f, 13f, 12g, 13g, 12h (g) 13h, 12j, 13j, dqg 12k, 13k, 11l, 12l, 13l, 11m (h) 12m, 13m, 11n, dqh 12n, 13n, 12p, 13p, 12r, 13r 6p tdo output ieee 1149.1 test output: jedec-standard 2.5v i/o level. 7c, 7d, 7e, 7f, 7g, v dd supply power supply: see dc electrical characteristics and operating 5h, 6h, 7h, 8h, 9h, conditions for range. 7j, 7k, 7l, 7m, 7n 4c, 5c, 9c, 10c, 4d, v dd q supply isolated output buffer supply: see dc electrical characteristics and 10d, 4e, 10e, 4f, operating conditions for range. 10f, 4g, 10g, 4h, 10h, 4j, 10j, 4k, 10k, 4l, 10l, 4m, 10m, 4n, 5n, 9n, 10n 5d, 6d, 8d, 9d, 5e, v ss supply ground: gnd. 6e, 8e, 9e, 5f, 6f, 8f, 9f, 5g, 6g, 8g, 9g, 5j, 6j, 8j, 9j, 5k, 6k, 8k, 9k, 5l, 6l, 8l, 9l, 5m, 6m, 8m, 9m 3b, 11b, 8c, 3h, nc ? no connect: these pins can be left floating or connected to gnd to 11h, 11p, 3r, 11r minimize thermal impedance. pins 11b and 3b are reserved for future address expansion; 32mb and 64mb respectively.
6 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram pin layout (top view) 209-pin bga 1234567891011 a dqg dqg sa ce2 sa adv/ld# sa ce2# sa dqb dqb b dqg dqg bwc# bwg# nc r/w# sa bwb# bwf# dqb dqb c dqg dqg bwh# bwd# nc ce# nc bwe# bwa# dqb dqb d dqg dqg v ss nc nc g#/oe# gw# nc v ss dqb dqb e dqpg dqpc v dd qv dd qv dd v dd v dd v dd qv dd q dqpf dqpb f dqc dqc v ss v ss v ss v ss v ss v ss v ss dqf dqf g dqc dqc v dd qv dd qv dd v dd v dd v dd qv dd q dqf dqf h dqc dqc v ss v ss v ss v ss v ss v ss v ss dqf dqf j dqc dqc v dd qv dd qv dd v dd v dd v dd qv dd q dqf dqf k nc nc clk nc v ss cke# v ss nc nc nc nc l dqh dqh v dd qv dd qv dd v dd v dd v dd qv dd q dqa dqa m dqh dqh v ss v ss v ss v dd v ss v ss v ss dqa dqa n dqh dqh v dd qv dd qv dd v dd v dd v dd qv dd q dqa dqa p dqh dqh v ss v ss v ss zz v ss v ss v ss dqa dqa r dqpd dqph v dd qv dd qv dd v dd v dd v dd qv dd q dqpa dqpe t dqd dqd v ss nc nc mode#/ nc nc v ss dqe dqe lbo u dqd dqd nc sa nc sa nc sa nc dqe dqe v dqd dqd sa sa sa sa1 sa sa sa dqe dqe w dqd dqd tms tdi sa sa0 sa tdo tck dqe dqe
7 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram pbga pin descriptions x72 symbol type description 6w sa0 input synchronous address inputs: these inputs are registered and must 6v sa1 meet the setup and hold times around the rising edge of clk. 3a, 5a, 7a, 9a, 7b, sa sa0 and sa1 are the two least significant bits (lsb) of the address 4u, 6u, 8u, 3v, 9v, field and set the internal burst counter if burst is desired. 5w, 7w 9c bwa# input synchronous byte write enables: these active low inputs allow 8b bwb# individual bytes to be written when a write cycle is active and must 3b bwc# meet the setup and hold times around the rising edge of clk. byte 4c bwd# writes need to be asserted on the same cycle as the address. bwa# 8c bwe# controls dqa pins; bwb# controls dqb pins; bwc# controls dqc pins; 9b bwf# bwd# controls dqd pins. 4b bwg# 3c bwh# 3k clk input clock: this signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock ? s rising edge. 6c ce# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). 8a ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). this input can be used for memory depth expansion. 4a ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). this input can be used for memory depth expansion. 6d oe# input output enable: this active low, asynchronous input enables the data (g#) i/o output drivers. g# is the jedec-standard term for oe#. 6a adv/ld# input synchronous address advance/load: when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when adv/ld# is high, r/w# is ignored. a low on adv/ld# clocks a new address at the clk rising edge. 6k cke# input synchronous clock enable: this active low input permits clk to propagate throughout the device. when cke is high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. 6p zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. this pin has an internal pull-down and can be floating. 3w tms input ieee 1149.1 test inputs: jedec-standard 2.5v i/o levels. these pins may 4w tdi be left not connected if the jtag function is not used in the circuit. 9w tck
8 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram pbga pin descriptions (continued) x72 symbol type description 6b r/w# input read/write: this input determines the cycle type when adv/ld# is low and is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus-width writes occur if all byte write enables are low. 6t mode input mode: this input selects the burst sequence. a low on this pin (lbo#) selects linear burst. nc or high on this pin selects interleaved burst. do not alter input state while device is operating. lbo# is the jedec- standard term for mode. 10l, 11l, 10m, 11m, dqa input/ sram data i/os: byte ? a ? is associated with dqa pins; byte ? b ? is 10n, 11n, 10p, 11p, output associated with dqb pins; byte ? c ? is associated with dqc pins; 10a, 11a, 10b, 11b, dqb byte ? d ? is associated with dqd pins. input data must meet setup 10c, 11c, 10d, 11d and hold times around the rising edge clk. 1f, 2f, 1g, 2g, 1h, dqc 2h, 1j, 2j 1t, 2t, 1u, 2u, 1v, dqd 2v, 1w, 2w 10t, 11t, 10u, 11u, dqe 10v, 11v, 10w, 11w 10f, 11f, 10g, 11g, dqf 10h, 11h, 10j, 11j 1a, 2a, 1b, 2b, dqg 1c, 2c, 1d, 2d, 1l, 2l, 1m, 2m, dqh 1n, 2n, 1p, 2p 10r dqpa nc/ these are parity pins which hold the parity bit information but have 11e dqpb i/o no parity logic. 2e dqpc 1r dqpd 11r dqpe 10e dqpf 1e dqph 2r dqph 5e, 6e, 7e, 5g, 6g, v dd supply power supply: see dc electrical characteristics and operating condi- 7g, 5j, 6j, 7j, 5l, 6l, tions for range. 7l, 5n, 6n, 7n, 5r, 6r, 7r 3e, 4e, 8e, 9e, 3g, v dd q supply isolated output buffer supply: see dc electrical characteristics and 4g, 8g, 9g, 3j, 4j, operating conditions for range. 8j, 9j, 3l, 4l, 8l, 9l, 3n, 4n, 8n, 9n, 3r, 4r, 8r, 9r 8w tdo output ieee 1149.1 test output: jedec-standard 2.5v i/o level.
9 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram pbga pin descriptions (continued) x72 symbol type description 3d, 9d, 3f, 4f, 5f, v ss supply ground: gnd. 6f, 7f, 8f, 9f, 3h, 4h, 5h, 6h, 7h, 8h, 9h, 5k, 7k, 3m, 4m, 5m, 7m , 8m, 9m, 3p, 4p, 5p, 7p, 8p, 9p, 3t, 9t 5b, 5c, 7c, 4d, 5d, nc ? no connect: these pins can be left floating or connected to gnd to 8d, 1k, 2k, 4k, 8k, minimize thermal impedance. 9k, 10k, 11k, 4t, 5t, 7t, 8t, 3u, 5u, 7u, 9u
10 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram interleaved burst address table (mode = nc or high) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 linear burst address table (mode = low) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 function r/w# bwa# bwb# bwc# bwd# bwe# bwf# bwg# bwh# read h x x xxxxxx write byte ? a ? l l hhhhhhh write byte ? b ? l h l hhhhhh write byte ? c ? l hh l hhhhh write byte ? d ? l hhh l hhhh write byte ? e ? l hhhh l hhh write byte ? f ? l hhhhh l hh write byte ? g ? l hhhhhh l h write byte ? h ? l hhhhhhh l partial truth table for read/write commands (x72) note: pins 11b and 3b reserved for address expansion; 32mb and 64mb respectively.
11 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram state diagram for zbt sram note: 1. a stall or ignore clock edge cycle is not shown in the above diagram. this is because cke# high only blocks the clock (clk) input and does not change the state of the device. 2. states change on the rising edge of the clock (clk). deselect begin read burst read begin write ds ds ds burst write read ds write write burst read write read burst burst read burst ds write key: command ds read write burst operation deselect new read new write burst read, burst write or continue deselect burst read write
12 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram truth table (notes 5-10) address adv/ operation used ce# ce2# ce2 zz ld# r/w# bwx oe# cke# clk dq notes deselect cycle none h x x l l x x x l l h high-z deselect cycle none x h x l l x x x l l h high-z deselect cycle none x x l l l x x x l l h high-z continue deselect cycle none x x x l h x x x l l h high-z 1 read cycle external l l h l l h x l l l hq (begin burst) read cycle next x x x l h x x l l l h q 1, 11 (continue burst) nop/dummy read external l l h l l h x h l l h high-z 2 (begin burst) dummy read next x x x l h x x h l l h high-z 1, 2, (continue burst) 11 write cycle external l l h l l l l x l l hd 3 (begin burst) write cycle next x x x l h x l x l l h d 1, 3, (continue burst) 11 nop/write abort none l l h l l l h x l l h high-z 2, 3 (begin burst) write abort next x x x l h x h x l l h high-z 1, 2, (continue burst) 3, 11 ignore clock edge current x x x l x x x x h l h ? 4 (stall) snooze mode none x x x h x x x x x x high-z note: 1. continue burst cycles, whether read or write, use the same control inputs. the type of cycle performed (read or write) is chosen in the initial begin burst cycle. a continue deselect cycle can only be entered if a deselect cycle is executed first. 2. dummy read and write abort cycles can be considered nops because the device performs no external operation. a write abort means a write command is given, but no operation is performed. 3. oe# may be wired low to minimize the number of control signals to the sram. the device will automatically turn off the output drivers during a write cycle. oe# may be used when the bus turn-on and turn-off times do not meet an application ? s requirements. 4. if an ignore clock edge command occurs during a read operation, the dq bus will remain active (low-z). if it occurs during a write cycle, the bus will remain in high-z. no write operations will be performed during the ignore clock edge cycle. 5. x means ? don ? t care. ? h means logic high. l means logic low. bwx = h means all byte write signals (bwa#, bwb#, bwc#, bwd#, bwe#, bwf#, bwg#, and bwh#) are high. bwx = l means one or more byte write signals are low. 6. bwa# enables writes to byte ? a ? (dqa pins); bwb# enables writes to byte ? b ? (dqb pins); bwc# enables writes to byte ? c ? (dqc pins); bwd# enables writes to byte ? d ? (dqd pins); bwe# enables writes to byte ? e ? (dqe pins); bwf# enables writes to byte ? f ? (dqf pins); bwg# enables writes to byte ? g ? (dqg pins); bwh# enables writes to byte ? h ? (dqh pins). 7. all inputs except oe# and zz must meet setup and hold times around the rising edge (low to high) of clk. 8. wait states are inserted by setting cke# high. 9. this device contains circuitry that will ensure that the outputs will be in high-z during power-up. 10. the device incorporates a 2-bit burst counter. address wraps to the initial address every fourth burst cycle. 11. the address counter is incremented for all continue burst cycles.
13 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram 3.3v v dd , absolute maximum ratings* voltage on v dd supply relative to v ss ............................................... -0.5v to +4.6v voltage on v dd q supply relative to v ss ................................................... -0.5v to v dd v in .............................................. -0.5v to v dd q + 0.5v storage temperature (plastic) ............ -55c to +150c junction temperature** ................................... +150c short circuit output current ........................... 100ma 2.5v v dd , absolute maximum ratings* voltage on v dd supply relative to v ss ............................................... -0.3v to +3.6v voltage on v dd q supply relative to v ss ................................................ -0.3v to +3.6v v in .............................................. -0.3v to v dd q + 0.3v storage temperature (plastic) ............ -55c to +150c junction temperature** ................................... +150c short circuit output current ........................... 100ma *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. see micron technical note tn-05-14 for more information. 3.3v v dd , 3.3v i/o dc electrical characteristics and operating conditions (0 c t a +70 c; v dd = +3.3v ?.165v, v dd q = +3.3v ?.165v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input high (logic 1) voltage dq pins v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 ? 3, 6 output leakage current output(s) disabled, il o -1.0 1.0 ? 0v v in v dd output high voltage i oh = -4.0ma v oh 2.4 ? v1, 4 output low voltage i ol = 8.0ma v ol ? 0.4 v 1, 4 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 3.135 v dd v1, 5 note: 1. all voltages referenced to v ss (gnd). 2. for 3.3v v dd : overshoot: v ih +4.6v for t t kc/2 for i 20ma undershoot: v il -0.7v for t t kc/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms for 2.5v v dd : overshoot: v ih +3.6v for t t kc/2 for i 20ma undershoot: v il -0.5v for t t kc/2 for i 20ma power-up: v ih +2.65v and v dd 2.375v for t 200ms 3. mode pin has an internal pull-up, and input leakage = ?0?. 4. the load used for v oh , v ol testing is shown in figure 2. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 5. v dd q should never exceed v dd . v dd and v dd q can be externally wired together to the same power supply. 6. ms# pin has an internal pull-down , and input leakage = ?0?.
14 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram 3.3v v dd , 2.5v i/o dc electrical characteristics and operating conditions (0 c t a +70 c; v dd = +3.3v ?.165v; v dd q = ?.125v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q 1.7 v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 ? 3, 4 output leakage current output(s) disabled, il o -1.0 1.0 ? 0v v in v dd q (dqx) output high voltage i oh = -2.0ma v oh 1.7 ? v1 i oh = -1.0ma v oh 2.0 ? v1 output low voltage i ol = 2.0ma v ol ? 0.7 v 1 i ol = 1.0ma v ol ? 0.4 v 1 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 2.375 2.625 v 1 2.5v v dd , 2.5v i/o dc electrical characteristics and operating conditions (0 c t a +70 c; v dd = +3.3v ?.165v; v dd q = +2.5v ?.125v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q 1.7 v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 ? 3, 4 output leakage current output(s) disabled, il o -1.0 1.0 ? 0v v in v dd q (dqx) output high voltage i oh = -2.0ma v oh 1.7 ? v1 i oh = -1.0ma v oh 2.0 ? v1 output low voltage i ol = 2.0ma v ol ? 0.7 v 1 i ol = 1.0ma v ol ? 0.4 v 1 supply voltage v dd 2.375 3.625 v 1 isolated output buffer supply v dd q 2.375 3.625 v 1 note: 1. all voltages referenced to v ss (gnd). 2. for 3.3v v dd : overshoot: v ih +4.6v for t t kc/2 for i 20ma undershoot: v il -0.7v for t t kc/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms for 2.5v v dd : overshoot: v ih +3.6v for t t kc/2 for i 20ma undershoot: v il -0.5v for t t kc/2 for i 20ma power-up: v ih +2.65v and v dd 2.375v for t 200ms 3. mode pin has an internal pull-up, and input leakage = ?0?. 4. ms# pin has an internal pull-down , and input leakage = ?0?.
15 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram fbga thermal resistance description conditions symbol typ units notes thermal resistance test conditions follow standard test methods ja tbd c/w 1 (junction to ambient) and procedures for measuring thermal thermal resistance impedance, per eia/jesd51. jc tbd c/w 1 (junction to top of case) note: 1. this parameter is sampled. fbga capacitance description conditions symbol typ max units notes control input capacitance t a = 25 c; f = 1 mhz c i tbd tbd pf 1 input/output capacitance (dq) v dd = 3.3v c o tbd tbd pf 1 address capacitance c a tbd tbd pf 1 clock capacitance c ck tbd tbd pf 1 pbga capacitance description conditions symbol typ max units notes control input capacitance t a = 25 c; f = 1 mhz c i tbd tbd pf 1 input/output capacitance (dq) v dd = 3.3v c o tbd tbd pf 1 address capacitance c a tbd tbd pf 1 clock capacitance c ck tbd tbd pf 1 pbga thermal resistance description conditions symbol typ units notes thermal resistance test conditions follow standard test methods ja tbd c/w 1 (junction to ambient) and procedures for measuring thermal thermal resistance impedance, per eia/jesd51. jc tbd c/w 1 (junction to top of case) thermal resistance jc tbd c/w 1 (junction to pins)
16 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram note: 1. if v dd = +3.3v, then v dd q = +3.3v or +2.5v. if v dd = +2.5v, then v dd q = +2.5v. voltage tolerances: +3.3v ?.165 or +2.5v ?.125v for all values of v dd and v dd q. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. ? device deselected ? means device is in a deselected cycle as defined in the truth table. ? device selected ? means device is active (not in deselected mode). 4. typical values are measured at 3.3v, 25 c and 10ns cycle time. i dd operating conditions and maximum limits (note 1) (0 c t a +70 c) description conditions symbol typ -6 -7.5 -10 units notes power supply device selected; all inputs v il current: or v ih ; cycle time t kc (min); i dd tbd 475 425 325 ma 2, 3, 4 operating v dd = max; outputs open power supply device selected; v dd = max; current: idle cke# v ih ;i dd 1 tbd 32 29 24 ma 2, 3, 4 all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 2 tbd 10 10 10 ma 3, 4 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or v ih ;i sb 3 tbd 25 25 25 ma 3, 4 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; adv/ld# v ih ; all inputs v ss + 0.2 i sb 4 tbd 120 105 75 ma 3, 4 or v dd - 0.2; cycle time t kc (min) snooze mode zz v ih i sb 2 z tbd 10 10 10 ma 4 max
17 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram note: 1. measured as high above v ih and low below v il . 2. refer to technical note tn-55-01, ? designing with zbt srams, ? for a more thorough discussion of these parameters. 3. this parameter is sampled. 4. this parameter is measured with output loading as shown in figure 2 for 3.3v i/o and figure 4 for 2.5v i/o. 5. transition is measured ?00mv from steady state voltage. 6. oe# can be considered a ? don ? t care ? during writes; however, controlling oe# can help fine-tune a system for turnaround timing. 7. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when they are being registered into the device. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when adv/ld# is low to remain enabled. 8. test conditions as specified with output loading as shown in figure 1 for 3.3v i/o (v dd q = +3.3v ?.165v) and figure 3 for 2.5v i/o (v dd q = +2.5v +0.4v/-0.125v). 9. a write cycle is defined by r/w# low having been registered into the device at adv/ld# low. a read cycle is defined by r/w# high with adv/ld# low. both cases must meet setup and hold times. 10. if v dd = +3.3v, then v dd q = +3.3v or +2.5v. if v dd = +2.5v, then v dd q = +2.5v. voltage tolerances: +3.3v ?.165 or +2.5v ?.125v for all values of v dd and v dd q. ac electrical characteristics (notes 6, 8, 9, 10) (0 c t a +70 c)(original zbt mode: ms# = high) -6 -7.5 -10 description symbol min max min max min max units notes clock clock cycle time t khkh 6.0 7.5 10 ns clock frequency f kf 166 133 100 mhz clock high time t khkl 1.8 2.2 3.2 ns 1 clock low time t klkh 1.8 2.2 3.2 ns 1 output times clock to output valid t khqv 3.5 4.2 5.0 ns clock to output invalid t khqx 1.5 1.5 1.5 ns 2 clock to output in low-z t khqx1 1.5 1.5 1.5 ns 2, 3, 4, 5 clock to output in high-z t khqz 1.5 3.0 1.5 3.0 1.5 3.3 ns 2, 3, 4, 5 oe# to output valid t glqv 3.5 4.2 5.0 ns 6 oe# to output in low-z t glqx 0 0 0 ns 2, 3, 4, 5 oe# to output in high-z t ghqz 3.5 4.2 5.0 ns 2, 3, 4, 5 setup times address t avkh 1.5 1.7 2.0 ns 7 clock enable (cke#) t evkh 1.5 1.7 2.0 ns 7 control signals t cvkh 1.5 1.7 2.0 ns 7 data-in t dvkh 1.5 1.7 2.0 ns 7 hold times address t khax 0.5 0.5 0.5 ns 7 clock enable (cke#) t khex 0.5 0.5 0.5 ns 7 control signals t khcx 0.5 0.5 0.5 ns 7 data-in t khdx 0.5 0.5 0.5 ns 7
18 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram q 50 v = 1.5v z = 50 o t figure 1 q 351 317 5pf +3.3v figure 2 3.3v v dd , 3.3v i/o ac test conditions input pulse levels ................. v ih = (v dd /2.2) + 1.5v .................... v il = (v dd /2.2) - 1.5v input rise and fall times ..................................... 1ns input timing reference levels ..................... v dd /2.2 output reference levels ............................ v dd q/2.2 output load ............................. see figures 1 and 2 load derating curves micron 256k x 72 zbt sram timing is dependent upon the capacitive loading on the outputs. consult the factory for copies of i/o current versus voltage curves. q 50 ? v = 1.25v z = 50 ? o t figure 3 q 225 ? 225 ? 5pf +2.5v figure 4 3.3v v dd , 2.5v i/o ac test conditions input pulse levels ............. v ih = (v dd /2.64) + 1.25v ................ v il = (v dd /2.64) - 1.25v input rise and fall times ..................................... 1ns input timing reference levels ................... v dd /2.64 output reference levels ............................... v dd q/2 output load ............................. see figures 3 and 4 3.3v i/o output load equivalents 2.5v i/o output load equivalents 2.5v v dd , 2.5v i/o ac test conditions input pulse levels .................. v ih = (v dd /2) + 1.25v ..................... v il = (v dd /2) - 1.25v input rise and fall times ..................................... 1ns input timing reference levels ........................ v dd /2 output reference levels ............................... v dd q/2 output load ............................. see figures 3 and 4
19 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram snooze mode snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is reduced to i sb 2 z . the duration of snooze mode is dictated by the length of time the zz pin is in a high state. after the device enters snooze mode, all inputs except zz become disabled and all outputs go to high-z. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb 2 z is guaran- teed after the time t zzi is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed. similarly, when exiting snooze mode during t rzz, only a deselect or read cycle should be given. snooze mode electrical characteristics description conditions symbol min max units notes current during snooze mode zz v ih i sb 2z 10 ma zz active to input ignored t zz 0 2( t khkh) ns 1 zz inactive to input sampled t rzz 0 2( t khkh) ns 1 zz active to snooze current t zzi 2( t khkh) ns 1 zz inactive to exit snooze current t rzzi 0 ns 1 snooze mode waveform t zz i supply clk zz t rzz all inputs (except zz) don ? t care i isb2z t zzi t rzzi outputs (q) high-z deselect or read only note: 1. this parameter is sampled.
20 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram read/write timing for original zbt write d(a1) 123 456789 clk t khkh t klkh t khkl 10 ce# t khcx t cvkh r/w# cke# t khex t evkh bwx# adv/ld# t khax t avkh address a1 a2 a3 a4 a5 a6 a7 t khdx t dvkh dq command t khqx1 d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t khqx t khqz t khqv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe# t glqv t glqx t ghqz t khqx don ? t care undefined q(a6) q(a4+1) note: 1. for this waveform, zz is tied low. 2. burst sequence order is determined by mode (0 = linear, 1 = interleaved). burst operations are optional. 3. ce# represents three signals. when ce# = 0, it represents ce# = 0, ce2# = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. -6 -7.5 -10 symbol min max min max min max units t ghqz 3.5 4.2 5.0 ns t avkh 1.5 1.7 2.0 ns t evkh 1.5 1.7 2.0 ns t cvkh 1.5 1.7 2.0 ns t dvkh 1.5 1.7 2.0 ns t khax 0.5 0.5 0.5 ns t khex 0.5 0.5 0.5 ns t khcx 0.5 0.5 0.5 ns t khdx 0.5 0.5 0.5 ns read/write timing parameters -6 -7.5 -10 symbol min max min max min max units t khkh 6.0 7.5 10 ns t khkl 1.8 2.2 3.2 ns t klkh 1.8 2.2 3.2 ns t khqv 3.5 4.2 5.0 ns t khqx 1.5 1.5 1.5 ns t khqx1 1.5 1.5 1.5 ns t khqz 1.5 3.0 1.5 3.0 1.5 3.3 ns t glqv 3.5 4.2 5.0 ns t glqx 0 0 0 ns
21 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram nop, stall and deselect cycles read q(a3) 456 78910 clk ce# r/w# cke# bwx# adv/ld# address a3 a4 a5 d(a4) dq command a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don ? t care undefined t khqz t khqx a2 d(a1) q(a2) q(a3) note: 1. the ignore clock edge or stall cycle (clock 3) illustrates cke# being used to create a ? pause. ? a write is not performed during this cycle. 2. for this waveform, zz and oe# are tied low. 3. ce# represents three signals. when ce# = 0, it represents ce# = 0, ce2# = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. nop, stall and deselect timing parameters -6 -7.5 -10 sym min max min max min max units t khqx 1.5 1.5 1.5 ns t khqz 1.5 3.0 1.5 3.0 1.5 3.3 ns
22 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram ieee 1149.1 serial boundary scan (jtag) the 16mb sram incorporates a serial boundary scan test access port (tap). this port operates in accor- dance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 com- pliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature these pins can be left floating (unconnected), if the jtag function is not to be implemented. upon power- up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure 5. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signifi- cant bit (msb) of any register. (see figure 6.) figure 5 tap controller state diagram note: the 0/1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
23 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. (see figure 5.) the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see figure 6.) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in figure 5. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register* 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo *x = xxxtbd for the x72 configuration. figure 6 tap controller block diagram when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board- level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional pins on the sram. the x72 configuration has a xxxtbd-bit-long register. the boundary scan register is loaded with the con- tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the pins on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo.
24 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the in- struction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruc- tion. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1-compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time ( t cs plus t ch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other informa- tion described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instruc- tions are listed as reserved and should not be used. the other five instructions are described in detail be- low. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully imple- mented. the tap controller cannot be used to load address, data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the i/o ring when these instruc- tions are executed. instructions are loaded into the tap controller dur- ing the shift-ir state when the instruction register is placed between tdi and tdo. during this state, in- structions are shifted through the instruction register through the tdi and tdo pins. to execute the instruc- tion once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruc- tion. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/ preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state.
25 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don ? t care undefined tap timing tap ac electrical characteristics (notes 1, 2) (+20 c t j +100 c; +2.4v v dd +2.6v) description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 10 ns hold times tms hold t thmx 10 ns capture hold t ch 10 ns note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in figure 7. bypass when the bypass instruction is loaded in the in- struction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instruction are not implemented but are re- served for future use. do not use these instructions.
26 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram tap ac test conditions input pulse levels ...................................... v ss to 2.5v input rise and fall times ....................................... 1ns input timing reference levels ........................... 1.25v output reference levels .................................... 1.25v test load termination supply voltage .............. 1.25v tdo 1.25v 20pf z = 50 ? o 50 ? figure 7 tap ac output load equivalent tap dc electrical characteristics and operating conditions (+20 c t j +110 c; +2.4v v dd +2.6v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 ? output leakage current output(s) disabled, il o -5.0 5.0 ? 0v v in v dd q (dqx) output low voltage i olc = 100? v ol 1 0.2 v 1 output low voltage i olt = 2ma v ol 2 0.7 v 1 output high voltage |i ohc | = 100? v oh 1 2.1 v 1 output high voltage |i oht | = 2ma v oh 2 1.7 v 1 note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh/2 undershoot: v il (ac) -0.5v for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . control input signals (such as ld#, r/w#, etc.) may not have pulse widths less than t khkl (min) or operate at frequencies exceeding f kf (max).
27 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram identification register definitions instruction field 256k x 72 description revision number xxxx reserved for version number. (31:28) device depth 00111 defines depth of 256k or 512k words. (27:23) device width xxxxxtbd defines width of x72 bits. (22:18) micron device id xxxxxx reserved for future use. (17:12) micron jedec id 00000101100 allows unique identification of sram vendor. code (11:1) id register presence 1 indicates the presence of an id register. indicator (0) scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 68 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
28 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram boundary scan order (x72) bga bit# signal name pin id bga bit# signal name pin id
29 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram 221-pin fbga note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 9.60 12.80 15.00 ?.10 0.80 typ 0.80 typ 4.80 ?.05 13.00 ?.10 pin a1 id pin a1 id ball a1 mold compound: epoxy novolac substrate: plastic laminate 6.50 ?.05 6.40 ?.05 7.50 ?.05 1.20 max solder ball material: eutectic 63% sn, 37% pb or 62% sn, 36% pb, 2% ag solder ball pad: ? .33mm seating plane 0.85 ?.075 0.12 c c 0.45 post reflow 221x ? 0.40 pre-reflow 221x ? ball a13
30 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ? rev. 8/00 ?2000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 zbt and zero bus turnaround are trademarks of integrated device technology, inc., and the architecture is supported by micron technology, inc., and motorola inc. micron is a registered trademark and the micron logo and m logo are trademarks of micron technology, inc. 209-pin pbga note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. solder ball land pad is ?0.45mm. ? 0.65 +0.05 -0.10 typ 0.90 ?.10 0.56 ?.10 2.20 max 18.00 22.00 ?.20 14.00 ?.20 5.00 ?.05 7.00 ?.10 20.00 ?.10 a1 corner ball a1 3x 45? x 1.00 ball a11 pin a1 id a1 corner 10.00 1.00 .15 c 30 (typ) seating plane c l c l 9.00 ?.05 1.00 typ 12.00 ?.10 mold compound: epoxy novolac substrate: plastic laminate solder ball material: eutectic 63% sn, 37% pb solder ball pad: .45mm c c data sheet designation advance: this data sheet contains initial descriptions of products still under development.
31 16mb: 256k x 72 pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l256y72p.p65 ?rev. 8/00 ?000, micron technology, inc. advance 16mb: 256k x 72 pipelined zbt sram revision history added 209-pin pbgapin diagram, rev. 8/00, advance ............................................................................. j uly/16/01 changed 195-pin fbga to 221-pin fbga, rev. 8/00, advance ................................................................ aug/14/ 00 original document, rev. 5/00, advance .......................................................................................... .............. may/00

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