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x28lc512/x28lc513 1 obsolete product 512k x28lc512/x28lc513 64k x 8 bit 3.3 volt, byte alterable e 2 prom ?xicor, inc. 1991, 1995, 1996 patents pending characteristics subject to change without notice 3005-3.2 8/5/97 t2/c0/d0 ew features low v cc operation: v cc = 3.3v 10% access time: 150ns simple byte and page write ?elf-timed ?o erase before write ?o complex programming algorithms ?o overerase problem low power cmos: ?ctive: 25ma ?tandby: 150 a software data protection ?rotects data against system level inadvertant writes high speed page write capability highly reliable direct write cell ?ndurance: 10,000 write cycles ?ata retention: 100 years early end of write detection data polling ?oggle bit polling 3005 ill f04.1 3005 ill f03 two plcc and lcc pinouts ?28lc512 ?28lc010 e 2 prom pin compatible ?28lc513 ?ompatible with lower density e 2 proms description the x28lc512/513 is a low-power 64k x 8 e 2 prom, fabricated with xicor? proprietary, high performance, floating gate cmos technology. the x28lc512/513 features the jedec approved pinout for bytewide memo- ries, compatible with industry standard eproms. the x28lc512/513 supports a 128-byte page write operation, effectively providing a 39 s/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. the x28lc512/513 also features data polling and toggle bit polling, system software support schemes used to indicate the early completion of a write cycle. in addition, the x28lc512/513 supports the soft- ware data protection option. plcc x28lc512 (top view) a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 a 14 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 a 12 a 15 nc nc v cc we nc 232 6 1 5 43 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 14 21 30 x28lc513 (top view) a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 9 a 11 nc a 10 oe i/o 7 ce i/o 6 a 8 i/o 1 i/o 2 v ss nc i/o 3 i/o 4 i/o 5 a 7 a 12 a 14 a 15 v cc we a 13 232 6 1 5 43 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 21 14 30 plcc pin configurations 3005 ill f02.1 nc nc a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we nc a 14 a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/0 4 i/o 3 x28lc512 plastic dip a 11 a 9 a 8 a 13 a 14 nc nc nc we v cc nc nc nc nc a 15 a 12 a 7 a 6 a 5 a 4 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 nc nc v ss nc nc i/o 2 i/o 1 i/o 0 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 x28lc512 tsop 3005 ill f22.2
2 x28lc512/x28lc513 obsolete product pin descriptions addresses (a 0 ? 15 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable ( ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, power consumption is reduced. output enable ( oe ) the output enable input controls the data output buffers and is used to initiate read operations. data in/data out (i/o 0 ?/o 7 ) data is written to or read from the x28lc512/513 through the i/o pins. pin names symbol description a 0 ? 15 address inputs i/o 0 ?/o 7 data input/output we write enable ce chip enable oe output enable v cc 3.3v 10% v ss ground nc no connect 3005 pgm t01 write enable ( we ) the write enable input controls the writing of data to the x28lc512/513. 3005 ill f01 x buffers latches and decoder i/o buffers and latches y buffers latches and decoder control logic and timing 512k-bit e 2 prom array i/o 0 ?/o 7 data inputs/outputs ce oe v cc v ss a 7 ? 15 we a 0 ? 6 functional diagram
x28lc512/x28lc513 3 obsolete product device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control architecture elimi- nates bus contention in a system environment. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28lc512/513 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , which- ever occurs first. a byte write operation, once initiated, will automatically continue to completion, typically within 5ms. page write operation the page write feature of the x28lc512/513 allows the entire memory to be written in 2.5 seconds. page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the x28lc512/513 prior to the commencement of the internal programming cycle. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 7 through a 15 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the initial byte write cycle, the host can write an additional one to one hundred twenty- seven bytes in the same manner as the first byte was written. each successive byte load cycle, started by the we high to low transition, must begin within 100 s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100 s, the internal automatic programming cycle will commence. there is no page write window limitation. effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100 s. write operation status bits the x28lc512/513 provides the user two write opera- tion status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. figure 1. status bit assignment 5 tb dp 43210 i/o reserved t oggle bit data polling 3005 ill f11 data polling (i/o 7 ) the x28lc512/513 features data polling as a method to indicate to the host system that the byte write or page write cycle has completed. data polling allows a simple bit test operation to determine the status of the x28lc512/ 513, eliminating additional interrupt inputs or external hardware. during the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on i/o 7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will reflect true data. toggle bit (i/o 6 ) the x28lc512/513 also provides another method for determining when the internal write cycle is complete. during the internal programming cycle, i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device. when the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
4 x28lc512/x28lc513 obsolete product data polling i/o 7 figure 2a. data polling bus sequence figure 2b. data polling software flow 3005 ill f12 data polling can effectively halve the time for writing to the x28lc512/513. the timing diagram in figure 2a illustrates the sequence of events on the bus. the software flow diagram in figure 2b illustrates one method of implementing the routine. 3005 ill f13 write data save last data and address read last address io 7 compare? x28lc512 ready no yes writes complete? no yes ce oe we i/o 7 x28lc512 ready last write high z v ol v ih a 0 ? 15 an an an an an an v oh an
x28lc512/x28lc513 5 obsolete product the toggle bit i/o 6 figure 3a. toggle bit bus sequence figure 3b. toggle bit software flow 3005 ill f14 the toggle bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement data polling. this can be especially helpful in an array comprised of multiple x28lc512/513 memories that is frequently updated. toggle bit polling can also provide a method for status checking in multiprocessor applications. the timing diagram in figure 3a illustrates the sequence of events on the bus. the software flow diagram in figure 3b illustrates a method for polling the toggle bit. 3005 ill f15 load accum from addr n compare accum with addr n x28lc512 ready compare ok? no yes last write ce oe we i/o 6 x28lc512 ready v oh v ol last write high z * beginning and ending state of i/o 6 will vary. * *
6 x28lc512/x28lc513 obsolete product hardware data protection the x28lc512/513 provides three hardware features that protect nonvolatile data from inadvertent writes. noise protection? we pulse typically less than 10ns will not initiate a write cycle. write inhibit?olding either oe low, we high, or ce high will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. write cycle timing specifications must be observed concurrently. software data protection the x28lc512/513 offers a software controlled data protection feature. the x28lc512/513 is shipped from xicor with the software data protection not enabled; that is, the device will be in the standard operating mode. in this mode data should be protected during power-up/ -down operations through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. the x28lc512/513 can be automatically protected dur- ing power-up and power-down without the need for external circuits by employing the software data protec- tion feature. the internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the x28lc512/ 513 is also protected from inadvertent and accidental writes in the powered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. note: the data in the three-byte enable sequence is not written to the memory array. software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific ad- dresses. refer to figure 4a and 4b for the sequence. the three byte sequence opens the page write window enabling the host to write from one to one hundred twenty-eight bytes of data. once the page load cycle has been completed, the device will automatically be re- turned to the data protected state.
x28lc512/x28lc513 7 obsolete product note: all other timings and control pins are per page write timing requirements. ce we (v cc ) write protected v cc 0v data addr aa 5555 55 2aaa a0 5555 t blc max writes ok byte or p age t wc software data protection figure 4a. timing sequence?oftware data protect enable sequence followed by byte or page write figure 4b. write sequence for software data protection write last byte to last address write data 55 to address 2aaa write data a0 to address 5555 write data xx to any address after t wc re-enters data protected state write data aa to address 5555 optional byte/page load operation regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the x28lc512/513 will automatically disable further writes unless another command is issued to cancel it. if no further commands are issued the x28lc512/513 will be write protected during power-down and after any subse- quent power-up. the state of a 15 while executing the algorithm is don? care. note: once initiated, the sequence of write operations should not be interrupted. 3005 ill f16 3005 fhd f17
8 x28lc512/x28lc513 obsolete product ce we standard operating mode v cc d ata addr aa 5555 55 2aaa 80 5555 note: all other timings and control pins are per page write timing requirements. t wc aa 5555 55 2aaa 20 5555 resetting software data protection figure 5a. reset software data protection timing sequence figure 5b. software sequence to deactivate software data protection 3005 ill f18 in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an e 2 prom programmer, the following six step algo- rithm will reset the internal protection circuit. after t wc , the x28lc512/513 will be in standard operating mode. note: once initiated, the sequence of write operations should not be interrupted. write data 55 to address 2aaa write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 20 to address 5555 write data aa to address 5555 3005 fhd f19
x28lc512/x28lc513 9 obsolete product system considerations because the x28lc512/513 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where mul- tiple i/o pins share the same bus. to gain the most benefit it is recommended that ce be decoded from the address bus and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. because the x28lc512/513 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause transient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of the i/ os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be sup- pressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recom- mended that a 0.1 f high frequency ceramic capacitor be used between v cc and v ss at each device. depend- ing on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended that a 4.7 f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces. active supply current vs. ambient temperature i cc (rd) by temperature over frequency standby supply current vs. ambient temperature ?5 ?0 +125 0.1 0.11 0.12 0.13 0.14 ambient temperature ( c) i sb (ma) 3005 ill f26 0.08 +35 +80 v cc = 3.3v 0.09 ?5 ?0 +125 5 5.5 6 6.5 7.5 ambient temperature ( c) i cc (ma) 3005 ill f25 4 +35 +80 7 v cc = 3.3v 4.5 0 15 20 25 30 35 frequency (mhz) i cc rd (ma) 3005 ill f24 10 510 ?5? +25? +125? 15 40 3.3 v cc
10 x28lc512/x28lc513 obsolete product d.c. operating characteristics (over recommended operating conditions, unless otherwise specified.) limits symbol parameter min. max. units test conditions i cc v cc current (active) 25 ma ce = oe = v il , we = v ih , (cmos inputs) all i/o? = open, address inputs = 0.1xv cc /0.9xv cc levels @ f = 5mhz i sb v cc current (standby) 150 a oe = v il , ce = v cc ?0.3v (cmos inputs) all i/o? = open, other inputs = v ih i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc , ce = v cc v ll (1) input low voltage ? 0.6 v v ih (1) input high voltage 2 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 1ma v oh output high voltage 2.4 v i oh = ?00 a 3005 pgm t04.2 absolute maximum ratings* temperature under bias x28lc512/513 ............................. ?0 c to +85 c x28lc512i/x28lc513i .............. ?5 c to +135 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to v ss ....................................... ?v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300 c *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommend operating conditions temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c 3005 pgm t02 supply voltage limits x28lc512/513 3.3v 10% 3005 pgm t03.1 notes: (1) v il min. and v ih max. are for reference only and are not tested.
x28lc512/x28lc513 11 obsolete product power-up timing symbol parameter max. units t pur (2) power-up to read operation 100 s t puw (2) power-up to write operation 5 ms 3005 pgm t05 capacitance t a = +25 c, f = 1mhz, v cc = 3.3v symbol parameter max. units test conditions c i/o (2) input/output capacitance 10 pf v i/o = 0v c in (2) input capacitance 10 pf v in = 0v 3005 pgm t06.1 endurance and data retention parameter min. max. units endurance 10,000 cycles per byte data retention 100 years 3005 pgm t11 a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v 3856 pgm t07.1 mode selection ce oe we mode i/o power ll h read d out active lh lw rite d in active hx x standby and high z standby write inhibit xl x write inhibit xx h write inhibit 3005 pgm t08 note: (2) this parameter is periodically sampled and not 100% tested. equivalent a.c. load circuit symbol table wa veform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance 3005 ill f21.3 5v 2.66k ? 30pf 4.46k ? output
12 x28lc512/x28lc513 obsolete product read cycle limits x28lc512-15 x28lc512-20 x28lc512-25 x28lc513-15 x28lc513-20 x28lc513-25 symbol parameter min. max. min. max. min. max. units t rc read cycle time 150 200 250 ns t ce chip enable access time 150 200 250 ns t aa address access time 150 200 250 ns t oe output enable access time 80 80 80 ns t lz (3) ce low to active output 0 0 0 ns t olz (3) oe low to active output 0 0 0 ns t hz (3) ce high to high z output 50 50 50 ns t ohz (3) oe high to high z output 50 50 50 ns t oh output hold from 0 0 0 ns address change 3005 pgm t09.2 a.c. characteristics (over the recommended operating conditions, unless otherwise specified.) read cycle notes: (3) t lz min., t hz , t olz min., and tohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. 3005 fhd f05 t ce t rc address ce oe we data valid data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z
x28lc512/x28lc513 13 obsolete product write cycle limits symbol parameter min. max. units t wc (4) write cycle time 5 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 100 ns t oes oe high setup time 10 ns t oeh oe high hold time 10 ns t wp we pulse width 100 ns t wph we high recovery 100 ns t dv data valid 1 s t ds data setup 50 ns t dh data hold 0 ns t dw delay to next write 10 s t blc byte load cycle 0.20 100 s 3005 pgm t10.1 we controlled write cycle notes: (4) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum tim e the device requires to complete the internal write operation. 3005 ill f06 address t as t wc t ah t oes t dv t ds t dh t oeh ce we oe data in data out high z t cs t ch t wp data valid
14 x28lc512/x28lc513 obsolete product ce controlled write cycle 3005 ill f07 notes: (5) between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. (6) the timings shown above are unique to page write operations. individual byte load operations within the page write must conf orm to either the ce or we controlled write cycle timing. page write cycle address t as t oeh t wc t ah t oes t wph t cs t dv t ds t dh t ch ce we oe data in data out high z t cw data valid we oe (5) byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce *address (6) i/o *for each successive write within the page write operation, a 7 ? 15 should be the same or writes to an unknown address could occur. last byte 3005 ill f08.1
x28lc512/x28lc513 15 obsolete product data polling timing diagram (7) address a n d in =x d out =x d out =x t wc t oeh t oes a n a n ce we oe i/o 7 t dw 3005 ill f09 toggle bit timing diagram ce oe we i/o 6 t oes t dw t wc t oeh high z * * * starting and ending state of i/o 6 will vary, depending upon actual t wc . 3005 ill f10 note: (7) polling operations are by definition read cycles and are therefore subject to read cycle timings.
16 x28lc512/x28lc513 obsolete product packaging information 0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) typ. typ. 0.017 (0.43) 0.045 (1.14) x 45 0.300 (7.62) ref. 0.453 (11.51) 0.447 (11.35) typ. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) typ. 0.490 (12.45) pin 1 0.400 (10.16) ref. 0.553 (14.05) 0.547 (13.89) typ. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) typ. 0.590 (14.99) 3 typ. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) typ. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) seating plane 0.004 lead co ?planarity 3926 fhd f13 32-lead plastic leaded chip carrier package type j notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only
x28lc512/x28lc513 17 obsolete product packaging information 3926 fhd f25 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.160 (4.06) 0.125 (3.17) 0.625 (15.88) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 1.665 (42.29) 1.644 (41.76) 1.500 (38.10) ref. pin 1 index 0.160 (4.06) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.070 (17.78) 0.030 (7.62) 0.557 (14.15) 0.510 (12.95) 0.085 (2.16) 0.040 (1.02) 0 15 32-lead plastic dual in-line package type p typ. 0.010 (0.25)
18 x28lc512/x28lc513 obsolete product packaging information 3926 ill f39.2 note: 1. all dimensions are shown in millimeters (inches in parentheses). 0.50 0.04 (0.0197 0.0016) 0.30 0.05 (0.012 0.002) 14.80 0.05 (0.583 0.002) 1.30 0.05 (0.051 0.002) 0.17 (0.007) 0.03 (0.001) typical 40 places 15 eq. spc. @ 0.50 0.04 0.0197 0.016 = 9.50 0.06 (0.374 0.0024) overall t ol. non-cumulative solder pads footprint 10.058 (0.396) 9.957 (0.392) 12.522 (0.493) 12.268 (0.483) pin #1 ident. o 1.016 (0.040) o 0.762 (0.030) 1 0.965 (0.038) 1.143 (0.045) 0.889 (0.035) 0.127 (0.005) dp. 0.076 (0.003) dp. x 0.065 (0.0025) 14.148 (0.557) 13.894 (0.547) seating plane a 0.178 (0.007) 1.016 (0.040) seating plane 15 typ. 0.500 (0.0197) 1.219 (0.048) 0.254 (0.010) 0.152 (0.006) 0.432 (0.017) 0.813 (0.032) typ. 0.432 (0.017) 0.508 (0.020) typ. 0.152 (0.006) typ. 4 typ. detail a 40-lead thin small outline package (tsop) type t
x28lc512/x28lc513 19 obsolete product limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. rese rves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874, 967; 4,883,976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor? products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reaso nably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. ordering information device access time ?5 = 150ns ?0 = 200ns ?5 = 250ns temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package j = 32-lead plcc x28lc513 x x -x device access time ?5 = 150ns ?0 = 200ns ?5 = 250ns temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package j = 32-lead plcc p = 32-lead plastic dip t = 40-lead tsop x28lc512 x x -x

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