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1 ? fn8167.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copy right intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x9252 low power + quad 256-tap + 2-wi re bus + up/down interface quad digitally-controlled (xdcp?) potentiometer the x9252 integrates 4 digita lly controlled potentiometers (xdcp) on a monolithic cmos integrated circuit. the digitally controlled pot entiometers are implemented using 255 resistive elements in a series array. between each pair of elements are tap points connected to wiper terminals through switches. the position of each wiper on the array is controlled by the user through the up/down (u/d ) or 2-wire bus interface. the wiper of each potentiometer has an associated volatile wiper counter register (wcr) and four non-volatile data registers (drs) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. at power-up, the devi ce recalls the contents of the default data registers dr00, dr10, dr20, dr30, to the corresponding wcr. each dcp can be used as a thre e-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including the programming of bias voltages, the implementation of ladder networks, and three resistor programmable networks. features ? quad solid state potentiometer ? 256 wiper tap points-0.4% resolution ? 2-wire serial interface fo r write, read, and transfer operations of the potentiometer ? up/down interface for individual potentiometers ? wiper resistance: 40 ? typical ? non-volatile storage of wiper positions ? power on recall. loads saved wiper position on power- up. ? standby current < 20a max ? maximum wiper current: 3ma ?v cc : 2.7v to 5.5v operation ?2.8k ? ,10k ? , 50k ? , 100k ? version of total pot resistance ? endurance: 100, 000 data changes per bit per register ? 100 yr. data retention ? 24-lead tssop pinout x9252 (24 ld tssop) top view ordering information ordering number rtotal package operating temperature range x9252yv24-2.7 2.8k ? 24-lead tssop 0c to 70c x9252yv24i-2.7 2.8k ? 24-lead tssop -40c to +85c x9252wv24-2.7 10k ? 24-lead tssop 0c to 70c x9252wv24i-2.7 10k ? 24-lead tssop -40c to +85c x9252uv24-2.7 50k ? 24-lead tssop 0c to 70c x9252uv24i-2.7 50k ? 24-lead tssop -40c to +85c x9252tv24-2.7 100k ? 24-lead tssop 0c to 70c x9252tv24i-2.7 100k ? 24-lead tssop -40c to +85c r h2 r h3 r w2 1 2 3 4 5 6 7 14 20 19 18 17 16 15 x9252 ds0 ds1 a0 r w3 u/d r l3 scl r l2 v ss r l1 r w0 cs r h0 r l0 r w1 r h1 v cc 8 9 10 13 wp a2 11 12 sda a1 24 23 22 21 data sheet march 23, 2005
2 fn8167.0 march 23, 2005 functional diagram power up, interface control and v cc v ss 2-wire r h0 r l0 dcp0 r w0 a1 sda scl cs u/d a2 ds0 ds1 wp wcr0 dr00 dr01 dr02 dr03 r h1 r l1 dcp1 r w1 wcr1 dr10 dr11 dr12 dr13 r h2 r l2 dcp2 r w2 wcr2 dr20 dr21 dr22 dr23 r h3 r l3 dcp3 r w3 wcr3 dr30 dr31 dr32 dr33 a0 interface up-down interface status pin descriptions tssop pin symbol brief description 1 ds0 dcp select for up/down interface. 2 a0 device address for 2-wire bus. 3 rw3 wiper terminal of dcp3. 4 rh3 high terminal of dcp3. 5 rl3 low terminal of dcp3. 6u/d increment/decrement for up/down interface. 7 vcc system supply voltage 8 rl0 low terminal of dcp0. 9 rh0 high terminal of dcp0. 10 rw0 wiper terminal of dcp0. 11 a2 device address for 2-wire bus. 12 wp hardware write protect 13 sda serial data input/output for 2-wire bus. 14 a1 device address for 2-wire bus. 15 rl1 low terminal of dcp1. 16 rh1 high terminal of dcp1. 17 rw1 wiper terminal dcp1. 18 vss system ground 19 cs chip select for up/down interface. 20 rw2 wiper terminal of dcp2. 21 rh2 high terminal of dcp2. 22 rl2 low terminal of dcp2. 23 scl serial clock for 2-wire bus. 24 ds1 dcp select for up/down interface. x9252
3 fn8167.0 march 23, 2005 absolute maximum ratings recommended operating conditions junction temperature under bias. . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c voltage at any digital interface pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v voltage at any dcp pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to v cc lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300 c i w (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (v cc )(note 4) limits . . . . . . . . . . . . . . . 2.7v to 5.5v caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog specifications over recommended operating conditions unless otherwise stated. symbol parameter test conditions min typ (note 4) max unit r total end to end resistance y, w, u, t versions respectively 2.8, 10, 50, 100 k ? end to end resistance tolerance -20 +20 % power rating 25c, each dcp 50 mw r total matching dcp to dcp resistance matching 0.75 2.0 % i w (note 5) wiper current see test circuit -3.0 +3.0 ma r w wiper resistance wiper current = 50 150 ? v term voltage on any dcp pin vss vcc v noise (note 5) ref: 1khz -120 dbv resolution 0.4 % absolute linearity (note 1) v(r h0 )=v(r h1 )=v(r h2 )=v(r h3 )=v cc v(r l0 )=v(r l1 )=v(r l2 )=v(r l3 )=v ss -1 +1 mi (note 3) relative linearity (note 2) -0.3 +0.3 mi (note 3) temperature coefficient of resistance (note 5) 300 ppm/ c ratiometric temperature (note 5) coefficient -20 +20 ppm/c c h /c l /c w potentiometer capacitance (note 5) see equivalent circuit 10/10/25 pf i ol leakage on dcp pins voltage at pin from v ss to v cc 0.1 10 a v cc r total dc electrical specifications over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min max units i cc1 v cc supply current (volatile write/read) f scl = 400khz;sda = open; (for 2-wire, active, read and volatile write states only) 3ma i cc2 v cc supply current (active) f scl = 200khz; (for u/d interface, increment, decrement) 3ma i cc3 v cc supply current (nonvolatile write) f scl = 400khz; sda = open; (for 2-wire, active, nonvolatile write state only) 5ma i sb v cc current (standby) v cc = +5.5v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) 20 a x9252
4 fn8167.0 march 23, 2005 i l leakage current, bus interface pins voltage at pin from v ss to v cc -10 10 a v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol sda pin output low voltage i ol = 3ma 0.4 v dc electrical specifications over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min max units endurance and data retention parameter min units minimum endurance 100,000 data changes per bit data retention 100 years capacitance symbol test test conditions max. units c in/out (note 5) input / output capacitance (sda) v out = 0v 8 pf c in (note 5) input capacitance (scl, wp , ds0, ds1, cs , u/d , a2, a1 and a0) v in = 0v 6 pf power-up timing symbol parameter max units t d (notes 5, 9) power up delay from v cc power up (v cc above 2.7v) to wiper position recall completed, and communication interfaces ready for operation. 2ms a.c. test conditions i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing threshold level v cc x 0.5 external load at pin sda 2.3k ? to v cc and 100pf to v ss 2-wire interface timing (s) symbol parameter min max units f scl clock frequency 400 khz t high clock high time 600 ns t low clock low time 1300 ns t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:sto stop condition setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r (note 5) scl and sda rise time 300 ns t f (note 5) scl and sda fall time 300 ns t aa (note 5) scl low to sda data output valid time 0.9 s t dh sda data output hold time 0 ns t in (note 5) pulse width suppression time at scl and sda inputs 50 ns x9252
5 fn8167.0 march 23, 2005 sda vs scl timing wp , a0, a1, and a2 pin timing t buf (note 5) bus free time (prior to any transmission) 1200 ns t su:wpa (note 5) a0, a1, a2 and wp setup time 600 ns t hd:wpa (note 5) a0, a1, a2 and wp hold time 600 ns 2-wire interface timing (s) (continued) symbol parameter min max units t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:wp scl sda in wp, a0, a1, or a2 t su:wp clk 1 start stop increment/decrement timing symbol parameter min typ (note 4) max units t ci cs to scl setup 600 ns t id (note 5) scl high to u/d , ds0 or ds1 change 600 ns t di (note 5) u/d , ds0 or ds1 to scl setup 600 ns t il scl low period 2.5 s t ih scl high period 2.5 s t ic scl inactive to cs inactive (nonvolatile store setup time) 1 s t cphs cs deselect time (store) 10 ms t cphns (note 5) cs deselect time (no store) 1 s t iw (note 5) scl to r w change 100 500 s t cyc scl cycle time 5 s t r , t f (note 5) scl input rise and fall time 500 s x9252
6 fn8167.0 march 23, 2005 increment/decrement timing notes: 1. absolute linearity is utilized to determine ac tual wiper voltage versus expected voltage = [v(r w(n)(actual) )-v(r w(n)(expected) )]/mi v(r w(n)(expected) ) = n(v(r h )-v(r l ))/255 + v(r l ), with n from 0 to 255. 2. relative linearity is a measure of the error in step size between taps = [v(r w(n+1) )-(v(r w(n) ) + mi)]/mi, with n from 0 to 254 3. 1 ml = minimum increment = [v(r h )-v(r l )]/255. 4. typical values are for t a = 25c and nominal supply voltage. 5. this parameter is not 100% tested. 6. ratiometric temperature coefficient = (v(r w ) t1(n) -v(r w ) t2(n) )/[v(r w ) t1(n) (t1-t2)] x 10 6 , with t1 & t2 being 2 temperatures, and n from 0 to 255. 7. measured with wiper at tap position 255, r l grounded, using test circuit. 8. t wc is the minimum cycle ti me to be allowed for any nonvolatile write by the us er, unless acknowledge polli ng is used. it is the t ime from a valid stop condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of cs of a valid ?store? operation of the up/down interface, to the end of the self-timed internal nonvolatile write cycle. 9. the recommended power up sequence is to apply v cc /v ss first, then the potentiometer voltages. during power up, the data sheet parameters for the dcp do not fully apply until t d after v cc reaches its final value. in order to prevent unwanted tap position changes, or an inadvertant store, bring the cs pin high before or concurrently with the v cc pin on power up. cs scl u/d r w t ci t il t ih t cyc t id t di t iw mi (3) t ic t cphs t f t r 10% 90% 90% t cphns ds0, ds1 high-voltage write cycle timing symbol parameter typ max units t wc (notes 5, 8) non-volatile write cycle time 5 10 ms xdcp timing symbol parameter min max units t wrl (note 5) scl rising edge to wiper code changed, wiper response time after instruction issued (all load instructions) 520s x9252
7 fn8167.0 march 23, 2005 test circuit equivalent circuit pin descriptions bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for the 2-wire interface. it receives device address, operation code, wiper register address and data from a 2-wire external master device at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. sda requires an external pull-up resistor, since it?s an open drain output. serial clock (scl) this input is the serial clock of the 2-wire and up/down interface. device address (a2-a0) the address inputs are used to set the least significant 3 bits of the 8-bit 2-wire interface slave address. a match in the slave address serial data st ream must be made with the address input pins in order to initiate communication with the x9252. a maximum of 8 devices may occupy the 2-wire serial bus. chip select (cs ) when the cs pin is low, increment or decrement operations are possible using the scl and u/d pins. the 2-wire interface is disabled at this time. when cs is high, the 2-wire interface is enabled. up or down control (u/d ) the u/d input pin is held high during increment operations and held low during decrement operations. dcp select (ds1-ds0) the ds1-ds0 select one of the four dcps for an up/down interface operation. hardware write protect input (wp ) when the wp pin is set low, ?write? operations to non volatile dcp data registers are disabled. this includes both 2-wire interface non-volatile ?write?, and up/down interface ?store? operations. dcp pins r h0 , r l0 , r h1 , r l1 , r h2 , r l2 , r h3 , and r l3 these pins are equivalent to the terminal connections on mechanical potentiometers. sinc e there are 4 dcps, there is one set of r h and r l for each dcp. r w0 , r w1 , r w2 , and r w3 the wiper pins are equivalent to the wiper terminal of mechanical potentiometers. since there are four dcps, there are 4 r w pins. force current test point r w c h c l r w r total c w r h r l x9252
8 fn8167.0 march 23, 2005 principles of operation the x9252 is an integrated circuit incorporating four resistor arrays, their associated regi sters and counters, and the serial interface logic providing direct communication between the host and the digita lly controlled potentiometers. this section provides detail description of the following: -resistor array - up/down interface - 2-wire interface resistor array description the x9252 is comprised of four resistor arra ys. each array contains 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r hi and r li inputs) (see figure 1.) at both ends of each array and between each resistor segment is a switch connected to the wiper (r wi ) pin. within each individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the 8-bits of the wcr (wcr[7:0]) are decoded to select and enable one of 256 switches (see table 1). note that each wiper has a dedicated wcr. when all bits of a wcr are zeroes, the switch closest to the corresponding r l pin is selected. when all bits of a wcr are ones, the switch closest to the corresponding r h pin is selected. the wcr is volatile and may be written directly. there are four non-volatile data regist ers (dr) associated with each wcr. each dr can be loaded into wcr. all drs and wcrs can be read or written. power up and down requirements during power up, cs must be high, to avoid inadvertant ?store? operations. at powe r up, the contents of data registers dr00, dr10, dr20, and dr30, are loaded into the corresponding wiper counter register. one wcr[7:0] r hi r wi r li = ff hex 255 254 253 252 of 256 decoder volatile 8-bit wiper counter register wcri four non-volatile data registers dri0, dri1, dri2, and dri3 i = 0, 1, 2, and 3 interface control and wcr[7:0] = 00 hex 2 1 0 volatile status register (sr) (shared by the four dcps) wp scl sda a2, a1, a0 cs u/d ds1, ds0 figure 1. detailed block diagram of one dcp x9252
9 fn8167.0 march 23, 2005 up/down interface operation the scl, u/d , cs , ds0 and ds1 inputs control the movement of the wiper along the resistor array. with cs set low the device is selected and enabled to respond to the u/d and scl inputs. high to low transitions on scl will increment or decrement (depend ing on the state of the u/d input) a wiper counter register selected by ds0 and ds1. the output of this counter is decoded to select one of 256 wiper positions along the resistor array. the value of the counter is stored in nonvolatile data registers dri0 whenever cs transitions high while the scl and wp inputs are high. ?i? indicates the dcp number selected with pins ds1 and ds0. during a ?store? operation bits drsel1 and drsel0 in the status register must be both ?0?, which is their power up default value. other combinations are reserved and must not be used. the system may select the x9252, move the wiper, and deselect the device without havi ng to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as described above and once the new position is reached, the system must keep scl low wh ile taking cs high. the new wiper position will be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. this procedure allo ws the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. the adjustments might be based on user preference, system parameter changes due to temperate drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. the 2-wire interface is disabled while cs remains low. mode selection fo r up/down control 2-wire serial interface protocol overview the device supports a bidirect ional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. the x9252 operates as a slave in all applications. all 2-wire interface operations must begin with a start, followed by a slave address byte. the slave address selects the x9252, and specifies if a read or write operation is to be performed. all communication over the 2-wir e interface is conducted by sending the msb of each byte of data first. serial clock and data data states on the sda line can change only while scl is low. sda state changes while scl is high are reserved for indicating start and stop conditions (see figure 2). on power up of the x9252, the sda pin is in the input mode. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met (see figure 2). serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus (see figure 2). table 1. dcp selection for up/down control ds1 ds0 selected dcp 00 dcp0 01 dcp1 10 dcp2 11 dcp3 cs scl u/d mode l h wiper up l l wiper down h x store wiper position to nonvolatile memory if wp pin is high. no store, return to standby, if wp pin is low. h x x standby l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended) x9252
10 fn8167.0 march 23, 2005 serial acknowledge an ack (acknowledge), is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 3). the device responds with an ack after recognition of a start condition followed by a valid slave address byte. a valid slave address byte must contain the device type identifier 0101, and the device address bits matching the logic state of pins a2, a1, and a0 (see figure 4). if a write operation is select ed, the device responds with an ack after the receipt of eac h subsequent eight-bit word. in the read mode, the device transmits eight bits of data, releases the sda line, and then monitors the line for an ack. the device continues transmitting data if an ack is detected. the device terminates further data transmissions if an ack is not detected. the master must then issue a stop condition to place the device into a known state. sda scl start data data stop stable change data stable figure 2. valid data changes, start, and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master figure 3. acknowledge response from receiver x9252
11 fn8167.0 march 23, 2005 slave address byte following a start condition, the master must output a slave address byte (refer to figure 4.). this byte includes three parts: - the four msbs (sa7-sa4) are the device type identifier, which must always be set to 0101 in order to select the x9252. - the next three bits (sa3-sa1) are the device address bits (as2-as0). to access any part of the x9252?s memory, the value of bits as2, as1, and as0 must correspond to the logic levels at pins a2, a1, and a0 respectively. - the lsb (sa0) is the r/w bit. this bit defines the operation to be performed on the device being addressed. when the r/w bit is ?1?, then a read operation is selected. a ?0? selects a write operation . nonvolatile write acknowledge polling after a nonvolatile write command sequence is correctly issued (including the final stop condition), the x9252 initiates an internal high vo ltage write cycle. this cycle typically requires 5ms. during this time, any read or write command is ignored by the x9252. write acknowledge polling is used to determine whether a high voltage write cycle is completed. during acknowledge polling, the master first issues a start condition followed by a slave address byte. the slave address byte contains the x9252?s device type identifier and device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is busy within the high voltage cycle, then no ack is returned. if the high voltage cycle is completed, an ack is returned and the master can then proceed with a new read or write operation. (refer to figure 5.) 2-wire serial interface operation x9252 digital potentiometer register organization refer to the functional diagram on page 2. there are four digitally controlled potentiometers, referred to as dcpi, i=0,1,2,3. each potentiometer has one volatile wiper control register (wcr) with the corresponding number, wcri, i=0,1,2,3. each potentiometer also has four nonvolatile registers to store wiper positio n or general data, these are numbered dri0, dri1, dri2 and dri3, i=0,1,2,3. the registers are organized in five pages of four, with one page consisting of the wcri (i=0-3), a second page containing the dri0 (i=0-3), a third page containing the dri1, and so forth. these pages can be written to four bytes at time. in this manner all four potentiometer wcrs can be updated in a single serial write (see ?page write operation?), as well as all four registers of a given page in the dr array. the unique feature of the x9252 device is that writing or reading to a data register of a given dcp automatically updates/moves the wcr of that dcp with the content of the dr. in this manner data can be moved from a particular dcp sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read or sa4 slave address bit(s) description sa7-sa4 device type identifier sa3-sa1 device address sa0 read or write operation select r/w 0101 address device as0 as1 as2 write figure 4. slave address (sa) format ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes no continue normal read or write command sequence proceed yes complete. continue command sequence. high voltage issue stop figure 5. acknowledge polling sequence x9252
12 fn8167.0 march 23, 2005 register to that dcp?s wcr just by performing a 2-wire read operation. simultaneously, that data byte can be utilized by the host. status register organization the status register (sr) is used in read and write operations to select the appropriate dcp register. before any dcp register can be accessed, the sr must be set to the correct value. it is accesse d by setting the address byte to 07h (see table 3). do this by writing the slave address followed by a byte address of 07h. the sr is volatile and defaults to 00h on power up. it is an 8-bit register containing three control bits in the 3 lsbs as follows: bits drsel1 and drsel0 determine which data register of a dcp is selected for a given operation. nvenable is used to select the volatile wcr if ?0?, and one of the nonvolatile dcp registers if ?1?. table 2 shows this register organization. ?store? operations using the up/down interface require that bits drsel1 and drsel0 are set to ?0?. to read or write the contents of a si ngle data register or wiper register: 1. load the status register (using a write command) to select the row (see figure 6) writing a 1, 3, 5, or 7 to the status register specifies that the subsequent read or write command will access a data register. this status register operation also initiates a transfer of the contents of the selected data register to its associated wcr for all dcps. so, for example, writing ?03h? to the status register causes the value in dr01 to move to wcr0, dr11 to move to wcr1, dr21 to move to wcr2, and dr31 to move to wcr3. writing a 0 to bit ?0? of the status register specifies that t he subsequent read or write command will access a wiper counter r egister. each wcr can be written to indi vidually, without affecting the contents of any other. 2. access the desired dr or wcr using a new write or read command (see figure 7 for write and figure 9 for read.) specify the desired column (dcp number) by sending t he dcp address as part of this read or write command. 76543 2 1 0 reserved drsel1 drsel0 nvenable table 2. register numbering status reg (note 1) (addr: 07h) registered selected (note 2) reserved bits 7-3 drsel1 bit 2 drsel0 bit 1 nvenable bit 0 dcp0 dcp1 dcp2 dcp3 (addr: 00h) (addr: 01h) (addr: 02h) (addr: 03h) reserved x x 0 wcr0 wcr1 wcr2 wcr3 0 0 1 dr00 dr10 dr20 dr30 0 1 1 dr01 dr11 dr21 dr31 1 0 1 dr02 dr12 dr22 dr32 1 1 1 dr03 dr13 dr23 dr33 s t a r t s t o p slave address status register address data a c k a c k signal at sda signals from the slave signals from the master 0 a c k if bit 0 of data byte = 1, dr contents move to wcr during this ack period 0101 0 0 0 0 0 1 1 1 0 0 0 0 0 x x 1 dr select figure 6. status register write (uses standard byte write sequence to set up access to a data register) x9252
13 fn8167.0 march 23, 2005 dcp addressing for 2-wire interface once the register number has been selected by a 2-wire instruction, then the dcp num ber is determined by the address byte of the following instruction. note again that this enables a complete page writ e of the drs of all four potentiometers at once. the register addresses accessible in the x9252 include: all other address bits in the address byte must be set to ?0? during 2-wire write operations and their value should be ignored when read. byte write operation for any byte write operation, the x9252 requires the slave address byte, an address byte, and a data byte (see figure 7). after each of them, the x9252 responds with an ack. the master then terminates t he transfer by generating a stop condition. at this time, if the write operation is to a volatile register (wcr, or sr), the x9252 is ready for the next read or write operation. if the write operation is to a nonvolatile register (dr), and the wp pin is high, the x9252 begins the internal write cycle to the nonvolatile memory. during the internal nonvolatile write cycle, the x9252 does not respond to any requests from the master. the sda output is at high impedance. the sr bits and wp pin determine the register being accessed through the 2-wire interface (see table 2). as noted before, any write ope ration to a data register (dr), also transfers the contents of all the data registers in that row to their corresponding wcr. for example, to write 3ahex to the data register 1 of dcp2 the following sequence is required: during the sequence of this example, wp pin must be high, and a0, a1, and a2 pins must be low. when completed, the dr21 register and the wcr2 will be set to 3ah and the other data register in row 1 will transfer their other contents to the respective wcr?s. table 3. 2-wire interface address byte address (hex) contents 0 dcp 0 1 dcp 1 2 dcp 2 3 dcp 3 4 not used 5 not used 6 not used 7 status register start slave address 0101 0000 ack address byte 0000 0111 ack data byte 0000 0011 ack note: at this ack, the wcrs are all updated with their respective dr. stop start slave address 0101 0000 ack address byte 0000 0010 ack data byte 0011 1010 ack stop (hardware address = 000, and a write command) (indicates status register address) (data register 1 and nvenable selected) (hardware address = 000, (access dcp2) (write data byte 3ah) write command) s t a r t s t o p slave address address byte data byte a c k signals from the master signals from the slave a c k 0 0 0 11 a c k write signal at sda figure 7. byte write sequence x9252
14 fn8167.0 march 23, 2005 page write operation as stated previously, the memory is organized as a single status register (sr), and four pages of four registers each. each page contains one data register for each dcp. the order of the bytes within a page is dr0i, followed by dr1i, followed by dr2i, and then dr3i, with i being the data register number (0, 1, 2, or 3). normally a page write operation will be used to efficiently update all four data registers and wcr in a single write command, starting at dcp0 and finishing with dcp3. in order to perform a page write operation to the memory array, the nvenable bit in the sr must first be set to ?1?. a page write operation is initia ted in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 4 bytes (see figure 8). after the receipt of each byte, the x9252 responds with an ack, and the internal dcp address counter is incremented by one. the page address remains constant. when the counter reaches the end of the page (dr3i, 03hex), it ?rolls over? and goes back to the first byte of the same page (dr0i, 00hex). for example, if the master wr ites 3 bytes to a page starting at location dr22, the first 2 bytes are written to locations dr22 and dr32, while the last byte is written to locations dr02. afterwards, the dcp counter would point to location dr12. if the master supplies more than 4 bytes of data, then new data overwrites the previous data, one byte at a time. the master terminates the loading of data bytes by issuing a stop condition, which initiate s the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. if the wp pin is low, the nonvolatile write cycle does n?t start and the bytes are discarded. notice that the data bytes are also written to the wcr of the corresponding dcps, therefore in the above example, wcr2, wcr3, and wcr0 are also written and wcr1 is updated with the c ontents of dr12. 2 < n < 4 signals from the master signals from the slave signal at sda s t a r t slave address address byte a c k a c k 0 0 0 11 data byte (1) s t o p a c k a c k data byte (n) write figure 8. page write operation x9252
15 fn8167.0 march 23, 2005 move/read operation the move/read operation simultaneously reads the contents of a data register (dr) and moves the contents into the corresponding dcp?s wcr and the wcrs of all dcps are updated with the cont ent of their corresponding dr. move/read operation consists of a one byte, or three byte instruction followed by one or more data bytes (see figure 9). to read an arbitrary byte, the master initiates the operation issuing the following sequence: a start, the slave address byte with the r/w bit set to ?0?, an address byte, a second start, and a second slave address byte with the r/w bit set to ?1?. after each of the three bytes, the x9252 responds with an ack. then the x9252 transmits data bytes as long as the master responds with an ack during the scl cycle fo llowing the eight bit of each byte. the master terminates the move/read operation (issuing a stop condition) following the last bit of the last data byte. the first byte being read is determined by the current dcp address and by the status register bits, according to table 2. if more than one byte is read, the dcp address is incremented by one after each byte, in the same way as during a page write operation. after reaching dcp3, the dcp address ?rolls over? to dcp0. on power up, the address pointer is set to the data register 0 of dcp0. signals from the master signals from the slave signal at sda s t a r t slave address with r/w =0 address byte a c k a c k 0 0 0 11 s t o p a c k 0 1 0 11 slave address with r/w =1 a c k s t a r t last read data byte first read data byte a c k one or more data bytes current address read setting the current address random address read figure 9. move/read sequence x9252
16 fn8167.0 march 23, 2005 applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + - v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + - v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? +5v tl072 + - v s v o r 2 r 1 } } +5v x9252
17 fn8167.0 march 23, 2005 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + - v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + - v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + - v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + - v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + - r 2 + - r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9252
18 fn8167.0 march 23, 2005 application circuits (continued) window comparator shunt limiter function generator + - v s v o v+ + - v ul v ll v+ + - v s v o } } v r + } mr nr pr + - v o } } } mr nr pr c + - x9252
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8167.0 march 23, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop, package code v24 .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ?a? .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 0-8 x9252

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