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?2002 fairchild semiconductor corporation august 2002 FDP13N40 / fdb13n40 rev. a, FDP13N40 / fdb13n40 FDP13N40 / fdb13n40 13a, 400v, 0.37 ohm, n-channel smps power mosfet applications switch mode power supplies(smps), such as ? pfc boost two-switch forward converter single switch forward converter flyback converter buck converter high speed switching features low gate charge q g results in simple drive requirement improved gate, avalanche and high reapplied dv/dt ruggedness reduced r ds(on) reduced miller capacitance and low input capacitance improved switching speed with low emi 175c rated junction temperature absolute maximum ratings t c = 25c unless otherwise noted thermal characteristics symbol parameter ratings units v dss drain to source voltage 400 v v gs gate to source voltage 30 v i d drain current 13 a continuous (t c = 25 o c, v gs = 10v) continuous (t c = 100 o c, v gs = 10v) 9.2 a pulsed (note 1) 52 a p d power dissipation derate above 25 o c 250 1.67 w w/ o c t j , t stg operating and storage temperature -55 to 175 o c soldering temperature for 10 seconds 300 (1.6mm from case) o c mounting torque, 8-32 or m3 screw 10ibf*in (1.1n*m) r jc thermal resistance junction to case 0.6 o c/w r cs thermal resistance case to sink, flat, greased surface 0.50 typ o c/w r ja thermal resistance junction to ambient 62 o c/w d g s drain (flange) drain source gate gate source drain (flange) package symbol jedec to-220ab jedec to-263ab
?2002 fairchild semiconductor corporation FDP13N40 / fdb13n40 rev. a FDP13N40 / fdb13n40 package marking and ordering information electrical characteristics t c = 25c (unless otherwise noted) statics dynamics avalanche characteristics drain-source diode characteristics notes: 1: repetitive rating; pulse width limited by maximum junction temperature 2: starting t j = 25 c, l = 7mh, i as = 13a device marking device package reel size tape width quantity FDP13N40 FDP13N40 to-220ab tube - 50 fdb13n40 fdb13n40 to-263ab 330mm 24mm 800 symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 400 - - v ? b vdss / ? t j breakdown voltage temp. coefficient v/c reference to 25c i d = 1ma -0.48- r ds(on) drain to source on-resistance v gs = 10v, i d = 6.5a - 0.35 0.37 ? v gs(th) gate threshold voltage v ds = v gs , i d = 250a 2.0 3.2 4.0 v i dss zero gate voltage drain current v ds = 400v t c = 25 o c --25 a v gs = 0v t c =150 o c - - 250 i gss gate to source leakage current v gs = 20v - - 100 na g fs forward transconductance v ds = 50v, i d = 6.5a 7 - - s q g(tot) total gate charge at 10v v gs = 10v v ds = 320v i d = 13a - 18.3 22 nc q gs gate to source gate charge - 5 6 nc q gd gate to drain ?miller? charge - 5.8 7 nc t d(on) turn-on delay time v dd = 200v i d = 13a r g = 10 ? r d = 15.4 ? -7.5- ns t r rise time - 25.5 - ns t d(off) turn-off delay time - 33.5 - ns t f fall time - 26.4 - ns c iss input capacitance v ds = 25v, v gs = 0v f = 1mhz -1060- pf c oss output capacitance - 143 - pf c rss reverse transfer capacitance - 6 - pf e as single pulse avalanche energy (note 2) 591 - - mj i ar avalanche current - - 13 a i s continuous source current (body diode) mosfet symbol showing the integral reverse p-n junction diode. --13a i sm pulsed source current (note 1) (body diode) --52a v sd source to drain diode voltage i sd = 13a - 0.9 1.2 v t rr reverse recovery time i sd = 13a, di sd /dt = 100a/ s - 280 364 ns q rr reverse recovered charge i sd = 13a, di sd /dt = 100a/ s- 2.6 3.4 c d g s
?2002 fairchild semiconductor corporation FDP13N40 / fdb13n40 rev. a FDP13N40 / fdb13n40 typical characteristic figure 1. output characteristics figure 2. output characteristics figure 3. transfer characteristics figure 4. normalized drain to source on resistance vs junction temperatrue figure 5. capacitance vs drain to source voltage figure 6. gate charge waveforms for constant gate current 1 10 100 110100 v ds , drain to source voltage (v) i d , drain to source current (a) t c = 25 o c pulse duration = 80 s duty cycle = 0.5% max 10v 7v 6.5v 6v 5.5v 5v v gs descending 1 10 40 110100 v ds , drain to source voltage (v) i d , drain to source current (a) pulse duration = 80 s duty cycle = 0.5% max t c = 175 o c 6.5v 6v 5.5v 5v v gs descending 5 10 15 20 25 3.5 4.0 4.5 5.0 5.5 6.0 0 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 50v t j = 175 o c t j = 25 o c 0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 150 175 3.5 normalized drain to source on resistance t j , junction temperature ( o c) v gs = 10v, i d = 6.5a pulse duration = 80 s duty cycle = 0.5% max 1 10 100 1000 110100 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c oss c iss c rss 0 5 10 15 0 5 10 15 20 25 30 80v v gs , gate to source voltage (v) q g , gate charge (nc) i d = 13a 200v 320v
?2002 fairchild semiconductor corporation FDP13N40 / fdb13n40 rev. a FDP13N40 / fdb13n40 figure 7. source to drain diode forward voltage figure 8. maximum safe operating area figure 9. maximum drain current vs case temperature figure 10. normalized maximum transient thermal impedance typical characteristic (continued) 5 10 15 20 25 30 35 40 0.20.30.40.50.60.70.80.91.01.11.2 0 i sd , source to drain current (a) v sd , source to drain voltage (v) t j = 175 o c t j = 25 o c 0.1 1 10 100 1 10 100 1000 i d , drain current (a) v ds , drain to source voltage (v) operation in this area t c = 25 o c limited by r ds(on) 1ms 100 s 10ms dc t c , case temperature (c) i d , drain current (a) 0 2 4 6 8 10 12 25 50 75 100 125 150 175 14 0.01 0.1 1.0 2.0 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 t 1 , rectangular pulse duration (s) z jc , normalized thermal impedance t 1 t 2 p d duty factor, d = t 1 / t 2 peak t j = (p d x z jc x r jc ) + t c single pulse 0.50 0.20 0.05 0.02 0.01 0.10
?2002 fairchild semiconductor corporation FDP13N40 / fdb13n40 rev. a FDP13N40 / fdb13n40 test circuits and waveforms figure 11. unclamped energy test circuit figure 12. unclamped energy waveforms figure 13. gate charge test circuit figure 14. gate charge waveforms figure 15. switching time test circuit figure 16. switching time waveform t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) q g(th) v gs = 1v q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0

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