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ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 1 69931234fa typical a pplica t ion fea t ures descrip t ion timerblox: monostable pulse generator (one shot) the lt c ? 6993 is a monostable multivibrator ( also known as a one-shot pulse generator) with a programmable pulse width of 1 s to 33.6 seconds. the ltc6993 is part of the timerblox ? family of versatile silicon timing devices. a single resistor, r set , programs an internal master os- cillator frequency, setting the ltc6993 s time base. the output pulse width is determined by this master oscillator and an internal clock divider, n div , programmable to eight settings from 1 to 2 21 . t out = n div ? r set 50k ? 1s, n div = 1, 8, 64,...,2 21 the output pulse is initiated by a transition on the trigger input ( trig). each part can be configured to generate posi- tive or negative output pulses. the ltc6993 is available in four versions to provide different trigger signal polarity and retrigger capability. device input polarity retrigger ltc6993-1 rising-edge no ltc6993-2 rising-edge yes ltc6993-3 falling-edge no ltc6993-4 falling-edge yes the ltc6993 also offers the ability to dynamically adjust the width of the output pulse via a separate control voltage. for easy configuration of the ltc6993, download the timerblox designer tool at www.linear.com/timerblox. envelope detector a pplica t ions n pulse width range: 1s to 33.6 seconds n configured with 1 to 3 resistors n pulse width max error: C <2.3% for pulse width > 512s C <3.4% for pulse width of 8s to 512s C <4.9% for pulse width of 1s to 8s n four ltc6993 options available: C rising-edge or falling-edge t rigger C retriggerable or non-retriggerable n configurable for positive or negative output pulse n fast recovery time n 2.25v to 5.5v single supply operation n 70a supply current at 10s pulse width n 500 s start-up time n cmos output driver sources/sinks 20ma n C40 c to 125c operating temperature range n available in low profile (1mm) sot-23 (thinsot?) and 2mm 3mm dfn n watchdog timer n frequency discriminators n missing pulse detection n envelope detection n high vibration, high acceleration environments n portable and battery-powered equipment l, lt , lt c , lt m , linear technology, timerblox and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 69931234 ta01a ltc6993-2 out v+ div trig gnd set r set 800k 3.3v 0.1f signal envelope modulated carrier trig 2v/div out 2v/div 50s/div 69931234 ta01b 80khz carrier 16s
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 2 69931234fa a bsolu t e maxi m u m r a t ings supply voltage (v +) to gnd ........................................ 6 v maximum voltage on any pin .................................. ( gnd C 0.3 v) v pin (v + + 0.3 v) operating temperature range ( note 2) ltc 69 93 c ............................................ C 40 c to 85 c ltc 69 93 i ............................................. C4 0 c to 85 c ltc 69 93 h .......................................... C4 0 c to 125 c (note 1) o r d er i n f or m a t ion tape and reel (mini) tape and reel part marking* package description specified temperature range ltc6993cdcb-1#trmpbf ltc6993cdcb-1#trpbf ldxh 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6993idcb-1#trmpbf ltc6993idcb-1#trpbf ldxh 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6993hdcb-1#trmpbf ltc6993hdcb-1#trpbf ldxh 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6993cdcb-2#trmpbf ltc6993cdcb-2#trpbf ldxk 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6993idcb-2#trmpbf ltc6993idcb-2#trpbf ldxk 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6993hdcb-2#trmpbf ltc6993hdcb-2#trpbf ldxk 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6993cdcb-3#trmpbf ltc6993cdcb-3#trpbf lfmj 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6993idcb-3#trmpbf ltc6993idcb-3#trpbf lfmj 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6993hdcb-3#trmpbf ltc6993hdcb-3#trpbf lfmj 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6993cdcb-4#trmpbf ltc6993cdcb-4#trpbf lfmm 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6993idcb-4#trmpbf ltc6993idcb-4#trpbf lfmm 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6993hdcb-4#trmpbf ltc6993hdcb-4#trpbf lfmm 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6993cs6-1#trmpbf ltc6993cs6-1#trpbf ltdxg 6-lead plastic tsot-23 0c to 70c ltc6993is 6-1#trmpbf ltc 6993is6-1#trpbf ltdxg 6-lead plastic tsot-23 C40c to 85c ltc6993hs6-1#trmpbf ltc6993hs6-1#trpbf ltdxg 6-lead plastic tsot-23 C40c to 125c top view out gnd trig v + div set dcb package 6-lead (2mm 3mm) plastic dfn 4 5 7 6 3 2 1 t jmax = 150c, ja = 64c/w, jc = 10.6c/w exposed pad (pin 7) connected to gnd, pcb connection optional trig 1 gnd 2 set 3 6 out 5 v + 4 div top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 192c/w, jc = 51c/w p in c on f igura t ion specified temperature range ( note 3) ltc 69 93 c ................................................ 0 c to 70 c ltc 69 93 i ............................................. C4 0 c to 85 c ltc 69 93 h .......................................... C4 0 c to 125 c junction temperature ........................................... 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) s6 p ackage ....................................................... 30 0 c lead free finish
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 3 69931234fa e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, trig = 0v, divcode = 0 to 15 (n div = 1 to 2 21 ), r set = 50k to 800k, r load = 5k, c load = 5pf unless otherwise noted. tape and reel (mini) tape and reel part marking* package description specified temperature range ltc6993cs6-2#trmpbf ltc6993cs6-2#trpbf ltdxj 6-lead plastic tsot-23 0c to 70c ltc6993is6-2#trmpbf ltc6993is6-2#trpbf ltdxj 6-lead plastic tsot-23 C40c to 85c ltc6993hs6-2#trmpbf ltc6993hs6-2#trpbf ltdxj 6-lead plastic tsot-23 C40c to 125c ltc6993cs6-3#trmpbf ltc6993cs6-3#trpbf ltfmh 6-lead plastic tsot-23 0c to 70c ltc6993is6-3#trmpbf ltc6993is6-3#trpbf ltfmh 6-lead plastic tsot-23 C40c to 85c ltc6993hs6-3#trmpbf ltc6993hs6-3#trpbf ltfmh 6-lead plastic tsot-23 C40c to 125c ltc6993cs6-4#trmpbf ltc6993cs6-4#trpbf ltfmk 6-lead plastic tsot-23 0c to 70c ltc6993is6-4#trmpbf ltc6993is6-4#trpbf ltfmk 6-lead plastic tsot-23 C40c to 85c ltc6993hs6-4#trmpbf ltc6993hs6-4#trpbf ltfmk 6-lead plastic tsot-23 C40c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o r d er i n f or m a t ion symbol parameter conditions min typ max units t out output pulse width 1 33.55 sec ?t out pulse width accuracy (note 4) n div 512 l 1.7 2.3 3.0 % % 8 n div 64 l 2.4 3.4 4.4 % % n div = 1 (ltc6993-1 or ltc6993-2) l 3.6 4.9 6.0 % % n div = 1 (ltc6993-3 or ltc6993-4) l 4.0 5.3 6.4 % % ?t out /?t pulse width drift over temperature n div 512 n div 64 l l 0.006 0.008 %/c %/c pulse width change with supply n div 512 v + = 4.5v to 5.5v v + = 2.25v to 4.5v l l C0.6 C0.4 C0.2 C0.1 % % 8 n div 64 v + = 4.5v to 5.5v v + = 2.7v to 4.5v v + = 2.25v to 2.7v l l l C0.9 C0.7 C1.1 C0.2 C0.2 C0.1 0.4 0.9 % % % pulse width jitter (note 10) n div = 1 v + = 5.5v v + = 2.25v 0.85 0.45 % p-p % p-p n div = 8 0.20 % p-p n div = 64 0.05 % p-p n div = 512 0.20 % p-p n div = 4096 0.03 % p-p t s pulse width change settling time (note 9) t master = t out /n div 6 ? t master s lead free finish
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 4 69931234fa e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, trig = 0v, divcode = 0 to 15 (n div = 1 to 2 21 ), r set = 50k to 800k, r load = 5k, c load = 5pf unless otherwise noted. symbol parameter conditions min typ max units power supply v + operating supply voltage range l 2.25 5.5 v power-on reset voltage l 1.95 v i s(idle) supply current (idle) r l = , r set = 50k, n div 64 v + = 5.5v v + = 2.25v l l 165 125 200 160 a a r l = , r set = 50k, n div 512 v + = 5.5v v + = 2.25v l l 135 105 175 140 a a r l = , r set = 800k, n div 64 v + = 5.5v v + = 2.25v l l 70 60 110 95 a a r l = , r set = 800k, n div 512 v + = 5.5v v + = 2.25v l l 65 55 100 90 a a analog inputs v set voltage at set pin l 0.97 1.00 1.03 v ?v set /?t v set drift over temperature l 75 v/c r set frequency-setting resistor l 50 800 k v div div pin voltage l 0 v + v ?v div /?v + div pin valid code range (note 5) deviation from ideal v div /v + = (divcode + 0.5)/16 l 1.5 % div pin input current l 10 na digital i/o trig pin input capacitance 2.5 pf trig pin input current trig = 0v to v + 10 na v ih high level trig pin input voltage (note 6) l 0.7 ? v + v v il low level trig pin input voltage (note 6) l 0.3 ? v + v i out(max) output current v + = 2.7v to 5.5v 20 ma v oh high level output voltage (note 7) v + = 5.5v i out = C1ma i out = C16ma l l 5.45 4.84 5.48 5.15 v v v + = 5.5v i out = C1ma i out = C16ma l l 3.24 2.75 3.27 2.99 v v v + = 2.25v i out = C1ma i out = C8ma l l 2.17 1.58 2.21 1.88 v v v ol low level output voltage (note 7) v + = 5.5v i out = 1ma i out = 16ma l l 0.02 0.26 0.04 0.54 v v v + = 3.3v i out = 1ma i out = 10ma l l 0.03 0.22 0.05 0.46 v v v + = 2.25v i out = 1ma i out = 8ma l l 0.03 0.26 0.07 0.54 v v
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 5 69931234fa e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6993c is guaranteed functional over the operating temperature range of C40c to 85c. note 3: the ltc6993c is guaranteed to meet specified performance from 0c to 70c. the ltc6993c is designed, characterized and expected to meet specified performance from C40c to 85c but it is not tested or qa sampled at these temperatures. the ltc6993i is guaranteed to meet specified performance from C40c to 85c. the ltc6993h is guaranteed to meet specified performance from C40c to 125c. note 4: pulse width accuracy is defined as the deviation from the t out equation, assuming r set is used to program the pulse width. note 5: see operation section, table 1 and figure 2 for a full explanation of how the div pin voltage selects the value of divcode. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, trig = 0v, divcode = 0 to 15 (n div = 1 to 2 21 ), r set = 50k to 800k, r load = , c load = 5pf unless otherwise noted. note 6: the trig pin has hysteresis to accommodate slow rising or falling signals. the threshold voltages are proportional to v + . typical values can be estimated at any supply voltage using: v trig(rising) 0.55 ? v + + 185mv and v trig(falling) 0.48 ? v + C 155mv note 7: to conform to the logic ic standard, current out of a pin is arbitrarily given a negative value. note 8: output rise and fall times are measured between the 10% and the 90% power supply levels with 5pf output load. these specifications are based on characterization. note 9: settling time is the amount of time required for the output to settle within 1% of the final pulse width after a 0.5 or 2 change in i set . note 10: jitter is the ratio of the deviation of the output pulse width to the mean of the pulse width. this specification is based on characterization and is not 100% tested. symbol parameter conditions min typ max units t pd trigger propagation delay v + = 5.5v v + = 3.3v v + = 2.25v 11 17 28 ns ns ns t width minimum recognized trig pulse width v + = 3.3v 5 ns t arm recovery time (ltc6993-1/ltc6993-3) C4 ns t retrig time between trigger signals (ltc6993-2/ltc6993-4) n div = 1 v + = 3.3v n div > 1 v + = 3.3v 10 50 ns ns t r output rise time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.1 1.7 2.7 ns ns ns t f output fall time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.0 1.6 2.4 ns ns ns
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 6 69931234fa typical p er f or m ance c harac t eris t ics t out drift vs temperature (n div 512) t out drift vs supply voltage (n div = 1, rising edge) t out drift vs temperature (n div 64) v + = 3.3v, r set = 200k and t a = 25c unless otherwise noted. t out drift vs temperature (n div 64) t out drift vs temperature (n div 64) temperature (c) ?50 drift (%) 0.5 1.0 1.5 25 75 69931234 g01 0 ?0.5 ?25 0 50 100 125 ?1.0 ?1.5 r set = 50k 3 parts temperature (c) ?50 drift (%) 0.5 1.0 1.5 25 75 69931234 g02 0 ?0.5 ?25 0 50 100 125 ?1.0 ?1.5 r set = 200k 3 parts temperature (c) ?50 drift (%) 0.5 1.0 1.5 25 75 69931234 g03 0 ?0.5 ?25 0 50 100 125 ?1.0 ?1.5 r set = 800k 3 parts temperature (c) ?50 drift (%) 0.5 1.0 1.5 25 75 69931234 g04 0 ?0.5 ?25 0 50 100 125 ?1.0 ?1.5 r set = 50k 3 parts t out drift vs temperature (n div 512) temperature (c) ?50 drift (%) 0.5 1.0 1.5 25 75 69931234 g05 0 ?0.5 ?25 0 50 100 125 ?1.0 ?1.5 r set = 200k 3 parts t out drift vs temperature (n div 512) temperature (c) ?50 drift (%) 0.5 1.0 1.5 25 75 69931234 g06 0 ?0.5 ?25 0 50 100 125 ?1.0 ?1.5 r set = 800k 3 parts supply (v) 2 ?1.0 drift (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 3 4 69931234 g07 ?0.6 0.6 0.8 0.2 5 6 r set = 50k r set = 200k r set = 800k ltc6993-1/ltc6993-2 divcode = 0 referenced to v + = 4v t out drift vs supply voltage (n div = 1, falling edge) supply (v) 2 ?1.0 drift (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 3 4 69931234 g08 ?0.6 0.6 0.8 0.2 5 6 r set = 50k r set = 200k r set = 800k ltc6993-3/ltc6993-4 divcode = 0 referenced to v + = 4v t out drift vs supply voltage (n div > 1) supply (v) 2 ?1.0 drift (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 3 4 69931234 g09 ?0.6 0.6 0.8 0.2 5 6 r set = 50k, n div = 8 r set = 50k to 800k, n div 512 r set = 800k, n div = 8 referenced to v + = 4v
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 7 69931234fa typical p er f or m ance c harac t eris t ics v set drift vs i set v + = 3.3v, r set = 200k and t a = 25c unless otherwise noted. t out error vs r set (n div = 1, rising edge) r set (k) 50 ?5 error (%) ?3 ?1 1 3 100 200 400 800 69931234 g10 5 ?4 ?2 0 2 4 ltc6993-1/ltc6993-2 divcode = 0 3 parts t out error vs r set (8 n div 64) r set (k) 50 ?5 error (%) ?3 ?1 1 3 100 200 400 800 69931234 g11 5 ?4 ?2 0 2 4 3 parts t out error vs r set (n div 512) r set (k) 50 ?5 error (%) ?3 ?1 1 3 100 200 400 800 69931234 g12 5 ?4 ?2 0 2 4 3 parts t out error vs r set (n div = 1, falling edge) r set (k) 50 ?5 error (%) ?3 ?1 1 3 100 200 400 800 69931234 g13 5 ?4 ?2 0 2 4 ltc6993-3/ltc6993-4 divcode = 0 3 parts t out error vs divcode (rising edge) divcode 0 error (%) 1 3 5 2 4 6 8 69931234 g14 ?1 ?3 0 2 4 ?2 ?4 ?5 10 12 14 ltc6993-1/ltc6993-2 r set = 50k 3 parts t out error vs divcode (falling edge) divcode 0 error (%) 1 3 5 2 4 6 8 69931234 g15 ?1 ?3 0 2 4 ?2 ?4 ?5 10 12 14 ltc6993-3/ltc6993-4 r set = 50k 3 parts i set (a) 0 ?1.0 0 0.4 0.2 0.6 0.8 1.0 10 15 20 ?0.4 ?0.2 ?0.6 ?0.8 5 69931234 g16 v set (mv) referenced to i set = 10a v set drift vs supply voltage supply (v) 2 ?1.0 0 0.4 0.2 0.6 0.8 1.0 4 5 6 ?0.4 ?0.2 ?0.6 ?0.8 3 69931234 g17 drift (mv) referenced to v + = 4v v set vs temperature temperature (c) ?50 0.980 1.000 1.010 1.005 1.015 1.020 0 25 50 100 125 0.995 0.990 0.985 ?25 75 69931234 g18 v set (v) 3 parts
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 8 69931234fa typical p er f or m ance c harac t eris t ics typical v set distribution supply current vs supply voltage supply current vs temperature supply current vs trig pin voltage supply current vs t out (5v) v + = 3.3v, r set = 200k and t a = 25c unless otherwise noted. v set (v) 0.98 0 100 50 150 200 250 0.996 1.004 1.012 1.02 0.988 69931234 g19 number of units 2 lots dfn and sot-23 1274 units typical i set current limit vs v + trig threshold voltage vs supply voltage peak-to-peak jitter vs t out supply current vs t out (2.5v) t out (ms) 50 power supply current (a) 100 150 200 250 0.001 0.1 1 100 69931234 g23 0 0.01 10 active idle v + = 5v c load = 5pf r load = active current measured with trigger period = 2 ? t out (50% duty cycle) 1 8 64 512 t out (ms) 50 power supply current (a) 100 150 200 250 0.001 0.1 1 100 69931234 g24 0 0.01 10 active idle v + = 2.5v c load = 5pf r load = active current measured with trigger period = 2 ? t out (50% duty cycle) 1 8 64 512 t out (ms) 0.001 0.4 jitter (% p-p ) 0.5 0.6 0.7 0.8 0.01 0.1 1 10 100 69931234 g26 0.3 0.2 0.1 0 0.9 1.0 1, 5.5v 1, 2.25v 8, 2.25v 8, 5.5v 64 512 4096 peak-to-peak t out variation measured over 30s intervals supply voltage (v) rst pin voltage (v) 69931234 g25 3.5 1.0 2.0 3.0 0.5 1.5 2.5 0 2 4 3 5 6 positive going negative going supply voltage (v) i set (a) 69931234 g27 1000 400 800 200 600 0 2 4 3 5 6 set pin shorted to gnd supply voltage (v) 2 0 power supply current (a) 50 100 150 200 250 300 3 4 5 6 69931234 g20 ?active? = 50% timing duty cycle r set = 50k 1, active r set = 50k 1, idle r set = 100k, 8, active r set = 100k, 8, idle r set = 800k, 512 c load = 5pf r load = temperature (c) ?50 ?25 0 power supply current (a) 50 100 150 200 250 0 25 50 75 100 125 69931234 g21 ?active? = 50% timing duty cycle r set = 100k, 8, active r set = 50k, 1, active r set = 100k, 8, idle r set = 50k, 1, idle r set = 800k, 512 c load = 5pf r load = v trig /v + (v/v) 0 power supply current (a) 150 200 250 0.8 69931234 g22 100 50 0 0.2 0.4 0.6 1.0 5v trig falling 5v trig rising 3.3v trig rising 3.3v trig falling c load = 5pf r load =
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 9 69931234fa trigger propagation delay (t pd ) vs supply voltage rise and fall time vs supply voltage output resistance vs supply voltage supply voltage (v) 2 0 propagation delay (ns) 5 10 15 20 25 30 3 4 5 6 69931234 g28 c load = 5pf supply voltage (v) rise/fall time (ns) 6990 g29 3.0 1.5 2.5 1.0 0.5 2.0 0 2 4 3 5 6 c load = 5pf t rise t fall supply voltage (v) output resistance () 69931234 g30 50 25 20 35 45 5 10 15 30 40 0 2 4 3 5 6 output sourcing current output sinking current typical p er f or m ance c harac t eris t ics v + = 3.3v, r set = 200k and t a = 25c unless otherwise noted.
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 10 69931234fa p in func t ions (dcb/s6) v + (pin 1/pin 5): supply voltage (2.25 v to 5.5 v). this sup- ply should be kept free from noise and ripple. it should be bypassed directly to the gnd pin with a 0.1f capacitor. div (pin 2/pin 4): programmable divider and polarity input. the div pin voltage (v div ) is internally converted into a 4- bit result ( divcode). v div may be generated by a resistor divider between v + and gnd. use 1% resistors to ensure an accurate result. the div pin and resistors should be shielded from the out pin or any other traces that have fast edges. limit the capacitance on the div pin to less than 100 pf so that v div settles quickly. the msb of divcode ( pol) determines the polarity of the out pins. when pol = 0 the output produces a positive pulse. when pol = 1 the output produces a negative pulse. set (pin 3/pin 3): pulse width setting input. the voltage on the set pin (v set ) is regulated to 1 v above gnd. the amount of current sourced from the set pin (i set ) pro- grams the master oscillator frequency. the i set current range is 1.25 a to 20 a. the output pulse will continue indefinitely if i set drops below approximately 500 na, and will terminate when i set increases again. a resistor connected between set and gnd is the most accurate way to set the pulse width. for best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50 ppm/c or better temperature coefficient. for lower accuracy applications an inexpensive 1% thick film resistor may be used. limit the capacitance on the set pin to less than 10pf to minimize jitter and ensure stability. capacitance less than 100 pf maintains the stability of the feedback circuit regulating the v set voltage. trig (pin 4/pin 1): trigger input. depending on the ver- sion, a rising or falling edge on trig will initiate the output pulse. ltc6993-1 and ltc6993-2 are rising-edge sensi- tive. ltc6993-3 and ltc6993-4 are falling-edge sensitive. the ltc6993-2 and ltc6993-4 are retriggerable, allowing the pulse width to be extended by additional trigger signals that occur while the output is active. the ltc6993 - 1/ ltc6993-3 will ignore additional trigger inputs until the output pulse has terminated. gnd (pin 5/pin 2): ground. tie to a low inductance ground plane for best performance. out (pin 6/pin 6): output. the out pin swings from gnd to v + with an output resistance of approximately 30. when driving an led or other low impedance load a series output resistor should be used to limit source/ sink current to 20ma. 69931234 pf ltc6993 trig gnd set out v + div c1 0.1f r set r2 r1 v + v +
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 11 69931234fa b lock diagra m (s6 package pin numbers shown) 69931234 bd programmable divider 1, 8, 64, 512, 4096, 2 15 , 2 18 , 2 21 master oscillator por digital filter 4-bit a/d converter pol r1 r2 div v + out 5 4 trig 1 6 halt oscillator if i set < 500na mclk + ? i set i set v set = 1v + ? 1v 3 22 gnd set r set t out trigger/ retrigger logic t master = ? 1s 50k v set i set s r q output polarity
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 12 69931234fa o pera t ion the ltc6993 is built around a master oscillator with a 1s minimum period. the oscillator is controlled by the set pin current (i set ) and voltage (v set ), with a 1s/50k conversion factor that is accurate to 1.7% under typical conditions. t master = 1s 50k ? v set i set a feedback loop maintains v set at 1v 30 mv, leaving i set as the primary means of controlling the pulse width. the simplest way to generate i set is to connect a resistor (r set ) between set and gnd, such that i set = v set /r set . the master oscillator equation reduces to: t master = 1s ? r set 50k from this equation, it is clear that v set drift will not affect the pulse width when using a single program resistor (r set ). error sources are limited to r set tolerance and the inherent pulse width accuracy ?t out of the ltc6993. r set may range from 50 k to 800k ( equivalent to i set between 1.25a and 20a). a trigger signal ( rising or falling edge on trig pin) latches the output to the active state, beginning the output pulse. at the same time, the master oscillator is enabled to time the duration of the output pulse. when the desired pulse width is reached, the master oscillator resets the output latch. the ltc6993 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 2 15 , 2 18 or 2 21 . this extends the pulse width duration by those same factors. the divider ratio n div is set by a resistor divider attached to the div pin. t out = n div 50k ? v set i set ? 1s with r set in place of v set /i set the equation reduces to: t out = n div ? r set 50k ? 1s divcode the div pin connects to an internal, v + referenced 4-bit a/d converter that determines the divcode value. divcode programs two settings on the ltc6993: 1. divcode determines the frequency divider setting, n div . 2. divcode determines the polarity of out pin, via the pol bit. v div may be generated by a resistor divider between v + and gnd as shown in figure 1. figure 1. simple technique for setting divcode 69931234 f01 ltc6993 v + div gnd r1 r2 2.25v to 5.5v table 1 offers recommended 1% resistor values that ac- curately produce the correct voltage division as well as the corresponding n div and pol values for the recommended resistor pairs. other values may be used as long as: 1. the v div /v + ratio is accurate to 1.5% ( including resis- tor tolerances and temperature effects). 2. the driving impedance ( r 1||r 2) does not exceed 500k . if the voltage is generated by other means ( i.e., the output of a dac) it must track the v + supply voltage. the last column in table 1 shows the ideal ratio of v div to the supply voltage, which can also be calculated as: v div v + = divcode + 0.5 16 1.5% for example, if the supply is 3.3 v and the desired divcode is 4, v div = 0.281 ? 3.3v = 928mv 50mv. figure 2 illustrates the information in table 1, showing that n div is symmetric around the divcode midpoint.
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 13 69931234fa o pera t ion table 1. divcode programming divcode pol n div recommended t out r1 (k) r2 (k) v div /v + 0 0 1 1s to 16s open short 0.03125 0.015 1 0 8 8s to 128s 976 102 0.09375 0.015 2 0 64 64s to 1.024ms 976 182 0.15625 0.015 3 0 512 512s to 8.192ms 1000 280 0.21875 0.015 4 0 4,096 4.096ms to 65.54ms 1000 392 0.28125 0.015 5 0 32,768 32.77ms to 524.3ms 1000 523 0.34375 0.015 6 0 262,144 262.1ms to 4.194sec 1000 681 0.40625 0.015 7 0 2,097,152 2.097sec to 33.55sec 1000 887 0.46875 0.015 8 1 2,097,152 2.097sec to 33.55sec 887 1000 0.53125 0.015 9 1 262,144 262.1ms to 4.194sec 681 1000 0.59375 0.015 10 1 32,768 32.77ms to 524.3ms 523 1000 0.65625 0.015 11 1 4,096 4.096ms to 65.54ms 392 1000 0.71875 0.015 12 1 512 512s to 8.192ms 280 1000 0.78125 0.015 13 1 64 64s to 1.024ms 182 976 0.84375 0.015 14 1 8 8s to 128s 102 976 0.90625 0.015 15 1 1 1s to 16s short open 0.96875 0.015 0.5 ? v + t out (ms) 69931234 f02 1000 10000 100 10 1 0.001 0.1 0.01 increasing v div v + 0v pol bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pol bit = 1 figure 2. pulse width range and pol bit vs divcode
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 14 69931234fa o pera t ion monostable multivibrator (one shot) the ltc6993 is a monostable multivibrator. a trigger signal on the trig input will force the output to the active (unstable) state for a programmable duration. this type of circuit is commonly referred to as a one-shot pulse generator. figures 3 details the basic operation. a rising edge on the trig pin initiates the output pulse. the pulse width (t out ) is determined by the n div setting and by the resis- tor (r set ) connected to the set pin. subsequent rising edges on trig have no affect until the completion of the one shot and for a short rearming time ( t arm ) thereafter. to ensure proper operation, positive and negative trig pulses should be at least t width wide. the ltc6993-2 and ltc6993-4 allow the output pulse to be retriggered. as shown in figure 4, the output pulse will stay high until t out after the last rising-edge on trig. successive trigger signals can extend the pulse width in- definitely. consecutive trigger signals must be separated by t retrig to be recognized. negative trigger versions in addition to the retrigger option, the ltc6993 family also includes negative input ( falling-edge) versions. these four combinations are detailed in table 2. table 2. retrigger and input polarity options device input polarity retrigger ltc6993-1 rising-edge no ltc6993-2 rising-edge yes ltc6993-3 falling-edge no ltc6993-4 falling-edge yes output polarity (pol bit) each variety of ltc6993 also offers the ability to invert the output, producing negative pulses. this option is programmed, along with n div , by the choice of divcode. ( the previous section describes how to program divcode using the div pin). figure 3. non-retriggering timing diagram (ltc6993-1, pol = 0) figure 4. retriggering timing diagram (ltc6993-2, pol = 0) t pd t width t retrig trig out t out t pd t pd t pd t out t out 69931234 f04 t pd trig out t pd t arm t width t out t out t out 69931234 f03
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 15 69931234fa o pera t ion changing divcode after start-up following start- up, the a/d converter will continue monitoring v div for changes. changes to divcode will be recognized slowly, as the ltc6993 places a priority on eliminating any wandering in the divcode. the typical delay depends on the difference between the old and new divcode settings and is proportional to the master oscillator period. t divcode = 16 ? (?divcode + 6) ? t master a change in divcode will not be recognized until it is stable, and will not pass through intermediate codes. a digital filter is used to guarantee the divcode has settled to a new value before making changes to the output. how- ever, if the output pulse is active during the transition, the pulse width can take on a value between the two settings. start-up time when power is first applied, the power-on reset (por) circuit will initiate the start-up time, t start . the out pin is held low during this time. the typical value for t start ranges from 0.5 ms to 8 ms depending on the master oscil- lator frequency (independent of n div ): t start( typ ) = 500 ? t master during start-up, the div pin a/d converter must deter- mine the correct divcode before an output pulse can be generated. the start-up time may increase if the supply or div pin voltages are not stable. for this reason, it is recommended to minimize the capacitance on the div pin so it will properly track v + . less than 100 pf will not extend the start-up time. the divcode setting is recognized at the end of the startup up. if pol = 1, the output will transition high. otherwise (if pol = 0) out simply remains low. at this point, the ltc6993 is ready to respond to rising/falling edges on the trig input. figure 5a. divcode change from 0 to 2 figure 5b. divcode change from 2 to 0 figure 6. start-up timing diagram div 500mv/div trig 2v/div out 2v/div ltc6993-1 v + = 3.3v r set = 200k 200s/div 69931234 f05a 512s 256s 4s div 500mv/div trig 2v/div out 2v/div ltc6993-1 v + = 3.3v r set = 200k 200s/div 69931234 f05b 512s 256s 4s trig v + out t start (trig ignored) t out pol = 1 69931234 f06 pol = 0
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 16 69931234fa a pplica t ions i n f or m a t ion basic operation the simplest and most accurate method to program the ltc6993 is to use a single resistor, r set , between the set and gnd pins. the design procedure is a four step process. alternatively, linear technology offers the easy-to-use timerblox designer tool to quickly design any ltc6993 based circuit. download the free timerblox designer software at www.linear.com/timerblox. step 1: select the pol bit setting. the ltc6993 can generate positive or negative output pulses, depending on the setting of the pol bit. the pol bit is the divcode msb, so any divcode 8 has pol = 1 and produces active-low pulses. step 2: select ltc6993 v ersion. tw o input-related choices dictate the proper ltc6993 for a given application: ? is trig a rising or falling-edge input? ? should retriggering be allowed? use t able 2 to select a particular variety of ltc6993. step 3: select the n div frequency divider value. as explained earlier, the voltage on the div pin sets the divcode which determines both the pol bit and the n div value. for a given output pulse width (t out ), n div should be selected to be within the following range: t out 16s n div t out 1s (1) to minimize supply current, choose the lowest n div value. however, in some cases a higher value for n div will provide better accuracy (see electrical characteristics). table 1 can also be used to select the appropriate n div values for the desired t out . with pol already chosen, this completes the selection of divcode. use table 1 to select the proper resistor divider or v div /v + ratio to apply to the div pin. step 4: calculate and select r set . the final step is to calculate the correct value for r set using the following equation: r set = 50k 1s ? t out n div (2) select the standard resistor value closest to the calculated value. example: design a one-shot circuit that satisfies the fol- lowing requirements: ? t out = 100s ? negative output pulse ? rising-edge t rigger input ? retriggerable input ? minimum power consumption step 1: select the pol bit setting. for inverted (negative) output pulse, choose pol = 1. step 2: select the ltc6993 v ersion. a rising-edge retriggerable input requires the ltc6993 - 2. step 3: select the n div frequency divider value. choose an n div value that meets the requirements of equation (1), using t out = 100s: 6.25 n div 100 potential settings for n div include 8 and 64. n div = 8 is the best choice, as it minimizes supply current by us- ing a large r set resistor. pol = 1 and n div = 8 requires divcode = 14. using table 1, choose r1 = 102 k and r2 = 976k values to program divcode = 14. step 4: select r set . calculate the correct value for r set using equation (2): r set = 50k 1s ? 100s 8 = 625k
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 17 69931234fa since 625 k is not available as a standard 1% resistor, substitute 619 k if a C0.97% shift in t out is acceptable. otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. the completed design is shown in figure 7. a pplica t ions i n f or m a t ion figure 7. 100s negative pulse generator ltc6993-2 trig gnd set out v + div r1 102k divcode = 14 69931234 f07 2.25v to 5.5v r2 976k 0.1f r set 625k figure 8. voltage-controlled pulse width ltc6993 trig gnd set out v + div r1 c1 0.1f 69931234 f08 v + r2 r set r mod v ctrl 69931234 f09 ltc6993 trig gnd set out v + div c1 0.1f r1 r2 v + r mod r set ? + v + 0.1f 1/2 ltc6078 ltc1659 v + v cc ref gnd v out p d in clk cs/ld n div ? r mod 50k t out = d in = 0 to 4095 ? ? 1+ r mod r set d in 4096 1s 0.1f voltage-controlled pulse width with one additional resistor, the ltc6993 output pulse width can be manipulated by an external voltage. as shown in figure 8, voltage v ctrl sources/sinks a current through r mod to vary the i set current, which in turn modulates the pulse width as described in equation (3). t out = n div ? r mod 50k ? 1s 1 + r mod r set ? v ctrl v set (3) digital pulse width control the control voltage can be generated by a dac (digital-to- analog converter), resulting in a digitally-controlled pulse width. many dacs allow for the use of an external refer- ence. if such a dac is used to provide the v ctrl voltage, the v set dependency can be eliminated by buffering v set and using it as the dacs reference voltage, as shown in figure 9. the dacs output voltage now tracks any v set variation and eliminates it as an error source. the set pin cannot be tied directly to the reference input of the dac because the current drawn by the dacs ref input would affect the pulse width. figure 9. digitally controlled pulse width
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 18 69931234fa i set extremes (master oscillator frequency extremes) when operating with i set outside of the recommended 1.25a to 20 a range, the master oscillator operates outside of the 62.5 khz to 1 mhz range in which it is most accurate. the oscillator will still function with reduced accuracy for i set < 1.25 a. at approximately 500 na, the oscillator will stop. under this condition, the output pulse can still be initiated, but will not terminate until i set increases and the master oscillator starts again. at the other extreme, it is not recommended to operate the master oscillator beyond 2 mhz because the accuracy of the div pin adc will suffer. settling time following a 2 or 0.5 step change in i set , the output pulse width takes approximately six master clock cycles (6 ? t master ) to settle to within 1% of the final value. an example is shown in figure 10, using the circuit in figure 8. coupling error the current sourced by the set pin is used to bias the internal master oscillator. the ltc6993 responds to changes in i set almost immediately, which provides excel- lent settling time. however, this fast response also makes the set pin sensitive to coupling from digital signals, such as the trig input. even an excellent layout will allow some coupling between trig and set. additional error is included in the speci- fied accuracy for n div = 1 to account for this. figure 11 shows that 1 supply variation is dependent on coupling from rising or falling trigger inputs and, to a lesser extent, output polarity. a very poor layout can actually degrade performance further. the pcb layout should avoid routing set next to trig (or any other fast-edge, wide-swing signal). a pplica t ions i n f or m a t ion figure 10. typical settling time v ctrl 2v/div trig 5v/div out 5v/div pulse width 2s/div ltc6993-1 v + = 3.3v divcode = 0 r set = 200k r mod = 464k t out = 3s and 6s 20s/div 69931234 f10 supply (v) 2 ?1.0 drift (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 3 4 69931234 f11 ?0.6 0.6 0.8 0.2 5 6 r set = 50k n div = 1 ltc6993-1 pol = 0 ltc6993-1 pol = 1 ltc6993-3 pol = 1 ltc6993-3 pol = 0 figure 11. t out drift vs supply voltage
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 19 69931234fa a pplica t ions i n f or m a t ion table 2. typical supply current condition typical i s(idle) typical ?i s(active) * n div 64 v + ? n div ? 7pf + 4pf ( ) t out + v + 500k + 2.2 ? i set + 50a v + ? duty cycle t out ? n div ? 5pf + 18pf + c load ( ) n div 512 v + ? n div ? 7pf t out + v + 500k + 1.8 ? i set + 50a v + ? duty cycle t out ? c load *ignoring resistive loads (assumes r load = ) power supply current the electrical characteristics table specifies the supply current while the part is idle ( waiting to be triggered). i s(idle) varies with the programmed t out and the supply voltage. once triggered, the instantaneous supply current increases to i s(active) while the timing circuit is active. i s(active) = i s(idle) + ?i s(active) the average increase in supply current ?i s(active) de- pends on the output duty cycle ( or negative duty cycle, if pol = 1), since that represents the percentage of time that the circuit is active. i s(idle) and ?i s(active) can be estimated using the equations in table 2. figure 12 shows how the supply current increases from i s(idle) as the input frequency increases . the increase is smaller at higher n div settings. duty cycle (%) idle power supply current (a) 150 200 250 80 69931234 f12 100 50 0 20 40 60 100 v + = 3.3v duty cycle = f in ? t out 1, r set = 50k 8, r set = 50k 1, r set = 100k 1, r set = 800k c load = 5pf r load = figure 12. i s(active) vs output duty cycle
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 20 69931234fa supply bypassing and pcb layout guidelines the ltc6993 is an accurate monostable multivibrator when used in the appropriate manner. the part is simple to use and by following a few rules, the expected performance is easily achieved. adequate supply bypassing and proper pcb layout are important to ensure this. figure 13 shows example pcb layouts for both the sot-23 and dcb packages using 0603 sized passive components. the layouts assume a two layer board with a ground plane layer beneath and around the ltc6993. these layouts are a guide and need not be followed exactly. 1. connect the bypass capacitor, c1, directly to the v + and gnd pins using a low inductance path. the connection from c1 to the v + pin is easily done directly on the top layer. for the dcb package, c1s connection to gnd is also simply done on the top layer. for the sot-23, out can be routed through the c1 pads to allow a good c1 gnd connection. if the pcb design rules do not allow that, c 1 s gnd connection can be accomplished through multiple vias to the ground plane. multiple vias for both the gnd pin connection to the ground plane and the c 1 connection to the ground plane are recommended to minimize the inductance. capacitor c1 should be a 0.1f ceramic capacitor. 2. place all passive components on the top side of the board. this minimizes trace inductance. 3. place r set as close as possible to the set pin and make a direct, short connection. the set pin is a cur- rent summing node and currents injected into this pin directly modulate the output pulse width. having a short connection minimizes the exposure to signal pickup. 4. connect r set directly to the gnd pin. using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. use a ground trace to shield the set pin. this provides another layer of protection from radiated signals. 6. place r1 and r2 close to the div pin. a direct, short connection to the div pin minimizes the external signal coupling. 69931234 f13 ltc6993 trig gnd set out v + div c1 0.1f r1 r2 r set v + v + div set out gnd trig c1 r1 r2 v + r set dcb package trig gnd set out v + div r2 v + r set tsot-23 package r1 c1 figure 13. supply bypassing and pcb layout a pplica t ions i n f or m a t ion
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 21 69931234fa typical a pplica t ions missing pulse detector ltc6993-2 trig gnd set out v + div r1 102k divcode = 14 (n div = 8, pol = 1) 69931234 ta02a 3.3v 0.1f r2 976k r set 402k trig 2v/div out 2v/div 50s/div 69931234 ta02b 25khz input 64s use retriggerable one shot with output inverted. output remains low as long as retrigger occurs within t out = 64s. reset = open run = gnd (closed) 20ms frame rate generator 1.5ms reference pulse 5v 20ms period 5v r4 976k r7 10k c1 0.01f r5 102k r3 121k 5v r1 1m c2 0.01f 1.5ms pulse 1.5ms cal trim 69931234 ta03 r2 280k r8 143k r6 10k ltc6991 out v + div rst gnd set ltc6993-1 out v + div trig gnd set 1.5ms radio control servo reference pulse generator pulse in 10s output pulse generator 100s delay generator 5v r4 182k c1 0.01f c2 0.1f r5 976k r6 78.7k 10s pulse in 10s pulse out 100s delay out ltc6993-1 out v + div trig gnd set 5v r1 976k r2 102k r3 61.9k ltc6993-1 out v + div trig gnd set pulse delay generator
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 22 69931234fa typical a pplica t ions trigger 1.5ms pulse generator 20ms retrigger lockout interval 5v r1 1m c2 0.1f 0.1f pulse out r2 280k r3 147k r9 10k r5 100k m1 2n7002 trigger pulse in 20ms retrigger lockout retrigger lockout time 1.5ms pulse out r4 243k 69931234 ta05 r7 392k r6 1m 5v ltc6993-1 out v + div trig gnd set ltc6993-1 trig gnd set out v + div rc servo pulse generator controlled retrigger lockout time interval retriggerable staircase reset pulse generator 5v r1 280k c2 0.1f c1 1f r6 20k r2 1m r9 100k r10 10k r11 2k d1 1n4148 r7 10k staircase out r8 4.99k 5v 0.1f v out r3 147k u4 2n7002 ? + u3 lt1490 5v pulses in 0.1f pulse frequency-to-voltage converter ? + u2 lt1490 reset staircase reset staircase out pulses in reset 69931234 ta06 ramp resets after 1.5ms if no pulses applied ltc6993-2 out v + div trig gnd set staircase generator with reset
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 23 69931234fa 5v voltage variable output pulse width ramp 0.1f q4 2n2219a q2 2n2907 r6 10k pulse in q1 2n2907 5v r14 976k c4 0.1f pulse out stretched pulse out r15 102k r13 113k r16 140k 1s to 10s input pulse width r2 182k c2 0.1f r5 976k 69931234 ta07 r3 392k 5v ? + q3 2n2219a c1 2200pf r7 10k ramp voltage proportional to input pulse width 500s ramp reset timer u4 lt1638 r1 10k 5v r4 4.99k u2 lt1009 2.5v ltc6993-1 out v + div trig gnd set ltc6993-3 out v + div trig gnd set r1 1m r4 2k 5 seconds on off trigger in d1 1n4004 24v c2 0.1f q1 2n2219a 100ma solenoid danfoss 042 n024d type ak024d r2 887k 69931234 ta08 r3 118k 5v trigger ltc6993-1 out v + div trig gnd set r1 1m r4 15k run reset timed (5s) turn-off after loss of input pulses d1 1n4148 12v no coto 1022 relay 9001-12-01 l c2 0.1f q1 2n2219a r2 887k 69931234 ta09 r3 118k 5v enable pulses c 1 ltc6993-2 out v + div trig gnd set pulse stretcher on-time programmable pulsed solenoid driver safety time-out relay driver typical a pplica t ions
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 24 69931234fa dcb package 6-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1715 rev a) p ackage descrip t ion s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref 3.00 0.10 (2 sides) 2.00 0.10 (2 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (tbd) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.35 0.10 (2 sides) 1 3 64 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dcb6) dfn 0405 0.25 0.05 0.50 bsc pin 1 notch r0.20 or 0.25 45 chamfer 0.25 0.05 1.35 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.70 0.05 3.55 0.05 package outline 0.50 bsc
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 25 69931234fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 7/11 revised description section 1 to 3 added text to basic operation paragraph in applications information section 15
ltc6993-1/ltc6993-2 ltc6993-3/ltc6993-4 26 69931234fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0711 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1799 1mhz to 33mhz thinsot silicon oscillator wide frequency range ltc6900 1mhz to 20mhz thinsot silicon oscillator low power, wide frequency range ltc6906/ltc6907 10khz to 1mhz or 40khz thinsot silicon oscillator micropower, i supply = 35a at 400khz ltc6930 fixed frequency oscillator, 32.768khz to 8.192mhz 0.09% accuracy, 110s start-up time, 105a at 32khz ltc6990 timerblox: voltage-controlled silicon oscillator fixed-frequency or voltage-controlled operation ltc6991 timerblox: resettable low frequency oscillator clock periods up to 9.5 hours ltc6992 timerblox: voltage-controlled pulse width modulator ( pwm ) simple pwm with wide frequency range ltc6994 timerblox: delay block/debouncer delay rising edge, falling edge or both edges consecutive test sequencer ltc6994-1 gnd set 30s 2s r2 1000k 0.1f r3 887k r1 63.4k r10 25k delay adjust r9 274k 5v v + 5v delay 2s to 30s delay start test sequence trig out div ltc6993-1 gnd set 0.1f r6 191k v + 5v test 1 trig out div ltc6993-3 one second duration sequential test pulses after an adjustable delay time gnd set 0.1f r7 191k v + 5v test 2 test 3 shared div pin biasing for equal one-shot timers trig out div ltc6993-3 gnd set r8 191k r5 1000k r4 681k 69931234 ta10 v + 5v test 3 trig out div 0.1f test 2 test 1 start delay

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