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future technology devices internationa l ltd (ftdi) unit 1, 2 seaward place, centurion business park, glasgow, g41 1hh, united kingdom tel.: +44 (0) 141 429 2777 fax: + 44 (0) 141 429 2758 e - mail (support): support1@ftdichip.com web: http://www.vinculum.com neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or re produced in any material or electronic form without the prior written consent of the copyright holder. this product and its documentation are supplied on an as - is basis and no warranty as to their suitability for any particular purpose is either made or implied. future t echn ology devices international ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appl iance, device or system in which the failure of the product might reasonably be expected to result in personal injury. this document provides preliminar y information that may be subject to change without notice. no freedom to use patents or other intellect ual property rights is implied by the publication of this document. future technology devices international ltd, unit 1, 2 seaward place, centurion business park, glasgow, g41 1hh , united kingdom. scotland registered number: sc136640 copyright ? 2010 futu re technology devices international limited future technology devices international ltd. v2dip1 - 64 vncl2 - 64q development module datasheet document reference no.: ft_000165 version 1.01 issue date: 20 10 - 0 5 - 25
copyright ? 2010 future technology devices international limited 1 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 1 introduction v2dip1 - 64 module is designed to allow rapid development of des igns using the vnc2 - 64q ic. the v2dip1 - 64 is supplied as a pcb designed to fit into a 60 pin 0. 8 wide 0.1 pitch dip socket .the module provides access to the ua r t , parallel fifo, and spi interface pins o f the vnc2 - 64q device, via its io bus pins. one usb port is accessed via a type a usb connector. figure 1 . 1 - v2dip1 64 the vnc2 is the second of f t di s v inculum family of embedded dual usb host controller devices. the vnc2 device provides usb host i nt erfac ing capability for a variety of different usb device classes including support for boms (bulk only mass storage), printer, hid (human interface devices). for mass storage devices such as usb flash drives, vnc2 also transparently handles the f a t f ile structure . c ommunicat ion with non usb devices such as a low cost microcontroller is accomplished via either ua r t , spi or parallel fifo interfaces. the vnc2 provides a new cost effective solution for providing usb host capability into products that previou sly did not have the hardware resources available. the vnc2 supports the capability to enable customers to develop custom firmware using the vinculum ii development software tool suite. the development tools support compiler, linker and debugger tools co mplete within an integrated development environment (ide). the vinculum - ii vnc2 family of devices are available in pb - free (rohs compliant) 32 - l ead lqfp, 32 - l ead qfn, 48 - l ead lqfp, 48 - l ead qfn, 64 - lead lqfp and 64 - l ead qfn packages
copyright ? 2010 future technology devices international limited 2 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 table of conten ts 1 introduction ................................ ................................ .... 1 2 features ................................ ................................ .......... 3 3 pin out and signal description ................................ ........ 4 3.1 module pin out ................................ ................................ .......... 4 3.2 pin signal description ................................ ............................... 6 3.3 default inte rface i/o pin configuration ................................ .... 8 3.4 uart interface ................................ ................................ ....... 10 3.4.1 signal description C uart interface ................................ ........................... 1 0 3.5 serial peripheral interface (spi) ................................ ............ 11 3.5.1 signal description - spi slave ................................ ................................ ... 11 3.5.2 signal d escription - spi master ................................ ................................ . 12 3.6 parallel fifo interface - asynchronous mode ......................... 13 3.6.1 signal description - parallel fifo interface ................................ ................. 13 3.6.2 timing diagram C asynchronous fifo mode read and write cycle ................ 14 3.7 parallel fifo interface - synchronous mode ............................. 15 3.7.1 timing diagram C synchronous fifo mode read and write cycle ................. 15 3.8 debugger interface ................................ ................................ . 17 3.8.1 ignal description - debugger interface ................................ ....................... 17 4 firmware ................................ ................................ ....... 18 4.1 firmware support ................................ ................................ ... 18 4.2 available firmware ................................ ................................ . 18 4.3 firmware upgrades ................................ ................................ . 18 5 external circuit configura tion ................................ ....... 19 5.1 adding a second usb port ................................ ....................... 19 6 mechanical dimensions ................................ ................. 20 7 schematic diagram ................................ ....................... 21 8 contact information ................................ ...................... 22 appendix a C references ................................ ................................ . 23 appendix b C list of figures and tables ................................ .......... 24 list of figures ................................ ................................ ................. 24 list of tables ................................ ................................ ................... 24 appendix c C revision history ................................ ......................... 25
copyright ? 2010 future technology devices international limited 3 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 2 features the v2dip1 - 64 incorporates the following features : uses ftdis vnc2 - 64q embedded usb host controller ic device usb single a type usb to interface wi th usb peripheral devices . second usb interface port available via module header pins if required . uart, parallel fifo and spi interfaces can be programmed to a choice of available i/o pins single 5v supply input from dil connectors or 5v supplied via usb vbus slave interface or debugger module . auxiliary 3.3 v / 200 ma power output to external logic all vnc2 signals available on 0.8 wid e, 0.1 pitch dil male connector s . power and traffic indicator leds v2dip1 - 64 is a pb - free, rohs complaint developm ent module debugger interface pin available on dil pins or via 6 way male header which interfaces to separate debugger module. firmware upgrades via uart or debug ger interface . foc s oftware development suite of tools to create customised firmware includes a compiler , linker , debugger and assembler all wrapped up in an easy to use integrated design environment gui.
copyright ? 2010 future technology devices international limited 4 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3 pin out and signal description 3.1 module pin out figure 3 . 1 - v2dip1 - 64 module pin out (top v iew)
copyright ? 2010 future technology devices international limited 5 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 figure 3 . 2 - v2dip1 - 64 module pin out (bottom view)
copyright ? 2010 future technology devices international limited 6 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.2 pin signal description pin no. vnc2 signal name pin name on pcb t ype description j1 - 1 io bus26 io 26 i/o 5v safe bidirectional data / con trol bus bit 26 j1 - 2 io bus27 io 27 i/o 5v safe bidirectional data / control bus bit 27 j1 - 3 io bus28 io 28 i/o 5v safe bidirectional data / control bus bit 28 j1 - 4 io bus29 io 29 i/o 5v safe bidirectional data / control bus bit 29 j1 - 5 io bus30 io 30 i/o 5v safe bidirectional data / control bus bit 30 j1 - 6 io bus31 io 31 i/o 5v safe bidirectional data / control bus bit 31 j1 - 7 io bus32 io 32 i/o 5v safe bidirectional data / control bus bit 32 j1 - 8 io bus33 io 33 i/o 5v safe bidirectional data / control bus bit 33 j1 - 9 io bus34 io 34 i/o 5v safe bidirectional data / control bus bit 34 j1 - 1 0 gnd gnd pwr module ground supply pin j1 - 1 1 - - - not connected j1 - 1 2 5v0 5v0 pwr input 5.0v module supply pin. this pin can be used to provide the 5.0 v in put to the v2dip1 - 64 when the v2dip1 - 64 is not powered from the usb connector (vbus) or the debugger interface. also connected to dil connector pins j1 - 12, j1 - 13 and j1 - 19 and j3 - 6 . j1 - 1 3 5v0 5v0 pwr input 5.0v module supply pin. this pin can be used to provide the 5.0v in put to the v2dip1 - 64 when the v2dip1 - 64 is not powered from the usb connector (vbus) or the debugger interface. also connected to dil connector pins j1 - 12, j1 - 13 and j1 - 19 and j3 - 6 . j 1 - 14 io bus5 io5 i/o 5v safe bidirectional data / control bus bit 5 j1 - 1 5 io bus6 io6 i/o 5v safe bidirectional data / control bus bit 6 j1 - 16 io bus7 io7 i/o 5v safe bidirectional data / control bus bit 7 j1 - 17 io bus8 io8 i/o 5v safe bidirectional data / control bus bit 8 j1 - 18 io bus9 io9 i/o 5v safe bidirectional data / control bus bit 9 j1 - 19 5v0 5v0 pwr input 5.0v module supply pin. this pin can be used to provide the 5.0v in put to the v2dip1 - 64 when the v2dip1 - 64 is not powered from the usb connector (vbus) or the debugger interface. also connected to dil connector pins j1 - 12, j1 - 13 and j1 - 19 and j3 - 6 . j1 - 20 io bus10 io1 0 i/o 5v safe bidirectional data / control bus bit 10 j1 - 21 io bus11 io 11 i/o 5v safe bidirectional data / control bus bit 11 j1 - 22 usbd1 p u1 p i/o usb host / slav e port 1 - usbdata signal plus with integrated pull up / pull down resis tor. module has on board 27 usb series resistor. this pin can be brought out along with pin j1 - 23 to provide a second usbport,if required. j1 - 23 usbd1 m u1 m i/o usb host / slave port 1 - usbdata signal minus with integrated pull up / pull down resis tor. module has on board 27 usb series resistor. this pin can be brought out along with pin j1 - 22 to provide a second usb port,if required. j1 - 24 io bus12 io 12 i/o 5v safe bidirect ional data / control bus bit 12 j1 - 25 gnd gnd pwr module ground supply pin j1 - 26 io bus13 io 13 i/o 5v safe bidirectional data / control bus bit 13 j1 - 27 io bus14 io14 i/o 5v safe bidirectional data / control bus bit 14 j1 - 28 io bus15 io 15 i/o 5v safe bidirectional data / control bus bit 15 j1 - 29 io bus16 io16 i/o 5v safe bidirectional data / control bus bit 16 j1 - 30 io bus17 io 17 i/o 5v safe bidirectional data / control bus bit 17 j2 - 1 io bus43 io 43 i/o 5v safe bidirectional data / control bus bit 26 j2 - 2 io bus42 io 42 i/o 5v safe bidirectional data / control bus bit 27 j2 - 3 io bus41 io 41 i/o 5v safe bidirectional data / control bus bit 28 j2 - 4 io bus40 io 40 i/o 5v safe bidirectional data / control bus bit 29 j2 - 5 io bus39 io 3 9 i/o 5v s afe bidirectional data / control bus bit 30 j2 - 6 io bus38 io 38 i/o 5v safe bidirectional data / control bus bit 31 j2 - 7 io bus37 io 3 7 i/o 5v safe bidirectional data / control bus bit 32 table 3 . 1 - pin s ignal descriptions
copyright ? 2010 future technology devices international limited 7 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 pin no. name pin name on pcb t ype description j2 - 8 io bus36 io 36 i/o 5v safe bidirectional data / control bus bit 33 j2 - 9 io bus35 io 3 5 i/o 5v safe bidirectional data / control bus bit 34 j2 - 1 0 gnd gnd pwr module ground supply pin j2 - 1 1 - - - not connected j2 - 1 2 3 v 3 3v3 3.3v output from v 2 dip1 s on board 3.3v l.d.o. 3.3v output from v2dip 1 s on board 3.3v l.d.o. j2 - 1 3 3 v 3 3v3 3.3v output from v 2 dip1 s on board 3.3v l.d.o. 3.3v output from v2dip 1 s on board 3.3v l.d.o. j 2 - 1 4 io bus4 io4 i/o 5v safe bidirectional data / control bus bit 4 j2 - 1 5 io bus3 io3 i/o 5v safe bidirectional data / control bus bit 3 j2 - 16 io bus2 io2 i/o 5v safe bidirectional data / control bus bit 2 j2 - 17 io bus1 io1 i/o 5v safe bidirectional da ta / control bus bit 1 j2 - 18 io bus0 io0 i/o 5v safe bidirectional data / control bus bit 0 j2 - 19 3 v 3 3v3 3.3v output from v dip1 s on board 3.3v l.d.o. 3.3v output from v2dip 1 s on board 3.3v l.d.o. j2 - 20 prog# p r g# input this pin is used in combinatio n with the reset# pin and the uart interface to program firmware into the vnc2 . j2 - 21 reset# r st # input can be used by an external device to reset the vnc2. this pin is also used in combination with prog# and the uart interface to program firmware into the vnc2 j2 - 22 io bus25 io 25 i/o 5v safe bidirectional data / control bus bit 25 j2 - 23 io bus24 io24 i/o 5v safe bidirectional data / control bus bit 24 j2 - 24 io bus23 io 23 i/o 5v safe bidirectional data / control bus bit 23 j2 - 25 gnd gnd pwr module ground supply pin j2 - 26 io bus22 io 22 i/o 5v safe bidirectional data / control bus bit 22 j2 - 27 io bus21 io21 i/o 5v safe bidirectional data / control bus bit 21 j2 - 28 io bus20 io 20 i/o 5v safe bidirectional data / control bus bit 20 j2 - 29 io bus19 io19 i/o 5v safe bidirectional data / control bus bit 19 j2 - 30 io bus18 io 18 i/o 5v safe bidirectional data / control bus bit 18 table 3.1 - pin signal descriptions
copyright ? 2010 future technology devices international limited 8 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.3 default interface i/o pin configuration the vnc2 - 64 q device device is delivered witho ut any firmware pre - loaded. as such the iomux will provide a default pinout as shown in table 3 . 2 pin no. pin name on pcb t ype data and control bus configuration options ua r t interface spi slave interface spi master in terface parallel fifo interface debugger interface j2 - 1 8 io0 i/o na na na na debug_if j2 - 28 io20 i/o uart_txd na na na na j2 - 27 io21 i/o uart_rxd na na na na j2 - 26 io22 i/o uart_rts# na na na na j2 - 24 io23 i/o uart_cts# na na na na j2 - 23 io24 i/o ua rt_dtr# na na na na j2 - 22 io25 i/o uart_dsr# na na na na j1 - 1 io26 i/o uart_dcd# na na na na j1 - 2 io27 i/o uart_ri# na na na na j1 - 3 io28 i/o uart_tx_active na na na na j1 - 7 io32 i/o na spi_s0_clk na na na j1 - 8 io33 i/o na spi_s0_mosi na na na j1 - 9 io34 i/o na spi_s0_miso na na na j2 - 9 io35 i/o na spi_s0_cs# na na na j2 - 8 io36 i/o na spi_s1_clk na na na j2 - 7 io37 i/o na spi_s1_mosi na na na j2 - 6 io38 i/o na spi_s1_miso na na na j2 - 5 io39 i/o na spi_s1_cs# na na na j2 - 4 io40 i/o na na spi_m_clk na na j2 - 3 io41 i/o na na spi_m_mosi na na j2 - 2 io42 i/o na na spi_m_miso na na j2 - 1 io43 i/o na na spi_m_cs# na na j2 - 14 io4 i/o na na na fifo_data[0] na j1 - 14 io5 i/o na na na fifo_data[1] na j1 - 15 io6 i/o na na na fifo_data[2] na table 3 . 2 - default interface i/o pin configuration
copyright ? 2010 future technology devices international limited 9 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 pin no. pin name on pcb t ype data and control bus configuration options ua r t interface spi slave interface spi master interface parallel fifo interface debugg er interface j1 - 16 io7 i/o na na na fifo_data[3] na j1 - 17 io8 i/o na na na fifo_data[4] na j1 - 18 io9 i/o na na na fifo_data[5] na j1 - 20 io10 i/o na na na fifo_data[6] na j1 - 21 io11 i/o na na na fifo_data[7] na j1 - 24 io12 i/o na na na fifo_rxf# na j 1 - 26 io13 i/o na na na fifo_txe# na j1 - 27 io14 i/o na na na fifo_rd# na j1 - 28 io15 i/o na na na fifo_wr# na j1 - 29 io 16 i/o na na na fifo_oe# na table 3.2 - default interface i/o pin configuration
copyright ? 2010 future technology devices international limited 10 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.4 uart interface when the data and control buses are co nfigured in uart mode, the interface implements a standard asynchronous serial uart port with flow control. the uart can support b aud rates from 300 baud to 3 m baud. further details on t he uart interface are available on the the vinculum - ii datasheet pleas e refer to: - ftdi website 3.4.1 signal description C uart interface the uart signals can be programmed to a choice of available i/o pin s . table 3 . 3 explai ns the available pins for each of the uart signals . available pins name ty pe description j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 uart_txd output transmit asynchronous data output j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 uart_rxd input receive asynchronous data input j2 - 16 , j1 - 15 , j1 - 20 , j1 - 27 , j2 - 30 , j2 - 26 , j1 - 1 , j1 - 5 , j1 - 9 , j2 - 6 , j2 - 2 uart_rts# output request to send control output j2 - 15 , ji - 16 , j1 - 21 , j1 - 28 , j2 - 29 , j2 - 24 , j1 - 2 , j1 - 6 , j2 - 9 , j2 - 5 , j2 - 1 uart_cts# input clear to send control input j2 - 14 , j1 - 17 , j1 - 2 4 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 uart_dtr# output data acknowledge (data terminal ready control) output j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 uart_dsr# input data request (data set ready control) input j 2 - 16 , j1 - 15 , j1 - 20 , j1 - 27 , j2 - 30 , j2 - 26 , j1 - 1 , j1 - 5 , j1 - 9 , j2 - 6 , j2 - 2 uart_dcd# input data carrier detect control input j2 - 15 , ji - 16 , j1 - 21 , j1 - 28 , j2 - 29 , j2 - 24 , j1 - 2 , j1 - 6 , j2 - 9 , j2 - 5 , j2 - 1 uart_ri# input ring indicator control input. ri# low can be used to resume the pc usb host controller from suspend. j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 uart_tx_active output enable transmit data for rs485 designs . u art_tx_active may be used to signal that a transmit operation is in prog ress. the u art_tx_active signal will be set high one bit - time before data is transmitted and return low one bit time after the last bit of a data frame has been transmitted table 3 . 3 - data and control bus si gnal mode options C uart
copyright ? 2010 future technology devices international limited 11 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.5 serial peripheral interface (spi) the vnc2 - 64 q has one spi master module and two spi slave modules. the se m odules are described more fully in a vinculum - ii datasheet please refer to: - ftdi website 3.5.1 signal description - spi slav e the spi slave signals can be programmed to a choice of available i/o pin s . table 3 . 4 explains the available pins for each of the spi slave signals . available pins name type description j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 spi_s0_clk spi_s1_clk input slave clock input j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 spi_s0_mosi spi_s1_mosi input /output master out slave in synchronous data from master to slave j2 - 16 , j1 - 15 , j1 - 20 , j1 - 27 , j2 - 30 , j2 - 26 , j1 - 1 , j1 - 5 , j1 - 9 , j2 - 6 , j2 - 2 spi_s0_miso spi_s1_miso output master in slave out synchronous data from slave to master j2 - 15 , ji - 16 , j1 - 21 , j1 - 28 , j2 - 29 , j2 - 24 , j1 - 2 , j1 - 6 , j2 - 9 , j2 - 5 , j2 - 1 spi_s0_ s s# spi_s 1_ s s# input slave chip select table 3 . 4 - data and contro l bus signal mode options C spi slave
copyright ? 2010 future technology devices international limited 12 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.5.2 signal description - spi master the spi master signals can be programmed to a choice of available i/o pin s . table 3 . 5 shows the spi master signals and the available pins that they can be mapped. available pins name type description j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 spi_m_clk outp ut spi master clock input j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 spi_m_mosi output master out slave in synchronous data from master to slave j2 - 16 , j1 - 15 , j1 - 20 , j1 - 27 , j2 - 30 , j2 - 26 , j1 - 1 , j1 - 5 , j1 - 9 , j2 - 6 , j2 - 2 spi_m_ miso input master in slave out synchronous data from slave to master j2 - 15 , ji - 16 , j1 - 21 , j1 - 28 , j2 - 29 , j2 - 24 , j1 - 2 , j1 - 6 , j2 - 9 , j2 - 5 , j2 - 1 spi_m_ s s_0# output active low slave select 0 from master to slave 0 j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 spi_m_ s s_1# output active low slave select 1 from master to slave 1 table 3 . 5 - data and control bus signal mode options C spi master
copyright ? 2010 future technology devices international limited 13 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.6 parallel fifo interface - asynchronous mode the parallel fifo asynchronous mode , functionally the same as the parallel fifo interface present in vdip1 , has an eight bit parallel data bus, individual read and write strobes and two hardware flow control signals. 3.6.1 signal description - parallel fifo inter face the parallel fifo interface signals can be programmed to a choice of available i/o pin s . shows the parallel fifo interface signals and the pins that they can be mapped available pins name type description j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 fifo_data[0] i/o fifo data bus bit 0 j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 fifo_data[1] i/o fifo data bus bit 1 j2 - 16 , j1 - 15 , j1 - 20 , j1 - 27 , j2 - 30 , j2 - 26 , j1 - 1 , j1 - 5 , j1 - 9 , j2 - 6 , j2 - 2 fifo_d ata[2] i/o fifo data bus bit 2 j2 - 15 , ji - 16 , j1 - 21 , j1 - 28 , j2 - 29 , j2 - 24 , j1 - 2 , j1 - 6 , j2 - 9 , j2 - 5 , j2 - 1 fifo_data[3] i/o fifo data bus bit 3 j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 fifo_data[4] i/o fifo data bus bit 4 j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 fifo_data[5] i/o fifo data bus bit 5 j2 - 16 , j1 - 15 , j1 - 20 , j1 - 27 , j2 - 30 , j2 - 26 , j1 - 1 , j1 - 5 , j1 - 9 , j2 - 6 , j2 - 2 fifo_data[6] i/o fifo data bus bit 6 j2 - 15 , ji - 16 , j1 - 21 , j1 - 28 , j2 - 29 , j2 - 24 , j1 - 2 , j1 - 6 , j2 - 9 , j2 - 5 , j2 - 1 fifo_data[7] i/o fifo data bus bit 7 j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 fifo_rxf# output when high, do not read data from the fifo. when low, there is data available in the fifo which can be r ead by strobing rd# low, then high. j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 fifo_txe# output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing fifo_wr# high, then low. j 2 - 16 , j1 - 15 , j1 - 20 , j1 - 27 , j2 - 30 , j2 - 26 , j1 - 1 , j1 - 5 , j1 - 9 , j2 - 6 , j2 - 2 fifo_rd# input enables the current fifo data byte on d0...d7 when low. fetches the next fifo data byte (if available) from the receive fifo buffer when fifo_rd# goes from high to low j2 - 15 , ji - 16 , j1 - 21 , j1 - 28 , j2 - 29 , j2 - 24 , j1 - 2 , j1 - 6 , j2 - 9 , j2 - 5 , j2 - 1 fifo_wr# input writes the data byte on the d0...d7 pins into the transmit fifo buffer when fifo_wr# goes from high to low. table 3 . 6 - data and control bus s ignal mode options C parallel fifo interface
copyright ? 2010 future technology devices international limited 14 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.6.2 timing diagram C asynchronous fifo mode read and write cycle when in asynchronous fifo interface mode, the timing of a read and write operation on the fifo interface is shown in figure 3 . 3 and table 3 . 7 figure 3 . 3 C asynchronous fifo mode r ead and write cycle . t ime description min max unit t 1 rd # ina ctive to rxf# 1 14 ns t 2 rxf# ina ctive after rd# cycle 100 - ns t 3 rd # to data 1 14 ns t4 rd # active pulse width 30 - ns t5 rd# active after rxf# 0 - ns t6 wr# active to txe# inactive 1 14 ns t7 txe# inactive after wr# cycle 100 - ns t8 data to txe# active setup ti me 5 - ns t9 data hold time after wr# inactive 5 - ns t 1 0 wr# active pulse width 30 - ns t 1 1 wr# active after txe# 0 - ns table 3 . 7 - a synchronous fifo mode read cycle timing in asynchronous mode an extern al device can control data transfer driving fifo_wr# and fifo_rd# inputs. in contrast to synchronous mode, in asynchronous mode the 245 fifo module generates the output enable en# signal. en# signal is effectively the read signal rd#. current byte is ava ilable to be read when fifo_rd# goes low. when fifo_rd# goes high, fifo_rxf# output will also go high. it will only become low again when there is another byte to read. when fifo_wr# goes low fifo_txe# flag will always go high. fifo_txe# goes low again on ly when there is still space for data to be written in to the module.
copyright ? 2010 future technology devices international limited 15 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.7 parallel fifo interface - synchronous mode the parallel fifo synchronous mode has an eight bit data bus, indivi dual read and write strobes, two hardware flow control signals , an output e nable and a clock out. the synchronous fifo mode uses the parallel fifo interface signals detailed in table 3 . 6 and additional two signals detailed table 3 . 8 . available p ins name type description j2 - 14 , j1 - 17 , j1 - 24 , j1 - 29 , j2 - 28 , j2 - 23 , j1 - 3 , j1 - 7 , j2 - 8 , j2 - 4 fifo_oe# output fifo output enable j2 - 17 , j1 - 14 , j1 - 18 , j1 - 26 , j1 - 30 , j2 - 27 , j2 - 22 , j1 - 4 , j1 - 8 , j2 - 7 , j2 - 3 fifo_clkout output fifo output enable table 3 . 8 - data and control bus s ignal mode options C synchronous fifo mode 3.7.1 timing diagram C s ynchronous fifo mode read and write cycle when in synchronous fifo interface mode, the timing of a read and write operati on on the fifo interface are shown in figure 3 . 4 and table 3 . 9 figure 3 . 4 - synchronous fifo mode read and write cycle
copyright ? 2010 future technology devices international limited 16 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 t ime description min typical max uni t t1 clkout period - 20.83 - ns t2 clkout high period 9.38 10.42 11.46 ns t3 clkout low period 9.38 10.42 11.46 ns t4 clkout to rxf# 1 - 7.83 ns t5 clkout to read data valid 1 - 7.83 ns t6 oe# to read data valid 1 - 7.83 ns t7 clkout to oe# 1 - 7.83 ns t8 rd# setup time 12 - - ns t9 rd# hold time 0 - - ns t10 clkout to txe# 1 - - ns t11 write data setup time 12 - - ns t12 write data hold time 0 - - ns t13 wr # setup time 12 - - ns t14 wr # hold time 0 - - ns table 3 . 9 - synchronous fifo mode read and write cycle timing in synchronous mode data can be transmitted to and from the fifo module on each clock edge. an external device synchronises to the clkout output and it also has access to the output enable oe# input to control data flow. an external device should drive output enable oe# low before pulling rd# line down. when bursts of data are to be read from the module rd# should be kept low. rxf# remains low whe n there is still data to be read. similarly when bursts of data are to be written to the module wr# should be kept low. txe# remains low when there is still space available for the data to be written
copyright ? 2010 future technology devices international limited 17 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 3.8 debugger interface the purpose of the debugger interfa ce is to provide access to the vnc2 silicon/firmware debugger. the debug interface can be accessed via the appropriate pin on the dil connector or more easily, it can be accessed by connecting a debug module to the j3 connector. this debug module will give access to the debugger through a usb connection to a pc via the integrated development environment ( ide ) . the ide is a graphical interface to the vnc2 software development tool - chain and gives the following debug capabilities through the debugger interfac e : flash erase, write and program. application debug - application code can have breakpoints, be single stepped and can be halted. detailed internal debug - memory and register read/write access. the debugger interface , and how to use it, is further desc ribed in the following applications note vinculum - ii debug interface description 3.8.1 ignal description - debugger interface table 3 . 10 shows the signals and pins d escription for the debugger interface pin header j3 pin no. name name on pcb type description j3 - 1 io0 dbg i/o debugger interface j3 - 2 - [key] - not connected . used to make sure that the debug module is connected correctly. j3 - 3 gnd gnd pwr module ground supply pin j3 - 4 reset# rs t# input can be used by an external device to reset the vncl2. this pin is also used in combination with prog# an d the uart interface t o program firmware int o the vnc 2. j3 - 5 prog# pr g# input this pin is used in combination with the reset# pin an d the uart interface to p r ogram firmware into the vnc2 . j3 - 6 5v0 vcc pwr input 5.0v module supply pin. this pin can be used to provide the 5.0v in put to the v2dip 1 - 64 from the debugger interface when the v2dip1 - 64 is not powered from the usb connector (vbus) or the dil connector pins j1 - 12, j1 - 13 and j1 - 19 and j3 - 6 . table 3 . 10 - s ignal name and description C debugger interface
copyright ? 2010 future technology devices international limited 18 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 4 firmware 4.1 firmware support the vnc2 on the v2dip1 - 64 can be programmed with the customers own firmware created using the vinculum ii firmware development tool chain or with various pre - compiled firmware profiles to allow a designer to easily ch ange the functionality of the chip. please refer to: - ftdi website for full details on available pre - compiled firmware 4.2 available firmware v2dap firmware is currently available: usb host for single flash disk and general purpose usb peripherals. selectable uart, fifo or spi interface command monitor. please refer to: - ftdi website for full details. 4.3 firmware upgrades r efer to the debugger interface section which can be used to update the firmware.
copyright ? 2010 future technology devices international limited 19 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 5 external circuit configuration 5.1 adding a second usb port the external circuit configuration for adding second usb host port, with the usb activity led, is shown below in figur e 5 . 1 figur e 5 . 1 additional usb port configuration
copyright ? 2010 future technology devices international limited 20 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 6 mechanical dimensions figure 6 . 1 - v2dip1 - 64 dimensions (top view) figure 6 . 2 - v2dip1 - 64 dimensions (side view) 0.2 0mm tolerance (except pitch) all dimensions are in mm. u 1 j 2 j 1 j 3 4 . 9 4 1 8 . 0 1 2 2 . 9 5 2 1 . 6 0 1 0 . 3 2 6 . 3 3 1 . 2 8 1 0 . 9 8 1 3 . 5 2 c n 1 f t d i x x x x x x x x v n c 2 - 6 4 q 1 a y y w w 1 2 . 3 2 4 . 9 8 8 4 . 6 4 8 6 . 2 4 9 1 . 5 3 2 . 5 4 7 . 0 0 1 7 . 8 5 4 . 9 0 1 . 6 0 8 . 6 5
copyright ? 2010 future technology devices international limited 21 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 7 schematic diagram figure 7 . 1 - v2dip1 - 64 schematics
copyright ? 2010 future technology devices international limited 22 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 8 contact information head office C glasgow, uk future technology devices international limited unit 1, 2 seaward place, centurion business park glasgow, g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales ) sales1@ftdichip.com e - mail (support) support1@ftdichip.com e - mail (general enquiries) admin1@ftdichip.com web site url http://www.ftdichip.com web shop url http://www.ftdichip.com branch office C taipei, taiwan future technology devices international limited (taiwan) 2f, no 516, sec. 1 neihu road taipei 114 taiwan, r.o.c. tel: +886 (0) 2 8791 3570 fax: +886 (0) 2 8791 3576 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (ge neral enquiries) tw.admin1@ftdichip.com web site url http://www.ftdichip.com branch office C hillsboro, oregon, usa future technology devices international limited (us a) 7235 nw evergreen parkway, suite 600 hillsboro, or 97123 - 5803 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail ( general enquiries ) us.admin@ftdichip.com web site url http://www.ftdichip.com branch office C shanghai, china future technology devices international limited (china) room 408, 317 xianxia road, changning district, shanghai, china tel: +86 (21) 62351596 fax: +86 (21) 62351595 e - mail (sales): cn.sales@ftdichip.com e - mail (support): cn .support@ftdichip .com e - ma il (general enquiries): cn. admin1@ftdichip.com web site url http://www.ftdichip.com distributor and sales representatives please visit the s ales network page of the ftdi web site for the contact details of our distributor(s) and sales representative(s) in your country.
copyright ? 2010 future technology devices international limited 23 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 appendix a C references application and technical notes vinculum - ii io cell description vinculum - ii debug interface description vinculum - ii io mux explained vinculum - ii pwm ex ample migrating vinculum designs from vnc1l to vnc2 - 48l1a vinculum - ii errata technical note
copyright ? 2010 future technology devices international limited 24 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 appendix b C list of figures and tables list of figures figure 1.1 - v2dip1 64 ................................ ................................ ................................ .................. 1 figure 3.1 - v2dip1 - 64 module pin out (top view) ................................ ................................ .......... 4 figure 3.2 - v2dip1 - 64 module pin out (bottom view) ................................ ................................ ..... 5 figure 3.3 C asynchronous fifo mode read and write cycle. ................................ ........................... 14 figure 3.4 - synchronous fifo mode read and write cycle ................................ .............................. 15 figure 5.1 additional usb port configuration ................................ ................................ .................. 19 figure 6.1 - v2dip1 - 64 dimensions (top view) ................................ ................................ .............. 20 figure 6.2 - v2dip1 - 64 dimensions (side view) ................................ ................................ ............. 20 figure 7.1 - v2dip1 - 64 schematics ................................ ................................ ............................... 21 list of tables table 3.1 - pin sig nal descriptions ................................ ................................ ................................ .. 6 table 3.2 - default interface i/o pin configuration ................................ ................................ ........... 8 table 3.3 - data and control bus signal mode options C uart ................................ ......................... 10 table 3.4 - data and control bus signal mode options C spi slave ................................ ................... 11 table 3.5 - data and control bus signal mode option s C spi master ................................ ................. 12 table 3.6 - data and control bus signal mode options C parallel fifo interface ................................ . 13 table 3.7 - asynchronous fif o mode read cycle timing ................................ ................................ .. 14 table 3.8 - data and control bus signal mode options C synchronous fifo mode .............................. 15 table 3.9 - synchron ous fifo mode read and write cycle timing ................................ .................... 16 table 3.10 - signal name and description C debugger interface ................................ ....................... 17
copyright ? 2010 future technology devices international limited 25 document reference no.: ft_000165 v2dip1 - 64 vncl2 - 64q development module datasheet version 1.01 clearance no.: ftdi# 154 appendix c C revision history version 1.0 first release 19 th april 20 10 version 1.0 1 updated modules images, mechanical drawings and figure 5.1 25 th may 20 10

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