datasheet low phase noise clock multiplier ics601-01 idt? / ics? low phase noise clock multiplier 1 ics601-01 rev n 051310 description the ics601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. it is idt?s lowest phase noise multiplier, and also the lowest cmos part in the industry. using idt?s patented analog and digital phase-locked loop (pll) techniques, the chip accepts a 10 - 27 mhz crystal or clock input, and produces output clocks up to 156 mhz at 3.3 v. this product is intended for clock generation. it has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. for applications which require definted input to output timing, use the ics670-01. features ? packaged in 16-pin soic or tssop ? pb (lead) free package ? uses fundamental 10 - 27 mhz crystal or clock ? patented pll with the lowest phase noise ? output clocks up to 156 mhz at 3.3 v ? low phase noise: -132 dbc/hz at 10 khz ? low jitter - 18 ps one sigma typ. ? full swing cmos outputs wit h 25 ma drive capability at ttl levels ? advanced, low power, sub-micron cmos process ? industrial temperature range available ? operating voltage of 3.3v or 5v block diagram rom based multipliers vco divide x1/iclk x2 crystal or clock input crystal oscillator reference divider phase comparator charge pump loop filter vco s3:0 gnd 3 4 vdd 3 clk refout refen oe
ics601-01 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 2 ics601-01 rev n 051310 pin assignment multiplier select table 0 = connect directly to ground 1 = connect directly to vdd pin descriptions 1 2 3 vdd 4 refen 5 6 gnd 7 8 gnd refout s3 s1 gnd x2 s2 vdd 16 clk vdd x1/iclk s0 oe 15 14 13 12 11 10 9 16 pin (150 mil) tssop or soic s3 s2 s1 s0 clk (see note 2 on following page) 00 0 0 test 00 0 1 test 00 10 input x1 00 11 input x3 01 00 input x4 01 01 input x5 01 10 input x6 01 11 input x8 10 0 0 test 10 0 1 crystal osc. pass through (no pll) 10 10 input x2 10 1 1 test 11 00 input x8 11 0 1 input x10 11 1 0 input x12 11 1 1 input x16 pin number pin name pin type pin description 1 clk output clock output from vco. output freque ncy equals the input frequency times multiplier. 2 refen input reference clock enable. turns off the buffered crystal oscillator clock (stops low) when low. 3 vdd power connect to +3.3v or +5v. must match other vdds. 4 vdd power connect to +3.3v or +5v. must match other vdds. 5 vdd power connect to +3.3v or +5v. must match other vdds. 6 x2 xo crystal connection. connect to a 10 - 27 mhz fundamental parallel mode crystal. leave disconnected for an external clock input. 7 s1 input multiplier select pin 1. determines clk output per table above. internal pull-up. 8 x1/iclk xi crystal connection. connect to a 10 - 27 mhz fundamental parallel mode crystal or clock. 9 s2 input multiplier select pin 2. determines clk output per table above. internal pull-up. 10 s3 input multiplier select pin 3. determines clk output per table above. internal pull-up. 11 s0 input multiplier select pin 0. determines clk output per table above. internal pull-up. 12 oe input output enable. tri-states both output clocks when low. internal pull-up. 13 refout output buffered crystal oscillator clock output. controlled by refin. 14 - 16 gnd power connect to ground.
ics601-01 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 3 ics601-01 rev n 051310 achieving low phase noise figure 1 shows a typical phase noise measurement in a 125 mhz system. therea are a few simple steps that can be taken to achieve these levels of phase noise from the ics601 -01. variations in vdd will increase the hase noise, so it is important to have a stable, low noise supply voltage at the device. use decoupling capacitors of 0.1 f in parallel with 0.01 f. it is important to have these capacitors as close as possible to the ics601-01 supply pins. disabling the refout clock is also important for achievin g low phase noise; lab tests have shown that this can reduce the phase noise by as much as 10 dbc/hz. external component/crystal selection the ics601-01 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01 f and 0.1 f should be connected between vdd and gnd, as close to the part as possible. a series termination resistor of 33 ? may be used for each clock output. the crysta l must be connected as close to the chip as possible. the crystal should be fundamental mode, parallel resonant. do not use third overtone. for exact tuning when using a crystal, capacitors should beconnected from pins x1 to ground and x2 to ground. in general, the value of these capacitors is given by the following equation, where cl is the crystal load capacitance: crystal caps (pf) = (cl - 5) x 2. so for a crystal with 16 pf load capacitance, two 22 pf caps can be used. for any given board layout, ics can measure the board capacitance and recommend the exact capacitance value to use. figure 1. phase noise of ics601-01 for 125 mhz output, 25 mhz crystal input. vdd = 3.3 v, refout disabled. -140 -120 -100 -80 -60 -40 -20 0 1. 00e+01 1. 00e+02 1. 00e+03 1. 00e+04 1. 00e+05 1. 00e+06 1. 00e+07 offset from carrier (hz) phase noise ( dbc/hz )
ics601-01 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 4 ics601-01 rev n 051310 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics601-01. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3 v 10% , ambient temperature -40 to +85 c note 1: switching occurs nominally at vdd/2 item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature, commercial version 0 to +70 c ambient operating temperature, industrial version -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +5.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.5 v input high voltage v ih x1/iclk pin only note 1 vdd/2+1 v input low voltage v il x1/iclk pin only note 1 vdd/2-1 v input high voltage v ih 2v input low voltage v il 0.8 v output high voltage v oh cmos level i oh = -4ma vdd-0.4 v i oh = -12ma 2.4 output low voltage v ol i ol = 12ma 0.4 v operating supply current idd no load, 125 mhz 22 30 ma short circuit current each output 40 60 ma input capacitance c in oe, select pins 5 pf
ics601-01 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 5 ics601-01 rev n 051310 ac electrical characteristics vdd = 3.3v 10% , ambient temperature -40 to +85 c note 2: input frequency limited by maximum output frequency and multiplication factor (i.e. for 16x, maximum input frequency is 13.75 mhz). parameter symbol conditions min. typ. max. units input frequency fin 10 27 mhz output frequency at 3.3v or 5v 156 mhz output rise time t or 0.8 to 2.0v no load 1.5 ns output fall time t of 0.8 to 2.0v, no load 1.5 ns output clock duty cycle at vdd/2 45 50 55 % maximum absolute jitter, short term, 125 mhz no load 50 75 ps maximum jitter, one sigma, 125 mhz (x5) no load 12 20 ps phase noise, relative to carrier, 125 mhz (x5) 100 hz offset -90 -94 dbc/hz phase noise, relative to carrier, 125 mhz (x5) 1 khz -116 -120 dbc/hz phase noise, relative to carrier, 125 mhz (x5) 10 khz offset -118 -122 dbc/hz phase noise, relative to carrier, 125 mhz (x5) 100 khz offset -115 -119 dbc/hz
ics601-01 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 6 ics601-01 rev n 051310 package outline and package dimensions (16 pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c c l h soic symbol min max a1.351.75 a1 0.10 0.25 b0.330.51 c0.190.25 d 9.80 10.00 e3.804.00 e 1.27 basic h5.806.20 l0.401.27 0 8
ics601-01 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 7 ics601-01 rev n 051310 package outline and package dimensions ( 16-pin tssop, 4.40 mm body, 0.65 mm pitch ) package dimensions are kept current with jedec publication no. 95 index area 1 2 16 d e1 e seating plane a 1 a a 2 e - c - b .10 (.004) c c l millimeters inches symbol min max min max a -- 1.20 -- 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8
ics601-01 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 8 ics601-01 rev n 051310 ordering information ?l? designates pb (lead) free package; ?i? designates industrial grade. while the information presented herein has been checked for both accuracy and reliability, integr ated circuit systems (idt) ass umes no responsibility for either its use or for the infringement of any patents or other ri ghts of third parties, which would result from its use. no oth er circuits, patents, or licenses are implied. this product is intended for use in normal commercial appl ications. any other applications such as those requiring ext ended temperature range, high reliability, or other extraordinary environmental requirements are not recommen ded without additional pr ocessing by idt. i dt reserves the right to change any circuitry or specificat ions without notice. idt does not authorize or warrant any idt product for use in life suppor t devices or critical medical instruments. part / order number marking shipping packaging package temperature 601m-01lf ics601m-01lf tubes 16-pin narrow soic 0 to 70 c 601m-01lft ics601m-01lf tape and reel 16-pin narrow soic 0 to 70 c 601m-01ilf ics601m01ilf tubes 16-pin narrow soic -40 to 85 c 601m-01ilft ics601m01ilf tape and reel 16-pin narrow soic -40 to 85 c 601g-01lf 601g01lf tubes 16-pin tssop 0 to 70 c 601g-01lft 601g01lf tape and reel 16-pin tssop 0 to 70 c 601g-01ilf 601g01il tubes 16-pin tssop -40 to 85 c 601g-01ilft 601g01il tape and reel 16-pin tssop -40 to 85 c
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