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"  ? organization: 524,288 words 32 or 36 bits ntd ? architecture for efficient bus operation  fast clock speeds to 200 mhz in lvttl/lvcmos  fast clock to data access: 3/3.4/4 ns fast oe access time: 3/3.4/4 ns  fully synchronous operation  ?flow-through? or ?pipelined? mode  asynchronous output enable control  economical 100-pin tqfp package  119 bga (7 x 17 ball grid array package)  byte write enables  clock enable for operation hold  multiple chip enables for easy expansion  2.5v core power supply  2.5v i/o operation  self-timed write cycles  interleaved or linear burst modes  snooze mode for standby operation write buffer address d q clk register output register dq [a:d] 36/32 36/32 19 19 clk ce0 ce1 ce2 a[18:0] oe clk cen control clk logic data d q clk input register 36/32 36/32 36/32 oe 512k x 32 sram array r/w dq [a:d] bwa bwc bwb bwd clk q d ft adv / ld lbo burst logic addr. registers write delay 36/32 19 #
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 zz clk note: pins 1,30,51,80 are nc for 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a a a a a1 a0 nc nc v ss v dd nc nc a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 bwd bwc bwb bwa ce2 v dd v ss clk r/w cen oe adv/ld a a a a tqfp 14 x 20mm a dqpc, nc dqc dqc v ddq v ssq dqc dqc dqc dqc v ssq v ddq dqc dqc ft v dd v dd v ss dqd dqd v ddq v ssq dqd dqd dqd dqd v ssq v ddq dqd dqd dqpd, nc dqpb, nc dqb dqb v ddq v ssq dqb dqb dqb dqb v ssq v ddq dqb dqb v ss zz dqa dqa v ddq v ssq dqa dqa dqa dqa v ssq v ddq dqa dqa dqpa, nc v dd v dd 

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 ntd ? is a trademark of alliance semiconductor corporation. -200 -166 -100 units minimum cycle time 5 6 10 ns maximum pipelined clock frequency 200 166 100 mhz maximum pipelined clock access time 3.0 3.4 4.0 ns maximum operating current 280 230 150 ma maximum standby current 100 70 50 ma maximum cmos standby current (dc) 30 30 30 ma
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