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? 2009 microchip technology inc. ds39755c pic18f2423/2523/4423/4523 data sheet 28/40/44-pin, enhanced flash microcontrollers with 12-bit a/d and nanowatt technology
ds39755c-page 2 ? 2009 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, uniwin driver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2009 microchip technology inc. ds39755c-page 3 pic18f2423/2523/4423/4523 power management features: ? run: cpu on, peripherals on ? idle: cpu off, peripherals on ? sleep: cpu off, peripherals off ? ultra low 50 na input leakage ? run mode currents down to 11 a typical ? idle mode currents down to 2.5 a typical ? sleep mode current down to 100 a typical ? timer1 oscillator: 900 na, 32 khz, 2v ? watchdog timer: 1.4 a, 2v typical ? two-speed oscillator start-up flexible oscillator structure: ? four crystal modes, up to 40 mhz ? 4x phase lock loop (pll) ? available for crystal and internal oscillators ? two external rc modes, up to 4 mhz ? two external clock modes, up to 40 mhz ? internal oscillator block: - fast wake from sleep and idle, 1 s typical - 8 user-selectable frequencies, from 31 khz to 8 mhz - provides a complete range of clock speeds, from 31 khz to 32 mhz, when used with pll - user-tunable to compensate for frequency drift ? secondary oscillator using timer1 @ 32 khz ? fail-safe clock monitor: - allows for safe shutdown if peripheral clock stops peripheral highlights: ? 12-bit, up to 13-channel analog-to-digital converter module (a/d): - auto-acquisition capability - conversion available during sleep mode ? dual analog comparators with input multiplexing ? high-current sink/source 25 ma/25 ma ? three programmable external interrupts ? four input change interrupts ? up to two capture/compare/pwm (ccp) modules, one with auto-shutdown (28-pin devices) ? enhanced capture/compare/pwm (eccp) module (40/44-pin devices only): - one, two or four pwm outputs - selectable polarity - programmable dead time - auto-shutdown and auto-restart peripheral highlights (continued): ? master synchronous serial port (mssp) module supporting 3-wire spi (all four modes) and i 2 c? master and slave modes ? enhanced usart module: - support for rs-485, rs-232 and lin/j2602 - rs-232 operation using internal oscillator block (no external crystal required) - auto-wake-up on start bit - auto-baud detect (abd) special microcontroller features: ? c compiler optimized architecture: optional extended instruction set designed to optimize re-entrant code ? 100,000 erase/write cycle, enhanced flash program memory typical ? 1,000,000 erase/write cycle, data eeprom memory typical ? flash/data eeprom retention: 100 years typical ? self-programmable under software control ? priority levels for interrupts ? 8 x 8 single-cycle hardware multiplier ? extended watchdog timer (wdt): programmable period, from 4 ms to 131s ? single-supply in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) via two pins ? operating voltage range: 2.0v to 5.5v ? programmable, 16-level high/low-voltage detection (hlvd) module: supports interrupt on high/low-voltage detection ? programmable brown-out reset (bor): with software-enable option note: this document is supplemented by the ?pic18f2420/2520/4420/4520 data sheet? (ds39631). see section 1.0 ?device overview? . device program memory data memory i/o 12-bit a/d (ch) ccp/ eccp (pwm) mssp eusart comp. timers 8/16-bit flash (bytes) # single-word instructions sram (bytes) eeprom (bytes) spi master i 2 c? pic18f2423 16k 8192 768 256 25 10 2/0 y y 1 2 1/3 pic18f2523 32k 16384 1536 256 25 10 2/0 y y 1 2 1/3 pic18f4423 16k 8192 768 256 36 13 1/1 y y 1 2 1/3 pic18f4523 32k 16384 1536 256 36 13 1/1 y y 1 2 1/3 28/40/44-pin, enhanced flas h microcontrollers with 12-bit a/d and nanowatt technology
pic18f2423/2523/4423/4523 ds39755c-page 4 ? 2009 microchip technology inc. pin diagrams pic18f2523 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /hlvdin/c2out v ss osc1/clki (3) /ra7 osc2/clko (3) /ra6 rc0/t1oso/t13cki rc1/t1osi/ccp2 (2) rc2/ccp1 rc3/sck/scl rb7/kbi3/pgd rb6//kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 rb3/an9/ccp2 (2) rb2/int2/an8 rb1/int1/an10 rb0/int0/flt0/an12 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda 28-pin pdip, soic pic18f2423 note 1: it is recommended to connect the bottom pad of qfn package parts to v ss . 2: rb3 is the alternate pin for ccp2 multiplexing. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. for additional information, see section 2.0 ?oscillator configurations? of the ?pic18f2420/2520/4420/4520 data sheet? (ds39631). 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 pic18f2423 rc0/t1oso/t13cki 5 4 rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4kbi0/an11 rb3/an9/ccp2 (2) rb2/int2/an8 rb1/int1/an10 rb0/int0/flt0/an12 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /hlvdin/c2out v ss osc1/clki (3) /ra7 osc2/clko (3) /ra6 rc1/t1osi/ccp2 (2) rc2/ccp1 rc3/sck/scl pic18f2523 28-pin qfn (1)
? 2009 microchip technology inc. ds39755c-page 5 pic18f2423/2523/4423/4523 pin diagrams (continued) rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 rb3/an9/ccp2 (1) rb2/int2/an8 rb1/int1/an10 rb0/int0/flt0/an12 v dd v ss rd7/psp7/p1d rd6/psp6/p1c rd5/psp5/p1b rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /hlvdin/c2out re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clki (2) /ra7 osc2/clko (2) /ra6 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1/p1a rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18f4523 40-pin pdip pic18f4423 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4423 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp /re3 nc rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1/p1a rc1/t1osi/ccp2 (1) nc nc rc0/t1oso/t13cki osc2/clko (2) /ra6 osc1/clki (2) /ra7 v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss /hlvdin/c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d v ss v dd rb0/int0/flt0/an12 rb1/int1/an10 rb2/int2/an8 rb3/an9/ccp2 (1) 44-pin tqfp pic18f4523 note 1: rb3 is the alternate pin for ccp2 multiplexing. 2: osc1/clki and osc2/clko are only available in se lect oscillator modes and when these pins are not being used as digital i/o. for additional information, see section 2.0 ?oscillator configurations? of the ?pic18f2420/2520/4420/4520 data sheet? (ds39631).
pic18f2423/2523/4423/4523 ds39755c-page 6 ? 2009 microchip technology inc. pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4423 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp /re3 rb3/an9/ccp2 (2) rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1/p1a rc1/t1osi/ccp2 (2) rc0/t1oso/t13cki osc2/clko (3) /ra6 osc1/clki (3) /ra7 v ss v ss v dd v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss /hlvdin/c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d v ss v dd v dd rb0/int0/flt0/an12 rb1/int1/an10 rb2/int2/an8 44-pin qfn (1) pic18f4523 note 1: it is recommended to connect the bottom pad of qfn package parts to v ss . 2: rb3 is the alternate pin for ccp2 multiplexing. 3: osc1/clki and osc2/clko are only available in sele ct oscillator modes and when these pins are not being used as digital i/o. for additional information, see section 2.0 ?oscillator configurations? of the ?pic18f2420/2520/4420/4520 data sheet? (ds39631).
? 2009 microchip technology inc. ds39755c-page 7 pic18f2423/2523/4423/4523 table of contents 1.0 device overview ............................................................................................................. ............................................................. 9 2.0 12-bit analog-to-digital converter (a/d) module ............................................................................. .......................................... 25 3.0 special features of the cpu................................................................................................. ..................................................... 35 4.0 electrical characteristics .................................................................................................. .......................................................... 37 5.0 packaging information....................................................................................................... ......................................................... 43 appendix a: revision history................................................................................................... ............................................................ 45 appendix b: device differences ................................................................................................. ......................................................... 45 appendix c: conversion considerations .......................................................................................... ................................................... 46 appendix d: migration from baseline to enhanced devices........................................................................ ........................................ 46 appendix e: migration from mid-range to enhanced devices ....................................................................... ..................................... 47 appendix f: migration from high-end to enhanced devices ........................................................................ ....................................... 47 index .......................................................................................................................... ......................................................................... 49 the microchip web site ......................................................................................................... .............................................................. 51 customer change notification service ........................................................................................... ..................................................... 51 customer support............................................................................................................... ................................................................. 51 reader response ................................................................................................................ ................................................................ 52 product identification system .................................................................................................. ............................................................ 53
pic18f2423/2523/4423/4523 ds39755c-page 8 ? 2009 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2009 microchip technology inc. ds39755c-page 9 pic18f2423/2523/4423/4523 1.0 device overview this document contains device-specific information for the following devices: this family offers the advantages of all pic18 microcontrollers ? namely, high computational perfor- mance at an economical price ? with the addition of high-endurance, enhanced flash program memory. on top of these features, the pic18f2423/2523/4423/ 4523 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power-sensitive applications. 1.1 new core features 1.1.1 nanowatt technology all of the devices in the pic18f2423/2523/4423/4523 family incorporate a range of features that can signifi- cantly reduce power consumption during operation. key items include: ? alternate run modes: by clocking the controller from the timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. ? multiple idle modes: the controller also can run with its cpu core disabled and the peripherals still active. in these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. ? on-the-fly mode switching: the power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application?s software design. ? low consumption in key modules: the power requirements for both timer1 and the watchdog timer are minimized. see section 4.0 ?electrical characteristics? for values. 1.1.2 multiple oscillator options and features all of the devices in the pic18f2423/2523/4423/4523 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. these include: ? four crystal modes, using crystals or ceramic resonators. ? two external clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general i/o). ? two external rc oscillator modes with the same pin options as the external clock modes. ? an internal oscillator block that offers eight clock frequencies: an 8 mhz clock and an intrc source (approximately 31 khz), as well as a range of six user-selectable clock frequencies, between 125 khz to 4 mhz. this option frees the two oscillator pins for use as additional general purpose i/o. ? a phase lock loop (pll) frequency multiplier, available to both the high-speed crystal and internal oscillator modes, allowing clock speeds of up to 40 mhz from the hs clock source. used with the internal oscillator, the pll gives users a complete selection of clock speeds, from 31 khz to 32 mhz, all without using an external crystal or clock circuit. besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: ? fail-safe clock monitor: constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. ? two-speed start-up: allows the internal oscillator to serve as the clock source from power-on reset, or wake-up from sleep mode, until the primary clock source is available. ? pic18f2423 ? pic18lf2423 ? pic18f2523 ? pic18lf2523 ? pic18f4423 ? pic18lf4423 ? pic18f4523 ? pic18lf4523 note: this data sheet documents only the devices? features and specifications that are in addition to, or different from, the features and specifi- cations of the pic18f2420/2520/4420/4520 devices. for information on the features and specifications shared by the pic18f2423/ 2523/4423/4523 and pic18f2420/2520/ 4420/4520 devices, see the ?pic18f2420/ 2520/4420/4520 data sheet? (ds39631).
pic18f2423/2523/4423/4523 ds39755c-page 10 ? 2009 microchip technology inc. 1.2 other special features ? 12-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, thereby reducing code overhead. ? memory endurance: the enhanced flash cells for both program memory and data eeprom are rated to last for many thousands of erase/write cycles ? up to 100,000 for program memory and 1,000,000 for eeprom. data retention without refresh is conservatively estimated to be greater than 40 years. ? self-programmability: these devices can write to their own program memory spaces under inter- nal software control. by using a bootloader routine located in the protected boot block at the top of program memory, it is possible to create an application that can update itself in the field. ? extended instruction set: the pic18f2423/ 2523/4423/4523 family introduces an optional extension to the pic18 instruction set that adds eight new instructions and an indexed addressing mode. this extension, enabled as a device con- figuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as c. ? enhanced ccp module: in pwm mode, this module provides one, two or four modulated outputs for controlling half-bridge and full-bridge drivers. other features include auto-shutdown, for disabling pwm outputs on interrupt or other select conditions, and auto-restart, to reactivate outputs once the condition has cleared. ? enhanced addressable usart: this serial communication module is capable of standard rs-232 operation and provides support for the lin/j2602 bus protocol. other enhancements include automatic baud rate detection and a 16-bit baud rate generator for improved resolution. when the microcontroller is using the internal oscillator block, the eusart provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). ? extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. see section 4.0 ?electrical characteristics? for time-out periods. 1.3 details on individual family members devices in the pic18f2423/2523/4423/4523 family are available in 28-pin and 40/44-pin packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2. the devices are differentiated from each other in these ways: ? flash program memory: - pic18f2423/4423 devices ? 16 kbytes - pic18f2523/4523 devices ? 32 kbytes ? a/d channels: - pic18f2423/2523 devices ? 10 - pic18f4423/4523 devices ? 13 ? i/o ports: - pic18f2423/2523 devices ? three bidirectional ports - pic18f4423/4523 devices ? five bidirectional ports ? ccp and enhanced ccp implementation: - pic18f2423/2523 devices ? two standard ccp modules - pic18f4423/4523 devices ? one standard ccp module and one eccp module ? parallel slave port ? present only on pic18f4423/4523 devices all other features for devices in this family are identical. these are summarized in table 1-1. the pinouts for all devices are listed in table 1-2 and table 1-3. members of the pic18f2423/2523/4423/4523 family are available only as low-voltage devices, designated by ?lf? (such as pic18 lf 2423), and function over an extended v dd range of 2.0v to 5.5v.
? 2009 microchip technology inc. ds39755c-page 11 pic18f2423/2523/4423/4523 table 1-1: device features features pic18f2423 pic18f2523 pic18f4423 pic18f4523 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 16,384 32,768 16,384 32,768 program memory (instructions) 8,192 16,384 8,192 16,384 data memory (bytes) 768 1,536 768 1,536 data eeprom memory (bytes) 256 256 256 256 interrupt sources 19 19 20 20 i/o ports ports a, b, c, (e) ports a, b, c, (e) ports a, b, c, d, e ports a, b, c, d, e timers 4 4 4 4 capture/compare/pwm modules 2 2 1 1 enhanced capture/compare/pwm modules 0011 serial communications mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart parallel communications (psp) no no yes yes 12-bit analog-to-digital module 10 input channels 10 input channels 13 input channels 13 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable high/low-voltage detect ye s yes yes ye s programmable brown-out reset yes yes yes yes instruction set 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled packages 28-pin pdip 28-pin soic 28-pin qfn 28-pin pdip 28-pin soic 28-pin qfn 40-pin pdip 44-pin qfn 44-pin tqfp 40-pin pdip 44-pin qfn 44-pin tqfp
pic18f2423/2523/4423/4523 ds39755c-page 12 ? 2009 microchip technology inc. figure 1-1: pic18f2423/2523 (28-pin) block diagram instruction decode and control porta portb portc ra4/t0cki/c1out ra5/an4/ss /hlvdin/c2out rb0/int0/flt0/an12 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 rb1/int1/an10 data latch data memory ( 3.9 kbytes ) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (16/32 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch rb2/int2/an8 rb3/an9/ccp2 (1) pclatu pcu osc2/clko (3) /ra6 note 1: ccp2 is multiplexed with rc1 when configuration bit, ccp2mx, is set or rb3 when ccp2mx is not set. 2: re3 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. for additional information, see section 2.0 ?oscillator configurations? of the ?pic18f2420/2520/4420/4520 data sheet? (ds39631). rb4/kbi0/an11 rb5/kbi1/pgm rb6/kbi2/pgc rb7/kbi3/pgd eusart comparator mssp 12-bit adc timer2 timer1 timer3 timer0 ccp2 hlvd ccp1 bor data eeprom w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1oso osc1/clki (3) /ra7 t1osi porte mclr /v pp /re3 (2)
? 2009 microchip technology inc. ds39755c-page 13 pic18f2423/2523/4423/4523 figure 1-2: pic18f4423/4523 (40/44-pin) block diagram instruction decode and control data latch data memory ( 3.9 kbytes ) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (16/32 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch portd rd0/psp0 pclatu pcu porte mclr /v pp /re3 (2) re2/cs /an7 re0/rd /an5 re1/wr /an6 note 1: ccp2 is multiplexed with rc1 when configuration bit, ccp2mx, is set or rb3 when ccp2mx is not set. 2: re3 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. for additional information, see section 2.0 ?oscillator configurations? of the ?pic18f2420/2520/4420/4520 data sheet? (ds39631). :rd4/psp4 eusart comparator mssp 12-bit adc timer2 timer1 timer3 timer0 ccp2 hlvd eccp1 bor data eeprom w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d porta portb portc ra4/t0cki/c1out ra5/an4/ss /hlvdin/c2out rb0/int0/flt0/an12 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1/p1a rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 rb1/int1/an10 rb2/int2/an8 rb3/an9/ccp2 (1) osc2/clko (3) /ra6 rb4/kbi0/an11 rb5/kbi1/pgm rb6/kbi2/pgc rb7/kbi3/pgd osc1/clki (3) /ra7
pic18f2423/2523/4423/4523 ds39755c-page 14 ? 2009 microchip technology inc. table 1-2: pic18f2423/2523 pinout i/o descriptions pin name pin number pin type buffer type description pdip, soic qfn mclr /v pp /re3 mclr v pp re3 126 i p i st st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki/ra7 osc1 clki ra7 96 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; cmos otherwise. external clock source input. always associated with pin function, osc1. (see relat ed osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 10 7 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o=output p =power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39755c-page 15 pic18f2423/2523/4423/4523 porta is a bidirectional i/o port. ra0/an0 ra0 an0 227 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 328 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref -/cv ref ra2 an2 v ref - cv ref 41 i/o i i o ttl analog analog analog digital i/o. analog input 2. a/d reference voltage (low) input. comparator reference voltage output. ra3/an3/v ref + ra3 an3 v ref + 52 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/c1out ra4 t0cki c1out 63 i/o i o st st ? digital i/o. timer0 external clock input. comparator 1 output. ra5/an4/ss /hlvdin/ c2out ra5 an4 ss hlvdin c2out 74 i/o i i i o ttl analog ttl analog ? digital i/o. analog input 4. spi slave select input. high/low-voltage detect input. comparator 2 output. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-2: pic18f2423/2523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip, soic qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o=output p =power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f2423/2523/4423/4523 ds39755c-page 16 ? 2009 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0/an12 rb0 int0 flt0 an12 21 18 i/o i i i ttl st st analog digital i/o. external interrupt 0. pwm fault input for ccp1. analog input 12. rb1/int1/an10 rb1 int1 an10 22 19 i/o i i ttl st analog digital i/o. external interrupt 1. analog input 10. rb2/int2/an8 rb2 int2 an8 23 20 i/o i i ttl st analog digital i/o. external interrupt 2. analog input 8. rb3/an9/ccp2 rb3 an9 ccp2 (1) 24 21 i/o i i/o ttl analog st digital i/o. analog input 9. capture 2 input/compare 2 output/pwm2 output. rb4/kbi0/an11 rb4 kbi0 an11 25 22 i/o i i ttl ttl analog digital i/o. interrupt-on-change pin. analog input 11. rb5/kbi1/pgm rb5 kbi1 pgm 26 23 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 27 24 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 28 25 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-2: pic18f2423/2523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip, soic qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o=output p =power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39755c-page 17 pic18f2423/2523/4423/4523 portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 11 8 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (2) 12 9 i/o i i/o st analog st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. rc2/ccp1 rc2 ccp1 13 10 i/o i/o st st digital i/o. capture 1 input/compare 1 output/pwm1 output. rc3/sck/scl rc3 sck scl 14 11 i/o i/o i/o st st i 2 c digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 15 12 i/o i i/o st st i 2 c digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 16 13 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 17 14 i/o o i/o st ? st digital i/o. eusart asynchronous transmit. eusart synchronous clock (see related rx/dt). rc7/rx/dt rc7 rx dt 18 15 i/o i i/o st st st digital i/o. eusart asynchronous receive. eusart synchronous data (see related tx/ck). re3 ? ? ? ? see mclr /v pp /re3 pin. v ss 8, 19 5, 16 p ? ground reference for logic and i/o pins. v dd 20 17 p ? positive supply for logic and i/o pins. table 1-2: pic18f2423/2523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip, soic qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o=output p =power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f2423/2523/4423/4523 ds39755c-page 18 ? 2009 microchip technology inc. table 1-3: pic18f4423/4523 pinout i/o descriptions pin name pin number pin type buffer type description pdip qfn tqfp mclr /v pp /re3 mclr v pp re3 11818 i p i st st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki/ra7 osc1 clki ra7 13 32 30 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; analog otherwise. external clock source input. always associated with pin function, osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 14 33 31 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39755c-page 19 pic18f2423/2523/4423/4523 porta is a bidirectional i/o port. ra0/an0 ra0 an0 21919 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 32020 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref -/cv ref ra2 an2 v ref - cv ref 42121 i/o i i o ttl analog analog analog digital i/o. analog input 2. a/d reference voltage (low) input. comparator reference voltage output. ra3/an3/v ref + ra3 an3 v ref + 52222 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/c1out ra4 t0cki c1out 62323 i/o i o st st ? digital i/o. timer0 external clock input. comparator 1 output. ra5/an4/ss /hlvdin/ c2out ra5 an4 ss hlvdin c2out 72424 i/o i i i o ttl analog ttl analog ? digital i/o. analog input 4. spi slave select input. high/low-voltage detect input. comparator 2 output. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-3: pic18f4423/4523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip qfn tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f2423/2523/4423/4523 ds39755c-page 20 ? 2009 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0/an12 rb0 int0 flt0 an12 33 9 8 i/o i i i ttl st st analog digital i/o. external interrupt 0. pwm fault input for enhanced ccp1. analog input 12. rb1/int1/an10 rb1 int1 an10 34 10 9 i/o i i ttl st analog digital i/o. external interrupt 1. analog input 10. rb2/int2/an8 rb2 int2 an8 35 11 10 i/o i i ttl st analog digital i/o. external interrupt 2. analog input 8. rb3/an9/ccp2 rb3 an9 ccp2 (1) 36 12 11 i/o i i/o ttl analog st digital i/o. analog input 9. capture 2 input/compare 2 output/pwm2 output. rb4/kbi0/an11 rb4 kbi0 an11 37 14 14 i/o i i ttl ttl analog digital i/o. interrupt-on-change pin. analog input 11. rb5/kbi1/pgm rb5 kbi1 pgm 38 15 15 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 39 16 16 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 40 17 17 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f4423/4523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip qfn tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39755c-page 21 pic18f2423/2523/4423/4523 portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 15 34 32 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (2) 16 35 35 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. rc2/ccp1/p1a rc2 ccp1 p1a 17 36 36 i/o i/o o st st ? digital i/o. capture 1 input/compare 1 output/pwm1 output. enhanced ccp1 output. rc3/sck/scl rc3 sck scl 18 37 37 i/o i/o i/o st st i 2 c digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 23 42 42 i/o i i/o st st i 2 c digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 24 43 43 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 25 44 44 i/o o i/o st ? st digital i/o. eusart asynchronous transmit. eusart synchronous clock (see related rx/dt). rc7/rx/dt rc7 rx dt 26 1 1 i/o i i/o st st st digital i/o. eusart asynchronous receive. eusart synchronous data (see related tx/ck). table 1-3: pic18f4423/4523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip qfn tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f2423/2523/4423/4523 ds39755c-page 22 ? 2009 microchip technology inc. portd is a bidirectional i/o port or a parallel slave port (psp) for interfacing to a microprocessor port. these pins have ttl input buffers when the psp module is enabled. rd0/psp0 rd0 psp0 19 38 38 i/o i/o st ttl digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 20 39 39 i/o i/o st ttl digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 21 40 40 i/o i/o st ttl digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 22 41 41 i/o i/o st ttl digital i/o. parallel slave port data. rd4/psp4 rd4 psp4 27 2 2 i/o i/o st ttl digital i/o. parallel slave port data. rd5/psp5/p1b rd5 psp5 p1b 28 3 3 i/o i/o o st ttl ? digital i/o. parallel slave port data. enhanced ccp1 output. rd6/psp6/p1c rd6 psp6 p1c 29 4 4 i/o i/o o st ttl ? digital i/o. parallel slave port data. enhanced ccp1 output. rd7/psp7/p1d rd7 psp7 p1d 30 5 5 i/o i/o o st ttl ? digital i/o. parallel slave port data. enhanced ccp1 output. table 1-3: pic18f4423/4523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip qfn tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39755c-page 23 pic18f2423/2523/4423/4523 porte is a bidirectional i/o port. re0/rd /an5 re0 rd an5 82525 i/o i i st ttl analog digital i/o. read control for parallel slave port (see also wr and cs pins). analog input 5. re1/wr /an6 re1 wr an6 92626 i/o i i st ttl analog digital i/o. write control for parallel slave port (see cs and rd pins). analog input 6. re2/cs /an7 re2 cs an7 10 27 27 i/o i i st ttl analog digital i/o. chip select control for parallel slave port (see related rd and wr ). analog input 7. re3 ? ? ? ? ? see mclr /v pp /re3 pin. v ss 12, 31 6, 30, 31 6, 29 p ? ground reference for logic and i/o pins. v dd 11, 32 7, 8, 28, 29 7, 28 p ? positive supply for logic and i/o pins. nc ? 13 12, 13, 33, 34 ? ? no connect. table 1-3: pic18f4423/4523 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip qfn tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power i 2 c=i 2 c?/smbus note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f2423/2523/4423/4523 ds39755c-page 24 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds39755c-page 25 pic18f2423/2523/4423/4523 2.0 12-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 10 inputs for the pic18f2423/2523 devices and 13 for the pic18f4423/4523 devices. this module allows conversion of an analog input signal to a corresponding 12-bit digital number. the module has five registers: ? a/d result high register (adresh) ? a/d result low register (adresl) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) ? a/d control register 2 (adcon2) of the adconx registers: ? adcon0 (shown in register 2-1) ? controls the module?s operation ? adcon1 (register 2-2) ? configures the functions of the port pins ? adcon2 (register 2-3) ? configures the a/d clock source, programmed acquisition time and justification register 2-1: adcon0: a/ d control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chs<3:0>: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) (1,2) 0110 = channel 6 (an6) (1,2) 0111 = channel 7 (an7) (1,2) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = channel 12 (an12 1101 = unimplemented (2) 1110 = unimplemented (2) 1111 = unimplemented (2) bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled note 1: these channels are not implemented on pic18f2423/2523 devices. 2: performing a conversion on unimplemented channels will return a floating input measurement.
pic18f2423/2523/4423/4523 ds39755c-page 26 ? 2009 microchip technology inc. register 2-2: adcon1: a/ d control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 (1) r/w (1) r/w (1) r/w (1) ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 vcfg1: voltage reference configuration bit (v ref - source) 1 = v ref - (an2) 0 = v ss bit 4 vcfg0: voltage reference configuration bit (v ref + source) 1 = v ref + (an3) 0 = v dd bit 3-0 pcfg<3:0>: a/d port configuration control bits: note 1: the por value of the pcfg bits depends on th e value of the pbaden configuration bit. when pbaden = 1 , pcfg<3:0> = 0000 ; when pbaden = 0 , pcfg<3:0> = 0111 . 2: an5 through an7 are only available on pic18f4423/4523 devices. a = analog input d = digital i/o pcfg<3:0> an12 an11 an10 an9 an8 an7 (2) an6 (2) an5 (2) an4 an3 an2 an1 an0 0000 (1) a a aaaaaaaaaaa 0001 a a aaaaaaaaaaa 0010 a a aaaaaaaaaaa 0011 d a aaaaaaaaaaa 0100 dd aaaaaaaaaaa 0101 dddaaaaaaaaaa 0110 ddddaaaaaaaaa 0111 (1) dddddaaaaaaaa 1000 d d ddddaaaaaaa 1001 d d dddddaaaaaa 1010 d d ddddddaaaaa 1011 d d dddddddaaaa 1100 d d ddddddddaaa 1101 d d dddddddddaa 1110 d d dddddddddda 1111 d d ddddddddddd
? 2009 microchip technology inc. ds39755c-page 27 pic18f2423/2523/4423/4523 register 2-3: adcon2: a/ d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt<2:0>: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs<2:0>: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion.
pic18f2423/2523/4423/4523 ds39755c-page 28 ? 2009 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ), or the voltage level on the ra3/an3/ v ref + and ra2/an2/v ref -/cv ref pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0<1>) is cleared and a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 2-1. figure 2-1: a/d block diagram (input voltage) v ain v ref + reference voltage v dd (2) vcfg<1:0> chs<3:0> an7 (1) an6 (1) an5 (1) an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 12-bit a/d v ref - v ss (2) converter an12 an11 an10 an9 an8 1100 1011 1010 1001 1000 note 1: channels, an5 through an7, are not available on pic18f2423/2523 devices. 2: i/o pins have diode protection to v dd and v ss . 0 x 1 x x 1 x 0
? 2009 microchip technology inc. ds39755c-page 29 pic18f2423/2523/4423/4523 the value in the adresh:adresl registers is unknown following por and bor resets and is not affected by any other reset. after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine acquisition time, see section 2.1 ?a/d acquisition requirements? . after this acquisition time has elapsed, the a/d conver- sion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to perform an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d acquisition time (adcon2) ? select a/d conversion clock (adcon2) ? turn on the a/d module (adcon0) 2. configure the a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time (if required). 4. start conversion by setting the go/done bit (adcon0<1>). 5. wait for the a/d conversion to complete by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read the a/d result registers (adresh:adresl) and clear the adif bit, if required. 7. for the next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 2-2: a/d transfer function figure 2-3: analog input model digital code output ffeh 003h 002h 001h 000h 0.5 lsb 1 lsb 1.5 lsb 2 lsb 2.5 lsb 4094 lsb 4094.5 lsb 3 lsb analog input voltage fffh 4095 lsb 4095.5 lsb v ain c pin rs anx 5 pf v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss v dd 100 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss v dd 6v sampling switch 5v 4v 3v 2v 123 4 (k )
pic18f2423/2523/4423/4523 ds39755c-page 30 ? 2009 microchip technology inc. 2.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 2-3. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor, c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 2-1 may be used. this equation assumes that 1/2 lsb error is used (4,096 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 2-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the application system assumptions shown in table 2-1: equation 2-1: acquisition time equation 2-2: a/d minimum charging time equation 2-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. table 2-1: t acq assumptions c hold = 25 pf rs = 2.5 k conversion error 1/2 lsb v dd =3v rss = 4 k temperature = 85 c (system maximum) t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /4096)) ? (1 ? e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/4096) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp ? 25 c)(0.02 s/ c) (85 c ? 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 ms. t c = -(c hold )(r ic + r ss + r s ) ln(1/4095) s -(25 pf) (1 k + 4 k + 2.5 k ) ln(0.0004883) s 1.56 s t acq =0.2 s + 1.56 s + 1.2 s 2.96 s
? 2009 microchip technology inc. ds39755c-page 31 pic18f2423/2523/4423/4523 2.2 selecting and configuring acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. it also gives users the option of having an automatically determined acquisition time. acquisition time may be set with the acqt<2:0> bits (adcon2<5:3>), which provide a range of 2 to 20 t ad . when the go/done bit is set, the a/d module con- tinues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. manual acquisition time is selected when acqt<2:0> = 000 . when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this option is also the default reset state of the acqt<2:0> bits and is compatible with devices that do not offer programmable acquisition times. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 2.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 13 t ad per 12-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible, but greater than the minimum t ad . (for more information, see parameter 130 on page 41.) table 2-2 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 2-2: t ad vs. device operating frequencies ?2 t osc ? 32 t osc ?4 t osc ? 64 t osc ?8 t osc ? internal rc oscillator ?16 t osc a/d clock source (t ad ) assumes t ad min. = 0.8 s operation adcs<2:0> maximum f osc 2 t osc 000 2.50 mhz 4 t osc 100 5.00 mhz 8 t osc 001 10.00 mhz 16 t osc 101 20.00 mhz 32 t osc 010 40.00 mhz 64 t osc 110 40.00 mhz rc (2) x11 1.00 mhz (1) note 1: the rc source has a typical t ad time of 2.5 s. 2: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or a f osc divider should be used instead; otherwise, the a/d accuracy specification may not be met.
pic18f2423/2523/4423/4523 ds39755c-page 32 ? 2009 microchip technology inc. 2.4 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the adcs<2:0> bits in adcon2 should be updated in accordance with the clock source to be used. the acqt<2:0> bits do not need to be adjusted as the adcs<2:0> bits adjust the t ad time for the new clock speed. after entering the mode, an a/d acquisition or conversion may be started. once started, the device should continue to be clocked by the same clock source until the conversion has been completed. if desired, the device may be placed into the corresponding idle mode during the conversion. if the device clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d f rc clock to be selected. if bits, acqt<2:0>, are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen bit (osccon<7>) must have already been cleared prior to starting the conversion. 2.5 configuring analog port pins the adcon1, trisa, trisb and trise registers all configure the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<3:0> bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). analog con- version on pins configured as digital pins can be performed. the voltage on the pin will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device?s specification limits. 3: the pbaden bit in configuration register 3h configures portb pins to reset as analog or digital pins by controlling how the pcfg<3:0> bits in adcon1 are reset.
? 2009 microchip technology inc. ds39755c-page 33 pic18f2423/2523/4423/4523 2.6 a/d conversions figure 2-4 shows the operation of the a/d converter after the go/done bit has been set and the acqt<2:0> bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 2-5 shows the operation of the a/d converter after the go/done bit has been set, the acqt<2:0> bits have been set to ? 010 ? and a 4 t ad acquisition time has been selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/ d result register pair will not be updated with the partially completed a/d conversion sample. this means, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t cy wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 2.7 discharge the discharge phase is used to initialize the value of the holding capacitor. the array is discharged before every sample. this feature helps to optimize the unity- gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. figure 2-4: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 2-5: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. code should wait at least 3 t ad after enabling the a/d before beginning an acquisition and conversion cycle. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy ? t ad adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b2 b11 b8 b7 b6 b5 b4 b3 b10 b9 on the following cycle: discharge t ad 13 t ad 12 b0 b1 t ad 1 (typically 200 ns) 1 2 3 4 5 6 7 8 13 set go/done bit (holding capacitor is disconnected) 9 12 conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b11 b8 b7 b6 b5 b4 b1 b10 b9 adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. on the following cycle: t ad 1 discharge 10 11 b3 b2 (typically 200 ns) points to end of t acqt period (current black arrow)
pic18f2423/2523/4423/4523 ds39755c-page 34 ? 2009 microchip technology inc. 2.8 use of the ccp2 trigger an a/d conversion can be started by the special event trigger of the ccp2 module. this requires that the ccp2m<3:0> bits (ccp2con<3:0>) be programmed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion, and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving adresh:adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user or an appropriate t acq time is selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module, but will still reset the timer1 (or timer3) counter. table 2-3: registers associated with a/d operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif (note 4) pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if (note 4) pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie (note 4) ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip (note 4) pir2 oscfif cmif ? eeif bclif hlvdif tmr3if ccp2if (note 4) pie2 oscfie cmie ? eeie bclie hlvdie tmr3ie ccp2ie (note 4) ipr2 oscfip cmip ? eeip bclip hlvdip tmr3ip ccp2ip (note 4) adresh a/d result register high byte (note 4) adresl a/d result register low byte (note 4) adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon (note 4) adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 (note 4) adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 (note 4) porta ra7 (2) ra6 (2) ra5 ra4 ra3 ra2 ra1 ra0 (note 4) trisa trisa7 (2) trisa6 (2) porta data direction control register (note 4) portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (note 4) trisb portb data direction control register (note 4) latb portb data latch register (read and write to data latch) (note 4) porte (1) ? ? ? ?re3 (3) re2 re1 re0 (note 4) trise (1) ibf obf ibov pspmode ? trise2 trise1 trise0 (note 4) late (1) ? ? ? ? ? porte data latch register (note 4) legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: these registers and/or bits are not implemented on pic18f2423/2523 devices and are read as ? 0 ?. 2: porta<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. when disabled, these bits read as ? 0 ?. 3: re3 port bit is available only as an input pin when the mclre configuration bit is ? 0 ?. 4: for these reset values, see section 4.0 ?reset? of the ?pic18f2420/2520/4420/4520 data sheet? (ds39631).
? 2009 microchip technology inc. ds39755c-page 35 pic18f2423/2523/4423/4523 3.0 special features of the cpu 3.1 device id registers the device id registers are read-only registers. they identify the device type and revision for device pro- grammers and can be read by firmware using table reads. table 3-1: device ids note: for additional details on the configuration bits, refer to section 23.1 ?configuration bits? in the ?pic18f2420/2520/4420/4520 data sheet? (ds39631). device id informa- tion presented in this section is for the pic18f2423/2523/4423/4523 devices only. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 3ffffeh devid1 (1) dev3 dev2 dev1 dev0 rev3 rev2 rev1 rev0 xxxx xxxx (2) 3fffffh devid2 (1) dev11 dev10 dev9 dev8 dev7 dev6 dev5 dev4 xxxx xxxx (2) legend: x = unknown, u = unchanged, ? = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: devid registers are read-only and c annot be programmed by the user. 2: see register 3-1 and register 3-2 for devid1 and devid2 values. register 3-1: devid1: device id register 1 for pic18f2423/2523/4423/4523 rrrrrrrr dev3 dev2 dev1 dev0 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-4 dev<3:0>: device id bits 1101 = pic18f4423 1001 = pic18f4523 0101 = pic18f2423 0001 = pic18f2523 bit 3-0 rev<3:0>: revision id bits these bits are used to indicate the device revision.
pic18f2423/2523/4423/4523 ds39755c-page 36 ? 2009 microchip technology inc. register 3-2: devid2: device id register 2 for pic18f2423/2523/4423/4523 rrrrrrrr dev11 (1) dev10 (1) dev9 (1) dev8 (1) dev7 (1) dev6 (1) dev5 (1) dev4 (1) bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-0 dev<11:4>: device id bits (1) these bits are used with the dev<3:0> bits in device id register 1 to identify the part number. 0001 0001 = pic18f2423/2523 devices 0001 0000 = pic18f4423/4523 devices note 1: these values for dev<11:4> may be shared with other devices. the specific device is always identified by using the entire dev<11:0> bit sequence.
? 2009 microchip technology inc. ds39755c-page 37 pic18f2423/2523/4423/4523 4.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ............................................................... ....................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................... ............................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports ...................................................................................................................... .200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the mclr /v pp /re3 pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 should be used when applying a ?low? level to the mclr /v pp / re3 pin, rather than pulling this pin directly to v ss . note: other than some basic data, this section documents only the pic18f2423/2523/4423/4523 devices? specifi- cations that differ from those of the pic18f2420/2520/4420/4520 devices. for detailed information on the electrical specifications shared by the pic18f2423/2523/4423/4523 and pic18f2420/2520/4420/4520 devices, see the ?pic18f2420/2520/4420/4520 data sheet? (ds39631). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic18f2423/2523/4423/4523 ds39755c-page 38 ? 2009 microchip technology inc. figure 4-1: pic18f2423/2523/4423/4523 voltage-frequency graph (industrial) figure 4-2: pic18f2423/2523/4423/4523 voltage-frequency graph (extended) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v 4.2v pic18f2423/2523/4423/4523 frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 25 mhz 5.0v 3.5v 3.0v 2.5v 4.2v pic18f2423/2523/4423/4523
? 2009 microchip technology inc. ds39755c-page 39 pic18f2423/2523/4423/4523 figure 4-3: pic18lf2423/2523/4423/4523 voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz note: v ddappmin is the minimum voltage of the pic ? device in the application. 4 mhz 4.2v pic18lf2423/2523/4423/4523
pic18f2423/2523/4423/4523 ds39755c-page 40 ? 2009 microchip technology inc. table 4-1: a/d converter characteristics: pic18f2423/2523/4423/4523 (industrial) pic18lf2423/2523/4423/4523 (industrial) param no. sym characteristic min typ max units conditions a01 n r resolution ? ? 12 bit v ref 3.0v a03 e il integral linearity error ? <1 2.0 lsb v dd = 3.0v v ref 3.0v ??2.0lsbv dd = 5.0v a04 e dl differential linearity error ? <1 +1.5/-1.0 lsb v dd = 3.0v v ref 3.0v ??+1.5/-1.0lsbv dd = 5.0v a06 e off offset error ? <1 5 lsb v dd = 3.0v v ref 3.0v ??3lsbv dd = 5.0v a07 e gn gain error ? <1 1.25 lsb v dd = 3.0v v ref 3.0v ??2.00lsbv dd = 5.0v a10 ? monotonicity guaranteed (1) ?v ss v ain v ref a20 v ref reference voltage range (v refh ? v refl ) 3?v dd ? v ss v for 12-bit resolution. a21 v refh reference voltage high v ss + 3.0v ? v dd + 0.3v v for 12-bit resolution. a22 v refl reference voltage low v ss ? 0.3v ? v dd ? 3.0v v for 12-bit resolution. a25 v ain analog input voltage v refl ?v refh v a30 z ain recommended impedance of analog voltage source ??2.5k a50 i ref v ref input current (2) ? ? ? ? 5 150 a a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never dec reases with an increase in the input voltage and has no missing codes. 2: v refh current is from the ra3/an3/v ref + pin or v dd , whichever is selected as the v refh source. v refl current is from the ra2/an2/v ref -/cv ref pin or v ss , whichever is selected as the v refl source.
? 2009 microchip technology inc. ds39755c-page 41 pic18f2423/2523/4423/4523 figure 4-4: a/d conversion timing table 4-2: a/d conversion requirements param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 f xxxx 0.8 12.5 (1) st osc based, v ref 3.0v pic18 lf xxxx 1.4 25.0 (1) sv dd = 3.0v; t osc based, v ref full range pic18 f xxxx ? 1 s a/d rc mode pic18 lf xxxx ? 3 sv dd = 3.0v; a/d rc mode 131 t cnv conversion time (not including acquisition time) (2) 13 14 t ad 132 t acq acquisition time (3) 1.4 ? s 135 t swc switching time from convert sample ? (note 4) 137 t dis discharge time 0.2 ? s note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres registers may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance (r s ) on the input channels is 50 . 4: on the following cycle of the device clock. 131 130 132 bsf adcon0, go q4 a/d clk (1) a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 11 10 9 3 2 1 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy 0
pic18f2423/2523/4423/4523 ds39755c-page 42 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds39755c-page 43 pic18f2423/2523/4423/4523 5.0 packaging information for packaging information, see section 28.0 ?packaging information? in the ?pic18f2420/2520/4420/4520 data sheet? (ds39631).
pic18f2423/2523/4423/4523 ds39755c-page 44 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds39755c-page 45 pic18f2423/2523/4423/4523 appendix a: revision history revision a (june 2006) original data sheet for pic18f2423/2523/4423/4523 devices. revision b (january 2007) this revision includes updates to the packaging diagrams. revision c (september 2009) electrical specifications updated. preliminary condition status removed. converted document to the ?mini data sheet? format. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences features pic18f2423 pic18f2523 pic18f4423 pic18f4523 program memory (bytes) 16384 32768 16384 32768 program memory (instructions) 8192 16384 8192 16384 interrupt sources 19 19 20 20 i/o ports ports a, b, c, (e) ports a, b, c, (e) ports a, b, c, d, e ports a, b, c, d, e capture/compare/pwm modules 2 2 1 1 enhanced capture/compare/pwm modules 00 1 1 parallel communications (psp) no no yes yes 12-bit analog-to-digital module 10 input channels 10 input channels 13 input channels 13 input channels packages 28-pin pdip 28-pin soic 28-pin qfn 28-pin pdip 28-pin soic 28-pin qfn 40-pin pdip 44-pin tqfp 44-pin qfn 40-pin pdip 44-pin tqfp 44-pin qfn
pic18f2423/2523/4423/4523 ds39755c-page 46 ? 2009 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available
? 2009 microchip technology inc. ds39755c-page 47 pic18f2423/2523/4423/4523 appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442? . the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and differences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration ?. this application note is available as literature number ds00726.
pic18f2423/2523/4423/4523 ds39755c-page 48 ? 2009 microchip technology inc. notes:
ds39755c-page 49 ? 2009 microchip technology inc. index a a/d ...................................................................................... 25 a/d converter interrupt, configuring .......................... 29 acquisition requirements ........................................... 30 adcon0 register....................................................... 25 adcon1 register....................................................... 25 adcon2 register....................................................... 25 adresh register................................................. 25, 28 adresl register ....................................................... 25 analog port pins, configuring ..................................... 32 associated registers .................................................. 34 configuring the module ............................................... 29 conversion clock (t ad ) .............................................. 31 conversion status (go/done bit) ............................. 28 conversions ................................................................ 33 converter characteristics ........................................... 40 discharge .................................................................... 33 operation in power-managed modes ......................... 32 selecting and configuring acquisition time ............... 31 special event trigger (ccp)....................................... 34 use of the ccp2 trigger............................................. 34 absolute maximum ratings ................................................ 37 adcon0 register............................................................... 25 go/done bit.............................................................. 28 adcon1 register............................................................... 25 adcon2 register............................................................... 25 adresh register............................................................... 25 adresl register ......................................................... 25, 28 analog-to-digital converter. see a/d. b block diagrams a/d .............................................................................. 28 analog input model ..................................................... 29 pic18f2423/2523 (28-pin) ......................................... 12 pic18f4423/4523 (40/44-pin) .................................... 13 c compare (ccp module) special event trigger.................................................. 34 conversion considerations ................................................. 46 customer change notification service ............................... 51 customer notification service............................................. 51 customer support ............................................................... 51 d device differences .............................................................. 45 device overview ................................................................... 9 details on individual family members ........................ 10 features (table)........................................................... 11 new core features ....................................................... 9 other special features ............................................... 10 documentation related data sheet....................................................... 9 e electrical characteristics..................................................... 37 equations a/d acquisition time................................................... 30 a/d minimum charging time ...................................... 30 calculating the minimum required acquisition time.................................................. 30 errata .................................................................................... 8 i internet address ................................................................. 51 interrupt sources a/d conversion complete .......................................... 29 m microchip internet web site................................................ 51 migration from baseline to enhanced devices ................... 46 migration from high-end to enhanced devices.................. 47 migration from mid-range to enhanced devices ............... 47 p packaging information ........................................................ 43 pin functions mclr /v pp /re3 .................................................... 14, 18 osc1/clki/ra7 ................................................... 14, 18 osc2/clko/ra6 ................................................. 14, 18 ra0/an0............................................................... 15, 19 ra1/an1............................................................... 15, 19 ra2/an2/v ref -/cv ref ......................................... 15, 19 ra3/an3/v ref + ................................................... 15, 19 ra4/t0cki/c1out .............................................. 15, 19 ra5/an4/ss /hlvdin/c2out.............................. 15, 19 rb0/int0/flt0/an12........................................... 16, 20 rb1/int1/an10 .................................................... 16, 20 rb2/int2/an8 ...................................................... 16, 20 rb3/an9/ccp2 .................................................... 16, 20 rb4/kbi0/an11 .................................................... 16, 20 rb5/kbi1/pgm..................................................... 16, 20 rb6/kbi2/pgc ..................................................... 16, 20 rb7/kbi3/pgd ..................................................... 16, 20 rc0/t1oso/t13cki ............................................ 17, 21 rc1/t1osi/ccp2................................................. 17, 21 rc2/ccp1 .................................................................. 17 rc2/ccp1/p1a .......................................................... 21 rc3/sck/scl ...................................................... 17, 21 rc4/sdi/sda ....................................................... 17, 21 rc5/sdo.............................................................. 17, 21 rc6/tx/ck ........................................................... 17, 21 rc7/rx/dt........................................................... 17, 21 rd0/psp0 .................................................................. 22 rd1/psp1 .................................................................. 22 rd2/psp2 .................................................................. 22 rd3/psp3 .................................................................. 22 rd4/psp4 .................................................................. 22 rd5/psp5/p1b .......................................................... 22 rd6/psp6/p1c .......................................................... 22 rd7/psp7/p1d .......................................................... 22 re0/rd /an5............................................................... 23 re1/wr /an6.............................................................. 23 re2/cs /an7............................................................... 23 v dd ....................................................................... 17, 23 v ss ....................................................................... 17, 23 pinout i/o descriptions pic18f2423/2523 ...................................................... 14 pic18f4423/4523 ...................................................... 18 power-managed modes and a/d operation ...................................................... 32
pic18f2423/2523/4423/4523 ds39755c-page 50 ? 2009 microchip technology inc. r reader response ............................................................... 52 registers adcon0 (a/d control 0) ............................................ 25 adcon1 (a/d control 1) ............................................ 26 adcon2 (a/d control 2) ............................................ 27 devid1 (device id 1) ................................................. 35 devid2 (device id 2) ....................................................... 36 revision history .................................................................. 45 s special features of the cpu............................................... 35 t timing diagrams a/d conversion........................................................... 41 timing diagrams and specifications a/d conversion requirements ................................... 41 v voltage-frequency graphics pic18f2423/2523/4423/4523 (extended) .................. 38 pic18f2423/2523/4423/4523 (industrial)................... 38 pic18lf2423/2523/4423/4523 (industrial)................. 39 w www address ................................................................... 51 www, on-line support ......... .............................................. 8
? 2009 microchip technology inc. ds39755c-page 51 pic18f2423/2523/4423/4523 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic18f2423/2523/4423/4523 ds39755c-page 52 ? 2009 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39755c pic18f2423/2523/4423/4523 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2009 microchip technology inc. ds39755c-page 53 pic18f2423/2523/4423/4523 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device pic18f2423 (1) , pic18f2523 (1) , pic18f4423t (2) , pic18f4523t (2) ; v dd range 4.2v to 5.5v pic18f2423 (1) , pic18f2523 (1) , pic18f4423t (2) , pic18f4523t (2) ; v dd range 2.0v to 5.5v temperature range i = -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package pt = tqfp (thin quad flat pack) ml = qfn so = soic sp = skinny plastic dip p=pdip pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18f4523-i/p 301 = industrial temp., pdip package, extended v dd limits, qtp pattern #301. b) pic18f4523-i/pt = industrial temp., tqfp package, extended v dd limits. c) pic18f4523-e/p = extended temp., pdip package, normal v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel plcc, and tqfp packages only.
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