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s524lb0x91/b0xb1 32k/64k-bit serial eeprom data sheet 7 - 1 overview the s524lb0d91/b0db1 serial eeprom has a 32/64 kbits (4,096/8,192 bytes) capacity, supporting the standard i 2 c? - bus serial interface. it is fabricated using samsung?s most advanced cmos technology. one of its major features is a hardware - based wri te protection circuit for the entire memory area. hardware - based write protection is controlled by the state of the write - protect (wp) pin. using one - page write mode, you can load up to 32 bytes of data into the eeprom in a single write operation. another significant feature of the s524lb0d91/b0db1 is its support for fast mode and standard mode. features i 2 c - bus interface two - wire serial interface automatic word address increment eeprom 32/64 kbits (4,096/8,192 bytes) storage area 32 - byte page bu ffer typical 3 - millisecond write cycle time with auto - erase function hardware - based write protection for the entire eeprom (using the wp pin) eeprom programming voltage generated on chip 1,000,000 erase/write cycles 100 years data retention operating characteristics operating voltage: 2.0 v to 5.5 v operating current ? maximum write current: < 3 ma at 5.5 v ? maximum read current: < 500 m a at 5.5 v ? maximum stand - by current: < 2 m a at 2.0 v operating temperature range: ? ? 25 c to + 70 c (commercial) ? ? 40 c to + 85 c (industrial) operating clock frequencies ? 100 khz at standard mode ? 400 khz at fast mode electrostatic discharge (esd) ? 5,000 v (hbm) ? 500 v (mm) packages 8 - pin dip and sop
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 2 slave address comparator data register column decoder hv generation timing control d out and ack row decoder eeprom cell array 4,096 x 8 bits 8,192 x 8 bits sda a0 a1 a2 wp scl start/stop logic word address pointer control logic figure 7 - 1. s524lb0d91/b0db1 block diagram
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 3 s524ab0d91/b0db1 v cc wp scl sda a0 a1 a2 v ss note: the s524ab0d91/b0db1 is available in 8-pin dip, sop, and tssop package. figure 7 - 2. pin assignment diagram table 7 - 1. s524lb0d91/b0db1 pin descriptions name type description circuit number a0, a1, a2 input input pins for device address selection. to configure a device addr ess, these pins should be connected to the v cc or v ss of the device. 1 v ss ? ground pin. ? sda i/o bi - directional data pin for the i 2 c - bus serial data interface. schmitt trigger input and open - drain output. an external pull - up resistor must be connected to v dd. 3 scl input schmitt trigger input pin for serial clock input. 2 wp input input pin for hardware write protection control. if you tie this pin to v cc, the write function is disabled to protect previously written data in the entire memory; if you tie it to v ss , t he write function is enabled. 1 v cc ? single power supply. ? note : see the following page for diagrams of pin circuit types 1, 2, and 3.
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 4 a0, a1, a2, wp figure 7 - 3. pin circuit type 1 scl noise filter figure 7 - 4. pin circuit type 2 sda v ss data out noise filter data in figure 7 - 5. pin circuit type 3
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 5 function description i 2 c - bus interface the s524lb0d91/b0db1 supports the i 2 c - bus serial interface data transmission protocol. the two - wire bus consists of a serial data line (sda) and a serial clock line (scl). the sda and the scl lines must be connected to v cc by a pull - up resistor that is located somewhere on the bus. any device that puts data onto the bus is defined as a ?transmitter? and any device that gets data from the bus is a ?receiver.? the bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. using the a0, a1, and a2 input pins, up to eight s524lb0d91/b0db1 devices can be connected to the same i 2 c - b us as slaves (see figure 7 - 6). both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active. sda bus master (transmitter/ receiver) mcu s524lb0d91/ b0xb1 tx/rx a0 a1 a2 slave 1 to v cc or v ss s524lb0d91/ b0xb1 tx/rx a0 a1 a2 slave 2 to v cc or v ss s524lb0d91/ b0xb1 tx/rx a0 a1 a2 slave 3 to v cc or v ss s524lb0d91/ b0xb1 tx/rx a0 a1 a2 slave 8 to v cc or v ss r v cc r v cc scl figure 7 - 6. typical configuration
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 6 i 2 c - bus protocols here are several rules for i 2 c - bus transfers: ? a new data transfer can be initiated only when the bus is currently not busy. ? msb is always transferred first in transmitting data. ? during a data transfer, the data line (sda) must remain stable when ever the clock line (scl) is high. the i 2 c - bus interface supports the following communication protocols: bus not busy : the sda and the scl lines remain in high level when the bus is not active. start condition : a start condition is initiated by a high - to - low transition of the sda line while scl remains in high level. all bus commands must be preceded by a start condition. stop condition : a stop condition is initiated by a low - to - high transition of the sda line while scl remains in high level. all bus operations must be completed by a stop condition (see figure 7 - 7). scl sda start condition data or ack valid data change stop condition ~ ~ ~ ~ figure 7 - 7. data transmission sequence data valid : following a start condition, the data becomes valid if the data line remains stable for the duration of the high period of scl. new data must be put onto the bus while scl is low. bus timing is one clock pulse per data bit. the number of data bytes to be transferred is determined by the master device. the total number of bytes that can be transferred in one operation is theoretically un limited. ack (acknowledge) : an ack signal indicates that a data transfer is completed successfully. the transmitter (the master or the slave) releases the bus after transmitting eight bits. during the 9th clock, which the master generates, the receiver pulls the sda line low to acknowledge that it has successfully received the eight bits of data (see figure 7 - 8). but the slave does not send an ack if an internal write cycle is still in progress. in data read operations, the slave releases the sda line after transmitting 8 bits of data and then monitors the line for an ack signal during the 9th clock period. if an ack is detected but no stop condition, the slave will continue to transmit data. if an ack is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand - by mode.
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 7 master scl line data from transmitter ack ack from receiver bit 9 bit 1 figure 7 - 8. acknowledge response from receiver slave address : after the master initiates a start condition, it must outpu t the address of the device to be accessed. the most significant four bits of the slave address are called the ?device identifier.? the identifier for the s524lb0d91/b0db1 is ?1010b?. the next three bits comprise the address of a specific device. the device address is defined by the state of the a0, a1, and a2 pins. using this addressing scheme, you can cascade up to eight s524lb0d91/b0db1s on the bus (see figure 7 - 9 below). read/write : the final (eighth) bit of the slave address defines the type of oper ation to be performed. if the r / w bit is ?1?, a read operation is executed. if it is ?0?, a write operation is executed. slave address 1 0 1 0 a2 a1 a0 r/w device identifier device select first word address second word address x x x (2) a12 (1) a11 a10 a9 a8 first (high) address a7 a6 a5 a4 a3 a2 a1 a0 second (low) address notes: 1. the a12 is "don't care" for the s524lb0x91. 2. x = don't care. figure 7 - 9. device address
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 8 byte write operation a write operation requires 2 - byte word addresses, the first (high) word address and the second (low) word address. in a byte write operation, the master transmits the slave address, the first word address, the second word address, and one data byte to the s524lb0d91/b0db1 slave device (see figure 7 - 10). slave address first word address second word address data start stop a c k a c k a c k a c k figur e 7 - 10. byte write operation following a start condition, the master puts the device identifier (4 bits), the device address (3 bits), and an r / w bit set to ?0? onto the bus. upon the receipt of the slave address, the s524lb0d91/b0db1 responds with an ack. and the master transmits the first word address, the second word address, and one byte data to be written into the addressed memory location. the master terminates the transfer by generating a stop condition, at which time the s524lb0d91/b0db1 begins the internal write cycle. while the internal write cycle is in progress, all s524lb0d91/b0db1 inputs are disabled and the s524lb0d91/b0db1 does not respond to any additional request from the master.
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 9 page write operation the s524lb0d91/b0db1 can also perform 32 - byte page write operation. a page write operation is initiated in the same way as a byte write operation. however, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 31 additional bytes. the s524lb0d91/b0db1 responds with an ack each time it receives a complete byte of data (see figure 7 - 11). first word address second word address slave address start stop a c k a c k a c k data byte 0 data byte n (n <= 31) a c k a c k a c k ... figure 7 - 11. page write operation the s524lb0d91/b0db1 automatically increments the word address pointer each time it receives a complete data byte. when one byte is received, the internal word address pointer increments to the next address so that the next data byte can be received. if the master transmits more than 32 bytes before it generates a stop condition to end the page write operation, the s52 4lb0d91/b0db1 word address pointer value ?rolls over? and the previously received data is overwritten. if the master transmits less than 32 bytes and generates a stop condition, the s524lb0d91/b0db1 writes the received data to the corresponding eeprom address. during a page write operation, all inputs are disabled and there would be no response to additional requests from the master until the internal write cycle is completed.
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 10 polling for an ack s ignal when the master issues a stop condition to initiate a write cycle, the s524lb0d91/b0db1 starts an internal write cycle. the master can then immediately begin polling for an ack from the slave device to determine whether the write cycle is completed. to poll for an ack signal in a write operation, the master issues a start condition followed by the slave address. as long as the s524lb0d91/b0db1 remains busy with the write operation, no ack is returned. when the s524lb0d91/b0db1 completes the write operation, it returns an ack and the master can then proceed wi th the next read or write operation (see figure 7 - 12). send stop condition to initiate write cycle send write command send start condition start next operation no yes ack = ?0? ? send slave address with r/ bit = ?0? w figure 7 - 12. master polling for an ack signal from a slave device
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 11 hardware - based write protection you can also write - protect the entire memory area of the s524lb0d91/b0db1. this write protection is controlled by the state of the write protect (wp) pin. when the wp pin is connected to v cc , any attempt to write a value to it is ignored. the s524lb0d91/b0db1 will acknowledge slave and word addresses, but it will not generate an acknowledge after rece iving the first byte of data. in this situation, the write cycle will not be started when a stop condition is generated. by connecting the wp pin to v ss , t he write function is allowed for the entire memory. these write protection features effectively change the eeprom to a rom in order to protect data from being overwritten. whenever the write function is disabled, a slave address and word addresses are acknowledged on the bus, but data bytes are not acknowledged. current address byte read operation the in ternal word address pointer maintains the address of the last word accessed, incremented by one. therefore, if the last access (either read or write) was to the address ?n?, the next read operation would be to access data at address ?n+1?. when the s524lb0d91/b0db1 receives a slave address with the r / w bit set to ?1?, it issues an ack and sends the eight bits of data. in a current address byte read operation, the master does not acknowledge the data, and it generates a stop condition, forcing the s524lb0d9 1/b0db1 to stop the transmission (see figure 7 - 13). slave address data start a c k n o a c k stop figure 7 - 13. current address byte read operation
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 12 random address byte read operation using random read operations, the master can access any memory location at any time. before it issues the slave address with the r / w bit set to ?1?, the master must first perform a ?dummy? write operation. this operation is performed in the following steps: 1. the master first issues a start condition, the slave address, and the word address (the first and the second add resses) to be read. (this step sets the internal word address pointer of the s524lb0d91/b0db1 to the desired address.) 2. when the master receives an ack for the word address, it immediately re - issues a start condition followed by another slave address, with the r / w bit set to ?1?. 3. the s524lb0d91/b0db1 then sends an ack and the 8 - bit data stored at the pointed address. 4. at this point, the master does not acknowledge the transmission, generating a stop condition. 5. the s524lb0d91/b0db1 stops transmi tting data and reverts to stand - by mode (see figure 7 - 14). first word address second word address slave address start stop a c k a c k a c k a c k slave address start data n o a c k figure 7 - 14. random address byte read operation
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 13 sequential read oper ation sequential read operations can be performed in two ways: current address sequential read operation, and random address sequential read operation. the first data is sent in either of the two ways, current address byte read operation or random address byte read operation described earlier. if the master responds with an ack, the s524lb0d91/b0db1 continues transmitting data. if the master does not issue an ack, generating a stop condition, the slave stops transmission, ending the sequential read operation. using this method, data is output sequentially from address ?n? followed by address ?n+1?. the word address pointer for read operations increments to all word addresses, allowing the entire eeprom to be read sequentially in a single operation. after the entire eeprom is read, the word address pointer ?rolls over? and the s524lb0d91/b0db1 continues to transmit data for each a ck it receives from the master (see figure 7 - 15). slave address data (n) start a c k n o a c k stop data (n+x) a c k a c k ~ ~ figure 7 - 15. sequential read operation
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 14 electrical data table 7 - 2. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v cc ? ? 0.3 to + 7.0 v input voltage v in ? ? 0.3 to + 7.0 v output voltage v o ? ? 0.3 to + 7.0 v operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c electrostatic discharge v esd hbm 5000 v mm 500 table 7 - 3. d.c. electrical characteristics (t a = ? 25 c to + 70 c (commercial), ? 40 c to + 85 c (industrial), v cc = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input low voltage v il scl, sda, a0, a1, a2 ? ? 0.3 v cc v input high voltage v ih 0.7 v cc ? ? v input leakage current i li v in = 0 to v cc ? ? 10 a output leakage current i lo v o = 0 to v cc ? ? 10 a output low voltage v ol i ol = 3 ma, v cc = 2.0 v ? ? 0.4 v supply current write i cc1 v cc = 5.5 v, 400 khz ? ? 3 ma i cc2 v cc = 2.0 v, 100 khz ? ? 1 read i cc3 v cc = 5.5 v, 4 00 khz ? ? 0.5 i cc4 v cc = 2.0 v, 100 khz ? ? 0.2 stand - by current i cc5 v cc = sda = scl = 5.5 v, all other inputs = 0 v ? ? 5 a i cc6 v cc = sda = scl = 2.0 v, all other inputs = 0 v ? ? 2
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 15 table 7 - 3. d.c. electrical characteristics (continued) (t a = ? 25 c to + 70 c (commercial), ? 40 c to + 85 c (industrial), v cc = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input capacitance c in 25 c, 1mhz, v cc = 5 v, v in = 0 v, a0, a1, a2, scl and wp pin ? ? 10 pf input/output capacit ance c i/o 25 c, 1mhz, v cc = 5 v, v i/o = 0 v, sda pin ? ? 10 table 7 - 4. a.c. electrical characteristics (t a = ? 25 c to + 70 c (commercial), ? 40 c to + 85 c (industrial), v cc = 2.0 v to 5.5 v) parameter symbol conditions v cc = 2.0 to 5.5 v (standard mode) v cc = 4.5 to 5.5 v (fast mode) unit min max min max external clock frequency f clk ? 0 100 (1) 0 400 (1) khz clock high time t high ? 4 ? 0.6 ? m s clock low time t low ? 4.7 ? 1.3 ? m s rising time t r sda, scl ? 1 ? 0.3 m s falling time t f sd a, scl ? 0.3 ? 0.3 m s start condition hold time t hd:sta ? 4 ? 0.6 ? m s start condition setup time t su:sta ? 4.7 ? 0.6 ? m s data input hold time t hd:dat ? 0 ? 0 ? m s data input setup time t su:dat ? 0.25 ? 0.1 ? m s stop condition setup time t su:sto ? 4 ? 0.6 ? m s bus free time t buf before new transmission 4.7 ? 1.3 ? m s data output valid from clock low (2) t aa ? 0.3 3.5 ? 0.9 m s noise spike width t sp ? ? 100 ? 50 ns write cycle time t wr ? ? 5 ? 5 ms notes : 1. upon customers request, up to 400 khz ( max.) in standard mode and 1 mhz in fast mode are available. 2. when acting as a transmitter, the s524lb0d91/b0db1 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of scl. this is required to avoid unintended generation of a start or stop condition.
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 16 scl t low t f t r sda in t su:sta t hd:sta t hd:dat t su:dat t su:sto t high sda out t buf t aa figure 7 - 16. timing diagram for bus operations 8th bit wordn scl sda start condition ~ ~ ~ ~ ~ ~ t wr stop condition ack figure 7 - 17. write cycle timing diagram
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 17 characteristic curve s note the characteristic values shown in the following graphs are based on actual test measurements. they do not, however, represent guaranteed operating values. (frequency = 100 khz) v cc (v) i cc (ma) 0 0.4 0.8 1.2 1.6 2.0 1.5 2 .5 3 .5 4 .5 5 .5 temp = -40 c temp = -25 c temp = 25 c temp = 70 c temp = 85 c figure 7 - 18. write current
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 18 (frequency = 100 khz) v cc (v) i cc (ua) 0 100 200 300 400 500 1.5 2 .5 3 .5 4 .5 5 .5 temp = -40 c temp = -25 c temp = 25 c temp = 70 c temp = 85 c figure 7 - 19. read current (frequency = 100 khz) v cc (v) i cc (ua) 0 0.3 0.6 0.9 1.2 1.5 1.5 2 .5 3 .5 4 .5 5 .5 temp = -40 c temp = -25 c temp = 25 c temp = 70 c temp = 85 c figure 7 - 20. stand - by current
data sheet s524lb0d 91/b0db1 serial eepr om 7 - 19 i ol (ma) v ol (v) (t a = 25 c) 1 2 3 4 6 0 5 v dd = 2 v v dd = 3 v v dd = 4 v v dd = 5 v v dd = 6 v 0 10 20 30 40 50 figure 7 - 21. output low voltage
s524lb0d91/b0db1 ser ial eeprom data she et 7 - 20 notes

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