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september 2012 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 fan7389 ? 3-phase half-bridge gate-drive ic fan7389 3-phase half-bridge gate-drive ic features ? floating channel for bootst rap operation to +600 v ? typically 350 ma/650 ma sourcing/sinking current driving capability for all channels ? extended allowable negative v s swing to -9.8 v for signal propagation at v dd =v bs =15 v ? output in-phase with input signal ? over-current shutdown turns off all six drivers ? matched propagation delay for all channels ? 3.3 v and 5.0 v input logic compatible ? adjustable fault-clear timing ? built-in advanced input filter ? built-in shoot-through prevention logic ? built-in soft turn-off function ? common-mode dv/dt noise canceling circuit ? built-in uvlo functions for all channels applications ? 3-phase motor inverter driver ? air conditioners ? washing machines ? general-purpose three-phase inverters description the fan7389 is a monolithic three-phase half-bridge gate-drive ic designed for high-voltage, high-speed driving mosfets and igbts operating up to +600 v. fairchild?s high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances. an advanced level-shift circuit allows high-side gate driver operation up to v s = -9.8 v (typical) for v bs =15 v. the protection functions include under-voltage lockout and inverter over-current trip with an automatic fault- clear function. over-current protection that terminates all six outputs can be derived from an external current-sense resistor. an open-drain fault signal is provided to indicate that an over-current or under-voltage shutdown has occurred. the uvlo circuits prevent malfunction when v dd and v bs are lower than the specif ied threshold voltage. output drivers typically source and sink 350 ma and 650 ma, respectively; which is suitable for three-phase half-bridge applications in motor drive systems. ordering information part number package operating temperature packing method fan7389mx1 (1) 28-lead, small outline int egrated circuit wide body (soic) -40 to +125c tape & reel note: 1. these devices passed wave soldering test by jesd22a-111. 28-soic
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 2 fan7389 ? 3-phase half-bridge gate-drive ic typical application diagram figure 1. 3-phase bldc motor drive application internal block diagram figure 2. functional block diagram
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 3 fan7389 ? 3-phase half-bridge gate-drive ic pin configuration figure 3. pin configuration pin definitions pin name description 1 v dd logic and low-side gate driver power supply voltage 2 hin1 logic input 1 for high-side gate 1 driver 3 hin2 logic input 2 for high-side gate 2 driver 4 hin3 logic input 3 for high-side gate 3 driver 5 lin1 logic input 1 for low-side gate 1 driver 6 lin2 logic input 2 for low-side gate 2 driver 7 lin3 logic input 3 for low-side gate 3 driver 8 fault output with open drain (indicates over-current and low-side under-voltage) 9 cs analog input for over-current shutdown 10 en logic input for shutdown functionality 11 rcin an external rc network input used to define the fault-clear delay 12 v ss logic ground 13 com low-side driver return 14 lo3 low-side gate driver 3 output 15 lo2 low-side gate driver 2 output 16 lo1 low-side gate driver 1 output 17, 21, 25 nc no connect 18 v s3 high-side driver 3 floating supply offset voltage 19 ho3 high-side driver 3 gate driver output 20 v b3 high-side driver 3 floating supply 22 v s2 high-side driver 2 floating supply offset voltage 23 ho2 high-side driver 2 gate driver output 24 v b2 high-side driver 2 floating supply 26 v s1 high-side driver 1 floating supply offset voltage 27 ho1 high-side driver 1 gate driver output 28 v b1 high-side driver 1 floating supply fo
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 4 fan7389 ? 3-phase half-bridge gate-drive ic absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. t a =25c, unless otherwise specified. symbol parameter min. max. unit v s high-side floating offset voltage v b1,2,3 -25.0 v b1,2,3 +0.3 v v b high-side floating supply voltage -0.3 625.0 v v dd low-side and logic-fixed supply voltage -0.3 25.0 v v ho high-side floating output voltage v ho1,2,3 v s1,2,3 -0.3 v b1,2,3 +0.3 v v lo low-side floating output voltage v lo1,2,3 -0.3 v dd +0.3 v v in input voltage (hinx, linx, cs, and en) -0.3 5.5 v v fo fault output voltage ( ) -0.3 v dd +0.3 v pw hin high-side input pulse width 500 ns dv s /dt allowable offset voltage slew rate 50 v/ns p d power dissipation (2,3,4) 1.4 w ja thermal resistance 70 c/w t j junction temperature 150 c t stg storage temperature -55 150 c notes: 2. mounted on 76.2 x 114.3 x 1.6 mm pcb (fr-4 glass epoxy material). 3. refer to the following standards: jesd51-2: integral circuits thermal test met hod environmental conditions - natural convection jesd51-3: low effective thermal conductivity test board for leaded surface-mount packages. 4. do not exceed p d under any circumstances. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v b1,2,3 high-side floating supply voltage v s1,2,3 +10 v s1,2,3 +20 v v s1,2,3 high-side floating supply offset voltage 6-v dd 600 v v dd low-side and logic fixed supply voltage 10 20 v v ho1,2,3 high-side output voltage v s1,2,3 v b1,2,3 v v lo1,2,3 low-side output voltage com v dd v v fo fault output voltage ( ) com v dd v v cs current-sense pin input voltage com 5 v v in logic input voltage (hin1,2,3 and lin1,2,3) com 5 v v ss logic ground -5 5 v t a ambient temperature -40 +125 c fo fo
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 5 fan7389 ? 3-phase half-bridge gate-drive ic electrical characteristics v bias (v dd , v bs1,2,3 ) = 15.0 v and t a = 25c unless otherwise specified. the v in and i in parameters are referenced to com and are applicable to all six channels. the v o and i o parameters are referenced to v s1,2,3 and com and are applicable to the respective output leads: ho1,2,3 and lo1,2,3. the v dduv parameters are referenced to com. the v bsuv parameters are referenced to v s1,2,3 . symbol parameter conditions min. typ. max. unit low-side power supply section i qdd quiescent v dd supply current v lin1,2,3 =0 v or 5 v, en=0 v 200 a i pdd operating v dd supply current f lin1,2,3 =20 khz, rms value 400 a v dduv+ v dd supply under-voltage positive-going threshold v dd =sweep 7.5 8.5 9.3 v v dduv- v dd supply under-voltage negative-going threshold v dd =sweep 7.0 8.0 8.7 v v ddhys v dd supply under-voltage lockout hysteresis v dd =sweep 0.5 v bootstrapped power supply section v bsuv+ v bs supply under-voltage positive-going threshold v bs1,2,3 =sweep 7.5 8.5 9.3 v v bsuv- v bs supply under-voltage negative-going threshold v bs1,2,3 =sweep 7.0 8.0 8.7 v v bshys v bs supply under-voltage lockout hysteresis v bs1,2,3 =sweep 0.5 v i lk offset supply leakage current v b1,2,3 =v s1,2,3 =600 v 10 a i qbs quiescent v bs supply current v hin1,2,3 =0v or 5 v, en=0v 10 50 80 a i pbs operating v bs supply current f hin1,2,3 =20 khz, rms value 200 420 480 a gate driver output section v oh high-level output voltage, v bias -v o i o =0 ma (no load) 100 mv v ol low-level output voltage, v o i o =0 ma (no load) 100 mv i o+ output high short-circuit pulse current (5) v o =0 v, v in =5 v with pw 10 s 250 350 ma i o- output low short-circuit pulsed current (5) v o =15 v, v in =0 v with pw 10 s 500 650 ma v s allowable negative v s pin voltage for hin signal propagation to ho -9.8 -7.0 v logic input section v ih logic "1" input voltage hin1 ,2,3, lin1,2,3 2.5 v v il logic "0" input voltage hin1 ,2,3, lin1,2,3 0.8 v i in+ logic input bias current (ho=lo=high) v in =5 v 100 a i in- logic input bias current (ho=lo=low) v in =0 v 2 a r in logic input pull-down resistance 50 k enable control section (en) v en+ enable positive-going threshold voltage 2.5 v v en- enable negative-going threshold voltage 0.8 v i en+ logic enable ?1? input bias current v en =5 v (pull-down=150k ) 33 a i en- logic enable ?0? input bias current v en =0 v 2 a continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 6 fan7389 ? 3-phase half-bridge gate-drive ic electrical characteristics v bias (v dd , v bs1,2,3 ) = 15.0 v and t a = 25c unless otherwise specified. the v in and i in parameters are referenced to com and are applicable to all six channels. the v o and i o parameters are referenced to v s1,2,3 and com and are applicable to the respective output leads: ho1,2,3 and lo1,2,3. the v dduv parameters are referenced to com. the v bsuv parameters are referenced to v s1,2,3 . symbol parameter conditions min. typ. max. unit over-current protection section v csth+ over-current detect positive threshold (5) 400 500 600 mv v csth- over-current detect negative threshold (5) 440 mv v cshys over-current detect hysteresis (5) 60 mv i csin short-circuit input current v csin =1 v 5 10 15 a i soft soft turn-off sink current 25 40 55 ma fault output section v rcinth+ rcin positive-going threshold voltage 3.3 v v rcinth- rcin negative-going threshold voltage 2.6 v v rcinhys rcin hysteresis voltage 0.7 v i rcin rcin internal current source c rcin =2 nf 3 5 7 a v fol fault output low level voltage v cs =1 v, i fo =1.5 ma 0.2 0.5 v r dsrcin rcin on resistance i rcin =1.5 ma 50 75 100 r dsfo fault output on resistance i fo =1.5 ma 90 130 170 note: 5. these parameters are guaranteed by design. dynamic electrical characteristics t a =25 c, v bias (v dd , v bs1,2,3 ) = 15.0 v, v s1,2,3 = com, c rcin =2 nf, and c load = 1000 pf unless otherwise specified. symbol parameter conditions min. typ. max. unit t on turn-on propagation delay v lin1,2,3 =v hin1,2,3 =0 v, v s1,2,3 =0 v 350 500 650 ns t off turn-off propagation delay v lin1,2,3 =v hin1,2,3 =5 v, v s1,2,3 =0 v 350 500 650 ns t r turn-on rise time v lin1,2,3 =v hin1,2,3 =0 v 20 50 100 ns t f turn-off fall time v lin1,2,3 =v hin1,2,3 =5 v 10 30 80 ns t en enable low to output shutdown delay 400 500 600 ns t csblt cs pin leading-edge blanking time (6) 200 300 400 ns t csfo time from cs triggering to (7) from v csc =1v to turn-off 630 ns t csoff time from cs triggering to all gate outputs turn-off (7) from v csc =1v to starting gate turn-off 640 ns t fltin input filtering time (8) (hinx, linx, en) 200 250 300 ns t fltclr fault-clear time 1.3 ms dt dead time 250 300 350 ns mdt dead-time matching (all six channels) 50 ns mt delay matching (all six channels) 50 ns pm output pulse-width matching (6,9) pw in > 1s 50 100 ns notes: 6. these parameters are guaranteed by design. 7. these parameters are referenced to specified c rcin (=2 nf), and proportional to value of c rcin as shown in figure 43. it is strongly recomm ended that the capacitor on r cin pin should be less than 5 nf. 8. the minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded. 9. pm is defined as pw in -pw out . fo fo
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 7 fan7389 ? 3-phase half-bridge gate-drive ic typical characteristics -40-20 0 20406080100120 350 400 450 500 550 600 650 high-side low-side t on [ns] temperature [c] -40-20 0 20406080100120 350 400 450 500 550 600 650 high-side low-side t off [ns] temperature [c] figure 4. turn-on propagation delay vs. temperature figure 5. turn-off propagation delay vs. temperature -40-20 0 20406080100120 20 30 40 50 60 70 80 90 100 high-side low-side t r [ns] temperature [c] -40-20 0 20406080100120 0 10 20 30 40 50 60 70 80 high-side low-side t f [ns] temperature [c] figure 6. turn-on rise time vs . temperature figure 7. turn-of f fall time vs. temperature -40-20 0 20406080100120 400 450 500 550 600 t en [ns] temperature [c] -40-20 0 20406080100120 1.0 1.2 1.4 1.6 1.8 2.0 t fltclr [ms] temperature [c] figure 8. enable low to output shutdown delay vs. temperature figure 9. fault-clear time vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 8 fan7389 ? 3-phase half-bridge gate-drive ic typical characteristics (continued) -40-20 0 20406080100120 200 250 300 350 400 dt1 dt2 dt [ns] temperature [c] -40-20 0 20406080100120 -50 -25 0 25 50 mdt [ns] temperature [c] figure 10. dead time vs. temperature figure 11.dead-time matching vs. temperature -40-20 0 20406080100120 -50 -40 -30 -20 -10 0 10 20 30 40 50 mton mtoff delay matching [ns] temperature [c] -40-20 0 20406080100120 -13 -12 -11 -10 -9 -8 -7 v s [v] temperature [c] figure 12. delay matching vs. temperature figure 13. a llowable negative v s v oltage vs. temperature -40-20 0 20406080100120 50 100 150 200 250 300 350 400 i qdd [ a] temperature [c] -40-20 0 20406080100120 0 20 40 60 80 100 i qbs [ a] temperature [c] figure 14. quiescent v dd supply current vs. temperature figure 15. quiescent v bs supply current vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 9 fan7389 ? 3-phase half-bridge gate-drive ic typical characteristics (continued) -40-20 0 20406080100120 100 200 300 400 500 600 700 i pdd [ a] temperature [c] -40-20 0 20406080100120 100 200 300 400 500 600 700 i pbs [ a] temperature [c] figure 16. operating v dd supply current vs. temperature figure 17.operating v bs supply current vs. temperature -40-20 0 20406080100120 7.5 8.0 8.5 9.0 9.5 v dduv+ [v] temperature [c] -40-20 0 20406080100120 6.5 7.0 7.5 8.0 8.5 9.0 9.5 v dduv- [v] temperature [c] figure 18. v dd uvlo+ vs. temperature figure 19. v dd uvlo- vs. temperature -40-20 0 20406080100120 7.5 8.0 8.5 9.0 9.5 v bsuv+ [v] temperature [c] -40-20 0 20406080100120 7.0 7.5 8.0 8.5 9.0 v bsuv- [v] temperature [c] figure 20. v bs uvlo+ vs. temperature figure 21. v bs uvlo- vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 10 fan7389 ? 3-phase half-bridge gate-drive ic typical characteristics (continued) -40-20 0 20406080100120 0 20 40 60 80 100 high-side low-side v oh [mv] temperature [c] -40-20 0 20406080100120 0 20 40 60 80 100 high-side low-side v ol [mv] temperature [c] figure 22. high-level output voltage vs. temperature figure 23.low-level output voltage vs. temperature -40-20 0 20406080100120 1.0 1.5 2.0 2.5 3.0 v ih [v] temperature [c] -40-20 0 20406080100120 0.5 1.0 1.5 2.0 2.5 3.0 v il [v] temperature [c] figure 24. logic high input voltage vs. temperature figure 25.logic low input voltage vs. temperature -40-20 0 20406080100120 60 80 100 120 140 160 i in+ [ a] temperature [c] -40-20 0 20406080100120 0.0 0.5 1.0 1.5 2.0 i in- [ a] temperature [c] figure 26. logic input high bias current vs. temperature figure 27.logic input low bias current vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 11 fan7389 ? 3-phase half-bridge gate-drive ic typical characteristics (continued) 10 12 14 16 18 20 0 20 40 60 80 100 r in [k ] supply voltage [v] 10 12 14 16 18 20 100 120 140 160 180 200 r en [k ] supply voltage [v] figure 28. input pull-down resistance vs. supply voltage figure 29.enable pin pull-down resistance vs. supply voltage 10 12 14 16 18 20 50 100 150 200 250 300 350 400 i qdd [ a] supply voltage [v] 10 12 14 16 18 20 0 20 40 60 80 100 i qbs [ a] supply voltage [v] figure 30. quiescent v dd supply current vs. supply voltage figure 31.quiescent v bs supply current vs. supply voltage 10 12 14 16 18 20 100 200 300 400 500 600 700 i pdd [ a] supply voltage [v] 10 12 14 16 18 20 100 200 300 400 500 600 700 i pbs [ a] supply voltage [v] figure 32. operating v dd supply current vs. supply voltage figure 33.operating v bs supply current vs. supply voltage
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 12 fan7389 ? 3-phase half-bridge gate-drive ic switching time definitions figure 34. switching time waveform definitions figure 35. input / output timing diagram figure 36. detailed view of b and c intervals during over-current protection
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 13 fan7389 ? 3-phase half-bridge gate-drive ic applications information 1. dead time dead time is automatically inserted whenever the dead time of the external two input signals (between hinx and linx signals) is shorter than internal fixed dead times (dt1 and dt2). otherwise, external dead times larger than internal dead times are not modified by the gate driver and internal dead-time waveform definition is shown in figure 37. figure 37. internal dead-time definitions 2. protection function 2.1 fault out ( ) and under-voltage lockout the high- and low-side drivers include under-voltage lockout (uvlo) protection circuitry that monitors the supply voltage for v dd and v bs independently. it can be designed to prevent malfunction when v dd and v bs are lower than the specified threshold voltage. also, the uvlo hysteresis prevents chattering during power- supply transitions. moreover, the fault signal ( ) goes to low state to operate reliably during power-on events, when the power supply (v dd ) is below the under-voltage lockout high threshold voltage for the circuit (during t 1 ~ t 2 ). the uvlo circuit is not otherwise activated; shown figure 38. figure 38. waveforms for under-voltage lockout 2.2 shoot-through protection the shoot-through protection circuitry prevents both high- and low-side switches from conducting at the same time, as shown figure 39. figure 39. shoot-through protection 2.3 enable input when the en pin is in high state, the gate driver operates normally. when a cond ition occurs that should shut down the gate driver, the en pin should be low. the enable circuitry has an input filter; the minimum input duration is specified by t fltin (typically 250 ns). figure 40. output enable timing waveform fo fo
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 14 fan7389 ? 3-phase half-bridge gate driver ic 2.4 fault-out ( ) and over-current protection fan7389 provides an integrated fault output ( ) and an adjustable fault-clear timer (t fltclr ). there are two situations that cause the gate driver to report a fault via the pin. the first is an under-voltage condition of low-side gate driver supply voltage (v dd ) and the second is when the current-sense pin (cs) recognizes a fault. once the fault condition occurs, the pin is internally pulled to com, the fault-clear timer is activated, and all outputs (h o1,2,3 and lo1,2,3) of the gate driver are turned off. the fault output stays low until the fault condition has been removed and the fault- clear timer expires. once th e fault-clear timer expires, the voltage on the pin returns to pull-up voltage. the fault-clear time (t fltclr ) is determined by an internal current source (i rcin =5 a) and an external c rcin at the rcin pin, as shown in this equation: ] [ , s i v c t rcin th rcin rcin fltclr = (1) the r dsrcin of the mosfet is a characteristic discharge curve with respect to the external capacitor c rcin . the time constant is defined by the external capacitor c rcin and the r dsrcin of the mosfet. the output of current-sens e comparator (cs_comp) passes a noise filter, which inhibits an over-current shutdown caused by parasitic voltage spikes of v cs . this corresponds to a voltage level at the comparator of v csth+ - v cshys = 500 mv - 60 mv =440 mv, where v cshys =60 mv is the hyster esis of the current comparator (cs_comp) as shown in figure 41. figure 41. over-current protection figure 42 shows the waveform definitions of rcin, fo and the low-side driver, which uses a soft turn-off method when an under-voltage condition of the low-side gate driver supply voltage (v dd ) or the current-sense pin (cs) recognizes a fault. once a fault condition occurs, the pin is internally pulled to com and all outputs (ho1,2,3 and lo1,2,3) of th e gate driver are turned off. low-side outputs decline linearly by the internal sink current source (i soft =40 ma) for soft turn-off, as shown in figure 42. figure 42. r cin and fault-clear waveform definition 2.5 recommended r cin figure 43 shows timing of t csoff and t csfo versus c rcin . it is strongly recommended that the capacitor on r cin pin should be less than 5 nf in order to properly protect power devices in over-current situations. 0123456789101112 200 300 400 500 600 700 800 900 1000 1100 1200 t csoff t csfo time [ns] c rcin [nf] figure 43. timing of t csoff and t csfo vs. c rcin 3. noise filter 3.1 input noise filter figure 44 shows the input nois e filter method, which has symmetry duration between the input signal (t input ) and the output signal (t output ) and helps to reject noise spikes and short pulses. this i nput filter is applied to the hinx, linx, and en inputs. the upper pair of waveforms (example a) shows an input signal duration (t input ) much longer than input filter time (t fltin ); it is approximately the same duration between the input signal time (t input ) and the output signal time (t output ). the lower pair of waveforms (example b) shows an input signal time (t input ) slightly longer than input filter time (t fltin ); it is approximately the same duration between input signal time (t input ) and the output signal time (t output ). fo fo fo fo f o f o fo
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 15 fan7389 ? 3-phase half-bridge gate driver ic figure 44. input noise filter definition 3.2. short-pulsed input noise rejection method the input filter circuitry provides protection against short-pulsed input signals (hinx, linx, and en) on the input signal lines by applied noise signal. if the input signal duration is less than input filter time (t fltin ), the output does not change states. example a and b of the figure 45 show the input and output waveforms with short-pulsed noise spikes with a duration less than input filter time; the output does not change states. figure 45. noise rejecting input filter definition figure 46 shows the characteristics of the input filters while receiving narrow on and off pulses. if input signal pulse duration, pw in , is less than input filter time, t fltin ; the output pulse, pw out , is zero. the input signal is rejected by input filter. once the input signal pulse duration, pw in , exceeds input filter time, t fltin , the output pulse durations, pw out , matches the input pulse durations, pw in . fan7389 input filter time, t fltin, is about 250 ns for the high- and low-side outputs. figure 46. input filter characteristic of narrow on
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 16 fan7389 ? 3-phase half-bridge gate driver ic package dimensions figure 47. 28-lead small outline integrated circuit (28-wide body soic) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan7389 ? rev. 1.0.2 17 fan7389 ? 3-phase half-bridge gate driver ic

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