brief bcm5482s ? dual-port 10/100/1000base-t gigabit ethernet transceiver bcm5482s system diagram ? dual-port integrated 10base-t/100base-tx/1000base-t gigabit ethernet transceiver rgmii, sgmii, and serdes mac interface options sgmii to sgmii support for sfp modules fully compliant with ieee 802.3?, ieee 802.3u, ieee 802.3ab standard, and ieee 802.3z 0.13-micron cmos?low power and cost supports copper or fiber in rgmii mode low power 725 mw per port advanced power management trace-matched output impedance line-side and mac-side loopback low emi emissions cablechecker? diagnostics cable plant analyzer function detects cable plant impairments ethernet@wirespeed automatic mdi/mdix crossover at all speeds robust cable-sourced electrostatic discharge (cesd) tolerance support for jumbo packets up to 10 kb ieee 1149.1 (jtag) boundary scan 121-pin bga package compact solution for high density uplink applications, enabling 10/100/1000base-t and 1000base-x/100base-fx uplinks 1000base-x and 100base-fx support from same line side pins enables direct interface to sfp modules provides compatibility with ieee standard devices operating at 10, 100, and 1000 mbps at half-duplex and full-duplex. clock timing can be adjusted to eliminate board trace delays required by the rgmii specification. lowers system bom cost and simplifies system design eases system level debugging enables use of low-cost magnetics cable diagnostic function charac terizes cable plant condition and immediately indicates cabling issues. prevents erroneous equipment return due to bad cable plants prevents manufacturing fallout due to bad cable plants allows immediate uptime at reduced speeds (100base-tx or 10base-t) over 3 kv of cesd tolerance prevents equipment damage and return. operates with larger packets for wider range of packet protocol support and improved efficiency ease of manufacturing with jtag support, simplified power supply, and multiple mac interfaces features summary of benefits bcm5482s strata or xgs switch sfp module sfp connector 1000 s e - b a x o r100ba se-f x o pt i cal module transformer rj-45
overview ? phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue, p.o. box 57013 irvine, california 92617 ? 2007 by broadcom corporation. all rights reserved. 5482s-pb00-r 05/02/07 broadcom ? , the pulse logo, quadsquad ?, and connecting everything ? are trademarks of broadcom corporation and/or its subsidiaries in the united st ates and certain other countries. all other trademarks mentioned are the property of their respective owners. bcm5482s block diagram a member of broadcom?s third generation of gigabit ethernet phys, the bcm5482s consists of two complete 10/100/1000base-t gigabit ethernet transceivers integrated on a single monolithic cmos chip. the bcm5482s is optimized for low power and small footprint size to reduce design complexity for high-density uplink applications. for high-density uplink applications, the single package offers a compelling advantage over two single devices for gigabit uplinks. the bcm5482s dsp-based architecture and advanced power management techniques combine to achieve robust and low-power operation over existing category 5 twisted-pair wiring. the bcm5482s architecture not only meets the requirements of ieee 802.3, ieee 802.3u, and ieee 802.3ab, but also maintains the industry?s highest level of margin over ieee requirements for echo, near-end crosstalk (next), and far-end crosstalk (fext). with the industry's lowest power at 725 mw per port, the bcm5482s assists in reducing the power distribution requirements of ip phone systems. in addition, the bcm5482s has extremely low emi emissions, which reduces the design constraints required to meet emi radiation specifications. the bcm5482s supports the rgmii, sgmii, and serdes mac interfaces. the rgmii, sgmii, and serial serdes interfaces are reduced-pin-count (12, 6, and 4, respectively, versus 25) versions of the gmii. the rgmii clock timing can be adjusted to eliminate the board trace delays required by the rgmii specification. these reduced-pin-count interfaces simplify design and lower system cost by reducing the number of layers required for signal routing. in addition, these interfaces allow fewer pins at the mac/switch, which reduces the mac/switch cost by enabling smaller die sizes than would be possible with full gmii. in most switch designs, a few ports are targeted as uplink ports to connect to servers, switches, or remote links. these connections can be 10/100/ 1000base-t, 1000base-sx/lx, or 100base-fx. in order to accommodate these various interfaces, one or more sfp slots can be designed into the switch and the user can plug an sfp module into the slot that meets their specific requirement. the bcm5482s addresses the specific problem of supporting multispeed sfp uplinks. 1000base-x sfp modules require a serdes interface to the sfp module. 10/100/1000base-t and 100base-fx require an sgmii interface in order to rate adapt to the lower speeds (less than 1 gigabit). the bcm5482s can switch between any of these interfaces, depending on the sfp module installed. each bcm5482s port is fully independent and has individual interface, control, and status registers, and incorporates a number of advanced features. this includes identifying physical wiring defects that the bcm5482s cannot automatically correct and channel conditions such as excessive cable length and return loss, crosstalk, echo, and noise. broadcom?s cable analyzer software can be used with the device to provide remote management of the cable and a first level of diagnostics and fault isolation. the bcm5482s also has esd tolerance that is well above typical industry standards. this prevents esd damage not only during manufacturing, but also during cesd events in the field. the cesd is an esd event that occurs when an electrically charged network cable is plugged into a network port. this issue is becoming more prevalent with contemporary cable installations. the bcm5482s can tolerate over 3 kv of cesd. trd2 [3:0] trd1 [3:0] xtali xtalo rdac txd {2:1} [3:0] tx_en {2:1} gtx_clk {2:1} sgin_p1 sgout_p1 led_p1[1]/anen (led1) led_p1[3] (led3) led_p1[4] (led4) led_p2[4] (led4) led_p2[1]/spd0 (led1) led_p2[2]/intr/f1000/sd (led2) rx_dv {2:1} rxd1[3:0] mdio_p1 mdio_p2 mdc_p1 mdc_p2 drvsel [1:0] intfsel [1:0] tx dac baseline wander correction pga adc auto- negotiation clock generator bias generator symbol encoder echo canceller ffe xtalk canceller x3 dfe & trellis decoder led drivers sgmii/serdes symbol decoder/ aligner mii registers mii management control timing & phase recovery timing & phase recovery voltage regulator bcm5482s sgclk_p1 sgin_p2 sgout_p2 sgclk_p2 s_sgin_p1 s_sgout_p1 s_sgin_p2 s_sgout_p2 rxc {2:1} rxd2[3:0] led_p1[2]/intr/fdx/sd (led2) led_p2[3] (led3) reg_sup {2:1} reg_out {2:1}
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