sh69p24 evb application note for sh69p24 evb ver1.0 1/8 sh69p24 evb the sh69p24 evb is used to evaluate the sh69p24 chip's functi on for the development of application program. it contains of a sh69v24 chip to evaluate the functions of sh69p24 includi ng lcd, led, keyscan and alarm.the following figure shows the placement diagram of sh69p24 evb. j2 j1 jp4 vcc gnd jp1 u2 u3 74hc273 74hc273 5v 3v ext u1 roml romh with ice stand alone stop halt s1 j3 1 idd test jp2 jp3 lvr power j4 stkovf sh69v24 1 on 234 http://www..net/ datasheet pdf - http://www..net/
sh69p24 evb 2/8 there are two configurations of sh69p24 evb in a pplication development: ice mode and stand-alone mode. in the ice mode, the ice (motherboard) is connected to the evb by the ice interface. usb port pc usb rice power evaluation board application board lpt port pc ide66 emulator evaluation board application board power (a) ice mode in the standalone mode, the sh69p24 evb is no longer connected to the motherboard, but the flash (or eprom) must be inserted to the socket that stored the application program. evaluation board application board dc 5v (b) stand-alone mode http://www..net/ datasheet pdf - http://www..net/
sh69p24 evb 3/8 the process of your program?s evaluation on sh69p24 evb user can use sino wealth ide66 integrated development environment (ide) to emulate the program and produce the obj file. ide66 ide is a real-time in-circuit emulator program. it provides real-time and transparent emulation support for the sh6x series 4-bit microcontroller. an d integrate assembler can create binar y (*.obj) file and the other files. use flash (or eprom) in standalone mode ide66 ide is built-in with an object file depart function. the co mmand ?split object file? can separate the one 16 bits object file into two 8 bits files, which contain the high and low bytes respectively. write the high/low byte obj file to flash (or eprom) and insert them to evb (romh and roml). then, user can evaluate the program in standalone mode. http://www..net/ datasheet pdf - http://www..net/
sh69p24 evb 4/8 sh69p24 evb interface connector: (top view from evb): user?s interface connector: j4 (top view from evb) j4 pe0 pd1 pd0 pe1 pd2 pd3 pc2 pc1 pc3 pb2 pb3 gnd pa0 pa1 pc0 pb1 pb0 vdd_ext pe3 pe2 pf0 pf1 pf2 pf3 most important: incorrect power input (the gnd is connected to vcc pin j1, and vcc is connected to gnd pin j2) will hurt or breakdown the ev board permanently. external vcc input for stand alone mode: j1, j2 -the external power input when the evb worked in stand-alone mode. the voltage of vcc must be 5v 5%. interface to test the ev chip operating current jp2 - user can test the ev chip current through jp2 note: in ice mode, the current value is correct only when t he ide66 runs in external cl ock from evb mode. (select the ?external clock from evb? in osc frequency configuration manual.) jumper setting: jp1 ev chip power supply select short at 3v position the power of ev chip is set as internal 3v power source short at 5v position the power of ev chip is set as internal 5v power source short at ext position the ev chip use external power supply that was input from ext pin. jp4 evb ice/stand-alone mode select short at stand-alone position select stand-alone mode. (the system clock is provided by the on board oscillator.) short at with-ice position select with-ice mode. (the system clock is provided by the ice.) jp3 stack overflow select short the stack overflow function in the ice mode will on open the stack overflow function in the ice mode will off http://www..net/ datasheet pdf - http://www..net/
sh69p24 evb 5/8 s1 bit 4 bit 3 bit 2 bit 1 remarks x lvr0 lvr wdt x x x off disable wdt x x x on enable wdt x x off x disable lvr x x on x enable lvr x off x x lvr high level:4v x on x x lvr low level:2.5v diagnostic led: power led: the led will be turned on when the evb is powered. stop led: the led will be turned on when the system is in stop mode. halt led: the led will be turned on when the system is in halt mode. lvr led: the led will be turned on when the vdd is lower than lvr voltage notes: application notes: 1.1 after entering into the ide66 and successfully downloaded the user program, use the f5 key on the pc keyboard to reset the evb before running the program. if abnorm al response occurs, the user must switch off the ice power and quit ide66, then wait fo r a few seconds before restarting. 1.2 when running the ide66 for the first time, the user needs to select the correct mcu type, clock frequency ... then save the settings and restart ide66 again. 1.3 can?t step (f8) or over (f 9) a halt and stop instruction. 1.4 can?t emulate the interrupt func tion in step (f8) operating mode. 1.5 when you want to escape from halt or stop (in ice mode), please press f5 key on the pc keyboard twice. 1.6 the maximum current limit supplied from evb to the tar get is 100ma. when the current in the target is over 100ma, please use external power supply. 1.7 can?t emulate the timer function in step (f8) operating mode. programming notes: 2.1 clear the data ram and init ialize all system registers du ring the initial programming. 2.2 the ?nop? instruction should be added at the begi nning of the program to en sure the ic is stable. 2.3 never use the reserved registers. 2.4 do not execute arithmetic operation with those register s that only have 1, 2 or 3 bits. this kind of operation may not produce the result you expected. http://www..net/ datasheet pdf - http://www..net/
sh69p24 evb 6/8 2.5 to add ?p=sh69p24? and ?romsize=4096? at the beginni ng of a program. if any problem occurs during the compilation of the program, check the dev ice and set if it was set correctly. 2.6 both index register dph and dpm have three bits; so pa y attention to the destination address when using them. 2.7 notes for interrupt: 2.7.1 please make sure that the ie flag is enabled befor e entering into a ?halt? or a ?stop mode. it means that the ?halt? or ?stop? instruction must follow the set ?ie? instruction closely. 2.7.2 after the cpu had responded to an interrupt, irq should be cleared before resetting ie in order to avoid multi-responses. 2.7.3 interrupt enable instruction will be automatically cleared after entering into the interrupt-processing subroutine. if setting ie is too early, it is possible to reenter into the interrupt. so the interrupt enable instruction should be placed at the last 3 instructions of the subroutine. 2.7.4 cpu will not respond to any interrupt during the next two instructions after the interrupt enable flag be set from 0 to 1. 2.7.5 after cpu has responded to an interrupt, ie will be cleared by the hardware. it is recommended to clear the irq at the end of interrupt subroutine. 2.7.6 the stack has eight levels. if an interrupt is enabl ed, there will be only seven levels that can be used. 2.7.7 it is recommended that the last line of program is ?end?. examples: 1> description: cpu can not wakeup after ex ecuting the ?halt? or ?stop? instruction. program: interrupt enable instruction is set outside the interrupt subroutine ?? ?? ldi ie, 0fh ; enable interrupt ldi ie, 0fh ; enable interrupt nop nop nop nop halt halt analysis: after two ?nop? instructions, if an interrupt requ est comes or irq is non-zero during the third instruction cycle, cpu will respond to the interrupt a nd ie will be cleared. then when returning to main program, cpu starts to execute ?halt? or ?stop? and wi ll not be activated, because ie is cleared to zero and all interrupts are disabled. solution: ?halt? or ?stop? are being followed closely by the ?ldi ie, 0fh? 2> description: cpu responds to one interrupt several times. program: interrupt enable instruction is placed outside the interrupt subroutine. l1: ?.. ldi ie, 0fh ; enable interrupts nop nop jump l1 http://www..net/ datasheet pdf - http://www..net/
sh69p24 evb 7/8 analysis: after executing this two ?nop? instructions, and irq is not cleared in time, cpu will respond to the interrupt again when it executes the two instructions followed by ?ldi ie, 0fh?. this will happen again and again. so cpu responds to one interrupt several times. solution: the relative irq flag is cleared in time after responding to the interrupt. 3> description: cpu is running dead in the interrupt-processing program. program: an interrupt subroutine. enterint: ?.. ldi ie, 0fh nop lda stack, 0 rtni analysis: after executing ?ldi ie, 0fh? and the following two instructions, an interrupt request comes or the last relative irq flag is not cleared in time, then cpu will respond to the interrupt again, so the interrupt is nesting again. when the stack exceeds over 8 levels, it will run into a dead loop. solution: make sure that the cpu can quit from interrupt subroutine within two instruction cycles after interrupt is enabled; after the interrupt is responded , the relative irq flag should be cleared before enabling the interrupt. 2.8 notes for timer 2.8.1 when setting the timer counter, write first t0l/t1l, then t0h/t1l 2.8.2 after setting tm0/tm1, t0l/t1l, t0h/t1h, there is no need to rewrite after the timer counts overflow, otherwise it will cause a time error every time. the timer is interrupted by the reload registrar that was set in different time. 2.9 notes for i/o 2.9.1 each i/o port (excluding those open drain output port s) contains pull-high mos controllable by the program. each pull-high mos is controlled by the value of the co rresponding bit in the port pull-high control register (ppcr), independently. when the port is selected as an input port (write 1 to the relevant bit in the port pull-high control register (ppcr) could turn on the pull-high mos and write 0 could turn off the pull-high mos). so the pull-high mos can be turned on and off indivi dually. but when the port is selected as output port, the pull-high mos must be turned off automatica lly, regardless the value of the corresponding bit in the port pull-high control register (ppcr). 2.9.2 when a digital i/o is selected to be an output port, t he reading of the associated port bit actually represents the value of the output data latch, not the status on the pad. only when a digital i/o is selected to be an input port, the reading of the associated port bit represents the status on the corresponding pad. 2.9.3 setting those i/o ports with open drain output type as input will cause leakage curre nt ranging from tens to hundreds micro-ampere. so do not forget to enable the pull-high mos or connect these input ports with external resistors (pull-high or pull- low) to prevent the i/o ?floating?. 2.9.4 the key de-bounce time is recommended to be 50ms. but in the rubber key application, it is best to test rubber key?s de-bounce time. 2.10 refer to the lcd, led programming notes in the sh69p24 data sheet. 2.11 refer to the keyscan programming notes in the sh69p24 data sheet. http://www..net/ datasheet pdf - http://www..net/
sh69p24 evb 8/8 application notes revision history revision no. history date 1.0 original june.2009 http://www..net/ datasheet pdf - http://www..net/
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