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general description the max5290?ax5295 dual, 12-/10-/8-bit, voltage- output digital-to-analog converters (dacs) offer buffered outputs and a 3? maximum settling time at the 12-bit level. the dacs operate from a 2.7v to 3.6v analog supply and a separate 1.8v to 3.6v digital sup- ply. the 20mhz 3-wire serial interface is compatible with spi, qspi, microwire, and digital signal processor (dsp) protocol applications. multiple devices can share a common serial interface in direct access or daisy-chained configuration. the max5290?ax5295 provide two multifunctional, user-programmable, digital i/o ports. the externally selectable power-up states of the dac outputs are either zero scale, midscale, or full scale. software-selectable fast and slow settling modes decrease settling time in fast mode, or reduce supply current in slow mode. the max5290/max5291 are 12-bit dacs, the max5292/ max5293 are 10-bit dacs, and the max5294/max5295 are 8-bit dacs. the max5290/ max5292/max5294 pro- vide unity-gain-configured output buffers, while the max5291/max5293/max5295 provide force-sense-con- figured output buffers. the max5290?max5295 are specified over the extended -40? to +85? temperature range, and are available in space-saving 4mm x 4mm, 16-pin thin qfn and 6.5mm x 5mm, 14-pin and 16-pin tssop packages. applications portable instrumentation automatic test equipment (ate) digital offset and gain adjustment automatic tuning programmable voltage and current sources programmable attenuators industrial process controls motion control microprocessor (?)-controlled systems power amplifier control fast parallel-dac to serial-dac upgrades features dual, 12-/10-/8-bit serial dacs in 4mm x 4mm thin qfn and tssop packages 3? (max) 12-bit settling time to 1/2 lsb integral nonlinearity 1 lsb (max) max5290/max5291 a-grade (12-bit) 1 lsb (max) max5292/max5293 (10-bit) 1/2 lsb (max) max5294/max5295 (8-bit) guaranteed monotonic, ? lsb (max) dnl two user-programmable digital i/o ports single +2.7v to +3.6v analog supply +1.8v to av dd digital supply 20mhz 3-wire spi-/qspi-/microwire- and dsp-compatible serial interface glitch-free outputs power up to zero scale, midscale or full scale unity-gain- or force-sense-configured output buffers max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ________________________________________________________________ maxim integrated products 1 ordering information 19-3005; rev 0; 11/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * future product?ontact factory for availability. specifications are preliminary. ** ep = exposed paddle. selector guide and pin configurations appear at end of data sheet. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. part temp range pin-package max5290 aeud* -40 c to +85 c 14 tssop max5290beud -40 c to +85 c 14 tssop max5290aete* -40 c to +85 c 16 thin qfn-ep** max5290bete* -40 c to +85 c 16 thin qfn-ep** max5291 aeue* -40 c to +85 c 16 tssop max5291beue -40 c to +85 c 16 tssop max5291aete* -40 c to +85 c 16 thin qfn-ep** max5291bete* -40 c to +85 c 16 thin qfn-ep** max5292 eud -40 c to +85 c 14 tssop max5292ete* -40 c to +85 c 16 thin qfn-ep** max5293 eue -40 c to +85 c 16 tssop max5293ete* -40 c to +85 c 16 thin qfn-ep** max5294 eud -40 c to +85 c 14 tssop max5294ete* -40 c to +85 c 16 thin qfn-ep** max5295 eue -40 c to +85 c 16 tssop max5295ete* -40 c to +85 c 16 thin qfn-ep**
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = 2.7v to 3.6v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v, r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to dv dd ........................................................................6v agnd to dgnd ..................................................................0.3v av dd to agnd, dgnd.............................................-0.3v to +6v dv dd to agnd, dgnd ............................................-0.3v to +6v fb_, out_, ref to agnd ........-0.3v to the lower of (av dd + 0.3v) or +6v sclk, din, cs , pu, dsp to dgnd .......-0.3v to the lower of (dv dd + 0.3v) or +6v upio1, upio2 to dgnd ...............-0.3v to the lower of (dv dd + 0.3v) or +6v maximum current into any pin .........................................50ma continuous power dissipation (t a = +70 c) 14-pin tssop (derate 9.1mw/ c above +70 c) .........727mw 16-pin tssop (derate 9.4mw/ c above +70 c) .........755mw 16-pin thin qfn (derate 16.9mw/ c above +70 c) .1349mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c maximum junction temperature .....................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units static accuracy max5290/max5291 12 max5292/max5293 10 resolution n max5294/max5295 8 bits max5290a/max5291a (12-bit) 1 max5290b/max5291b (12-bit) 2 4 max5292/max5293 (10-bit) 0.5 1 integral nonlinearity inl v ref = 2.5v at av dd = 2.7v (note 2) max5294/max5295 (8-bit) 0.125 0.5 lsb differential nonlinearity dnl guaranteed monotonic (note 2) 1 lsb max5290a/max5291a (12-bit), decimal code = 40 5 max5290b/max5291b (12-bit), decimal code = 82 5 25 max5292/max5293 (10-bit), decimal code = 21 5 25 offset error v os max5294/max5295 (8-bit), decimal code = 5 5 25 mv offset-error drift 5 ppm of fs/ c max5290a/max5291a (12-bit) 4 max5290b/max5291b (12-bit) 10 20 max5292/max5293 (10-bit) 3 5 gain error ge full-scale output max5294/max5295 (8-bit) 0.5 2 lsb gain-error drift 1 ppm of fs/ c
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = 2.7v to 3.6v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v, r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units power-supply rejection ratio psrr full-scale output, av dd = 2.7v to 3.6v 200 v/v reference input reference input range v ref 0.25 av dd v reference input resistance r ref normal operation (no code dependence) 145 200 k ? reference leakage current i ref shutdown mode 0.5 1 a dac output characteristics unity gain 85 slow mode, full scale force sense 67 unity gain 140 output voltage noise fast mode, full scale force sense 110 v rms unity-gain output 0 av dd output voltage range (note 4) force-sense output 0 av dd / 2 v dc output impedance 38 ? short-circuit current av dd = 3v, out_ to agnd, full scale, fast mode 45 ma power-up time from dv dd applied, interface is functional 30 60 s wake-up time coming out of shutdown, outputs settled 40 s output out_ and fb_ open-circuit leakage current programmed in shutdown mode, force-sense outputs only 0.01 a digital outputs (upio_) output high voltage v oh i source = 2ma dv dd - 0.5 v output low voltage v ol i sink = 2ma 0.4 v digital inputs (sclk, cs , din, dsp , upio_) 2.7v dv dd 3.6v 2.4 input high voltage v ih dv dd < 2.7v 0.7 x dv dd v 2.7v dv dd 3.6v 0.6 input low voltage v il dv dd < 2.7v 0.2 v input leakage current i in 0.1 1 a input capacitance c in 10 pf
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = 2.7v to 3.6v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v, r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units pu input input high voltage v ih-pu dv dd - 200mv v input low voltage v il-pu 200 mv input leakage current i in-pu pu still considered floating when connected to a tri-state bus 200 na dynamic performance fast mode 3.6 voltage-output slew rate sr slow mode 1.6 v/s m ax 5290/m ax 5291 fr om cod e 322 to cod e 4095 to 1/2 ls b 23 m ax 5292/m ax 5293 fr om cod e 82 to cod e 1023 to 1/2 ls b 1.5 3 fast mode max5294/max5295 from code 21 to code 255 to 1/2 lsb 12 m ax 5290/m ax 5291 fr om cod e 322 to cod e 4095 to 1/2 ls b 36 max5292/max5293 from code 82 to code 1023 to 1/2 lsb 2.5 6 voltage-output settling time (note 5) slow mode max5294/max5295 from code 21 to code 255 to 1/2 lsb 24 s fb_ input voltage 0v ref / 2 v fb_ input current 0.1 a unity gain 200 reference -3db bandwidth (note 6) force sense 150 khz digital feedthrough cs = dv dd , code = zero scale, any digital input from 0 to dv dd and dv dd to 0, f = 100khz 0.1 nv-s digital-to-analog glitch impulse major carry transition 2 nv-s dac-to-dac crosstalk (note 3) 15 nv-s
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = 2.7v to 3.6v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v, r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage range av dd 2.7 3.6 v digital supply voltage range dv dd 1.8 av dd v unity gain 0.55 0.8 a slow mode, all digital inputs at dgnd or dv dd , no load, v ref = 2.5v force sense 0.9 1.2 ma unity gain 0.85 2 operating supply current i avdd + i dvdd fast mode, all digital inputs at dgnd or dv dd , no load, v ref = 2.5v force sense 1.2 2 ma shutdown supply current i av d d ( s h d n ) + i d v d d ( s h d n ) no clocks, all digital inputs at dgnd or dv dd , all dacs in shutdown mode 2.5 a timing characteristics?sp mode disabled (3v, 3.3v logic) (figure 1) (dv dd = 2.7v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 2.7v < dv dd < 3.6v 20 mhz sclk pulse-width high t ch (note 7) 20 ns sclk pulse-width low t cl (note 7) 20 ns cs fall to sclk rise setup time t css 10 ns sclk rise to cs rise hold time t csh 5ns sclk rise to cs fall setup time t cs0 10 ns din to sclk rise setup time t ds 12 ns din to sclk rise hold time t dh 5ns sclk rise to doutdc1 valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 mode 30 ns sclk fall to dout_ valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 or doutrb mode 30 ns cs rise to sclk rise hold time t cs1 microwire and spi modes 0 and 3 10 ns cs pulse-width high t csw 45 ns
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 6 _______________________________________________________________________________________ timing characteristics dsp mode disabled (3v, 3.3v logic) (figure 1) (continued) (dv dd = 2.7v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units upio timing characteristics dout tri-state time when exiting doutdc0, doutdc1, or doutrb upio modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 100 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 20 ns doutrb tri-state enable time from 8th sclk rise t zen c l = 20pf, from 8th rising edge of sclk to upio_ driven out of tri-state 20 ns ldac pulse-width low t ldl figure 5 20 ns ldac effective delay t lds figure 6 100 ns clr , mid , set pulse-width low t cms figure 5 20 ns gpo output settling time t gp figure 6 100 ns gpo output high-impedance time t gpz 100 ns timing characteristics dsp mode disabled (1.8v logic) (figure 1) (dv dd = 1.8v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 1.8v < dv dd < 3.6v 10 mhz sclk pulse-width high t ch (note 7) 40 ns sclk pulse-width low t cl (note 7) 40 ns cs fall to sclk rise setup time t css 20 ns sclk rise to cs rise hold time t csh 0ns sclk rise to cs fall setup time t cs0 10 ns din to sclk rise setup time t ds 20 ns din to sclk rise hold time t dh 5ns sclk rise to doutdc1 valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 mode 60 ns sclk fall to dout_ valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 or doutrb mode 60 ns cs rise to sclk rise hold time t cs1 microwire and spi modes 0 and 3 20 ns cs pulse-width high t csw 90 ns
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 7 timing characteristics dsp mode disabled (1.8v logic) (figure 1) (continued) (dv dd = 1.8v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units upio_ timing characteristics dout tri-state time when exiting doutdc0, doutdc1, or doutrb upio modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 200 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 40 ns doutrb tri-state enable time from 8th sclk rise t zen c l = 20pf, from 8th rising edge of sclk to upio_ driven out of tri-state 40 ns ldac pulse-width low t ldl figure 5 40 ns ldac effective delay t lds figure 6 200 ns clr , mid , set pulse-width low t cms figure 5 40 ns gpo output settling time t gp figure 6 200 ns gpo output high-impedance time t gpz 200 ns timing characteristics dsp mode enabled (3v, 3.3v logic) (figure 2) (dv dd = 2.7v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 2.7v < dv dd < 3.6v 20 mhz sclk pulse-width high t ch (note 7) 20 ns sclk pulse-width low t cl (note 7) 20 ns cs fall to sclk fall setup time t css 10 ns dsp fall to sclk fall setup time t dss 10 ns sclk fall to cs rise hold time t csh 5ns sclk fall to cs fall delay t cs0 10 ns sclk fall to dsp fall delay t ds0 10 ns din to sclk fall setup time t ds 12 ns din to sclk fall hold time t dh 5ns sclk rise to dout_ valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 or doutrb mode 30 ns sclk fall to doutdc0 valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 mode 30 ns cs rise to sclk fall hold time t cs1 microwire and spi modes 0 and 3 10 ns cs pulse-width high t csw 45 ns dsp pulse-width high t dsw 20 ns dsp pulse-width low t dspwl (note 8) 20 ns
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 8 _______________________________________________________________________________________ timing characteristics dsp mode enabled (3v, 3.3v logic) (figure 2) (continued) (dv dd = 2.7v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units upio_ timing characteristics dout tri-state time when exiting doutdc0, doutdc1, or doutrb upio modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 100 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 20 ns doutrb tri-state enable time from 8th sclk fall t zen c l = 20pf, from 8th falling edge of sclk to upio_ driven out of tri-state 20 ns ldac pulse-width low t ldl figure 5 20 ns ldac effective delay t lds figure 6 100 ns clr , mid , set pulse-width low t cms figure 5 20 ns gpo output settling time t gp figure 6 100 ns gpo output high-impedance time t gpz 100 ns timing characteristics dsp mode enabled (1.8v logic) (figure 2) (dv dd = 1.8v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 1.8v < dv dd < 3.6v 10 mhz sclk pulse-width high t ch (note 7) 40 ns sclk pulse-width low t cl (note 7) 40 ns cs fall to sclk fall setup time t css 20 ns dsp fall to sclk fall setup time t dss 20 ns sclk fall to cs rise hold time t csh 0ns sclk fall to cs fall delay t cs0 10 ns sclk fall to dsp fall delay t ds0 15 ns din to sclk fall setup time t ds 20 ns din to sclk fall hold time t dh 5ns sclk rise to dout_ valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 or doutrb mode 60 ns sclk fall to doutdc0 valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 mode 60 ns cs rise to sclk fall hold time t cs1 microwire and spi modes 0 and 3 20 ns cs pulse-width high t csw 90 ns dsp pulse-width high t dsw 40 ns dsp pulse-width low t dspwl (note 8) 40 ns
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 9 timing characteristics dsp mode enabled (1.8v logic) (figure 2) (continued) (dv dd = 1.8v to 3.6v, dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units upio_ timing characteristics dout tri-state time when exiting doutdc0, doutdc1, or doutrb upio_ modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 200 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 40 ns doutrb tri-state enable time from 8th sclk fall t zen c l = 20pf, from 8th falling edge of sclk to upio_ driven out of tri-state 40 ns ldac pulse-width low t ldl figure 5 40 ns ldac effective delay t lds figure 6 200 ns clr , mid , set pulse-width low t cms figure 5 40 ns gpo output settling time t gp figure 6 200 ns gpo output high-impedance time t gpz 200 ns note 1: for the force-sense versions, fb_ is connected to its respective out_. v out (max) = v ref / 2, unless otherwise noted. note 2: linearity guaranteed from decimal code 82 to 4095 for the max5290b/max5291b (12-bit, b-grade), code 21 to 1023 for the max5292/max5293 (10-bit), and code 5 to 255 for the max5294/max5295 (8-bit). note 3: dac-to-dac crosstalk is measured as follows: outputs of daca and dacb are set to full scale and the output of dacb is measured. while keeping dacb unchanged, the output of daca is transitioned to zero scale and the ? v out of dacb is measured. the procedure is repeated with daca and dacb interchanged. dac-to-dac crosstalk is the maximum ? v out measured. note 4: represents the functional range. the linearity is guaranteed at v ref = 2.5v. see the typical operating characteristics sec- tion for linearity at other voltages. note 5: guaranteed by design. note 6: the reference -3db bandwidth is measured with a 0.1v p-p sine wave on v ref and with the input code at full scale. note 7: in some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol- lowing edge. in the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7v) or 50ns (1.8v). note 8: the falling edge of dsp starts a dsp-type bus cycle, provided that cs is also active low to select the device. dsp active low and cs active low must overlap by a minimum of 10ns (2.7v) or 20ns (1.8v). cs can be permanently low in this mode of operation.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 10 ______________________________________________________________________________________ integral nonlinearity vs. digital input code (12-bit) max5290 toc01 digital input code inl (lsb) 3072 2048 1024 -3 -2 -1 0 1 2 3 4 -4 0 4096 unity gain b-grade integral nonlinearity vs. digital input code (10-bit) max5290 toc02 digital input code inl (lsb) 768 512 256 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 1024 unity gain integral nonlinearity vs. digital input code (8-bit) max5290 toc03 digital input code inl (lsb) 192 128 64 -0.25 0 0.25 0.50 -0.50 0 256 unity gain differential nonlinearity vs. digital input code (12-bit) max5290 toc04 digital input code dnl (lsb) 3072 2048 1024 -0.1 0 0.1 0.2 -0.2 0 4096 unity gain b-grade differential nonlinearity vs. digital input code (10-bit) max5290 toc05 digital input code dnl (lsb) 768 512 256 -0.025 0 0.025 0.050 -0.050 0 1024 unity gain differential nonlinearity vs. digital input code (8-bit) max5290 toc06 digital input code dnl (lsb) 192 128 64 -0.01 0 0.01 0.02 -0.02 0 256 unity gain typical operating characteristics (av dd = dv dd = 3v, v ref = 2.5v, r l = 10k ? , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.)
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 11 differential nonlinearity vs. temperature (12-bit) max5290 toc08 temperature ( c) dnl (lsb) 60 35 10 -15 -0.1 0 0.1 0.2 -0.2 -40 85 unity gain b-grade offset error vs. temperature max5290 toc09 temperature ( c) offset error (lsb) 60 35 10 -15 -8 -6 -4 -2 0 -10 -40 85 force sense unity gain unity gain: 1 lsb = 0.6mv force sense: 1 lsb = 0.3mv gain error vs. temperature max5290 toc10 temperature ( c) gain error (lsb) 60 35 10 -15 -8 -6 -4 -2 0 -10 -40 85 force sense unity gain unity gain: 1 lsb = 0.6mv force sense: 1 lsb = 0.3mv integral nonlinearity vs. temperature (12-bit) max5290 toc07 temperature ( c) inl (lsb) 60 35 10 -15 -2 0 2 4 -4 -40 85 unity gain b-grade typical operating characteristics (continued) (av dd = dv dd = 3v, v ref = 2.5v, r l = 10k ? , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.) reference input bandwidth max5290 toc11 frequency (hz) gain (db) 1m 100k 10k 1k -25 -20 -15 -10 -5 0 5 -30 0 10m v ref = 0.1v p-p at 2.5v dc
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 12 ______________________________________________________________________________________ pin description pin max5290 max5292 max5294 max5291 max5293 max5295 thin qfn tssop thin qfn tssop name function 1213 dsp clock enable. connect dsp to dv dd at power-up to transfer data on the rising edge of sclk. connect dsp to dgnd at power-up to transfer data on the falling edge of sclk. 2 3 2 4 din serial data input 3435 cs active-low chip-select input 4 5 4 6 sclk serial clock input 5657dv dd digital supply 6 7 6 8 dgnd digital ground 7 8 7 9 agnd analog ground 89810av dd analog supply 9 10 9 11 outb dacb output 10 12 fbb feedback for dacb output buffer 10 11 11 13 ref reference input 12 14 fba feedback for daca output buffer 11, 13 n.c. no connection. not internally connected. 12 12 13 15 outa daca output 14 13 14 16 pu power-up state select input. connect pu to dv dd to set outa and outb to full scale upon power-up. connect pu to dgnd to set outa and outb to zero upon power-up. leave pu floating to set outa and outb to midscale upon power-up. 15 14 15 1 upio2 user-programmable input/output 2 16 1 16 2 upio1 user-programmable input/output 1 ep exposed paddle (qfn only). not internally connected. do not connect to circuitry.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 13 functional diagrams max5290 max5292 max5294 dout register 16-bit shift register cs sclk din dsp serial interface control mux av dd upio1 upio2 ref pu upio1 and upio2 logic power-down logic and register decode control input register dac register dac a outa input register dac b outb dac register dv dd agnd dgnd
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 14 ______________________________________________________________________________________ functional diagrams (continued) max5291 max5293 max5295 dout register 16-bit shift register cs sclk din dsp serial interface control mux av dd upio1 upio2 ref pu upio1 and upio2 logic power-down logic and register decode control input register dac register dac a outa fba input register dac b outb fbb dac register dv dd agnd dgnd
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 15 detailed description the max5290 max5295 dual, 12-/10-/8-bit, voltage- output digital-to-analog converters (dacs) offer buffered outputs and a 3s maximum settling time at the 12-bit level. the dacs operate from a single 2.7v to 3.6v analog supply and a separate 1.8v to av dd digi- tal supply. the max5290 max5295 include an input register and dac register for each channel and a 16-bit data-in/data-out shift register. the 3-wire serial interface is compatible with spi, qspi, microwire, and dsp applications. the max5290 max5295 pro- vide two user-programmable digital i/o ports, which are programmed through the serial interface. the exter- nally selectable power-up states of the dac outputs are either zero scale, midscale, or full scale. reference input the reference input, ref, accepts both ac and dc val- ues with a voltage range extending from 0.25v to av dd . the voltage at ref (v ref ) sets the full-scale out- put of the dacs. determine the output voltage using the following equation: unity-gain versions: v out_ = (v ref x code) / 2 n force-sense versions (fb_ connected to out_): v out = 0.5 x (v ref x code) / 2 n where code is the numeric value of the dac s binary input code and n is the bits of resolution. for the max5290/max5291, n = 12 and code ranges from 0 to 4095. for the max5292/max5293, n = 10 and code ranges from 0 to 1023. for the max5294/ max5295, n = 8 and code ranges from 0 to 255. output buffers the daca and dacb output-buffer amplifiers of the max5290 max5295 are unity-gain stable with rail-to- rail output voltage swings and a typical slew rate of 5.7v/s. the max5290/max5292/max5294 provide unity-gain outputs, while the max5291/max5293/ max5295 provide force-sense outputs. for the max5291/max5293/max5295, access to the output amplifier s inverting input provides flexibility in output gain setting and signal conditioning (see the applications information section). the max5290 max5295 offer fast and slow-settling time modes. in the fast mode, the settling time is 3s (max), and the supply current is 2ma (max). in the slow mode, the settling time is 6s (max), and the supply cur- rent drops to 0.8ma (max). see the digital interface sec- tion for settling-time mode programming details. use the serial interface to set the shutdown output impedance of the amplifiers to 1k ? or 100k ? for the max5290/max5292/max5294 and 1k ? or high imped- ance for the max5291/max5293/max5295. the dac outputs can drive a 2k ? (typ) load and are stable with up to 500pf (typ) of capacitive load. power-on reset at power-up, all dac outputs power up to full scale, midscale, or zero scale, depending on the configuration of the pu input. connect pu to dv dd to set out_ to full scale upon power-up. connect pu to dgnd to set out_ to zero scale upon power-up. leave pu floating to set out_ to midscale. digital interface the max5290 max5295 use a 3-wire serial interface that is compatible with spi, qspi, microwire, and dsps (figures 1 and 2). connect dsp to dv dd before power-up to clock data in on the rising edge of sclk. connect dsp to dgnd before power-up to clock data in on the falling edge of sclk. after power-up, the device enters dsp frame sync mode on the first rising edge of dsp . refer to the programmer? handbook for details. each max5290 max5295 includes a 16-bit input shift register. the data is loaded into the input shift register through the serial interface. the 16 bits can be sent in two serial 8-bit packets or one 16-bit word ( cs must remain low until all 16 bits are transferred). the data is loaded msb first. for the max5290/max5291, the 16 bits consist of 4 control bits (c3 c0) and 12 data bits (d11 d0) (see table 1). for the 10-bit max5292/ max5293 devices, d11 d2 are the data bits and d1 and d0 are sub-bits. for the 8-bit max5294/ max5295 devices, d11 d4 are the data bits and d3 d0 are sub-bits. set all sub-bits to zero for optimum performance. each dac channel includes two registers: an input reg- ister and the dac register. at power-up, the dac out- put is set according to the state of pu. the dacs are double-buffered, which allows any of the following for each channel: loading the input register without updating the dac register loading the dac register without updating the input register updating the dac register from the input register updating the input and dac registers simultaneously rail-to-rail is a registered trademark of nippon motorola, ltd.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 16 ______________________________________________________________________________________ table 1. serial write data format msb 16 bits of serial data lsb control bits data bits c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 figure 1. serial-interface timing diagram (dsp mode disabled) figure 2. serial-interface timing diagram (dsp mode enabled) sclk din cs doutdc1* doutdc0 or doutrb* *upio1/upio2 configured as doutdc_ (daisy-chain data output, mode 0 or 1) or doutrb (read-back data output). see the data output section for details. t ch t ds t cs0 t dh t csh t do1 t do2 t cl c2 c3 c1 d0 t csw t cs1 dout valid dout valid t css sclk din cs doutdc0* doutdc1 or doutrb* dsp *upio1/upio2 configured as doutdc_ (daisy-chain data output, mode 0 or 1) or doutrb (read-back data output). see the data output section for details. t cl t ds t css t dsw t dspwl t d02 t d01 t dh t cs0 t ch c3 c2 c1 d0 t csh t csw t dss t cs1 t ds0 dout valid dout valid
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 17 sclk din c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 din sclk dv dd command takes effect here only if sclk count = n ? 16 command takes effect here only if sclk count = n ? 16 microwire or spi (cpol = 0, cpha = 0) 8-bit control data or 12-bit dac data write: cs must remain low between bytes on a 16-bit write operation spi (cpol = 1, cpha = 1) 8-bit control data or 12-bit dac data write: cs must remain low between bytes on a 16-bit write operation din sclk cs cs max5290 max5295 v dd v dd microwire sk so i/o sclk din dv dd max5290 max5295 v dd v dd spi or qspi sck mosi ss or i/o cs dsp dsp cs c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sclk din c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 din sclk dgnd command takes effect here only if sclk count = n ? 16 command takes effect here only if sclk count = n ? 16 dsp or spi (cpol = 0, cpha = 0) 8-bit control data or 12-bit dac data write: dsp or spi (cpol = 1, cpha = 0) 8-bit control data or 12-bit dac data write: din sclk cs cs max5290 max5295 v ss dsp tclk, sclk, or clkx dt or dx tfs or fsx sclk din dgnd max5290 max5295 v ss spi or qspi sck mosi ss or i/o cs dsp dsp cs cs must remain low between bytes on a 16-bit write operation cs must remain low between bytes on a 16-bit write operation figure 3. microwire and spi (cpol = 0, cpha = 0 or cpol = 1, cpha = 1) dac writes figure 4. dsp and spi (cpol = 0, cpha = 1 or cpol = 1, cpha = 0) dac writes serial-interface programming commands tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the max5290 max5295. table 2a shows the basic dac programming com- mands, table 2b gives the advanced-feature program- ming commands, and table 2c provides the 24-bit read commands. figures 3 and 4 illustrate the serial- interface diagrams for read and write operations. loading input and dac registers the max5290 max5295 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit dac register for each channel (see the functional diagrams ). tables 3, 4, and 5 highlight a few of the com- mands for the loading of the input and dac registers. see table 2a for all dac programming commands.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 18 ______________________________________________________________________________________ control bits data bits data c3 c2 c1 c0 d1 d1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function loading input and dac registers a and b din 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load input register a from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0 0 0 1 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dac register a from shift register; input registers are unchanged. dac outputs are updated.* din 0 0 1 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load input register a and dac register a from shift register. dac outputs are updated.* din 0 0 1 1 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load input register b; dac registers are unchanged. dac outputs are unchanged.* din 0 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dac register b from shift register; input registers are unchanged. dac outputs are updated.* din 0 1 0 1 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load input register b and dac register b from shift register. dac outputs are updated.* din 0 1 1 0 x x x x x x x x x x x x command is ignored. din 0 1 1 1 x x x x x x x x x x x x command is ignored. din 1 0 0 0 x x x x x x x x x x x x command is ignored. din 1 0 0 1 x x x x x x x x x x x x command is ignored. din 1 0 1 0 x x x x x x x x x x x x command is ignored. din 1 0 1 1 x x x x x x x x x x x x command is ignored. din 1 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load all input registers from the shift register; all dac registers are unchanged. all dac outputs are unchanged.* din 1 1 0 1 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load all input and dac registers from shift register. dac outputs are updated.* table 2a. dac programming commands x = don? care. * for the max5292/max5293 (10-bit version), d11?2 are the significant bits and d1 and d0 are sub-bits. for the max5294/max5295 ( 8-bit version), d11?4 are the significant bits and d3?0 are sub-bits. set all sub-bits to zero during the write commands.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 19 control bits data bits data c3 c2 c1 c0 d1 d1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function select bits din 111000xx x x x x x x mb ma load dac register a from input register a when ma is 1. dac register a is unchanged if ma is 0. load dac register b from input register b when mb is 1. dac register b is unchanged if mb is 0. shutdown-mode bits din 1 1 1 0 0 1 0 x x x x x pdb1 pdb0 pda1 pda0 write daca and dacb shutdown mode bits. see table 8. din1110011xxxxxxxxx doutrb x x x x x x x x x x x x pdb1 pdb0 pda1 pda0 read daca and dacb shutdown mode bits. upio configuration bits din 1 1 1 0 1 0 0 x upsl2 upsl1 up3 up2 up1 up0 x x write upio configuration bits. see tables 19 and 22. din1110101xxxxxxxxx doutrb x x x x x x x x up3-2 up2-2 up1-2 up0-2 up3-1 up2-1 up1-1 up0-1 read upio configuration bits. settling-time-mode bits din 1 1 1 0 1 1 0 x x x x x x x spdb spda write daca and dacb settling-time mode bits. din1110111xxxxxxxxx doutrb x x x x x x x x x x x x x x spdb spda read daca and dacb settling-time mode bits. cpol and cpha control bits din 1 1 1 1 0 0 0 0 x x x x x x cpol cpha write cpol, cpha control bits. see table 15. din 11110001 x x x x x x x x doutrb x x x x x x x x x x x x x x cpol cpha read cpol, cpha control bits. table 2b. advanced-feature programming commands x = don? care.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 20 ______________________________________________________________________________________ control bits data bits data c3 c2 c1 c0 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function read input and dac registers a and b din 1 1 1 1 0 1 0 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x x x d ou trb x x x x x x x x d23 d22 d21 d20 d19 d18 d17 d16 d15/ x d14/ x d13/ x d12/ x d11 d10 d9 d8 d7 d6 d5 d4 d3/ x d2/ x d1/ x d0/ x read i np ut r eg i ster a and d ac r eg i ster a ( al l 24 b i ts) .** ? din 1 1 1 1 0 1 1 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x x x d ou trb x x x x x x x x d23 d22 d21 d20 d19 d18 d17 d16 d15/ x d14/ x d13/ x d12/ x d11 d10 d9 d8 d7 d6 d5 d4 d3/ x d2/ x d1/ x d0/ x read i np ut r eg i ster b and d ac r eg i ster b ( al l 24 b i ts) .** ? table 2c. 24-bit read commands x = don? care. ** d23?12 represent the 12-bit data from the corresponding dac register. d11?0 represent the 12-bit data from the corresponding input register. for the max5292/max5293, bits d13, d12, d1, and d0 are don?-care bits. for the max5294/max5295, bits d15?12 and d3?0 are don?-c are bits. ? during readback, all ones (code ff) must be clocked into din for all 24 bits. no command may be issued before all 24 bits have been clocked out. cs must be kept low while all 24 bits are clocked out. control bits data bits data c3 c2 c1 c0 d1 d1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function upio_ as gpi (general-purpose input) din1111001xxxxxxxxx doutrb x x x x x x x x x x rtp2 lf2 lr2 rtp1 lf1 lr1 read upio_ inputs. (valid only when upio1 or upio2 is configured as a general-purpose input.) see gpi, gpol, gpoh section. other commands din 1 1 1 1 1 0 0 x x x x x x x x x command is ignored. din 1 1 1 1 1 0 1 x x x x x x x x x command is ignored. din 1 1 1 1 1 1 0 x x x x x x x x x command is ignored. din 1 1 1 1 1 1 1 0 x x x x x x x x command is ignored. din 11111111 1 1 1 1 1 1 1 1 16-bit no-op command. all dacs are unaffected. table 2b. advanced-feature programming commands (continued) x = don? care.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 21 default register values at power-up correspond to the state of pu, e.g. input and dac registers are set to 800hex if pu is floating, fffhex if pu = dv dd , and 000hex if pu= dgnd. dac programming examples: to load input register a from the shift register, leaving dac register a unchanged (dac output unchanged), use the command in table 3. the max5290 max5295 can load dac register a from the shift register, leaving input register a unchanged, by using the command in table 4. to load input register a and dac register a simultane- ously from the shift register, use the command in table 5. for the 10-bit and 8-bit versions, set sub-bits = 0 for best performance. advanced feature programming commands refer to the programmer? handbook for details. select bits (ma, mb) the select bits allow synchronous updating of any com- bination of channels. the select bits command the loading of the dac register from the input register of each channel. set the select bit m_ = 1 to load the dac register _ with data from the input register _ , where _ is replaced with a or b depending on the selected channel. setting the select bit to m_ = 0 results in no action for that channel (table 6). table 3. load input register a from shift register table 4. load dac register a from shift register table 5. load input register a and dac register a from shift register table 6. select command data control bits data bits din 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 0 0 0 1 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 0 0 1 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 1 1 1 0 0 0 x x x x x x x x mb ma table 7. select bits programming example data control bits data bits din111000xxxxxxxx10 x = don? care. x = don? care.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 22 ______________________________________________________________________________________ table 9. shutdown-mode write command table 10. shutdown-mode bits write example table 11. shutdown-mode read command data control bits data bits din 1 1 1 0 0 1 0 x x x x x pdb1 pdb0 pda1 pda0 data control bits data bits din 1 1 1 0 0 1 0 x x x x x 0 1 0 0 data control bits data bits din 1110011xxxxxxxxx doutrb x x x xxxxxxxxx pdb1 pdb0 pda1 pda0 x = don? care. x = don? care. table 12. settling-time-mode write command data control bits data bits din 1 1 1 0 1 1 0 x x x x x x x spdb spda x = don? care. x = don? care. select bits programming example: to load dac register b from input register b while keeping channel a unchanged, set mb = 1 and ma = 0, as in the command in table 7. shutdown-mode bits (pda0, pda1, pdb0, pdb1) use the shutdown-mode bits to shut down each dac independently. set pd_0 and pd_1 according to table 8 to select the shutdown mode for dac_, where _ is replaced with a or b depending on the selected chan- nel. the three possible states for unity-gain versions are 1) normal operation, 2) shutdown with 1k ? output impedance, and 3) shutdown with 100k ? output imped- ance. the three possible states for force-sense ver- sions are 1) normal operation, 2) shutdown with 1k ? output impedance, and 3) shutdown with high-imped- ance output. table 9 shows the command for writing to the shutdown mode bits. shutdown-mode bits write example: to put a unity-gain version s daca into shutdown mode with internal 1k ? termination to ground and dacb into the shutdown mode with the internal 100k ? termination to ground, use the command in table 10 (applicable to unity-gain output only). to read back the shutdown-mode bits, use the com- mand in table 11. table 8. shutdown-mode bits pd_1 pd_0 descriptions 00 shutdown with 1k ? termination to ground on dac_ output. 01 shutdown with 100k ? termination to ground on dac_ output for unity-gain versions. shutdown with high-impedance output for force-sense versions. 1 0 ignored. 11 dac_ is powered up in its normal operating mode.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 23 settling-time-mode bits (spda, spdb) the settling-time-mode bits select the settling time (fast mode or slow mode) of the max5290 max5295. set spd_ = 1 to select fast mode or set spd_ = 0 to select slow mode, where _ is replaced by a or b, depending on the selected channel (see table 12). fast mode provides a 3s maximum set- tling time and slow mode provides a 10s maximum settling time. default settling-time mode bits are [0, 0] (slow mode for both dacs). settling-time-mode write example: to configure daca into fast mode and dacb into slow mode, use the command in table 13. to read back the settling-time-mode bits, use the com- mand in table 14. cpol and cpha control bits the cpol and cpha control bits of the max5290 max5295 are defined the same as the cpol and cpha bits in the spi standard. set the cpol = 0 and cpha = 0 or set cpol = 1 and cpha = 1 for microwire and spi applications requiring the clocking of data in on the rising edge of sclk. set the cpol = 0 table 13. settling-time-mode write example data control bits data bits din 1 1 1 0 1 1 0 x x x x x x x 0 1 x = don? care. table 14. settling-time-mode read command data control bits data bits din 1110111xx xxxxx x x doutrb x xxxxxxxxxxxxx spdb spda table 17. cpol and cpha read command data control bits data bits din 1111 0 0 0 1 x x x x x x x x doutrb xxxx x x x x x x x x x x cpol cpha table 15. cpol and cpha bits cpol cpha description 00 default values at power-up when dsp is connected to dv dd . data is clocked in on the rising edge of sclk. 01 default values at power-up when dsp is connected to dgnd. data is clocked in on the falling edge of sclk. 1 0 data is clocked in on the falling edge of sclk. 1 1 data is clocked in on the rising edge of sclk. table 16. cpol and cpha write command data control bits data bits din 1 1 1 1 0 0 0 0 x x x x x x cpol cpha x = don? care. x = don? care. x = don? care.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 24 ______________________________________________________________________________________ table 20. upio programming example data control bits data bits din1110100x010000xx x = don? care. table 21. upio read command data control bits data bits din 11101 01xxxxxxxxx doutrb x x x x x x x x up3-2 up2-2 up1-2 up0-2 up3-1 up2-1 up1-1 up0-1 x = don? care. and cpha = 1 or set cpol = 1 and cpha = 0 for dsp and spi applications requiring the clocking of data in on the falling edge of sclk (refer to the programmer? handbook and see table 15 for details). at power-up, if dsp = dv dd , the default value of cpha is zero and if dsp = dgnd, the default value of cpha is one. the default value of cpol is zero at power-up. to write to the cpol and cpha bits, use the command in table 16. to read back the device s cpol and cpha bits, use the command in table 17. upio bits (upsl1, upsl2, up0?p3) the max5290 max5295 provide two user-programma- ble input/output (upio) ports: upio1 and upio2. these ports have 15 possible configurations, as shown in table 22. upio1 and upio2 can be programmed inde- pendently or simultaneously by writing to the upsl1, upsl2, and up0 up3 bits (see table 18). table 19 shows how upio1 and upio2 are selected for configuration. the up0 up3 bits select the desired functions for upio1 and/or upio2 (see table 22). default states of up10_ are high impedance. if using up10_, connect 10k ? pullup resistors from each upio pin to dv dd . upio programming example: to set only upio1 as ldac and leave upio2 unchanged, write the command in table 20. the upio selection and configuration bits can be read back from the max5290 max5295 when upio1 or upio2 is configured as a doutrb output. table 21 shows the read-back data format for the upio bits. writing a 1110 101x xxxx xxxx initiates a read operation of the upio bits. the data is clocked out starting on the 9th clock cycle of the sequence. up3-2 through up0-2 provide the up3 up0 configuration bits for upio2 (see table 22), and up3-1 through up0-1 provide the up3 up0 configuration bits for upio1. table 18. upio write command data control bits data bits din 1 1 1 0 1 0 0 x upsl2 upsl1 up3 up2 up1 up0 x x x = don? care. table 19. upio selection bits (upsl1 and upsl2) upsl2 upsl1 upio port selected 0 0 none selected 0 1 upio1 selected 1 0 upio2 selected 1 1 both upio1 and upio2 selected
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 25 user-programmable input/output (upio) configuration table 22 lists the possible configurations for upio1 and upio2. upio1 and upio2 use the selected function when configured by the up3 up0 configuration bits. ldac ldac controls loading of the dac registers. when ldac is high, the dac registers are latched, and any change in the input registers does not affect the con- tents of the dac registers or the dac outputs. when ldac is low, the dac registers are transparent, and the values stored in the input registers are fed directly to the dac registers, and the dac outputs are updated. drive ldac low to asynchronously load the dac regis- ters from their corresponding input registers (dacs that are in shutdown remain shut down). the ldac function does not require any activity on cs , sclk, or din. if ldac is brought low coincident with a rising edge of cs, (which executes a serial command modifying the value of either dac input register), then ldac must remain asserted for at least 120ns following the cs ris- ing edge. this requirement applies only to serial com- mands that modify the value of the dac input registers. see figures 5 and 6 for timing details. table 22. upio configuration register bits (up3 up0) upio configuration bits up3 up2 up1 up0 function description 0000 ldac active-low load dac input. drive low to asynchronously load all dac registers with data from input registers. 0001 set active-low input. drive low to set all input and dac registers to full scale. 0010 mid active-low input. drive low to set all input and dac registers to midscale. 0011 clr active-low input. drive low to set all input and dac registers to zero scale. 0100 pdl active-low power-down lockout input. drive low to disable software shutdown. 0101 reserved this mode is reserved. do not use. 0110 shdn1k active-low 1k ? shutdown input. overrides pd_1 and pd_0 settings. drive shdn1k low to pull outa and outb to agnd with 1k ? . 0111 shdn100k active-low 100k ? shutdown input. overrides pd_1 and pd_0 settings. for the max5290/max5292/max5294, drive shdn100k low to pull outa and outb to agnd with 100k ? . for the max5291/max5293/max5295, drive shdn100k low to leave outa and outb high impedance. 1000 doutrb data read-back output 1001 doutdc0 mode 0 daisy-chain data output. data is clocked out on the falling edge of sclk. 1010 doutdc1 mode 1 daisy-chain data output. data is clocked out on the rising edge of sclk. 1011 gpi general-purpose logic input 1100 gpol general-purpose logic-low output 1101 gpoh general-purpose logic-high output 1110 togg toggle input. toggles dac outputs between data in input registers and data in dac registers. drive low to set all dac outputs to values stored in input registers. drive high to set all dac outputs to values stored in dac registers. 1111 fast fast/slow settling-time mode input. drive low to select fast mode (3s) or drive high to select slow settling mode (10s). overrides the spda and spdb settings.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 26 ______________________________________________________________________________________ set , mid , clr the set , mid , and clr signals force the dac outputs to full scale, midscale, or zero scale (figure 5). these signals cannot be active at the same time. the active-low set input forces the dac outputs to full scale when set is low. when set is high, the dac out- puts follow the data in the dac registers. the active-low mid input forces the dac outputs to mid- scale when mid is low. when mid is high, the dac out- puts follow the data in the dac registers. the active-low clr input forces the dac outputs to zero scale when clr is low. when clr is high, the dac out- puts follow the data in the dac registers. if clr , mid , or set signals go low in the middle of a write command, reload the data to ensure accurate results. power-down lockout ( pdl ) the pdl active-low software-shutdown lockout input overrides (not overwrites), the pd_0 and pd_1 shut- down mode bits. pdl cannot be active at the same time as shdn1k or shdn100k (see the shutdown mode ( shdn1k , shdn100k ) section). if the pd_0 and pd_1 bits command the dac to shut down prior to pdl going low, the dac returns to shut- down mode immediately after pdl goes high, unless the pd_0 and pd_1 bits are changed in the meantime. shutdown mode ( s s h h d d n n 1 1 k k , s s h h d d n n 1 1 0 0 0 0 k k ) the shdn1k and shdn100k are active-low signals that override (not overwrite) the pd_1 and pd_0 bit set- tings. for the max5290/max5292/max5294, drive shdn1k low to select shutdown mode with outa and outb internally terminated with 1k ? to ground, or drive shdn100k low to select shutdown with an internal 100k ? termination. for the max5291/max5293/ max5295, drive shdn1k low for shutdown with 1k ? output termination, or drive shdn100k low for shut- down with high-impedance outputs. data output (doutrb, doutdc0, doutdc1) upio1 and upio2 can be configured as serial data outputs, doutrb (data out for read back), doutdc0 (data out for daisy-chaining, mode 0), and doutdc1 (data out for daisy-chaining, mode 1). the differences between doutrb and doutdc0 (or doutdc1) are as follows: the source of read-back data on doutrb is the dout register. daisy-chain doutdc_ data comes directly from the shift register. read-back data on doutrb is only present after a dac read command. daisy-chain data is present on doutdc_ for any dac write after the first 16 bits are written. the doutrb idle state ( cs = high) for read back is high impedance. daisy-chain doutdc_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. see figures 1 and 2 for timing details. t cms t ldl t s 0.5 lsb togg v out_ ldac pdl clr, mid, or set pdl affects dac ouptuts (v out_ ) only if dacs were previously shut down. figure 5. asynchronous signal timing t gp t lds end of cycle* gpo_ ldac *end-of-cycle represents the rising edge of cs or the 16th active clock edge, depending on the mode of operation. figure 6. gpo_ and ldac signal timing
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 27 gpi, gpol, gpoh upio1 and upio2 can each be configured as a gener- al-purpose logic input (gpi), a general-purpose logic- low output (gpol), or general-purpose logic-high output (gpoh). the gpi can detect interrupts from ps or microcon- trollers. it provides three functions: 1) sample the signal at gpi at the time of the read (rtp1 and rtp2). 2) detect whether or not a falling edge has occurred since the last read or reset (lf1 and lf2). 3) detect whether or not a rising edge has occurred since the last read or reset (lr1 and lr2). rtp1, lf1, and lr1 represent the data read from upio1. rtp2, lf2, and lr2 represent the data read from upio2. to issue a read command for the upio configured as gpi, use the command in table 23. once the command is issued, rtp1 and rtp2 provide the real-time status (0 or 1) of the inputs at upio1 or upio2, respectively, at the time of the read. if lf2 or lf1 is one, then a falling edge has occurred on the upio1 or upio2 input since the last read or reset. if lr2 or lr1 is one, then a rising edge has occurred since the last read or reset. gpol outputs a constant logic low, and gpoh outputs a constant logic high (see figure 6). togg use the togg input to toggle a dac output between the values in the input register and dac register. a delay of greater than 100ns from the end of the previ- ous write command is required before the togg signal can be correctly switched between the new value and the previously stored value. when togg = 0, the out- put follows the information in the input registers. when togg = 1, the output follows the information in the dac register (figure 5). fast the max5290 max5295 have two settling-time-mode options: fast (3s max at 12 bits) and slow (6s max at 12 bits). to select the fast mode, drive fast low, and to select slow mode, drive fast high. this over- rides (not overwrites) the spda and spdb bit settings. table 23. gpi read command data control bits data bits din 1111 0 0 1 x x x x x x x x x doutrb x x x x x x x x x x rtp2 lf2 lr2 rtp1 lf1 lr1 table 24. unipolar code table (gain = +1) dac contents msb lsb analog output 1111 1111 1111 +v ref (4095 / 4096) 1000 0000 0001 +v ref (2049 / 4096) 1000 0000 0000 +v ref (2048 / 4096) = v ref / 2 0111 1111 1111 +v ref (2047 / 4096) 0000 0000 0001 +v ref (1 / 4096) 0000 0000 0000 0 max5290 dac_ ref out_ v out_ = v ref x code / 4096 code is the dac_ input code (0 to 4095 decimal). figure 7. unipolar output circuit x = don? care.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 28 ______________________________________________________________________________________ applications information unipolar output figure 7 shows the unity gain of the max5290 in a unipolar output configuration. table 24 lists the unipolar output codes. bipolar output the max5290 outputs can be configured for bipolar operation, as shown in figure 8. the output voltage is given by the following equation: v out_ = v ref x (code - 2048) / 2048 where code represents the numeric value of the dac s binary input code (0 to 4095 decimal). table 25 shows digital codes and the corresponding output volt- age for the figure 8 circuit. configurable output gain the max5291/max5293/max5295 have force-sense out- puts, which provide a connection directly to the inverting terminal of the output op amp, yielding the most flexibility. the advantage of the force-sense output is that specific gains can be set externally for a given application. the gain error for the max5291/max5293/max5295 is speci- fied in a unity-gain configuration (op-amp output and inverting terminals connected) and additional gain error results from external resistor tolerances. the force-sense dacs allow many useful circuits to be created with only a few simple external components. an example of a custom, fixed gain using the max5291 s force-sense output is shown in figure 9. in this example, the external reference is set to 1.25v, and the gain is set to +1.1v/v with external discrete resis- tors to provide an approximate 0 to 1.375v dac output voltage range. v out_ = [(0.5 x v ref x code) / 4096] x [1 + (r2 / r1)] where code represents the numeric value of the dac s binary input code (0 to 4095 decimal). in this example, if r2 = 12k ? and r1 = 10k ? , set the gain = 1.1v/v: v out_ = [(0.5 x 1.25v x code) / 4096] x 2.2 table 25. bipolar code table (gain = +1) dac contents msb lsb analog output 1111 1111 1111 +v ref (2047 / 2048) 1000 0000 0001 +v ref (1 / 2048) 1000 0000 0000 0 0111 1111 1111 +v ref (1 / 2048) 0000 0000 0001 -v ref (2047 / 2048) 0000 0000 0000 -v ref (2048 / 2048) = -v ref figure 8. bipolar output circuit max5290 dac_ ref out_ 10k ? 10k ? v+ v- v out_ max5291 dac_ ref out_ fb_ r2 = 12k ? 0.1% 25ppm r1 = 10k ? 0.1% 25ppm figure 9. configurable output gain
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 29 power-supply and layout considerations bypass the analog and digital power supplies with a 10f capacitor in parallel with a 0.1f capacitor to ana- log ground (agnd) and digital ground (dgnd) (see figure 10). minimize lead lengths to reduce lead induc- tance. if noise is an issue, use shielding and/or ferrite beads to increase isolation. digital and ac transient signals coupling to agnd cre- ate noise at the output. connect agnd to the highest quality ground available. use proper grounding tech- niques, such as a multilayer board with a low-induc- tance ground plane. wire-wrapped boards and sockets are not recommended. for optimum system perfor- mance, use printed circuit (pc) boards with separate analog and digital ground planes. connect the two ground planes together at the low-impedance power- supply source. using separate power supplies for av dd and dv dd improves noise immunity. connect agnd and dgnd at the low-impedance power-supply source (see figure 11). max5290 max5295 v ref 10 f* 0.1 f* ref sclk din pu upio1 upio2 cs dsp agnd** dgnd** outa fba fbb outb max5291/ max5293/ max5295 only 10 f 0.1 f 0.1 f10 f dv dd av dd dv dd av dd *remove bypass capacitors on ref for ac-reference inputs. **connect analog and digital ground planes at the low-impedance power-supply source. figure 10. bypassing power supplies and reference max5290 max5295 0.1 f 10 f av dd agnd av dd agnd 0.1 f 10 f dv dd dgnd dv dd dgnd dv dd dgnd analog supply digital supply digital circuitry figure 11. separate analog and digital power supplies
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 30 ______________________________________________________________________________________ chip information transistor count: 16,758 process: bicmos 16 15 14 13 9 10 11 12 outb ref n.c. outa 4 3 2 1 sclk cs din dsp 5678 max5290 max5292 max5294 upio1 upio2 pu n.c. dv dd dgnd agnd av dd (4mm x 4mm) thin qfn 16 15 14 13 9 10 11 12 outb fbb ref fba 4 3 2 1 sclk cs din dsp 5678 max5291 max5293 max5295 upio1 upio2 pu outa dv dd dgnd agnd av dd (4mm x 4mm) thin qfn 14 13 12 11 10 9 8 1 2 3 4 5 6 7 upio2 pu outa ref cs din dsp upio1 top view max5290 max5292 max5294 outb av dd agnd dgnd dv dd sclk 14 tssop 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 upio2 pu outa fba ref fbb outb av dd agnd max5291 max5293 max5295 16 tssop upio1 dsp sclk din cs dv dd dgnd pin configurations selector guide part output buffer co nfigur ation r eso l u tio n ( b it s) inl (lsbs max) max5290 aeud* unity gain 12 1 max5290beud unity gain 12 4 max5290aete* unity gain 12 1 max5290bete unity gain 12 4 max5291 aeue* force sense 12 1 max5291beue force sense 12 4 max5291aete* force sense 12 1 max5291bete force sense 12 4 max5292 eud unity gain 10 1 max5292ete unity gain 10 1 max5293 eue force sense 10 1 max5293ete force sense 10 1 max5294 eud unity gain 8 0.5 max5294ete unity gain 8 0.5 max5295 eue force sense 8 0.5 max5295ete force sense 8 0.5 * future product?ontact factory for availability. specifications are preliminary.
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 31 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) tssop4.40mm.eps
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs 32 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps 21-0139 a package outline 12,16,20,24l qfn thin, 4x4x0.8 mm
max5290?ax5295 buffered, fast-settling, dual, 12-/10-/8-bit, voltage-output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) a 21-0139 package outline 12,16,20,24l qfn thin, 4x4x0.8 mm

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