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general description the max98090 is a fully integrated audio codec whose high-performance, ultra-low power consumption and small footprint make it ideal for portable applications. the device features a highly flexible input scheme with six input pins (wlp) that can be configured as analog or digital microphone inputs, differential or single-ended line inputs, or as full-scale direct differential inputs. analog inputs can be routed to the record path adc or directly to any analog output mixer. the device accepts master clock frequencies of either 256 x f s or from 10mhz to 60mhz. the digital audio inter - face supports master or slave mode operation, sample rates from 8khz to 96khz, and standard pcm formats such as i 2 s, left/right-justified, and tdm. the record/playback paths feature flexsound? technology dsp. this includes digital gain and filtering, a biquad filter (record), dynamic range control (playback), and a seven band parametric equalizer (playback) that can improve loud - speaker performance by optimizing the frequency response. the stereo class d speaker amplifier provides efficient amplification, features low radiated emissions, supports filterless operation, and can drive both 4 and 8 loads. the directdrive? stereo class h headphone ampli - fier provides a ground referenced output eliminating the need for large dc-blocking capacitors. the device also includes a differential receiver (earpiece) amplifier that can be reconfigured as a stereo single-ended line output. features and benefts 102db dr stereo dac to hp (8khz < f s < 96khz) 3.6mw playback power consumption 99db dr stereo adc (8khz < f s < 96khz) 4.1mw record power consumption 3 stereo single-ended/differential analog microphone/line inputs (wlp version) stereo pdm digital microphone input master clock frequencies from 256 x f s to 60mhz i 2 s/lj/rj/tdm digital audio interface flexsound technology signal processing ? record path biquad ? playback path 7-band parametric eq ? playback path automatic level control ? digital filtering and gain/level control stereo low emi class d speaker amplifiers ? 3.2w/channel (r l = 4, v spk_vdd = 5v, wlp) ? 1.8w/channel (r l = 8, v spk_vdd = 5v, wlp) stereo directdrive class h headphone amplifier jack detection and identification differential receiver amplifier/stereo line output extensive click-and-pop reduction circuitry rf immune analog inputs and outputs programmable microphone bias i 2 c control interface with two address options 49-bump 0.4mm wlp and 40-pin tqfn packages 19-6492; rev 0; 1/13 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max98090.related . simplifed block diagram evaluation kit available microphone 1 preamp/pga (differential) ? digit al biquad filt er (record) ? 7-band p arametri c equalizer (pla yback) ? dynamic range contro l (pla yback) ? digit al fil tering ? digit al gain / level control flexsound dsp line input a pga (differential or single-ended) microphone 2 preamp/pga (differential) line input b pga (differential or single-ended) 6 5 stereo digit al micophone power management control registers i 2 c digit al audio interf ace i 2 s/ tdm ba ttery 1.2v 1.8v jack detection 4 3 2 1 charge pump stereo adc stereo dac max98090 stereo headphon e class h amplifie r (single ended) speaker righ t class d amplifie r (differential) speaker left class d amplifie r (differential) speaker left class d amplifie r (differential) stereo line output class ab amplifie r (single ended) or 3-pole (trs) 4-pole (trrs) or analog microphone digit al microphone line input or or analog microphone line input or analog microphone line input or headphones or headset line output receive r/ earpiece or speaker left/ right max98090 ultra-low power stereo audio codec
maxim integrated 2 general description ............................................................................ 1 features and benefits .......................................................................... 1 simplified block diagram ........................................................................ 1 functional diagram ............................................................................ 9 absolute maximum ratings ..................................................................... 10 package thermal characteristics ................................................................ 10 electrical characteristics ....................................................................... 10 digital filter specifications ...................................................................... 20 digital input/output characteristics ............................................................... 24 input clock characteristics ..................................................................... 26 digital audio interface timing characteristics ....................................................... 27 i 2 c timing characteristics ...................................................................... 29 digital microphone timing characteristics ......................................................... 30 quiescent power consumption .................................................................. 31 typical operating characteristics ................................................................ 37 bump/pin configurations ....................................................................... 64 bump/pin descriptions ......................................................................... 66 detailed description ........................................................................... 68 device i 2 c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 software reset ............................................................................... 76 power and performance management ............................................................ 77 device performance configuration .............................................................. 77 device enable configuration .................................................................. 78 analog audio input configuration ................................................................ 81 analog microphone inputs .................................................................... 82 analog microphone preamplifier and pga ..................................................... 83 analog microphone bias voltage ............................................................. 84 digital microphone inputs ..................................................................... 84 digital microphone clock configuration ....................................................... 84 digital microphone frequency compensation ................................................... 86 analog line inputs .......................................................................... 89 analog line input mixers ................................................................... 89 analog line input pgas ................................................................... 90 analog input pga to analog output mixer ........................................................ 92 analog full-scale direct to adc mixer inputs ..................................................... 92 audio record path ............................................................................ 93 analog-to-digital converter (adc) .............................................................. 94 adc functional configuration ............................................................... 94 table of contents max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 3 adc input mixer configuration .............................................................. 95 record path flexsound dsp .................................................................. 95 record path digital filters .................................................................. 95 record path sidetone ..................................................................... 98 record path digital gain and level control .................................................... 99 digital audio interface (dai) configuration ........................................................ 100 dai clock control and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 master mode clock configuration ............................................................. 101 quick configuration mode ................................................................. 103 exact integer mode ...................................................................... 104 manual ratio mode ...................................................................... 105 slave mode clock configuration .............................................................. 105 dai digital audio data path control and routing ................................................. 107 dai digital audio data format ................................................................ 110 tdm mode data format .................................................................. 113 audio playback path .......................................................................... 115 playback path flexsound dsp ................................................................ 115 playback path digital gain and level control .................................................. 115 playback path 7-band parametric equalizer ................................................... 117 playback path dynamic range control ....................................................... 120 playback path digital filters ............................................................... 124 digital-to-analog converter (dac) configuration .................................................. 124 analog audio output configuration .............................................................. 126 analog class ab configurable receiver/line output .............................................. 127 receiver/earpiece mixer and gain control .................................................... 127 line output mixer and gain control ......................................................... 129 analog class d speaker output ............................................................... 131 speaker output mixer and gain control ...................................................... 132 efficient class d speaker output driver ...................................................... 134 analog class-h headphone output ............................................................ 134 headphone output mixer and gain control ................................................... 135 headphone ground sense ................................................................ 138 directdrive headphone output amplifier ..................................................... 139 class h amplifier charge pump ............................................................ 139 click-and-pop reduction .................................................................... 141 jack detection .............................................................................. 143 jack detection internal comparators ........................................................... 144 jack detection programmable debounce ....................................................... 144 table of contents ( continued ) max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 4 jack detection interrupt generation ............................................................ 146 operation with an internal pullup resistance .................................................... 146 operation with an external pullup resistance .................................................... 146 accessory button detection .................................................................. 148 jack detection with internal analog microphones ................................................. 148 quick setup configuration ..................................................................... 150 device status flags .......................................................................... 153 status flag masking ........................................................................ 153 device revision identification .................................................................. 154 i 2 c serial interface ........................................................................... 155 bit transfer ............................................................................... 155 start and stop conditions ................................................................. 155 early stop conditions ...................................................................... 155 slave address ............................................................................. 155 acknowledge .............................................................................. 156 write data format .......................................................................... 156 read data format .......................................................................... 157 applications information ....................................................................... 158 typical application circuits ................................................................... 158 startup/shutdown register sequencing ......................................................... 160 component selection ....................................................................... 161 ac-coupling capacitors .................................................................. 161 charge-pump capacitor selection .......................................................... 161 filterless class d speaker operation .......................................................... 161 emi considerations and optional ferrite bead filter ............................................ 162 rf susceptibility ........................................................................... 162 supply bypassing, layout, and grounding ....................................................... 163 recommended pcb routing ................................................................. 163 unused pins .............................................................................. 164 wlp applications information ................................................................. 164 ordering information ......................................................................... 165 chip information ............................................................................. 165 package information ......................................................................... 165 revision history ............................................................................. 166 table of contents ( continued ) max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 5 figure 1. i 2 s audio interface timing diagrams (tdm = 0) ............................................. 28 figure 2. tdm audio interface short mode timing diagram (tdm = 1, bci = 1) ........................... 28 figure 3. i 2 c interface timing diagram ............................................................ 29 figure 4. digital microphone timing diagram ....................................................... 30 figure 5. analog audio input functional diagram .................................................... 81 figure 6. analog microphone input functional diagram ............................................... 82 figure 7. digital microphone input functional diagram ................................................ 84 figure 8. digital microphone compensation filter frequency response .................................. 86 figure 9. analog line input functional diagram ..................................................... 89 figure 10. analog line input external gain configurations ............................................ 90 figure 11. analog direct to adc mixer input functional diagram ....................................... 92 figure 12. record path block diagram ............................................................ 93 figure 13. record path adc section ............................................................. 94 figure 14. record path flexsound technology dsp block ............................................ 96 figure 15. simplified digital audio interface block diagram ........................................... 100 figure 16. dai clock control and configuration section ............................................. 101 figure 17. dai digital data path configuration ..................................................... 107 figure 18. digital audio interface (dai) data path configurations ...................................... 108 figure 19. dai timing for i 2 s data format ......................................................... 111 figure 20. dai timing for left justified data formats ................................................ 111 figure 21. dai timing for right justified data formats ............................................... 112 figure 22. dai timing for tdm data format ........................................................ 114 figure 23. playback path block diagram .......................................................... 115 figure 24. playback path sidetone and level control ................................................ 116 figure 25. playback path dsp ................................................................... 117 figure 26. dynamic range compression and expansion ............................................. 120 figure 27. drc enable and make-up gain ........................................................ 120 figure 28. drc compression ratio and threshold .................................................. 121 figure 29. drc expansion ratio and threshold .................................................... 121 figure 30. drc attack and release time waveforms ............................................... 122 figure 31. playback path digital-to-analog converter ............................................... 125 figure 32. analog audio output functional diagram ................................................ 126 figure 33. receiver output functional diagram .................................................... 127 figure 34. stereo single-ended line output functional diagram ...................................... 128 figure 35. class d speaker output functional diagram .............................................. 131 figure 36. directdrive headphone output functional diagram ........................................ 134 figure 37. reduced power dac playback to headphone output configuration ........................... 136 figure 38. headphone output ground sense connections ........................................... 138 list of figures max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 6 figure 39. conventional vs. directdrive headphone output bias ...................................... 139 figure 40. class h amplifier charge pump operating ranges ........................................ 140 figure 41. class h amplifier supply range transitions ............................................... 141 figure 42. zero-crossing detection ............................................................... 141 figure 43. block diagram and typical application circuit for jack detection ............................. 143 figure 44. jack detection cases with internal pullup resistance ...................................... 145 figure 45. jack detection operation with external pullup resistance .................................... 147 figure 46. jack detection with internal analog microphones .......................................... 148 figure 47. start, stop, and repeated start conditions ......................................... 155 figure 48. acknowledge timing ................................................................. 156 figure 49. writing one byte of data to the max98090 .............................................. 156 figure 50. writing n-bytes of data to the max98090 ................................................ 156 figure 51. reading one byte of data from the max98090 ........................................... 157 figure 52. reading n-bytes of data from the max98090 ............................................ 157 figure 53. typical application circuit with analog microphone inputs and receiver output .................. 158 figure 54. typical application circuit with digital microphone input and stereo line outputs ................ 159 figure 55. optional class d ferrite bead filter ..................................................... 162 figure 56. optional class h output filter ......................................................... 162 figure 57. pcb breakout routing example for wlp package ......................................... 163 figure 58. wlp package ball dimensions ........................................................ 164 table 1. max98090 control register map ......................................................... 69 table 2. software reset register ................................................................ 76 table 3. bias control register ................................................................... 77 table 4. dac and headphone performance mode control register ..................................... 77 table 5. adc performance mode control register ................................................... 78 table 6. device shutdown register ............................................................... 78 table 7. input enable register ................................................................... 79 table 8. output enable register ................................................................. 80 table 9. microphone 1 enable and level configuration register ........................................ 83 table 10. microphone 2 enable and level configuration register ....................................... 83 table 11. microphone bias level configuration register .............................................. 85 table 12. digital microphone clocks for commonly used master clocks settings .......................... 85 table 13. digital microphone enable .............................................................. 85 table 14. digital microphone configuration ......................................................... 86 table 15. recommended compensation filter settings for f mclk = 11.2896mhz ........................... 87 list of figures ( continued ) list of tables max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 7 table 16. recommended compensation filter settings for f mclk = 12mhz ............................... 87 table 17. recommended compensation filter settings for f mclk = 12.288mhz ............................ 87 table 18. recommended compensation filter settings for f mclk = 13mhz/26mhz ......................... 88 table 19. recommended compensation filter settings for f mclk = 19.2mhz .............................. 88 table 20. recommended compensation filter settings for f mclk = 256 x f s .............................. 88 table 21. line input mixer configuration register .................................................... 89 table 22. external gain mode series resistance values .............................................. 90 table 23. line input level configuration register .................................................... 91 table 24. input mode and source configuration register .............................................. 91 table 25. left adc mixer input configuration register ................................................ 95 table 26. right adc mixer input configuration register .............................................. 95 table 27. dsp filter configuration register ........................................................ 96 table 28. dsp biquad filter enable register ....................................................... 97 table 29. record path biquad digital preamplifier level configuration register ............................ 97 table 30. record path biquad filter coefficient ..................................................... 98 table 31. record path sidetone configuration register ............................................... 98 table 32. left record path digital gain configuration register ......................................... 99 table 33. right record path digital gain configuration register ........................................ 99 table 34. system master clock (mclk) prescaler configuration register ............................... 102 table 35. master mode clock configuration register ................................................ 102 table 36. master clock quick setup register ...................................................... 103 table 37. sample rate quick setup register ...................................................... 103 table 38. quick configuration mode lookup ...................................................... 104 table 39. clock mode configuration register ...................................................... 104 table 40. manual clock ratio configuration register (ni msb) ........................................ 105 table 41. manual clock ratio configuration register (ni lsb) ........................................ 106 table 42. manual clock ratio configuration register (mi msb) ........................................ 106 table 43. manual clock ratio configuration register (mi msb) ....................................... 106 table 44. digital audio interface (dai) data path configurations ....................................... 109 table 45. digital audio interface (dai) input/output configuration register .............................. 109 table 46. digital audio interface (dai) format configuration register .................................... 110 table 47. digital audio interface (dai) tdm control register ........................................... 113 table 48. digital audio interface (dai) tdm format register .......................................... 113 table 49. playback gain and level configuration register ............................................ 116 table 50. dsp biquad filter enable register ....................................................... 118 table 51. parametric equalizer playback level configuration register ................................... 118 table 52. parametric equalizer band n (1C7) biquad filter coefficient registers ........................... 119 table 53. dynamic range control (drc) timing register ............................................ 123 list of tables ( continued ) max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 8 table 54. dynamic range control (drc) gain configuration register .................................. 123 table 55. dynamic range control (drc) compressor register ........................................ 123 table 56. dynamic range control (drc) expander register .......................................... 124 table 57. dsp filter configuration register ....................................................... 125 table 58. receiver and left line output mixer source configuration register ............................ 128 table 59. receiver and left line output mixer gain control register ................................... 129 table 60. receiver and left line output volume control register ...................................... 129 table 61. right line output mixer source configuration register ...................................... 130 table 62. right line output mixer gain control register ............................................. 130 table 63. right line output volume control register ................................................ 130 table 64. left speaker mixer configuration register ................................................ 132 table 65. right speaker mixer configuration register ............................................... 132 table 66 speaker mixer gain control register ..................................................... 132 table 67. left speaker amplifier volume control register ............................................ 133 table 68. right speaker amplifier volume control register ........................................... 133 table 69. left headphone mixer configuration register .............................................. 135 table 70. right headphone mixer configuration register ............................................ 135 table 71. headphone mixer control and gain register .............................................. 135 table 72. left headphone amplifier volume control register ......................................... 137 table 73. right headphone amplifier volume control register ........................................ 137 table 74. charge-pump operating ranges ........................................................ 139 table 75. zero-crossing detection and volume smoothing configuration register ........................ 142 table 76. jack detection status results .......................................................... 144 table 77. jack detect configuration register ...................................................... 149 table 78. jack status register ................................................................. 149 table 79. digital audio interface (dai) quick setup register .......................................... 150 table 80. playback path quick setup register ..................................................... 150 table 81. analog microphone/direct input to record path quick setup register ........................... 151 table 82. line input to record path quick setup register ............................................. 151 table 83. analog microphone input to analog output quick setup register .............................. 152 table 84. line input to analog output quick setup register .......................................... 152 table 85. device status interrupt register ........................................................ 153 table 86. device status interrupt mask register ................................................... 154 table 87. revision id number register ........................................................... 154 table 88. device i 2 c slave address ............................................................. 155 table 89. detailed device startup sequence ...................................................... 160 table 90. register changes that require shdn = 0 ................................................ 160 table 91. unused pin connections .............................................................. 164 list of tables ( continued ) max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 9 functional diagram prescaled clock (pclk) generation frame clock bit clock data output enable i2c interface bias control and generation output shift register input shift register data input enable playback input mixer loop back mux digital mic left mux digmicl adc left adc right loop through mux sdoen hizoff rj, dly ws[1:0] tdm, fsw slotdly[3:0] slotl/r[1:0] left filters mode ahpf dhf left biquad filter recbqen avbq[3:0] rec_b0[23:0] rec_b1[23:0] rec_b2[23:0] rec_a1[23:0] rec_a2[23:0] left sidetone dvg[1:0] dsts[1:0] dvst[4:0] bci wci mas mclk lrclk pll and clock generation bclk dai: clock control and configuration flexsound technology dsp dai: data path digital audio interface to adc clock generation to dac clock generation to digital mic control psclk[1:0] mben pa1en[1:0] extmic[0] adren adlen pclk dmdl dmdr adchp osr128 adcdither avlg[2:0] avl[3:0] avrg[2:0] avr[3:0] sdout dvdd dvddio sdin scl sda irq avdd ref v cm lten dmono sdien lben freq[3:0] bsel[2:0] mbvsel[1:0] use_mi ni[14:0] mi[14:0] headphon e directdrive charge pump digital mic right mux mic 1 input mux right filters jack detection jacksns micbias microphone bias generator micclk[2:0] digmicr digital microphone control right record path sidetone to playback path sidetone from playback pat h left record path right playback path left playback path right biquad filter right sidetone left sidetone dsts[1:0] right sidetone left 7-band parametric equalizer right 7-band parametric equalizer left/right drc: dynamic range contro l b0_eq_[23:0] b1_eq_[23:0] b2_eq_[23:0] a1_eq_[23:0] a2_eq_[23:0] eq_banden dveq[3:0] eqclp left filters mode dhpf right alc: automatic level control right filters dac left dac right dacren daclen dachp perfmode left level l /r st level right level dvm dv[3:0] left level mic 1 preamp pgam1[4:0] 0db to 20db 0db to 20db 0db 10db 30db 0db 10db 30db -6db to 20db -6db to 20db in1-in2 in3-in4 in5-in6 line a line b mic 1 mic 2 in1-in2 in3-in4 in5-in6 line a line b mic 1 mic 2 mic 1 pga mic 2 input mux mic 2 preamp zdenb pa2en[1:0] extmic[1] pgam2[4:0] lineaen extbufa mixhpr[5:0] mixhprg[1:0] in1seen in3seen in5seen in34diff in2seen in4seen in6seen in65diff linbpga[2:0] line a pga line b pga lineben extbufb linapga[2:0] line a input mixer mixg135 mixg246 line b input mixer adc left mixer adc right mixer dacl dacr mic 1 mic 2 line a line b hp right mixer dacl dacr mic 1 mic 2 line a line b hp left mixer dacl dacr mic 1 mic 2 line a line b spk right mixer dacl dacr mic 1 mic 2 line a line b spk left mixer dacl dacr mic 1 mic 2 line a line b rcv/ line out right mixer dacl dacr mic 1 mic 2 line a line b rcv/ line out left mixer mixadr[6:0] mixadl[6:0] mic 2 pga right level left gain right gain in1-in2 in5-in6 in1/ dmd in3 in4 in5 in6 (wlp only) in2/ dmc mixhplsel mixhprsel linmod hp left mux rcv/ line out mux in3-in4 in5-in6 in3 in1 in3-in4 in5 in4 in2 in6-in5 in6 hpvoll[4:0] hplm hplen -67db to 3db -67db to 3db -12db to 0db -12db to 0db -12db to 0db hp right mux -12db to 0db rcvlvol[4:0] rcvlm rcvlen headphone left pga headphone right pga hpvolr[4:0] hprm hpren rcvrvol[4:0] rcvrm rcvren spkslave mixhpl[5:0] mixhplg[1:0] mixspl[5:0] mixsplg[1:0] spvolr[4:0] splm spren spvoll[4:0] splm splen -48db to 14db 6db speaker right pga -12db to 0db mixspl[5:0] mixsplg[1:0] mixspl[5:0] mixsplg[1:0] mixspl[5:0] mixsplg[1:0] -48db to 14db 6db speaker left pga -62db to 8db -12db to 0db line out right pga -62db to 8db rcvp/ loutl rcvn/ loutr spklp spklgnd spk_vdd spkrgnd hpsns hpl hpr hpvdd hpgnd spkln spkrp spkrn line out left pga drcen drcg[4:0] drcrls[2:0] drcatk[2:0] drccmp[2:0] drcthc[4:0] drcexp[2:0] drche[4:0] analog inpu t to analog output cpvss agnd dgnd cpvdd c1n c1p max98090 analog inputs to adc dac to analog outputs zden vs2en vsen zden vs2en vsen zden vs2en vsen max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 10 electrical characteristics (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . (voltages with respect to agnd, unless otherwise noted.) avdd, dvdd, hpvdd ......................................... -0.3v to +2.2v spklvdd, spkrvdd, dvddio ......................... -0.3v to +6.0v dgnd, hpgnd, spklgnd, spkrgnd ............. -0.1v to +0.1v cpvdd ............................ (v hpgnd - 0.3v) to (v hpgnd + 2.2v) cpvss ............................ (v hpgnd - 2.2v) to (v hpgnd + 0.3v) c1n .................................. (v cpvss - 0.3v) to (v hpgnd + 0.3v) c1p .................................. (v hpgnd - 0.3v) to (v cpvdd + 0.3v) micbias ......................................... -0.3v to (v spklvdd + 0.3v) ref, bias ............................................ -0.3v to (v avdd + 0.3v) mclk, sdin, sda, scl, irq .............................. -0.3v to +6.0v lrclk, bclk, sdout .................... -0.3v to (v dvddio + 0.3v) in1, in2, in3, in4, in5, in6 ................................. -0.3v to +2.2v hpsns ............................ (v hpgnd - 0.3v) to (v hpgnd + 0.3v) hpl, hpr ......................... (v cpvss - 0.3v) to (v cpvdd + 0.3v) rcvp/loutl ........... (v spklgnd - 0.3v) to (v spklvdd + 0.3v) rcvn/loutr .......... (v spklgnd - 0.3v) to (v spklvdd + 0.3v) spklp, spkln ........ (v spklgnd - 0.3v) to (v spklvdd + 0.3v) spkrp, spkrn ...... (v spkrgnd - 0.3v) to (v spkrvdd + 0.3v) jacksns ............................................................. -0.3v to +6.0v continuous power dissipation (t a = +70c) wlp (derate 23.8mw/c above +70c) .......................... 1.9w tqfn (derate 35.7mw/c above +70c) ...................... 2.86w operating temperature range ........................... -40c to +85c storage temperature range ............................ -65c to +150c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. junction-to-case thermal resistance ( jc ) tqfp ............................................................................. 1c/w junction-to-ambient thermal resistance ( ja ) tqfp ............................................................................. 1c/w absolute maximum ratings package thermal characteristics (note 1) parameter symbol conditions min typ max units power supply supply voltage range guaranteed by psrr (note 3) v spklvdd , v spkvdd , v spkrvdd 2.8 3.7 5.5 v v avdd , v hpvdd 1.65 1.8 2 v dvdd 1.08 1.2 1.98 v dvddio 1.65 1.8 3.6 total supply current (note 4) i vdd full-duplex 8khz mono, receiver output analog 1.94 3.5 ma speaker 0.73 2 digital 0.97 1.2 dac playback 48khz stereo, headphone outputs analog 1.45 2 speaker 0 0.005 digital 1.04 1.3 dac playback 48khz stereo, speaker outputs analog 0.91 2.4 speaker 2.18 3 digital 1.05 1.3 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 11 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units ref voltage 1.25 v bias voltage bias from resistive division (bias_mode = 0) 0.90 v bias from bandgap (bias_mode = 1) 0.78 shutdown supply current (note 4) t a = +25c analog 1 10 a speaker 1 5 digital 2.1 20 shutdown to full operation 10 ms differential input (analog microphone) to adc record path dynamic range (note 5) dr f s = 48khz, mode = 1 (fir audio), a-weighting flter applied 97 db f s = 8khz, mode = 0 (iir voice), a-weighting flter applied 90 96 db total harmonic distortion + noise thd+n a v_micpre = 20db, v in = 90mv rms , f = 1khz, -82 -75 db av_micpre = 0db, v in = 900mv rms , f = 1khz -91 a v_micpre = 30db, v in = 28.5mv rms , f = 1khz -73 common-mode rejection ratio cmrr f = 217hz, v in_cm = 100mv p-p 59 db power-supply rejection ratio (note 3) psrr v avdd = 1.65v to 2.0v, input referred 40 57 db v ripple = 100mv p-p , input referred f = 217hz 78 f = 1khz 78 f = 10khz 77 path phase delay 1khz, 0db input, highpass flter disabled measured from analog input to digital output mode = 0 (voice) 8khz 2.2 ms mode = 0 (voice) 16khz 1.1 mode = 1 (audio) 8khz 4.5 mode = 1 (audio) 48khz 0.8 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 12 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units gain error dc accuracy 1 6.2 % differential (analog microphone) preamp and pga full-scale input a v_micpre = 0db 1 v rms microphone preamplifer gain a v_micpre (note 6) pa_en[1:0] = 01 0 db pa_en[1:0] = 10 19 20 21 pa_en[1:0] = 11 29 30 31 microphone level adjust gain (pga) a v_micpga (note 6) pgam_[4:0] = 0x00 19 20 21 db pgam_[4:0] = 0x14 0 mic input resistance r in_mic all gain settings, measured at in_ (measured single-ended) 28 50 k microphone bias micbias output voltage v micbias i load = 1ma, mbvsel[1:0] = 00 2.1 2.2 2.3 v i load = 1ma, mbvsel[1:0] = 01 2.3 2.4 2.5 i load = 1ma, mbvsel[1:0] = 10 2.475 2.57 2.7 i load = 1ma, mbvsel[1:0] = 11 2.7 2.8 2.9 load regulation i load = 1ma to 2ma, mbvsel[1:0] = 00 wlp 0.085 0.5 mv tqfn 0.085 0.75 line regulation v spklvdd = 2.8v to 5.5v, mbvsel[1:0] = 00 0.01 1 mv ripple rejection f = 217hz, v ripple (spklvdd) = 100mv p-p 70 db f = 10khz, v ripple (spklvdd) = 100mv p-p 75 noise voltage a-weighted, f = 20hz to 20khz 7.4 v rms f = 1khz 52.3 nv/ hz single-ended (line) input to adc path dynamic range (note 5) dr f s = 48khz, f mclk = 12.288mhz, mode = 1 (fir audio) 98 db total harmonic distortion + noise thd+n v in = 0.222v rms , f = 1khz -85 -80 db single-ended (line) input pga full-scale input v in 0.5 v rms a v_external = -6db, extbuf = 1 1 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 13 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units line input level adjust gain (pga) a v_linepga (note 6) pgalin = 0x0 18 20 21.5 db pgalin = 0x1 13 14 15 pgalin = 0x2 2 3 4 pgalin = 0x3 -1 0 +1 pgalin = 0x4 -4 -3 -2 pgalin = 0x5, 0x6, 0x7 -7 -6 -5 line input amplifer gain a v_lineamp single-ended only 6 db input resistance r in 14 20 k feedback resistance r in_fb t a = +25c 19 20 21 k digital loop-through: record output to playback input path dynamic range (note 5) dr f s = 48khz, f mclk = 12.288mhz, mode = 1 (fir audio) 97 db total harmonic distortion + noise thd+n f in = 1khz, f s = 48khz, f mclk = 12.288mhz, mode = 1 (fir audio) -83 -72 db dac playback path to receiver amplifier path dynamic range (note 5) dr f s = 48khz, f mclk = 12.288mhz 100 db total harmonic distortion + noise thd+n f = 1khz, p out = 20mw, r rec = 32 w -68 -58 db differential analog input to receiver amplifier path dynamic range (note 5) dr 90 96 db total harmonic distortion + noise thd+n -71 db power-supply rejection ratio (note 3) psrr v spklvdd = 2.8v to 5.5v 68.4 80 db v ripple = 100mv p-p f = 217hz 77 f = 1khz 77 f = 10khz 69 receiver amplifier (note 7) output power p out r rec = 32 w , f = 1khz, thd < 1%, bias_ mode = 0 97 mw r rec = 32 w , f = 1khz, thd < 1%, bias_ mode = 1 74 full-scale output a v_recpga = 0db (note 8) 1 v rms receiver volume control (pga) a v_recpga (notes 6 and 9) rcvlvol = 0x00 -63 -61 -59.5 db rcvlvol = 0x1f +7.2 +8 +8.75 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 14 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units volume control step size (note 9) +8db to +6db 0.5 db +6db to +0db 1 0db to -14db 2 -14db to -38db 3 -38db to -62db 4 mute attenuation f = 1khz 87 97 db output offset voltage v os a v_rec = -62db, t a = +25c 3 mv click-and-pop level k cp peak voltage, a-weighted, 32 samples per second, a v_rec = 0db into shutdown -67 dbv out of shutdown -68 capacitive drive capability no sustained oscillations r l = 32 w 500 pf r l = 100 dac playback path to lineout amplifier path dynamic range (note 5) dr f s = 48khz, f mclk = 12.288mhz 100 db total harmonic distortion + noise thd+n f = 1khz, r lout = 10k w (0.5v rms output level) -86 -70 db single-ended analog input to line out amplifier path dynamic range (note 5) dr 98 db total harmonic distortion + noise thd+n f = 1khz, r lout = 10k w (0.5v rms output level) -86 db power-supply rejection ratio (note 3) psrr v spk_vdd = 2.8v to 5.5v 60 74 db v ripple = 100mv p-p f = 217hz 74 f = 1khz 74 f = 10khz 73 line out amplifier (note 7) full-scale output (note 8) 0.707 v rms line output amplifer gain a v_loutamp -3 db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 15 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units line output volume control (pga) a v_loutpga (notes 6 and 9) rcv_vol = 0x00 -63 -61 -59.5 db rcv_vol = 0x1f +7.2 +8 +8.75 volume control step size (note 9) 8db to 6db 0.5 db 6db to 0db 1 0db to -14db 2 -14db to -38db 3 -38db to -62db 4 mute attenuation f = 1khz 87 97 db capacitive drive capability no sustained oscillations r lout = 1k w 500 pf r lout = 100 dac playback path to speaker amplifier path dynamic range (note 5) dr 91 db total harmonic distortion + noise thd+n f = 1khz, p out = 200mw, z spk = 8 w + 68h, f mclk = 12.288mhz -73 db crosstalk spl to spr and spr to spl, p out = 640mw, f = 1khz -104 db output noise 27 v rms differential analog input to speaker amplifier path dynamic range (note 5) dr output referenced to 2v rms 91 db total harmonic distortion + noise thd+n f = 1khz, p out = 200mw, z spk = 8 w + 8 m h -73 db output noise 28 v rms power-supply rejection ratio (note 3) psrr v spk_vdd = 2.8v to 5.5v 50 80 db v ripple = 100mv p-p f = 217hz 68 f = 1khz 67 f = 10khz 61 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 16 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units speaker amplifier (note 7) output power p out f = 1khz, thd+n = 1%, z spk = 8 w + 68h, wlp package v spk_vdd = 5.0v 1400 mw v spk_vdd = 4.2v 1000 v spk_vdd = 3.7v 780 v spk_vdd = 3.3v 600 v spk_vdd = 3.0v 500 f = 1khz, thd+n = 10%, z spk = 8 w + 68h, wlp package v spk_vdd = 5.0v 1800 v spk_vdd = 4.2v 1250 v spk_vdd = 3.7v 970 v spk_vdd = 3.3v 760 v spk_vdd = 3.0v 620 output power p out f = 1khz, thd+n = 1%, z spk = 4 w + 33h, wlp package v spk_vdd = 5.0v 2600 mw v spk_vdd = 4.2v 1800 v spk_vdd = 3.7v 1400 v spk_vdd = 3.3v 1050 v spk_vdd = 3.0v 850 f = 1khz, thd+n = 10%, z spk = 4 w + 33h, wlp package v spk_vdd = 5.0v 3200 v spk_vdd = 4.2v 2200 v spk_vdd = 3.7v 1700 v spk_vdd = 3.3v 1350 v spk_vdd = 3.0v 1100 full-scale output a v_spk = +6db (note 8) 2 v rms speaker output amplifer gain a v_spkamp +6 db speaker volume control (pga) a v_spkpga (notes 6 and 9) s pvol_ = 0x00 -51 -48 -44.5 db s pvol_ = 0x1f 13 14 15 volume control step size (note 9) 14db to 9db 0.5 db +9db to -6db 1 -6db to -14db 2 -14db to -32db 3 -32db to -48db 4 mute attenuation f = 1khz 76 84 db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 17 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units output offset voltage v os a v_spkpga = -62db, t a = +25c 0.5 4 mv click-and-pop level k cp peak voltage, a-weighted, 32 samples per second, a v_spk = 0db into shutdown -65 dbv out of shutdown -65 dac playback path to headphone amplifier path dynamic range (note 5) dr f s = 48khz, f mclk = 12.288mhz master or slave mode 102 db slave mode 94 total harmonic distortion + noise thd+n f = 1khz, p out = 10mw r hp = 16 w -86 -77 db r hp = 32 w -88 f = 1khz, v out = 1v rms , r hp = 10k w -88 crosstalk f = 1khz, v in = -1dbfs, r hp = 10k w -105 db hpl to hpr and hpr to hpl, p out = 5mw, f = 1khz, r hp = 32 w -104 db power-supply rejection ratio (note 3) psrr v avdd = v hpvdd = 1.65v to 2.0v 70 80 db v ripple = 100mv p-p , a v_hp = 0db f = 217hz 79 f = 1khz 79 f = 10khz 74 dac path phase delay 1khz, 0db input, highpass flter disabled measured from digital input to analog output mode = 0 (voice) 8khz 2.2 ms mode = 0 (voice) 16khz 1.1 mode = 1 (audio) 8khz 4.5 mode = 1 (audio) 48khz 0.76 gain error 1 5 % channel gain mismatch 1 % single-ended analog input to headphone amplifier path dynamic range (note 5) a v_line = 0db a v_hppga = 0 db 101 db total harmonic distortion + noise thd+n v in = 250mv rms , f =1khz -80 db crosstalk hpl to hpr and hpr to hpl, p out = 5mw, f = 1khz, r hp = 32 w -94 db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 18 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units power-supply rejection ratio (note 3) psrr v avdd = v hpvdd = 1.65v to 2.0v 40 60 db v ripple = 100mv p-p , a v_total = 0db f = 217hz 61 f = 1khz 61 f = 10khz 60 headphone amplifier (note 7) output power p out f = 1khz, thd = 1% r hp = 16 w 20 40 mw r hp = 32 w 30 total harmonic distortion + noise thd+n r hp = 16 w , p out = 10mw, f = 1khz -88 -77 db r hp = 10k w , v out = 1v rms , f = 1khz -88 full-scale output a vhp = 0db (note 8) 1 v rms headphone volume control (pga) a v_hppga hpvol_ = 0x00 -69 -67 -65 db hpvol_ = 0x1f 2.5 3 3.5 volume control step size (note 9) +3db to +1db 0.5 db +1db to -5db 1 -5db to -19db 2 -19db to -43db 3 -43db to -67db 4 mute attenuation f = 1khz 110 db output offset voltage v os av_hp = -67db t a = +25c 0.5 1 mv t a = t min to t max 3 capacitive drive capability no sustained oscillations r hp = 32 w 500 pf r hp = 100 click-and-pop level k cp peak voltage, a-weighted, 32 samples per second, a v_hp = -67db into shutdown -73 dbv out of shutdown -73 jack detection jacksns high threshold v th_high micbias enabled 0.80 x v micbias 0.95 x v micbias 0.98 x v micbias v micbias disabled 0.80 x v spklvdd 0.95 x v spklvdd 0.98 x v spklvdd max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 19 electrical characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units jacksns low threshold v th_low micbias enabled 0.06 x v micbias 0.10 x v micbias 0.17 x v micbias v micbias disabled 0.06 x v spklvdd 0.10 x v spklvdd 0.17 x v spklvdd jacksns sense voltage v sense micbias disabled v spklvdd v jacksns strong pullup resistance r spu micbias disabled, jdwk = 0 1.9 2.4 2.7 k jacksns weak pullup current i wpu micbias disabled, jdwk = 1 5 12 a jacksns glitch debounce period t glitch jdeb = 00 25 ms jdeb = 11 200 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 20 digital filter specifcations (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (notes 2, 10) parameter symbol conditions min typ max units record path level control record level adjust range a v_adclvl avl/avr = 0xf to 0x0 (note 6) -12 +3 db record level adjust step size 1 db record gain adjust range a v_adcgain avlg/avrg = 0x0 to 0x3 (note 6) 0 42 db record gain adjust step size 6 db record path voice mode iir lowpass filter (mode = 0) passband cutoff f plp ripple limit cutoff 0.444 x f s hz -3db cutoff 0.449 x f s passband ripple f < f plp -0.1 0.1 db stopband cutoff f slp 0.47 x f s hz stopband attenuation f > f slp 74 db record path stereo audio mode fir lowpass filter (mode = 1, dhf = 0, f lrclk < 50khz) passband cutoff f plp ripple limit cutoff 0.43 x f s hz -3db cutoff 0.48 x f s -6.02db cutoff 0.5 x f s passband ripple f < f plp -0.1 +0.1 db stopband cutoff f slp 0.58 x f s hz stopband attenuation f < f slp 60 db record path stereo audio mode fir lowpass filter (mode = 1, dhf = 1, f lrclk > 50khz) passband cutoff f plp ripple limit cutoff 0.208 x f s hz -3db cutoff 0.28 x f s passband ripple f < f plp -0.1 +0.1 db stopband cutoff f slp 0.45 x f s hz stopband attenuation f < f slp 60 db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 21 digital filter specifcations (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (notes 2, 10) parameter symbol conditions min typ max units record path dc-blocking highpass filter dc attenuation a v_adchpf ahpf = 1 90 db record path programmale biquad filter preattenuator gain range -15 0 db preattenuator step size 1 db cutoff frequency highpass flter 0.0008 x f s hz high-frequency shelving flter 0.02 x f s lowpass flter 0.002 x f s low-frequency shelving flter 0.0008 x f s peak flter 0.0008 x f s quality factor q peak flter 10 digital sidetone: record path to playback path (mode = 0) sidetone level adjust range a v_stlvl dvst = 0x1f to 0x01 -60.5 -0.5 db sidetone level adjust step side 2 db sidetone path phase delay f in = 1khz, full-scale amplitude, highpass flter disabled f s = 8khz 1.8 ms f s = 16khz 0.9 playback path level control playback path attenuation range a v_daclvl dv1 = 0xf to 0x0 (note 6) -15 0 db playback path attenuation step size 1 db playback path gain adjust range a v_dacgain dv1g = 00 to 11 (note 6) 0 18 db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 22 digital filter specifcations (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (notes 2, 10) playback path gain adjust step size 6 db parameter symbol conditions min typ max units playback path voice mode iir lowpass filter (mode = 0) passband cutoff f plp ripple limit cutoff 0.448 x f s hz -3db cutoff 0.451 x f s passband ripple f < f plp -0.1 +0.1 db stopband cutoff f slp 0.476 x f s hz stopband attenuation (note 11) f > f slp 75 db playback path stereo audio mode fir lowpass filter (mode = 1, dhf = 0, f lrclk < 50khz) passband cutoff f plp ripple limit cutoff 0.43 x f s hz -3db cutoff 0.47 x f s -6.02db cutoff 0.5 x f s passband ripple f < f plp -0.1 +0.1 db stopband cutoff f slp 0.58 x f s hz stopband attenuation (note 11) f > f slp 60 db playback path stereo audio mode fir lowpass filter (mode1 = 1, dhf = 1 for f lrclk > 50khz) passband cutoff f plp ripple limit cutoff 0.24 x f s hz -3db cutoff 0.31 x f s passband ripple f < f plp -0.1 +0.1 db stopband cutoff f slp 0.477 x f s hz stopband attenuation (note 11) f < f slp 60 db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 23 digital filter specifcations (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (notes 2, 10) playback path dc-blocking highpass filter dc attenuation a v_dachpf dhpf = 1 89 db parameter symbol conditions min typ max units playback path dynamic range control gain range 0 12 db compression threshold -31 0 dbfs expansion threshold -66 -35 dbfs attack time 0.0005 0.2 s release time 0.0625 8 s playback path parametric equalizer number of bands 7 bands per band gain range -12 +12 db preattenuator gain range -15 0 db preattenuator step size 1 db cutoff frequency highpass flter 0.0008 x f s hz high-frequency shelving flter 0.02 x f s lowpass flter 0.002 x f s low-frequency shelving flter 0.0008 x f s peak flter 0.0008 x f s quality factor q peak flter 10 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 24 digital input/output characteristics (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (rhp) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units mclk input high voltage v ih 1.26 v input low voltage v il 0.6 v input leakage current i ih , i il v dvddio = 2.0v, v in = 0v, 5.5v, t a = +25c -1 +1 a input capacitance 10 pf sdin, bclk, lrclk (input) input high voltage v ih 0.7 x v dvddio v input low voltage v il 0.3 x v dvddio v input hysteresis 100 mv input leakage current i ih , i il v dvddio = 3.6v, v in = 0v, 3.6v, t a = +25c -1 +1 a input capacitance 10 pf bclk, lrclk, sdout (output) output high voltage v oh i oh = 3ma v dvddio - 0.4 v output low voltage v ol i ol = 3ma 0.4 v input leakage current i ih , i il v dvddio = 2.0v, v in = 0v, 5.5v, t a = +25c, high-impedance state -1 +1 a sda, scl (input) input high voltage v ih 0.7 x v dvddio v input low voltage v il 0.3 x v dvddio v input hysteresis 100 mv input leakage current i ih , i il v dvddio = 2.0v, v in = 0v, 5.5v, t a = +25c -1 +1 a input capacitance 10 pf sda, irq (output) output low voltage v ol i oh = 3ma 0.2 x v dvddio v output high current i oh i ol = 3ma 1 a max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 25 digital input/output characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (rhp) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units digmicdata (input) input high voltage v ih 0.65 x v dvddio v input low voltage v il 0.35 x v dvddio v input hysteresis 100 mv input leakage current i ih , i il v dvddio = 2.0v, v in = 0v, 5.5v, t a = +25c -25 +25 a input capacitance 10 pf digmicclk (input) input high voltage v ih 0.65 x v avdd v input low voltage v il 0.35 x v avdd v input hysteresis 100 mv input capacitance 10 pf digmicclk (output) output high voltage v oh i oh = 3ma v avdd - 0.4 v output low voltage v ol i ol = 3ma 0.4 v max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 26 input clock characteristics (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, av_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (notes 2, 10) parameter symbol conditions min typ max units input clock characteristics mclk input frequency f mclk f s = 8khz, voice mode flters (mode = 0) 2.048 60 mhz f s = 48khz, music mode flters (mode = 1) 10 60 f s = 96khz, music mode flters (mode = 1) 12.288 60 mclk input duty cycle psclk = 01 40 50 60 % psclk = 10 or 11 30 70 maximum mclk input jitter 1 ns lrclk sample rate (note 12) f lrclk dhf = 0 8 48 khz dhf = 1 48 96 dai lrclk average frequency error (note 13) freq = 0x8 to 0xf 0 0 % freq = 0x0 -0.025 +0.025 pll lock time 2 7 ms maximum lrclk input jitter to maintain pll lock 100 ns soft-start/stop time 10 ms max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 27 digital audio interface timing characteristics (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units digital audio interface timing characteristics bclk cycle time t bclk slave mode 80 ns bclk high time t bclkh slave mode 20 ns bclk low time t bclkl slave mode 20 ns bclk or lrclk rise and fall time t r , t f master mode, c l = 15pf 5 ns sdin to bclk setup time t setup 20 ns lrclk to bclk setup time t syncset slave mode 20 ns sdin to bclk hold time t hold 20 ns lrclk to bclk hold time t synchold slave mode 20 ns minimum delay time from lsb bclk falling edge to high- impedance state t hizout master mode tdm = 1 20 ns tdm = 1, fsw = 1 20 tdm = 1, fsw = 0 20 tdm = 0, dly = 1 20 lrclk rising edge to sdout msb delay t synctx c = 30pf, tdm = 1, fsw = 1 40 ns bclk to sdout delay t clktx c = 30pf tdm = 1, bclk rising edge 50 ns tdm = 0 50 delay time from bclk to lrclk t clksync master mode tdm = 1 -15 +15 ns tdm = 0 0.8 x t bclk max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 28 figure 1. i 2 s audio interface timing diagrams (tdm = 0) figure 2. tdm audio interface short mode timing diagram (tdm = 1, bci = 1) t r t clktx t setup t hold t bclk t bclkh t bclkl msb lsb lsb bclk (output) lrclk (output) sdout (output) sdin (input) bclk (input) lrclk (input) sdout (output) sdin (input) master mode t setup t hold msb msb lsb lsb hi-z sla ve mode hi-z msb t clksync t f t hizout t clktx t syncset t hizout lrclk (output) bclk (output) tdm shor t mode timing (f sw = 0) tdm long mode timing (f sw = 1) sdout (output) sdin (input) lrclk (output) bclk (output) sdout (output) sdin (input) lrclk (output) bclk (output) sdout (output) sdin (input) lrclk (output) bclk (output) sdout (output) sdin (input) t clktx t hizout t hi-zout hi-z lsb t hold t setup t hold t setup t hold t setup lsb msb hi-z lsb msb msb lsb msb t hi-zout hi-z lsb msb lsb msb t clksync t r t f t f t r t clktx t hizout hi-z lsb t hold t setup lsb t synchold msb msb t bclkh t bclkl t bclk t bclkh t bclkl t bclk t syncset master mode sla ve mode t clksync t endsync t synctx t synctx t clksync t clktx t clktx sla ve mode sla ve mode max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 29 i 2 c timing characteristics (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (rhp) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) figure 3. i 2 c interface timing diagram parameter symbol conditions min typ max units i 2 c timing characteristics serial clock frequency f scl guaranteed by scl pulse width low and high 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd,sta 0.6 s scl pulse-width low t low 1.3 s scl pulse-width high t high 0.6 s setup time for a repeated start condition t su,sta 0.6 s data hold time t hd,dat r pu = 475 , c b = 100pf, 400pf 0 900 ns transmitting 0 900 receiving 0 data setup time t su,dat 100 ns sda and scl receiving rise time t r (note 14) 20 + 0.1 x c b 300 ns sda and scl receiving fall time t f (note 14) 20 + 0.1 x c b 300 ns sda transmitting fall time t f r pu = 475 , c b = 100pf to 400pf (note 14) 20 + 0.1 x c b 250 ns setup time for stop condition t su,sto 0.6 s bus capacitance c b guaranteed by sda transmitting fall time 400 pf pulse width of suppressed spike t sp 0 50 ns scl sda t r t f t buf st ar t condition st op condition repea ted st ar t condition st ar t condition t su,st o t hd,st a t su,st a t hd,da t t su,da t t low t high t hd,st a t sp max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 30 digital microphone timing characteristics (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) connected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) note 2: the max98090 is 100% production tested at t a =+25c. specifications over temperature limits are guaranteed by design. note 3: bias derived from a bandgap reference (bias_mode = 1). note 4: analog supply current = avdd + hpvdd, speaker supply current = spklvdd + spkrvdd, and digital supply current = dvdd + dvddio. note 5: dynamic range measurements are performed with the eiaj method (a -60dbfs output signal at 1khz, a-weighted and nor - malized to 0dbfs; f = 20hz C 20khz). note 6: gain measured relative to the 0db setting. note 7: performance measured using dac inputs, unless otherwise stated. note 8: full-scale analog output with 0db of programmable gain, and a 0dbfs dac input amplitude, a 1v rms differential analog input amplitude, or a 0.5v rms single-ended analog input amplitude. note 9: performance measured using an analog input to amplifier output path. note 10: digital filter performance is invariant over temperature and production tested at t a = +25c. note 11: the filter specification is accurate only for synchronous clocking modes (integer mclk to lrclk ratio). note 12: f lrclk may be any rate in the indicated range. asynchronous and non-integer f mclk /f lrclk ratios can exhibit some full- scale performance degradation compared to synchronous integer ratios. note 13: in master-mode operation, the accuracy of the mclk input proportionally determines the accuracy of the sample clock rate. note 14: c b is in pf. figure 4. digital microphone timing diagram parameter symbol conditions min typ max units digital microphone timing characteristics digmicclk frequency f digmicclk micclk = 000 f pclk /2 mhz micclk = 001 f pclk /3 micclk = 010 f pclk /4 micclk = 011 f pclk /5 micclk = 100 f pclk /6 micclk = 101 f pclk /8 digmicdata to digmicclk setup time t su,mic either clock edge 20 ns digmicdata to digmicclk hold time t hd,mic either clock edge 0 ns 1/ f mi cc lk t hd,mic t su,mic t hd,mic t su,mic left digmicclk digmicda ta right left right max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 31 quiescent power consumption (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v, slave mode operation.) device mode and configuration i avdd (ma) i hpvdd (ma) i dvdd (ma) i dvddio (ma) i spk_vdd (ma) power (mw) dynamic range (db) digital audio input to playback path to headphone output (music filters) stereo dac playback to headphone output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 32 1.39 1.28 1.04 0.02 0.00 6.05 102 stereo dac playback to headphone output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 32, low power mode 0.94 0.51 1.02 0.02 0.00 3.84 99 stereo dac playback to headphone output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 32, dynamic range control enabled 1.39 1.28 1.11 0.02 0.00 6.14 102 stereo dac playback to headphone output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 32, parametric equalizer enabled 1.39 1.28 1.65 0.02 0.00 6.78 102 stereo dac playback to headphone output f mclk = 12.288mhz, f s = 96khz, 20-bit, music flters, r load = 32 1.39 1.28 1.17 0.02 0.00 6.21 102 stereo dac playback to headphone output f mclk = 13mhz, f s = 44.1khz, 20-bit, music flters, r load = 32 1.40 1.29 1.00 0.02 0.00 6.03 102 stereo dac playback to headphone output f mclk = 13mhz, f s = 44.1khz, 20-bit, music flters, r load = 32, low power mode 0.96 0.51 1.00 0.02 0.00 3.85 99 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 32 quiescent power consumption (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v, slave mode operation.) device mode and configuration i avdd (ma) i hpvdd (ma) i dvdd (ma) i dvddio (ma) i spk_vdd (ma) power (mw) dynamic range (db) digital audio input to playback path to headphone output (voice filters) stereo dac playback to headphone output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32 1.35 1.28 0.89 0.02 0.00 5.81 101 stereo dac playback to headphone output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32, low power mode 0.91 0.51 0.89 0.02 0.00 3.62 98.5 mono dac playback to headphone output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32 0.78 0.69 0.82 0.02 0.00 3.64 101 mono dac playback to headphone output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32, low power mode 0.56 0.30 0.82 0.02 0.00 2.55 98.5 stereo dac playback to headphone output f mclk = 13mhz, f s = 16khz, 16-bit, voice flters, r load = 32 1.35 1.28 0.94 0.02 0.00 5.87 99 stereo dac playback to headphone output f mclk = 13mhz, f s = 16khz, 16-bit, voice flters, r load = 32, low power mode 0.91 0.50 0.94 0.02 0.00 3.68 97 digital audio input to playback path to speaker output stereo dac playback to speaker output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 8, l load = 68h 1.10 0.00 1.04 0.02 2.18 11.47 91 stereo dac playback to speaker output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 8, l load = 68h, low power mode 0.91 0.00 1.03 0.02 2.18 10.93 91 mono dac playback to speaker output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 8, l load = 68h 0.65 0.00 0.90 0.02 1.11 6.36 91 mono dac playback to speaker output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 8, l load = 68h, low power mode 0.51 0.00 0.90 0.02 1.11 6.09 91 stereo dac playback to speaker output f mclk = 12.288mhz, f s = 96khz, 20-bit, music flters, r load = 8, l load = 68h 1.21 0.00 1.17 0.02 2.18 11.61 91 stereo dac playback to speaker output f mclk = 13mhz, f s = 44.1khz, 20-bit, music flters, r load = 8, l load = 68h 1.21 0.00 1.06 0.02 2.18 11.50 91 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 33 quiescent power consumption (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v, slave mode operation.) device mode and configuration i avdd (ma) i hpvdd (ma) i dvdd (ma) i dvddio (ma) i spk_vdd (ma) power (mw) dynamic range (db) analog audio line input to digital record path output stereo differential line input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters 3.09 0.00 1.38 0.02 0.00 7.19 98 stereo differential line input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, low power mode 1.97 0.00 1.39 0.02 0.00 5.21 98 stereo differential line input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, digital biquad filter enabled 3.10 0.00 1.46 0.02 0.00 7.30 98 mono differential line input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters 1.86 0.00 1.10 0.02 0.00 4.65 98 stereo single-ended line input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters 3.19 0.00 1.35 0.02 0.00 7.33 97 stereo single-ended line input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, low power mode 2.02 0.00 1.35 0.02 0.00 5.24 97 stereo single-ended line input to record path f mclk = 13mhz, f s = 8khz, 16-bit, voice flters 2.90 0.00 0.90 0.02 0.00 6.28 98 stereo single-ended line input to record path f mclk = 13mhz, f s = 8khz, 16-bit, voice flters low power mode 1.73 0.00 0.90 0.02 0.00 4.20 97 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 34 quiescent power consumption (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v, slave mode operation.) device mode and configuration i avdd (ma) i hpvdd (ma) i dvdd (ma) i dvddio (ma) i spk_vdd (ma) power (mw) dynamic range (db) analog microphone input to digital record path output (music filters) stereo analog microphone input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters 3.50 0.00 1.36 0.02 0.00 7.88 97 stereo analog microphone input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, low power mode 2.22 0.00 1.38 0.02 0.00 5.65 97 mono analog microphone input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters 2.02 0.00 1.05 0.02 0.00 4.90 97 mono analog microphone input to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, low power mode 1.35 0.00 1.08 0.02 0.00 3.74 97 analog microphone input to digital record path output (voice filters) stereo analog microphone input to record path f mclk = 13mhz, f s = 8khz, 16-bit, voice flters 3.20 0.00 0.91 0.02 0.00 6.81 99 stereo analog microphone input to record path f mclk = 13mhz, f s = 8khz, 16-bit, voice flters low power mode 1.93 0.00 0.92 0.02 0.00 4.57 98 mono analog microphone input to record path f mclk = 13mhz, f s = 8khz, 16-bit, voice flters 1.87 0.00 0.82 0.02 0.00 4.35 99 mono analog microphone input to record path f mclk = 13mhz, f s = 8khz, 16-bit, voice flters low power mode 1.20 0.00 0.83 0.02 0.00 3.18 98 stereo analog microphone input to record path f mclk = 13mhz, f s = 16khz, 16-bit, voice flters 3.26 0.00 1.11 0.02 0.00 7.16 98 stereo analog microphone input to record path f mclk = 13mhz, f s = 16khz, 16-bit, voice flters low power mode 1.98 0.00 1.12 0.02 0.00 4.91 97 mono analog microphone input to record path f mclk = 13mhz, f s = 16khz, 16-bit, voice flters 1.90 0.00 0.94 0.02 0.00 4.54 98 mono analog microphone input to record path f mclk = 13mhz, f s = 16khz, 16-bit, voice flters low power mode 1.23 0.00 0.94 0.02 0.00 3.35 97 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 35 quiescent power consumption (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v, slave mode operation.) device mode and configuration i avdd (ma) i hpvdd (ma) i dvdd (ma) i dvddio (ma) i spk_vdd (ma) power (mw) dynamic range (db) analog audio input direct to digital record path output stereo differential input direct to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters 2.85 0.00 1.39 0.02 0.00 6.76 99 stereo differential input direct to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, low power mode 1.84 0.00 1.39 0.02 0.00 4.98 98 mono differential input direct to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters 1.61 0.00 1.08 0.02 0.00 4.20 99 mono differential input direct to record path f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, low power mode 1.09 0.00 1.09 0.02 0.00 3.29 98 analog audio input to analog audio output stereo single-ended line input to headphones (r load = 32) 1.12 2.42 0.00 0.00 0.00 6.34 99 mono single-ended line input to headphones (r load = 32) 0.72 1.57 0.00 0.00 0.00 3.41 99 stereo differential line input to headphones (r load = 32) 1.07 1.26 0.00 0.00 0.00 4.19 100 stereo differential line input to speaker output (r load = 8, l load = 68h) 0.36 0.00 0.00 0.00 2.08 8.34 91 mono differential line input to speaker output (r load = 8, l load = 68h) 0.31 0.00 0.00 0.00 1.04 4.42 91 stereo single-ended line input to line output (r load = 10k) 0.76 0.00 0.00 0.00 0.74 4.12 99 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 36 quiescent power consumption (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v, slave mode operation.) device mode and configuration i avdd (ma) i hpvdd (ma) i dvdd (ma) i dvddio (ma) i spk_vdd (ma) power (mw) dynamic range (db) full-duplex audio operation mono full duplex: analog microphone input to record path and dac playback to receiver output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32 2.67 0.00 0.95 0.02 0.73 8.61 rec: 99 pb: 100 mono full duplex: analog microphone input to record path and dac playback to receiver output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32, low power mode 1.94 0.00 0.95 0.02 0.73 7.31 rec: 99 pb: 98 mono full duplex: analog microphone input to record path and dac playback to headphone output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 32 2.69 0.69 1.22 0.02 0.00 7.51 rec: 97 pb: 102 mono full duplex: analog microphone input to record path and dac playback to headphone output f mclk = 12.288mhz, f s = 48khz, 20-bit, music flters, r load = 32, low power mode 1.80 0.30 1.24 0.02 0.00 5.26 rec: 97 pb: 99 mono full duplex: analog microphone input to record path and dac playback to headphone output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32 2.54 0.69 0.95 0.02 0.00 6.93 rec: 99 pb: 102 mono full duplex: analog microphone input to record path and dac playback to headphone output f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32, low power mode 1.66 0.30 0.96 0.02 0.00 4.67 rec: 99 pb: 99 stereo full duplex: analog microphone input to record path and dac playback to headphones f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32 4.44 1.28 1.14 0.02 0.00 11.54 rec: 99 pb: 102 stereo full duplex: analog microphone input to record path and dac playback to headphones f mclk = 13mhz, f s = 8khz, 16-bit, voice flters, r load = 32, low power mode 2.73 0.51 1.15 0.02 0.00 7.18 rec: 99 pb: 99 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 37 typical operating characteristics (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) analog microphone (input to adc output) total harmonic distortion plus noise vs. frequency (mic to adc) max98090 toc01 frequency (hz) thd+n ratio (db) 1k 100 10 10k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 8khz v in = 707mv rms a v_mic = 0db c in = 10f total harmonic distortion plus noise vs. frequency (mic to adc) max98090 toc04 frequency (hz) 10k 1k 100 0 10 100k thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 -100 f mclk = 12.288mhz f lrclk = 96khz v in = 707mv rms a v_mic = 0db c in = 10f total harmonic distortion plus noise vs. frequency (mic to adc) max98090 toc02 frequency (hz) 10k 1k 100 0 10 100k thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 f mclk = 13mhz f lrclk = 44.1khz v in = 707mv rms a v_mic = 0db c in = 10f total harmonic distortion plus noise vs. frequency (mic to adc) max98090 toc05 frequency (hz) thd+n ratio (db) 1k 100 10 10k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 8khz v in = 70.7mv rms a v_mic = +20db c in = 10f total harmonic distortion plus noise vs. frequency (mic to adc) max98090 toc03 frequency (hz) 10k 1k 100 0 10 100k thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 -100 f mclk = 12.288mhz f lrclk = 48khz v in = 707mv rms a v_mic = 0db c in = 10f total harmonic distortion plus noise vs. frequency (mic to adc) max98090 toc06 frequency (hz) thd+n ratio (db) 1k 100 10 10k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 8khz v in = 22.4mv rms a v_mic = +30db c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 38 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) gain vs. frequency (mic to adc) max98090 toc07 frequency (hz) normalized gain (db) 1k 100 10 10k 4 5 -5 -4 -3 -2 -1 0 1 2 3 f mclk = 13mhz f lrclk = 8khz v in = 707mv rms a v_mic = 0db c in = 10f inband output spectrum, -3dbfs input (mic to adc) max98089 toc10 frequency (hz) output amplitude (dbfs) -140 -120 -100 -80 -60 -40 -20 0 20 -160 0 500 1000 2000 1500 2500 3000 4000 3500 f mclk = 13mhz f lrclk = 8khz a v_mic = 0db c in = 10f common-mode rejection ratio vs. frequency (mic to adc) max98090 toc08 frequency (hz) 100 90 10 cmrr (db) 0 10 20 30 40 50 60 70 80 100k 10k 1k 100 f mclk = 12.288mhz f lrclk = 48khz c in = 10f a v_mic = +20db a v_mic = +30db a v_mic = +0db inband output spectrum, -60dbfs input (mic to adc) max98090 toc11 frequency (hz) output amplitude (dbfs) -140 -120 -100 -80 -60 -40 -20 0 20 -160 0 500 1000 2000 1500 2500 3000 4000 3500 f mclk = 13mhz f lrclk = 8khz a v_mic = 0db c in = 10f power-supply rejection ratio vs. frequency (mic to adc) max98090 toc09 frequency (hz) 100 90 10 psrr (db) 0 10 20 30 40 50 60 70 80 100k 10k 1k 100 f mclk = 12.288mhz f lrclk = 48khz v ripple = 100mv p-p c in = 10f inband output spectrum, -3dbfs input (mic to adc) max98090 toc12 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 44.1khz a v_mic = 0db c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 39 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) inband output spectrum, -60dbfs input (mic to adc) max98090 toc13 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 44.1khz a v_mic = 0db c in = 10f inband output spectrum, -3dbfs input (mic to adc) max98090 toc14 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz a v_mic = 0db c in = 10f inband output spectrum, -60dbfs input (mic to adc) max98090 toc15 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz a v_mic = 0db c in = 10f inband output spectrum, -60dbfs input (mic to adc) max98090 toc17 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 96khz a v_mic = 0db c in = 10f inband output spectrum, -3dbfs input (mic to adc) max98090 toc16 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 96khz a v_mic = 0db c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 40 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) digital microphone input to record path output inband output spectrum, -26dbfs input (digital mic to record path) max98090 toc20 frequency (hz) output amplitude (dbfs) 500 1000 2000 3000 4000 1500 2500 3500 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 8khz f dmicclk = 3.25mhz a v_dmic = 0db inband output spectrum, -60dbfs input (digital mic to record path) max98090 toc21 frequency (hz) output amplitude (dbfs) 500 1000 2000 3000 4000 1500 2500 3500 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 8khz f dmicclk = 3.25mhz a v_dmic = 0db inband output spectrum, -10dbfs input (digital mic to record path) max98090 toc23 frequency (hz) output amplitude (dbfs) -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 16khz f dmicclk = 3.25mhz a v_dmic = 0db 1k 2k 4k 6k 8k 3k 5k 7k 0 1k 100 10 10k total harmonic distortion plus noise vs. frequency (digital mic to record path) max98090 toc22 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 16khz f dmicclk = 3.25mhz a v_dmic = 0db v in = -26dbfs v in = -3dbfs 1k 100 10 10k total harmonic distortion plus noise vs. frequency (digital mic to record path) max98090 toc18 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 8khz f dmicclk = 3.25mhz a v_dmic = 0db v in = -26dbfs v in = -3dbfs inband output spectrum, -10dbfs input (digital mic to record path) max98090 toc19 frequency (hz) output amplitude (dbfs) 500 1000 2000 3000 4000 1500 2500 3500 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 8khz f dmicclk = 3.25mhz a v_dmic = 0db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 41 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (digital mic to record path) max98090 toc26 frequency (hz) thd+n ratio (db) 0 -20 -40 -60 -80 -100 -120 f mclk = 12.288mhz f lrclk = 48khz f dmicclk = 3.072mhz a v_dmic = 0db v in = -3dbfs v in = -26dbfs inband output spectrum, -10dbfs input (digital mic to record path) max98090 toc27 frequency (hz) output amplitude (dbfs) 15k 10k 5k 0 20k -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz f dmicclck = 3.072mhz a v_dmic = 0db inband output spectrum, -60dbfs input (digital mic to record path) max98090 toc29 frequency (hz) output amplitude (dbfs) 15k 10k 5k 0 20k -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz f dmicclck = 3.072mhz a v_dmic = 0db inband output spectrum, -26dbfs input (digital mic to record path) max98090 toc28 frequency (hz) output amplitude (dbfs) 15k 10k 5k 0 20k -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz f dmicclck = 3.072mhz a v_dmic = 0db inband output spectrum, -60dbfs input (digital mic to record path) max98090 toc25 frequency (hz) output amplitude (dbfs) 1k 2k 4k 6k 8k 3k 5k 7k 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 16khz f dmicclk = 3.25mhz a v_dmic = 0db inband output spectrum, -26dbfs input (digital mic to record path) max98090 toc24 frequency (hz) output amplitude (dbfs) -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 16khz f dmicclk = 3.25mhz a v_dmic = 0db 1k 2k 4k 6k 8k 3k 5k 7k 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 42 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) line input to adc output 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (line to adc) max98090 toc31 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz a v_linepga = 0db v in_se = 354mv rms v in_diff = 707mv rms c in = 10f single-ended differential 10k 1k 100 10 100k power-supply rejection ratio vs. frequency (line to adc) max98090 toc34 frequency (hz) f mclk = 12.288mhz f lrclk = 48khz v in single-ended v ripple = 100mv p-p c in = 10f vcm_mode = 0 100 90 psrr (db) 0 10 20 30 40 50 60 70 80 vcm_mode = 1 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (line to adc) max98090 toc32 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz a v_linepga = +20db v in_se = 35.4mv rms v in_diff = 70.7mv rms c in = 10f single-ended differential -120 -100 -80 -60 -40 -20 10k 1k 100 10 100k crosstalk vs. frequency (line to adc) max98090 toc35 frequency (hz) f mclk = 12.288mhz f lrclk = 48khz v in = 0.5mv rms a v_linepre = 0db c in = 10f differential 0 crosstalk (db) -140 single-ended 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (line to adc) max98090 toc33 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz a v_linepga = -9db v in_se = 2v rms c in = 10f single-ended differential 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (line to adc) max98090 toc30 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz a v_linepga = -6db v in_se = 0.5v rms v in_diff = 1v rms c in = 10f differential single-ended max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 43 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) direct analog input to adc mixer inband output spectrum vs. frequency,-3dbfs input (line to adc) max98090 toc36 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz v in = 354mv rms_se a v_pre = 0db c in = 10f inband output spectrum vs. frequency, -60dbfs input (line to adc) max98090 toc37 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz v in = 0.5mv rms_se a v_pre = 0db c in = 10f frequency (hz) 1k 100k crosstalk (db) 10k 100 10 crosstalk vs. frequency (input direct to adc mixer) max98090 toc40 -100 -80 -60 -40 -20 0 -140 -120 f mclk = 12.288mhz f lrclk = 48khz v in = 0.5v rms c in = 10f right to left left to right 10k 1k 100 100k total harmonic distortion plus noise vs. frequency (input direct to adc mixer) max98090 toc38 frequency (hz) thd+n ratio (db) 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz v in = 707mv rms c in = 10f 100 90 0 10 20 30 40 50 60 70 80 frequency (hz) 1k 100k psrr (db) 10k 100 10 power-supply rejection ratio vs. frequency (input direct to adc mixer) max98090 toc39 mclk = 12.288mhz lrclk = 48khz v ripple = 100mv p-p c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 44 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) adc output to dac input loop through 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (line to adc to dac to headphone) max98090 toc43 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 44.1khz a v_total = 0db r hp = 32 i c in = 10f p out = 20mw p out = 10mw 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (line to adc to dac to headphone) max98090 toc44 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz a v_total = 0db r hp = 32 i c in = 10f p out = 20mw p out = 10mw inband output spectrum, -3dbfs input (line to adc to dac to headphone) max98090 toc45 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 44.1khz a v_total = 0db r hp = 32 i c in = 10f inband output spectrum, -3dbfs (input direct to adc mixer) max98090 toc41 frequency (khz) amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz v in = 0.707v rms c in = 10f inband output spectrum, -60dbfs (input direct to adc mixer) max98090 toc42 frequency (khz) amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz v in = 1mv rms c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 45 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) dac input to receiver output max98090 toc46 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 13mhz f lrclk = 44.1khz a v_total = 0db r hp = 32 i c in = 10f inband output spectrum, -60dbfs input (line to adc to dac to headphone) max98090 toc47 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz a v_total = 0db r hp = 32 i c in = 10f inband output spectrum, -3dbfs input (line to adc to dac to headphone) max98090 toc48 frequency (khz) output amplitude (dbfs) 15 10 5 02 0 -140 -120 -100 -80 -60 -40 -20 0 20 -160 f mclk = 12.288mhz f lrclk = 48khz a v_total = 0db r hp = 32 i c in = 10f inband output spectrum, -60dbfs input (line to adc to dac to headphone) total harmonic distortion plus noise vs. output power (dac to receiver) max98090 toc49 output power (w) thd+n ratio (db) 0.10 0.08 0.06 0.04 0.02 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 0.12 vcm_mode = 0 f mclk = 13mhz f lrclk = 8khz a v_rec = +8db r rec = 32i f in = 100hz f in = 1000hz f in = 3000hz total harmonic distortion vs. output power (dac to receiver) max98090 toc50 output power (w) thd+n ratio (db) 0.10 0.08 0.06 0.04 0.02 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 0.12 vcm_mode = 1 f mclk = 13mhz f lrclk = 8khz a v_rec = +8db r rec = 32i f in = 100hz f in = 1000hz f in = 3000hz total harmonic distortion vs. frequency (dac to receiver) max98090 toc51 frequency (hz) thd+n ratio (db) 1k 100 10 10k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 8khz a v_rec = +8db r rec = 32i p out = 25mw p out = 50mw max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 46 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) output power vs. speaker supply voltage (dac to receiver) max98090 toc52 speaker supply voltage (v) receiver output power (mw) 5.0 4.5 4.0 3.5 3.0 25 50 75 100 125 150 0 2.5 5.5 vcm_mode = 0 vcm_mode = 1 f mclk = 13mhz f lrclk = 8khz a v_rec = +8db r rec = 32i power-supply rejection ratio vs. frequency (dac to receiver) max98090 toc55 frequency (hz) psrr (db) 10k 1k 100 10 100k 10 20 30 40 50 60 70 80 90 100 0 f mclk = 12.288mhz f lrclk = 48khz v ripple = 100mv p-p r rec = 32i other supplies spk_vdd gain vs. frequency (dac to receiver) max98090 toc53 frequency (hz) normalized gain (db) 1k 100 10 10k -4 -3 -2 -1 0 1 2 3 4 5 -5 f mclk = 13mhz f lrclk = 8khz voice filter a v_rec = 0db r rec = 32i inband output spectrum, -3dbfs input (dac to receiver) max98090 toc56 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 8khz a v_rec = 0db r rec = 32i power consumption vs. output power (dac to receiver) max98090 toc54 temperature (nc) power consumption (mw) 120 100 80 60 40 20 40 80 120 160 200 0 0 140 f mclk = 13mhz f lrclk = 8khz vcm_mode = 1 thd+n 1% a v_rec = +8db r rec = 16i r rec = 32i inband output spectrum, -60dbfs input (dac to receiver) max98090 toc57 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 8khz a v_rec = 0db r hp = 32i max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 47 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) line input to receiver output total harmonic distortion plus noise vs. output power (line to receiver) max98090 toc58 output power (w) thd+n ratio (db) 0.10 0.08 0.06 0.04 0.02 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 0.12 differential input vcm_mode = 0 a v_linepga = 0db a v_rec = +8db r rec = 32i c in = 10f f in = 100hz f in = 1000hz f in = 6000hz gain vs. frequency (line to receiver) max98090 toc61 frequency (hz) normalized gain (db) 10k 1k 100 10 100k -4 -3 -2 -1 0 1 2 3 4 5 -5 differential input a v_total = 0db r rec = 32i c in = 10f total harmonic distortion plus noise vs. output power (line to receiver) max98090 toc59 output power (w) thd+n ratio (db) 0.10 0.08 0.06 0.04 0.02 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 0.12 differential input vcm_mode = 1 a v_linepga = 0db a v_rec = +8db r rec = 32i c in = 10f f in = 100hz f in = 1000hz f in = 6000hz total harmonic distortion plus noise vs. frequency (line to receiver) max98090 toc60 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 25mw p out = 80mw differential input vcm_mode = 0 a v_linepga = 0db a v_rec = +8db r rec = 32i c in = 10f power-supply rejection ratio vs. frequency (line to receiver) max98090 toc62 frequency (hz) psrr (db) 10k 1k 100 10 100k 20 40 60 80 100 120 0 other supplies spk_vdd differential input v ripple = 100mv p-p r rec = 32i c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 48 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) dac input to line output inband output spectrum, -3dbv input (line to receiver) max98090 toc63 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 differential input a v_linepga = 0db a v_rec = +8db r rec = 32i c in = 10f inband output spectrum, -3dbfs input (dac to line out) max98090 toc65 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 8khz a v_lout = +3db r lout = 10ki inband output spectrum, -60dbv input (line to receiver) max98090 toc64 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 differential input a v_linepga = 0db a v_rec = +6db r rec = 32i c in = 10f inband output spectrum, -60dbfs input (dac to line out) max98090 toc66 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 8khz a v_lout = +3db r lout = 10ki max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 49 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) line input to line output total harmonic distortion plus noise vs. output level (line in to line out) max98090 toc67 output level (v) thd+n ratio (db) 0.8 0.6 0.4 0.2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.0 a v_linepga = 0db a v_lout = +3db r lout = 10k i c in = 10f f in = 1000hz f in = 100hz f in = 6000hz inband output spectrum, -3dbv input (line in to line out) max98090 toc70 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 a v_linepga = 0db a v_lout = +3db r lout = 10ki c in = 10f total harmonic distortion plus noise vs. frequency (line in to line out) max98090 toc68 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v out = 0.707mv rms v out = 300mv rms a v_linepga = 0db a v_lout = +3db r lout = 10ki c in = 10f total harmonic distortion plus noise vs. frequency (line in to line out) max98090 toc69 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 differential line input single-ended line input v in = 2v rms a v_external = -9db a v_lout = +3db r lout = 10ki c in = 10f inband output spectrum, -60dbv input (line in to line out) max98090 toc71 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 a v_linepga = 0db a v_lout = +3db r lout = 10ki c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 50 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) dac input to speaker output total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc72 output power (w) thd+n ratio (db) 1.5 1.0 0.5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 2.0 v spk_vdd = 5v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h f in = 100hz f in = 1000hz f in = 6000hz total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc73 output power (w) thd+n ratio (db) 1.0 1.2 0.8 0.6 0.2 0.4 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.4 v spk_vdd = 4.2v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h f in = 100hz f in = 1000hz f in = 6000hz total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc74 output power (w) thd+n ratio (db) 1.0 0.8 0.6 0.2 0.4 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.2 v spk_vdd = 3.7v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h f in = 100hz f in = 1000hz f in = 6000hz total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc76 output power (w) thd+n ratio (db) 3.0 2.5 1.5 2.0 0.5 1.0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 3.5 v spk_vdd = 5v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h f in = 100hz f in = 1000hz f in = 6000hz total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc77 output power (w) thd+n ratio (db) 1.5 2.0 0.5 1.0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 2.5 v spk_vdd = 4.2v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h f in = 100hz f in = 1000hz f in = 6000hz total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc75 output power (w) thd+n ratio (db) 0.7 0.6 0.4 0.5 0.1 0.2 0.3 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 0.8 v spk_vdd = 3v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h f in = 100hz f in = 1000hz f in = 6000hz max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 51 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc79 output power (w) thd+n ratio (db) 0.8 1.0 1.2 0.4 0.2 0.6 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.4 v spk_vdd = 3v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h f in = 100hz f in = 1000hz f in = 6000hz max98090 toc80 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 1.00w p out = 0.25w total harmonic distortion plus noise vs. frequency (dac to speaker) v spk_vdd = 5v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h total harmonic distortion plus noise vs. output power (dac to speaker) max98090 toc78 output power (w) thd+n ratio (db) 1.25 1.50 1.75 0.75 0.50 0.25 1.00 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 2.00 v spk_vdd = 3.7v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h f in = 100hz f in = 1000hz f in = 6000hz max98090 toc82 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 0.60w p out = 0.15w total harmonic distortion plus noise vs. frequency (dac to speaker) v spk_vdd = 3.7v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h max98090 toc83 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 2.00w p out = 0.50w total harmonic distortion plus noise vs. frequency (dac to speaker) v spk_vdd = 5v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h max98090 toc81 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 0.76w p out = 0.20w total harmonic distortion plus noise vs. frequency (dac to speaker) v spk_vdd = 4.2v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 52 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (dac to speaker) max98090 toc84 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v spk_vdd = 4.2v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h p out = 1.50mw p out = 0.40mw 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (dac to speaker) max98090 toc85 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v spk_vdd = 3.7v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h p out = 1.20mw p out = 0.30mw output power vs. supply voltage (dac to speaker) max98090 toc86 supply voltage (v) output power per channel (mw) 5.0 4.5 4.0 3.5 3.0 500 1000 1500 2000 2500 0 2.5 5.5 f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 8 i + 68h wlp package thd+n = 10% thd+n = 1% frequency (hz) 10k 1k 100 10 100k gain vs. frequency (dac to speaker) max98090 toc88 normalized gain (db) -4 -3 -2 -1 0 1 2 3 4 5 -5 f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = 0db z spk = 8i + 68h 3.0 2.5 2.0 1.5 1.0 0.5 efficiency vs. output power (dac to speaker) max98090 toc89 output power per channel (w) efficiency (%) 10 20 30 40 50 60 70 80 90 100 0 0 3.5 v spk_vdd = 5v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4i + 33h z spk = 8i + 68h output power vs. supply voltage (dac to speaker) max98090 toc87 supply voltage (v) output power per channel (mw) 5.0 4.5 4.0 3.5 3.0 2.5 5.5 500 1000 1500 2000 2500 3000 3500 4000 4500 0 f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4 i + 33h wlp package thd+n = 10% thd+n = 1% max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 53 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 efficiency vs. output power (dac to speaker) max98090 toc91 output power per channel (w) efficiency (%) 10 20 30 40 50 60 70 80 90 100 0 0 2.00 v spk_vdd = 3.7v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4i + 33h z spk = 8i + 68h supply current vs. supply voltage (dac to speaker) max98090 toc92 supply voltage (v) 2.5 5.5 supply current (ma) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5.0 4.5 4.0 3.5 3.0 f mclk = 12.288mhz f lrclk = 48khz z spk = 8 i + 68h 2.5 2.0 1.5 1.0 0.5 efficiency vs. output power (dac to speaker) max98090 toc90 output power per channel (w) efficiency (%) 10 20 30 40 50 60 70 80 90 100 0 0 3.0 v spk_vdd = 4.2v f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = +8db z spk = 4i + 33h z spk = 8i + 68h crosstalk vs. frequency (dac to speaker) max98090 toc94 0 -120 frequency (hz) 10k 1k 100 10 100k crosstalk (db) -100 -80 -60 -40 -20 right to left left to right f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = 0db z spk = 8i + 68h inband output spectrum, -3dbfs input (dac to speaker) max98090 toc95 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 0 -20 20 -160 -140 02 0 f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = -6db z spk = 8i + 68h power-supply rejection ratio vs. frequency (dac to speaker) max98090 toc93 120 0 frequency (hz) 10k 1k 100 10 100k psrr (db) 20 40 60 80 100 spk_vdd other supplies f mclk = 12.288mhz f lrclk = 48khz v ripple = 100mv p-p z spk = 8i + 68h max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 54 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) inband output spectrum, -60dbfs input (dac to speaker) max98090 toc96 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 0 -20 20 -160 -140 02 0 f mclk = 12.288mhz f lrclk = 48khz a v_spkpga = -6db z spk = 8i + 68h inband output spectrum, -3dbfs input (dac to speaker) max98090 toc97 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 0 -20 20 -160 -140 02 0 f mclk = 13mhz f lrclk = 44.1khz a v_spkpga = -6db z spk = 8i + 68h inband output spectrum, -60dbfs input (dac to speaker) max98090 toc98 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 0 -20 20 -160 -140 02 0 f mclk = 13mhz f lrclk = 44.1khz a v_spkpga = -6db z spk = 8i + 68h inband output spectrum, -60dbfs input (dac to speaker) max98090 toc100 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 0 -20 20 -160 -140 02 0 f mclk = 12.88mhz f lrclk = 48khz a v_spkpga = -6db z spk = 4i + 33h wideband frequency spectrum (dac to speaker) max98090 toc101 frequency (mhz) amplitude (dbv) 10 1 -100 -80 -60 -40 -20 0 -120 0.1 100 f mclk = 12.88mhz f lrclk = 48khz a v_spkpga = 0db z spk = 8w + 68h inband output spectrum, -3dbfs input (dac to speaker) max98090 toc99 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 0 -20 20 -160 -140 02 0 f mclk = 12.88mhz f lrclk = 48khz a v_spkpga = -6db z spk = 4i + 33h max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 55 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) line input to speaker output 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (line to speaker) max98090 toc103 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 a v_linepga = 0db a v_spkpga = +8db z spk = 8 i + 68h c in = 10f p out = 0.60w p out = 0.15w gain vs. frequency (line to speaker) max98090 toc104 frequency (hz) normalized gain (db) 10k 1k 100 -4 -3 -2 -1 0 1 2 3 4 5 -5 10 100k a v_linepga = 0db a v_spkpga = +8db z spk = 8 i + 68h c in = 10f total harmonic distortion plus noise vs. output power (line to speaker) max98090 toc102 output power (w) thd+n ratio (db) 0.2 0.4 0.6 0.8 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.0 a v_linepga = 0db a v_spkpga = +8db z spk = 8 i + 68h c in = 10f f = 6000hz f = 100hz f = 1000hz crosstalk vs. frequency (line to speaker) max98090 toc106 frequency (hz) crosstalk (db) -100 -80 -60 -40 -20 0 -120 1k 100k 10k 100 10 a v_linepga = 0db a v_spkpga = 0db z spk = 8 i + 68h c in = 10f left to right right to left inband output spectrum, -3dbv input (line to speaker) max98090 toc107 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 -20 0 -140 02 0 a v_linepga = -6db a v_spkpga = 0db z spk = 8i + 68h c in = 10f 100 90 0 10 20 30 40 50 60 70 80 frequency (hz) 1k 100k psrr (db) 10k 100 10 power-supply rejection ratio vs. frequency (line to speaker) max98090 toc105 v ripple = 100mv p-p z spk = 8 i + 68h c in = 10f other supplies spk_vdd max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 56 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) inband output spectrum, -60dbv input (line to speaker) max98090 toc108 frequency (khz) output amplitude (dbv) 15 10 5 -120 -100 -80 -60 -40 -20 0 -140 02 0 a v_linepga = -6db a v_spkpga = 0db z spk = 8i + 68h c in = 10f total harmonic distortion plus noise vs. output power (dac to headphone) max98090 toc109 thd+n ratio (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -100 -90 f mclk = 13mhz f lrclk = 8khz a v_hp = +3db r hp = 32i output power (w) 0.04 0.03 0.02 0.01 0 0.05 f = 100hz f = 1000hz f = 3000hz total harmonic distortion plus noise vs. output power (dac to headphone) max98090 toc110 thd+n ratio (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -100 -90 f mclk = 13mhz f lrclk = 44.1khz a v_hp = +3db r hp = 32i output power (w) 0.04 0.03 0.02 0.01 0 0.05 f = 100hz f = 6000hz f = 1000hz total harmonic distortion plus noise vs. output power (dac to headphone) max98090 toc112 thd+n ratio (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -100 -90 f mclk = 12.288mhz f lrclk = 96khz a v_hp = +3db r hp = 32i output power (w) 0.04 0.03 0.02 0.01 0 0.05 f = 1000hz f = 100hz f = 6000hz total harmonic distortion plus noise vs. output power (dac to headphone) max98090 toc113 thd+n ratio (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -100 -90 f mclk = 12.288mhz f lrclk = 48khz a v_hp = +3db r hp = 16i output power (w) 0.06 0.05 0.04 0.03 0.02 0.01 0 0.07 f = 1000hz f = 100hz f = 6000hz total harmonic distortion plus noise vs. output power (dac to headphone) max98090 toc111 thd+n ratio (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -100 -90 f mclk = 12.288mhz f lrclk = 48khz a v_hp = +3db r hp = 32i output power (w) 0.04 0.03 0.02 0.01 0 0.05 f = 6000hz f = 1000hz f = 100hz max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 57 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) total harmonic distortion plus noise vs. output power (dac to headphone) max98090 toc115 thd+n ratio (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -100 -90 f mclk = 12.288mhz f lrclk = 48khz low power mode a v_hp = +3db r hp = 32i output power (w) 0.04 0.03 0.02 0.01 0 0.05 f = 1000hz f = 6000hz f = 100hz 1k 100 10 10k total harmonic distortion plus noise vs. frequency (dac to headphone) max98090 toc116 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 8khz a v_hp = +3db r hp = 32 i p out = 0.01w p out = 0.02w total harmonic distortion plus noise vs. output power (dac to headphone) max98090 toc114 thd+n ratio (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -100 -90 f mclk = 12.288mhz f lrclk = 48khz low power mode a v_hp = +3db r hp = 16i output power (w) 0.06 0.05 0.04 0.03 0.02 0.01 0 0.07 f = 6000hz f = 1000hz f = 100hz 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (dac to headphone) max98090 toc118 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz a v_hp = +3db r hp = 32 i p out = 0.02w p out = 0.01w 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (dac to headphone) max98090 toc119 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 96khz a v_hp = +3db r hp = 32 i p out = 0.02w p out = 0.01w 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (dac to headphone) max98090 toc117 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 13mhz f lrclk = 44.1khz a v_hp = +3db r hp = 32 i p out = 0.02w p out = 0.01w max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 58 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency (dac to headphone) max98090 toc120 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f mclk = 12.288mhz f lrclk = 48khz a v_hp = +3db r hp = 16 i p out = 0.01w p out = 0.025w max98090 toc121 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 0.025w p out = 0.01w total harmonic distortion plus noise vs. frequency (dac to headphone) f mclk = 12.288mhz f lrclk = 48khz low power mode a v_hp = +3db r hp = 16 i max98090 toc122 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 0.02w p out = 0.01w total harmonic distortion plus noise vs. frequency (dac to headphone) f mclk = 12.288mhz f lrclk = 48khz low power mode a v_hp = +3db r hp = 32 i gain vs. frequency (line to headphone) max98090 toc124 frequency (hz) normalized gain (db) 10k 1k 100 10 100k -4 -3 -2 -1 0 1 2 3 4 5 -5 f mclk = 12.288mhz f lrclk = 48khz a v_hp = 0db r hp = 32i power consumption vs. output power (dac to headphone) max98090 toc125 output power per channel (mw) current consumption (ma) 10 1 0.1 100 f mclk = 12.288mhz f lrclk = 48khz a v_hp = +3db 20 40 60 80 100 120 0 r hp = 32 i r hp = 16 i gain vs. frequency (dac to headphone) max98090 toc123 frequency (hz) normalized gain (db) 1k 100 10 10k -4 -3 -2 -1 0 1 2 3 4 5 -5 f mclk = 13mhz f lrclk = 8khz a v_hp = 0db r hp = 32 i max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 59 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) power-supply rejection ratio vs. frequency (dac to headphones) max98090 toc127 frequency (hz) psrr (db) f mclk = 12.288mhz f lrclk = 48khz v ripple = 100mv p-p r hp = 32 i 20 40 60 80 100 120 0 other supplies spk_vdd 10k 1k 100 10 100k power-supply rejection ratio vs. frequency (dac to headphones) max98090 toc128 frequency (hz) psrr (db) f mclk = 12.288mhz f lrclk = 48khz low power mode v ripple = 100mv p-p r hp = 32 i 20 40 60 80 100 120 0 other supplies spk_vdd 10k 1k 100 10 100k power consumption vs. output power (dac to headphone) max98090 toc126 output power per channel (mw) current consumption (ma) 10 1 0.1 100 f mclk = 12.288mhz f lrclk = 48khz low power mode a v_hp = +3db 20 40 60 80 100 120 0 r hp = 32i r hp = 16i inband output spectrum, -3dbfs input (dac to headphone) max98090 toc130 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 8khz a v_hp = 0db r hp = 32i inband output spectrum, -60dbfs input (dac to headphone) max98090 toc131 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 8khz a v_hp = 0db r hp = 32i crosstalk vs. frequency (dac to headphone) max98090 toc129 frequency (hz) crosstalk (db) 10k 1k 100 10 100k -4 -3 -2 -1 0 1 2 3 4 5 -5 f mclk = 12.288mhz f lrclk = 48khz a v_hp = 0db r hp = 32i right to left left to right max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 60 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) inband output spectrum, -3dbfs input (dac to headphone) max98090 toc132 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 44.1khz a v_hp = 0db r hp = 32i inband output spectrum, -60dbfs input (dac to headphone) max98090 toc133 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 13mhz f lrclk = 44.1khz a v_hp = 0db r hp = 32i inband output spectrum, -60dbfs input (dac to headphone) max98090 toc134 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 48khz a v_hp = 0db r hp = 32i inband output spectrum, -3dbfs input (dac to headphone) max98090 toc136 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 96khz a v_hp = 0db r hp = 32i inband output spectrum, -60dbfs input (dac to headphone) max98090 toc137 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 96khz a v_hp = 0db r hp = 32i inband output spectrum, -60dbfs input (dac to headphone) max98090 toc135 frequency (hz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 48khz a v_hp = 0db r hp = 32i max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 61 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) inband output spectrum, -60dbfs input (dac to headphone) max98090 toc139 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 48khz low power mode a v_hp = 0db r hp = 32i inband output spectrum, -3dbfs input (dac to headphone) max98090 toc138 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 48khz low power mode a v_hp = 0db r hp = 32i inband output spectrum, -3dbfs input (dac to headphone) max98090 toc140 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 48khz a v_hp = 0db r hp = 16i inband output spectrum, -60dbfs input (dac to headphone) max98090 toc141 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 f mclk = 12.288mhz f lrclk = 48khz a v_hp = 0db r hp = 16i max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 62 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) line input to headphone total harmonic distortion plus noise vs. output power (line to headphone) max98090 toc142 output power (w) thd+n ratio (db) 0.04 0.03 0.02 0.01 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -100 -110 0 0.05 a v_linepga = 0db a v_hp = +3db r hp = 32i c in = 10f f in = 100hz f in = 1000hz f in = 6000hz total harmonic distortion plus noise vs. frequency (line to headphone) max98090 toc143 frequency (hz) thd+n ratio (db) 10k 1k 100 10 100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 p out = 10mw p out = 20mw a v_linepga = 0db a v_hp = +8db r hp = 32i c in = 10f gain vs. frequency (line to headphone) max98090 toc144 frequency (hz) normalized gain (db) 10k 1k 100 10 100k -4 -3 -2 -1 0 1 2 3 4 5 -5 a v_linepga = 0db a v_hp = 0db r hp = 32i c in = 10f power-supply rejection ratio vs. frequency (line to headphones) max98090 toc145 frequency (hz) psrr (db) 10k 1k 100 10 100k 20 40 60 80 100 120 0 vcm_mode = 0 vcm_mode = 1 v ripple = 100mv p-p r hp = 32i c in = 10f max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 63 typical operating characteristics (continued) (v avdd = v hpvdd = v dvddio = 1.8v, v dvdd = 1.2v, v spklvdd = v spkrvdd = v spkvdd = 3.7v. receiver load (r rcv ) connected between rcvp/loutl and rcvn/loutr (linmod = 0). line output loads (r lout ) connected between from rcvp/loutl and rcvn/loutr to gnd (linmod = 1). headphone loads (r hp ) connected from hpl or hpr to gnd. speaker loads (z spk ) con - nected between spk_p and spk_n. r rcv = j , r lout = j , r hp = j , z spk = j . c ref = 2.2f, c bias = c micbias = 1f, c c1n-c1p = c cpvdd = c cpvss = 1f. a v_micpre_ = a v_micpga_ = a v_linepga_ = 0db, a v_adclvl = a v_adcgain = 0db, a v_daclvl = a v_dacgain = 0db, a v_mixgain = 0db, a v_rcv = a v_lout = a v_hp = a v_spk = 0db. f mclk = 12.288mhz, f lrclk = 48khz, mas = 0, 20-bit source data. t a = t min to t max unless otherwise noted. typical values are at t a = +25c.) (note 2) inband output spectrum, -3dbfs input (line to headphone) max98090 toc148 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 a v_linepga = 0db a v_hp = 0db r hp = 32i c in = 10f crosstalk vs. frequency (line to headphone) max98090 toc146 frequency (hz) crosstalk (db) 10k 1k 100 10 100k f mclk = 12.288mhz f lrclk = 48khz a v_hp = 0db r hp = 32i left to right right to left -100 -80 -60 -40 -20 0 -120 inband output spectrum, -60dbfs input (line to headphone) max98090 toc149 frequency (khz) output amplitude (dbv) 15 10 5 -140 -120 -100 -80 -60 -40 -20 0 20 -160 02 0 a v_linepga = 0db a v_hp = 0db r hp = 32i c in = 10f common-mode rejection ratio vs. frequency (line to headphone) max98090 toc147 frequency (hz) cmrr (dbv) 10k 1k 100 10 100k 10 20 30 40 50 60 70 80 90 100 0 r hp = 32i c in = 10f a v_hp = 0db a v_linepga = 0db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 64 bump/pin confgurations max98090 tqfn (5mm x 5mm x 0.75mm) top view 35 36 34 33 12 11 13 cpvss hpl hpsn s hpr jacksn s 14 hpgnd dvdd agnd bias dvddi o dgnd sdin ref micbias 12 irq 45 67 27 28 29 30 26 24 23 22 mclk scl in2/dmc spklgnd spklp spkln cpvd d avd d 3 25 37 sda spklvdd 38 39 40 hpvdd c1p c1n spkrvdd spkrp spkrn + bclk 32 15 in1/dmd lrclk 31 16 17 18 19 20 in3 rcvp /l outl rcvn /l outr spkrgn d in4 89 10 21 sdout max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 65 bump/pin confgurations (continued) top view (bump side down) max98090 a b c d wlp (3.15mm x 3.15 mm, 0.4 pitch) e f g 1234567 + rcvn/lout r rcvp/loutl hpr hpl cpvdd hpgnd in2/dmc micbias agnd av dd dvdd dgnd in3 in4 ref bias dvddi o sdout jacksns n.c. n.c. sdin lrclk bclk spkvdd in5 in6 n.c. irqb mclk spkvdd n.c. scl n.c. c1p hpvdd spkrgnd in1/ dmd spklgnd spkln spklp spkrn spkrp n.c. n.c. hpsns sda c1n cpvss max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 66 bump/pin descriptions pin bump max98090 function tqfn wlp 1 g1 hpgnd headphone ground 2 g2 cpvss inverting charge-pump output. bypass to hpgnd with a 1f ceramic capacitor . 3 f1 cpvdd noninverting charge-pump output. bypass to hpgnd with a 1f ceramic capacitor . 4 e1 hpl left-channel headphone output 5 d2 hpsns headphone amplifer ground sense. connect to the headphone jack ground terminal or connect to ground. 6 d1 hpr right-channel headphone output 7 b5 jacksns jack detection input. connect to the microphone terminal of the headset jack to detect jack activity. 8 c1 rcvp/loutl positive earpiece amplifer output/left line output 9 b1 rcvn/loutr negative earpiece amplifer output/right line output 10 a1 spkrgnd right speaker amplifer ground 11 a2 spkrn negative right-channel class d speaker output 12 a3 spkrp positive right-channel class d speaker output 13 spkrvdd right speaker power supply. bypass to spkrgnd with a 1f capacitor. 14 spklvdd left speaker and microphone bias power supply. bypass to spklgnd with a 1f capacitor. 15 a5 spkln negative left-channel class d speaker output 16 a4 spklp positive left-channel class d speaker output 17 a6 spklgnd left speaker amplifer ground. 18 b7 in2/dmc positive differential microphone 1 input or single-ended line input 2. ac-couple with a series 1f capacitor. can be retasked as a digital microphone clock output. 19 a7 in1/dmd negative differential microphone 1 input or single-ended line input 1. ac-couple with a series 1f capacitor. can be retasked as a digital microphone data input. 20 b6 in3 negative differential microphone 2 input or single-ended line input 3. ac-couple with a series 1f capacitor. 21 c6 in4 positive differential microphone 2 input or single-ended line input 4. ac-couple with a series 1f capacitor. 22 c7 micbias low-noise bias voltage. the bias voltage is programmable. an external resistor in the 2.2k? to 1k? range should be used to set the microphone current. 23 d6 ref converter reference. bypass to agnd with a 2.2f capacitor. 24 e6 bias common-mode reference voltage. bypass to agnd with a 1f capacitor. 25 d7 agnd analog ground. 26 e7 avdd analog power supply. bypass to agnd with a 1f capacitor. 27 f7 dvdd digital power supply. bypass to dgnd with a 1f capacitor. 28 f6 dvddio digital audio interface power-supply input. bypass to dgnd with a 1f capacitor. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 67 bump/pin descriptions (continued) pin bump max98090 function tqfn wlp 29 g7 dgnd digital ground 30 e5 sdin digital audio serial data playback input 31 g6 sdout digital audio serial data record output. the output voltage is referenced to dvddio. 32 f5 lrclk digital audio left-right clock input/output. lrclk is the audio sample rate clock and determines whether audio data is routed to the left or right channel. in tdm mode, lrclk is a frame sync pulse. lrclk is an input when the device is in slave mode and an output when in master mode. 33 g5 bclk digital audio bit clock input/output. bclk is an input when the device is in slave mode and an output when in master mode. the input/output voltage is referenced to dvddio. 34 f4 irq active-low hardware interrupt output. connect a 10k? pullup resistor to v dd . 35 g4 mclk master clock input. acceptable input frequency range is either 256 x f s or from 10mhz to 60mhz. 36 d3 scl i 2 c serial clock input. connect a pullup resistor to dvdd for full output swing. 37 e2 sda i 2 c serial data input/output. connect a pullup resistor to dvdd for full output swing. 38 g3 hpvdd headphone power supply. bypass to hpgnd with a 1f capacitor. 39 f3 c1p charge-pump flying capacitor positive terminal. connect a 1f ceramic capacitor between c1n and c1p. 40 f2 c1n charge-pump flying capacitor negative terminal. connect a 1f ceramic capacitor between c1n and c1p. b3, b4 spkvdd speaker and microphone bias power supply. bypass to spk_gnd with a 1f capacitor. c4 in5 auxiliary negative differential microphone input or single-ended line input. ac-couple with a series 1f capacitor. d4 in6 auxiliary positive differential microphone input or single-ended line input. ac-couple with a series 1f capacitor. b2, c2, c3, c5, d5, e3, e4 n.c. not connected internally max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 68 detailed description the max98090 is a fully integrated stereo audio codec with flexsound audio processing and integrated input and output audio amplifiers. the device features either six (wlp package) or four (tqfn package) flexible analog inputs. each pair can be configured as a differential analog microphone input, a stereo single ended or differential line input(s), or as a reduced power, direct differential analog input to the adc mixer. one input pair, in1/in2, can also be retasked to support two digital microphones. as a result, two micro - phones (either analog or digital) can be recorded from simultaneously. the input analog signals can be amplified by up to 50db, and then are either recorded by the stereo adc or routed directly to the analog output mixers for playback. the adc supports sample rates between 8khz and 96khz, features two performance modes, and provides two oversampling rate options. the adc to dai digital record path features both voice (iir) and music (fir) filtering, an optional dc-blocking highpass filter, a fully configurable biquad filter, and a -12db to +45db range of programmable digital gain and level control. the digital audio interface (dai) can simultaneously transmit and receive separate and distinct stereo audio signals. the dai supports a wide range of pcm digital audio formats including i 2 s, left justified (lj), right justi - fied (rj), and four slot tdm. as with the record path, the dai to dac playback path supports sample rates from 8khz to 96khz, both voice (iir) and music (fir) filtering (high stop band attenuation at f s /2), optional dc blocking filters, and a -15db to +18db range of programmable digital gain and level control. in addition, the playback path also features a 7-band para - metric biquad equalizer, dynamic range control (drc), and a summing digital sidetone from the record path dsp. the device includes three analog output drivers. the first is a class ab differential receiver/earpiece amplifier. alternatively, the receiver amplifier can also be configured as a stereo single-ended line output driver. the second is an integrated, filterless, class d stereo speaker amplifier. this amplifier provides efficient ampli - fication for two speakers, and includes active emissions limiting to minimize the radiated emissions (emi) tradition - ally associated with class d. the right channel features a slave mode, in which the switching is synchronized to that of the left channel to eliminate the beat tone that can occur with asynchronous operation. in most systems with short speaker traces, no class d output filtering is required. the third is a class h, ground referenced stereo headphone amplifier featuring maxims second generation directdrive architecture. the class h headphone amplifier features an internal charge pump that generates both a positive and negative supply for the headphone amplifier. this provides a ground referenced output signal that eliminates the need for either dc-blocking capacitors or a midrail bias for the headphone jack ground return. the headphone dedicated ground sense current return reduces crosstalk and output noise. a tracking circuit monitors the signal level and automatically selects the appropriate switching frequency and supply voltage level. for low signal levels, the charge pump switches at a reduced frequency and out - puts v hpvdd /2 for improved efficiency. when the signal amplitude increase, the charge-pump switching frequency also increases, and continues to output v hpvdd /2. for high signal levels, the charge pump outputs full-scale rails at v hpvdd to maximize output power. the device also includes several additional features such as a programmable external microphone bias, configurable jack detection and identification, extensive click-and-pop reduction circuitry, power and performance management settings, and a full range of quick configuration options. device i 2 c register map table 1 lists all of the registers, their addresses, and power-on-reset (por) states. registers 0x01, 0x02, and 0xff are read only. register 0x00 and all of the remain - ing registers are read/write. write zeros to all unused bits in the register table when updating the register, unless otherwise noted. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 69 table 1. max98090 control register map note: register bits in bold italics are for the wlp package only. register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset/status/interrupt registers 0x00 software reset w swreset 0x00 0x01 device status cor cld sld ulk jdet drcact drcclp 0x00 0x02 jack status r lsns jksns 0x00 0x03 interupt masks r/w icld isld iulk ijdet idrcact idrcclp 0x04 quick setup registers 0x04 system clock w 26m 19p2m 13m 12p288m 12m 11p2896m 256f s 0x00 0x05 sample rate w sr_96k sr_32k sr_48k sr_44k1 sr_16k sr_8k 0x00 0x06 dai interface w rj_m rj_s lj_m lj_s i2s_m i2s_s 0x00 0x07 dac path w dig2_hp dig2_ ear dig2_ spk dig2_ lout 0x00 0x08 mic/direct to adc w in12_mic1 in34_ mic2 in12_ dadc in34_ dadc in56_ dadc 0x00 0x09 line to adc w in12s_ab in34s_ab in56s_ab in34d_a in65d_b 0x00 0x0a analog mic loop w in12_ m1hpl in12_ m1spkl in12_ m1ear in12_ m1loutl in34_ m2hpr in34_ m2spkr in34_ m2ear in34_ m2loutr 0x00 0x0b analog line loop w in12s_ abhp in34d_ aspkl in34d_ aear in12s_ ablout in34s_ abhp in65d _bspkr in65d_ bear in34s_ ablout 0x00 reserved register 0x0c reserved 0x00 analog input configuration registers 0x0d line input config. r/w in34diff in65diff in1seen in2seen in3seen in4seen in5seen in6seen 0x00 0x0e line input level r/w mixg135 mixg246 linapga[2:0] linbpga[2:0] 0x1b 0x0f input mode r/w extbufa extbufb ext_mic[1:0] 0x00 0x10 mic1 input level r/w pa1en[1:0] pgam1[4:0] 0x14 0x11 mic2 input level r/w pa2en[1:0] pgam2[4:0] 0x14 microphone configuration registers 0x12 mic bias voltage r/w mbvsel[1:0] 0x00 0x13 digital mic enable r/w micclk[2:0] digmicr digmicl 0x00 0x14 digital mic config. r/w dmic_comp[3:0] dmic_freq[1:0] 0x00 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 70 table 1. max98090 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc path and configuration registers 0x15 left adc mixer r/w mixadl[6:0] 0x00 0x16 right adc mixer r/w mixadr[6:0] 0x00 0x17 left record level r/w avlg[2:0] avl[3:0] 0x03 0x18 right record level r/w avrg[2:0] avr[3:0] 0x03 0x19 record biquad level r/w avbq[3:0] 0x00 0x1a record sidetone r/w dsts[1:0] dvst[4:0] 0x00 clock configuration registers 0x1b system clock r/w psclk[1:0] 0x00 0x1c clock mode r/w freq[3:0] use_mi 0x00 0x1d clock ratio ni msb r/w ni[14:8] 0x00 0x1e clock ratio ni lsb r/w ni[7:0] 0x00 0x1f clock ratio mi msb r/w mi[15:8] 0x00 0x20 clock ratio mi lsb r/w mi[7:0] 0x00 0x21 master mode r/w mas bsel[2:0] 0x00 interface control registers 0x22 interface format r/w rj wci bci dly ws[1:0] 0x00 0x23 tdm control r/w fsw tdm 0x00 0x24 tdm format r/w slotl[1:0] slotr[1:0] slotdly[3:0] 0x00 0x25 i/o configuration r/w lten lben dmono hizoff sdoen sdien 0x00 0x26 filter configuration r/w mode ahpf dhpf dhf 0x80 0x27 dai playback level r/w dvm dvg[1:0] dv[3:0] 0x00 0x28 eq playback level r/w eqclp dveq[3:0] 0x00 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 71 table 1. max98090 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 headphone (hp) control registers 0x29 left hp mixer r/w mixhpl[5:0] 0x00 0x2a right hp mixer r/w mixhpr[5:0] 0x00 0x2b hp control r/w mixhp rsel mixhp lsel mixhprg[1:0] mixhplg[1:0] 0x00 0x2c left hp volume r/w hplm hpvoll[4:0] 0x1a 0x2d right hp volume r/w hprm hpvolr[4:0] 0x1a speaker (spk) configuration registers 0x2e left spk mixer r/w mixspl[5:0] 0x00 0x2f right spk mixer r/w spk_ slave mixspr[5:0] 0x00 0x30 spk control r/w mixsprg[1:0] mixsplg[1:0] 0x00 0x31 left spk volume r/w splm spvoll[5:0] 0x2c 0x32 right spk volume r/w sprm spvolr[5:0] 0x2c dynamic range control (drc) configuration registers 0x33 drc timing r/w drcen drcrls[2:0] drcatk[2:0] 0x00 0x34 drc compressor r/w drccmp[2:0] drcthc[4:0] 0x00 0x35 drc expander r/w drcexp[2:0] drcthe[4:0] 0x00 0x36 drc gain r/w drcg[4:0] 0x00 receiver (rcv or earpiece) and line output (lout) registers 0x37 rcv/loutl mixer r/w mixrcvl[5:0] 0x00 0x38 rcv/loutl control r/w mixrcvlg[1:0] 0x00 0x39 rcv/loutl volume r/w rcvlm rcvlvol[4:0] 0x15 0x3a loutr mixer r/w linmod mixrcvr[5:0] 0x00 0x3b loutr control r/w mixrcvrg[1:0] 0x00 0x3c loutr volume r/w rcvrm rcvrvol[4:0] 0x15 jack detect and enable registers 0x3d jack detect r/w jdeten jdwk jdeb[1:0] 0x00 0x3e input enable r/w mben lineaen lineben adren adlen 0x00 0x3f output enable r/w hpren hplen spren splen rcvlen rcvren daren dalen 0x00 0x40 level control r/w zden vs2en vsen 0x00 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 72 table 1. max98090 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x41 dsp filter enable r/w recbqen eq3band en eq5band en eq7band en 0x00 bias and power mode configuration registers 0x42 bias control r/w bias_ mode 0x00 0x43 dac control r/w perf mode dachp 0x00 0x44 adc control r/w osr128 adc dither adchp 0x06 0x45 device shutdown r/w shdn 0x00 playback parametric equalizer band 1: biquad filter coefficient registers 0x46 equalizer band 1 coefficient b0 r/w b0_1[23:16] 0x47 r/w b0_1[15:8] 0x48 r/w b0_1[7:0] 0x49 equalizer band 1 coefficient b1 r/w b1_1[23:16] 0x4a r/w b1_1[15:8] 0x4b r/w b1_1[7:0] 0x4c equalizer band 1 coefficient b2 r/w b2_1[23:16] 0x4d r/w b2_1[15:8] 0x4e r/w b2_1[7:0] 0x4f equalizer band 1 coefficient a1 r/w a1_1[23:16] 0x50 r/w a1_1[15:8] 0x51 r/w a1_1[7:0] 0x52 equalizer band 1 coefficient a2 r/w a2_1[23:16] 0x53 r/w a2_1[15:8] 0x54 r/w a2_1[7:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 73 table 1. max98090 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 playback parametric equalizer band 2: biquad filter coefficient registers 0x55 equalizer band 2 coefficient b0 r/w b0_2[23:16] 0x56 r/w b0_2[15:8] 0x57 r/w b0_2[7:0] 0x58 equalizer band 2 coefficient b1 r/w b1_2[23:16] 0x59 r/w b1_2[15:8] 0x5a r/w b1_2[7:0] 0x5b equalizer band 2 coefficient b2 r/w b2_2[23:16] 0x5c r/w b2_2[15:8] 0x5d r/w b2_2[7:0] 0x5e equalizer band 2 coefficient a1 r/w a1_2[23:16] 0x5f r/w a1_2[15:8] 0x60 r/w a1_2[7:0] 0x61 equalizer band 2 coefficient a2 r/w a2_2[23:16] 0x62 r/w a2_2[15:8] 0x63 r/w a2_2[7:0] playback parametric equalizer band 3: biquad filter coefficient registers 0x64 equalizer band 3 coefficient b0 r/w b0_3[23:16] 0x65 r/w b0_3[15:8] 0x66 r/w b0_3[7:0] 0x67 equalizer band 3 coefficient b1 r/w b1_3[23:16] 0x68 r/w b1_3[15:8] 0x69 r/w b1_3[7:0] 0x6a equalizer band 3 coefficient b2 r/w b2_3[23:16] 0x6b r/w b2_3[15:8] 0x6c r/w b2_3[7:0] 0x6d equalizer band 3 coefficient a1 r/w a1_3[23:16] 0x6e r/w a1_3[15:8] 0x6f r/w a1_3[7:0] 0x70 equalizer band 3 coefficient a2 r/w a2_3[23:16] 0x71 r/w a2_3[15:8] 0x72 r/w a2_3[7:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 74 table 1. max98090 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 playback parametric equalizer band 4: biquad filter coefficient registers 0x73 equalizer band 4 coefficient b0 r/w b0_4[23:16] 0x74 r/w b0_4[15:8] 0x75 r/w b0_4[7:0] 0x76 equalizer band 4 coefficient b1 r/w b1_4[23:16] 0x77 r/w b1_4[15:8] 0x78 r/w b1_4[7:0] 0x79 equalizer band 4 coefficient b2 r/w b2_4[23:16] 0x7a r/w b2_4[15:8] 0x7b r/w b2_4[7:0] 0x7c equalizer band 4 coefficient a1 r/w a1_4[23:16] 0x7d r/w a1_4[15:8] 0x7e r/w a1_4[7:0] 0x7f equalizer band 4 coefficient a2 r/w a2_4[23:16] 0x80 r/w a2_4[15:8] 0x81 r/w a2_4[7:0] playback parametric equalizer band 5: biquad filter coefficient registers 0x82 equalizer band 5 coefficient b0 r/w b0_5[23:16] 0x83 r/w b0_5[15:8] 0x84 r/w b0_5[7:0] 0x85 equalizer band 5 coefficient b1 r/w b1_5[23:16] 0x86 r/w b1_5[15:8] 0x87 r/w b1_5[7:0] 0x88 equalizer band 5 coefficient b2 r/w b2_5[23:16] 0x89 r/w b2_5[15:8] 0x8a r/w b2_5[7:0] 0x8b equalizer band 5 coefficient a1 r/w a1_5[23:16] 0x8c r/w a1_5[15:8] 0x8d r/w a1_5[7:0] 0x8e equalizer band 5 coefficient a2 r/w a2_5[23:16] 0x8f r/w a2_5[15:8] 0x90 r/w a2_5[7:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 75 table 1. max98090 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 playback parametric equalizer band 6: biquad filter coefficient registers 0x91 equalizer band 6 coefficient b0 r/w b0_6[23:16] 0x92 r/w b0_6[15:8] 0x93 r/w b0_6[7:0] 0x94 equalizer band 6 coefficient b1 r/w b1_6[23:16] 0x95 r/w b1_6[15:8] 0x96 r/w b1_6[7:0] 0x97 equalizer band 6 coefficient b2 r/w b2_6[23:16] 0x98 r/w b2_6[15:8] 0x99 r/w b2_6[7:0] 0x9a equalizer band 6 coefficient a1 r/w a1_6[23:16] 0x9b r/w a1_6[15:8] 0x9c r/w a1_6[7:0] 0x9d equalizer band 6 coefficient a2 r/w a2_6[23:16] 0x9e r/w a2_6[15:8] 0x9f r/w a2_6[7:0] playback parametric equalizer band 7: biquad filter coefficient registers 0xa0 equalizer band 7 coefficient b0 r/w b0_7[23:16] 0xa1 r/w b0_7[15:8] 0xa2 r/w b0_7[7:0] 0xa3 equalizer band 7 coefficient b1 r/w b1_7[23:16] 0xa4 r/w b1_7[15:8] 0xa5 r/w b1_7[7:0] 0xa6 equalizer band 7 coefficient b2 r/w b2_7[23:16] 0xa7 r/w b2_7[15:8] 0xa8 r/w b2_7[7:0] 0xa9 equalizer band 7 coefficient a1 r/w a1_7[23:16] 0xaa r/w a1_7[15:8] 0xab r/w a1_7[7:0] 0xac equalizer band 7 coefficient a2 r/w a2_7[23:16] 0xad r/w a2_7[15:8] 0xae r/w a2_7[7:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 76 table 1. max98090 control register map (continued) software reset the device provides a software controlled reset (table 2) that is used to return most registers to their default (por) states (the record biquad and playback parametric equalizer coefficients are not reset). the software reset register is a pushbutton, write only register. as a result, a read of this register always returns 0x00. writing logic- high to swreset triggers a software register reset, while writing a logic-low to swreset has no effect. table 2. software reset register register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 record biquad filter coefficient registers 0xaf record biquad coefficient b0 r/w rec_b0[23:16] 0xb0 r/w rec_b0[15:8] 0xb1 r/w rec_b0[7:0] 0xb2 record biquad coefficient b1 r/w rec_b1[23:16] 0xb3 r/w rec_b1[15:8] 0xb4 r/w rec_b1[7:0] 0xb5 record biquad coefficient b2 r/w rec_b2[23:16] 0xb6 r/w rec_b2[15:8] 0xb7 r/w rec_b2[7:0] 0xb8 record biquad coefficient a1 r/w rec_a1[23:16] 0xb9 r/w rec_a1[15:8] 0xba r/w rec_a1[7:0] 0xbb record biquad coefficient a2 r/w rec_a2[23:16] 0xbc r/w rec_a2[15:8] 0xbd r/w rec_a2[7:0] revision id register 0xff revision id r revid[7:0] 0x43 address: 0x00 description bit name type por 7 swreset w 0 pushbutton software device reset 0: writing a logic low to swreset has no effect. 1: reset all registers to their default por values. this excludes the record biquad and playback parametric equalizer flter coeffcients (table 24 and table 45). 6 5 4 3 2 1 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 77 table 3. bias control register table 4. dac and headphone performance mode control register power and performance management the device includes comprehensive power management to allow the disabling of unused blocks to minimize sup - ply current. in addition to this, the available power modes provide a software configurable choice between highest performance and reduced power consumption. device performance confguration the bias control register (table 3) selects the method used to derive the common-mode reference voltage. a common-mode bias created by resistive division (from the avdd supply) facilitates lower overall power consumption by disabling the bandgap reference circuit. however, this type of bias reference has the disadvantage of scaling with the avdd supply voltage (and thus also has reduced psrr). when derived from a bandgap reference, bias is constant regardless of the supply voltage, but the addi - tional circuitry increases power consumption. the adc, dac, and headphone playback all have option - al high-performance modes (tables 4 and 5). in each case, these modes trade additional power consumption for enhanced performance. the adc also has optional address: 0x42 description bit name type por 7 6 5 4 3 2 1 0 bias_mode r/w 0 select source for bias. 0: bias derived from resistive division. 1: bias created by bandgap reference. address: 0x43 description bit name type por 7 6 5 4 3 2 1 perfmode r/w 0 performance mode selects dac to headphone playback performance mode: 1: low power headphone playback mode. 0: high performance headphone playback mode. 0 dachp r/w 0 dac high-performance mode 0: dac settings optimized for lowest power consumption. 1: dac settings optimized for best performance. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 78 dither (recommended for the cleanest spectrum), and can be configured to two different oversampling rates. see the analog-to-digital converter (adc) section for additional details on adc operation. device enable confguration in addition to a device global shutdown control, the major input and output blocks can be independently enabled (or disabled) to optimize power consumption. the device global shutdown control is detailed in table 6. table 5. adc performance mode control register table 6. device shutdown register address: 0x44 description bit name type por 7 6 5 4 3 2 osr128 r/w 1 adc oversampling rate 0: f adcclk = 64 x f s 1: f adcclk = 128 x f s 1 adcdither r/w 1 adc quantizer dither 0: dither disabled. 1: dither enabled. 0 adchp r/w 0 adc high-performance mode 0: adc is optimized for low power operation. 1: adc is optimized for best performance. address: 0x45 description bit name type por 7 shdn r/w 0 device active-low global shutdown control 0: device is in shutdown. 1: device is active. certain registers should not be written to while the device is active (table 82). 6 5 4 3 2 1 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 79 table 7. input enable register table 7 details the available input signal path enables (with the exception of the analog microphone inputs 1/2, which are enabled from registers 0x10 and 0x11, or tables 9 and 10, respectively). table 8 details the avail - able output signal path enables. when the device is in global shutdown, the major input and output blocks are all disabled to conserve power. however, the i 2 c interface remains active and all device registers can be configured. certain registers should be programmed while in shutdown only (detailed in table 82). changing these registers when the device is active could result in unexpected behavior. for optimal mini - mized power consumption, only enable the stage blocks that are part of the intended signal path configuration. address: 0x3e description bit name type por 7 6 5 4 mben r/w 0 microphone bias enable 0: microphone bias disabled. 1: microphone bias enabled. 3 lineaen r/w 0 enables line a analog input block 0: line a input amplifer disabled. 1: line a input amplifer enabled. 2 lineben r/w 0 enables line b analog input block 0: line b input amplifer disabled. 1: line b input amplifer enabled. 1 adren r/w 0 right adc enable 0: right adc disabled. 1: right adc enabled. 0 adlen r/w 0 left adc enable 0: left adc disabled. 1: left adc enabled. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 80 table 8. output enable register address: 0x3f description bit name type por 7 hpren r/w 0 right headphone output enable 0: right headphone output disabled. 1: right headphone output enabled . 6 hplen r/w 0 left headphone output enable 0: left headphone output disabled. 1: left headphone output enabled. 5 spren r/w 0 right class d speaker output enable 0: right speaker output disabled. 1: right speaker output enabled. 4 splen r/w 0 left class d speaker output enable 0: left speaker output disabled. 1: left speaker output enabled. 3 rcvlen r/w 0 receiver (earpiece)/left line output enable 0: receiver/left line output disabled. 1: receiver/left line output enabled. 2 rcvren r/w 0 right line output enable 0: right line output disabled. 1: right line output enabled. 1 daren r/w 0 right dac digital input enable 0: right dac input disabled. 1: right dac input enabled. 0 dalen r/w 0 left dac digital input enable 0: left dac input disabled. 1: left dac input enabled. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 81 figure 5. analog audio input functional diagram analog audio input confguration the device features either six (wlp package) or four (tqfn package) flexible analog inputs. each pair can be configured as either an analog microphone input, a single-ended or differential line input(s), or as a reduced power, full-scale differential analog input direct to the adc mixer. the analog microphone and line inputs can either be routed to the stereo adc mixer for recording or directly to any analog output mixer for playback. mben pa1en[1:0] extmic[0] pclk mbvsel[1:0] mic 1 input mux micbias microphone bias generator micclk[2:0] digmicl digital microphone control mic 1 preamp pgam1[4:0] 0db to 20db 0db to 20db -6db to 20db -6db to 20db in1-in2 in3-in4 in5-in6 line a line b mic 1 mic 2 in1-in2 in3-in4 in5-in6 line a line b mic 1 mic 2 adlen adren adchp osr128 adcdither mic 1 pga mic 2 input mux mic 2 preamp zdenb pa2en[1:0] extmic[1] pgam2[4:0] lineaen extbufa in1seen in3seen in5seen in34diff in2seen in4seen in6seen in65diff linbpga[2:0] line a pga line b pga lineben extbufb linapga[2:0] line a input mixer mixg135 mixg246 line b input mixer adc left mixer adc right mixer mic 2 pga in1-in2 in5-in6 in1/ dmd in3 in4 in5 in6 (wlp only) in2/ dmc digital mic data left mux digital mic data left mux in3-in4 in5-in6 in3 in1 in3-in4 in5 in4 in2 in6-in5 in6 analo g output mixers mixadl[6:0] mixadr[6:0] digmicr dmdl dmdr adcl adc left adc right adcr flexsound technology dsp max98090 0db 10db 30db 0db 10db 30db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 82 analog microphone inputs the device includes three differential microphone inputs (three for the wlp package and two for the tqfn pack - age) and a programmable, low-noise microphone bias for powering a wide variety of external micro phones (figure 6). by default, analog inputs in1 and in2 differen - tially (in1/in2) provide the input to microphone amplifier 1, while in3 and in4 differentially (in3/in4) form the input to microphone amplifier 2. for the wlp package, the additional analog input pair (in5 and in6) can be con - figured as a differential input (in5 - in6) to either micro - phone amplifier 1 or 2 (table 18). in the typical application, one microphone input is used for the handset microphone and the other is used as an accessory microphone (in1/in2 and in3/in4). in systems using a background noise microphone, in5/in6 (wlp only) can be retasked as another microphone input. figure 6. analog microphone input functional diagram mben pa1en[1:0] extmic[0] mbvsel[1:0] mic 1 input mux micbias microphone bias generator mic 1 preamp pgam1[4:0] 0db to 20db 0db to 20db 0db 10db 30db 0db 10db 30db in1-in2 in3-in4 in5-in6 mic 1 mic 2 line a line b in1-in2 in3-in4 in5-in6 mic 1 mic 2 line a line b mic 1 pga mic 2 input mux mic 2 preamp zdenb pa2en[1:0] extmic[1] pgam2[4:0] adc left mixer adc right mixer mic 2 pga in1-in2 in5-in6 line a line b in1/ dmd in2/ dmc in5 in3-in4 in5-in6 analog output mixers max98090 mixadr[6:0] mixadl[6:0] in6 (wlp only) in3 in4 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 83 table 9. microphone 1 enable and level configuration register table 10. microphone 2 enable and level configuration register analog microphone preamplifer and pga the analog microphone inputs have two stages of pro - grammable gain amplifiers, and are then routed to the adc mixer (record), the analog outputs (playback), or simultaneously to both. the first, a coarse preamplifier gain stage, includes the analog microphone enable, and offers selectable 0db, 20db, or 30db gain settings. the second, a fine gain stage, is a programmable-gain ampli - fier (pga) adjustable from 0db to 20db in 1db steps (tables 9 and 10). together, the two stages provide up to 50db of signal gain for the analog microphone inputs. to maximize the signal-to-noise ratio, use the coarse gain settings of the first stage whenever possible. zero- crossing detection is included on the pga to minimize zipper noise while making gain changes. address: 0x10 description bit name type por 7 6 pa1en[1:0] r/w 0 microphone 1 input amplifer enable and coarse gain setting 00: disabled 10: 20db 01: 0db 11: 30db 5 0 4 pgam1[4:0] r/w 1 microphone 1 programmable gain amplifer fine adjust confguration 3 0 0x1f: 0db 0x14: 0db 0x13: 1db 0x12: 2db 0x11: 3db 0x10: 4db 0x0f: 5db 0x0e: 6db 0x0d: 7db 0x0c: 8db 0x0b: 9db 0x0a: 10db 0x09: 11db 0x08: 12db 0x07: 13db 0x06: 14db 0x05: 15db 0x04: 16db 0x03: 17db 0x02: 18db 0x01: 19db 0x00: 20db 2 1 1 0 0 0 address: 0x11 description bit name type por 7 6 pa2en[1:0] r/w 0 microphone 2 input amplifer enable and coarse gain setting 00: disabled 10: 20db 01: 0db 11: 30db 5 0 4 pgam2[4:0] r/w 1 microphone 2 programmable gain amplifer fine adjust confguration 3 0 0x1f: 0db 0x14: 0db 0x13: 1db 0x12: 2db 0x11: 3db 0x10: 4db 0x0f: 5db 0x0e: 6db 0x0d: 7db 0x0c: 8db 0x0b: 9db 0x0a: 10db 0x09: 11db 0x08: 12db 0x07: 13db 0x06: 14db 0x05: 15db 0x04: 16db 0x03: 17db 0x02: 18db 0x01: 19db 0x00: 20db 2 1 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 84 figure 7. digital microphone input functional diagram analog microphone bias voltage the device features a regulated, low noise microphone bias output (micbias) that can be configured to power a wide range of external microphone devices. to enable the microphone bias output, set mben in the input enable register (table 7). when the device is powered and the microphone bias is disabled (mben is low or the device is in shutdown), micbias is placed in a high-impedance state. the microphone bias voltage can be set by the soft - ware to any one of 4 voltages (2.2v, 2.4v, 2.55v, or 2.8v) by programming the microphone bias level configuration register (table 11). digital microphone inputs one pair of microphone inputs (in1/in2) can also be configured to interface to up to two digital microphones (figure 7). the record path dsp is automatically switched to accept the appropriate digital microphone data channel when enabled (figure 13). both channels (left and right) must be enabled to use the digital microphone interface. when both channels are enabled, the digital microphone interface provides a digital microphone clock on in2/dmc and accepts pdm data on in1/dmd. a single digital micro - phone input cannot be paired with a single analog micro - phone input. left channel data is accepted on falling clock edges while the right channel data is accepted on the rising clock edges (see figure 4 for timing requirements). to avoid any potential clipping and distortion, always enable the record path dc blocking filters to remove any built-in dc offsets when using a digital microphone input (ahpf, table 21). the record path biquad filter and digital gain and level control stages can also be applied to digital microphone input signals. digital microphone clock confguration the digital microphone clock frequency (f dmicclk ) can be configured to any one of 6 settings using micclk[2:0] (table 13). the digital microphone clock is derived from a pclk divider, with available settings ranging incremen - tally from f pclk /2 to f pclk /8. this wide range of available digital microphone clock frequencies is intended to sup - port both current and next generation digital microphones. table 12 lists the resulting clock frequencies for common - ly used master clock (and resulting pclk) frequencies. digmicr adc left mixer adc left adc right mixer adc right pclk dmdl adcl dmdr adcr digmicl micclk[2:0] digital microphone control in2/ dmc in1/ dmd in3 in4 in5 micbias (wlp only) in6 digital mic left mux digital mic right mux left record path dsp right record path dsp flexsound technology dsp dai max98090 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 85 table 11. microphone bias level configuration register table 12. digital microphone clocks for commonly used master clocks settings table 13. digital microphone enable address: 0x12 description bit name type por 7 6 5 4 3 2 1 mbvsel[1:0] r/w 0 microphone bias level confguration 00: 2.2v 10: 2.55v 01: 2.4v 11: 2.8v 0 0 master clock frequency (f mclk ) 10mhz 11.2896mhz 12mhz 12.288mhz 13/26mhz 19.2mhz approximate digital microphone clock frequency (f dmicclk ) f pclk /2 5.0mhz 5.645mhz 6.0mhz 6.144mhz 6.5mhz f pclk /3 3.333mhz 3.763mhz 4.0mhz 4.096mhz 4.333mhz 6.4mhz f pclk /4 2.5mhz 2.822mhz 3.0mhz 3.072mhz 3.25mhz 4.8mhz f pclk /5 2.0mhz 2.258mhz 2.4mhz 2.458mhz 2.6mhz 3.84mhz f pclk /6 1.667mhz 1.882mhz 2.0mhz 2.048mhz 2.167mhz 3.2mhz f pclk /8 1.25mhz 1.411mhz 1.5mhz 1.536mhz 1.625mhz 2.4mhz address: 0x13 description bit name type por 7 6 micclk[2:0] r/w 0 digital microphone clock rate confguration 000: f dmicclk = f pclk /2 100: f dmicclk = f pclk /6 001: f dmicclk = f pclk /3 101: f dmicclk = f pclk /8 010: f dmicclk = f pclk /4 110: reserved 011: f dmicclk = f pclk /5 111: reserved 5 0 4 0 3 2 1 digmicr r/w 0 digital microphone right channel enable 0: right record channel uses on-chip adc. 1: right record channel uses digital microphone input. 0 digmicl r/w 0 digital microphone left channel enable 0: left record channel uses on-chip adc. 1: left record channel uses digital microphone input. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 86 digital microphone frequency compensation the digital microphone inputs can be configured to pro - duce a wide range of digital microphone clock frequen - cies. to optimize performance over the entire range of available frequencies, the device provides configurable frequency range and compensation settings. once the master clock (and thus prescaled clock) frequency is decided, and the digital microphone clock divider is cho - sen, the digital microphone frequency range bits should be programmed to the correct range (dmic_freq, table 14). if quick configuration mode is used and a system clock bit is selected (table 36), then the device automatically calculates and selects the correct range once the digital microphone clock divider is configured. the digital microphone inputs also provide a configu - rable frequency compensation filter with nine frequency response settings (figure 8). every digital microphone clock and sample rate combination results in a different baseline frequency response. table 15 to table 20 pro - vide the recommended compensation filter settings for the most commonly used clock and sample rate combina - tions. for nonstandard combinations either use the clos - est recommended setting or choose the curve that best fits the measured response. in quick configuration mode, once both the system clock and sample rate bits are selected (table 36 and table 37), the device automatically selects the recommended response curve once the digital microphone clock divider is configured. the digital micro - phone input does not support sample rates in excess of 50khz (where dhf = 1, table 27). table 14. digital microphone configuration figure 8. digital microphone compensation filter frequency response address: 0x14 description bit name type por 7 dmic_comp[3:0] r/w 0 digital microphone compensation filter confguration 0000C1000: figure 8 details the available compensation flter confgurations. 1001C1111: confgures the compensation flter to a pass through response. the compensation flter response scales with the sample rate up to the nyquist bandwidth limit (f s /2). automatically decoded in quick confguration mode. 6 0 5 0 4 0 3 2 1 dmic_freq[1:0] r/w 0 digital microphone frequency range confguration 00: f digmicclk < 3.5mhz 10: 4.5mhz f digmicclk 01: 3.5mhz f digmicclk < 4.5mhz 11: reserved if any of the system clock quick confguration bits in register 0x04 are set, then the frequency range confguration is automatically decoded. 0 r/w 0 digital microphone compensation filte r response vs. normalized frequency normalized frequenc y compensation filter response (db ) 0.4 x f s 0.3 x f s 0.2 x f s 0.1 x f s 0.5 1.0 1.5 2.0 2.5 0 0 x f s 0.5 x f s dmic_comp = 6 dmic_comp = 5 dmic_comp = 4 dmic_comp = 3 dmic_comp = 2 dmic_comp = 1 dmic_comp = 0 dmic_comp = 8 dmic_comp = 7 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 87 table 15. recommended compensation filter settings for f mclk = 11.2896mhz table 16. recommended compensation filter settings for f mclk = 12mhz table 17. recommended compensation filter settings for f mclk = 12.288mhz f pclk = 11.2896mhz recommended dmic_comp setting by sample rate (khz) micclk divider f dmicclk (mhz) dmic_freq 8 16 32 44.1 48 0 f pclk /2 5.6448 2 7 8 3 3 3 1 f pclk /3 3.7632 1 7 8 2 2 2 2 f pclk /4 2.8224 0 7 8 3 3 3 3 f pclk /5 2.25792 0 7 8 6 6 6 4 f pclk /6 1.8816 0 7 8 3 3 3 5 f pclk /8 1.4112 0 7 8 3 3 3 f pclk = 12mhz recommended dmic_comp setting by sample rate (khz) micclk divider f dmicclk (mhz) dmic_freq 8 16 32 44.1 48 0 f pclk /2 6 2 7 8 3 3 3 1 f pclk /3 4 1 7 8 2 2 2 2 f pclk /4 3 0 7 8 3 3 3 3 f pclk /5 2.4 0 7 8 5 5 6 4 f pclk /6 2 0 7 8 3 3 3 5 f pclk /8 1.5 0 7 8 3 3 3 f pclk = 12.288(mhz) recommended dmic_comp setting by sample rate (khz) micclk divider f dmicclk (mhz) dmic_freq 8 16 32 44.1 48 0 f pclk /2 6.144 2 7 8 3 3 3 1 f pclk /3 4.096 1 7 8 2 2 2 2 f pclk /4 3.072 0 7 8 3 3 3 3 f pclk /5 2.4576 0 7 8 6 6 6 4 f pclk /6 2.048 0 7 8 3 3 3 5 f pclk /8 1.536 0 7 8 3 3 3 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 88 table 18. recommended compensation filter settings for f mclk = 13mhz/26mhz table 19. recommended compensation filter settings for f mclk = 19.2mhz table 20. recommended compensation filter settings for f mclk = 256 x f s f pclk = 13mhz recommended dmic_comp setting by sample rate (khz) micclk divider f dmicclk (mhz) dmic_freq 8 16 32 44.1 48 0 f pclk /2 6.5 2 7 8 1 1 1 1 f pclk /3 4.333 1 7 8 0 0 1 2 f pclk /4 3.25 0 7 8 1 1 1 3 f pclk /5 2.6 0 7 8 4 4 5 4 f pclk /6 2.167 0 7 8 1 1 1 5 f pclk /8 1.625 0 7 8 1 1 1 f pclk = 19.2mhz recommended dmic_comp setting by sample rate (khz) micclk divider f dmicclk (mhz) dmic_freq 8 16 32 44.1 48 0 f pclk /2 1 f pclk /3 6.4 2 7 8 1 1 1 2 f pclk /4 4.8 2 7 8 5 5 6 3 f pclk /5 3.84 1 7 8 2 2 3 4 f pclk /6 3.2 0 7 8 1 1 2 5 f pclk /8 2.4 0 7 8 5 5 6 f pclk = 256 x f s recommended dmic_comp setting by sample rate (khz) micclk divider f dmicclk (mhz) dmic_freq 8 16 32 44.1 48 0 f pclk /2 7 8 3 3 3 1 f pclk /3 7 8 2 2 2 2 f pclk /4 7 8 3 3 3 3 f pclk /5 7 8 6 6 6 4 f pclk /6 7 8 3 3 3 5 f pclk /8 7 8 3 3 3 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 89 analog line inputs the device includes multiple line level input options and two analog line input programmable gain amplifiers (pgas, figure 9). the line input structure supports mul - tiple configurations including stereo single-ended inputs, stereo differential inputs, and stereo mixed single-ended inputs (any two per line input mixer). analog line input mixers the analog line input mixer allows the selection of either single-ended or differential inputs to each line input chan - nel (table 21). the line a input mixer can accept single- ended inputs from in1, in3, and in5, or a differential input from in3 and in4 (in3 - in4). the line b input mixer can accept single-ended inputs from in2, in4, and in6, or a table 21. line input mixer configuration register figure 9. analog line input functional diagram address: 0x0d description bit name type por 7 in34diff r/w 0 selects in3, in4 differentially as an input to the line a mixer. 6 in65diff r/w 0 selects in6, in5 differentially as an input to the line b mixer (wlp only). 5 in1seen r/w 0 selects in1 single ended as an input to the line a mixer. 4 in2seen r/w 0 selects in2 single ended as an input to the line b mixer. 3 in3seen r/w 0 selects in3 single ended as an input to the line a mixer. 2 in4seen r/w 0 selects in4 single ended as an input to the line b mixer. 1 in5seen r/w 0 selects in5 single ended as an input to the line a mixer (wlp only). 0 in6seen r/w 0 selects in6 single ended as an input to the line b mixer (wlp only). mixg135 in1-in2 in3-in4 in5-in6 mic 1 mic 2 line a line b adc left mixer analog output mixers mixadr[6:0] mixadl[6:0] in1-in2 in3-in4 in5-in6 mic 1 mic 2 line a line b adc right mixer -6db to 20db -6db to 20db -6db / 0db -6db / 0db lineaen extbufa in2seen in4seen in6seen in65diff line a pga line b pga lineben extbufb linapga[2:0] line a input mixer mixg246 line b input mixer in3 in1 in1/dmd in2/dmc in6 in5 in3 in4 (wlp only) in3-in4 mic 1 mic 1 mic 2 mic 2 in5 in4 in2 in6-in5 in6 linbpga[2:0] in1seen in3seen in5seen in34diff max98090 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 90 table 22. external gain mode series resistance values differential input from in5 and in6 (in6 - in5). internally, all analog signal paths are differential. as a result, single- ended inputs have a built in baseline gain of +6db (from the single-ended to differential conversion) while differen - tial inputs have 0db of built in gain. the line input mixer can also be set to accept and mix any two single-ended inputs. to facilitate full-scale sig - nals, when mixing two single-ended inputs an optional -6db of attenuation is available (mixg135 and mixg246, table 23). the line input mixer attenuation setting has no effect if enabled when only a single input source is selected. if a differential input to either mixer is enabled, any single-ended inputs that are also selected are ignored, and the mixer accepts only the differential input. analog line input pgas to facilitate a wide range of input signal levels, each analog line input includes a coarse programmable gain amplifier (pga) that can provide from 6db of attenuation to 20db of signal gain. the line inputs are then routed to either the adc mixer (record) or analog outputs (playback). if the line input signal exceeds full scale and requires additional attenuation, the external gain mode provides trimmed internal feedback resistors (20k) for custom gain levels. line input external gain mode is not intended to provide positive gain, and as such for optimal perfor - mance any gain of -6db of higher should be set using the provided internal pga gain settings. differentially, the external line input gain is set by using two precision (1% or better), well-matched series input resistors (figure 10). use the following formula to calcu - late the appropriate differential series input resistors: a v_extline = 20 x log (20k/r s_ext ) for single-ended inputs, the external line input gain is set using a single precision (1% or better) series input resis - tor (figure 10). however, due to the internal single-ended to differential conversion, this configuration creates an unbalanced differential amplifier configuration (configured external gain paired with a fixed internal gain of +6db). table 22 provides the appropriate series resistance val - ues for common attenuation settings. figure 10. analog line input external gain configurations line input external gain (db) r s_ext differential (k?) single-ended (k?) a v_extline = -9.5 60 84.5 a v_extline = -12.0 80 115 a v_extline = -15.0 112 165 a v_extline = -18.0 160 237 r fb_int+ = 20k r fb_int - = 20k r s_ext- r s_ext+ v in_d if f+ v in_d if f- differential line input r fb_int+ = 20k r fb_int - = 30k r s_ext - = 15k r s_ext+ v in_s in gl e-ende d v co mmon_mo de single-ended line input line a pga line a pga max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 91 table 23. line input level configuration register table 24. input mode and source configuration register address: 0x0e description bit name type por 7 mixg135 r/w 0 enable for a -6db reduction for two single-ended line a mixer inputs 0: normal line a mixer operation. 1: gain is reduced by -6db when two single-ended inputs are selected. 6 mixg246 r/w 0 enable for a -6db reduction for two single-ended line b mixer inputs 0: normal line b mixer operation. 1: gain is reduced by -6db when two single-ended inputs are selected 5 linapga[2:0] r/w 0 line input a programmable internal preamp gain confguration 4 1 000: 20db 001: 14db 010: 3db 011: 0db 100: -3db 101, 110, 111: -6db 3 1 2 linbpga[2:0] r/w 0 line input b programmable internal preamp gain confguration 1 1 000: 20db 001: 14db 010: 3db 011: 0db 100: -3db 101, 110, 111: -6db 0 1 address: 0x0f description bit name type por 7 extbufa r/w 0 selects external resistor gain mode for line input a. 6 extbufb r/w 0 selects external resistor gain mode for line input b. 5 4 3 2 1 extmic[1:0] r/w 0 external microphone (in6, in5) input control confguration (wlp only) 00: ext_mic not selected. 10: ext_mic selected on mic 2. 01: ext_mic selected on mic 1. 11: ext_mic not selected. 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 92 analog input pga to analog output mixer the analog line input pga and analog microphone pga outputs can be routed directly to any of the analog out - put mixers. this configuration allows the analog inputs to operate as line or microphone level input amplifiers capable of driving headphone, speaker, receiver, or line output loads. the analog inputs can also be mixed with the dac outputs to any of the available analog output mixers. the figures in the appropriate analog input and output sections detail the signal routing. analog full-scale direct to adc mixer inputs the analog inputs can also be configured to accept and route differential analog signals directly to the adc mixers (record path, figure 11). by disabling and bypassing the analog microphone and line input gain stages, this mode provides a reduced power configuration for full-scale (up to 1v rms ) analog input signals. unlike the analog micro - phone and line input configurations, this mode does not allow the input signals to be routed directly to the analog output mixers (playback path, figure 31). figure 11. analog direct to adc mixer input functional diagram in1-in2 in3-in4 in5-in6 mic 1 mic 2 line a line b adc left mixer mixadr[6:0] mixadl[6:0] adlen adren in1-in2 in3-in4 in5-in6 mic 1 mic 2 line a line b adc right mixer in1/dmd in2/dmc in3 in4 in5 in6 (wlp only) adc left adc right max98090 flexsound technology dsp adchp osr128 adcdither max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 93 audio record path the device record path comprises several sequential blocks. the first block is a stereo adc with configurable mixers that can accept input from the microphone pgas, line input pgas, or directly differentially from any of the analog input pairs. internally, the digital record path has two channels (left and right), which accept a digital signal either from the appropriate digital microphone or adc output channel. the two channels then pass through sev - eral dsp stages before being routed into the digital audio interface (dai, figure 12). figure 12. record path block diagram digital mic left mux digmicl adc left adc right left filters mode ahpf dhf left biquad filter recbqen avbq[3:0] rec_b0[23:0] rec_b1[23:0] rec_b2[23:0] rec_a1[23:0] rec_a2[23:0] left sidetone dsts[1:0] dvst[3:0] flexsound technology dsp dmdl dmdr adcr adcl adchp osr128 adcdither avlg[2:0] avl[3:0] avrg[2:0] avr[3:0] digital mic right mux right filters digmicr right record path sidetone to playback path left record path right biquad filter right sidetone left level l /r st level right level mixadl[6:0] mixadr[6:0] in1-in2 digital mic data in3-in4 in5-in6 line a line b mic 1 mic 2 adc left mixer in1-in2 in3-in4 in5-in6 line a line b mic 1 mic 2 adc right mixer adlen adren dai max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 94 figure 13. record path adc section analog-to-digital converter (adc) the stereo adc architecture includes two independent audio paths and provides a flexible, fully configurable input mixer, two performance and power based con - figuration options, oversampling rate selection, and an input dither option (figure 13). both adc channels can be enabled independently allowing the device to support both stereo and left or right mono configurations (table 7). adc functional confguration the adc can be configured into one of two operating modes. one operating mode is optimized for maximum dynamic performance while the other is optimized for lower power consumption (table 5). input dither can also be added to the adc record path. this feature consumes almost no appreciable power, but raises the rms level of the noise floor slightly at the high end of the audio band. the adc supports both an over sampling rate (osr) of 64 and 128 times the configured sampling frequency (f s ). an osr of 128 x f s optimizes adc performance at the cost of slightly more power consumption than an osr of 64 x f s . the dsp timing, however, places some limitations on which osr can be used. for voice applications using standard (f s = 8khz) and wideband (f s = 16khz) sampling rates, the dsp is typically configured to utilize the voice filters (iir). if the voice filters are enabled, the osr is automatically configured to 128 x f s and cannot be manu - ally reprogrammed in order to meet timing requirements. in most standard music/full audio range applications (where f s = 32khz, 44.1khz, 48khz, etc.) the music filters (fir) are used. if the music filters are enabled, the osr can be configured manually, however, the prescaled mas - ter clock (pclk) must always be at least twice the fre - quency of the adc sampling clock. to ensure this condi - tion is met, if f pclk < 256 x f s , then the osr must be set to 64 x f s . in addition, if the sampling rate exceeds 50khz (dhf = 1, such as f s = 96khz), then the osr must be configured to 64 x f s regardless of the ratio. in any other music filter configuration, osr = 128 can be selected as desired for optimal adc performance. digital mic left mux digmicl adc left adc right left filters mode ahpf dhf left biquad filter recbqen avbq[3:0] rec_b0[23:0] rec_b1[23:0] rec_b2[23:0] rec_a1[23:0] rec_a2[23:0] left sidetone dsts[1:0] dvst[3:0] flexsound technology dsp dmdl dmdr adcr adcl adchp osr128 adcdither avlg[2:0] avl[3:0] avrg[2:0] avr[3:0] digital mic right mux right filters digmicr right record path sidetone to playback path left record path right biquad filter right sidetone left level l /r st level right level mixadl[6:0] mixadr[6:0] in1-in2 digital mic data in3-in4 in5-in6 line a line b mic 1 mic 2 adc left mixer in1-in2 in3-in4 in5-in6 line a line b mic 1 mic 2 adc right mixer adlen adren dai max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 95 table 26. right adc mixer input configuration register adc input mixer confguration the device allows for each adc input mixer to be con - figured separately to accept any combination of valid input sources. the adc mixers can accept input from the microphone pgas (1 or 2), line input pgas (a or b), or directly differentially from any of the analog input pairs (in1/in2, in3/in4, or in5/in6). the adc input mixers then route the selected sources to the left and right adc inputs (tables 25 and table 26). record path flexsound dsp the digital record path is part of the flexsound tech - nology dsp and comprises multiple sequential dsp blocks. the first dsp stage contains digital filters includ - ing a voice filter (iir), music filter (fir), and a highpass dc-blocking filter. the next stage is a digital biquad filter with a pre-attenuation amplifier, and it is followed by a digital gain and level control stage. the record path dsp also features a digital sidetone path that is routed to and mixed into the digital playback path (figure 14). record path digital filters the record path dsp includes a digital filter stage. one filter, set with the mode bit (table 27), offers the choice between the iir voice filters and the fir music filters. the iir filters are optimized for standard (f s = 8khz) and wide - band (f s = 16khz) voice applications, while the fir filters are optimized for low power operation at higher audio/ music sampling rates. for sampling rates in excess of 50khz (f lrclk > 50khz), use the fir audio filters and set the dhf bit. the mode configuration selected applies to both channels of both the record and playback path dsp. the record path dsp also features a dc-blocking filter. this filter can be used with both the iir voice and fir music filters, and blocks low frequency (including dc) input signals outside of the lower end of the audio band. table 25. left adc mixer input configuration register address: 0x16 description bit name type por 7 6 mixadr[6:0] r/w 0 selects microphone input 2 to right adc mixer. 5 r/w 0 selects microphone input 1 to right adc mixer. 4 r/w 0 selects line input b to right adc mixer. 3 r/w 0 selects line input a to right adc mixer. 2 r/w 0 selects in5/in6 differential input direct to right adc mixer (wlp only). 1 r/w 0 selects in3/in4 differential input direct to right adc mixer. 0 r/w 0 selects in1/in2 differential input direct to right adc mixer. address: 0x15 description bit name type por 7 6 mixadl[6:0] r/w 0 selects microphone input 2 to left adc mixer. 5 r/w 0 selects microphone input 1 to left adc mixer. 4 r/w 0 selects line input b to left adc mixer. 3 r/w 0 selects line input a to left adc mixer. 2 r/w 0 selects in5/in6 differential input direct to left adc mixer (wlp only). 1 r/w 0 selects in3/in4 differential input direct to left adc mixer. 0 r/w 0 selects in1/in2 differential input direct to left adc mixer. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 96 table 27. dsp filter configuration register figure 14. record path flexsound technology dsp block address: 0x26 description bit name type por 7 mode r/w 1 enables the codec dsp fir music filters (default iir voice filters) 0: the codec dsp flters operate in iir voice mode with stop band frequencies below the f s /2 nyquist rate. the voice mode flters are optimized for 8khz or 16khz voice application use. 1: the codec dsp flters operate in a linear phase fir audio mode optimized to maintain stereo imaging and operate at higher f s rates while utilizing lower power. 6 ahpf r/w 0 enables the record path dc-blocking filter 0: dc-blocking flter disabled. 1: dc-blocking flter enabled. 5 dhpf r/w 0 enables the playback path dc-blocking filter 0: dc-blocking flter disabled. 1: dc-blocking flter enabled. 4 dhf r/w 0 enables the dac high sample rate mode (lrclk > 50khz, fir only) 0: lrclk is less than 50khz. 8x fir interpolation flter used. 1: lrclk is greater than 50khz. 4x fir interpolation flter used. 3 2 1 0 digital mic left mux digmicl left filters mode ahpf dhf left biquad filter recbqen avbq[3:0] rec_b0[23:0] rec_b1[23:0] rec_b2[23:0] rec_a1[23:0] rec_a2[23:0] left sidetone dsts[1:0] dvst[3:0] flexsound technology dsp avlg[2:0] avl[3:0] avrg[2:0] avr[3:0] digital mic right mux right filters digmicr right record path sidetone to playback path left record path right biquad filter right sidetone left level l /r st level right level dai adc left adc right dmdl dmdr adcr adcl adchp osr128 adcdither mixadl[6:0] mixadr[6:0] in1-in2 digital mic data in3-in4 in5-in6 line a line b mic 1 mic 2 adc left mixer in1-in2 in3-in4 in5-in6 line a line b mic 1 mic 2 adc right mixer adlen adren max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 97 table 28. dsp biquad filter enable register table 29. record path biquad digital preamplifier level configuration register record path biquad filter the record path dsp has a single stage digital biquad fil - ter with a programmable preattenuation amplifier. the dig - ital biquad filter configuration applies to both the left and right record channels. to enable the record path biquad filter, set recbqen high (table 28). once enabled, the level of preattenuation can be adjusted from 0db down to -15db (denoted a v_bq , see table 29). the digital biquad filter cannot be set to a gain greater than 12db, to a q greater than 10, or to below a minimum f c that varies by filter type. see the electrical characteristics table. the digital biquad coefficients are uninitialized at power- up, and if the filter is going to be used, the coefficients must be programmed before the device and biquad filter are enabled. the transfer function is: 12 01 2 12 01 2 b bz b z h( z ) a az a z ?? ?? + + = + + address: 0x41 description bit name type por 7 6 5 4 3 recbqen r/w 0 enable biquad filter in record path 0: biquad flter not used. 1: biquad flter used in record path. 2 eq3banden r/w 0 enable 3-band eq in playback path (bands 4C7 are not used) 0: 3-band eq disabled. 1: 3-band eq enabled. only valid if eq7banden = 0 and eq5banden = 0. 1 eq5banden r/w 0 enable 5-band eq in playback path (bands 6 and 7 are not used) 0: 5-band eq disabled. 1: 5-band eq enabled. only valid if eq7banden = 0 0 eq7banden r/w 0 enable 7-band eq in playback path 0 : 7-band eq disabled. 1 : 7-band eq enabled. this makes eq5banden and eq3banden redundant. address: 0x19 description bit name type por 7 6 5 4 3 avbq[3:0] r/w 0 adc biquad digital preamplifer gain confguration 2 0 0x0: +0db 0x1: -1db 0x2: -2db 0x3: -3db 0x4: -4db 0x5: -5db 0x6: -6db 0x7: -7db 0x8: -8db 0x9: -9db 0xa: -10db 0xb: -11db 0xc: -12db 0xd: -13db 0xe: -14db 0xf: -15db 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 98 table 30. record path biquad filter coefficient the digital biquad filter has five user-programmable coefficients (b 0 , b 1 , b 2 , a 1 , and a 2 ), and each individual coefficient is 3 bytes (24 bits) long (a 0 is fixed at 1). they occupy 15 consecutive registers (table 30) and each set of three registers (per coefficient) must be programmed consecutively for the settings to take effect. the coeffi - cients are stored using a twos complement format where the first 4 bits are the integer portion and the last 20 bits are the decimal portion (which results in an approximate +8 to -8 range for each coefficient). record path sidetone the record path sidetone is available to allow a low-level copy of the recorded audio signal to be mixed back into the playback audio signal. when enabled, the sidetone can route the left channel, right channel, or both divided by two and then summed back into the playback path dsp. the sidetone digital gain can be programmed from -0.5db to -60.5db (table 31). the digital sidetone is com - monly used in telephony to allow the speaker to hear their own voice to provide a more natural user experience. table 31. record path sidetone configuration register address range name type coefficient segment 0xaf 0xb0 0xb1 record biquad coeffcient b0 r/w rec_b0[23:16] rec_b0[15:8] rec_b0[7:0] 0xb2 0xb3 0xb4 record biquad coeffcient b1 r/w rec_b1[23:16] rec_b1[15:8] rec_b1[7:0] 0xb5 0xb6 0xb7 record biquad coeffcient b2 r/w rec_b2[23:16] rec_b2[15:8] rec_b2[7:0] 0xb8 0xb9 0xba record biquad coeffcient a1 r/w rec_a1[23:16] rec_a1[15:8] rec_a1[7:0] 0xbb 0xbc 0xbd record biquad coeffcient a2 r/w rec_a2[23:16] rec_a2[15:8] rec_a2[7:0] address: 0x1a description bit name type por 7 dsts[1:0] 0 sidetone enable and digital source confguration 00: no sidetone selected 10: right channel 01: left channel 11: left + right channel 6 0 5 4 dvst[4:0] r/w 0 sidetone digital gain confguration 3 0 0x00: off 0x01: -0.5db 0x02: -2.5db 0x03: -4.5db 0x04: -6.5db 0x05: -8.5db 0x06: -10.5db 0x07: -12.5db 0x08: -14.5db 0x09: -16.5db 0x0a: -18.5db 0x0b: -20.5db 0x0c: -22.5db 0x0d: -24.5db 0x0e: -26.5db 0x0f: -28.5db 0x10: -30.5db 0x11: -32.5db 0x12: -34.5db 0x13: -36.5db 0x14: -38.5db 0x15: -40.5db 0x16: -42.5db 0x17: -44.5db 0x18: -46.5db 0x19: -48.5db 0x1a: -50.5db 0x1b: -52.5db 0x1c: -54.5db 0x1d: -56.5db 0x1e: -58.5db 0x1f: -60.5db 2 0 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 99 record path digital gain and level control the stereo record path dsp includes a digital gain and level control stage. the settings can be configured independently by channel, and are primarily used when adjusting the record level for digital microphones. the coarse digital gain adjustment can be set from 0db to +42db in 6db increments, and the fine adjust level control gain can be set from -12db to +3db in 1db increments (tables 32 and 33). table 33. right record path digital gain configuration register table 32. left record path digital gain configuration register address: 0x18 description bit name type por 7 6 avrg[2:0] r/w 0 right record path digital coarse gain confguration 000 : 0db 010 : +12db 100 : +24db 110 : +36db 001 : +6db 011 : +18db 101 : +30db 111 : +42db 5 0 4 0 3 avr[3:0] r/w 0 right record path digital fine adjust gain confguration 0x0: +3db 0x4: -1db 0x8: -5db 0xc: -9db 0x1: +2db 0x5: -2db 0x9: -6db 0xd: -10db 0x2: +1db 0x6: -3db 0xa: -7db 0xe: -11db 0x3: +0db 0x7: -4db 0xb: -8db 0xf: -12db 2 0 1 1 0 1 address: 0x17 description bit name type por 7 6 avlg[2:0] r/w 0 left record path digital coarse gain confguration 000 : 0db 010 : +12db 100 : +24db 110 : +36db 001 : +6db 011 : +18db 101 : +30db 111 : +42db 5 0 4 0 3 avl[3:0] r/w 0 left record path digital fine adjust gain confguration 0x0: +3db 0x4: -1db 0x8: -5db 0xc: -9db 0x1: +2db 0x5: -2db 0x9: -6db 0xd: -10db 0x2: +1db 0x6: -3db 0xa: -7db 0xe: -11db 0x3: +0db 0x7: -4db 0xb: -8db 0xf: -12db 2 0 1 1 0 1 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 100 figure 15. simplified digital audio interface block diagram digital audio interface (dai) confguration the digital audio interface (dai) contains two primary sec - tions (figure 15). the first is the clock control and configu - ration section. the device supports both master and slave mode operation, can accept a master clock of either 256 x f s or ranging from 10mhz to 60mhz, and can be config - ured for any digital audio sampling rate (f s ) from 8khz to 96khz. when the device is configured as the digital audio master, a variety of operating modes are available. these include a simple quick configuration mode, exact integer sampling mode, and a manual clock divider mode. when the device is configured to slave mode, the internal pll quickly locks onto the external lrclk frequency. the second section is the digital audio data path control and signal routing. this section supports a variety of ste - reo data path configurations including serial audio input and output, audio loop through from the record to play - back paths, and audio loop back from the serial data input to the serial data output. the serial data interface also supports several standard digital audio formats (pcm) including i 2 s, left justified, right justified, and time division multiplexed (tdm). prescaled clock generation frame clock bit clock data output enable output shift register input shift register data input enable playback input mixer loop back mux loop through mux sdoen hizoff rj, dly ws[1:0] tdm, fsw slotdly[3:0] slotl/r[1:0] bci wci mas mclk lrclk pll and clock generation bclk dai: clock control and configuration dai: data path digital mic clock configuratio n to adc clock generation l/r audio output record path dsp psclk[1:0] pclk sdout sdin lten 1 01 0 dmono sdien lben freq[3:0] use_mi ni[14:0] mi[14:0] max98090 to dac clock generation l/r audio input playback path dsp bsel[2:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 101 figure 16. dai clock control and configuration section dai clock control and confguration the clock control and configuration section is one of the two major blocks in the digital audio interface (figure 16). this section is responsible for accepting and scaling the device master clock, for internal digital clock generation, and for digital audio interface data clocking and timing. the device can accept an external master clock (mclk) with a frequency ranging from 10mhz to 60mhz. however, for digital operation, signal processing, and data conver - sion the device requires an internal clock between 10mhz and 20mhz. to generate an internal master clock within this frequency range, an internal clock divider is used (table 34). the internal clock divider can be set to fre - quency divide mclk by a factor 1, 2, or 4 to create the internal prescaled master clock (pclk). pclk is then used, either directly or through additional divider/multiplier blocks, to clock all internal digital sections. the digital audio interface signal paths support any sam - pling rate from 8khz to 96khz. the device has only a single dai, and as a result both the record (output) and playback (input) digital audio paths use the same sampling rate. the device digital audio interface supports both master and slave mode operation (table 35). to properly time the serial data input (sdin) and output (sdout), the dai requires both a left-right frame clock (lrclk) and a bit clock (bclk). in master mode, the device uses one of several modes to generate both lrclk and bclk from the internal prescaled master clock (pclk). in slave mode however, both lrclk and bclk must be exter - nally provided. master mode clock confguration when the device is configured as the digital audio mas - ter, the frame clock (lrclk) and bit clock (bclk) are configured as outputs and the device uses the internal prescaled master clock (pclk) to create them. if no clock outputs or unexpected clock outputs are mea - sured on lrclk and/or bclk, verify that the device is not in shutdown and that all three clocks are configured cor - rectly. if the master clock prescale value is not selected (psclk[1:0]), the clock ratio is not fully configured (oper - ating mode), or if the bit clock rate is not set (bsel[2:0]) prescaled clock generation frame clock bit clock bci wci mas mclk lrclk pll and clock generation bclk dai: clock control and configuration digital mic clock configuratio n to adc clock generation l/r audio output record path dsp psclk[1:0] pclk sdout sdin freq[3:0] use_mi ni[14:0] mi[14:0] max98090 to dac clock generation l/r audio input playback path dsp bsel[2:0] data output enable output shift register input shift register data input enable playback input mixer loop back mux loop through mux sdoen hizoff rj, dly ws[1:0] tdm, fsw slotdly[3:0] slotl/r[1:0] dai: data path lten 1 01 0 dmono sdien lben max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 102 table 34. system master clock (mclk) prescaler configuration register table 35. master mode clock configuration register then no valid clock output is present. in addition to this, the device does not generate any clocks unless at least one valid digital audio data path is enabled (adc record, dac playback, digital microphone input, etc.). in master mode, the device uses two integer values (ni and mi) as a multiplier and divider (respectively) to scale pclk into lrclk. bclk is then created either from a pclk divider or from an lrclk multiplier (table 35). based on the oversampling rate selected (osr, see the adc functional configuration section), and the config - ured ni/mi ratio, the output lrclk frequency is calcu - lated with the following relationship: lrclk pclk ni ff mi osr = this expression illustrates that in master mode, the rela - tionship between lrclk and pclk frequency (as well as bclk) is based on an integer ratio. as a result, any cycle to cycle jitter or absolute frequency variation in mclk is translated first into pclk and then into lrclk (and bclk) based on the selected clock ratios. address: 0x1b description bit name type por 7 6 5 psclk[1:0] r/w 0 master clock (mclk) prescaler confguration 00: internal master clock generation disabled 01: f pclk = f mclk /1, 10mhz f mclk 20mhz 10: f pclk = f mclk /2, 20mhz < f mclk 40mhz 11: f pclk = f mclk /4, 40mhz < f mclk 60mhz 4 0 3 2 1 0 address: 0x21 description bit name type por 7 mas r/w 0 master mode enable 0: slave mode (lrclk/bclk are inputs and accept external clock sources). 1: master mode (lrclk/bclk are outputs and timing signals are generated internally). 6 5 4 3 2 bsel[2:0] r/w 0 bit clock (bclk) confguration (master mode/slave right justifed only) 000: bit clock disabled 100: f bclk = f pclk /2 001: f bclk = 32 x f s 101: f bclk = f pclk /4 010: f bclk = 48 x f s 110: f bclk = f pclk /8 011: f bclk = 64 x f s 111: f bclk = f pclk /16 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 103 in master mode, the device provides three clock operating modes. in reality all three modes operate in exactly the same manner (using an internal mi and ni ratio to create lrclk). however, the first two modes will internally set ni and mi automatically and are provided as configura - tion shortcuts for commonly used pclk to lrclk ratios. the three operating modes are detailed below, and are presented in order of activation priority. quick confguration mode in quick configuration mode, the master clock frequency (table 36) and sample rate (table 37) are selected from a list of commonly used frequencies. only a single bit in each quick setup register can be enabled at any given time. quick configuration mode is activated anytime that both a master clock frequency quick setup bit and a sample rate quick setup bit are concurrently enabled. once enabled, this mode supersedes both of the other operating modes and an internal preset ratio for ni and mi is used to create lrclk. as a result, when quick configuration mode is enabled the exact integer mode settings (table 32), and the manual ratio mode settings (tables 33 to 36) are preserved but ignored. if this mode is later disabled, the preserved settings of any active lower precedence modes reassert. to ensure that the dsp is optimally configured and that all timing requirements are met, when using quick configura - tion mode the master clock divider (psclk, table 34), digital filters (mode, table 27), and adc oversampling rate (osr128,table 5) are automatically configured. while in quick configuration mode these registers are table 36. master clock quick setup register table 37. sample rate quick setup register address: 0x04 description bit name type por 7 26m r/w 0 setup device for operation with a 26mhz master clock (mclk). 6 19p2m r/w 0 setup device for operation with a 19.2mhz master clock (mclk). 5 13m r/w 0 setup device for operation with a 13mhz master clock (mclk). 4 12p288m r/w 0 setup device for operation with a 12.288mhz master clock (mclk). 3 12m r/w 0 setup device for operation with a 12mhz master clock (mclk). 2 11p2896m r/w 0 setup device for operation with a 11.2896mhz master clock (mclk). 1 0 256f s r/w 0 setup device for operation with a 256 x f s mhz master clock (mclk) address: 0x05 description bit name type por 7 6 5 sr_96k r/w 0 setup clocks and flters for a 96khz sample rate. 4 sr_32k r/w 0 setup clocks and flters for a 32khz sample fate. 3 sr_48k r/w 0 setup clocks and flters for a 48khz sample rate. 2 sr_44k1 r/w 0 setup clocks and flters for a 44.1khz sample rate. 1 sr_16k r/w 0 setup clocks and flters for a 16khz sample rate. 0 sr_8k r/w 0 setup clocks and flters for an 8khz sample rate. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 104 table 38. quick configuration mode lookup fixed and cannot be manually changed. in this mode, when the sample rate is set to 8khz or 16khz, voice filters (iir) are automatically selected and the adc oversam - pling rate is fixed to 128. for any other selected sample rate, music filters (fir) are selected and the adc overs - ampling rate is configured to insure that the pre-scaled master clock frequency is greater than or equal to 256 x fs. if f pclk 256 x f s then the oversampling rate (osr) is set to 128, otherwise osr is set to 64. table 38 provides a complete lookup table for the resulting quick configura - tion mode settings. exact integer mode in exact integer mode, the master clock frequency and sam - ple rate can be set to one of eight preprogrammed combi - nations (table 39). there are four different available mas - ter clock frequencies (12mhz/13mhz/16mhz/19.2mhz), each of which can be selected with a sampling rate (f s ) of either 8khz or 16khz. once a configuration is selected, the ni and mi bits are internally programmed to the cor - rect ratio. these combinations are primarily intended for standard or wideband voice applications. table 39. clock mode configuration register selected master clock frequency selected sample rate (khz) 8 16 32 44.1 48 96 f mclk divider f pclk voice filter (iir) music filter (fir) 26mhz 2 13mhz osr = 128 osr = 128 osr = 128 osr = 128 osr = 128 osr = 64 19.2mhz 1 19.2mhz osr = 128 osr = 128 osr = 128 osr = 128 osr = 128 osr = 64 13mhz 1 13mhz osr = 128 osr = 128 osr = 128 osr = 128 osr = 128 osr = 64 12.288mhz 1 12.288mhz osr = 128 osr = 128 osr = 128 osr = 128 osr = 128 osr = 64 12mhz 1 12mhz osr = 128 osr = 128 osr = 128 osr = 128 osr = 128 osr = 64 11.2896mhz 1 11.2896mhz osr = 128 osr = 128 osr = 128 osr = 128 osr = 64 osr = 64 256 x f s 1 256 x f s osr = 128 osr = 128 osr = 128 osr = 128 osr = 64 2 128 x f s osr = 64 address: 0x1c description bit name type por 7 freq[3:0] r/w 0 exact integer sampling frequency (lrclk) confguration confgure the dai for specifc pclk to lrclk ratios for f s = 8khz/16khz operation (voice modes). any setting other than 0x0 overrides manual ratio mode settings. 0000: disabled 1xxx: enabled other combinations are reserved when enabled, the following pclk to lrclk ratios are available: 1000: f pclk = 12mhz, f lrclk = 8khz 1001: f pclk = 12mhz, f lrclk = 16khz 1010: f pclk = 13mhz, f lrclk = 8khz 1011: f pclk = 13mhz, f lrclk = 16khz 1100: f pclk = 16mhz, f lrclk = 8khz 1101: f pclk = 16mhz, f lrclk = 16khz 1110: f pclk = 19.2mhz, f lrclk = 8khz 1111: f pclk = 19.2mhz, f lrclk = 16khz 6 0 5 0 4 0 3 2 1 0 use_mi r/w 0 use mi[15:0] in addition to ni[14:0] to set an accurate frequency ratio 0 : mi = 65536; ni = (f lrclk / f pclk ) x 65536 x 96 1 : mi is set to the value of mi[15:0] ( table 35 and table 36). max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 105 when freq[3:0] register is set to 0 (freq[3:0] = 0000), exact integer mode is disabled. when the msb is set to 1 (freq[3:0] = 1xxx) exact integer mode is enabled and the remaining bits determine which setting is selected (table 39). if exact integer mode is enabled, the manual ratio mode settings (tables 33 to 36) are preserved but ignored. however, if this mode is later disabled, the manual ratio mode settings reassert. manual ratio mode in manual ratio mode, the ni and mi registers (table 40 to table 43) are directly programmed to set up the clock ratio. manual ratio mode is only active when the quick configuration and exact integer modes are disabled. in manual ratio mode, if use_mi (table 39) is set to 0, mi is fixed at its maximum value of 0xffff (65536) and the programmed value has no effect. for optimal perfor - mance (especially with any noninteger pclk to lrclk ratio), set use_mi to 1 and calculate both mi and ni. to calculate the appropriate ni and mi value, use the fol - lowing method: 1) choose the over sampling rate (osr). if f pclk < 256 x f lrclk , then osr must be set to 64. otherwise, osr can be set to either 128 or 64. for optimal per - formance, choose osr = 128 when possible. 2) calculate the oversampling frequency using the lrclk frequency, and the selected oversampling rate: f osr = f lrclk x osr. 3) calculate mi using the prescaled master clock fre - quency, and the greatest common denominator (gcd) of the prescaled master clock frequency and the cal - culated oversampling frequency: mi = f pclk / gcd(f pclk , f osr ) 4) calculate ni using the calculated oversampling fre - quency and mi value: ni = f osr x mi/f pclk slave mode clock confguration when the device is configured as a digital audio slave, the frame clock (lrclk) and bit clock (bclk) are configured as external inputs. these inputs accept an externally generated frame and bit clock, and then an internal pll determines the correct pclk to lrclk frequency ratio. within a few lrclk cycles, the internal pll is locked onto the clock ratio and then automatically programs the internal divider ratio appropriately. in slave mode, the clock generation register settings have no effect (quick configuration, exact integer, and manual ratio mode settings have no effect). the correct mclk to pclk scaling factor, mode (voice/audio), and oversam - pling rate still need to be programmed. however, all other clock configuration settings are for master mode only. the only exception to this is when the digital audio format is set to slave mode operation with right justified data. in this configuration, the bclk setting (bsel[2:0], table 29) is used to determine the number of leading padding bits (bclk cycles) to insert (skip) before the data transmis - sion/receiving in each frame. table 40. manual clock ratio configuration register (ni msb) address: 0x1d description bit name type por 7 6 ni[14:8] r/w 0 upper half of the pll n value used in master mode clock generation to calculate the frequency ratio (manual ratio master mode). 5 0 4 0 3 0 2 0 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 106 table 41. manual clock ratio configuration register (ni lsb) table 42. manual clock ratio configuration register (mi msb) table 43. manual clock ratio configuration register (mi msb) address: 0x1e description bit name type por 7 ni[7:0] r/w 0 lower half of the pll n value used in master mode clock generation to calculate the frequency ratio (manual ratio master mode). 6 0 5 0 4 0 3 0 2 0 1 0 0 0 address: 0x1f description bit name type por 7 mi[15:8] r/w 0 upper half of the pll m value used in master mode clock generation to calculate an accurate noninteger frequency ratio (manual ratio master mode). 6 0 5 0 4 0 3 0 2 0 1 0 0 0 address: 0x20 description bit name type por 7 mi[7:0] r/w 0 lower half of the pll m value used in master mode clock generation to calculate an accurate noninteger frequency ratio (manual ratio master mode). 6 0 5 0 4 0 3 0 2 0 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 107 dai digital audio data path control and routing the digital audio data path section supports a variety of stereo data path configurations and formats (figure 17). the standard configuration is to route either the record path digital audio output to the serial data output (record path to sdout) or to route the serial data input to the dig - ital audio playback path (sdin to playback path). these two primary configurations can be used either individually or together as needed by the application. the dai data path also supports two loop configurations. loop back mode takes the digital audio serial data input and routes it back to the serial data output (sdin to sdout). loop through mode allows the record path audio data output to be looped through to the digital audio play - back path (and can be combined with the record path to sdout configuration if desired). the configuration settings for all valid data path combinations are detailed in table 44 and are illustrated in figure 18. sdout can be configured to go to either a high imped - ance state or to drive a valid logic level (lsb) after all data bits have been transmitted. when high impedance mode is enabled, sdout goes to a high-impedance state quickly after the bclk edge for the lsb occurs to avoid potential bus contention. sdin/loopthrough audio data can be routed through the playback path input mixer as either stereo audio data, or as a mono representation of the input audio data. by default, playback mono mode is disabled and the left/right input audio data is routed to the left/right playback channels respectively. if playback mono mode is enabled, the input audio data channels are reduced in amplitude by 6db, mixed together (summed), and then routed to both the left and right record path channels. the full list of dai data path configuration con - trol bits are detailed in table 45. figure 17. dai digital data path configuration prescaled clock generation frame clock bit clock bci wci mas mclk lrclk pll and clock generation bclk dai: clock control and configuration to adc clock generation psclk[1:0] pclk freq[3:0] use_mi ni[14:0] mi[14:0] max98090 to dac clock generation bsel[2:0] digital mic clock configuratio n l/r audio output record path dsp sdout sdin l/r audio input playback path dsp data output enable output shift register input shift register data input enable playback input mixer loop back mux loop through mux sdoen hizoff rj, dly ws[1:0] tdm, fsw slotdly[3:0] slotl/r[1:0] dai: data path lten 1 01 0 dmono sdien lben max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 108 figure 18. digital audio interface (dai) data path configurations loop back mux da ta inpu t enable output shift register input shift register sdout sdin l/r audio (pla yback) l/r audio (record) loop through mux pla yback input mixer pat h 1: record da ta output enable loop back mux da ta inpu t enable output shift register input shift register sdout sdin l/r audio (pla yback) l/r audio (record) loop through mux pla yback input mixer pat h 2: pla yback da ta output enable loop back mux da ta inpu t enable output shift register input shift register sdout sdin l/r audio (pla yback) l/r audio (record) loop through mux pla yback input mixer pat h 3: full duplex da ta output enable loop back mux da ta inpu t enable output shift register input shift register sdout sdin l/r audio (pla yback) l/r audio (record) loop through mux pla yback input mixer pat h 4: pla yback/ loop back da ta output enable loop back mux da ta inpu t enable output shift register input shift register sdout sdin l/r audio (pla yback) l/r audio (record) loop through mux pla yback input mixer pat h 5: loop through da ta output enable loop back mux da ta inpu t enable output shift register input shift register sdout sdin l/r audio (pla yback) l/r audio (record) loop through mux pla yback input mixer pat h 6: record/ loop through da ta output enable max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 109 table 44. digital audio interface (dai) data path configurations table 45. digital audio interface (dai) input/output configuration register dai data path configuration path description sdoen sdien lten lben dai data path disabled 0 0 0 0 1 record path to serial data output 1 0 0 0 2 serial data input to playback path 0 1 0 0 3 record path to serial data output/serial data input to playback path 1 1 0 0 4 serial data input loop back to serial data output 1 1 0 1 5 record path loop through to playback path 0 1 1 0 6 record path to serial data output and loop through to playback path 1 1 1 0 invalid confgurations all other combinations address: 0x25 description bit name type por 7 6 5 lten r/w 0 enables data loop through (playback path to record path) 1: adc to dac loop-through enabled. 0: adc to dac loop-through disabled. 4 lben r/w 0 enables data loop back (sdin to sdout) 1: dai sdin used as sdout data source. 0: adc used as sdout data source. 3 dmono r/w 0 enables playback mono mode (sdin l/2 + r/2 to playback path) 1: the left- and right-channel sdin audio input data are reduced in gain by 6db, mixed together (summed), and routed to both the left and right record paths. 0: the left- and right-channel sdin audio input data are routed to the left and right record path channels. 2 hizoff r/w 0 disables hi-z mode for sdout 1: sdout drives a valid logic level after all data bits have been transmitted. 0: sdout goes to a high-impedance state after all data bits have been transmitted, allowing the sdout bus to be shared by other devices. 1 sdoen r/w 0 enables the serial data output (sdout) 1: serial data output enabled. 0: serial data output disabled. 0 sdien r/w 0 enables the serial data input (sdin/loop-through) 1: serial data input enabled. 0: serial data input disabled. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 110 dai digital audio data format the serial data interface supports multiple pulse code mod - ulated (pcm) digital audio formats including i 2 s, left justi - fied, right justified, and time division multiplexed (tdm). if tdm mode is enabled, it takes precedence and the dai data is in tdm format. in this case, all non-tdm digital audio data format configuration registers have no effect. if tdm mode is disabled, then the data format is deter - mined by the configuration selected by the control bits detailed in table 46. these settings can be used to change the dai data format to several supported stan - dards such as i 2 s (figure 19), left justified (figure 20) or right justified (figure 21). in addition, the configuration settings can be enabled or disabled independently, allow - ing the device to support many nonstandard data format variations. table 46. digital audio interface (dai) format configuration register address: 0x22 description bit name type por 7 6 5 rj r/w 0 confgures the dai for right justifed mode (no data delay) 0: left justifed mode enabled with optional data delay. 1: right justifed mode enabled. dly register is not used and bsel[2:0] is used to determine the timing (see the dai clock control and confguration section for details). note: tdm has priority over all other data formats. 4 wci r/w 0 confgures the dai for frame clock (lrclk) inversion tdm = 0: 1: right-channel data is transmitted while lrclk is low. 0: left-channel data is transmitted while lrclk is low. tdm = 1: 0: start of a new frame is signifed by the rising edge of the lrclk pulse. 1: start of a new frame is signifed by the falling edge of the lrclk pulse. 3 bci r/w 0 confgures the dai for bit clock (bclk) inversion 1: sdin is accepted on the falling edge of bclk. 0: sdin is accepted on the rising edge of bclk. master mode: 1: lrclk transitions occur on the rising edge of bclk. 0: lrclk transitions occur on the falling edge of bclk. 2 dly r/w 0 confgures the dai for data delay (i 2 s standard) 1: the most signifcant bit of an audio word is latched at the second bclk edge after the lrclk transition. 0: the most signifcant bit of an audio word is latched at the frst bclk edge after the lrclk transition. set dly = 1 to conform to the i 2 s standard. dly is only effective when tdm = 0. 1 ws[1:0] r/w 0 dai input data word size if rj = 1: 00: 16 bits 10: 24 bits 01: 20 bits 11: reserved if rj = 0: 00: 16 bits 01, 10, 11: 20 bits 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 111 figure 19. dai timing for i 2 s data format figure 20. dai timing for left justified data formats d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi zh iz hi z i 2 s mode (tdm = 0, wci = 0, bc i = 0, dly = 1, rj = 0, w s[1:0] = 00, hi zo ff = 0) lrcl k bc lk sd ou t ri gh t le ft sd in left justified mode ? standard (tdm = 0, wci = 1, bci = 0, dly = 0, rj = 0, ws[1:0] = 00, hizoff = 0) lrcl k left bc lk sd ou t ri gh t left ri gh t left ri gh t sd in left justified mode ? lrlck inverted (tdm = 0, wci = 0, bci = 0, dly = 0, rj = 0, ws[1:0] = 00, hizoff = 0) lrcl k bc lk sd ou t sd in lrcl k bc lk sd ou t sd in left justified mode ? bclk inverted (tdm = 0, wci = 1, bci = 1, dly = 0, rj = 0, ws[1:0] = 00, hizoff = 0) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi zh iz hi z hi zh iz hi z d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi zh iz hi z max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 112 figure 21. dai timing for right justified data formats lrcl k bc lk sd ou t sd in lrcl k bc lk sd ou t sd in lrcl k bc lk sd ou t sd in right justified mode ? standard (tdm = 0, wci = 1, bci = 0, dly = 0, rj = 1, ws[1:0] = 00, hizoff = 0) right justified mode ? lrclk inverted (tdm = 0, wci = 0, bci = 0, dly = 0, rj = 1, ws[1:0] = 00, hizoff = 0) right justified mode ? bclk inverted (tdm = 0, wci = 1, bci = 1, dly = 0, rj = 1, ws[1:0] = 00, hizoff = 0) left ri gh t d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi zh iz hi z left ri gh t d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi zh iz hi z left ri gh t d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi zh iz hi z max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 113 table 47. digital audio interface (dai) tdm control register table 48. digital audio interface (dai) tdm format register tdm mode data format if tdm mode is enabled (table 47), the register settings in table 39 have no effect. tdm mode supports up to four mono audio time slots in each frame. however, internally, the device only has two digital audio channels (left and right) that can be assigned to any two of the four available time frames (table 48). the remaining two time slots remain free for another device to utilize. a data delay can be set individually for each time frame, and when operat - ing in master mode the frame sync pulse can be set to transmit for either a single bit or an entire word in length. tdm mode timing for common configuration options is detailed in figure 22. address: 0x23 description bit name type por 7 6 5 4 3 2 1 fsw r/w 0 confgures the dai frame sync pulse width (tdm = 1 and mas = 1) 1: frame sync pulse extended to the width of the entire data word. 0: frame sync pulse is one bit wide. note: in slave mode, the device accepts a frame sync pulse width up to frame width - 1. 0 tdm r/w 0 enable for time division multiplex (tdm) mode 1: enable tdm mode and confgures the dai to transmit and receive tdm data. 0: disable tdm mode. address: 0x24 description bit name type por 7 slotl[1:0] r/w 0 selects the time slot to use for left-channel data in tdm mode 00: time slot 1 10: time slot 3 01: time slot 2 11: time slot 4 6 0 5 slotr[1:0] r/w 0 selects the time slot to use for right-channel data in tdm mode 00: time slot 1 10: time slot 3 01: time slot 2 11: time slot 4 4 0 3 slotdly[3:0] r/w 0 enables data delay for slot 4 in tdm mode. 2 0 enables data delay for slot 3 in tdm mode. 1 0 enables data delay for slot 2 in tdm mode. 0 0 enables data delay for slot 1 in tdm mode. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 114 figure 22. dai timing for tdm data format lrcl k bclk sdou t sdin tdm mode with single bit sync pulse (tdm = 1, wci = 0, bci = 1, fsw = 0, ws[1:0] = 00, hizoff = 0, slotl[1:0] = 00, slotr[1:0] = 01) l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 hi-z hi-z l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 hi-z hi-z lrclk bclk sdout sdin lrclk bclk sdout sdin lrclk bclk sdout sdin lrcl k bclk sdou t sdin tdm mode with word length sync pulse (tdm = 1, wci = 0, bci = 1, fsw = 1, ws[1:0] = 00, hizoff = 0, slotl[1:0] = 00, slotr[1:0 ] = 01) tdm mode with hi-z mode disabled (tdm = 1, wci = 0, bci = 1, fsw = 0, ws[1:0] = 00, hizoff = 1, slotl[1:0] = 00, slotr[1:0] = 01) tdm mode using slots 2 and 3 (tdm = 1, wci = 0, bci = 1, fsw = 0, ws[1:0] = 00, hizoff = 0, slotl[1:0] = 10, slotr[1:0] = 11 ) hi-z hi-z 32 cycles ll ll l lll rrrr rrr r hi-z ll ll lll l1 11 1 rrrr hi-z 16 cycles 16 cycles 16 cycles 16 cycles tdm mode with 4 slots (tdm = 1, wci = 0, bci = 1, fsw = 0, ws[1:0] = 00, hizoff = 0, slotl[1:0] = 00, slotr[1:0] = 01) max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 115 figure 23. playback path block diagram audio playback path the device playback path has two channels (left and right) and can accept digital audio input from the dai and/or the record path sidetone. the digital audio is then routed through several stages of flexsound dsp followed by the digital to analog converter (figure 23). playback path flexsound dsp the first playback path section features the maxim flexsound dsp stages. the first stage accepts and mixes the dai input with the record path sidetone (if enabled), and contains separate digital gain and digital level control stages. this stage is followed by three stereo dsp stages including a 7-band parametric equalizer, a dynamic range control section (drc), and a digital filter stage. the play - back path digital output is then routed into the dac where it is converted back to analog before being routed to the analog output mixers. playback path digital gain and level control the stereo playback path dsp includes separate digital gain and level control stages (figure 24). unlike the record path, both playback path channels (left and right) share the same digital gain and level control settings. the coarse digital gain stage accepts its input from the dai digital data output and can be set from 0db to +18db in 6db increments. the fine adjust, level control stage input is the summation of the coarse gain stage output with the record path sidetone signal. it can be adjusted from -15db to 0db in 1db increments (table 49). the playback path gain and level control stage also include a mute enable. dvg[1:0] flexsound technology dsp dai sidetone from record path right playback path to the analog output mixers left playback path left sidetone dsts[1:0] right sidetone left 7-band parametric equalizer right 7-band parametric equalizer left alc: automatic level control b0_eq_[23:0] b1_eq_[23:0] b2_eq_[23:0] a1_eq_[23:0] a2_eq_[23:0] eq_banden dveq[3:0] eqclp left filters mode dhpf right alc: automatic level control right filters dac left dac right daren dalen dvst[3:0] dachp perfmode dvm dv[3:0] left level right level left gain l/r st level right gain drcen drcg[4:0] drcrls[2:0] drcatk[2:0] drccmp[2:0] drcthc[4:0] drcexp[2:0] drcthe[4:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 116 table 49. playback gain and level configuration register figure 24. playback path sidetone and level control address: 0x27 description bit name type por 7 dvm r/w 0 enables the playback path data input mute. 6 5 dvg[1:0] r/w 0 playback path coarse adjust gain confguration 00: 0db 10: +12db 01: +6db 11: +18db 4 0 3 dv[3:0] r/w 0 playback path fine level control confguration 2 0 0x0: 0db 0x4: -4db 0x8: -8db 0xc: -12db 0x1: -1db 0x5: -5db 0x9: -9db 0xd: -13db 0x2: -2db 0x6: -6db 0xa: -10db 0xe: -14db 0x3: -3db 0x7: -7db 0xb: -11db 0xf: -15db 1 0 0 0 dvg[1:0] flexsound technology dsp dai sidetone from record path right playback path to the analog output mixers left playback path left sidetone dsts[1:0] right sidetone dvst[3:0] dvm dv[3:0] left level right level left gain l/r st level right gain left 7-band parametric equalizer right 7-band parametric equalizer left alc: automatic level control b0_eq_[23:0] b1_eq_[23:0] b2_eq_[23:0] a1_eq_[23:0] a2_eq_[23:0] eq_banden dveq[3:0] eqclp left filters mode dhpf right alc: automatic level control right filters dac left dac right daren dalen dachp perfmode drcen drcg[4:0] drcrls[2:0] drcatk[2:0] drccmp[2:0] drcthc[4:0] drcexp[2:0] drcthe[4:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 117 figure 25. playback path dsp playback path 7-band parametric equalizer the playback path dsp features a 7-band parametric equalizer with clipping detection and a programmable pre-attenuation amplifier (figure 25). each of the 7 bands is a full, individually programmable digital biquad filter. the chosen configuration for any given band applies to both the left and right playback channels. the parametric equalizer can be enabled in a 3-band, 5-band, or the full 7-band configuration (table 50). once the parametric equalizer is enabled, the clip detec - tion can be set and the level of preattenuation can be adjusted from 0db down to -15db (denoted a v_eq , see table 51). no single band biquad filter can be set to a gain greater than 12db, to a q greater than 10, or to below a minimum f c that varies by filter type. see the electrical characteristics table. daren dalen dachp perfmode dvg[1:0] flexsound technology dsp dai sidetone from record path right playback path to the analog output mixers left playback path left sidetone dsts[1:0] right sidetone dvst[3:0] dvm dv[3:0] left level right level left gain l/r st level right gain left 7-band parametric equalizer right 7-band parametric equalizer left alc: automatic level control b0_eq_[23:0] b1_eq_[23:0] b2_eq_[23:0] a1_eq_[23:0] a2_eq_[23:0] eq_banden dveq[3:0] eqclp left filters mode dhpf right alc: automatic level control right filters dac left dac right drcen drcg[4:0] drcrls[2:0] drcatk[2:0] drccmp[2:0] drcthc[4:0] drcexp[2:0] drcthe[4:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 118 table 51. parametric equalizer playback level configuration register table 50. dsp biquad filter enable register address: 0x28 description bit name type por 7 6 5 4 eqclp r/w 0 enables dai digital input equalizer clipping detection 1: equalizer clip detect disabled. 0: equalizer clip detect enabled. 3 dveq[3:0] r/w 0 dai digital input equalizer attenuation level confguration (a v_eq ) 2 0 0x0: 0db 0x4: -4db 0x8: -8db 0xc: -12db 0x1: -1db 0x5: -5db 0x9: -9db 0xd: -13db 0x2: -2db 0x6: -6db 0xa: -10db 0xe: -14db 0x3: -3db 0x7: -7db 0xb: -11db 0xf: -15db 1 0 0 0 address: 0x41 description bit name type por 7 6 5 4 3 recbqen r/w 0 enable biquad filter in record path 0: biquad flter not used. 1: biquad flter used in adc path. 2 eq3banden r/w 0 enable 3-band eq in dac path (bands 4C7 are not used) 0: 3-band eq disabled. 1: 3-band eq enabled. only valid if eq7banden == 0 and eq5banden == 0. 1 eq5banden r/w 0 enable 5-band eq in dac path (bands 6 and 7 are not used) 0: 5-band eq disabled. 1: 5-band eq enabled. only valid if eq7banden == 0 0 eq7banden r/w 0 enable 7-band eq in dac path 0: 7-band eq disabled. 1: 7-band eq enabled. this makes eq5banden and eq3banden redundant. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 119 table 52. parametric equalizer band n (1C7) biquad filter coefficient registers the parametric equalizer coefficients are uninitialized at power-up, and when used the coefficients should be pro - grammed before the device and equalizer are enabled. the transfer function for each band is defined as: 12 01 2 12 01 2 b bz b z h( z ) a az a z ?? ?? + + = + + the biquad filter in each band has 5 user programmable coefficients (b 0 , b 1 , b 2 , a 1 , and a 2 ), and each individual coefficient is 3 bytes (24 bits) long (a 0 is fixed at 1). they occupy 15 consecutive registers per band for a total of 105 consecutive registers for all 7 bands (table 52). each set of three registers (per coefficient) must be pro - grammed consecutively for the settings to take effect. the coefficients are stored using a twos complement format where the first 4 bits are the integer portion and the last 20 bits are the decimal portion (which results in an approxi - mate +8 to -8 range for each coefficient). address range (by band) name type coefficient segment 1 2 3 4 5 6 7 0x46 0x55 0x64 0x73 0x82 0x91 0xa0 equalizer band n coeffcient b0 r/w b0_n[23:16] 0x47 0x56 0x65 0x74 0x83 0x92 0xa1 r/w b0_n[15:8] 0x48 0x57 0x66 0x75 0x84 0x93 0xa2 r/w b0_n[7:0] 0x49 0x58 0x67 0x76 0x85 0x94 0xa3 equalizer band n coeffcient b1 r/w b1_n[23:16] 0x4a 0x59 0x68 0x77 0x86 0x95 0xa4 r/w b1_n[15:8] 0x4b 0x5a 0x69 0x78 0x87 0x96 0xa5 r/w b1_n[7:0] 0x4c 0x5b 0x6a 0x79 0x88 0x97 0xa6 equalizer band n coeffcient b2 r/w b2_n[23:16] 0x4d 0x5c 0x6b 0x7a 0x89 0x98 0xa7 r/w b2_n[15:8] 0x4e 0x5d 0x6c 0x7b 0x8a 0x99 0xa8 r/w b2_n[7:0] 0x4f 0x5e 0x6d 0x7c 0x8b 0x9a 0xa9 equalizer band n coeffcient a1 r/w a1_n[23:16] 0x50 0x5f 0x6e 0x7d 0x8c 0x9b 0xaa r/w a1_n[15:8] 0x51 0x60 0x6f 0x7e 0x8d 0x9c 0xab r/w a1_n[7:0] 0x52 0x61 0x70 0x7f 0x8e 0x9d 0xac equalizer band n coeffcient a2 r/w a2_n[23:16] 0x53 0x62 0x71 0x80 0x8f 0x9e 0xad r/w a2_n[15:8] 0x54 0x63 0x72 0x81 0x90 0x9f 0xae r/w a2_n[7:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 120 figure 26. dynamic range compression and expansion playback path dynamic range control the playback path includes a dynamic range control (drc) section (figure 25). the drc is highly configu - rable and features digital make-up gain, a dynamic range compression and expansion, and programmable attack and release times. the device dynamic range is determined by the difference between the full-scale and the rms noise floor amplitude of the configured signal path. to avoid performance limit - ing, the application dynamic range is typically smaller than the dynamic range of the selected signal path. with dynamic range control disabled, the input dynamic range is equal to the output dynamic range (figure 26). when compression is enabled, if the input signal amplitude exceeds the compression threshold the gain is reduced by the chosen compression ratio. this results in a smaller, compressed output dynamic range relative to the input dynamic range. when expansion is enabled, the gain is decreased by the chosen expansion ratio if the input sig - nal amplitude instead falls below the expansion threshold. this results in a larger, expanded output dynamic range. the drc also features a digital make-up gain control section (table 54), that can be programmed from 0db to 12db in 1db increments. figure 27 shows the effect of enabling the drc with and without digital make-up gain. figure 27. drc enable and make-up gain input amplitude (dbfs) output amplitude (dbfs) drc disabled -140 -120 -100 -80 -60 -20 -40 0- 14 0- 120 -100 -80 -60 -20 -40 0- 14 0- 120 -100 -80 -60 -20 -40 0 full scale applica tin output dynamic range full scale dynamic range compression dynamic range exp ansion full scal e -140 -120 -100 -80 -60 -40 -20 -140 -120 -100 -80 -60 -40 -20 -140 -120 -100 -80 -60 -40 -20 0 input amplitude (dbfs) output amplitude (dbfs) 0 input amplitude (dbfs) output amplitude (dbfs) 0 compressed output dynamic range exp anded output dynamic range compression threshold = -30d b ra tio = 2:1 expa nsion t hreshold = -60db, ra tio = 1:2 applic at ion input dynamic rang e applica tion input dynamic range noise floor noise floor noise floor applica tion input dynamic range input amplitude (dbfs) output amplitude (dbfs) drc disabled -120 -100 -80 -60 -40 -20 0 full scale full scale compression threshold = -30d b ratio = 4:1 drc enabled expa nsion threshold = -60d b ra tio = 1:2 drc enabled with gain full scal e -120 -100 -80 -60 -40 -20 0 input amplitude (dbfs) output amplitude (dbfs) -120 -100 -80 -60 -40 -20 0 -120 -100 -80 -60 -40 -20 0 input amplitude (dbfs) output amplitude (dbfs) -120 -100 -80 -60 -40 -20 0 -120 -100 -80 -60 -40 -20 0 a v_alc = +10db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 121 figure 28. drc compression ratio and threshold figure 29. drc expansion ratio and threshold the drc features two programmable signal thresholds. the high amplitude compression threshold is used to ensure maximum signal amplitude without audible clip - ping. the compression ratio can be set to one of five options from a 1:1 ratio to an infinite:1 ratio (or flat output amplitude as input amplitude increases). the compres - sion threshold can be configured from -31db to 0db. the compression ratios and a range of thresholds are illus - trated in figure 28. the low amplitude expansion threshold is used to prevent background noise from being amplified. when the signal level drops below the expansion threshold, the drc reduces the gain until the signal increases above the threshold. the expansion ratio can be set to a 1:1, 1:2, or 1:3 ratio while the threshold can be configured from -35db to - 66db. the expansion ratios and a range of threshold are illustrated in figure 29. input amplitude (dbfs) output amplitude (dbfs) drc enabled -60 -50 -40 -30 -20 -10 0 -60 -50 -40 -30 -20 -10 0 -60 -50 -40 -30 -20 -10 0 full scale full scale ra tio option full scal e threshold option s compression ra tion = 4:1 0db -5db -10db -15db -20db -25db -30db -60 -50 -40 -30 -20 -10 0 input amplitude (dbfs) output amplitude (dbfs) -60 -50 -40 -30 -20 -10 0 input amplitude (dbfs) output amplitude (dbfs) -60 -50 -40 -30 -20 -10 0 compression threshold compression ratio 1:1 1:5:1 2:1 4:1 inf:1 compression threshold = -30db ratio =4:1 compression threshold = - 30db expansion ratio expansion threshol d input amplitude (dbfs) output amplitude (dbfs) -30 drc enabled -90 -50 -70 -90 -80 -40 -60 -80 expander threshold = -60db ratio = 1:2 output amplitude (dbfs) expansion threshold = -60db ratio options 1:1 1:2 1:3 output amplitude (dbfs) expansion ratio = 1:2 threshold options -65db -70 -60 -50 -40 -30 input amplitude (dbfs) -30 -90 -50 -70 -90 -80 -40 -60 -80 -70 -60 -50 -40 -30 input amplitude (dbfs) -30 -90 -50 -70 -90 -80 -40 -60 -80 -70 -60 -50 -40 -30 -60db -55db -50db -45db -40db -35db max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 122 the drc provides a wide range of programmable attack and release times (table 53). when the compression is enabled and the signal amplitude increases until the compression threshold is exceeded, the attack time determines how quickly the selected compression ratio is applied. when the signal amplitude decreases and the compression threshold would no longer be exceeded, the release time determines how quickly the gain returns to normal (figure 30). when expansion is enabled and the signal amplitude decreases until it drops below the expansion threshold, the release time determines how quickly the selected expansion ratio is applied. when the signal amplitude increases and the expansion threshold would no longer be exceeded, the attack time determines how quickly the gain returns to normal. the attack and release times are not absolute. they are instead used to set the rate at which the gain is adjusted once the signal amplitude is either above or below the appropriate threshold. therefore the selected attack/ release times are relative to the ratio of the new signal amplitude to the selected compression and expansion thresholds. the values provided in table 53 all assume the input signal amplitude changed to exceed the appro - priate threshold by a ratio of 12db (above for compression and below for expansion). if the appropriate threshold is exceeded by a larger or smaller ratio, the attack time is increased or decreased appropriately. the change is proportional to the change in ratio in db. for example, release time is reduced by 50% for 6db. for compression, if the signal amplitude exceeds the threshold by 12db, the attack time when entering com - pression precisely matches the selected configuration. likewise, when exiting compression, the release time is determined by the ratio by which the threshold was exceeded prior to the amplitude dropping. expansion works in exactly the same fashion except for two differences. the expansion ratio is applied when the signal amplitude drops below the expansion threshold (rather than above for compression), and the release time (rather than attack time) determines how long it takes to enter expansion (centered at 12db below the expansion threshold). likewise, the attack time is then used when exiting expansion. in addition, when entering expansion, the ratio of the initial input amplitude to the expansion threshold sets a delay before the expansion ratio is applied. this delay is centered at 12db above the expan - sion threshold and is determined by the selected release time. there is no delay prior to the attack time when exit - ing expansion. figure 30. drc attack and release time waveforms compression release time (2:1 ) released amplitude compressed amplitude amplitude dececreases release time compression attack time (2:1) amplitude increases compression threshold compressed amplitude attack time max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 123 table 53. dynamic range control (drc) timing register table 54. dynamic range control (drc) gain configuration register table 55. dynamic range control (drc) compressor register address: 0x33 description bit name type por 7 drcen r/w 0 playback drc enable 0: drc disabled. 1: drc enabled. 6 drcrls[2:0] r/w 0 playback drc release time confguration (12db relative to threshold) 5 r/w 0 0x0: 8s 0x1: 4s 0x2: 2s 0x3: 1s 0x4: 0.5s 0x5: 0.25s 0x6: 0.125s 0x7: 0.0625s 4 r/w 0 3 2 drcatk[2:0] r/w 0 playback drc attack time confguration (12db relative to threshold) 1 r/w 0 0x0: 0.125ms 0x1: 0.25ms 0x2: 1.25ms 0x3: 2.5ms 0x4: 6.25ms 0x5: 12.5ms 0x6: 25ms 0x7: 50ms 0 r/w 0 address: 0x36 description bit name type por 7 6 5 4 drcg[4:0] r/w 0 playback drc make-up gain confguration 3 0 0x0: +0db 0x1: +1db 0x2: +2db 0x3: +3db 0x4: +4db 0x5: +5db 0x6: +6db 0x7: +7db 0x8: +8db 0x9: +9db 0xa: +10db 0xb: +11db 0xc: +12db 0xd: reserved 0xe: reserved 0xf: reserved 2 0 1 0 0 0 address: 0x34 description bit name type por 7 drccmp[2:0] r/w 0 playback drc compression ratio confguration 0x0: 1:1 0x3: 4:1 0x1: 1.5:1 0x4: inf:1 0x2: 2:1 0x5C0x7: reserved 6 0 5 0 4 drcthc[4:0] r/w 0 playback drc compression threshold confguration 3 0 0x00: 0 0x01: -1db 0x02: -2db 0x03: -3db 0x04: -4db 0x05: -5db 0x06: -6db 0x07: -7db 0x08: -8db 0x09: -9db 0x0a: -10db 0x0b: -11db 0x0c: -12db 0x0d: -13db 0x0e: -14db 0x0f: -15db 0x10: -16db 0x11: -17db 0x12: -18db 0x13: -19db 0x14: -20db 0x15: -21db 0x16: -22db 0x17: -23db 0x18: -24db 0x19: -25db 0x1a: -26db 0x1b: -27db 0x1c: -28db 0x1d: -29db 0x1e: -30db 0x1f: -31db 2 0 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 124 table 56. dynamic range control (drc) expander register playback path digital filters the playback path dsp includes a digital filter stage. one filter, set with the mode bit (table 57), offers the choice between the iir voice filters and the fir music filters. the iir filters are optimized for standard (f s = 8khz) and wideband (f s = 16khz) voice applications, while the fir filters are optimized for low power operation at higher audio/music sampling rates. for sampling rates in excess of 50khz (f lrclk > 50khz), the fir audio filters must be used, and the dhf bit should be set to appropriately scale the fir interpolation filter. the mode configuration selected applies to both channels of both the record and playback path dsp. the playback path dsp also features a dc-blocking filter. this filter can be used with both the iir voice and fir music filters, and blocks low-frequency (including dc) input signals outside of the lower end of the audio band. digital-to-analog converter (dac) confguration the stereo dac architecture includes two independent audio paths, analog outputs that can be routed to any of the analog output mixers, and two operating modes (table 4). one operating mode is optimized for maximum dynamic performance while the other is optimized for lower power consumption. both dac channels can be enabled independently, allowing the device to support both stereo and left or right mono configurations (table 8). address: 0x35 description bit name type por 7 6 drcexp[2:0] r/w 0 playback drc expansion ratio confguration 0x0: 1:1 0x2: 1:3 0x1: 1:2 0x3C0x7: reserved 5 0 4 drcthe[4:0] r/w 0 playback drc expansion threshold confguration 3 0 0x00: -35db 0x01: -36db 0x02: -37db 0x03: -38db 0x04: -39db 0x05: -40db 0x06: -41db 0x07: -42db 0x08: -43db 0x09: -44db 0x0a: -45db 0x0b: -46db 0x0c: -47db 0x0d: -48db 0x0e: -49db 0x0f: -50db 0x10: -51db 0x11: -52db 0x12: -53db 0x13: -54db 0x14: -55db 0x15: -56db 0x16: -57db 0x17: -58db 0x18: -59db 0x19: -60db 0x1a: -61db 0x1b: -62db 0x1c: -63db 0x1d: -64db 0x1e: -65db 0x1f: -66db 2 0 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 125 table 57. dsp filter configuration register figure 31. playback path digital-to-analog converter address: 0x26 description bit name type por 7 mode r/w 1 enables the codec dsp fir music filters (default iir voice filters) 0: the codec dsp flters operate in iir voice mode with stop band frequencies below the f s /2 nyquist rate. the voice mode flters are optimized for 8khz or 16khz voice application use. 1: the codec dsp flters operate in a linear phase fir audio mode optimized to maintain stereo imaging and operate at higher f s rates while utilizing lower power. 6 ahpf r/w 0 enables the record path dc blocking filter 0: dc-blocking flter disabled. 1: dc-blocking flter enabled. 5 dhpf r/w 0 enables the playback path dc blocking filter 0: dc-blocking flter disabled. 1: dc-blocking flter enabled. 4 dhf r/w 0 enables the dac high sample rate mode (lrclk > 50khz, fir only) 0: lrclk is less than 50khz. 8x fir interpolation flter used. 1: lrclk is greater than 50khz. 4x fir interpolation flter used. 3 2 1 0 dvg[1:0] flexsound technology dsp dai sidetone from record path right playback path to the analog output mixers left playback path left sidetone dsts[1:0] right sidetone left 7-band parametric equalizer right 7-band parametric equalizer left alc: automatic level control b0_eq_[23:0] b1_eq_[23:0] b2_eq_[23:0] a1_eq_[23:0] a2_eq_[23:0] eq_banden dveq[3:0] eqclp left filters mode dhpf right alc: automatic level control right filters dac left dac right daren dalen dvst[3:0] dachp perfmode dvm dv[3:0] left level right level left gain l/r st level right gain alcen alcg[4:0] alcrls[2:0] alcatk[2:0] alccmp[2:0] alcthc[4:0] alcexp[2:0] alcthe[4:0] max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 126 analog audio output confguration the device features three independent integrated analog audio output drivers (figure 32). the receiver/line output driver can be configured either as a differential receiver/ earpiece output or as a stereo single-ended line output driver. the stereo speaker output drivers are filterless class d differential amplifiers capable of driving both 4 and 8 speakers. the headphone output drivers utilize maxims directdrive architecture with an integrated charge pump, and provide configurable headphone and headset jack detection. each analog audio output driver has a program - mable gain input mixer and output amplifier. each mixer accepts any combination of signals from the playback dac, the analog microphone amplifier, and the line input drivers. figure 32. analog audio output functional diagram headphon e direct driv e charge pump mixhpr[5:0] mixhprg[1:0] dacl dacr mic 1 mic 2 line a line b hp right mixer dacl dacr mic 1 mic 2 line a line b hp left mixer dacl dacr mic 1 mic 2 line a line b spk right mixer dacl dacr mic 1 mic 2 line a line b spk left mixer dacl dacr mic 1 mic 2 line a line b rcv/ line out right mixer dacl dacr mic 1 mic 2 line a line b rcv/ line out left mixer mixhplsel mixhprsel linmod hp left mux rcv/ line out mux hpvoll[4:0] hplm hplen -67db to 3db -67db to 3db -12db to 0db -12db to 0db -12db to 0db hp right mux -12db to 0db rcvlvol[4:0] rcvlm rcvlen headphone left pga headphone right pga hpvolr[4:0] hprm hpren rcvrvol[4:0] rcvrm rcvren spkslave mixhpl[5:0] mixhplg[1:0] mixspl[5:0] mixsplg[1:0] spvolr[4:0] splm spren spvoll[4:0] splm splen -48db to 14db 6db speaker right pga -12db to 0db mixspl[5:0] mixsplg[1:0] mixrvcl[5:0] mixrvclg[1:0] mixrvcl[5:0] mixrvclg[1:0] -48db to 14db 6db speaker left pga -62db to 8db -12db to 0db line out right pga -62db to 8db rcvp/ loutl rcvn/ loutr spklp spklgnd spk_vdd spkrgnd hpsns hpl hpr hpvdd hpgnd spkln spkrp spkrn line out left pga cpvss cpvdd c1n c1p analog input drivers daclen dacren dachp perfmode dac left dac right flexsound technology dsp max98090 zden vs2en vsen zden vs2en vsen zden vs2en vsen max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 127 figure 33. receiver output functional diagram analog class ab confgurable receiver/line output the device features a configurable analog class ab pro - grammable gain amplifier output that can be configured to act either a mono differential output or as a stereo single- ended output. when configured as a differential analog output (linemod = 0, table 61), the driver is an ideal receiver driver capable of driving both 16 and 32 differ - ential loads (such as an earpiece speaker). in the receiver configuration, the mono output of the left receiver/line output mixer is routed to both the left and right output driv - ers in a bridge tied load (btl) configuration (figure 33). in this configuration, the mixer input signal source(s) and both the mixer and output amplifier gain settings are deter - mined by the left channel registers. all right output channel register settings have no effect in receiver/earpiece mode. when configured as a stereo single-ended analog out - put (linemod = 1, table 61), the driver is optimized for standard ground referenced, high impedance line outputs. in the line output configuration, the output of the left and right line output mixers are individually routed to the left and right output drivers (respectively, figure 34). in this configuration, both channels are configured individually by the left and right channel registers. receiver/earpiece mixer and gain control when configured as a differential receiver output, only the left output configuration registers are used. the receiver mixer can be configured to accept any combination of signals from the playback dac, the analog microphone amplifiers, and the line input drivers (table 58). the receiver input mixer also provides several attenuation options (table 59). the mixer attenuation options of -6db, -9.5db, and -12db are sized to prevent clipping when several full-scale input sources are selected. the receiver output is a programmable gain amplifier (pga) capable of driving a wide range of differential loads (including standard 16 and 32 earpiece speakers). the receiver pga has a wide volume adjustment range from -62db to +8db, provides a high attenuation mute control (table 60), and features programmable click and pop reduction options. see the click-and-pop reduction sec - tion for details. the receiver pga output common-mode voltage is either half of v avdd (in resistive divider bias mode) or about 0.78v (in bandgap bias mode). dacr dacl mic 1 mic 2 line a line b rcv/ line out right mixer dacr dacl mic 1 mic 2 line a line b rcv/ line out left mixer linmod rcv/ line out mux -12db to 0db rcvlvol[4:0] rcvlm rcvlen rcvrvol[4:0] rcvrm rcvren mixrvcl[5:0] mixrvclg[1:0] mixrvcl[5:0] mixrvclg[1:0] -62db to 8db -12db to 0db line out right pga -62db to 8db rcvp/ loutl rcvn/ loutr line out left pga analog input drivers daclen dacren dachp perfmode dac left dac right flexsound technology dsp speaker/ headphones max98090 zden vs2en zsen max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 128 figure 34. stereo single-ended line output functional diagram table 58. receiver and left line output mixer source configuration register address: 0x37 description bit name type por 7 6 5 mixrcvl[5:0] r/w 0 selects mic 2 as the input to the receiver/line out left mixer. 4 0 selects mic 1 as the input to the receiver/line out left mixer. 3 0 selects line b as the input to the receiver/line out left mixer. 2 0 selects line a as the input to the receiver/line out left mixer. 1 0 selects dac right as the input to the receiver/line out left mixer. 0 0 selects dac left as the input to the receiver/line out left mixer. dacr dacl mic 1 mic 2 line a line b rcv/ line out right mixer dacr dacl mic 1 mic 2 line a line b rcv/ line out left mixer linmod rcv/ line out mux -12db to 0db rcvlvol[4:0] rcvlm rcvlen rcvrvol[4:0] rcvrm rcvren mixrvcl[5:0] mixrvclg[1:0] mixrvcl[5:0] mixrvclg[1:0] -62db to 8db -12db to 0db line out right pga -62db to 8db rcvp/ loutl rcvn/ loutr line out left pga analog input drivers daclen dacren dachp perfmode dac left dac right flexsound technology dsp speaker/ headphones max98090 zden vs2en zsen max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 129 table 59. receiver and left line output mixer gain control register table 60. receiver and left line output volume control register line output mixer and gain control when configured as a stereo single-ended line output, the left and right configuration registers can be programmed independently. each channel mixer can be configured to accept any combination of signals from the playback dac, the analog microphone amplifiers, and the line input drivers (tables 58 and 61). the input mixers also provide several attenuation options (tables 59 and 62). the mixer attenuation options of -6db, -9.5db, and -12db are sized to prevent clipping when several full-scale input sources are selected. the left and right line output drivers are independent programmable gain amplifiers (pgas) capable of driv - ing high impedance ground referenced loads. the line output pgas have a wide volume adjustment range from -62db to +8db, provide a high attenuation mute control (tables 60 and 62), and feature programmable click and pop reduction options. see the click-and-pop reduction section for details. the output common-mode voltage is either half of v avdd (in resistive divider bias mode) or about 0.78v (in bandgap bias mode). as a result of the internal architecture, the left and right channel each have a built in baseline gain of -3db (when all programmable gain options are set to 0db). address: 0x38 description bit name type por 7 6 5 4 3 2 1 mixrcvlg[1:0] r/w 0 receiver/line output left mixer gain confguration 00: 0db 10: -9.5db 01: -6db 11: -12db 0 0 address: 0x39 description bit name type por 7 rcvlm r/w 0 left receiver/line output mute 0: left output amplifer not muted. 1: left output amplifer is muted. 6 5 4 rcvlvol[4:0] r/w 1 receiver/line output left pga volume confguration 3 0 0x1f: +8db 0x1e: +7.5db 0x1d: +7db 0x1c: +6.5db 0x1b: +6db 0x1a: +5db 0x19: +4db 0x18: +3db 0x17: +2db 0x16: +1db 0x15: +0db 0x14: -2db 0x13: -4db 0x12: -6db 0x11: -8db 0x10: -10db 0x0f: -12db 0x0e: -14db 0x0d: -17db 0x0c: -20db 0x0b: -23db 0x0a: -26db 0x09: -29db 0x08: -32db 0x07: -35db 0x06: -38db 0x05: -42db 0x04: -46db 0x03: -50db 0x02: -54db 0x01: -58db 0x00: -62db 2 1 1 0 0 1 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 130 table 61. right line output mixer source configuration register table 62. right line output mixer gain control register table 63. right line output volume control register address: 0x3a description bit name type por 7 linmod r/w 0 selects between receiver btl mode and line output mode 0: receiver btl mode. all control of the output is from the left-channel registers. 1: line output mode. left and right channels are programmed independently . 6 5 mixrcvr[5:0] r/w 0 selects mic 2 as the input to the line out right mixer 4 0 selects mic 1 as the input to the line out right mixer 3 0 selects line b as the input to the line out right mixer 2 0 selects line a as the input to the line out right mixer 1 0 selects dac right as the input to the line out right mixer 0 0 selects dac left as the input to the line out right mixer address: 0x3b description bit name type por 7 6 5 4 3 2 1 mixrcvrg[1:0] r/w 0 line output right mixer gain confguration 00: 0db 10: -9.5db 01: -6db 11: -12db 0 0 address: 0x3c description bit name type por 7 rcvrm r/w 0 right receiver/line output mute 0: right output amplifer not muted. 1: right output amplifer is muted. 6 5 4 rcvrvol[4:0] r/w 1 line output right pga volume confguration 3 0 0x1f: +8db 0x1e: +7.5db 0x1d: +7db 0x1c: +6.5db 0x1b: +6db 0x1a: +5db 0x19: +4db 0x18: +3db 0x17: +2db 0x16: +1db 0x15: +0db 0x14: -2db 0x13: -4db 0x12: -6db 0x11: -8db 0x10: -10db 0x0f: -12db 0x0e: -14db 0x0d: -17db 0x0c: -20db 0x0b: -23db 0x0a: -26db 0x09: -29db 0x08: -32db 0x07: -35db 0x06: -38db 0x05: -42db 0x04: -46db 0x03: -50db 0x02: -54db 0x01: -58db 0x00: -62db 2 1 1 0 0 1 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 131 figure 35. class d speaker output functional diagram analog class d speaker output the device features an integrated stereo differential speaker amplifier. the analog stereo speaker output has three series sections comprising a flexible input mixer, a programmable gain amplifier, and a differential class d output driver (figure 35). the speaker output is capable of driving both 4 and 8 loads, utilizes a highly efficient class d architecture, and meets emi emission standards while driving a filterless speaker load. dacr dacl mic 1 mic 2 line a line b dacr dacl mic 1 mic 2 line a line b analog input drivers daclen dacren dachp perfmode dac left dac right flexsound technology dsp receiver/line out/ headphones spk right mixer spk left mixer -12db to 0db spkslave mixspl[5:0] mixsplg[1:0] spvolr[4:0] splm spren spvoll[4:0] splm splen -48db to 14db 6db speaker right pga -12db to 0db mixspl[5:0] mixsplg[1:0] -48db to 14db 6db speaker left pga spklp spklgnd spk_vdd spkrgnd spkln spkrp spkrn max98090 zden vs2en zsen max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 132 table 64. left speaker mixer configuration register table 65. right speaker mixer configuration register speaker output mixer and gain control the speaker mixers can be configured to accept any combination of signals from the playback dac, the analog microphone amplifiers, and the line input drivers (tables 64 and 65). the input mixers also provide several attenuation options (table 66). the mixer attenuation options of -6db, -9.5db, and -12db are sized to prevent clipping when sev - eral full-scale input sources are selected. table 66 speaker mixer gain control register address: 0x2e description bit name type por 7 6 5 mixspl[5:0] r/w 0 selects microphone input 2 to left speaker mixer 4 0 selects microphone input 1 to left speaker mixer 3 0 selects line input b to left speaker mixer 2 0 selects line input a to left speaker mixer 1 0 selects right dac output to left speaker mixer 0 0 selects left dac output to left speaker mixer address: 0x2f description bit name type por 7 6 spk_slave speaker slave mode enable 0: right-channel clock always generated independently. 1: right channel uses left-channel clock if both channels are enabled. 5 mixspr[5:0] r/w 0 selects microphone input 2 to right speaker mixer. 4 0 selects microphone input 1 to right speaker mixer. 3 0 selects line input b to right speaker mixer. 2 0 selects line input a to right speaker mixer. 1 0 selects right dac output to right speaker mixer. 0 0 selects left dac output to right speaker mixer. address: 0x30 description bit name type por 7 6 5 4 3 mixsprg[1:0] r/w 0 right-speaker mixer gain confguration 00: +0db 10: -9.5db 01: -6db 11: -12db 2 0 1 mixsplg[1:0] r/w 0 left-speaker mixer gain confguration 00: +0db 10: -9.5db 01: -6db 11: -12db 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 133 table 67. left speaker amplifier volume control register table 68. right speaker amplifier volume control register the speaker output programmable gain amplifiers (pgas) have a wide volume adjustment range from -48db to +14db, provide a high attenuation mute control (table 67 and table 68), and feature programmable click and pop reduction options. see click-and-pop reduction section for details. in addition to the programmable gain range, the class d output driver also provides another 6db of built-in gain. address: 0x31 description bit name type por 7 splm r/w 0 left speaker output mute enable 0 : speaker output volume set by the volume control bits. 1 : left speaker output muted. 6 5 spvoll[5:0] r/w 1 left speaker output amplifer volume control confguration 4 0 0x3f: +14db 0x3e: +13.5db 0x3d: +13db 0x3c: +12.5db 0x3b: +12db 0x3a: +11.5db 0x39: +11db 0x38: +10.5db 0x37: +10db 0x36: +9.5db 0x35: +9db 0x34: +8db 0x33: +7db 0x32: +6db 0x31: +5db 0x30: +4db 0x2f: +3db 0x2e: +2db 0x2d: +1db 0x2c: +0db 0x2b: -1db 0x2a: -2db 0x29: -3db 0x28: -4db 0x27: -5db 0x26: -6db 0x25: -8db 0x24: -10db 0x23: -12db 0x22: -14db 0x21: -17db 0x20: -20db 0x1f: -23db 0x1e: -26db 0x1d: -29db 0x1c: -32db 0x1b: -36db 0x1a: -40db 0x19: -44db 0x18: -48db 3 1 2 1 1 0 0 0 address: 0x32 description bit name type por 7 sprm r/w 0 right speaker output mute enable 0 : speaker output volume set by the volume control bits. 1 : right-speaker output muted. 6 5 spvolr[5:0] r/w 1 right speaker output amplifer volume control confguration 4 0 0x3f: +14db 0x3e: +13.5db 0x3d: +13db 0x3c: +12.5db 0x3b: +12db 0x3a: +11.5db 0x39: +11db 0x38: +10.5db 0x37: +10db 0x36: +9.5db 0x35: +9db 0x34: +8db 0x33: +7db 0x32: +6db 0x31: +5db 0x30: +4db 0x2f: +3db 0x2e: +2db 0x2d: +1db 0x2c: +0db 0x2b: -1db 0x2a: -2db 0x29: -3db 0x28: -4db 0x27: -5db 0x26: -6db 0x25: -8db 0x24: -10db 0x23: -12db 0x22: -14db 0x21: -17db 0x20: -20db 0x1f: -23db 0x1e: -26db 0x1d: -29db 0x1c: -32db 0x1b: -36db 0x1a: -40db 0x19: -44db 0x18: -48db 3 1 2 1 1 0 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 134 effcient class d speaker output driver a class d amplifier offers much higher efficiency than a class ab amplifier. the high efficiency is due to the switching operation of the output stage transistors. in a class d amplifier, the output transistors act as current steering switches and consume negligible additional power. any power loss associated with a class d output stage is primarily due to the loss in the mosfet on- resistance, and the baseline quiescent current overhead. for comparison, the theoretical best-case efficiency of a linear amplifier is 78%. however, that efficiency is only possible at peak output power conditions. under normal operating levels (typical music reproduction levels), effi - ciency often falls below 30%. under the same conditions, the devices differential class d speaker output amplifier still exhibits 80% efficiency. by default, the class d output switching clocks are inde - pendently generated for the left and right channels. with slave mode enabled, the right channel becomes a slave to the left channel and uses the same clock (table 65). in slave mode, the switching scheme is synchronous. as a result, slave mode operation eliminates potential beat tones that can occur with asynchronous stereo class d switching. traditional class d amplifiers often require the use of external lc filters and/or shielding to meet en55022b and fcc electromagnetic-interference (emi) regulation standards. maxims patented active emissions limiting edge-rate control circuitry reduces emi emissions. this allows the device to drive both 4 and 8 without any additional output filtering. the filterless class d outputs are designed for typical applications where the trace length to the speakers is short and has a low series resistance. see the filterless class d speaker operation section for application level details. analog class-h headphone output the stereo headphone output driver has a flexible input mixer, programmable gain stage, an integrated charge pump, and a ground referenced directdrive class h output amplifier (figure 36). the headphone output amplifier is capable of driving both 16 and 32 ground- referenced headphone loads. figure 36. directdrive headphone output functional diagram dacr dacl mic 1 mic 2 line a line b dacr dacl mic 1 mic 2 line a line b analog input drivers daclen dacren dachp perfmode dac left dac right headphon e direct driv e charge pump mixhpr[5:0] mixhprg[1:0] hp right mixer hp left mixer mixhplsel mixhprsel hp left mux hpvoll[4:0] hplm hplen -67db to 3db -67db to 3db -12db to 0db hp right mux -12db to 0db headphone left pga headphone right pga hpvolr[4:0] hprm hpren mixhpl[5:0] mixhplg[1:0] hpsns hpl hpr hpvdd hpgnd c1p c1n cpvdd cpvss flexsound technology dsp speaker/receiver/ line out max98090 zden vs2en zsen max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 135 headphone output mixer and gain control the headphone mixers can be configured to accept any combination of signals from the playback dac, the analog microphone amplifiers, and the line input drivers (table 69 and table 70). the input mixers also provide several atten - uation options (table 71). the mixer attenuation options of -6db, -9.5db, and -12db are sized to prevent clipping when several full-scale input sources are selected. table 69. left headphone mixer configuration register table 70. right headphone mixer configuration register table 71. headphone mixer control and gain register address: 0x29 description bit name type por 7 6 5 mixhpl[5:0] r/w 0 selects microphone input 2 to left headphone mixer. 4 0 selects microphone input 1 to left headphone mixer. 3 0 selects line input b to left headphone mixer. 2 0 selects line input a to left headphone mixer. 1 0 selects right dac output to left headphone mixer. 0 0 selects left dac output to left headphone mixer. address: 0x2a description bit name type por 7 6 5 mixhpr[5:0] r/w 0 selects microphone input 2 to right headphone mixer. 4 0 selects microphone input 1 to right headphone mixer. 3 0 selects line input b to right headphone mixer. 2 0 selects line input a to right headphone mixer. 1 0 selects right dac output to right headphone mixer. 0 0 selects left dac output to right headphone mixer. address: 0x2b description bit name type por 7 6 5 mixhprsel r/w 0 select headphone mixer as right input source (default dac right direct) 0: dac only source (best dynamic range and power consumption) 1: headphone mixer source 4 mixhplsel r/w 0 select headphone mixer as left input source (default dac left direct) 0: dac only source (best dynamic range and power consumption) 1: headphone mixer source 3 mixhprg[1:0] r/w 0 right-headphone mixer gain confguration 00: +0db 10: -9.5db 01: -6db 11: -12db 2 0 1 mixhplg[1:0] r/w 0 left-headphone mixer gain confguration 00: +0db 10: -9.5db 01: -6db 11: -12db 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 136 additionally, the headphone output has a reduced power direct from dac playback mode (figure 37). in this con - figuration, the stereo dac outputs from the playback path are routed around the headphone mixer directly to the headphone output amplifiers. when paired with the low power headphone playback mode (table 4), this com - bination is the lowest power digital to analog playback configuration available. figure 37. reduced power dac playback to headphone output configuration dacr dacl mic 1 mic 2 line a line b dacr dacl mic 1 mic 2 line a line b analog input drivers daclen dacren dachp perfmode dac left dac right headphon e direct driv e charge pump mixhpr[5:0] mixhprg[1:0] hp right mixer hp left mixer mixhplsel mixhprsel hp left mux hpvoll[4:0] hplm hplen -67db to 3db -67db to 3db -12db to 0db hp right mux -12db to 0db headphone left pga headphone right pga hpvolr[4:0] hprm hpren mixhpl[5:0] mixhplg[1:0] hpsns hpl hpr hpvdd hpgnd flexsound technology dsp max98090 c1p c1n cpvdd cpvss speaker/receiver/ line out zden vs2en zsen max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 137 table 73. right headphone amplifier volume control register table 72. left headphone amplifier volume control register the headphone output programmable gain amplifiers (pgas) have a wide volume adjustment range from -67db to +3db, provide a high attenuation mute control (table 72 and table 73), and feature programmable click-and-pop reduction options. see the click-and-pop reduction sec - tion for details. address: 0x2d description bit name type por 7 hprm r/w 0 right headphone output mute enable 0 : headphone output volume set by the volume control bits. 1 : headphone output muted. 6 5 4 hpvolr[4:0] r/w 1 right headphone output amplifer volume control confguration 3 1 0x1f: +3db 0x1e: +2.5db 0x1d: +2db 0x1c: +1.5db 0x1b: +1db 0x1a: +0db 0x19: -1db 0x18: -2db 0x17: -3db 0x16: -4db 0x15: -5db 0x14: -7db 0x13: -9db 0x12: -11db 0x11: -13db 0x10: -15db 0x0f: -17db 0x0e: -19db 0x0d: -22db 0x0c: -25db 0x0b: -28db 0x0a: -31db 0x09: -34db 0x08: -37db 0x07: -40db 0x06: -43db 0x06: -47db 0x04: -51db 0x03: -55db 0x02: -59db 0x01: -63db 0x00: -67db 2 0 1 1 0 0 address: 0x2c description bit name type por 7 hplm r/w 0 left headphone output mute enable 0 : headphone output volume set by the volume control bits. 1 : headphone output muted. 6 5 4 hpvoll[4:0] r/w 1 left headphone output amplifer volume control confguration 3 1 0x1f: +3db 0x1e: +2.5db 0x1d: +2db 0x1c: +1.5db 0x1b: +1db 0x1a: +0db 0x19: -1db 0x18: -2db 0x17: -3db 0x16: -4db 0x15: -5db 0x14: -7db 0x13: -9db 0x12: -11db 0x11: -13db 0x10: -15d 0x0f: -17db 0x0e: -19db 0x0d: -22db 0x0c: -25db 0x0b: -28db 0x0a: -31db 0x09: -34db 0x08: -37db 0x07: -40db 0x06: -43db 0x06: -47db 0x04: -51db 0x03: -55db 0x02: -59db 0x01: -63db 0x00: -67db 2 0 1 1 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 138 headphone ground sense to improve channel isolation, the device has a low-side headphone sense (hpsns) that senses the ground return of the headphone load. for optimal performance, connect the headphone sense line through an isolated trace to a point as close as possible to the ground pole of the headphone jack (figure 38). if this is not possible, or if headphone sense is not used, connect it to the analog ground plane. in this configuration, channel isolation can be degraded, resulting in increased channel-to-channel crosstalk. figure 38. headphone output ground sense connections headphone left pga headphone right pga codec ground plane headphone output jack optimal ground sense configura tion al terna tive ground sense configura tion hpr hpsns hpl headphone left pga headphone right pga codec ground plane headphone output jack hp sense to ground isola ted hp sense trace hpr hpsns hpl max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 139 directdrive headphone output amplifer traditional single-supply headphone amplifiers have out - puts biased at a nominal dc voltage (typically at either half the high-side supply, or at a bandgap referenced common mode level). as a result, large coupling capaci - tors are needed to block this dc bias and ac-couple the audio output to the headphone load. without these capacitors, a significant dc current would flow through the ground referenced headphone load. the result is both unnecessary power dissipation, and potential damage to both the headphone load and amplifier. maxims second-generation directdrive architecture solves this problem by using a charge pump to create an internal negative supply voltage. this increases the overall output signal swing while at the same time, allow - ing the headphone outputs to be biased at gnd even while operating from a single supply (figure 39). without a dc bias component, there is no need for the large ac-coupling capacitors. instead of two large (typically 220f) capacitors, the charge pump only requires three small ceramic capacitors. this conserves board space, reduces cost, and improves the frequency response of the headphone amplifier. class h amplifer charge pump a class h amplifier has the same output architecture as a class ab amplifier. however, in a class h amplifier the power supplies are modulated by the output signal. the integrated headphone charge pump generates both the positive and negative power supply for the headphone output amplifier. to maximize efficiency, both the charge pumps switching frequency and output voltage level and format change based on the headphone output signal level. the charge pump has three different operating ranges each with a different switching frequency. the two lower power ranges use a three-level switching scheme to gen - erate half supply rails at v hpvdd /2 while the high power range uses a standard two-level switching scheme to generate full supply rails at v hpvdd . the switching fre - quency and voltage levels of each range are optimized to maintain high efficiency while meeting the different output power requirements (table 74). table 74. charge-pump operating ranges figure 39. conventional vs. directdrive headphone output bias range headphone output level (% of v hpvdd ) charge pump configuration frequency (khz) v cpvdd/cpvss waveform 1 < 10 ~82 v hpvdd /2 range 1 2 10 to 25 ~660 v hpvdd /2 range 2 3 > 25 ~500 v hpvdd range 3 v hpvdd +v hpvdd -v hpvdd v hpvdd 2 gnd gnd conventional headphone bias directdrive headphone bias v hp_out v hp_out max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 140 range 1 (v hp_out < 10% of v hpvdd ): when the out - put signal level is less than 10% of hpvdd, the output signal swing is low and the power consumption for driving the headphone load is small relative to the charge pump quiescent consumption and switching losses. therefore, to minimize switching losses, the charge-pump frequency is reduced to its lowest rate (~82khz) and the bipolar out - put supply rails are set to half of hpvdd or v hpvdd /2 (figure 40, range 1). range 2 (10% of v hpvdd v hp_out < 25% of v hpvdd ): when the output signal level is between 10% and 25% of hpvdd, the output signal swing is still less than half of hpvdd. however, the load power consumption requirements are now much higher than the charge-pump quiescent consumption and switching losses. to meet the increased load power requirements, the charge-pump switching frequency increases (~660khz) while the bipolar output supply rails remain at half of hpvdd or v hpvdd /2 (figure 40, range 2). range 3 (25% of v hpvdd v hp_out ): when the output signal level exceeds 25% of hpvdd, the output signal swing is much wider. as a result, the charge pump now generates bipolar full hpvdd output supply rails (v hpvdd ). the switching frequency in this range is slightly lower (~500khz). however, the increased voltage differential allows the headphone output driver to reach its maximum voltage swing and load driving capability (figure 40, range 3). figure 40. class h amplifier charge pump operating ranges v hpvdd v hpvdd 2 -v hpvdd -v hpvdd 2 gnd v hpvdd v hpvdd 2 -v hpvdd -v hpvdd 2 gnd v hpvdd v hpvdd 2 -v hpvdd -v hpvdd 2 gnd v hpvdd v hpvdd 2 -v hpvdd -v hpvdd 2 gnd v hpvdd v hpvdd 2 -v hpvdd -v hpvdd 2 gnd v hpvdd v hpvdd 2 -v hpvdd -v hpvdd 2 gnd positive terminal (c1p) negative terminal (c1n) positive terminal (c1p) negative terminal (c1n) positive terminal (c1p ) negative terminal (c1n ) operating range 1 v hp_out < 10% v hpvdd operating range 2 10% v hpvdd v hp_out < 25% v hpvd d operating range 3 25% v hpvdd v hp_out max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 141 to prevent audible crosstalk, the switching frequency in all three charge pump ranges is well outside of the audio band. in addition, to prevent audible distortion during supply range changes, the charge pump transitions from one output power range to another very quickly. when changing from the half supply range (v hpvdd /2) to the full supply range (v hpvdd /2), the transition occurs immediately if the threshold is exceeded (to avoid clipping for a rapidly increasing audio output). when moving back down, there is a 32ms delay between the threshold detec - tion and the supply range transition. the quick supply level transitions draw a significant transient current from hpvdd. to prevent a droop/glitch on hpvdd, the bypass capacitance must be appropriate to supply the required transient current (figures 52 and 53). click-and-pop reduction the device includes extensive click-and-pop reduction circuitry designed to minimizes audible clicks and pops at turn-on, turn-off, and during volume changes. these features include zero-crossing detection, volume change smoothing, and volume change stepping (table 75). zero-crossing detection is available on the analog micro - phone input pgas and all analog output pgas and volume controls to prevent large glitches when volume changes are made. instead of making a volume change immediately, the change is made when the audio signal crosses the midpoint (figure 42). if no zero crossing occurs within the timeout window (100ms), the volume change occurs regardless of signal level. figure 41. class h amplifier supply range transitions figure 42. zero-crossing detection v hpvdd v hpvdd 2 gnd v th_25% -v hpvdd 2 v cpvd d v cpvs s v hp_out -v th_25% 32ms 32ms -v hpvdd gnd zero-crossing detection disabled (zden = 1) i 2 c pga volume change i 2 c pga volume change audio output volume change audio output volume change gnd zero-crossing detection disabled (zden = 0) max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 142 volume smoothing is available on all analog output pgas. when enabled, all volume changes are broken into the smallest available step size. the volume is then ramped through each step between the initial and final volume set - ting at a rate of one step every 1ms. volume smoothing also occurs at device turn-on and turn-off. during turn-on, the volume is first set to mute before the output is enabled. once enabled, mute is first disabled and then the volume is ramped to the programmed level. at turn-off, the volume is ramped down to the minimum gain, and then muted, before the outputs are disabled. if zero-crossing detection is enabled, each volume step occurs at a zero crossing. when no audio signal is present, zero-crossing detection can timeout and prevent volume smoothing from occur - ring. enable enhanced volume smoothing to prevent the volume controller from requesting another volume step until the previous step has been set. each step in the volume ramp then occurs either after a zero crossing has occurred in the audio signal or after the timeout window has expired. during turn-off, enhance volume smoothing is always disabled. table 75. zero-crossing detection and volume smoothing configuration register address: 0x40 description bit name type por 7 6 5 4 3 2 zden r/w 0 zero-crossing detection 0: volume changes made only at zero crossings or after approximately 100ms. 1: volume changes made immediately upon request. 1 vs2en r/w 0 enhanced volume smoothing only valid is volume adjustment smoothing is enabled ( vsen = 0). 0: each volume change waits until the previous volume step has been applied to the output. allows volume smoothing to function with zero-crossing timeout. 1: volume smoothing enhancement is disabled. 0 vsen r/w 0 volume adjustment smoothing 0: volume changes are smoothed by stepping through intermediate levels. 1: volume changes are made directly in a single step. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 143 figure 43. block diagram and typical application circuit for jack detection jack detection the device features a flexible, software configurable jack detection interface. once enabled, the jack detec - tion interface uses two internal comparators to sense the insertion/removal of a jack and identify the type of jack inserted (headphones or headset). when the device is in shutdown or the microphone bias is disabled, the com - parator thresholds are referenced to v spklvdd . when the device is active and microphone bias is enabled, the comparator thresholds are referenced to v micbias . jack detection operation relies on a pullup resistance to set the bias when no jack is inserted. when the device is in shutdown mode or the microphone bias is disabled (micbias is high impedance), an internal pul - lup is enabled on jacksns, and is referenced to the spklvdd supply. when the device is not in shutdown and the microphone bias is enabled, the internal pullup is disabled (jacksns is high impedance). in this state, successful jack detection requires an external pullup on jacksns to micbias. the jack detection internal interface structure and typical external application circuit is shown in figure 43. hpsns hpr hpl micbias analog mic input load sense comparator jack sense comparator v in+ jdeten jdwk jdeten jdeb[1:0] internal pull-up control v in- jacksns lsns jksns v spklvdd v micbias v th 95% v th 10% v spklvdd v micbias 2.2k 1f 1f mben v spklvdd gn d left mi c right max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 144 table 76. jack detection status results jack detection internal comparators when enabled, the device detects jack insertion and removal by monitoring the voltage on jacksns with two internal comparators. the load sense comparator has a 95% threshold of the reference supply and is used to deter - mine whether or not a jack has been inserted or removed. the jack sense comparator has a threshold of 10% of the reference supply, and is used to identify the type of jack (headphones/headset) inserted (table 78). when a jack is not inserted (open), the pullup resistance conducts high. in this state, v jacksns is above the load sense comparator threshold and lsns is set high to indicate that no jack is inserted. when a jack is inserted it loads jacksns and pulls the voltage below the load sense comparator threshold. lsns is then set low to indi - cate that a jack is now inserted. when the jack is removed, the pullup resistance once again conducts high and lsns is set high to indicate that the jack was removed. when a jack is inserted, the loading on jacksns pulls the voltage below the load sense comparator threshold. however, depending on the type of jack connected the voltage may or may not be pulled below the jack sense comparator threshold. if a headphone jack is inserted (3 pole), jacksns is shorted to ground. this pulls the voltage below the jack sense comparator threshold (10% of the reference supply) and jksns is set low to indicate headphones are inserted. if instead, a headset jack is inserted (4 pole, as shown in figure 44), instead jacksns is biased to a voltage somewhere between the referenced supply and ground. in this case, v jacksns is above the jack sense comparator threshold but below the load sense comparator threshold. this state indicates that a headset is inserted. table 76 details the three possible jack detection status results. these comparators are only active when the jdeten is set high. when jack detection is disabled, jacksns is in a high impedance state and the interface is completely shut down. when the device is in shutdown and jdeten is low, lsns and jksns retain their previous state regardless of the jack status. jack detection programmable debounce the load sense and jack sense comparators also have a programmable debounce timeout. the debounce timeout ensures that the jack detection status doesnt change unless the new state is persistent for longer than the time - out. this prevents rapid changes on lsns and jksns during jack insertion/removal transients, and ensures that false jack detection interrupts are not generated. the debounce timeout can be programmed to one of four set - tings from 25ms to 200ms (table 77). jacksns voltage jack detection results lsns jksns state v th_95% v jacksns 1 1 no jack detected v th_10% v jacksns < v th_95% 0 1 headset detected v jacksns < v th_10% 0 0 headphones detected no condition 1 0 not possible/reserved max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 145 figure 44. jack detection cases with internal pullup resistance hpsns hpr hpl micbias analog mic input internal pullup disabled jack detect comparator s disabled v in+ v in- jacksns 2.2k 1f hi-z 1f jdwk = 0 lsns /jksns = last stat e jdeten = 0 mben = 0 or shdn = 0 open jack jdwk = 1 lsns /jksns = last stat e hi-z jdwk = 0 lsns = 0 jksns = 0 jdeten = 1 mben = 1 shdn = 1 headphone jack jdwk = 1 lsns = 0 jksns = 0 jdwk = 0 lsns = 0 jksns = 1 jdeten = 1 mben = 1 shdn = 1 headset jack jdwk = 1 lsns = 0 jksns = 0 spklvdd jdeten = 1 mben = 0 or shdn = 0 open jack hpsns hpr hpl micbias analog mic input jack detect comparator s enabled short to gn d v in+ v in- jacksns 2.2k 1f hi-z headphone detect (internal pullup ) jack detection disabled 1 2 3 4 headset detect (internal pullup ) open jack detect (internal pullup ) hpsns hpr hpl micbias analog mic input jack detect comparator s enable d bias current v in+ v in- jacksns 2.2k 1f hi-z jdwk = 0 lsns = 1 jksns = 1 jdwk = 1 lsns = 1 jksns = 1 hpsns hpr hpl micbias analog mic input jack detect comparator s enable d pullup path v in+ v in- jacksns 2.2k 1f hi-z spklvdd pullup spklvdd pullup spklvdd pullup 1f 1f 1f gn d mi c righ t left right gn d left max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 146 jack detection interrupt generation whenever a jack is inserted or removed and the state of either lsns or jksns changes, a jack detection event is indicated with the jack configuration change flag (jdet, table 78). if the jack detection event is not masked (ijdet, table 79), it also generates an interrupt on irq . the jack detection event bit (jdet) is clear on read. an i 2 c read clears both the jdet bit status and the interrupt assertion on irq (if present). unless a read occurs after each jack detection event, both the jdet bit and the irq interrupt will remain asserted and no new events or inter - rupts can be detected. a change in state from lsns = 1 to lsns = 0 indicates that a jack has been inserted, while a change in state from lsns = 0 to lsns = 1 indicates that a jack has been removed. when an insertion occurs, if jksns does not change and remains at jksns = 1, a headset insertion is indicated, while a change in state from jksns = 1 to jksns = 0 indicates headphones have been inserted. the state transitions, and the interrupt events generated, are ideally used for state machine control in any jack detection software drivers. operation with an internal pullup resistance the device has both a strong and weak internal pullup option. the internal pullup resistors are only active if the device is in shutdown ( shdn = 0,table 6) or when micbias is disabled (mben = 0, table 7), and they allow jack detection and identification to function in those states. this functionality is ideal for cases where the device is put into a sleep or shutdown state, but needs to trigger a device or system level interrupt signal for wake on insertion operation. when jdwk is low (default, table 70), the strong inter - nal pullup is used (approximately 2.4k referenced to spklvdd). this configuration is capable of detecting and identifying both headphone and headset insertion. when jdwk is high, the weak internal pullup (approximately 5a to spklvdd) is used. the weak internal pullup mini - mizes the supply current after jack insertion and is ideal for wake on insertion cases where the system might not immediately power up. the weak internal pullup cannot bias a microphone load, and therefore, cannot identify headset insertion or accessory button presses. figure 44 details how jack detection works with the internal pullup resistance. in case 1, jack detection is disabled and both micbias and jacksns are high impedance. in this state, lsns and jksns retain the last valid jack detection result. in case 2, no jack is inserted and the internal pullup resistance to spklvdd conducts jacksns up above both the load and jack sense com - parator thresholds. in this case, with an open circuit jack, both the strong and weak internal pullups produce the correct jack detection result and the only power consump - tion is that required to bias the internal comparators. in case 3, a headphone jack is inserted shorting jacksns to ground, well below both the load and jack sense comparator thresholds. in this state, both the strong and weak internal pullups produce the correct jack detection result but the strong internal pullup consumes significantly more current than the weak internal pullup. in case 4, a headset jack is inserted. in this state, the strong and weak internal pullups produce different jack detection results. the strong internal pullup biases the headset mic (and jacksns) to a level between the load sense and jack sense comparator thresholds that produces the correct jack detection result. the weak internal pullup, however, is not strong enough to bias a headset mic and as a result it falsely reports that a headphones jack is present. operation with an external pullup resistance the internal pullup resistance is sufficient for wake on interrupt or basic jack detection and identification, but an external pullup resistance to micbias is required to properly bias and current limit a headset microphone (figure 42). when jack detect is enabled and the device is active ( shdn = 1, table 6) with micbias enabled (mben = 1, table 7), jacksns is placed into a high-impedance state and the internal pullup resistor is disabled. in this state, the external pullup resistor then determines the bias voltage level at jacksns. figure 45 details the operation of jack detection with an external pullup resistance. in case 1, jack detection is disabled. as a result, the internal jack detect compara - tors are disabled and lsns/jksns retain their last valid jack detection result. in case 2, no jack is inserted and the external pullup resistance to micbias conducts jacksns up above both the load and jack sense comparator thresholds. in case 3, a headphone jack is inserted shorting jacksns to ground, well below both the load and jack sense comparator thresholds. in case 4, a headset jack is inserted and the external pullup biases the headset mic (and jacksns) to a level between the load sense and jack sense comparator thresholds. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 147 figure 45. jack detection operation with external pullup resistance hpsns hpr hpl micbias analog mic input internal pullup disabled jack detect comparator s disabled v in+ v in- jacksns 2.2k 1f hi-z jdeten = 0 jdwk = x mben = 1 shdn = 1 open jack jdeten = 1 jdwk = x mben = 1 shdn = 1 open jack hi-z hi-z hi-z hi-z jdeten = 1 jdwk = x mben = 1 shdn = 1 headphone jack jdeten = 1 jdwk = x mben = 1 shdn = 1 headset jack internal pullup disabled spklvdd spklvdd internal pullup disabled spklvdd internal pullup disabled spklvdd hpsns hpr hpl micbias analog mic input jack detect comparator s enable d short to gn d bias current pullup path v in+ v in- jacksns 2.2k 1f lsns = 0 jksns = 0 lsns = 0 jksns = 1 lsns = 1 jksns = 1 lsns / jksns = last state hpsns hpr hpl micbias analog mic input jack detect comparator s enabled v in+ v in- jacksns 2.2k 1f hpsns hpr hpl micbias analog mic input jack detect comparator s enabled v in+ v in- jacksns 2.2k 1f 1f 1f 1f 1f headphone detect (internal pullup ) jack detection disabled 1 2 3 4 headset detect (internal pullup ) open jack detect (internal pullup ) gn d mi c righ t left righ t gn d left max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 148 figure 46. jack detection with internal analog microphones accessory button detection after jack insertion, the device can detect button presses on any accessories that include a microphone and a switch that shorts the microphone ring to ground. button presses can be detected either when micbias is enabled or if it is disabled and the strong internal pullup is used (jdwk = 0). a button press changes the state of jksns from 1 to 0 until the button is released, and this change in state generates an event on the jack detection change flag (jdet). this event is used to trigger the appropriate action associated with the key press. jack detection with internal analog microphones if the application requires fixed internal analog microphone(s), and must also detect, identify, and oper - ate with a headset microphone, the general jack dete - caion application circuit (figure 43) does not operate as expected. the complication introduced by an internal analog microphone is detailed in figure 46. when no jack is inserted (case 1) the internal pullup resis - tance attempts to pull jacksns above the load sense comparator threshold. however, the external pullup to micbias creates an unintended current path through the internal analog microphone pullup. as a result, the voltage at jacksns is biased to a level between the jack sense and load sense comparator thresholds, resulting in a false head - set jack detection. when a headset jack is inserted, there is a parallel load on jacksns between the inserted headset jack and the internal analog microphone. this could poten - tially result in a headset being reported as headphones. a schottky diode with a very low forward drop (case 2) can be inserted in series with the external pullup resis - tance. when micbias is disabled, the schottky diode is reverse biased and the current path is blocked. when micbias is enabled, the diode is forward biased and the external pullup to mic bias functions as detailed in figure 45. the diode does introduce a series voltage drop, and the micbias voltage and/or the series resistance value might need to be adjusted to compensate and ensure that the headset mic is properly biased. alternatively, a switch can be used in series either above or below the internal analog microphone to break the bias current path when micbias is disabled. pullup jack detect comparator s enabled spklvdd pullup jack detect comparator s enabled spklvdd 1f v in+ v in- v in+ v in- micbia s hi-z 1f 1f 2.2k 1f bias current pat h lsns = 0 jksns = 1 2.2k jdeten = 1 jdwk = x mben = 0 or shdn = 0 open jack jdeten = 1 jdwk = x mben = 0 or shdn = 0 open jack analog mic input 2 analog mic input 1 jacksns hpl hpr hpsns 1f v in+ v in- v in+ v in- micbias hi-z 1f 1f 2.2k 1f current path blocke d lsns = 0 jksns = 1 2.2k analog mic input 2 analog mic input 1 jacksns hpl hpr hpsns fa lse jack detection with internal analog microphone 1 2 schottky diode blocks bias current path to internal analog microphon e analog single-ende d microphone analog single-ended microphone max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 149 table 77. jack detect configuration register table 78. jack status register address: 0x3d description bit name type por 7 jdeten r/w 0 jack detect enable 0: jack detect circuitry disabled 1: jack detect circuitry enabled 6 jdwk r/w 0 jacksns pullup confguration 0: 2.4k resistor to spklvdd (allows microphone detection) 1: 5a to spklvdd (minimizes supply current) valid when micbias = 0 or shdn = 0. 5 4 3 2 1 jdeb[1:0] r/w 0 jack detect debounce confgures the jack detect debounce time: 00: 25ms 10: 100ms 01: 50ms 11: 200ms 0 0 address: 0x02 description bit name type por 7 6 5 4 3 2 lsns r 0 microphone load sense (valid only if jdeten = 1) 0: v jacksns 0.95v x v supply 1: v jacksns > 0.95v x v supply v supply is determined by the state of mben and shdn so that: mben = 0 or shdn = 0: v supply = v spklvdd (internal pullup) mben = 1 and shdn = 1: v supply = v micbias (external pullup) 1 jksns r 0 jack connection sense (valid only if jdeten = 1) 0: v jacksns < 0.1v x v supply 1: v jacksns 0.1v x v supply v supply is determined by the state of mben and shdn so that: mben = 0 or shdn = 0: v supply = v spklvdd (internal pullup) mben = 1 and shdn = 1: v supply = v micbias (external pullup) 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 150 quick setup confguration the quick setup configuration registers provide simple device configuration options for commonly used signal paths and settings. each quick setup register contains write only, push-button configuration bits. when written high, a quick configuration bit will internally set all other appropriate register bits to program the device to the selected configuration. writing a logical low to a quick configuration bit has no effect, and when read back all quick configuration bits always show a logic-low. quick setup bits change the state of registers appropriate to the selected configuration only. as such, they do not remove or reset existing device settings that do not share the same configuration registers. this allows comple - mentary selections from several different quick configura - tion registers to be used together in a logical sequence to configure the device. do not combine multiple quick setup bits that configure either the same section or any shared data path as part of a single sequence. this type of sequence might not produce the desired results as later quick setup bits may overwrite registers programmed by earlier selections. the digital audio interface (dai) quick setup register (table 79) is used to select the dai data format. the configurations in this register program the master mode clock configuration register (table 29), the dai format configuration register (table 39), and the dai tdm control register (table 40). the playback path quick setup register (table 80) is used to configure the digital playback path and to select and program an analog output. the configuration bits in this register program the dai i/o configuration register (table 38), the output enable register (table 8), and the selected analog output mixer, volume, and control regis - ters (headphones, receiver, speaker, or line output). table 79. digital audio interface (dai) quick setup register table 80. playback path quick setup register address: 0x06 description bit name type por 7 6 5 rj_m w 0 sets up dai for right-justifed master mode operation. 4 rj_s w 0 sets up dai for right-justifed slave mode operation. 3 lj_m w 0 sets up dai for left-justifed master mode operation. 2 lj_s w 0 sets up dai for left-justifed slave mode operation. 1 i2s_m w 0 sets up dai for i 2 s master mode operation. 0 i2s_s w 0 sets up dai for i 2 s slave mode operation. address: 0x07 description bit name type por 7 dig2_hp w 0 sets up the dac to headphone path. 6 dig2_ear w 0 sets up the dac to receiver path. 5 dig2_spk w 0 sets up the dac to speaker path 4 dig2_lout w 0 sets up the dac to line out path. 3 2 1 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 151 table 82. line input to record path quick setup register table 81. analog microphone/direct input to record path quick setup register the analog microphone/direct input to record path quick setup register (table 81) is used to select and program an analog input and to configure the digital record path. the configuration bits in this register program the dai i/o configuration register (table 38), the input enable register (table 7), and the appropriate input mixer, volume, and control registers (analog microphone or direct to adc mixer). the line input to record path quick setup register (table 82) is used to program the analog input and to configure the digital record path. the configuration bits in this register program the dai i/o configuration register (table 38), the input enable register (table 7), and the appropriate input mixer, volume, and control registers (single-ended or dif - ferential line input). address: 0x08 description bit name type por 7 in12_mic1 w 0 sets up the in1/in2 to microphone 1 to adcl path 6 in34_mic2 w 0 sets up the in3/in4 to microphone 2 to adcr path 5 4 3 in12_dadc w 0 sets up the in1/in2 direct to adcl path 2 in34_dadc w 0 sets up the in3/in4 direct to adcr path 1 in56_dadc w 0 sets up the in5/in6 direct to adcl path (wlp only) 0 address: 0x09 description bit name type por 7 in12s_ab w 0 sets up stereo single-ended record: in1/in2 to line in a/b to adcl/r 6 in34s_ab w 0 sets up stereo single-ended record: in3/in4 to line in a/b to adcl/r 5 in56s_ab w 0 sets up stereo single-ended record: in5/in6 to line in a/b to adcl/r (wlp only) 4 in34d_a w 0 sets up mono differential record: in3/in4 to line in a to adcl 3 in65d_b w 0 sets up mono differential record: in6/in5 to line in b to adcr (wlp only) 2 1 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 152 table 83. analog microphone input to analog output quick setup register table 84. line input to analog output quick setup register the analog microphone input to analog output quick setup register (table 83) is used to configure the analog input and to select and program an analog output. the configuration bits in this register program the input enable register (table 7), the output enable register (table 8), and the appropriate input and output mixer, volume, and control registers (analog microphone and either the head - phones, speaker, receiver, or line output). the line input to analog output quick setup register (table 84) is used to configure the analog input and to select and program an analog output. the configuration bits in this register program the input enable register (table 7), the output enable register (table 8), and the appropriate input and output mixer, volume, and control registers (line input and either the headphones, speaker, receiver, or line output). address: 0x0a description bit name type por 7 in12_m1hpl w 0 sets up the in1/in2 differential to microphone 1 to headphone left path 6 in12_m1spkl w 0 sets up the in1/in2 differential to microphone 1 to speaker left path 5 in12_m1ear w 0 sets up the in1/in2 differential to microphone 1 to receiver path 4 in12_m1loutl w 0 sets up the in1/in2 differential to microphone 1 to lineout left path 3 in34_m2hpr w 0 sets up the in3/in4 differential to microphone 2 to headphone right path 2 in34_m2spkr w 0 sets up the in3/in4 differential to microphone 2 to speaker right path 1 in34_m2ear w 0 sets up the in3/in4 differential to microphone 2 to receiver path 0 in34_m2loutr w 0 sets up the in3/in4 differential to microphone 2 to lineout right path address: 0x0b description bit name type por 7 in12s_abhp w 0 sets up the in1/in2 single ended to line in a/b to headphone l/r path 6 in34d_aspkl w 0 sets up the in3/in4 differential to line in a to speaker left path 5 in34d_aear w 0 sets up the in3/in4 differential to line in a to receiver path 4 in12s_ablout w 0 sets up the in1/in2 single ended to line in a/b to lineout l/r path 3 in34s_abhp w 0 sets up the in3/in4 single ended to line in a/b to headphone l/r path 2 in65d_bspkr w 0 sets up the in6/in5 differential to line in b to speaker right path (wlp only) 1 in65d_bear w 0 sets up the in6/in5 differential to line in b to receiver path (wlp only) 0 in34s_ablout w 0 sets up the in3/in4 single ended to line in a/b to lineout l/r path max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 153 table 85. device status interrupt register device status flags the device uses register 0x01 (table 85) and irq to report the status of various device functions. the status register bits are set when their respective events occur, and cleared upon reading the register. device status can be determined either by polling register 0x01, or by configuring irq to pull low when specific events occur. irq is an open-drain out - put that requires a pullup resistor (10k nominal) for proper operation. when first exiting shutdown (into normal opera - tion), other status flags may assert based on the device settings, register sequencing, and clock sequencing. status flag masking register 0x03, the device status interrupt mask register (table 86) determines which bits in the device status inter - rupt register (table 85) can trigger a hardware interrupt address: 0x01 description bit name type por 7 cld cor 0 clipping detect flag 0: no clipping has occurred. 1: digital record / playback clipping has occurred. cld asserts when the digital record or playback path is clipping due to signal amplitude exceeding full-scale. this condition is detected at the record path gain control output (avlg/avrg), the playback path gain control output (dvg), and the parametric equalizer output. to resolve, adjust the gain settings near these detection points. 6 sld cor 0 slew level detect flag 0: no volume slewing sequences have completed. 1: all volume / level slewing complete. sld asserts when any one (or more) of the programmable-gain analog output volume controllers or digital level control arrays has completed slewing from a previous setting to a new programmed setting. if multiple settings are changed at the same time, in either the analog or digital domain, the sld fag will assert only after the last slew is completed. sld also asserts when the serial interface soft-start or soft-stop process has completed. 5 ulk cor 0 digital audio interface (dai) phase locked loop (pll) unlock flag 0: pll is locked (if enabled and operating properly). 1: pll is not locked (if enabled and operating properly). ulk reports that the digital audio phase-locked loop for dai is not locked. this condition only occurs in slave mode when the deviation on lrclk relative to pclk exceeds the lock on range (approximately 4 pclk periods). this condition can also occur if pclk is running and lrclk has been stopped outside of shutdown. deviation in bclk (or shutting it down) will never trigger a ulk assertion. dai input and output data may not be processed / clocked correctly if a ulk event occurs. 4 3 2 jdet cor 0 jack confguration change flag 0: no change in jack confguration. 1: jack confguration has changed. jdet asserts anytime jack detection is enabled, and either lsns or jksns changes state (table 78). if jack detection is enabled, jdet will assert correctly even while the device is in the shutdown state. this allows jdet to generate wake on insert interrupts. 1 drcact cor 0 drc compression flag 0: the drc is either disabled or not in the compression region. 1: the drc is operating in the compression region. 0 drcclp cor 0 drc clipping flag 0: the drc is either disabled or no clipping has occurred. 1: drc clipping has occurred. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 154 table 86. device status interrupt mask register on irq (assert low). by default, all of the device status interrupts (except jdet) only set the corresponding status bit and do not generate a hardware interrupt. set the corresponding bit high in the mask register to enable hardware interrupts. device revision identifcation the device provides a revision id number register to allow the software to identify the current version of the device. the current device revision id value is 0x43. table 87. revision id number register address: 0x03 description bit name type por 7 icld r/w 0 clipping detect interrupt enable 0: clipping detection only sets cld (0x01[7]). 1: clipping detection triggers irq and sets cld (0x02[7]). 6 isld r/w 0 slew level detect interrupt enable 0: slew level detection only sets sld (0x01[6]). 1: slew level detection triggers irq and sets sld (0x02[6]). 5 iulk r/w 0 digital pll unlock interrupt enable 0: pll unlock condition only sets ulk (0x01[5]). 1: pll unlock condition triggers irq and sets ulk (0x02[5]). 4 3 2 ijdet r/w 1 jack confguration change interrupt enable 0: changes in headset confguration only sets jdet (0x01[2]). 1: changes in headset confguration triggers irq and sets jdet (0x01[2]). 1 idrcact r/w 0 drc compression interrupt enable 0: drc compression only sets drcact (0x01[1]). 1: drc compression triggers irq and sets drcact (0x01[1]). 0 idrcclp r/w 0 drc clipping interrupt enable 0: drc clipping only sets drcclp (0x01[0]). 1: drc clipping triggers irq and sets drcclp (0x01[0]). address: 0xff description bit name type por 7 rev_id[7:0] r 0 read back the revision id of the device the current revision id is 0x43. 6 1 5 0 4 0 3 0 2 0 1 1 0 0 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 155 i 2 c serial interface the max98090 features an i 2 c/smbus-compatible, 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the max98090 and the master at clock rates up to 400khz. figure 3 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the max98090 by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condi - tion. each word transmitted to the max98090 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the max98090 transmits the proper slave address followed by a series of nine scl pulses. the max98090 transmits data on sda in sync with the master-generated scl pulses. the master acknowl - edges receipt of each byte of data. each read sequence is framed by a start (s) or repeated start (sr) condition, a not acknowledge, and a stop (p) condition. sda operates as both an input and an open-drain output. a pullup resistor, typically greater than 500, is required on sda. scl operates only as an input. a pullup resistor, typically greater than 500, is required on scl if there are multiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the max98090 from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are con - trol signals. see the start and stop conditions section. start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start con - dition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high. a start condition from the master signals the beginning of a transmission to the max98090. the master terminates transmission, and frees the bus, by issuing a stop condition. the bus remains active if a repeated start condition is gener - ated instead of a stop condition. early stop conditions the max98090 recognizes a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the slave address is defined as the seven most sig - nificant bits (msbs) followed by the read/write bit. for the max98090a, the seven most significant bits are 0010000. setting the read/write bit to 1 (slave address = 0x21) configures the max98090a for read mode. setting the read/write bit to 0 (slave address = 0x20) configures the max98090a for write mode. the address is the first byte of information sent to the max98090 after the start condition. similarly, for the max98090b, the seven most significant bits are 0010001. setting the read/write bit to 1 (slave address = 0x23) configures the max98090b for read mode. setting the read/write bit to 0 (slave address = 0x22) configures the max98090b for write mode. the slave address are summarized in table 88. figure 47. start, stop, and repeated start conditions table 88. device i 2 c slave address part number read address write address max98090a 0x21 0x20 max98090b 0x23 0x22 scl sda ss rp max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 156 figure 48. acknowledge timing figure 50. writing n-bytes of data to the max98090 figure 49. writing one byte of data to the max98090 acknowledge the acknowledge bit (ack) is a clocked 9th bit that the max98090 uses to handshake receipt each byte of data when in write mode. the max98090 pulls down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master retries communication. the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when the max98090 is in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not acknowledge is sent when the master reads the final byte of data from the max98090, followed by a stop condition. write data format a write to the max98090 includes transmission of a start condition, the slave address with the r / w bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a stop condition. figure 49 illustrates the proper frame format for writing one byte of data to the max98090. figure 50 illustrates the frame format for writing n-bytes of data to the max98090. 1 scl st ar t condition sda 28 9 clock pulse for acknowledgment acknowledge not a cknowledge acknowledge from max98090 sla ve address register address da ta byte 1 aut oincrement internal register address pointer 1 byte acknowledge from max98090 acknowledge from max98090 acknowledge from max98090 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 s o a a a da ta byte n 1 byte p a r/w 1 byte aut oincrement interna l register address pointe r acknowledge from max98090 b7 b6 b5 b4 b3 b2 b1 b0 acknowledge from max98090 acknowledge from max98090 s o a a ap sla ve address r/ w register address da ta byte max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 157 figure 51. reading one byte of data from the max98090 figure 52. reading n-bytes of data from the max98090 the slave address with the r / w bit set to 0 indicates that the master intends to write data to the max98090. the max98090 acknowledges receipt of the address byte during the master-generated 9th scl pulse. the second byte transmitted from the master configures the max98090s internal register address pointer. the pointer tells the max98090 where to write the next byte of data. an acknowledge pulse is sent by the max98090 upon receipt of the address pointer data. the third byte sent to the max98090 contains the data that is written to the chosen register. an acknowledge pulse from the max98090 signals receipt of the data byte. the address pointer autoincrements to the next register address after each received data byte. this auto - increment feature allows a master to write to sequential registers within one continuous frame. the master signals the end of transmission by issuing a stop condition. register addresses greater than 0xe7 are reserved. do not write to these addresses. read data format send the slave address with the r/ w bit set to 1 to initiate a read operation. the max98090 acknowledges receipt of its slave address by pulling sda low during the 9th scl clock pulse. a start command followed by a read com - mand resets the address pointer to register 0x00. the first byte transmitted from the max98090 is the con - tents of register 0x00. transmitted data is valid on the rising edge of scl. the address pointer autoincrements after each read data byte. this autoincrement feature allows all registers to be read sequentially within one con - tinuous frame. a stop condition can be issued after any number of read data bytes. if a stop condition is issued followed by another read operation, the first data byte to be read will be from register 0x00. the address pointer can be preset to a specific register before a read command is issued. the master presets the address pointer by first sending the max98090s slave address with the r/ w bit set to 0 followed by the register address. a repeated start condition is then sent fol - lowed by the slave address with the r/ w bit set to 1. the max98090 then transmits the contents of the specified register, and the address pointer autoincrements after transmitting the first byte. the master acknowledges receipt of each read byte during the acknowledge clock pulse. the master must acknowledge all correctly received bytes except the last byte. the final byte must be followed by a not acknowl - edge from the master and then a stop condition. figure 51 illustrates the frame format for reading one byte from the max98090. figure 52 illustrates the frame for - mat for reading multiple bytes from the max98090. acknowledge from max98090 acknowledge from max98090 acknowledge from max98090 not acknowledge from master aut oincrement internal register address pointer 1 byte p repea ted st ar t s oa a sr 1 a a sla ve address register address sla ve address da ta byte r/ w r/ w acknowledge from max98090 acknowledge from max98090 acknowledge from max98090 aut oincrement internal register address pointer 1 byte repea ted st ar t s o a a sr 1 a a sla ve address register address sla ve address da ta byte r/ w r/ w max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 158 figure 53. typical application circuit with analog microphone inputs and receiver output applications information typical application circuits figures are two example application circuits for the device. the external components shown are the minimum required for the device to operate. additional application specific components might be required. irq 1.8v 10k controller interupt i 2 c interf ace sda scl 1 f cpvss 1 f cpvdd c1n 1f c1p hpgnd dgnd spklgnd spkrgnd agnd max98090 bclk lrclk sdin sdout digit al a udio interf ace por t (dai) 2.2k analog single-ended microphone 1 f 1 f analog differential microphone 1 f 1 f in1/ dmd in2/dmc mic2p/ dmicdin2 mic2n / dmicck2 line inpu t/ external microphone 1 f 1 f in5* in6* 1f 1.8v 1.2v 1f 1f 1f 3.7v 10f 1f 1f 0.1f av dd dvdd spkl vdd* spkl vdd* dvddio hpvdd mclk master clock (10mhz to 60mhz) 1f 2.2f v cm ref 4/8 spklp spkln 4/8 spkrp spkrn 32 rcvp/ loutl rcv n/ loutn hpr hpl micbias 1k micbias 1k receive r/ line output (receive r btl mode) left speake r output right speake r output headphone output jack hpsns 2.2k 1f micbias micbias jacksns *in5 a nd in6 are w lp package only . spklvdd/spkrvdd are titled spkvdd on the wlp pa ckage (bypass each spkvdd as sho wn). max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 159 figure 54. typical application circuit with digital microphone input and stereo line outputs irq 1.8v 10k sda scl 1 f cpvss 1 f cpvdd c1n 1f c1p hpgnd dgnd spklgnd spkrgnd agnd max98095 bclk lrclk sdin sdout digit al microphone 1 digit al microphone 2 in1/ dmd in2/ dmd da ta clock differentia l line inpu t 1 f 1 f in5* in6* differentia l line inpu t 1 f 1 f in3 in4 10f 1.8v 1.2v 1f 0.1f 1f 3.7v 10f 1f 1f 0.1f av dd dvdd spkl vdd* spkr vdd* dvddio hpvdd mclk controller interupt i 2 c interf ace digit al a udio interf ace por t (dai) master clock (10mhz to 60mhz) 1f 1f 2.2f v cm ref 4/8 spklp spkln 4/8 spkrp spkrn rcvp/ loutl 1f rcv n/ loutn hpr hpl receiver / line output (single-ende d line out mode) left speake r output right speake r output headphone output jack hpsns jacksns 2.2k 1f micbias micbias *in5 a nd in6 are w lp package only . spklvdd/spkrvdd are titled spkvdd on the wlp package (bypass each spkvdd as shown). da ta clock max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 160 startup/shutdown register sequencing to ensure proper device initialization and minimal click- and-pop, program the devices control registers in the correct order. to shut down the device, simply set shdn = 0. table 89 details an example startup sequence for the device. to minimize click and pop on the analog output drivers (headphones, speakers, receiver, and line outputs), the output drivers should be powered using the following sequence: 1) prior to powering the device ( shdn = 0) and before enabling the outputs, the output driver mute(s) should be enabled and the pga gain(s) should be set to their lowest setting. 2) after all configuration settings are complete, power up the device ( shdn = 1). 3) enable any analog outputs that are part of the desired configuration. 4) disable the mute on each respective analog output. 5) if volume smoothing is disabled (table 68), ramp the volume up, one register step at a time, from the mini - mum setting until the desired volume (gain) is reached (this sequence is part of the example in table 81). if volume smoothing is enabled, this sequence is auto - matically implemented and the desired volume (gain) can be programmed in a single step. while many configuration options and settings can be changed while the device is operating ( shdn = 1), some settings should only be adjusted with the device in shutdown ( shdn = 0). table 90 lists the registers and bits that should not be changed during active operation. changing these settings during normal operation ( shdn = 1) can compromise device stability and performance specifications. all external clocks (mclk in master mode and mclk, lrclk, and bclk in slave mode) must be running and stable before the device is taken out of shutdown. if the clocks are enabled or changed while the device is active (not in shutdown) phase errors and audible glitches may be introduced. table 90. register changes that require shdn = 0 table 89. detailed device startup sequence sequence description registers 1 set shdn = 0 0x45 (default por state) 2 confgure clocks (also enable all external clocks) 0x1b to 0x21 3 confgure digital audio interface (dai) 0x22 to 0x25 4 confgure digital signal processing (dsp) 0x17 to 0x1a, 0x26 to 0x28, 0x33 to 0x36, 0x41 5 load coeffcients 0x46 to 0xbd 6 confgure power and bias mode 0x42 to 0x44 7 confgure analog mixers 0x0d, 0x15, 0x16, 0x29, 0x2a, 0x2b, 0x2e, 0x2f, 0x37, 0x3a 8 confgure analog gain and volume controls. to minimize click and pop for analog outputs, enable mute and set the output pgas to the minimum gain setting. 0x0e to 0x11, 0x2b to 0x2d, 0x30 to 0x32, 0x38, 0x39, 0x3b, 0x3c 9 confgure miscellaneous functions 0x03, 0x12, 0x13, 0x14, 0x40 11 set shdn = 1 (power up) 0x45 10 enable desired functions 0x3d to 0x3f 11 disable mute on analog output drivers 0x2c, 0x2d, 0x31, 0x32, 0x39, 0x3c 12 for all analog output drivers, if gain smoothing is disabled ramp the gain up one volume step per write until the desired gain is reached. if it is enabled, program the desired gain in a single step. 0x30 to 0x32, 0x38, 0x39, 0x3b, 0x3c description register clock control registers 0x04, 0x05, 0x1b to 0x20 dac/adc enables (only these bits) 0x3e, 0x3f bias/dac/adc control 0x42 to 0x44 digital signal processing coeffcients 0x46 to 0xbd max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 161 component selection ac-coupling capacitors an input capacitor, c in , in conjunction with the input impedance of the device line inputs forms a highpass filter that removes the dc bias from an incoming analog signal. the ac-coupling capacitor allows the amplifier to automatically bias the signal to an optimum dc level. assuming very low source impedance (comparatively), the -3db point of the highpass filter is given by: 3db in in 1 f 2r c ? = choose c in such that f -3db is well below the lowest fre - quency of interest. for best audio quality, use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. capacitors with high-voltage coefficients, such as ceramics, can result in increased distortion at low frequencies. if needed, line output ac-coupling capacitor values can be calculated in similar fashion by using the input resistance of the output stage connected to the line output drivers. charge-pump capacitor selection use capacitors with an esr less than 100m for optimum performance. low-esr ceramic capacitors minimize the output resistance of the charge pump. most surface mount ceramic capacitors satisfy the esr requirement. for best performance over the extended temperature range, select capacitors with an x7r dielectric. the value of the flying capacitor (connected between c1n and c1p) affects the output resistance of the charge pump. a value that is too small degrades the devices ability to provide sufficient current drive, which leads to a loss of output voltage. increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. above 1f, the on-resistance of the internal switches and the esr of external charge pump capaci - tors dominate. the holding capacitor (bypassing hpvss) value and esr directly affect the ripple at hpvss. increasing the capaci - tors value reduces output ripple. likewise, decreasing the esr reduces both ripple and output resistance. lower capacitance values can be used in systems with low maxi - mum output power levels. see the output power vs. load resistance graph in the typical operating characteristics section for more information. filterless class d speaker operation traditional class d amplifiers require an output filter to recover the audio signal from the amplifiers output. the filters add cost, increase the solution size of the amplifier, and can decrease efficiency and thd+n performance. the traditional pwm scheme uses large differential output swings (2 x spk_vdd peak to peak) and causes large ripple currents. any parasitic resistance in the filter com - ponents results in a loss of power, lowering the efficiency. for typical applications (such as handsets, pads, etc.) where the trace length from driver the speaker is short and low impedance, the device does not require an output filter. the device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. eliminating the class d output filter results in a smaller, less costly, and more efficient solution. in cases where the trace/wire length is long, and/or series resistance/inductance is high, an output lc filter might be required. in such a case, if the nominal impedance of the load is not constant over the entire audio band, a zobel (impedance matching) circuit might be required. because the frequency of the ics output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. although this movement is small, a speaker not designed to handle the additional power can be damaged. for optimum results, use a speaker with a series inductance > 10h. typical 8 speakers exhibit series inductances in the 20h to 100h range. max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 162 emi considerations and optional ferrite bead filter reducing trace length minimizes radiated emi. on the pcb, route spklp/spkln and spkrp/spkrn as differ - ential pairs with the shortest trace lengths possible. this minimizes trace loop area, and thereby, the inductance of the circuit. if filter components are used on the speaker outputs, minimize the trace length from any ground tied passive components to spk_gnd to further minimize radiated emi. in applications where speaker leads/wires are long (exceeding approximately 12in), additional emi suppres - sion can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground (figure 55). use a ferrite bead with low dc resistance, high frequency (> 600mhz) impedance between 100 and 600, and rated for at least 1a. the capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. select a capacitor less than 1nf with the value based upon optimizing emi performance. rf susceptibility gsm radios transmit using time-division multiple access (tdma) with 217hz intervals. the result is an rf signal with strong amplitude modulation at 217hz and its har - monics that is easily demodulated by audio amplifiers. the device is designed specifically to reject rf signals; however, pcb layout has a large impact on the suscepti - bility of the end product. in rf applications, improvements to both layout and component selection decreases the susceptibility to rf noise and prevent rf signals from being demodulated into audible noise. trace lengths should be kept below 1/4 of the wavelength of the rf frequency of interest. minimizing the trace lengths prevents them from function - ing as antennas and coupling rf signals into the device. the wavelength () in meters is given by: = c/f, where c = 3 x 10 8 m/s, and f = the rf frequency of interest. route audio signals on middle layers of the pcb to allow ground planes above and below to shield them from rf interference. ideally the top and bottom layers of the pcb should primarily be ground planes to create effective shielding. additional rf immunity can also be obtained by relying on the self-resonant frequency of capacitors, as it exhibits a frequency response similar to a notch filter. depending on the manufacturer, 10pf to 20pf capacitors typically exhib - it self-resonance at rf frequencies. these capacitors, when placed at the input pins, can effectively shunt the rf noise at the inputs of the device. for these capacitors to be effective, they must have a low-impedance, low- inductance path to the ground plane. avoid using micro vias to connect to the ground plane as these vias do not conduct well at rf frequencies. at the headphone outputs, additional rfi can be achieved by using ferrite beads with the capacitors to ground (figure 56). figure 55. optional class d ferrite bead filter figure 56. optional class h output filter spk_p spk_n max98090 hpl hpr hpsns jacksns max98090 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 163 figure 57. pcb breakout routing example for wlp package supply bypassing, layout, and grounding proper layout and grounding are essential for optimum performance. when designing a pcb layout, partition the circuitry so that the analog sections of the device are separated from the digital sections. this ensures that the analog audio traces are not routed near digital traces. use a large continuous ground plane on a dedicated layer of the pcb to minimize loop areas. connect agnd, dgnd, and hpgnd directly to the ground plane using the shortest trace length possible. proper grounding improves audio performance, minimizes crosstalk between chan - nels, and prevents any digital noise from coupling into the analog audio signals. ground the bypass capacitors on micbias, bias and ref directly to the ground plane with minimum trace length. also be sure to minimize the path length to agnd, and bypass avdd directly to agnd. connect all digital i/o termination to the ground plane with minimum path length to dgnd, and bypass dvdd and dvddio directly to dgnd. place the capacitor between c1p and c1n as close as possible to the device to minimize trace length from c1p to c1n. inductance and resistance added between c1p and c1n reduce the output power of the headphone amplifier. bypass hpvdd, cpvdd and cpvss with capacitors located close to the pin with short trace lengths to hpgnd. close decoupling of cpvdd and cpvss minimizes supply ripple and maximizes output power from the headphone amplifier. hpsns senses ground noise on the headphone jack and adds the same noise to the output audio signal, thereby making the output (headphone output, ground) noise free. connect hpsns to the headphone jack shield to ensure accurate pickup of headphone ground noise. bypass spk_vdd to spk_gnd with the shortest trace length possible and connect spklp, spkln, spkrp, and spkrn to the stereo speakers using the shortest traces possible. if filter components are used on the speaker outputs, be sure to locate them as close as possible to the device to ensure maximum effectiveness. route microphone signals from the microphone to the device as a differential pair, ensuring that the positive and negative signals follow the same path as closely as possible with equal trace length. when using single- ended microphones or other single-ended audio sources, ground the negative microphone input as near to the audio source as possible and then treat the positive and negative traces as differential pairs. an evaluation kit (ev kit) is available to provide an exam - ple layout. the ev kit allows quick setup of the device and includes easy-to-use software allowing all internal registers to be controlled. recommended pcb routing the ic uses a 49-bump wlp package. figure 57 pro - vides an example of how to connect to all active bumps using 3 layers of the pcb. to ensure uninter rupted ground returns, use layer 2 as a connecting or dog-bone layer between layer 1 and layer 3, and flood the remaining area with a copper ground plane. la yer 1l a yer 2l a yer 3 max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 164 figure 58. wlp package ball dimensions unused pins table tbd shows how to connect the devices unused pins when circuit blocks are disabled. if the system is extremely noisy or there is a concern that unused analog inputs might be enabled, then alternatively unused analog audio inputs can be ac coupled to agnd (if component cost and area allow it). wlp applications information for the latest application details on wlp construction, dimensions, tape carrier information, pcb techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability test - ing results, refer to the application note 1891 : wafer- level packaging (wlp) and its applications . figure 58 shows the dimensions of the wlp balls used on this device. table 91. unused pin connections pin name connection pin name connection supply planes analog audio outputs avdd always connect hpl unconnected agnd always connect hpr unconnected hpvdd always connect hpsns agnd hpgnd always connect spklp unconnected dvdd always connect spkln unconnected dvddio always connect spkrp unconnected dgnd always connect spkrn unconnected spkvdd always connect rcvp / loutl unconnected spklvdd always connect rcvn / loutr unconnected spkrvdd always connect digital audio interface spklgnd always connect sdin dgnd spkrgnd always connect sdout unconnected charge pump mclk always connect cpvdd unconnected lrclk dgnd cpvss unconnected bclk dgnd c1p unconnected i 2 c interface c1n unconnected scl always connect analog audio inputs sda always connect in1/dmd unconnected irq unconnected in2/dmc unconnected other in3 unconnected micbias unconnected in4 unconnected jacksns unconnected in5 unconnected bias always connect in6 unconnected ref always connect 0.24 mm 0.21 mm max98090 ultra-low power stereo audio codec www.maximintegrated.com
maxim integrated 165 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos +denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. ordering information part address temp range pin-package max98090aewj+t 0x20 -40c to +85 c 49 wlp max98090aetl+t 0x20 -40c to +85c 40 tqfn max98090bewj+t 0x22 -40c to +85c 49 wlp max98090betl+t 0x22 -40c to +85c 40 tqfn package type package code outline no. land pattern no. 49 wlp w493b3+2 21-0443 refer to application note 1891 40 tqfn t4055+1 21-0140 90-0121 max98090 ultra-low power stereo audio codec www.maximintegrated.com
? 2013 maxim integrated 166 revision history flexsound and directdrive are registered trademarks of maxim integrated products, inc. revision number revision date description pages changed 0 1/13 initial release maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical character - istics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. max98090 ultra-low power stereo audio codec for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.

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