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RT8207 1 ds8207-07 march 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. complete ddrii/ddriii memory power supply controller general description the RT8207 provides a complete power supply for both ddrii/ddriii memory systems. it integrates a synchronous pwm buck controller with a 3a sink/source tracking linear regulator and a buffered low noise reference. the pwm controller provides the high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high-voltage batteries to generate low voltage chipset ram supplies in notebook computers. the constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ? instant-on ? response to load transients while maintaining a relatively constant switching frequency. the RT8207 achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode pwms. efficiency is further enhanced by its ability to drive very large synchronous rectifier mosfets. the buck conversion allows this device to directly step down high-voltage batteries for the highest possible efficiency. the 3a sink/source ldo maintains fast transient response only requiring 20 f of ceramic output capacitance. in addition, the ldo supply input is available externally to significantly reduce the total power losses. the RT8207 supports all of the sleep state controls placing vtt at high-z in s3 and discharging vddq, vtt and vttref (soft-off) in s4/s5. the RT8207 has all of the protection features including thermal shutdown and is available in the wqfn-24l 4x4 package. features z z z z z pwm controller ` ` ` ` ` resistor programmable current limit by low-side r ds(on) sense ` ` ` ` ` quick load-step response within 100ns ` ` ` ` ` 1% v out accuracy over line and load ` ` ` ` ` fixed 1.8v (ddrii), 1.5v (ddriii) or adjustable 0.75v to 3.3v output range ` ` ` ` ` battery input range 2.5v to 26v ` ` ` ` ` resistor programmable frequency ` ` ` ` ` over/under voltage protection ` ` ` ` ` 4 steps current limit during soft-start ` ` ` ` ` drives large synchronous-rectifier fets ` ` ` ` ` power-good indicator z z z z z 3a ldo (vtt), buffered reference (vttref) ` ` ` ` ` capable to sink and source up to 3a ` ` ` ` ` ldo input available to optimize power losses ` ` ` ` ` requires only 20 f ceramic output capacitor ` ` ` ` ` buffered low noise 10ma vttref output ` ` ` ` ` accuracy 20mv for both vttref and vtt ` ` ` ` ` supports high-z in s3 and soft-off in s4/s5 z z z z z rohs compliant and halogen free applications z ddrii/ddriii memory power supplies z notebook computers z sstl18, sstl15 and hstl bus termination pin configurations (top view) wqfn-24l 4x4 vttgnd vttsns gnd mode vttref dem ton nc vddq fb s5 s3 pgnd nc vddp vdd pgood cs ugate lgate vtt vldoin boot phase gnd 1 2 3 4 5 6 78910 12 11 18 17 16 15 14 13 21 20 19 24 22 23 25 RT8207 package type qw : wqfn-24l 4x4 (w-type) lead plating system g : green (halogen free and pb free)
RT8207 2 ds8207-07 march 2011 www.richtek.com typical application circuit figure b. fixed voltage regulator figure a. adjustable voltage regulator marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. 1 0 2 1 2 0 1 9 9 v d d p s 3 u g a t e f b r t 8 2 0 7 l g a t e 1 5 2 2 b o o t p h a s e v d d q 8 l 1 v i n v d d 1 4 p g o o d 1 3 p g o o d g n d 3 , e x p o s e d p a d ( 2 5 ) t o n 1 2 v d d p 5 v c 1 1 f r 2 1 0 0 k r 1 5 . 1 c 2 1 f v t t / v t t r e f c o n t r o l 2 . 5 v t o 2 6 v r 4 6 2 0 k r 5 0 r 6 0 c 4 0 . 1 f c 9 1 0 f x 3 q 1 b s c 0 9 4 n 0 3 5 q 2 b s c 0 3 2 n 0 3 5 1 h r 7 c 5 r 8 6 k c 7 2 2 0 f v v d d q 1 . 2 v s5 1 1 v d d q c o n t r o l mode d i s c h a r g e m o d e c c m / d e m r 9 1 0 k 4 c 6 v l d o i n 2 3 c s 1 6 r 3 5 . 6 k v t t 2 4 v t t s n s 2 c 8 1 0 f x 2 v t t r e f 5 c 3 3 3 n f dem 6 pgnd 1 8 vttgnd 1 c 9 0 . 1 f 1 0 2 1 2 0 1 9 9 v d d p s 3 u g a t e f b r t 8 2 0 7 l g a t e 1 5 2 2 b o o t p h a s e v d d q 8 l 1 v i n v d d 1 4 p g o o d 1 3 p g o o d g n d 3 , e x p o s e d p a d ( 2 5 ) t o n 1 2 v d d p 5 v c 1 1 f r 2 1 0 0 k r 1 5 . 1 c 2 1 f v t t / v t t r e f c o n t r o l 2 . 5 v t o 2 6 v r 4 6 2 0 k r 5 0 r 6 0 c 4 0 . 1 f c 8 1 0 f x 2 q 1 b s c 0 9 4 n 0 3 5 q 2 b s c 0 3 2 n 0 3 5 1 h r 7 c 5 c 6 2 2 0 f v v d d q 1 . 8 v / 1 . 5 v s5 1 1 v d d q c o n t r o l mode d i s c h a r g e m o d e c c m / d e m 4 v l d o i n 2 3 c s 1 6 r 3 5 . 6 k v t t 2 4 v t t s n s 2 c 7 1 0 f x 2 v t t r e f 5 c 3 3 3 n f dem 6 pgnd 1 8 vttgnd 1 v d d p f o r d d r i i g n d f o r d d r i i i
RT8207 3 ds8207-07 march 2011 www.richtek.com function block diagram r q s min. t off qtrig 1-shot + - + - comp gm + - v ref 0.75v s1 q latch s1 q latch + - ov - + uv 115% v ref 70% v ref + - 90% v ref ss timer thermal shutdown diode emulation drv + - 10a on-time compute 1-shot cs fb vddq vdd pgood pgnd gnd lgate ton pwm trig pwm dem s5 + - gm vdd + - + - + - + - vttref vtt vldoin vttgnd discharge mode select + - + - 110% v vttref 90% v vttref vttsns s3 mode ugate phase vddp boot drv
RT8207 4 ds8207-07 march 2011 www.richtek.com functional pin description pin no. pin name pin function 1 vttgnd power ground for the vtt_ldo. 2 vttsns voltage sense input for the vtt_ldo. connect to the terminal of the vtt_ldo output capacitor 3, 25 (exposed pad) gnd analog ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 4 mode output discharge mode setting pin. connect to vddq for tracking discharge. connect to gnd for non-tracking discharge. connect to vdd for no discharge. 5 vttref vttref buffered reference output. 6 de m diode-emulation mode enable pin. connect to vdd w ill enable diode-emulation mode. connect to gnd will always operate in forced ccm mode. 7, 17 nc no internal connection. 8 vd dq vddq reference input for vtt and vttref. discharge current sinking terminal for vddq non-tracking discharge. output voltage feedback input for vddq output if fb pin is connected to vdd or gnd 9 fb vddq output setting pin. connect to gnd for ddriii (v ddq = 1.5v) power supply. the pin should be connect to vdd for ddrii (v ddq = 1.8v) power supply or be connected to a resistive voltage divider from vddq to gnd to adjust the output of pwm from 0.75v to 3.3v. 10 s3 s3 signal input. 11 s5 s5 signal input 12 ton the pin is used to set the ugate on time through a pull-up resistor connecting to v in . 13 pgood power-good open-drain output. this pin will be in high state when vddq output voltage is within the target range. 14 vdd supply input for the analog supply. 15 vddp supply input for the low gate driver. 16 cs current limit threshold setting input. connect this pin to vdd through the voltage setting resistor. 18 pgnd power ground for low-side mosfet. 19 lgate low-side gate driver output for vddq. 20 phase external inductor connection for vddq and it behaves as the current sense comparator input for low-side mosfet r ds(on) sensing. 21 ugate high-side gate driver output for vddq. 22 boot boost flying capacitor connection for vddq. 23 vldoin power supply for the vtt_ldo. 24 vtt power output for the vtt_ldo
RT8207 5 ds8207-07 march 2011 www.richtek.com electrical characteristics (v ddp = v dd = 5v, v in = 15v, dem = v dd , r ton = 1m , t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) z input voltage, to n to gnd ---------------------------------------------------------------------------------------------- ? 0.3v to 32v z boot to gnd -------------------------------------------------------------------------------------------------------------- ? 0.3v to 38v z phase to gnd dc ----------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 32v <20ns ------------------------------------------------------------------------------------------------------------------------ ? 8v to 38v z phase to boot ---------------------------------------------------------------------------------------------------------- ? 6v to 0.3v z vdd, vddp, cs, mode, s3, s5, vttsns, vddq, dem to gnd -------------------------------------------- ? 0.3v to 6v z vttref, vtt, vldoin, fb, pgood to gnd ---------------------------------------------------------------------- ? 0.3v to 6v z ugate to phase dc ----------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v <20ns ------------------------------------------------------------------------------------------------------------------------ ? 5v to 7.5v z lgate to gnd dc ----------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v <20ns ------------------------------------------------------------------------------------------------------------------------ ? 2.5v to 7.5v z pgnd, vttgnd to gnd ------------------------------------------------------------------------------------------------- ? 0.3v to 0.3v z power dissipation, p d @ t a = 25 c wqf n-24l 4x4 ----------------------------------------------------------------------------------------------------------- 1.923w z package thermal resistance (note 2) wqfn-24l 4x4, ja ------------------------------------------------------------------------------------------------------- 52 c/w wqfn-24l 4x4, jc ------------------------------------------------------------------------------------------------------ 7 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v to be continued parameter symbol test conditions min typ max unit pwm controller quiescent supply current (vdd + vddp) fb forced above the regulation point, v s5 = 5v, v s3 = 0v -- 470 1000 a ton operating current r to n = 1m -- 15 -- a i vldoin bias current v s5 = v s3 = 5v, v tt = no load -- 1 -- a i vldoin standby current v s5 = 5v, v s3 = 0, v tt = no load -- 0.1 10 a recommended operating conditions (note 4) z input voltage, v in ---------------------------------------------------------------------------------------------------------- 2.5v to 26v z control voltage, v ddp , v dd ---------------------------------------------------------------------------------------------- 4.5v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
RT8207 6 ds8207-07 march 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit v dd + v ddp -- 0.1 10 ton -- 0.1 5 s3/s5/dem = 0v ? 1 0.1 1 shutdown current (v s5 = v s3 = 0v) i vldoin -- 0.1 1 a fb reference voltage v ref v dd = 4.5v to 5.5v 0.742 0.75 0.758 v fb = gnd -- 1.5 -- fixed vddq output voltage fb = v dd -- 1.8 -- v fb input bias current fb = 0.75v ? 1 0.1 1 a vddq voltage range 0.75 -- 3.3 v on-time, v in = 15v r to n = 1m 267 334 401 ns minimum off-time 250 400 550 ns vddq input resistance -- 100 -- k vddq shutdown discharge resistance v s5 = gnd -- 15 -- current sensing cs sink current v cs > 4.5v, after uv blank time 9 10 11 a current comparator offset gnd ? phase ? 15 -- 15 mv zero crossing threshold phase ? gnd, dem = 5v ? 10 -- 5 mv fault protection gn d ? phase, r cs = 5k 35 50 65 mv current limit (p os itive) gn d ? phase, r cs = 20k 170 200 230 mv output uv threshold 60 70 80 % ovp threshold with respect to error comparator threshold 10 15 20 % ov fault delay fb forced above ov threshold -- 20 -- s vddp under voltage lockout threshold rising edge, hysteresis = 20mv, pwm disabled below this level 3.9 4.2 4.5 v current limit step time at soft start each step -- 128 -- clks uv blank time from s5 signal going high -- 512 -- clks thermal shutdown hysteresis = 10 c -- 165 -- c driver on-resistance ugate gate driver (pull up) (boot ? phase) forced to 5v -- 2 4 ugate gate driver (sink) (boot ? phase) forced to 5v -- 1 3 lgate gate driver (pull up) lgate, high state (source) -- 2.5 6 lgate gate driver (pull down) lgate, low state (sink) -- 0.6 1.5 ugate gate driver source/sink current ugate forced to 2.5v, (boot ? phase) forced to 5v -- 1 -- a lgate gate driver source current lgate forced to 2.5v -- 1 -- a lgate gate driver sink current lgate forced to 2.5v -- 3 -- a lgate rising (phase = 1.5v) -- 40 -- dead time ugate rising -- 40 -- ns internal boost charging switch on resistance vddp to boot, 10ma -- -- 80
RT8207 7 ds8207-07 march 2011 www.richtek.com parameter symbol test conditions min typ max unit logic i/o logic input low voltage s3, s5, dem low -- -- 0.8 v logic input high voltage s3, s5, dem high 2 -- -- v logic input current s3/s5/dem = vdd/gnd ? 1 0 1 a pgood (upper side threshold decide by ov threshold) trip threshold (falling) measured at fb, with respect to reference, no load. hysteresis = 3% ? 13 ? 10 ? 7 % fault propagation delay falling edge, fb forced below pgood trip threshold -- 2.5 -- s output low voltage i sink = 1ma -- -- 0.4 v leakage current high state, forced to 5.0v -- -- 1 a vtt ldo t a = 25 c, unless otherwise specification v ddq = v ld oin = 1.5v/1.8v, ? i vtt ? = 0a ? 20 -- +20 v ddq = v ld oin = 1.5v/1.8v, ? i vtt ? = 1a ? 30 -- +30 vtt output tolerance v vtttol v ddq = v ld oin = 1.5v/1.8v, ? i vtt ? = 2a, ? 40 -- +40 mv ddq v vtt = 0.95 2 ?? ?? ?? , pgood = high 3 -- 6 vtt source current limit i vttoclsrc vtt = 0v -- 2 -- a ddq v vtt = 1.05 2 ?? ?? ?? pgood = high 3 -- 6 vtt sink current limit i vttoclsnk vtt = vddq -- 2 -- a vtt leakage current i vttlk s5 = 5v, s3 = 0v, ddq v vtt = 2 ?? ?? ?? ? 10 -- 10 a vttfb leakage current i vttsnslk i sink = 1ma ? 1 -- 1 a vtt discharge current i dschrg v ddq = 0v, vtt = 0.5v, s5 = s3 = 0v 10 30 -- ma vttref output voltage v vttref ddq vttref v v = 2 ?? ?? ?? -- 0.9/0.75 -- v v ldoin = v ddq = 1.5v, ? i vttref ? < 10ma ? 15 -- +15 vddq/2, vttref output voltage tolerance v vttreftol v ldoin = v ddq = 1.8v, ? i vttref ? < 10ma ? 18 -- +18 mv vttref source current limit i vttrefocl v vttref = 0v 10 40 80 ma
RT8207 8 ds8207-07 march 2011 www.richtek.com note 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective 4 layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the wqfn package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8207 9 ds8207-07 march 2011 www.richtek.com typical operating characteristics vddq efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) dem pwm v in = 20v, v ddq = 1.5v, s3 = gnd, s5 = v ddp ddriii vddq efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) dem pwm v in = 12v, v ddq = 1.5v, s3 = gnd, s5 = v ddp ddriii vddq efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) dem pwm v in = 8v, v ddq = 1.5v, s3 = gnd, s5 = v ddp ddriii vddq efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) dem pwm v in = 20v, v ddq = 1.8v, s3 = gnd, s5 = v ddp ddrii vddq efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) dem pwm v in = 12v, v ddq = 1.8v, s3 = gnd, s5 = v ddp ddrii vddq efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) dem pwm v in = 8v, v ddq = 1.8v, s3 = gnd, s5 = v ddp ddrii
RT8207 10 ds8207-07 march 2011 www.richtek.com switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) dem pwm ddrii, v in = 8v, v ddq = 1.8v, s3 = gnd, s5 = v ddp switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) dem pwm ddrii, v in = 12v, v ddq = 1.8v, s3 = gnd, s5 = v ddp switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) dem pwm v in = 20v, v ddq = 1.8v, s3 = gnd, s5 = v ddp ddrii switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) dem pwm ddriii, v in = 8v, v ddq = 1.5v, s3 = gnd, s5 = v ddp switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) dem pwm v in = 12v, v ddq = 1.5v, s3 = gnd, s5 = v ddp ddriii switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) dem pwm v in = 20v, v ddq = 1.5v, s3 = gnd, s5 = v ddp ddriii
RT8207 11 ds8207-07 march 2011 www.richtek.com vttref output voltage vs. output current 0.754 0.756 0.758 0.760 0.762 0.764 0.766 0.768 -10-8-6-4-20246810 output current (ma) output voltage (v) ddriii, v in = 12v, v ddq = 1.5v, s3 = s5 = v ddp vttref output voltage vs. output current 0.902 0.904 0.906 0.908 0.910 0.912 0.914 0.916 0.918 -10-8-6-4-2 0 2 4 6 810 output current (ma) output voltage (v) ddrii, v in = 12v, v ddq = 1.8v, s3 = s5 = v ddp vtt output voltage vs. output current 0.9090 0.9095 0.9100 0.9105 0.9110 0.9115 0.9120 0.9125 0.9130 -2 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2 output current (a) output voltage(v) ddrii, v in = 12v, v ddq = 1.8v, s3 = s5 = v ddp vddq output voltage v s. output current 1.815 1.820 1.825 1.830 1.835 1.840 1.845 0.001 0.01 0.1 1 10 output current (a) output voltage (v) dem pwm ddrii, v in = 12v, v ddq = 1.8v, s3 = gnd, s5 = v ddp vddq output voltage vs. output current 1.515 1.520 1.525 1.530 1.535 1.540 0.001 0.01 0.1 1 10 output current (a) output voltage (v) dem pwm ddriii, v in = 12v, v ddq = 1.5v, s3 = gnd, s5 = v ddp vtt output voltage vs. output current 0.7600 0.7605 0.7610 0.7615 0.7620 0.7625 0.7630 0.7635 -2 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2 output current (a) output voltage (v) ddriii, v in = 12v, v ddq = 1.5v, s3 = s5 = v ddp
RT8207 12 ds8207-07 march 2011 www.richtek.com standby current vs. input voltage 330 340 350 360 370 380 390 7 9 11 13 15 17 19 21 23 25 input voltage (v) standby current (ua) shutdown current vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 7 9 11 13 15 17 19 21 23 25 input voltage (v) shutdown current (ua) no load, dem = 5v, s3 = s5 = 5v no load, dem = 5v, s3 = s5 = gnd vddq and vtt start up time (400 s/div) v ddq (2v/div) v tt (1v/div) s5 (5v/div) pgood (5v/div) v in = 12v, v ddq = 1.8v, dem = 5v, s3 = s5 = 5v no load vddq voltage vs. temperature 1.510 1.514 1.518 1.522 1.526 1.530 1.534 1.538 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature vddq voltage (v) ddriii, v in = 12v, v ddq = 1.5v, s3 = gdn, s5 = v ddp ( c) vddq voltage vs. temperature 1.780 1.784 1.788 1.792 1.796 1.800 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature vddq voltage (v) ddrii, v in = 12v, v ddq = 1.8v, s3 = gdn, s5 = v ddp ( c) vddq start up time (1ms/div) v ddq (1v/div) v in = 12v, v ddq = 1.8v dem = 5v, s3 = gnd ugate (20v/div) lgate (5v/div) inductor current (10a/div) s5 = 5v, i load = 10a
RT8207 13 ds8207-07 march 2011 www.richtek.com shutdown time (2ms/div) v ddq (2v/div) v in = 12v, dem = 5v, s3 = s5 = 5v, mode = gnd non-tracking mode v tt (1v/div) v ttref (1v/div) s5 (10v/div) no load shutdown time (200 s/div) v ddq (2v/div) v in = 12v, dem = 5v, s3 = s5 = 5v, mode = v ddq no load, tracking mode v tt (1v/div) v ttref (1v/div) s5 (10v/div) vddq load transient response time (20 s/div) inductor current (10a/div) v ddq_ac (50mv/div) lgate (10v/div) ddrii, v in = 12v, v ddq = 1.8v, dem = 5v, i load = 1a to 10a, s3 = gnd, s5 = 5v ugate (20v/div) vddq load transient response time (20 s/div) inductor current (10a/div) v ddq_ac (50mv/div) lgate (10v/div) ddriii, v in = 12v, v ddq = 1.5v, dem = 5v, i load = 1a to 10a, s3 = gnd, s5 = 5v ugate (20v/div) vtt load transient response time (500 s/div) v tt_ac (20mv/div) ddriii, v in = 12v, v ddq = 1.5v, dem = 5v, i load = ? 2a to 2a, s3 = s5 = 5v i load (2a/div) v ttref_ac (20mv/div) vtt load transient response time (500 s/div) v tt_ac (50mv/div) ddrii, v in = 12v, v ddq = 1.8v, dem = 5v, i load = ? 2a to 2a, s3 = s5 = 5v i load (2a/div) v ttref_ac (20mv/div)
RT8207 14 ds8207-07 march 2011 www.richtek.com ovp time (40 s/div) ugate (10v/div) lgate (5v/div) v in = 12v, dem = 5v, s3 = gnd, s5 = 5v no load v ddq (1v/div) uvp time (20 s/div) ugate (20v/div) lgate (5v/div) v in = 12v, dem = 5v, s3 = gnd, s5 = 5v no load v ddq (2v/div) inductor current (10a/div)
RT8207 15 ds8207-07 march 2011 www.richtek.com application information the RT8207 pwm controller provides the high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high-voltage batteries to generate low-voltage chipset ram supplies in notebook computers. richtek's mach response tm technology is specifically designed for providing 100ns ? instant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the topology circumvents the poor load-transient timing problems of fixed-frequency current-mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant- off-time pwm schemes. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a single output application. the 3a sink/source ldo maintains fast transient response only requiring 20 f of ceramic output capacitance. in addition, the ldo supply input is available externally to significantly reduce the total power losses. the RT8207 supports all of the sleep state controls placing vtt at high-z in s3 and discharging vddq, vtt and vttref (soft-off) in s4/s5. pwm operation the mach response tm , drv tm mode controller relies on the output filter capacitor's effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. refer to the function diagrams of the RT8207, the synchronous high- side mosfet will be tuned on at the beginning of each cycle. after the internal one-shot timer expires, the mosfet will be turned off. the pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. another one-shot sets a minimum off-time (400ns typ.). on-time control (t on ) the on-time one-shot comparator has two inputs. one input looks at the output voltage, while the other input samples the input voltage and converts it into a current. this input voltage-proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to vddq, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. the implementation results in a nearly constant switching frequency without the need of a clock generator. t on = 3.85p x r ton x v ddq / (v in ? 0.5) and then the switching frequency is : f = v ddq / (v in x t on ) r ton is a resistor connected from the input supply (v in ) to the ton pin. mode selection (dem) operation the dem pin enables the supply. when the dem pin is connected to vdd, the controller will be enabled and operated in diode-emulation mode. when the dem pin is connected to gnd, the RT8207 will operate in forced-ccm mode. diode-emulation mode (dem = vddp) in diode-emulation mode, the RT8207 automatically reduces switching frequency at light-load conditions to maintain high efficiency. this reduction of the frequency is achieved smoothly and without increasing vddq ripple or load regulation. as the output current decreases from heavy-load condition, the inductor current will also be reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low-side mosfet allows only partial of negative current when the inductor freewheeling current reaches negative. as the load current is further decreased, it takes longer time to discharge the output capacitor to the level than requires the next ? on ? cycle. the on-time is kept the same as that in the heavy-load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conducting condition. the transition load point to the light-load operation can be calculated as follows (figure 1) : where t on is on-time. ( ) ? ? in ddq load(skip) on vv it 2l
RT8207 16 ds8207-07 march 2011 www.richtek.com figure 1. boundary condition of ccm/dcm the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in dem noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. the disadvantages for using higher inductor values include larger physical size and degrades load-transient response (especially at low input-voltage levels). forced-ccm mode (dem = gnd) the low-noise, forced-ccm mode (dem = gnd) disables the zero-crossing comparator, which controls the low-side switch on-time. this causes the low-side gate-drive waveform to become the complement of the high-side gate- drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop maintains a duty ratio of v ddq /v in . the benefit of forced-ccm mode is to keep the switching frequency fairly constant, but it comes at a cost : the no-load battery current can be up to 10ma to 40ma, depending on the external mosfets. current-limit setting for vddq (cs) the RT8207 provides cycle-by-cycle current limiting control. the current-limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current- sense signal at the phase pin is above the current-limit threshold, the pwm is not allowed to initiate a new cycle (figure 2). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and battery and output voltage. figure 2. ? valley ? current -limit the RT8207 uses the on-resistance of the synchronous rectifier as the current-sense element. use the worse- case maximum value for r ds(on) from the mosfet datasheet, and add a margin of 0.5%/ c for the rise in r ds(on) with temperature. the r ilim setting resistor between cs pin and vdd sets the current limit threshold. the resistor r ilim is connected to a 10 a current source from the cs pin. when the voltage drop across the low-side mosfet equals the voltage across the r ilim setting resistor, positive current limit will be activated. the high-side mosfet will not be turned on until the voltage drop across the mosfet falls below the current limit threshold. choose a current limit setting resistor by following equation : r ilim = i lim x r ds(on) / 10 a carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signal seen by the phase pin and pgnd. current protection for vtt the ldo has an internally fixed constant over-current limiting of 4.5a while operating at normal condition. this over-current point is reduced to 2a before the output voltage comes within 5% of its set voltage or goes outside of 10% of its set voltage. mosfet gate driver (ugate, lgate) the high-side driver is designed to drive high-current, low r ds(on) n-mosfet(s). when configured as a floating driver, the 5v bias voltage will be delivered from the vddp supply. the average drive current is proportional to the gate charge at v gs = 5v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between boot and phase pins. i l t 0 i l, peak i lim i load i l t 0 t on slope = (v in - v ddq ) / l i l, peak i load = i l, peak / 2
RT8207 17 ds8207-07 march 2011 www.richtek.com a dead time to prevent shoot through is internally generated between high-side mosfet off to low-side mosfet on, and low-side mosfet off to high-side mosfet on. the low-side driver is designed to drive high current, low r ds(on) n-mosfet(s). the internal pull-down transistor that drives lgate low is robust, with a 0.4 typical on- resistance. a 5v bias voltage is delivered from vddp supply. the instantaneous drive current is supplied by the flying capacitor between vddp and pgnd. for high-current applications, some combinations of high- and low-side mosfets might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with the boot pin, which increases the turn-on time of the high-side mosfet without degrading the turn-off time (figure 3). figure 3. reducing the ugate rise time power-good output (pgood) the power good output is an open-drain output and requires a pull-up resistor. when the output voltage is 15% above or 10% below its set voltage, pgood will be pulled low. it is held low until the output voltage returns to within these tolerances once more. in soft start, the pgood pin will be actively held low and is allowed to transition high until soft start is over and the output reaches 93% of its set voltage. there is a 2.5 s delay built into pgood circuitry to prevent the false transition. uvlo protection the RT8207 has a vddp supply under-voltage lockout protection (uvlo). when the vddp voltage is lower than 4.3v (typ.), vddq, vtt and vttref will be shut off. this is a non-latch protection. soft-start a build-in soft-start of vddq is used to prevent surge current from power supply input after s5 is enabled. the maximum allowed current limit is segmented in 4 steps: 25%, 50%, 75% and 100% and each step duration is 128 cycles. the current limit steps can minimize the vddq folded-back in the soft-start duration when the fixed or adjustable output is determined by the RT8207. the soft-start function of the vtt is achieved by the current clamp. the current limit threshold is also changed in two stages using an internal power-good signal dedicated for ldo. during vtt is below the power-good threshold, the current limit level is 2a. this allows the output capacitors to be charged with low and constant current that gives linear ramp up of the output. when the output comes up to the good state, the over-current limit is released to 4.5a. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage protection. when over voltage protection is enabled, if the output exceeds 15% of its set voltage threshold, over voltage protection will be triggered and the lgate low-side gate drivers will be forced high. this activates the low-side mosfet switch, which rapidly discharges the output capacitor and reduces the input voltage. the RT8207 will be latched once the ovp is triggered and can only be released by vdd power-on reset or s5. there is a 20 s delay built into the over voltage protection circuit to prevent false transitions. note that lgate latching high causes the output voltage to dip slightly negative when energy has been previously stored in the lc tank circuit. for loads that cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse polarity clamp. if the over voltage condition is caused by a short in high- side switch, turning the low-side mosfet on 100% creates an electrical short between the battery and gnd, blowing the fuse and disconnecting the battery from the output. output under voltage protection (uvp) the output voltage can be continuously monitored for under boot ugate phase 10 +5v v in
RT8207 18 ds8207-07 march 2011 www.richtek.com voltage protection. when the under voltage protection is enabled, if the output is less than 70% of its set voltage threshold, the under voltage protection is triggered, then both ugate and lgate gate drivers are forced low while entering soft-discharge mode. during soft-start, the uvp will be blanked around 512 cycles. thermal protection the RT8207 monitors the temperature of itself. if the temperature exceeds the threshold value, +165 c (typ.), the pwm output, vttref and vtt will be shut off. the RT8207 is latched once the thermal shutdown is triggered and can only be released by vdd power-on reset or s5. output voltage setting (fb) the RT8207 can be used for both of ddr2 (vddq = 1.8v) and ddr3 (vddq = 1.5v) power supply and it adjustable output voltage (0.75v < vddq < 3.3v) by connecting fb pin as shown in table 1. table 1. fb and output voltage setting fb vddq (v) v ttref and vtt note vdd 1.8 v ddq /2 ddr2 gnd 1.5 v ddq /2 ddr3 fb resistors adjustable v ddq /2 0.75v < v ddq < 3.3v connect a resistor voltage-divider at the fb between vddq and gnd to adjust the respective output voltage between 0.75v and 3.3v (figure 4). choose r2 to be approximately 10k and solve for r1 using the equation as follows : where v ref is 0.75v (typ.). figure 4. setting vddq with a resistor-divider vtt linear regulator and vttref RT8207 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking current up to 3a (vddq>= 1.8v). this vtt linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to keep tracking the vttref within 40mv at all conditions including fast load transient. to achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, vttsns, should be connected to the positive node of the vtt output capacitor(s) as a separate trace from the vtt pin. for stable operation, total capacitance of the vtt output terminal can be equal to or greater than 20 f. it is recommended to attach two 10 f ceramic capacitors in parallel to minimize the effect of esr and esl. if esr of the output capacitor is greater than 2m , insert an rc filter between the output and vttsns input to achieve loop stability. the rc filter time constant should be almost the same or slightly lower than the time constant made by the output capacitor and its esr. the vttref block consists of on-chip 1/2 divider, lpf and buffer. this regulator also has sink and source capability up to 10ma. bypass vttref to gnd by a 33nf ceramic capacitor for stable operation. outputs management by s3 and s5 control in ddrii/ddriii memory applications, it is important to keep vddq always higher than vtt/vttref including both start-up and shutdown. the RT8207 provides this management by simply connecting both s3 and s5 terminals to the sleep-mode signals such as slp_s3 and slp_s5 in notebook pc system. all of vddq, vttref and vtt are turned on at s0 state (s3 = s5 = high). in s3 state (s3 = low, s5 = high), vddq and vttref voltages are kept on while vtt is turned off and left at high impedance (high-z) state. the vtt output is floated and does not sink or source current in this state. in s4/s5 states (s3 = s5 = low), all of the three outputs are disabled. outputs are discharged to ground according to the discharge mode selected by the mode pin (see vddq and vtt discharge control section). each state code represents as follows; s0 = full on, s3 = suspend to ram (str), s4 = suspend to disk (std), s5 = soft off. (see table 2) ddq ref r1 vv1 r2 ?? ?? =+ ?? ?? ?? ?? phase lgate r1 r2 v ddq v in ugate vddq fb gnd
RT8207 19 ds8207-07 march 2011 www.richtek.com table 2. s3 and s5 truth table state s3 s5 vddq s0 hi hi on s3 lo hi on s4/s5 lo lo off (discharge) state vttref vtt s0 on on s3 on off (hi-z) s4/s5 off (discharge) off (discharge) vddq and vtt discharge control (mode) the RT8207 discharge vddq, vttref and vtt outputs during s3 and s5 are both low. there are two different discharge modes. the discharge mode can be set by connecting mode pin as shown in table 3. table 3. discharge selection mode discharge mode vdd no discharge vddq tracking discharge gnd non-tracking discharge when in tracking discharge mode, the RT8207 discharges outputs through the internal vtt regulator transistors and vtt output tracks half of vddq voltage during this discharge. note that vddq discharge current flows via vldoin to vttgnd, thus vldoin must be connected to vddq in this mode. the internal ldo can handle up to 3a and can be dischargeed quickly. after vddq is discharged down to 0.15v, the terminal ldo will be turned off and the operation mode will be changed to the non- tracking discharge mode. when in non-tracking discharge mode, the RT8207 discharges outputs using internal mosfets which are connected to vddq and vtt. the current capability of these mosfets are limited to discharge slowly. note that vddq discharge current flows from vddq to gnd in this mode. in case of no discharge mode, the RT8207 does not discharge output charge at all. output inductor selection the switching frequency (on-time) and operating point (% ripple or l ir ) determine the inductor value as follows : where l ir is the ratio of the peak to peak ripple current to the average inductor current. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough to prevent it from saturating at the peak inductor current (i peak ) : i peak = i load(max) + [(l ir / 2) x i load(max) ] this inductor ripple current also impacts transient-response performance, especially at low vin ? vddq differences. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the peak amplitude of the output transient (v sag ) is also a function of the output transient. the v sag is also features a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time : where minimum off-time (t off(min) )=400ns(typical). output capacitor selection the output filter capacitor must have low enough esr to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no- load condition without tripping the ovp circuit. for cpu core voltage converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: ? = on in ddq ir load(max) t(vv) l li () ?+ = ?? ?+ ?? 2 sag load on off(min) out ddq in on ddq on off(min) v (i ) l (t t ) 2c v v t v t t p-p load(max) v esr i in non-cpu applications, the output capacitor's size depends on how much esr is needed to maintain an acceptable level of output voltage ripple : p-p ir load(max) v esr li where v p-p is the peak-to-peak output voltage ripple.
RT8207 20 ds8207-07 march 2011 www.richtek.com organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. for low input-to-output voltage differentials (vin/vddq < 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode. the amount of overshoot due to stored inductor energy can be calculated as : where i peak is the peak inductor current. output capacitor stability stability is determined by the value of the esr zero relative to the switching frequency. the point of instability is given by the following equation : do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. large ceramic capacitors can have a high- esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting vddq or the fb divider close to the inductor. unstable operation manifests itself in two related and distinctly different ways: double-pulsing and feedback loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ? fools ? the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. double- pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under- or over-shoot. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) - t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8207, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-24l 4x4 packages, the thermal resistance ja is 54 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (52 c/w) = 1.923w for wqfn-24l 4x4 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8207 packages, the figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. = 2 peak soar out ddq (i ) l v 2c v = sw esr out 1f f 2 esr c 4
RT8207 21 ds8207-07 march 2011 www.richtek.com layout considerations layout is very important in high frequency switching converter design. if the ic is designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. certain points must be considered before starting a layout for the RT8207. ` connect an rc low-pass filter from vddp to vdd, 1 f and 5.1 are recommended. place the filter capacitor close to the ic. ` keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high-voltage switching node. ` connections from the drivers to the respective gate of the high-side or the low-side mosfet should be as short as possible to reduce stray inductance. ` all sensitive analog traces and components such as vddq, fb, pgnd, dem, pgood, cs, vdd, and ton should be placed away from high-voltage switching nodes such as phase, lgate, ugate, or boot nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` vldoin should be connected to vddq output with short and wide trace. if different power source is used for vldoin, an input bypass capacitor should be placed to the pin as close as possible with short and wide trace. ` the output capacitor for vtt should be placed close to the pin with short and wide connection in order to avoid additional esr and/or esl of the trace. ` vttsns should be connected to the positive node of vtt output capacitor(s) as a separate trace from the high current power line and is strongly recommended to avoid additional esr and/or esl. if it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. also, it is recommended to minimize any additional esr and/or esl of ground trace between gnd pin and the output capacitor(s). ` current sense connections must always be made using kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses. figure 5. derating curves for RT8207 packages 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) four layers pcb wqfn-24l 4x4
RT8207 22 ds8207-07 march 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e d2 e2 l b e 1 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.950 4.050 0.156 0.159 d2 2.300 2.750 0.091 0.108 e 3.950 4.050 0.156 0.159 e2 2.300 2.750 0.091 0.108 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 24l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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