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3-channel digital potentiometer with nonvolatile memory adn2860 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2009 analog devices, inc. all rights reserved. features 3 channels dual 512-position single 128-position 25 k or 250 k full-scale resistance low temperature coefficient potentiometer divider 15 ppm/c rheostat mode 35 ppm/ c nonvolatile memory retains wiper settings permanent memory write protection linear increment/decrement 6 db increment/decrement i 2 c-compatible serial interface 2.7 v to 5.5 v single-supply operation 2.25 v to 2.75 v dual-supply operation power-on reset time 256 bytes general-purpose user eeprom 11 bytes rdac user eeprom gbic and sfp compliant eeprom 100-year typical data retention at t a = 55c applications laser diode drivers optical amplifiers tia gain setting tec controller temperature setpoint functional block diagram a0 w0 b0 a1 w1 b1 a2 w2 b2 a0 w0 b0 a0 w0 b0 a1 w1 b1 a1 w1 b1 a2 w2 b2 a2 w2 b2 rdac0 rdac0 register rdac1 register rdac2 register 9 bits rdac1 9 bits rdac2 7 bits data control command decode logic address decode logic decode logic power-on reset i 2 c serial interface 32 bytes rdac eeprom 256 bytes user eeprom v dd v ss dgnd scl sda ad0 ad1 a0_ee a1_ee reset wp 03615-001 figure 1. general description the adn2860 provides dual 512-position and single 128-position, digitally controlled variable resistors 1 (vr) in a single 4 mm 4 mm lfcsp package. this device performs the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. each vr offers a completely programmable value of resistance between the a terminal and the wiper, or the b terminal and the wiper. the fixed a-to-b terminal resistance of 25 k or 250 k has a 1% channel-to- channel matching tolerance and a nominal temperature coefficient of 35 ppm/c. wiper position programming, eeprom 2 reading, and eeprom writing are conducted via the standard 2-wire i 2 c interface. pre- vious default wiper position settings can be stored in memory, and refreshed upon system power-up. additional features of the adn2860 include preprogrammed linear and logarithmic increment/decrement wiper changing. the actual resistor tolerances are stored in eeprom so that the actual end-to-end resistance is known, which is valuable for calibration in precision applications. the adn2860 eeprom, channel resolution, and package size conform to gbic and sfp specifications. the adn2860 is available in a 4 mm 4 mm, 24-lead lfcsp package. all parts are guaranteed to operate over the extended industrial tempera- ture range ?40c to +85c. 1 the terms programmable resistor, variable resistor, rdac, and digital potentiometer are used interchangeably. 2 the terms nonvolatile memory, eemem, and eeprom are used interchangeably.
adn2860 rev. b | page 2 of 20 table of contents electrical characteristics ................................................................. 3 electrical characteristics ................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 interface descriptions .................................................................... 10 i 2 c interface ................................................................................ 10 eeprom interface ..................................................................... 11 rdac i 2 c interface .................................................................... 12 theory of operation ...................................................................... 15 linear increment and decrement commands ...................... 15 logarithmic taper mode adjustment ( 6 db/step) .............. 15 using additional internal nonvolatile eeprom .................. 16 digital input/output configuration ........................................ 16 multiple devices on one bus ................................................... 16 level shift for bidirectional communication ........................ 16 terminal voltage operation range ......................................... 16 power-up sequence ................................................................... 17 layout and power supply biasing ............................................ 17 rdac structure .......................................................................... 17 calculating the programmable resistance ............................. 17 programming the potentiometer divider ............................... 18 applications ..................................................................................... 19 laser diode driver (ldd) calibration ................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 4/09rev. a to rev. b changes to eeprom write protection section ......................... 12 11/04rev. 0 to rev. a changes to ordering guide .......................................................... 20 7/04revision 0: initial version
adn2860 rev. b | page 3 of 20 electrical characteristics single supply: v dd = 2.7 v to 5.5 v and ?40c < t a < +85c, unless otherwise noted. dual supply: v dd = +2.25 v or +2.75 v, v ss = ?2.25 v or ?2.75 v, and ?40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode resistor differential nonlinearity 2 r-dnl r wb , 7-bit channel ?0.75 +0.75 lsb r wb , 9-bit channels ?2.5 +2.5 lsb resistor integral nonlinearity 2 r-inl r wb , 7-bit channel ?0.5 +0.5 lsb r-inl r wb , 9-bit channels, v dd = 5.5 v ?2.0 +2.0 lsb r-inl r wb , 9-bit channels, v dd = 2.7 v ?4.0 +4.0 lsb resistance temperature coefficent (?r wb /r wb )/?t 10 6 35 ppm/c wiper resistance r w v dd = 5 v, i w = 1 v/r wb 100 150 v dd = 3 v, i w = 1 v/r wb 250 400 channel resistance matching ?r ab1 /?r ab2 ch 1 and ch 2 r wb , dx = 0x1ff 0.1 % nominal resistor tolerance ?r ab /r ab dx = 0x3ff ?15 +15 % dc characteristics, potentiometer divider mode differential nonlinearity 3 dnl 7-bit channel ?0.5 +0.5 lsb dnl 9-bit channels ?2.0 +2.0 lsb integral nonlinearity 3 inl 7-bit channel ?0.5 +0.5 lsb inl 9-bit channels ?2.0 +2.0 lsb voltage divider temperature coefficent (?v w /v w )/?t 10 6 code = half scale 15 ppm/c full-scale error v wfse 7-bit channel/9-bit channels, code = full scale ?1/?2.75 0/0 lsb zero-scale error v wzse 7-bit channel/9-bit channels, code = zero scale 0/0 1/2.0 lsb resistor terminals terminal voltage range 4 v a, b, w v ss v dd v capacitance 5 ax, bx c a,b f = 1 khz, measured to gnd, code = half scale 85 pf capacitance 5 wx c w f = 1 khz, measured to gnd, code = half scale 95 pf common-mode leakage current 5 , 6 i cm v w = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5 v, v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 0.6 v output logic high (sda) v oh r pull-up = 2.2 k to v dd = 5 v, v ss = 0 v 4.9 v output logic low v ol r pull-up = 2.2 k to v dd = 5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 9 a a0 leakage current i a0 a0 = gnd 3 a
adn2860 rev. b | page 4 of 20 parameter symbol conditions min typ 1 max unit input leakage current (excluding wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd, v ss = 0 v 5 15 a negative supply current i ss v ih = v dd or v il = gnd, v dd = 2.5 v, v ss = ?2.5 v ?5 ?15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd 35 ma eemem data restoring mode current i dd_restore v ih = v dd or v il = gnd 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 25 75 w power supply sensitivity 5 p ss ?v dd = 5 v 10% 0.01 0.025 %/% 1 typical represents average readings at 25c, v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. 4 resistor terminals a, b, and w have no limit ations on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the f astest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 03615-015 sd a scl ps sp t 1 t 2 t 3 t 8 t 8 t 9 t 4 t 5 t 7 t 10 t 6 figure 2. i 2 c timing diagram
adn2860 rev. b | page 5 of 20 electrical characteristics single supply: v dd = 3 v to 5.5 v and ?40c < t a < +85c, unless otherwise noted. dual supply: v dd = +2.25 v or +2.75 v, v ss = ?2.25 v or ?2.75 v, and ?40c < t a < +85c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dynamic characteristics 2 , 3 bandwidth ?3 db bw v dd /v ss = 2.5 v, r ab = 25 k/250 k. 125/12 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz. 0.05 % v w settling time t s v a = v dd , v b = 0 v, v w = 0.50% error band, code = 0x000 to 0x100, r ab = 25 k/250 k. 4/36 s resistor noise spectral density e n_wb r ab = 25 k/250 k, t a = 25c. 14/45 nvhz digital crosstalk c t v a = v dd , v b = 0 v, measure vw with adjacent rdac making full-scale change. ?80 db analog crosstalk c at signal input at a0 and measure output at w1, f = 1 khz. ?72 db interface timing characteristics (apply to all parts) 4 , 5 scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 600 ns t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for start condition t 5 600 ns t hd;dat data hold time t 6 900 ns t su;dat data setup time t 7 100 ns t r rise time of both sda and scl signals t 8 300 ns t f fall time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 600 ns eemem data storing time t eemem_store 26 ms eemem data restoring time at power-on t eemem_restore1 360 s eemem data restoring time on restore t eemem_restore2 360 s command or reset operation eemem data rewritable time t eemem_rewrite 540 s flash/ee memory reliability endurance 6 100 kcycles data retention 7 55c. 100 years 1 typical represents average readings at 25c, v dd = 5 v. 2 all dynamic characteristics use v dd = 5 v. 3 guaranteed by design and not subject to production test. 4 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the f astest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 5 see figure 2 for the location of measured values. 6 endurance is qualified to 100,000 cycles as per jedec std. 22 metho d a117 and measured at ?40c, +25c, and +85c. typical end urance at 25c is 700,000 cycles. 7 retention lifetime equivalent at junction temperature (t j ) = 55c as per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6 ev derates with junction temperature.
adn2860 rev. b | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v, +7 v v ss to gnd +0.3 v, ?7 v v dd to v ss 7 v v a , v b , v w to gnd v ss ? 0.3 v, v dd + 0.3 v i a , i b , i w intermittent 1 20 ma continuous 2 ma digital inputs and output voltage to gnd ?0.3 v, v dd + 0.3 v operating temperature range 2 ?40c to +85c maximum junction temperature (t j max) 150c storage temperature ?65c to +150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c thermal resistance junction-to-ambient ja lfcsp-24 32c/w 1 includes programming of nonvolatile memory. 2 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adn2860 rev. b | page 7 of 20 pin configuration and fu nction descriptions pin 1 indicator nc = no connect 1reset 2wp 3scl 4sda 5dgnd 6v ss v dd 15 a0 16 17 test3 (nc) 18 test2 (nc) 14 w0 13 b0 7 a 2 8 w 2 9 b 2 1 1 w 1 1 2 b 1 1 0 a 1 2 1 a 1 _ e e 2 2 a 0 _ e e 2 3 a d 1 2 4 a d 0 2 0 t e s t 0 ( n c ) 1 9 t e s t 1 ( n c ) top view (not to scale) ad2860 03615-014 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 reset resets the scratchpad register with current contents of the eemem register. factory defaults to midscale before any programming. 2 wp write protect. when active low, wp prevents any changes to the present register contents, except that reset and commands 1 and 8 still refresh the rdac register from eemem. 3 scl serial input register clock. shifts in on e bit at a time upon the positive clock edges. 4 sda serial data input. shifts in one bit at a time upon the positive edges. the msb is loaded first. 5 dgnd ground. logic ground reference. 6 v ss negative supply. connect to 0 v for single-supply applications. 7 a2 a terminal of rdac2. 8 w2 wiper terminal of rdac2. 9 b2 b terminal of rdac2. 10 a1 a terminal of rdac1. 11 w1 wiper terminal of rdac1. 12 b1 b terminal of rdac1. 13 b0 b terminal of rdac0. 14 w0 wiper terminal of rdac0. 15 a0 a terminal of rdac0. 16 v dd positive power supply. 17 test3 test pin 3. do not connect. 18 test2 test pin 2. do not connect. 19 test1 test pin 1. do not connect. 20 test0 test pin 0. do not connect. 21 a1_ee i 2 c device address 1 for eemem. 22 a0_ee i 2 c device address 0 for eemem. 23 ad1 i 2 c device address 1 for rdac. 24 ad0 i 2 c device address 0 for rdac.
adn2860 rev. b | page 8 of 20 typical performance characteristics ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl (lsb) 256 192 64 128 0 320 384 448 512 code (decimal) 03615-002 t a = ?40c, +25c, +85c superimposed v dd = 5v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 r-dnl (lsb) 256 192 64 128 0 320 384 448 512 code (decimal) 03615-005 t a = ?40c, +25c, +85c superimposed v dd = 5v figure 4. inl9-bit rdac figure 7. r-dnl9-bit rdac ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 inl (lsb) 64 48 16 32 0 80 96 112 128 code (decimal) 03615-006 t a = ?40c, +25c, +85c superimposed v dd = 5v ?1.50 ?1.00 ?0.50 ?0.75 ?1.25 0 ?0.25 dnl (lsb) 0.50 0.25 1.00 0.75 1.50 1.25 256 192 64 128 0 320 384 448 512 code (decimal) 03615-003 t a = ?40c, +25c, +85c superimposed v dd = 5v figure 5. dnl9-bit rdac figure 8. inl7-bit rdac ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 r-inl (lsb) 256 192 64 128 0 320 384 448 512 code (decimal) 03615-004 t a = ?40c, +25c, +85c superimposed v dd = 5v ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (lsb) 64 48 16 32 0 80 96 112 128 code (decimal) 03615-007 t a = ?40c, +25c, +85c superimposed v dd = 5v figure 6. r-inl9-bit rdac figure 9. dnl7-bit rdac
adn2860 rev. b | page 9 of 20 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 r-inl (lsb) 64 48 16 32 0 80 96 112 128 code (decimal) 03615-008 t a = ?40c, +25c, +85c superimposed v dd = 5v figure 10. r-inl7-bit rdac ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 r-dnl (lsb) 64 48 16 32 0 80 96 112 128 code (decimal) 03615-009 t a = ?40c, +25c, +85c superimposed v dd = 5v figure 11. r-dnl7-bit rdac 0 5 10 15 20 25 30 35 40 45 50 rheostat mode te mpco (ppm/c) 256 192 64 128 0 320 384 448 512 code (decimal) 03615-010 t a = ?40c, +85c v dd = 5v v a = v dd v b = 0v figure 12. temperature coefficient (rheostat mode) 0 5 10 15 20 25 30 35 40 45 50 potentiometer mode tempco (ppm/c) 256 192 64 128 0 320 384 448 512 code (decimal) 03615-011 t a = ?40c, +85c v dd = 5v v a = v dd v b = 0v figure 13. temperature coefficient (potentiometer mode) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 supply current (ma) ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 03615-012 i dd : v dd = 5.5v i dd : v dd = 2.7v i s : v dd = 2.7v, v ss = 2.7v figure 14. supply current vs. temperature 30 40 50 60 70 80 i dd (ma) 90 100 110 110 1 10 2 10 3 10 4 10 5 10 6 10 7 clock frequency (hz) 03615-013 t a = 25c v dd = 5.5v v dd = 2.7v figure 15. supply current vs. clock frequency
adn2860 rev. b | page 10 of 20 interface descriptions i 2 c interface all control and access to both eeprom memory and the rdac registers are conducted via a standard 2-wire i 2 c interface. figure 2 shows the timing characteristics of the i 2 c bus. figure 16 and figure 17 illustrate standard transmit and receive bus signals in the i 2 c interface. these figures use the following legend: from master to slave from slave to master s = start condition p = stop condition a = acknowledge (sda low) a = not acknowledge (sda high) r/ w = read enable at high and write enable at low slave address s 0 = write a data a data transferred (n bytes + acknowledge) data a/a p 03615-016 r/w figure 16. i 2 cmaster transmitting data to slave slave address s 1 = write a data a data transferred (n bytes + acknowledge data a p 03615-017 r/w figure 17. i 2 cmaster reading data from slave slave address s read or write a data (n bytes + acknowledge) a/a p 03615-018 r/w slave address s read or write repeated start a data (n bytes + acknowledge) a/a r/w direction of transfer may change at this point figure 18. combined transmit/read
adn2860 rev. b | page 11 of 20 eeprom interface memory address memory data memory data saa a aa 00 01 ee 0 01 1 p 03615-019 0 write (n bytes + acknowledge) eeprom slave address a/a figure 19. eeprom write memory data memory data saa aa 00 01 ee 0 01 1 p 03615-020 1 read (n bytes + acknowledge) eeprom slave address a figure 20. eeprom current read slave address memory address s 0 write aa p 03615-021 w slave address memory data sr 1 read repeated start a (n bytes + acknowledge) a/a figure 21. eeprom random read the 256 bytes of eeprom memory provided in the adn2860 are organized into 16 pages of 16 bytes each. the word size of each memory location is one byte wide. the i 2 c slave address of the eeprom is 10100(a1e)(a0e), where a1e and a0e are external pin-programmable address bits. the 2-pin programmable address bits allow a total of four adn2860 devices to be controlled by a single i 2 c master bus, each having its own eeprom. an internal 8-bit address counter for the eeprom is automatically incremented following each read or write operation. for read operations, the address counter is incremented after each byte is read, and the counter rolls over from address 255 to 0. for write operations, the address counter is incremented after each byte is written. the counter rolls over from the highest address of the current page to the lowest address of the current page. for example, writing two bytes beginning at address 31 causes the counter to roll back to address 16 after the first byte is written; then the address increments to 17 after the second byte is written. eeprom write each write operation issued to the eeprom programs between 1 byte and 16 bytes (one page) of memory. figure 19 shows the eeprom write interface. the number of bytes of data, n, that the user wants to send to the eeprom is unrestricted. if more than 16 bytes of data are sent in a single write operation, the address counter rolls back to the beginning address, and the previously sent data is overwritten. eeprom write-acknowledge polling after each write operation, an internal eeprom write cycle begins. during the eeprom internal write cycle, the i 2 c interface of the device is disabled. it is necessary to determine if the internal write cycle is complete and whether the i 2 c interface is enabled. to do so, execute i 2 c interface polling by sending a start condition, followed by the eeprom slave address plus the desired r/ w bit. if the adn2860 i 2 c interface responds with an ack, the write cycle is complete and the interface is ready to proceed with further operations. otherwise, the i 2 c interface must be polled again to determine whether the write cycle has been completed. eeprom read the adn2860 eeprom provides two different read operations, shown in figure 20 and figure 21 . the number of bytes, n, read from the eeprom in a single operation is unrestricted. if more than 256 bytes are read, the address counter rolls back to the start address, and data previously read is read again. figure 20 shows the eeprom current read operation. this operation does not allow an address location to be specified, and reads data beginning at the current address location stored in the internal address counter.
adn2860 rev. b | page 12 of 20 a random read operation is shown in figure 21 . this operation changes the address counter to the specified memory address by performing a dummy write and then performing a read operation beginning at the new address counter location. eeprom write protection setting the wp pin to logic low protects the eeprom memory from future write operations. in this mode, eeprom and rdac register readings operate normally. rdac i 2 c interface data data sa a a aa 10 0 01 r ee/ rd a 4 a 3 a 2 a 1 a 0 ac cmd/ reg r 1 10 0 p 03615-022 0 write (n bytes + acknowledge) rdac address rdac slave address a/a figure 22. rdac write sa aa 11 01 r a rdac eeprom or register data rdac eeprom or register data r 1 10 0 p 03615-023 1 read (n bytes + acknowledge) rdac slave address a figure 23. rdac current read slave address rdac address s 0 write aa p 03615-024 w slave address rdac data sr 1 read repeated start a (n bytes + acknowledge) a/a figure 24. rdac random read sa aa 10 01 r c 1 c 2 c 3 c 0 a 2 a 1 a 0 cmd/ reg r 1 10 0 p 03615-025 a 0 write 1 cmd rdac slave address figure 25. rdac shortcut commands table 5. rdac register addresses (cmd/ reg = 0, ee/ rdac = 0) a4 a3 a2 a1 a0 rdac byte description 0 0 0 0 0 rdac0 (d7)(d6)(d5)(d4)(d3)(d2)(d1)(d0)rdac0 8 lsbs 0 0 0 0 1 rdac0 (x)(x)(x)(x)(x)(x)(x)(d8)rdac0 msb 0 0 0 1 0 rdac1 (d7)(d6)(d5)(d4)(d3)(d2)(d1)(d0)rdac1 8 lsbs 0 0 0 1 1 rdac1 (x)(x)(x)(x)(x)(x)(x)(d8)rdac1 msb 0 0 1 0 0 rdac2 (x)(d6)(d5)(d4)( d3)(d2)(d1)(d0)rdac2 7 bits 0 0 1 0 1 reserved to 1 1 1 1 1
adn2860 rev. b | page 13 of 20 table 6. rdac r/ w eeprom addresses (cmd/ reg = 0, ee/ rdac = 1) a4 a3 a2 a1 a0 byte description 0 0 0 0 0 rdac0 8 lsbs 0 0 0 0 1 rdac0 msb 0 0 0 1 0 rdac1 8 lsbs 0 0 0 1 1 rdac1 msb 0 0 1 0 0 rdac2 7 bits 0 0 1 0 1 11 bytes rdac user eeprom to 0 1 1 1 1 table 7. rdac command table (cmd/ reg = 1) c3 c2 c1 c0 command description 0 0 0 0 nop. 0 0 0 1 restore eeprom to rdac. 1 0 0 1 0 store rdac to eeprom. 2 0 0 1 1 decrement rdac 6 db. 0 1 0 0 decrement all rdacs 6 db. 0 1 0 1 decrement rdac one step. 0 1 1 0 decrement all rdacs one step. 0 1 1 1 reset. restore eeprom to all rdacs. 2 1 0 0 0 increment rdac 6 db. 1 0 0 1 increment all rdacs 6 db. 1 0 1 0 increment rdac one step. 1 0 1 1 increment all rdacs one step. 1 1 0 0 reserved. to 1 1 1 1 1 command leaves the device in the eeprom read power state. i ssue the nop command to return the device to the idle state. 2 command requires acknowledg e polling after execution. rdac interface operation each programmable resistor wiper setting is controlled by specific rdac registers, as shown in table 5 . each rdac register corresponds to an eeprom memory location, which provides nonvolatile wiper storage functionality. rdac registers and their corresponding eeprom memory locations are programmed and read independently from each other. the rdac register is refreshed by the eeprom locations, either with a hardware reset via pin 1, or by issuing one of the various rdac register load commands shown in the table 7 . rdac write setting the wiper position requires an rdac write operation, shown in figure 22 . rdac write operations follow a format similar to the eeprom write interface. the only difference between an rdac write and an eeprom write operation is the use of an rdac address byte in place of the memory address used in the eeprom write operation. the rdac address byte is described in detail in table 5 and table 6 . as with the eeprom write operation, any rdac eeprom (shortcut command 2) write operation disables the i 2 c interface during the internal write cycle. acknowledge polling, as described in the eeprom interface section, is required to determine whether the write cycle is complete. rdac read the adn2860 provides two rdac read operations. the first, shown in figure 23 , reads the contents of the current rdac address counter. figure 24 illustrates the second read operation, which allows users to specify which rdac register to read by first issuing a dummy write command to change the rdac address pointer, and then proceeding with the rdac read operation at the new address location. the read-only rdac eeprom memory locations can also be read by using the address and bits specified in table 6 .
adn2860 rev. b | page 14 of 20 rdac shortcut commands eleven shortcut commands are provided for easy manipulation of rdac registers and their corresponding eeprom memory locations. these commands are shown in table 9 . a more detailed discussion about the rdac shortcut commands can be found in the theory of operation section. the interface for issuing an rdac shortcut command is shown in figure 25 . all shortcut commands require acknowledge polling to determine whether the command has finished executing. rdac resistor tolerance the end-to-end resistance tolerance for each rdac channel is stored in read-only memory during factory production. this information is read by using the address and bits specified in table 8 . tolerance values are stored in percentage form. figure 26 shows the format of the tolerance data stored in memory. each stored tolerance uses two memory locations. the first location stores the integer portion, while the second location stores the decimal portion. the resistance tolerance is stored in sign-magnitude format. the msb of the first memory location designates the sign (0 = +, 1 = ?) and the remaining 7 lsbs are designated for the integer portion of the tolerance. all eight bits of the second memory location are represented by the decimal portion of the tolerance value. table 8. addresses for reading tolerance (cmd/ reg = 0, ee/ rdac = 1, a4 = 1) a4 a3 a2 a1 a0 data byte description 1 1 0 0 0 sign and 7-bit integer valu es of rdac0 tolerance (read only) 1 1 0 0 1 8-bit decimal value of rdac0 tolerance (read only) 1 1 0 1 0 sign and 7-bit integer valu es of rdac1 tolerance (read only) 1 1 0 1 1 8-bit decimal value of rdac1 tolerance (read only) 1 1 1 0 0 sign and 7-bit integer valu es of rdac2 tolerance (read only) 1 1 1 0 1 8-bit decimal value of rdac2 tolerance (read only) 7 bits for integer number sign sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a a d6 d5 d4 d3 d2 d1 d0 d7 2 ?2 2 ?1 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 2 ?8 a d6 d5 d4 d3 d2 d1 d0 d7 8 bits for decimal number 03615-026 figure 26. format of stored tolerance in sign magnitude with bi t position descriptions (unit is in %, only data bytes shown)
adn2860 rev. b | page 15 of 20 theory of operation the adn2860 digital potentiometer operates as a true variable resistor. the rdac register contents determine the resistor wiper position. the rdac register acts like a scratchpad register, allowing unlimited resistance setting changes. rdac register contents are changed using the adn2860s serial i 2 c interface. see the rdac i2c interface section for the format of the data words and commands to program the rdac registers. each rdac register has a corresponding eeprom memory location, which provides nonvolatile storage of resistor wiper position settings. the adn2860 provides commands to store the rdac register contents to their respective eeprom memory locations. during subsequent power-on sequences, the rdac registers are automatically loaded with the stored values. saving data from an rdac register to eeprom memory takes approximately 25 ms and consumes 35 ma. in addition to moving data between rdac registers and eeprom memory, the adn2860 provides other shortcut commands. table 9. adn2860 shortcut commands no. function 1 restore eeprom setting to rdac 1 2 store rdac register contents to eeprom 2 3 decrement rdac 6 db (s hift data bits right) 4 decrement all rdacs 6 db (shift all data bits right) 5 decrement rdac one step 6 decrement all rdacs one step 7 reset eeprom setting to rdac 2 8 increment rdac 6 db (shift data bits left) 9 increment all rdacs 6 db (shift all data bits left) 10 increment rdac one step 11 increment all rdacs one step __________________________ 1 command leaves the device in the eepro m read power state. issue the nop command to return the devi ce to the idle state. 2 command requires acknowledg e polling after execution. linear increment and decrement commands the increment and decrement commands (commands 10, 11, 5, and 6) are useful for linear step adjustment applications. these commands simplify microcontroller software coding by allowing the controller to send only an increment or decrement command to the adn2860. the adjustment can be directed to an individual rdac or to all three rdacs. logarithmic taper mode adjustment ( 6 db/step) the adn2860 accommodates logarithmic taper adjustment of the rdac wiper position(s) by shifting the register contents left/right for increment/decrement operations. commands 8, 9, 3, and 4 are used to logarithmically increment or decrement the wiper positions individually or change all three channel settings at the same time. incrementing the wiper position by +6 db doubles the rdac register value, whereas decrementing by ?6 db halves it. internally, the adn2860 uses a shift register to shift the bits left and right to achieve a logarithmic increment or decrement. nonideal 6 db step adjustment occurs under certain conditions. table 10 illustrates how the shifting function affects the data bits of an individual rdac. each row going down the table represents a successive shift operation. note that the left-shift commands (commands 10 and 11) were modified such that if the data in the rdac register equals 0 and the data is shifted, the rdac register is set to code 1. similarly, if the data in the rdac register is greater than or equal to midscale and the data is left shifted, the data in the rdac register is automatically set to full scale. this makes the left-shift function as close as possible to a logarithmic adjustment. the right-shift commands (commands 3 and 4) are ideal only if the lsb is a 0 (ideal logarithmic = no error). if the lsb is 1, the right-shift function generates a linear half lsb error. table 10. rdac register contents after 6 db step adjustments left shift (+6 db/step) right shift (?6 db/step) 0 0000 0000 1 1111 1111 0 0000 0001 0 1111 1111 0 0000 0010 0 0111 1111 0 0000 0100 0 0011 1111 0 0000 1000 0 0001 1111 0 0001 0000 0 0000 1111 0 0010 0000 0 0000 0111 0 0100 0000 0 0000 0011 0 1000 0000 0 0000 0001 1 0000 0000 0 0000 0000 1 1111 1111 0 0000 0000 1 1111 1111 actual conformance to a logarithmic curve between the data contents in the rdac register and the wiper position for each right-shift command (commands 3 and 4) execution contains an error only for odd numbers of bits. even numbers of bits are ideal. figure 26 shows a plot of log_error, that is, 20 log10(error/code), for the adn2860.
adn2860 rev. b | page 16 of 20 using additional internal nonvolatile eeprom the adn2860 contains additional internal user eeprom for saving constants and other data. the user eeprom i 2 c data- word follows the same format as the general-purpose eeprom memory shown in figure 19 and figure 20 . user eeprom memory addresses are shown in table 6 . to support the use of multiple eeprom modules on a single i 2 c bus, the adn2860 features two external addressing pins, pins 21 and 22 (a1_ee and a0_ee), to manually set the address of the eeprom included with the adn2860. this feature ensures that the correct eeprom memory is accessed when using multiple memory modules on a single i 2 c bus. digital input/output configuration all digital inputs are esd protected. digital inputs are high impedance and can be driven directly from most digital sources. the reset digital input pin does not have an internal pull-up resistor. therefore, the user should place a pull-up resistor from reset to v dd if the function is not used. the wp pin has an internal pull-down resistor. if not driven by an external source, the adn2860 defaults to a write-protected state. esd protection of the digital inputs is shown in . figure 27 wp inputs v dd gnd 03615-027 figure 27. equivalent wp esd protection multiple devices on one bus figure 28 shows four adn2860 devices on the same serial bus. each has a different slave address because the state of their ad0 and ad1 pins are different. this allows independent reading and writing to each rdac within each device. +5v r p r p master sda sda ad1 ad0 scl sda ad1 ad0 scl sda ad1 ad0 scl sda ad1 ad0 scl scl v dd v dd v dd 03615-028 figure 28. multiple adn2860 devices on a single bus level shift for bidirectional communication while most legacy systems operate at one voltage, adding a new component might require a different voltage. when two systems transmit the same signal at two different voltages, use a level shifter to allow the systems to communicate. for example, a 3.3 v microcontroller (mcu) can be used along with a 5 v digital potentiometer. a level shifter is required to enable bidirectional communication. figure 29 shows one of many possible techniques to properly level-shift signals between two devices. m1 and m2 are n-channel fets (2n7002). if v dd falls below 2.5 v, use low threshold n-channel fets (fdv301n) for m1 and m2. v dd1 = 3.3v v dd2 = 5v sda1 scl1 sda2 scl2 r p r p r p r p g g s s d d m1 m2 3.3v mcu 5v adn2860 03615-029 figure 29. level shifting for different voltage devices on an i 2 c bus terminal voltage operation range the adn2860 positive v dd and negative v ss power supply inputs define the boundary conditions for proper 2-terminal programmable resistance operation. supply signals on terminals w and b that exceed v dd or v ss are clamped by the internal forward-biased diodes of the adn2860. v dd v ss a w b 03615-030 figure 30. maximum terminal voltages set by v dd and v ss the ground pin of the adn2860 is used as a digital ground reference and needs to be tied to the common ground of the pcb. reference the digital input control signals to the adn2860 ground pin and satisfy the logic levels defined in table 1 and table 2 .
adn2860 rev. b | page 17 of 20 power-up sequence because the esd protection diodes limit the voltage compliance at the a, b, and w terminals ( figure 30 ), it is important to power v dd /v ss before applying voltage to the a, b, and w terminals. otherwise, the diode is forward biased such that v dd /v ss are powered unintentionally, which affects the rest of the circuit. the ideal power-up sequence is as follows: gnd, v dd , v ss , digital inputs, and v a/b/w . the order of powering v a , v b , v w , and the digital inputs is not important, as long as they are powered after v dd /v ss . layout and power supply biasing it is always a good practice to use compact, minimum-lead- length layout design. make the leads to the input as direct as possible with a minimum conductor length. make sure that ground paths have low resistance and low inductance. it is also a good practice to bypass the power supplies with quality capacitors. use low equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and filter low frequency ripple. figure 31 illustrates the basic supply-bypassing configuration for the adn2860. v dd v ss v dd v ss gnd adn2860 c3 c4 c1 c2 + + 10 f 10 f 0.1 f 0.1 f 03615-031 figure 31. power supply bypassing solder the slug on the bottom of the lfcsp package to a floating pad to improve thermal dissipation. do not connect the slug to a ground plane on the pcb. rdac structure the patent pending rdac contains a string of equal resistor segments with an array of analog switches. the switches together act as the wiper connection. the adn2860 has two rdacs with 512 connection points, allowing it to provide better than 0.2% progammability resolution. the adn2860 also contains a third rdac with 128-step resolution. figure 32 shows an equivalent structure of the connections between the two terminals that make up one channel of an rdac. the sw b switch is always on, while one of switches sw(0) to sw(2 n ? 1) may or may not be on at any given time, depending on the resistance position decoded from the data bits in the rdac register. since the switches are nonideal, there is a 100 wiper resistance, r w . wiper resistance is a function of supply voltage and temperature; lower supply voltages and higher temperatures result in higher wiper resistances. consideration of wiper resistance dynamics is important in applications in which accurate prediction of output resistance is required. 03615-032 rdac wiper register and decoder digital circuitry omitted for clarity r s = r ab /2 n r s r s r s a x w x b x sw b sw(0) sw(1) sw(2 n ?1) sw(2 n ?2) sw a figure 32. equivalent rdac structure calculating the programmable resistance the nominal resistance of the rdac between the a and b terminals is available in 25 k or 250 k. the final two or three digits of the part number determine the nominal resistance value, for example, 25 k = 25 and 250 k = 250. the following discussion describes the calculation of resistance r wb (d) at different codes of a 25 k part for rdac0. the 9-bit data-word in the rdac latch is decoded to select one of the 512 possible settings. the first wiper connection starts at the b terminal for data 0x000. r wb (0) is 100 of the wiper resistance and is independent of the full-scale resistance. the second connection is the first tap point where r wb (1) becomes 48.8 + 100 = 148.8 for data 0x001. the third connection is th e next tap point representing r wb (2) = 97.6 + 100 = 197.6 for data 0x002, and so on. each lsb data-value increase moves the wiper up the resistor ladder until the last tap point is reached at r wb (511) = 25,051 . see figure 32 for a simplified diagram of the equivalent rdac circuit. these general equations determine the programmed output resistance between terminals w and b.
adn2860 rev. b | page 18 of 20 for rdac0 and rdac1: () w ab wb rr d dr += 512 (1) for example, the following rdac latch codes set the corresponding output resistance values, which apply to r ab = 25 k digital potentiometers. table 12. r wa (d) at selected codes for r ab = 25 k d (dec) r wa (d) () output state for rdac2: () w ab wb rr d dr += 128 (2) 511 148.8 full scale 256 12600 midscale 1 25051 1 lsb 0 25100 zero scale where: d is the decimal equivalent of the data contained in the rdac register. r w is the wiper resistance. the typical distribution of r ab from channel to channel is 0.1% within the same package. device-to-device matching is lot dependent, with a worst-case variation of 15%. r ab temp- erature coefficient is 35 ppm/c. the output resistance values in table 11 are set for the given rdac latch codes with v dd = 5 v, which applies to r ab = 25 k digital potentiometers. programming the potentiometer divider voltage output operation table 11. r wb at selected codes for r wb_fs = 25 k d (dec) r wb (d) () the digital potentiometer can be configured to generate an output voltage at the wiper terminal, which is proportional to the input voltages applied to the a and b terminals. connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at the wiper that can vary between 0 v to 5 v. each lsb of voltage is equal to the voltage applied across the a and b terminals divided by the 2 n position resolution of the potentiometer divider. output state 511 25051 full scale 256 12600 midscale 1 148.8 1 lsb 0 100 zero scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 100 is present. to avoid degradation or possible destruction of the internal switches, care should be taken to limit the current flow between terminals w and b to no more than 20 ma intermittently or 2 ma continuously. since the adn2860 can operate from dual supplies, the general equations defining the output voltage at v w with respect to ground for any given input voltages applied to the a and b terminals are as follows: channel-to-channel r wb matching is better than 0.1%. the change in r wb with temperature has a 35 ppm/c temperature coefficient. for rdac0 and rdac1: () b ab w vv d dv += 512 (5) like the mechanical potentiometer that the rdac replaces, the adn2860 parts are totally symmetrical. the resistance between the w wiper and the a terminal also produces a digitally con- trolled complementary resistance, r wa . when r wa is used, the b terminal can be floating or tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general transfer equations for this operation are as follows: for rdac2: () b ab w vv d dv += 128 (6) for rdac0 and rdac1: () w ab wb rr d dr + ? = 512 512 (3) equation 5 assumes that v w is buffered to null the effect of wiper resistance. operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. in this mode, the output voltage is dependent on the ratio of the internal resistors, not on the absolute value; therefore, the drift improves to 15 ppm/c. there is no voltage polarity restriction between the a, b, and w terminals as long as the terminal voltage (v term ) stays within v ss < v term < v dd . for rdac2: () w ab wb rr d dr + ? = 128 128 (4)
adn2860 rev. b | page 19 of 20 applications information laser diode driver (ldd) calibration the adn2860 can be used with any laser diode driver. its high resolution, compact footprint, and superior temperature drift characteristics make it ideal for optical parameter setting. the adn2841 is a 2.7 gbps laser diode driver that uses a unique control algorithm to manage both the laser average power and extinction ratio after initial factory calibration. it stabilizes the laser data transmission by continuously monitoring its optical power and by correcting the variations caused by temperature and the laser degradation over time. in the adn2841, the i mpd monitors the laser diode current. through its dual-loop power and extinction ratio control, calibrated by the adn2860, the internal driver controls the bias current, i bias , and, consequently, the average power. it also regulates the modulation current, i modp , by changing the modulation current linearly with slope efficiency. any changes in the laser threshold current or slope efficiency are, therefore, compensated. as a result, this optical supervisory system minimizes the laser characterization efforts, enabling designers to apply comparable lasers from multiple sources. adn2860 adn2841 sda scl pset erset aset v cc v cc 03615-033 figure 33. optical supervisory system
adn2860 rev. b | page 20 of 20 outline dimensions 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vggd-2 figure 34. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-1) dimensions shown in millimeters ordering guide model r ab (k) temperature range package descript ion package option ordering quantity ADN2860ACPZ25-RL7 1 25 ?40c to +85c 24-lead lfcsp_vq cp-24-1 1,500 adn2860acpz250-rl7 1 250 ?40c to +85c 24-lead lfcsp_vq cp-24-1 1,500 1 z = rohs compliant part. ?2004C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03615-0-4/09(b)

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