204 tm march 1997 hm-65262/883 16k x 1 asynchronous cmos static ram features ? this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. ? fast access time . . . . . . . . . . . . . . . . . . . 70/85ns max ? low standby current. . . . . . . . . . . . . . . . . . . . 50 a max ? low operating current . . . . . . . . . . . . . . . . . 50ma max ? data retention at 2.0v . . . . . . . . . . . . . . . . . . . 20 a max ? ttl compatible inputs and outputs ? jedec approved pinout ? no clocks or strobes required ? temperature range . . . . . . . . . . . . . . . +55 o c to +125 o c ? gated inputs-no pull-up or pull-down resistors required ? equal cycle and access time ? single 5v supply description the hm-65262/883 is a cmos 16384 x 1-bit static ran- dom access memory manufactured using the intersil advanced saji v process. the device utilizes asynchro- nous circuit design for fast cycle times and ease of use. the hm-65262/883 is available in both jedec standard 20 pin, 0.300 inch wide cerdip and 20 pad clcc pack- ages, providing high board-level packing density. gated inputs lower standby current, and also eliminate the need for pull-up or pull-down resistors. the hm-65262/883, a full cmos ram, utilizes an array of six transistor (6t) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. in addition to this, the high stability of the 6t ram cell provides excellent protection against soft errors due to noise and alpha particles. this stability also improves the radiation tolerance of the ram over that of four transistor (4t) devices. pinouts ordering information 70ns/20 a 85ns/20 a 85ns/400 a temp. range package pkg. no. - hm1-65262/883 - -55 o c to +125 o c cerdip f20.3 hm4-65262b/883 hm4-65262/883 - -55 o c to +125 o c clcc j20.c hm1-65262/883 (cerdip) top view hm-65262 (clcc) top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 a0 a1 a2 a3 a4 a5 q a6 w gnd vcc a12 a11 a10 a13 a9 a8 a7 d e 3 4 5 6 7 9101112 220 119 8 15 14 18 17 16 13 a0 a1 a2 vcc a13 a3 a4 a5 a6 q a12 a11 a10 a9 a8 a7 w gnd e d a0 - a13 address input e chip enable/power down q data out d data in vss/gnd ground vcc power (+5) w write enable fn3003.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
205 functional diagram row address buffer 128 7 7 a0 a1 a2 a3 a12 a13 128 128 x 128 memory array a 7 a 7 a a row decoder (1 of 128) a4 column decoder (1 of 128) and i / o circuitry q w e d a7 a6 a8 a9 a10 a11 a5 column address buffers hm-65262/883
206 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input or output voltage applied for all grades . . . . . -0.3v to vcc +0.3v typical derating factor. . . . . . . . . . . . . . . .5ma/mhz increase in iccop esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance (typical) ja jc cerdip package. . . . . . . . . . . . . . . . . . 66 o c/w 13 o c/w clcc package . . . . . . . . . . . . . . . . . . . 75 o c/w 18 o c/w maximum storage temperature range . . . . . . . . . . . . -65 o c to +150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . . . +300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range. . . . . . . . . . . . . . . . -55 o c to +125 o c input low voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to +0.8v input high voltage (vih) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2v to vcc data retention supply voltage . . . . . . . . . . . . . . . . . . . 2.0v to 4.5v input rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns max. table 1. hm-65262/883 dc electrical performance specifications device guaranteed and 100% tested dc parameter symbol (note 1) conditions group a sub-groups temperature min max units high level output voltage voh1 vcc = 4.5v, io = -4.0ma 1, 2, 3 -55 o c t a +125 o c2.4 - v low level output voltage vol vcc = 4.5v, io = 8.0ma 1, 2, 3 -55 o c t a +125 o c- 0.4 v high impedance output leakage current ioz vcc = 5.5v, e = 5.5v, vo = gnd or vcc 1, 2, 3 -55 o c t a +125 o c-1.0 1.0 a input leakage current ii vcc = 5.5v, vi = gnd or vcc 1, 2, 3 -55 o c t a +125 o c-1.0 1.0 a standby supply current iccsb1 vcc = 5.5v, io = 0ma, e = vcc -0.3v 1, 2, 3 -55 o c t a +125 o c- 50 a standby supply current iccsb vcc = 5.5v, io = 0ma, e = 2.2v 1, 2, 3 -55 o c t a +125 o c- 5 ma operating supply current iccop vcc = 5.5v, (note 2), f = 1mhz, e = 0.8v 1, 2, 3 -55 o c t a +125 o c- 50 ma data retention supply current iccdr vcc = 2.0v, io = 0ma, e = vcc -0.3v 1, 2, 3 -55 o c t a +125 o c- 20 a enable supply current iccen vcc = 5.5v, io = 0ma, e = 0.8v 1, 2, 3 -55 o c t a +125 o c- 50 ma functional test ft vcc = 4.5v (note 3) 7, 8a, 8b -55 o c t a +125 o c- - - notes: 1. all voltages referenced to device gnd. 2. typical derating 1.5ma/mhz increase in iccop. 3. tested as follows: f = 2mhz, vih = 2.4v, vil = 0.4v, ioh = -4.0ma, iol = 4.0ma, voh 1.5v, and vol 1.5v. table 2. hm-65262/883 ac electrical performance specifications device guaranteed and 100% tested ac parameter symbol (notes 1, 2) conditions group a sub- groups temperature hm- 65262b/883 limits hm-65262/883 limits units min max min max read/write/cycle time (1) tavax vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c70 - 85 - ns address access time (2) tavqv vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c- 70 - 85 ns hm-65262/883
207 chip enable to end of write (3) telwh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c55 - 65 - ns chip enable access time (4) telqv vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c- 70 - 85 ns address hold time (5) twhax vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns address setup time (6) tavwl vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns address valid to end of write (7) tavwh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c55 - 65 - ns address setup time (8) tavel vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns address hold time (9) tehax vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns address valid to end of writes (10) taveh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c55 - 65 - ns write enable pulse write (11) twlwh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c40 - 45 - ns data setup time (12) tdvwh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c30 - 35 - ns data hold time (13) twhdx vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns enable pulse width (14) teleh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c55 - 65 - ns write to end of write (15) twleh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c40 - 45 - ns data setup time (16) tdveh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c30 - 35 - ns data hold time (17) tehdx vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns notes: 1. all voltages referenced to device gnd. 2. input pulse levels: 0.8v to vcc -2.0v; input rise and fall times: 5ns (max); input and output timing reference level: 1.5v; o utput load: 1 ttl gate equivalent, cl = 50pf (min) - for cl greater than 50pf, access time is derated by 0.15ns per pf. 3. tavqv = telqv + tavel. table 2. hm-65262/883 ac electrical performance specifications (continued) device guaranteed and 100% tested ac parameter symbol (notes 1, 2) conditions group a sub- groups temperature hm- 65262b/883 limits hm-65262/883 limits units min max min max table 3. hm-65262/883 electrical performance specifications, ac and dc parameter symbol (note 1) conditions notes temperature limits units min max input capacitance cin vcc = open, f = 1mhz, all measurements refer- enced to device grounds 1, 2 t a = +25 o c - 10 pf vcc = open, f = 1mhz, all measurements refer- enced to device grounds 1, 3 t a = +25 o c-6pf output capacitance co vcc = open, f = 1mhz, all measurements refer- enced to device grounds 1, 2 t a = +25 o c - 12 pf vcc = open, f = 1mhz, all measurements refer- enced to device grounds 1, 3 t a = +25 o c-8pf hm-65262/883
208 write enable to output in high z (18) twlqz vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c - 40 ns write enable high to output on (19) twhqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c0 -ns chip enable to output on (20) telqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c5 -ns output enable high to output in high z (21) tehqz vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c - 40 ns chip disable to output hold time (22) te- hqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c5 -ns address invalid output hold time (23) taxqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c5 -ns high level output voltage (24) voh2 vcc = 4.5v, io = -100ma 1 -55 o c t a +125 o c- vcc -0.4v - v notes: 1. the parameters listed in table 3 are controlled via design or process parameters and are not directly tested. these parameter s are characterized upon initial design release and upon design changes which would affect these characteristics. 2. applies to dip device types only. 3. applies to lcc device types only. table 3. hm-65262/883 electrical performance specifications, ac and dc (continued) parameter symbol (note 1) conditions notes temperature limits units min max table 4. applicable subgroups conformance groups method subgroups initial test 100%/5004 - interim test 100%/5004 1, 7, 9 pda 100%/5004 1 final test 100%/5004 2, 3, 8a, 8b, 10, 11 group a samples/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 groups c & d samples/5005 1, 7, 9 hm-65262/883
209 timing waveforms note: 1. w is high for entire cycle and d is ignored. address is stable by the time e goes low and remains valid until e goes high. figure 1. read cycle 1: controlled by e note: 1. w is high for the entire cycle and d is ignored. e is stable prior to a becoming valid and after a becomes invalid. figure 2. read cycle 2: controlled by address (20) telqx a (4) telqv (22) tehqx (21) tehqz e q (1) tavax (2) tavqv (20) telqx a e q (21) tehqz (23) taxqx hm-65262/883
210 low voltage data retention note: 1. in this mode, e rises after w . the address must remain stable whenever both e and w are low. figure 3. write cycle 1: controlled by w (late write) note: 1. in this mode, w rises after e . if w falls before e by a time exceeding twlqz (max) telqx (min), and rises after e by a time exceeding tehqz (max) twhqz (min), then q will remain in the high impedance state throughout the cycle. figure 4. write cycle 2: controlled by e (early write) timing waveforms (continued) a (7) tavwh (3) telwh (5) twhax (11) twlwh (6) (21) tehqz (13) twhdx (12) tdvwh (18) twlqz (20) telqx (19) twhqx (1) tavax e w d q tavwl (1) tavax (10) taveh e w d q (14) teleh (15) twleh (16) tdveh (9) tehax (19) twhqx (17) tehdx (20) telqx (18) twlqz (21) tehqz a (8) tavel hm-65262/883
211 intersil cmos rams are designed with battery backup in mind. data retention voltage and supply current are guaran- teed over temperature. the following rules ensure data retention: 1. chip enable (e ) must be held high during data retention; within vcc to vcc +0.3v. 2. on rams which have selects or output enables (e.g., s, g ), one of the selects or output enables should be held in the deselected state to keep the ram outputs high impedance, minimizing power dissipation. 3. inputs which are to be held high (e.g., e ) must be kept between vcc +0.3v and 70% of vcc during the power up and down transitions. 4. the ram can begin operation >55ns after vcc reaches the minimum operating voltage (4.5v). test circuit note: 1. test head capacitance includes stray and jig capacitance. vcc 2.0v 4.5v 4.5v vcc >55ns vcc -0.3v to vcc +0.3v data retention mode e figure 5. data retention timing dut 1.5v iol ioh + - (note 1) cl equivalent circuit hm-65262/883
212 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com burn-in circuits hm-65262/883 cerdip top view notes: all resistors 47k ? 5%. f0 = 100khz 10%. f1 = f0 2, f2 = f1 2, f3 = f2 2 . . . f13 = f12 2. vcc = 5.5v 0.5v. vih = 4.5v 10%. vil = -0.2v to +0.4v. c = 0.01 f min. hm-65262/883 clcc top view notes: all resistors 47k ? 5%. f0 = 100khz 10%. f1 = f0 2, f2 = f1 2, f3 = f2 2 . . . f13 = f12 2. vcc = 5.5v 0.5v. vih = 4.5v 10%. vil = -0.2v to +0.4v. c = 0.01 f min. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 a0 a1 a2 a3 a4 a5 q a6 w gnd vcc a12 a11 a10 a13 a9 a8 a7 d e f16 f14 f13 f12 f15 f11 f10 f2 f0 f3 f5 f6 f7 f4 f8 f9 f2 f1 3 4 5 6 7 9101112 220 119 8 15 14 18 17 16 13 a0 a1 a2 vcc a13 a3 a4 a5 a6 q a12 a11 a10 a9 a8 a7 w gnd e d f16 f0 f4 f5 f6 f7 f8 f9 f2 c vcc f15 f14 f13 f12 f11 f10 f1 f0 f2 hm-65262/883
213 die characteristics die dimensions: 148 x 187 x 19 mils metallization: type: si - al thickness: 11k ? 2k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: 1.2 x 10 5 a/cm 2 metallization mask layout hm-65262/883 a2 a1 a0 vcc a13 a12 a11 a10 a9 a8 a7 d e gnd w q a6 a5 a4 a3
|
