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preliminary atm hotlink? transceiver CY7C954DX cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 february 8, 2000 features ? second-generation hotlink? technology utopia level i and ii compatible host bus interface three-bit multi-phy address capability built-in three user-selectable start of cell marker/indicators embedded 256-character synchronous fifos built-in atm header error control (hec) automatic transmit-hec insertion & receiver-hec check fifo cell-level flushing of invalid atm cells atm forum, fibre channel, and escon? compliant 8b/10b encoder/decoder 50- to 200-mbaud serial signaling rate internal plls with no external pll components dual differential pecl-compatible serial inputs dual differential pecl-compatible serial outputs compatible with fiber-optic modules and copper cables built-in self-test (bist) for link testing link quality indicator single +5.0v 10% supply 100-pin tqfp 0.35 cmos technology functional description the 200-mbaud CY7C954DX hotlink transceiver is a point- to-point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging be- tween 50 and 200 mbaud. the transmit section accepts par- allel data of selectable width and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable width. figure 1 illustrates typical connections between two independent host systems and cor- responding CY7C954DX parts. as a second-generation hotlink device, the CY7C954DX provides enhanced levels of technology, functionality, and integration over the field proven cy7b923/933 hotlink. the transmit section of the CY7C954DX hotlink has been configured to accept 8-bit data characters on each clock cycle, and store the parallel data into an internal transmit fifo. data is read from the transmit fifo and is encoded using an em- bedded 8b/10b encoder to improve its serial transmission characteristics. these encoded characters are then serialized and output from two pseudo ecl (ecl referenced to +5.0v) compatible differential transmission line drivers at a bit-rate of 10 times the input reference clock. the receive section of the CY7C954DX hotlink accepts a serial bit-stream from one of two pecl-compatible differential line receivers and, using a completely integrated pll clock synchronizer, recovers the timing information necessary for data reconstruction. the recovered bit stream is deserialized and framed into characters, 8b/10b decoded, and checked for transmission errors. recovered decoded characters are re- constructed into 8-bit data characters, written to an internal receive fifo, and presented to the destination host system. for those systems requiring even greater fifo storage capa- bility, external fifos may be directly coupled to the CY7C954DX device through the parallel interface without ad- ditional glue-logic for single phy connections. the ttl parallel i/o interface may be configured as either a fifo (configurable for utopia emulation or for depth expan- sion through external fifos) or as a pipeline register extender. the fifo configurations are optimized for transport of time- independent (asynchronous) 8-bit character-oriented data across a link. a built-in self-test (bist) pattern generator and checker allows for at-speed testing of the high-speed serial data paths in both the transmit and receive sections, and across the interconnecting links. hotlink devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to- point serial links. some applications include interconnecting workstations, backplanes, servers, mass storage, and video transmission equipment. figure 1. hotlink system connections deserializer framer 8b/10b decoder receive fifo transmit fifo 8b/10b encoder serializer CY7C954DX receive data transmit data system host control status deserializer framer 8b/10b decoder receive fifo transmit fifo 8b/10b encoder serializer CY7C954DX receive data transmit data system host control status serial link serial link hotlink is a registered trademark of cypress semiconductor corporation. escon is a registered trademark of international business machines.
CY7C954DX preliminary 2 CY7C954DX transceiver logic block diagram ina inb outb outa routing matrix a/b* serial shifter bit clock bist lfsr 8b/10b encoder pipeline register mux elasticity buffer transmit fifo input register txdata transmit control transmit pll clock multiplier txclk refclk output register flags mode output register receive clock/data recovery bit clock deserializer framer clock divider bist lfsr 8b/10b decoder hec check receive fifo receive control rxdata rxclk flags 3 rx status tx status cardet signal validation 11 tx status txempty* txclav txfull* 3 rxstatus lfi* rxempty* rxclav rxfull* 4 11 mode control control 6 14 control rxaddr[2:0] txen* rxen* txrst* rxrst* rfen txbisten* rxbisten* mode rangesel spdsel receive formatter transmit formatter state machine state machine rxmode[1:0] cursetb curseta loopback dlb[1:0] looptx control loopback control reset* extfifo test* addrsel[2:0] txaddr[2:0] cell discard policy pipeline register hec generate
CY7C954DX preliminary 3 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +6.5v dc voltage applied to outputs in high-z state ......................................... ? 0.5v to v dd +0.5v output current into ttl outputs (low) ...................... 30 ma dc input voltage ..................................... ? 0.5v to v dd +0.5v static discharge voltage ......................................... > 2001 v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma pin configuration tqfp top view 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 spdsel rangesel rfen txfull* rxaddr[2] txclav rxsc/d* txclk vss vss vdd rxdata[1] txsoc rxrst* rxen* rxdata[0] txempty* vss txsvs vdd txaddr[1] rxdata[2] reset* vss vdd 58 57 56 55 54 53 52 51 test* a/b* lfi* dlb[1] dlb[0] looptx vss rxclk rxfull* vss vdd vdd txen* txaddr[2] txbisten* vss txrst* rxclav txsc/d* rxempty* txdata[0] rxsoc rxmode[1] rxmode[0] refclk 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 cardet vssa vdda curseta vdda vdda outa ? ina ? vssa vdda vdda vssa vssa vssa ina+ inb+ inb ? outb ? outb+ vdda vssa cursetb rxbisten* vssa outa+ 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 addrsel[0] extfifo rxdata[3] rxdata[4] txaddr[0] rxdata[5] txdata[5] rxdata[6] rxdata[7] vss vss txdata[3] rxaddr[0] txdata[6] txdata[7] txdata[4] vdd txdata[2] rxaddr[1] txdata[1] rxrvs addrsel[2] addrsel[1] vss vss 33 32 31 30 29 28 27 26 CY7C954DX operating range range ambient temperature v cc commercial 0 c to +70 c 5.0v 10%
CY7C954DX preliminary 4 pin descriptions CY7C954DX hotlink transceiver pin # name i/o characteristics signal description transmit path signals 44, 42, 40, 36, 34, 32, 30, 22 txdata[7:0] ttl input, sampled on txclk , internal pull-up parallel transmit data input. these inputs contain data that is written to the transmitter fifo when txaddr[2:0] matches addrsel[2:0] and transmitter input is selected by txen*. 56 txsvs ttl input, sampled on txclk , internal pull-up transmit send violation symbol input. this input is interpreted along with txsoc and txsc/d* (see ta ble 1 for details). 58 txsoc ttl input, sampled on txclk , internal pull-up transmit start of cell input. this input is used as a message frame delimiter to indicate the beginning of a data packet. it is interpreted along with txsvs and txsc/d* (see table 1 for details). 20 txsc/d* ttl input, sampled on txclk , internal pull-up transmit special character or data select input. this input is interpreted along with txsvs and txsoc (see table 1 for de- tails). 18 txen* ttl input, sampled on txclk , internal pull-up transmit enable input. data enable for the txdata bus write operations. active low when config- ured for utopia timing, active high when configured for cascade timing. 9, 54, 46 txaddr[2:0] ttl input, sampled on txclk , internal pull-up on transmit address select input. this is the three bit transmit port address that is matched to addrsel[2:0] to enable data transfer from the transmitting system. 68 txclk ttl clock input, internal pull-up transmit fifo clock. the input clock for the parallel interface when the transmit fifo is enabled. used to sample all transmit fifo related interface signals. 72 txfull* 3-state ttl output, changes following txclk transmit fifo full status flag. active low when configured for utopia timing, active high when configured for cascade timing. when txfull* is first asserted, the transmit fifo can still accept a minimum of four write cycles without loss of data. fifo flags are updated one txclk cycle after an address match condition exists. 70 txclav 3-state ttl output, changes following txclk transmit fifo cell available status flag. active low. txclav is asserted low when the transmit fifo has sufficient space to insert one or more 53-byte atm cells. txclav is forced to the high-z state only during a ? full-chip ? reset (i.e., while reset* is low) or on the cycle after an ? unmatch ? in txaddr[2:0]. (used for polling fifo status.) fifo flags are updated one txclk cycle after an address match condition exists. 60 txempty* 3-state ttl output, changes following txclk transmit fifo empty status flag. active low when configured for utopia timing, active high when configured for cascade timing. txempty* is asserted either when no data has been loaded into the transmit fifo, or when the transmit fifo has been emptied by either a transmit fifo reset or by the normal transmission of the fifo contents. when txbisten* is asserted low, txempty* becomes the transmit bist- loop counter indicator. in this mode txempty* is asserted for one txclk period at the end of each transmitted bist sequence. fifo flags are updated one txclk cycle after an address match condition exists.
CY7C954DX preliminary 5 16 txrst* ttl input, internal pull-up, sampled on txclk , internal pull-up transmit fifo reset. when txrst* is sampled asserted (low) for eight or more txclk cycles, a reset operation is started on the transmit fifo. 7 txbisten* ttl input, asynchronous, internal pull-up transmitter bist enable. when txbisten* is low, the transmitter generates a 511-character repeat- ing sequence, that can be used to validate link integrity. the transmitter returns to normal operation when txbisten* is high. all transmit fifo read oper- ations are suspended when bist is active. receive path signals 41, 43, 45, 47, 48, 53, 59, 61 rxdata[7:0] 3-state ttl output, changes following rxclk , parallel data output. these outputs change following the rising edge of rxclk, when enabled to output data (the device rxaddr[2:0] address matches addrsel[2:0] and selected by rxen*). 29 rxrvs 3-state ttl output, changes following rxclk , internal pull-up received violation symbol indicator. in receive mode (11), this output is the indicator that data has been received continuing errors, and is decoded in conjunction with rxsc/d* and rxsoc, per ta b l e 4 , to indicate the presence of specific special character codes in the received data stream. this output is unused for the other receive modes, except that rxrvs is used to report character mismatches when rxbisten* is low this output changes following the rising edge of rxclk, when enabled to output data (the device rxaddr[2:0] address matches addrsel[2:0] and selected by rxen*). 23 rxsoc 3-state ttl output, changes following rxclk receive start of cell. this output is one of the indicators for the start of a cell and is decoded in conjunction with rxsc/d* and rxrvs, per table 4 , to indicate the presence of specific special character codes in the received data stream. this output changes following the rising edge of rxclk, when enabled to output data (the device rxaddr[2:0] address matches addrsel[2:0] and selected by rxen*). 65 rxsc/d* 3-state ttl output, changes following rxclk received special character or data indicator. this signal is use to differentiate between special characters and data bytes. it is also decoded in conjunction with rxsoc and rxrvs, per ta ble 4 , to indicate the presence of specific special character codes in the received data stream. this output changes following the rising edge of rxclk, when enabled to output data (the device rxaddr[2:0] address matches addrsel[2:0] and selected by rxen*). 69 rxen* ttl input, sampled on rxclk , internal pull-up receive enable. data enable for the rxdata bus write and read operations. active low when configured for utopia timing, active high when configured for cascade tim- ing as determined by the extfifo pin. 71,31, 33 rxaddr[2:0] ttl input, sampled on rxclk receive address input. this is the three-bit receive port address that is matched to addrsel[2:0] to enable data transfer to the receiving system. 8 rxclk ttl output clock, internal pull-up receive clock. this clock is the receive interface input clock and is used to control receive fifo read, reset, and serial register access operations. pin descriptions (continued) CY7C954DX hotlink transceiver pin # name i/o characteristics signal description
CY7C954DX preliminary 6 10 rxfull* 3-state ttl output, changes following rxclk receive fifo full flag. active low when configured for utopia timing (extfifo is low), active high when configured for cascade timing (extfifo is high). in receive mode (11), when the receive fifo is addressed, rxfull* is asserted one rxclk cycle after the address match, when the receive fifo has room for four or fewer writes. if the rxclk input is not continuous, or if the fifo is accessed at a rate slower than data is being received, rxfull* may indicate loss of data. this output is not used in receive modes (00, 01, 10). 19 rxclav 3-state ttl output, changes following rxclk receive fifo cell available flag. this signal is asserted (low) when the receive fifo contains at least one atm cell ready to be read. it is asserted one rxclk cycle after the device rxaddr[2:0] address matches addrsel[2:0] and selected by rxen*. rxclav is forced to the high-z state only during a ? full-chip ? reset (i.e., while reset* is low) or on the cycle after an ? unmatch ? in rxaddr[2:0]. (used for polling fifo status.) 21 rxempty* 3-state ttl output, changes following rxclk receive fifo empty flag. active low when configured for utopia timing (extfifo is low), active high when configured for cascade timing (extfifo is high). in receive mode (11), when the receive fifo is enabled, rxempty* is as- serted one rxclk cycle after the address match, when no data remains in the receive fifo. any read operation occurring when rxempty* is asserted results in no change in the fifo status, and the data from the last valid read remains on the rxdata bus. this output functions the same rxclav in receive modes (00, 01, 10). 67 rxrst* ttl input, sampled on rxclk , internal pull-up receive fifo reset. when the receive fifo is addressed and rxrst* is sampled while asserted (low) for eight or more rxclk cycles, along with the deassertion of rxen* and an address match condition existing, a receive fifo reset is initiated. 73 rfen ttl input, asynchronous, internal pull-up reframe enable. used to control when the framer is allowed to adjust the character boundaries based on detection of one or more k28.5 characters in the data stream. when high, the framer is allowed to adjust the character boundaries relative to re- ceived serial data stream. when low, the boundary is fixed. 77 rxbisten* ttl input, asynchronous, internal pull-up receiver bist enable. when active, the receiver is configured to perform a character-for-character match of the incoming data stream with a 511-character bist sequence. the result of character mismatches are indicated on rxrvs. completion of each 511-character bist loop is accompanied by an assertion pulse on the rxfull* flag. control signals 6 looptx ttl asynchronous input, internal pull-down serial-in to serial-out loop select. this input controls the loop-through function in which the serial data is re- covered by the clock/data recovery pll and then is retransmitted using the transmitter pll as the bit-rate reference. it selects between the output of the transmitter fifo and the output of the elasticity buffer as the input to the transmit encoder. when low, the transmit fifo is the source of data for transmission. when high, the elasticity buffer is the source of data for trans- mission. pin descriptions (continued) CY7C954DX hotlink transceiver pin # name i/o characteristics signal description
CY7C954DX preliminary 7 12 refclk ttl input clock reference clock. this clock input is used as the timing reference for the transmit and receive plls. see table 3 for the relationships between refclk, spdsel, and rangesel. 75 spdsel static control input ttl levels normally wired high or low speed select. used to select one of two operating data rates for the device. when the oper- ating bit rate is between 100 and 200 mbaud, spdsel must be high. when the operating bit rate is between 50 and 100 mbaud, spdsel must be low (see ta ble 3 ). 74 rangesel static control input ttl levels normally wired high or low range select. selects the proper prescaler for the refclk input. see table 3 for the various relationships between refclk, spdsel, and rangesel. 49 extfifo static control input ttl levels normally wired high or low external fifo interface levels and timing select. extfifo modifies the active level of the rxen* and txen* inputs and the timing of the transmitter and receiver data buses. while this compromises the utopia multi-phy compatibility, it adds additional fifo capability for single phy systems. in utopia interface mode (extfifo is low), txen* is assumed to be driven as a pipeline register and rxen* is assumed to be driven by a controller for a pipeline register. in this mode the active transmit data information is within the same clock as the clock edge that ? enables ? the data bus. in cascade interface mode (extfifo is high), txen is assumed to be driven by the empty flag of an attached cy7c42x5 fifo, and rxen is assumed to be driven by the almost full flag of an attached cy7c42x5 fifo. in this mode the active transmit data information is in the clock following the clock edge that ? enables ? the data bus. receive data information is always in the clock cycle following the rxen*. extfifo also modifies the output state of the receive and transmit fifo flags. when configured in utopia mode (extfifo is low), all of the fifo flags are active low. when configured in cascade mode (extfifo is high), the full and empty fifo flags are active high (the txclav and rxclav flags are always active low). 28,27, 50 addrsel[2:0] static control input ttl levels normally wired high or low utopia chip address input. these inputs select one of 7 chip addresses to which the txaddr[2:0] and rxaddr[2:0] are compared. a match of these vectors and the appropriate txen* or rxen* results in an address match and selection operation. 24,25 rxmode[1:0] static control input ttl levels normally wired high or low receive discard policy select. these inputs select between the four received-cell discard modes in the re- ceiver. see table 5 . 52 reset* ttl asynchronous input global logic reset. this input is pulsed low for one or more refclk periods to reset the internal logic. 1 test* ttl asynchronous input. normally wired high factory test mode select. used to force the part into a diagnostic test mode used for factory ate test. this pin is tied high during normal operation. pin descriptions (continued) CY7C954DX hotlink transceiver pin # name i/o characteristics signal description
CY7C954DX preliminary 8 analog i/o and control 89, 90, 81, 82 outa outb pecl differential output differential serial data outputs. these pecl outputs are capable of driving terminated transmission lines or commercial fiber-optic transmitter modules. an unused output pair may be powered down by leaving the outputs uncon- nected and strapping the associated cursetx pin to v dd . 97 curseta analog current-set resistor input for outa . a precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the outa differential driver. 78 cursetb analog input current-set resistor input for outb . a precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the outb differential driver. 94, 93, 86, 85 ina inb pecl compatible differential input differential serial data inputs. these inputs accept the serial data stream for deserialization and decoding. only one serial stream at a time may be fed to the receiver pll to extract the data content. this stream is selected using the a/b* input. these inputs may also be routed to the outb serial outputs using the dlb[1:0] inputs. 2 a/b* ttl input, asynchronous, internal pull-up receive data input selector. determines which internal or external serial bit-stream is passed to the receiv- er clock and data recovery circuit. see table 2 for details. 4, 5 dlb[1:0] ttl input, asynchronous, internal pull-down loop back select inputs. selects connections between serial inputs and outputs. controls diagnostic loop-back and serial loop-through functions. see table 2 for details. 100 cardet pecl input, asynchronous carrier detect input. used to allow an external device to signify a valid signal is being presented to the high-speed pecl input buffers, as is typical on an optical module. when cardet is deasserted low, the lfi * indicator asserts low signifying a link fault. this input can be tied high for copper media applications. 3 lfi* ttl output, changes following rxclk link fault indication output. active low. lfi* changes synchronous with rxclk. this output is driven low when the serial link currently selected by a/b* is not suitable for data recovery. this could be because 1. serial data amplitude is below acceptable levels 2. input transition density is not sufficient for pll clock recovery 3. input data stream is outside an acceptable frequency range of operation 4. cardet is low power 80, 87, 88, 95, 96, 98 v dda power for pecl i/o signals and internal analog circuits. 76, 79, 83, 84, 91, 92, 99 v ssa ground for pecl i/o signals and internal analog circuits. 4, 14, 17, 35, 55, 62, 64 v dd power for cmos i/o signals and internal logic circuits. pin descriptions (continued) CY7C954DX hotlink transceiver pin # name i/o characteristics signal description
CY7C954DX preliminary 9 CY7C954DX hotlink operation overview the CY7C954DX is designed to move parallel data across both short and long distances with minimal overhead or host system intervention. this is accomplished by converting the parallel characters into a serial bit-stream, transmitting these serial bits at high speed, and converting the received serial bits back into the original parallel data format. the CY7C954DX offers a large feature set, allowing it to be used in a wide range of host systems. some of the configura- tion options are: atm cell size and header rules generate/check user-definable data packet or frame structure two-octave data-rate range asynchronous (fifoed) data interface 8b/10b encoded serial data with or without hec check/generate selectable cell discard policy based on 53-byte cell size selectable cell discard policy based on hec errors embedded 256-byte (4-cell) fifo data storage multi-phy capability (three-bit address match) point-to-point, or point-to-multipoint data-transport this flexibility allows the cy7c 954dx to meet the data trans- port needs of almost any system. transmit data path transmit data interface/transmit data fifo the host interface functions in a manner similar to that of a synchronous fifo clocked by txclk. in this configuration an internal 256 character transmit fifo is enabled. it allows the host interface to be written at any rate from dc to 50 mhz. the interface operations support two interface timing models: utopia and cascade. the utopia timing model is designed to match the active levels, bus timing, and signal sequencing called out in the atm forum utopia specification. the cas- cade timing model is designed to match a host bus that resem- bles a synchronous fifo. these timing models allow the CY7C954DX to directly couple to host systems, registers, state machines, fifos, etc. with minimal and in many cases no external glue logic. encoder data from the host interface or transmit fifo is next passed to an encoder block. the CY7C954DX contains an internal 8b/10b encoder that is used to improve the serial transport characteristics of the data. serializer/line driver the data from the encoder is passed to a serializer. this se- rializer operates at either 2.5, 5, or 10 times the rate of the refclk input. the serialized data is output from two pecl- compatible differential line drivers configured to drive trans- mission lines or optical modules. receive data path line receiver/deserializer/framer serial data is received at one of two pecl-compatible differ- ential line receivers. the data is passed to both a clock and data recovery pll (phase locked loop) and to a deserializ- er that converts serial data into parallel characters. the fram- er adjusts the boundaries of these characters to match those of the original transmitted characters. decoder the parallel characters are passed through a 10b/8b decoder and returned to their original form. receive data interface/receive data fifo data from the decoder is passed either to a receive fifo or is passed directly to the output register. the output register is configured for operation with 8-bit data. when configured for an asynchronous buffered (fifoed) in- terface, the data is passed through a 256-character receive fifo that allows data to be read at any rate from dc to 50 mhz. the receive interface is also configurable for both utopia and cascade timing models. CY7C954DX hotlink transceiver block diagram description transmit input/register the transmit input register, shown in figure 2 , captures the data to be processed by the hotlink transmitter, and allows the input timing to be made compatible with asynchronous or synchronous host system buses. these buses can take the form of utopia compliant interfaces, external fifos, state machines, or other control structures. data present on the txdata[7:0] and txsc/d* inputs are captured at the rising edge of the selected sample clock. the logical sense of the enable and fifo flag signals depends on the intended inter- face convention and is set by the extfifo pin. asynchronous interface clocking controls the writing of host bus data into the transmit fifo. in this configuration, all writes to the transmit input register, and associated transfers to the transmit fifo, are controlled by txclk. the remainder of the transmit data path is clocked by refclk or synthesized de- rivatives of refclk. 11, 13, 15, 26, 37, 38, 39, 51, 52, 57, 63, 66 v ss ground for cmos i/o signals and internal logic circuits. pin descriptions (continued) CY7C954DX hotlink transceiver pin # name i/o characteristics signal description
CY7C954DX preliminary 10 utopia timing model the utopia timing model allows multiple CY7C954DX trans- mitters to be addressed and accessed from a common host bus, using the protocols defined in the atm forum utopia interface standards. it is enabled by setting extfifo low. in utopia timing, the txempty* and txfull* outputs and txen* input are all active low signals. if the CY7C954DX is addressed by txaddr[2:0] matching addrsel[2:0], it be- comes ? selected ? when txen* is asserted low. following se- lection, data is written into the transmit fifo on every clock cycle where txen* remains low. cascade timing model the cascade timing model is a variation of the utopia timing model. the multi-phy polling schemes used by utopia-ii do not work in the cascade mode. this mode is intended for point-to-point (single phy) use only. here the txempty and txfull* outputs, and txen input are all active high signals. cascade timing makes use of the same address and selection sequences as utopia timing, but write data accesses use a delayed write. this delayed write is necessary to allow direct coupling to external fifos, or to state machines that initiate a write operation one clock cycle before the data is available on the bus. cascade timing is enabled by setting extfifo high. when used for fifo depth expansion, cascade timing allows the size of the internal transmit fifo to be expanded to an almost unlimited depth. it allows a cy7c42x5 series synchro- nous fifo to be attached to the transmit interface without any extra logic, as shown in figure 3 . transmit fifo the transmit fifo is used to buffer data captured in the input register for later processing and transmission. this fifo is sized to hold 256 14-bit characters. when the transmit fifo is enabled, and a transmit fifo write is enabled (the device is selected and txen* is sampled asserted) data is captured in the transmit input register and stored into the transmit fifo. all transmit fifo write operations are clocked by txclk. the transmit fifo presents full, half-full, and empty fifo flags. these flags are provided synchronous to txclk to al- low operation with a moore-type external controlling state ma- chine. when configured for cascade timing, the timing and active levels of these signals are also designed to support di- rect expansion to cypress cy7c42x5 synchronous fifos. the transmit fifo can be clocked at any rate from dc to 50 mhz. this gives the transmit fifo a maximum bandwidth of 50 million characters per second. since the serial output speed is limited to 20 million characters per second at its fast- est operating rate, there is ample time to service multiple hotlinks with a single controller. the read port of the transmit fifo is connected to a logic block that performs data formatting and validation. all data read operations from the transmit fifo are controlled by a transmit control state machine that operates synchronous to refclk. transmit formatter and validation the transmit formatter and validation logic controls the timing for the transfer of data from the transmit input register, trans- mit fifo, or elasticity buffer. transmit data formatting the CY7C954DX supports a number of protocol enhance- ments over a raw physical-layer device. these enhancements are made possible in part through the use of the transmit and receive fifos. these fifos allow the CY7C954DX to man- age the data stream to a much greater extent than was possi- ble before. in addition to the standard 8b/10b encoding used to improve serial data transmission, the CY7C954DX also sup- ports: marking of packet or cell boundaries using txsoc calculation and optional insertion of header error check byte (hec). both of these capabilities are supported for 8-bit encoded characters, and use of the txsoc bit. this bit is interpreted, along with txsc/d* and txsvs to trigger hec operations and create three unique start of cell markers. all three bits determine how the data associated with them is processed for transmission. these operations are listed in table 1 . the entries in ta ble 1 where txsoc is low generate the same characters in the serial data stream as a standard transmit input register txen* txdata[7:0] 8 txclk refclk transmit fifo figure 2. transmit input register 14 txaddr[2:0] control 3 address match addrsel[2:0] figure 3. external fifo depth expansion of the CY7C954DX transmit data path ff* wen* d txclk ff* wen* d wclk ef* ren* q rclk txen txfull txdata txclk txsc/d* cy7c42x5 fifo CY7C954DX txsoc txsvs extfifo ? 1 ? 11 11
CY7C954DX preliminary 11 cy7b923 hotlink transmitter, which uses the ansi standard 8b/10b character set. the data, command, and exception character encoding are listed in the data and special charac- ter code tables ( tables 8 and 9 ) found near the end of this data sheet. when the txsoc bit (as read from the transmit fifo) is high, an extra character is inserted into the data stream. this extra character is always a special character code (see ta b l e 9 ) that is used to inform the remote receiver that the immedi- ately following character should be interpreted differently from its normal meaning. the associated character present on txdata[x:0] is always encoded as a data character. the 100b (txsoc = 1, txsc/d* = 0, and txsvs = 0), 110b and 111b combinations are used as markers for the start of a cell, frame, or packet of data being sent across the interface. when a character is read from the transmit fifo with these bits set, a c8.0, c9.0, or c10.0 special character code is sent to the encoder prior to sending the associated data character. the 101b encoding has the same function as the 001b and 011b normal data modes. it instructs the encoder to discard the associated data character and to replace it with a c0.7 exception character. the 110b encoding might be used for a context-based start of cell marker (soc with one of three modifiers), or it could be used to expand the command space beyond that available with the default 8b/10b code (sc/d* with a modifier). the 8b/10b code normally supports a data space of 256 data characters, and a command (non-data) space of twelve command charac- ters (c0.0-c11.0 in ta ble 9 ). for those data links where these few commands are not sufficient, the 110b encoding can be used to mark the associated data as an extended command. this expands the command space to 256 commands (in addi- tion to some of the present twelve). when a character is read from the transmit fifo with these bits set, a c9.0 special character code is sent to the encoder prior to sending the data character. note: since this character is interpreted as a ? start of cell ? marker, care should be taken in its placement. if the receiver is in receive mode (00, 01,10) placements that create ? illegal at m c e l l s ? will be discarded. the 111b encoding might be used for a different context-based start of cell marker (soc with one of three modifiers). when a character is read from the transmit fifo with these bits set, a c10.0 special character is sent to the encoder prior to sending the associated data character. header error check generation and insertion if hec generation is enabled (although not really a ? receive mode ? , this function is enabled by 00b on the rxmode[1:0] pins; see ta b l e 5 ) the transmitter will overwrite the 5th byte of each atm cell with the appropriate internally generated hec code. this code is a crc of the first four bytes in the atm header (the first four bytes after the transmit start of cell marker) as is defined by the atm forum spec i413. encoder block the encoder logic block performs two primary functions: en- coding the data for serial transmission and generating bist (built-in self test) patterns to allow at-speed link and device testing. bist lfsr the encoder logic block operates on data stored in a register. this register accepts information directly from the transmit fifo, the transmit input register, the 10/8 byte-packer, or from the transmit control state machine when it inserts spe- cial characters into the data stream. this same register is converted into a linear-feedback shift- register (lfsr) when the built-in self-test (bist) pattern generator is enabled (txbisten* is low). when enabled, this lfsr generates a 511-character sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable but pseudo- random sequence that can be matched to an identical lfsr in the receiver. the specific patterns generated are described in detail in the cypress application note ? hotlink built-in self-test. ? the se- quence generated by the CY7C954DX is identical to that in the cy7b923, cy7c924, and cy7b929, allowing interoperable systems to be built when used at compatible serial signaling rates and appropriate atm cell handling logic, since none of these are atm aware. encoder the data passed through the transmit fifo and formatter, or as received directly from the transmit input register, is seldom in a form suitable for transmission across a serial link. the characters must usually be processed or transformed to guar- antee: a minimum transition density (to allow the serial receiver pll to extract a clock from the data stream), a dc-balance in the signaling (to prevent baseline wander), run-length limits in the serial data (to limit the bandwidth of the link), and some way to allow the remote receiver to determine the correct character boundaries (framing). the CY7C954DX contains an integrated 8b/10b encoder that accepts 8-bit data characters and converts these into 10-bit transmission characters that have been optimized for transport on serial communications links. the operation of the 8b/10b encoding algorithm is described in detail later in this table 1. transmit data formatting txsoc txsc/d* txsvs data format operation 0 0 0 normal data encode 0 0 1 replace character with c0.7 exception 0 1 0 normal command encode 0 1 1 replace character with c0.7 exception 1 0 0 send start of cell marker type i (c8.0) + data character 1 0 1 replace character with c0.7 exception 1 1 0 send start of cell marker type ii (c9.0) + data character 1 1 1 send start of cell marker type iii (c10.0) + data character
CY7C954DX preliminary 12 datasheet, and the complete encoding tables are listed in ta - bles 8 and 9 . the transmit data characters (as passed through the transmit fifo and formatter) are converted to either a 10-bit data symbol or a 10-bit special character, depending upon the state of the txsc/d* input. if txsc/d* is high, the data inputs represent a special character code and are encoded using the special char- acter encoding rules in ta b l e 9 . if txsc/d* is low, the data inputs are encoded using the data character encoding in ta ble 8 . if this bit (txsvs) is high, the respective character is re- placed with an svs (c0.7) character. this can be used to check error handling system-logic in the receiver controller or for proprietary applications. this will cause the entire atm cell to be discarded, except in receive mode (11), which will pass the error character to down stream logic. the 8b/10b encoder is standards compliant with ansi/ncits asc x3.230-1994 (fibre channel), ieee 802.3z (gigabit ethernet), the ibm escon and ficon channels, and atm forum standards for data transport. transmit shifter the transmit shifter accepts 10-bit parallel data from the en- coder block once each character time, and shifts it out the serial interface output buffers using a pll-multiplied bit-clock. this bit-clock runs at 2.5, 5, or 10 times the refclk rate as selected by rangesel and spdsel (see table 3 ). timing for the parallel transfer is controlled by the counter and dividers in the clock multiplier pll and is not affected by signal levels or timing at the input pins. bits in each character are shifted out lsb first, as required by ansi and ieee standards for 8b/10b coded serial data streams. routing matrix the routing matrix is a set of precision multiplexors that allow various combinations of transmit shifter, buffered ina or inb serial line receiver inputs, or a reclocked serial line re- ceiver input to be transmitted from the outb serial data out- puts. the signal routing for the transmit serial outputs is con- trolled primarily by the dlb[1:0] inputs as listed in ta b l e 2 . serial line drivers the serial interface pecl-compatible output drivers (ecl ref- erenced to +5v) are the transmission line drivers for the serial media. outa receives its data direct from the transmit shifter, while outb receives its data from the routing matrix. these two outputs (outa and outb) are capable of direct con- nection to +5v optical modules, and can also directly drive dc- or ac-coupled transmission lines. the pecl-compatible output drivers can be viewed as pro- grammable current sources. therefore, the output voltage am- plitude (v odif ) is proportional to the programmed current am- plitude and the total impedance that the output driver sees. the output current amplitude is programmed by the curseta/b resistor. v odif can be approximated by the fol- lowing equation: v odif = 180 * r load /r curset (v) where r load is the load resistance that the output driver sees; and r curset is the curseta/b resistor value. unused differential output drivers should be left open, and can reduce their power dissipation by connecting their respective cursetx input to v dd . transmit pll clock multiplier the transmit pll clock multiplier accepts an external clock at the refclk input, and multiples that clock by 2.5, 5, or 10 to generate a bit-rate clock for use by the transmit shifter. it also provides a character-rate clock used by the transmit controller state machine. the clock multiplier pll can accept a refclk input between 10 mhz and 40 mhz, however, this clock range is limited by the operation mode of the CY7C954DX as selected by the spdsel and rangesel inputs. the operating serial signal- ling rate and allowable range of refclk frequencies is listed in ta b l e 3 . transmit control state machine the transmit control state machine responds to multiple in- puts to control the data stream passed to the encoder. it oper- ates in response to: the state of the looptx inputs the presence of data in the transmit fifo table 2. transmit data routing matrix dlb[1] dlb[0] data connections 00 01 10 11 ina inb outb outa transmit shifter receive pll a/b* ina inb outb outa transmit shifter receive pll a/b* ina inb outb outa transmit shifter receive pll a/b* ina inb outb outa transmit shifter receive pll a/b*
CY7C954DX preliminary 13 the contents of the transmit fifo the contents of the elasticity buffer the state of the transmitter bist enable (txbisten*) these signals are used by the transmit control state machine to control the data formatter, read access to the transmit fifo and elasticity buffer, the byte-packer, and bist. they deter- mine the content of the characters passed to the encoder and transmit shifter. elasticity buffer a short (8-character) fifo is contained between the receive and transmit paths. this fifo is used to separate the time domains of the received serial data stream and the outbound transmit data stream. this permits retransmission of received data without worry of jitter gain or jitter transfer. this allows error-free transmission of the same data, when configured in daisy-chain or ring configurations, to an unlimited number of destinations. this elasticity buffer is enabled when the looptx input is asserted high. this directs the receiver to place all non-c5.0 (k28.5) characters into the elasticity buffer. looptx also di- rects the transmit control state machine to read data from the elasticity buffer instead of from the transmit fifo. while retransmitting data from the elasticity buffer, the trans- mit fifo is available for preloading of data to be transmitted. once looptx is deasserted (low), normal data transmis- sion from the transmit fifo resumes. serial line receivers two differential line receivers, ina and inb, are available for accepting serial data streams, with the active input selected using the a/b* input. the dlb[1:0] inputs allow the transmit serializer output to be selected as a third input serial stream (dlb[1:0]=01 is the di- agnostic loopback function). the serial line receiver inputs are all differential, and will accommodate wire interconnect with filtering losses or transmission line attenuation greater than 9db (v dif > 200 mv, or 400 mv peak-to-peak differential) or can be directly connected to +5v fiber-optic interface modules with appropriate terminations (any ecl logic family, not limited to ecl 100k). the common-mode tolerance of these line re- ceivers accommodates a wide range of signal termination volt- ages. input levels less than about 300 mv will cause lfi* to be asserted low, indicating a line fault, but the input should still decode data correctly. as can be seen in ta b l e 2 , these inputs are configured to allow single-pin control for most applications. for those systems re- quiring selection of only ina or inb, the dlb[1:0] signals can be tied low, and the a/b selection can be performed us- ing only a/b*. for those systems requiring only a single input and a local loopback, the a/b* can be tied high or low, dlb[1] signal can be tied low and dlb[0] can be used for loopback control. the level-restored (10) and reclocked (11) settings make use of one of the transmit data outputs. when configured for level- restored or reclocked data, the selected input is retransmitted on outb. the level-restored connection simply buffers the input signal allowing a ? bus-like ? connection to be constructed without concern for multi-drop pecl signal layout issues. the reclocked connection buffers a pll-filtered copy of the selected input data stream. this removes most of the high- frequency jitter that accumulates on a signal when sent over long transmission lines. unlike data retransmitted from the elasticity buffer, the output data stream is clocked by a recov- ered clock, not by a derivative of the local reflck input. this allows a data source to provide data to multiple recipients, but can suffer from jitter peaking when communicated through several plls. the reclocked connection may be required when sending non-8b/10b coded data streams, or data streams that cannot tolerate the data forwarding policies of the elasticity buffer. this reclocked output stream may also be beneficial in sys- tems requiring very low latency. the internal data delays for a reclocked serial stream are a small number of bits, while data sent through the elasticity buffer incurs a delay of a small num- ber of characters. signal detect the selected line receiver (that routed to the clock and data recovery pll) is simultaneously monitored for: analog amplitude (>400 mv pk-pk) on selected input, transition density, received data stream outside normal frequency range (400 ppm), and carrier detected. all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on the lfi* (link fault indicator) output, which changes synchro- nous to rxclk. while link status is monitored internally at all times, it is necessary to have transitions on rxclk to allow this signal to change externally. clock/data recovery the extraction of a bit-rate clock and recovery of data bits from the received serial stream is performed within the clock/data recovery (cdr) block. the clock extraction function is per- formed by a high-performance embedded phase-locked loop (pll) that tracks the frequency of the incoming bit stream and aligns the phase of its internal bit-rate clock to the transitions in the serial data stream. the cdr makes use of the clock present at the refclk input. it is used to ensure that the vco (within the cdr) is operating at the correct frequency (rather than some harmonic of the bit rate), to improve pll acquisition time, and to limit unlocked frequency excursions of the cdr vco when no data is present at the serial inputs. regardless of the type of signal present, the cdr w ill attempt to recover a data stream from it. if the frequency of the recov- ered data stream is outside the limits for the range controls, the cdr pll will track refclk instead of the data stream. when the frequency of the selected data stream returns to a table 3. speed select and range select settings spdsel rangesel serial data rate (mbaud) refclk frequency (mhz) low low 50 ? 100 10 ? 20 low high 50 ? 100 20 ? 40 high low 100 ? 200 10 ? 20 high high 100 ? 200 20 ? 40
CY7C954DX preliminary 14 valid frequency, the cdr pll is allowed to track the received data stream. the frequency of refclk is required to be within 400 ppm of the frequency of the clock that drives the refclk signal at the remote transmitter to ensure a lock to the incoming data stream. for systems using multiple or redundant connections, the lfi* output can be used to select an alternate data stream. when an lfi* indication is detected, external logic can toggle selec- tion of the ina and inb inputs through the a/b* input. when a port switch takes place, it is necessary for the pll to re- acquire the new serial stream and frame to the incoming char- acters. clock divider this block contains the clock division logic used to transfer the data from the deserializer/framer to the decoder once every character (once every ten or twelve bits) clock. this counter is free running and generates outputs at the bit-rate divided by 10. deserializer/framer the cdr circuit extracts bits from the serial data stream and clocks these bits into the shifter/framer at the bit-clock rate. when enabled, the framer examines the data stream looking for c5.0 (k28.5) characters at all possible bit positions. the location of this character in the data stream is used to deter- mine the character boundaries of all following characters. the framer operates in one of three different modes, as select- ed by the rfen input. when rfen is first asserted (high), the framer is allowed to reset the internal character boundaries on any detected c5.0 character. once rfen has been high for greater than approximately 2000 character clock cycles, the multi-byte framer is enabled. this requires two c5.0 characters, within a span of five char- acters, with both c5.0 characters located on identical 10-bit character boundary locations, before the framer is allowed to reset the internal character boundary. if rfen is low, the framer is disabled and no changes are made to character boundaries. the framer in the CY7C954DX operates by shifting the internal character position to align with the character clock. this en- sures that the recovered clock will not contain any significant phase changes/hops during normal operation or framing, and allows the recovered clock to be replicated and distributed to other circuits using pll-based logic elements. decoder block the decoder logic block performs two primary functions: de- coding the received transmission characters back into data and special character codes, and comparing generated bist patterns with received characters to permit at-speed link and device testing. 10b/8b decoder the framed parallel output of the deserializer is passed to the 10b/8b decoder where, if the decoder is enabled, it is trans- formed from a 10-bit transmission character back to the origi- nal data and special character codes. this block uses the standard decoder patterns in tables 8 and 9 of this data sheet. data patterns are indicated by a low on rxsc/d*, and special character codes are indicated by a high. invalid patterns or dispar- ity errors are signaled as errors by a high on rxrvs, and by spe- cific special character codes. bist lfsr the output register of the decoder block is normally used to accumulate received characters for delivery to the receive formatter block. when configured for bist mode (rxbisten* is low), this register becomes a signature pat- tern generator and checker by logically converting to a linear- feedback shift-register (lfsr). when enabled, this lfsr generates a 511-character sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable but pseudo-random se- quence that can be matched to an identical lfsr in the trans- mitter. when synchronized with the received data stream, it checks each character in the decoder with each character generated by the lfsr and indicates compare errors at the rxrvs output of the receive output register. the lfsr is initialized by the bist hardware to the bist loop start code of d0.0 (d0.0 is sent only once per bist loop). once the start of the bist loop has been detected by the receiver, rxrvs is asserted for pattern mismatches between the re- ceived characters and the internally generated character se- quence. code rule violations or running disparity errors that occur as part of the bist loop do not cause an error indication. rxfull* pulses asserted for one rxclk cycle per bist loop and can be used to check test pattern progress. the specific patterns checked by the receiver are described in detail in the cypress application note ? hotlink built-in self- te st . ? the sequence compared by the CY7C954DX is identical to that in the cy7b933 and cy7b929, allowing interoperable systems to be built when used at compatible serial signaling rates. if a large number of errors are detected, the receive bist state machine aborts the compare operations and resets the lfsr to the d0.0 state to look for the start of the bist sequence again. receive formatter the protocol enhancements of the transmit path are mirrored in the receive path logic. in addition to the standard 10b/8b decoding used for character reception and recovery, the CY7C954DX also supports: marking of packet or cell boundaries using rxsoc, rxsc/d*, and rxrvs ability to accept or discard data based received cell size ability to accept or discard data based received hec calculation the entries in ta ble 4 show how the rxsoc, rxsc/d*, and rxrvs bits are encoded to indicate the reception of specific characters and character combinations. normal data and special character code characters are indicated by rxsoc being low (0). this allows the standard special characters codes to also be reported and output. individual character errors that are not part of one of the sup- ported sequences (i.e., start of cell marker) are marked by the 011b (rxsoc = 0, rxsc/d* = 1, and rxrvs = 1) decode. anytime rxsoc is reported high (1) at least one of the c8.0, c9.0, or c10.0 characters was received as a valid character. if the immediately following character is a valid data character, then the corresponding combination of rxsoc, rxsc/d*,
CY7C954DX preliminary 15 and rxrvs indicate the type of information received. if the immediately following character is a special character code of any type (even a c5.0), then a 101b is posted to indicate an illegal sequence was received. an illegal sequence can be caused by a remote transmitter sending incorrect information, or by the data getting corrupted during transmission. when such an error is detected and the 101b status bits posted, the associated data field is set to the special character code that was received without error (c8.0, c9.0, or c10.0 reported as d8.0, d9.0, or d10.0 along with the 101b status). this information is provided to assist in debug- ging link or protocol faults. note : since an error in an atm cell causes the cell to be dis- carded, except in receive mode (11), these error indications will not be visible. the 100b indication is used to mark the associated data char- acter as the first character of a new cell (soc marker type i), packet, cell, or other data construct used by the system. the data characters and special character codes that follow this marker are written to the receive fifo (depending on the re- ceiver discard policy in effect; see ta ble 5 ). the 110b indication is used to mark the associated data char- acter as the first character of a new cell (soc marker type ii). this marker is treated internally the same as the 100b start- of-cell marker, which allows it to be used to mark the bound- ary of any user-specific information. as a boundary or cell marker, the immediately following data can be a data field, a header, a stream identifier, a transaction number, a packet length indicator, or any of a number of pieces of information connected to a data transfer. the 111b indication is used to mark the associated data char- acter as the first character of a new cell (soc marker type iii). this marker is treated internally the same as the 100b and 110b start-of-cell markers, which allows it to be used to mark the boundary of any user-specific information. the 100b, 110b and 110b, indicators can be used interchange- ably; i.e., they can be used for start of cell markers, extended command markers, general cell routing indicators, or any number of user specified functions. if the transmit fifo is allowed to empty, the transmitter will fill the unused data spaces with c5.0 (k28.5). a receiver set to allow cells longer than 53 bytes will assume that eight consec- utive c5.0 characters are equivalent to a ? virtual soc ? and will release the cell into the fifo for further processing. care should be taken to avoid intra-cell gaps that might result in unintentional termination of the atm cell, because for receive modes that discard cells less than 53 bytes, this ? virtual soc ? could result in cell loss. receive control state machine the receive control state machine responds to multiple input conditions to control the routing and handling of received char- acters. it controls the staging of characters across various reg- isters and the receive fifo. it also interprets all embedded special character codes, and converts the appropriate ones to specific bit combinations in the receive fifo. it controls the various discard policies and error control within the receiver. it operates in response to: the received character stream the room for additional data in the receive fifo the state of the receiver bist enable (rxbisten*) the state of looptx these signals are used by the receive control state machine to control the receive formatter, write access to the receive fifo, write access to the elasticity buffer, the receive output register, and bist. they determine the content of the charac- ters passed to each of these destinations, the receive control state machine always operates synchro- nous to the recovered character clock (bit-clock/10). discard policies the receive control state machine has the ability to selective- ly discard specific characters and cells from the data stream that are determined by the present configuration as being un- necessary. when discarding is enabled, it reduces the host system overhead necessary to keep the receive fifo from overflowing and losing data. the discard policy is configured as part of the operating mode and is set using the rxmode[1:0] inputs. the four discard policies are listed in ta ble 5 . policy 0 (00b) is the most stringent and also most closely ap- proximates the rules for an atm data link. in this mode, every cell is checked for a valid header error check byte (transmitted cells have the hec calculated and inserted into the 5th byte after the start of cell marker) and cell lengths are checked. the receiver will calculate the hec code for each atm header and compare it with the 5th byte of each cell. if the calculated hec code does not match the one that is received, the atm cell will be discarded. long cell truncation is enabled and the hotlink will truncate long cells to 53 bytes, discarding the remainder. the receiver counts incoming bytes upon receipt of a start of cell command code. once 53 bytes of data are received, a new start of cell is assumed. the remainder creates a short cell fragment in the receiver which will be flushed because of hec check, or length. short cell flushing is enabled, so any atm cells that are shorter than 53 bytes will be discarded. the rxfifo will begin c ount- ing incoming bytes upon receipt of the start of cell command table 4. receive data formatting rxsoc rxsc/d* rxrvs data format indication 0 0 0 normal data character 001reserved 0 1 0 normal command character 0 1 1 received c0.7 exception character or other character exception (as listed in ta b l e 9 ) 1 0 0 received start of cell marker type i (c8.0) + data character 1 0 1 received illegal sequence 1 1 0 received start of cell marker type ii (c9.0) + data character 1 1 1 received start of cell marker type iii (c10.0) + data character
CY7C954DX preliminary 16 code. if another start of cell command code is received before 53 bytes of data have been accumulated, the cell will be flushed from the fifo. policy 1 (01b) is similar to policy 0, except that the transmitter does not insert hec, but the receiver checks and discards cells with defective hec. long cells are truncated and short cells are discarded. policy 2 (10b) further relaxes the restrictions on the data for- mat by not generating or checking hec. cells longer than 64 bytes are truncated and short cells are discarded. policy 3 (11b) accepts all data that is received and puts it into the receive fifo, without checking hec or cell byte count. the receive fifo is used to buffer data captured from the selected serial stream for later processing by the host system. this fifo is sized to hold 256 characters. it is written to by the receive control state machine. when data is present in the receive fifo (as indicated by the rxfull*, rxclav (rxhalf* in this mode), and rxempty* receive fifo sta- tus flags), it can be read from the output register by asserting rxaddr[2:0] matching addrsel[2:0] and rxen*. all k28.5 (c5.0) characters are automatically discarded at the receiver fifo. these characters are used for fill when the transmitter fifo goes empty and are not part of any atm protocol structures. if eight contiguous c5.0 (k28.5) characters are received, a ? virtual soc ? is asserted, which might truncate atm cells. to prevent this occurrence, the transmitter fifo should not be allowed to run empty during atm cell transmission. the read port on the receive fifo may be configured for the same two timing models as the transmit interface: utopia and cascade. the utopia timing model has active low rxempty* and rxfull* status flags, and an active low rxen* enable. when configured for cascade operation (not compatible with utopia status polling), these same signals are all active high. either timing model supports connection to various host bus interfaces, state machines, or external fifos for depth expansion (see figure 4 ). the receive fifo presents full, half-full, and empty fifo status flags. these flags are provided synchronous to rxclk to allow operation with a moore-type external controlling state machine. receive output register the receive output register changes in response to the ris- ing edge of rxclk. the receive fifo status flag outputs of this register are placed in a high-z state when the CY7C954DX is not addressed (rxaddr[2:0] doesn ? t match addrsel[2:0]). the rxdata bus output drivers are enabled when the device is addressed (rxaddr[2:0] matches addrsel[2:0]), and rxen* is sampled asserted, initiating a receive fifo read cycle. table 5. receiver discard policies policy# rxmode[1] rxmode[0] policy description 0 0 0 hec-gen=on, (insert calculated hec into 5th byte of transmitted cell.) discard cells with received hec-check=error, truncate cells >53 bytes, discard short cells<53 bytes 1 0 1 hec-gen=off (ignore transmitter hec) discard cells with received hec-check=error, truncate cells >53 bytes, discard short cells<53 bytes 2 1 0 hec-gen=off, no received hec-check, truncate cells >64 bytes, discard short cells<53 bytes 3 1 1 hec-gen=off, no received hec-check, no cell byte counting figure 4. external fifo depth expansion of the CY7C954DX receive data path ef* ren* d rxclk ef* ren* d rclk ff* wen* q wclk rxen rxempty rxdata rxclk rxsc/d* cy7c42x5 fifo CY7C954DX rxsoc rxrvs extfifo ? 1 ? 11 11
CY7C954DX preliminary 17 CY7C954DX dc electrical characteristics over the operating range parameter description test conditions min. max. unit ttl outputs v oht output high voltage i oh = ? 2 ma, v dd = min 2.4 v v olt output low voltage i ol = 8 ma, v dd = min 0.4 v i ost output short circuit current v out = 0v [1] ? 30 ? 80 ma i ozl high-z output leakage current ? 20 20 a ttl inputs v iht input high voltage 2.0 v cc v v ilt input low voltage ? 0.5 0.8 v i iht input high current v in = v cc +40 a i ilt input low current v in = 0.0v ? 40 a i ihpd input high current v in = v cc , pins with internal pull-down +300 a i ilpu input low current v in = 0.0v, pins with internal pull-up ? 300 a transmitter pecl-compatible output pins: outa+, outa ? , outb+, outb ? v ohe output high voltage (v dd referenced) load = 50 ? to v cc ? 1.33v r curset = 10k ( %1 tolerance) v dd ? 1.03 v dd ? 0.83 v v ole output low voltage (v dd referenced) load = 50 ? to v cc ? 1.33v r curset = 10k ( %1 tolerance) v dd ? 2v dd ? 1.62 v v odif output differential voltage |(out+) ? (out ? )| load = 50 ? to v cc ? 1.33v r curset = 10k ( %1 tolerance) 600 1100 mv receiver single-ended pecl-compatible input pin: cardet v ihe input high voltage (v dd referenced) v dd ? 1.165 v dd v v ile input low voltage (v dd referenced) 2.5 v dd ? 1.475 v i ihe input high current v in = v ihe (min.) +40 a i ile input low current v in = v ile (max.) ? 40 a differential line receiver input pins: ina+, ina ? , inb+, inb ? v diff input differential voltage |(in+) ? (in ? )| 200 2500 mv v ihh highest input high voltage v dd v v ill lowest input low voltage 2.5 v i ihh input high current v in = v ihh max. 750 a i ill [2] input low current v in = v ill min. ? 200 a miscellaneous typ. max. i dd [3] power supply current freq. = max. 170 250 ma capacitance [4] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25 c, f 0 = 1 mhz, v dd = 5.0v 7 pf c inpecl pecl input capacitance t a = 25 c, f 0 = 1 mhz, v dd = 5.0v 4 pf notes: 1. tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 2. to guarantee positive currents for all pecl voltages, an external pull-down resistor must be present. 3. maximum i dd is measured with v dd = max, rfen = low, and outputs unloaded. typical i dd is measured with v dd = 5.0v, t a = 25 c, rfen = low, and outputs unloaded. 4. tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
CY7C954DX preliminary 18 ac test loads and waveforms 2.0v 0.8v 3.0v 0.0v 2.0v 0.8v 5.0v output (a) ttl ac test load (b) pecl ac test load <1ns <1 ns 80% 20% 80% 20% (c) ttl input test waveform (d) pecl input test waveform r1 r2 c l c l r l r1 = 500 ? r2 = 333 ? (includes fixture and probe capacitance) r l =50 ? c l <5pf (includes fixture and probe capacitance) v ihe 3.0v v dd ? 1.33v v ihe v ile v ile [5] [5] v th =1.5v v th =1.5v 1 ns 1 ns c l 10 pf [5] CY7C954DX transmitter ttl switching characteristics over the operating range parameter description 7c954dx unit min. max. f ts txclk clock cycle frequency 50 mhz t txclk txclk period 20 ns t txcpwh txclk high time 6.5 ns t txcpwl txclk low time 6.5 ns t txclkr txclk rise time 0.7 2 ns t txclkf txclk fall time 0.7 2 ns t txa flag access time from txclk to output 2 15 ns t txds transmit data set-up time to txclk 4ns t txdh transmit data hold time from txclk 1ns t txens transmit enable set-up time to txclk 4ns t txenh transmit enable hold time from txclk 1ns t txrss transmit fifo reset (txrst*) set-up time to txclk 4ns t txrsh transmit fifo reset (txrst*) hold time from txclk 1ns t txams transmit address match set-up time to txclk 4ns t txamh transmit address match hold time from txclk 1ns t txoza sample of address match true by txclk , output high-z to active high or low 0ns t txoe sample of address match true by txclk to output valid 1.5 20 ns t txoaz sample of address match false by txclk to output in high-z 1.5 20 ns note: 5. cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only.
CY7C954DX preliminary 19 CY7C954DX receiver ttl switching characteristics over the operating range parameter description 7c954dx unit min. max. f ris rxclk clock cycle frequency 50 mhz t rxclkp rxclk input period 20 ns t rxcpwh rxclk input high time 6.5 ns t rxcpwl rxclk input low time 6.5 ns t rxclkir rxclk input rise time 0.25 2 ns t rxclkif rxclk input fall time 0.25 2 ns t rxens receive enable set-up time to rxclk 4ns t rxenh receive enable hold time from rxclk 1ns t rxrss receive fifo reset (rxrxt*) set-up time to rxclk 4ns t rxrsh receive fifo reset (rxrxt*) hold time from rxclk 1ns t rxams receive address match set-up time to rxclk 4ns t rxamh receive address match hold time from rxclk 1ns t rxa [6] flag and data access time from rxclk to output 1.5 15 ns t rxoza [6] sample of address match true by rxclk , output high-z to active high or low, or sample of rxen* asserted by rxclk , output high-z to active high or low 0ns t rxoe [6] sample of address match true by rxclk to output valid [6] , or sample of rxen* asserted by rxclk to rxdata outputs valid 1.5 20 ns t rxoaz [6] sample of address match false by rxclk to output in high-z [6] , or sample of rxen* asserted by rxclk to rxdata outputs in high-z 1.5 20 ns CY7C954DX refclk input switching characteristics over the operating range parameter description conditions min. max. unit spdsel rangesel f ref refclk clock frequency ? 40 to 100 mbaud, 8-bit mode, refclk = 2x character rate 00820mhz refclk clock frequency ? 40 to 100 mbaud, 8-bit mode, refclk = 4x character rate 011640mhz refclk clock frequency ? 100 to 200 mbaud, 8-bit mode, refclk = character rate 101020mhz t refclk refclk period 25 120 ns t refh refclk high time 6.5 ns t refl refclk low time 6.5 ns t refrx refclk frequency referenced to received clock period [7] ? 0.04 +0.04 % notes: 6. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. 7. refclk has no phase or frequency relationship with the recovered byte clock, which sets the receiver operating frequency, and only acts as a centering reference to reduce clock synchronization time. refclk must be within 0.04% of the transmitter pll reference (refclk) frequency, necessitating a 200-ppm crystal.
CY7C954DX preliminary 20 CY7C954DX receiver switching characteristics over the operating range parameter description condition 7c954dx unit min. max. t b [8] bit time 5.0 20.0 ns t in-j in peak-to-peak input jitter tolerance [4, 10, 11] 0.5 ui t sa static alignment [4, 9] 600 ps t efw error free window [4, 10, 12] 0.65 ui CY7C954DX transmitter switching characteristics over the operating range parameter description condition 7c954dx unit min. max. t b [8] bit time 5.0 20.0 ns t rise pecl output rise time 20 ? 80% (pecl test load) [4] 200 1700 ps t fa ll pecl output fall time 80 ? 20% (pecl test load) [4] 200 1700 ps t dj deterministic jitter (peak-peak) [4, 13] 0.02 ui t rj random jitter ( ) [4, 14] 0.008 ui t jt transmitter total output jitter (pk-pk) [4] 0.08 ui notes: 8. the pecl switching threshold is the midpoint between the v ohe , and v ole specification (approximately v dd ? 1.33v). 9. static alignment is a measure of the alignment of the receiver sampling point to the center of a bit. static alignment is mea sured by the absolute difference of the left and right edge shifts (|t sh_l ? t sh_r |) of one bit until a character error occurs. 10. receiver ui (unit interval) is calculated as (1/f ref ) if no data is being received, or (1/f ref ) of the remote transmitter if data is being received. in an operating link this is equivalent to 10 * t b . 11. the specification is sum of 25% duty cycle distortion (dcd), 10% data dependent jitter (ddj), 15% random jitter (rj). 12. error free window is a measure of the time window between bit centers where an input data transition may occur without causi ng a bit sampling error. efw is measured over the operating range, input jitter < 50% dj. 13. while sending continuous k28.5s, outputs l oaded to 50 ? to v dd ? 1.33v, over the operating range. 14. while sending continuous k28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to refclk input, over the operating range.
CY7C954DX preliminary 21 CY7C954DX hotlink transmitter switching waveforms notes: 15. when transferring data to the transmit fifo from a depth expanded external fifo, the data is captured from the external fifo one clock cycle following the actual enable. 16. when writing data from a utopia compliant interface, the write data is captured on the same clock cycle as the data. no operation t txa t txa txclk t txclk t txclkh t txclkl txdata[7:0] txsc/d* txen txfull txclav txempty t txds t txdh t txens t txenh note 15 cascade timing write cycle txsoc txsvs no operation t txa txclk txen* txfull* txclav txempty* t txdh t txds t txclk t txclkh t txclkl t txens t txenh note 16 t txa utopia timing write cycle txdata[7:0] txsc/d* txsoc txsvs
CY7C954DX preliminary 22 note: 17. transmit fifo writes are permitted while the status flag outputs are high-z, however operation in this mode is not encourage d since this may mask a fifo full condition, causing data to be lost. CY7C954DX hotlink transmitter switching waveforms (continued) no operation txclk txen* txfull* txempty* t txdh t txds t txclk t txclkh t txclkl t txens t txenh note 17 t txoza t txoe t txoaz t txrss txrst* t txrsh output enable timing txdata[7:0] txsc/d* txsoc txsvs txaddr[2:0]=addrsel[2:0] txaddr[2:0] t txamh t txams
CY7C954DX preliminary 23 CY7C954DX hotlink receiver switching waveforms notes: 18. when transferring data from the receive fifo to a depth expanded external fifo, the data is sent to the external fifo on the same clock cycle an rxempty indicates the data is available. 19. on inhibited reads, or if the receive fifo goes empty, the data outputs do not change. 20. when reading data from a utopia compliant interface, the data is captured on the same clock cycle as the fifo flag indicates data available, and not when the fifo indicates empty. cascade timing read cycle no operation rxclk rxempty rxen valid data t rxclkp t rxclkh t rxclkl t rxens t rxenh rxdata[7:0] rxsc/d* lfi* rxfull rxclav t ra read read t ra note 18 note 19 fifo empty rxsoc rxrvs with address matched utopia timing read cycle rxclk rxempty* rxen* valid data t rxclkp t rxclkh t rxclkl t rxens t rxenh t ra read t ra note 20 fifo empty rxdata[7:0] rxsc/d* lfi* rxfull rxclav rxsoc rxrvs with address matched
CY7C954DX preliminary 24 note: 21. receive fifo reads are inhibited while the outputs are high-z. CY7C954DX hotlink receiver switching waveforms (continued) output enable timing no operation rxclk rxen* rxempty* t rxclk t rxclkh t rxclkl t rxens t rxenh t rxoza t rxoe t rxoaz old data note 21 t rxams rxdata[7:0] rxsc/d* rxfull* rxclav rxsoc rxrvs rxaddr[2:0]=addrsel[2:0] rxaddr[2:0] t rxamh refclk t refl t refh t refclk b923 ? 14 ina inb t b /2- t sa t b /2- t sa static alignment sample window ina inb t b t efw bit center bit center error-free window
CY7C954DX preliminary 25 CY7C954DX hotlink transceiver operation the interconnection of two or more CY7C954DX transceivers form a general-purpose communications subsystem capable of transporting user data at up to 20 mbytes per second over several types of serial interface media. the CY7C954DX is highly configurable with multiple modes of operation. in the transmit section of the CY7C954DX, data moves from the input register, through the transmit fifo, to the 8b/10b encoder. the encoded data is then shifted serially out the outx differential pecl compatible drivers. the bit-rate clock is generated internally from a 2.5x, 5x, or 10x pll clock mul- tiplier. a more complete description is found in the section CY7C954DX hotlink transmit-path operating mode de- scription . in the receive section of the CY7C954DX, serial data is sam- pled by the receiver on one of the inx differential line receiver inputs. the receiver clock and data recovery pll locks onto the selected serial bit stream and generates an internal bit-rate sample clock. the bit stream is deserialized, decoded, and presented to the receive fifo, along with a character clock. the data in the fifo can then be read either slower or faster than the incoming character rate. a more complete description is found in the section CY7C954DX hotlink receive-path operating mode description . the transmitter and receiver parallel interface timing and functionality can be configured to be a utopia level i or ii compliant interface, or for single phy (point-to-point interfac- es) to cascade directly to external fifos for depth expansion. the hotlink transceiver serial interface provides a seamless interface to various types of media. a minimal number of ex- ternal passive components are required to properly terminate transmission lines and provide pecl loads. for power supply decoupling, a single capacitor (in the range of 0.02 f to 0.1 f) is required per power/ground pair. additional informa- tion on interfacing these components to various media can be found in the ? hotlink design considerations ? application note. CY7C954DX hotlink transmit-path operating mode descriptions the hotlink transmitter data interface is an asynchronous parallel data register, enabled by a match between the txaddr[2:0] and the strapped value on addrsel[2:0], and qualified by txen. input register mapping txdata input bus is mapped into characters including a txsoc and txsvs bit for protocol mapping, eight bits of data and a txsc/d* bit to select either control or data characters. if the txsvs bit is high (and either txsoc or txsc/d* is low), an svs (c0.7) character is passed to the encoder, re- gardless of the contents of the other txdata inputs. if the txsvs bit is low, the associated txdata character is encod- ed per the remaining bits in that character. when txsoc is low, the txsc/d* bit controls the encoding of the data bits txdata[7:0] of each character. it is used to identify if the input character represents data or a special character code. if the txsc/d* input is low, the character is encoded using the data character codes listed in ta ble 8 . if the txsc/d* input is high, the character is encoded using the special character codes listed in ta b l e 9 . this input structure allows transmission of normal data streams, while offering the added benefits of three types of embedded cell markers. the serializer operates synchronous to refclk, which is multiplied by 10 to generate the serial data bit-clock. embedded cell marker embedded cell markers are used to mark the start of cells or frames of information passed from one end of the link to the other. these markers are set by asserting txsoc high, with txsc/d* and txsvs in combinations of high or low (see ta ble 1 ), along with the remaining data on the txdata bus. when the character accompanying this marker is read from the output end of the transmit fifo, a c8.0 (k23.7), c9.0 (k27.7), or c10.0 (k29.7) character is inserted into the data stream prior to the following data characters being read from the transmit fifo. CY7C954DX hotlink receive-path the hotlink receiver is a serial-in to parallel-out converter with some data processing capability. in this mode, serial data is received at one of the differential line receiver inputs and routed to the deserializer and framer. the pll in the clock and data recovery block is used to extract a bit-rate clock from the transitions in the data stream, and uses that clock to capture bits from the serial stream. these bits are passed to the deserializer where they are formed into 10-bit characters. to align the incoming bit stream to the proper character bound- aries, the framer must be enabled by asserting rfen high. the framer logic-block checks the incoming bit stream for the unique pattern that defines the character boundaries. this log- ic filter looks for the ansi x3.230 symbol defined as a ? special character comma ? (k28.5 or c5.0). once a k28.5 is found, the framer captures the offset of the data stream from the present character boundaries, and resets the boundary to re- flect this new offset, thus framing the data to the correct char- acter boundaries. since noise-induced errors can cause the incoming data to be corrupted, and since many combinations of corrupt and legal data can create an aliased k28.5, the framer may also be dis- abled by deasserting rfen low. an option exists in the framer to require multiple k28.5 char- acters, meeting specific criteria, before the character bound- aries are reset. this multi-byte mode of the framer is enabled by keeping rfen asserted high for greater than approxi- mately 2000 character clock cycles. for multi-byte framing, the receiver must find a pair of k28.5 characters, both on identical 10-bit boundaries, within a 5-character span (50 bits). the deserializer operates synchronous to the recovered bit- clock, which is divided by 10 to generate the receive fifo write clock. data words are read from the receive fifo, using the external rxclk input, when addressed by rxaddr[2:0] matching addrsel[2:0] and selected by rxen*. embedded cell marker three types of embedded cell marker are available to mark the start of cells or frames of information passed from one end of the link to the other. when a c8.0 (k23.7) character is detected
CY7C954DX preliminary 26 in the data stream it is discarded and the following character is written to the receive fifo along with rxsoc set high, and rxsc/d* and rxrvs set low. when the character ac- companying this marker is read from the receive fifo with these same bits set, it indicates the start of cell marker type i. when a c9.0 (k27.7) character is detected in the data stream it is discarded, and the following character is written to the receive fifo along with both rxsoc and rxsc/d* set high, and rxrvs set low indicating start of cell marker type ii. when a c10.0 (k29.7) character is detected in the data stream it is discarded, and the following character is written to the receive fifo along with rxsoc, rxsc/d*, and rxrvs set high indicating start of cell marker type iii. bist operation and reporting the CY7C954DX hotlink transceiver incorporates the same built-in self-test (bist) capability used with the cy7b923/cy7b933 and cy7c954 hotlink components. this link diagnostic uses a linear-feedback shift-register (lfsr) to generate a 511-character repeating sequence that is compared, character-for-character, at the receiver. bist mode is intended to check the entire high-speed serial link at full link-speed, without the use of specialized and expen- sive test equipment. the complete sequence of patterns used in bist are documented in the ? hotlink built-in self-test ? application note. bist enable inputs there are separate bist enable inputs for the transmit and receive paths of the CY7C954DX. these inputs are both active low; i.e., bist is enabled in its respective section of the de- vice when the bist enable input is determined to be at a logic- 0 level. both bist enable inputs are asynchronous; i.e., they are synchronized inside the CY7C954DX to the internal state machines. bist transmit path the transmit path operation with bist is controlled by the txbisten* input and overrides most other inputs (see figure 5 ). when txbisten* is recognized internally, all reads from the transmit fifo are suspended and the bist generator is enabled to sequence out the 511-character repeating bist sequence. if the transmit control state machine was in the middle of an atomic operation (e.g., sending an soc of any type) the data character associated with the special charac- ter code must be transmitted prior to recognition of the txbisten* signal and suspension of fifo data processing. if the recognition occurs in the middle of a cell, the remaining data for that cell is not transmitted at that time, but remains in the transmit fifo. once the txbisten* signal is removed, the data in the transmit fifo is again available for transmis- sion. with transmit bist enabled, the transmit fifo remains avail- able for loading of data. it may be written up to its normal max- imum limit while the bist operation takes place. to allow re- figure 5. built-in self-test illustration rxbisten* txbisten* txclk txempty* refclk txen* txaddr[2:0] rxclk rxempty* rxen* rxaddr[2:0] addrsel[2:0] txdata[7:0] txsc/d* txsoc txsvs txclav txfull* rxclav rxfull* rxdata[7:0] rxsc/d* rxsoc rxrvs enable tx bist start of tx bist bist loop don ? t care address must match to enable flags ignore these outputs low to enable rxrvs forced to indicate empty by bist enable rx bist start of rx bist wait start of rx bist match bist loop outa+ outb+ ina+ inb+ a/b* high to select a CY7C954DX error
CY7C954DX preliminary 27 moval of stale data from the transmit fifo, it may also be reset during a bist operation. the reset operation proceeds as doc- umented, with the exception of the information presented on the txempty* fifo status flag. since this flag is used to present bist loop status, it will reflect the state of the transmit bist loop status until txbisten* is no longer recognized in- ternally. the completion of the reset operation may still be monitored through the txfull* fifo status flag. the txempty* flag, when used for transmit bist progress indication, continues to reflect the active high or active low settings determined by the utopia or cascade timing model selected by the extfifo input.; i.e., when configured for the cascade timing model, the txempty and txfull fifo flags are active high, when configured for the utopia timing model the txempty* and txfull* fifo flags are active low. figure 5 uses the utopia conventions for the illustra- tion. when txbisten* is first recognized, the txempty* flag is clocked to a reset state, regardless of the addressed state of the transmit fifo (if txaddr[2:0] matches addrsel[2:0] or not), but is not driven out of the part unless the match has been sampled true. following this, on each completed pass through the bist loop, the txempty* flag is set for one txclk period. the txempty* flag remains set until the interface is ad- dressed and the state of txempty* has been observed. if the device is not addressed (if txaddr[2:0] does not match addrsel[2:0]), the flag remains set internally regardless of the number of txclk clock cycles that are processed. if the device status is not polled on a sufficiently regular basis, it possible for the host system to miss some of these bist loop indications. a pass through the loop is defined as that condition where the encoder generates the d0.0 state. depending on the initial state of the bist lfsr, the first pass through the loop may occur at substantially less than 511 character periods. follow- ing the first pass, as long as txbisten* remains low, all remaining passes are exactly 511 characters in length. bist receive path the receive path operation in bist is similar to that of the transmit path. when rxbisten* is recognized internally, all writes to the receive fifo are suspended. if the receive data state machine was in the middle of processing a multi-charac- ter sequence or other atomic operation (e.g., a start of cell marker and its associated data), the characters associated with the atomic operation are discarded and not written to the receive fifo. any data present in the receive fifo when rxbisten* is recognized remains in the fifo but is not available for read- ing through the host parallel interface until the bist operation is complete. this is because the error output indicator for re- ceive bist operations is the rxrvs pin, which is normally associated with the rxdata bus. to prevent read operations while bist is in operation, the rxempty* and rxclav flags are forced to indicate an empty condition. once rxbisten* has been removed and recognized internally, the receive fifo status flags are updated to reflect the current content status of the receive fifo. to allow removal of stale data from the receive fifo, it may be reset during a bist operation. the reset operation pro- ceeds as documented, with the exception that the rxempty* and rxclav status flags already indicate an empty condition. the rxfull* flag is used to present bist progress. the ac- tive (asserted) state on rxfull* (and rxempty*) remain controlled by the present operating mode and interface timing model (utopia or cascade). when rxbisten* has been recognized, rxfull* becomes the receive bist loop indicator. when rxbisten* is first rec- ognized, the rxfull* flag is clocked to a set state, regardless of the addressed state of the receive fifo (regardless of the match between txaddr[2:0] and addrsel[2:0]). following this, rxfull* remains set until the receiver detects the start of the bist pattern. then rxfull* is deasserted for the du- ration of the bist pattern, pulsing asserted for one rxclk period on the last symbol of each bist loop. if 14 of 28 con- secutive characters are received in error, rxfull* returns to the set state until the start of a bist sequence is again de- tected. just like the bist status flag on the transmit data path, the rxfull* flag captures the asserted states, and keeps them until they are read. this means that if the status flag is not read on a regular basis, events may be lost. the detection of errors is presented on the rxrvs output. unlike the rxfull* fifo status flag, the active state of this outputs is not controlled by the extfifo input. with the re- ceive fifo enabled, this output will operate the same as the rxfull* flag, with respect to preserving the detection state of an error until it is read. an error indication that occurs while the rxen* is deasserted will be ? remembered ? until rxen* is asserted. unlike the rxfull* flag, which only needs the CY7C954DX to be addressed (rxaddr[2:0] matching addrsel[2:0] sampled true by rxclk) to enable the rxfull* three-state driver, and an rxclk to ? read ? the flag, the rxrvs output requires a selection (assertion of rxen* while addressed) to enable the rxdata bus three-state drivers. the selection pro- cess is necessary to ensure that a multi-phy implementation does not enable two drivers onto the rxrvs output at the same time. bus interfacing the parallel transmit and receive host interfaces to the CY7C954DX are configurable. the choices are utopia or cascade control modes. both modes have internal transmit and receive fifos which can be written or read at any rate up to the maximum 50-mhz clock rate of the fifos. internal operations of the CY7C954DX do not use the external txclk or rxclk, but instead make use of refclk for transmit path operations and a recovered character clock for receive path operations. the utopia timing model is based on the atm forum utopia interface standards. this timing model is that of a fifo with active low fifo status flags and read/write en- ables. the cascade timing model is a modification of the utopia configuration that changes the flags and fifo read/write en- ables to active high. this model is present primarily to allow depth expansion of the internal fifo by direct coupling to ex- ternal cy7c42x5 synchronous fifos. to allow this direct cou- pling, the cycle-to-cycle timing between the transmit and re- ceive enables (txen* and rxen*) are also modified to ensure correct data transfer.
CY7C954DX preliminary 28 these two configurations of bus operation and timing/control can all be used with or without external fifos. depending on the specific mode selected, the amount of external hardware necessary to properly couple the CY7C954DX to state ma- chines or external fifos is minimal in all cases, and may be zero if the proper configuration is selected. with only minor exceptions, all configurations rely on the com- mon utopia concepts of addressing and selection to control the enabled/disabled state of the output drivers, and when data can be written to or read from the part. utopia interface background the utopia interface is defined by the atm forum as the bus interface between the atm and phy layer devices of an atm system. this interface is defined as 8 bits or 16 bits wide, with the later reserved mainly for high-speed physical interfaces (phys) such as 622 mbps oc-12. due to the limited speed range of the cy7c954, only the 8-bit interface is implemented. utopia-1 was the original utopia specification (created in 1993) which covers transport of: 155.52 mbps (scrambled sonet/ oc-3) 155.52 mbps (8b/10b block coded at 194.4 mbaud) 100 mbps (4b/5b encoded taxi) 44.736 mbps (ds-3/t3) 51.84 mbps (oc-1) the utopia-1 interface has a maximum clock rate of 25 mhz. all ac timing and pin descriptions are covered in the utopia-1 specification, version 2.01. utopia-2 was created as an addendum to the utopia-1 specification. in this revision, the parallel interface was extend- ed to both 33 mhz and 50 mhz to accommodate pci bus ar- chitectures in atm designs. a method of addressing was add- ed to allow up to thirty one devices (phys) to share a common host bus. also, a description of a management interface was added (not supported by this device). the CY7C954DX contains all pins necessary to support the utopia-1 and up to seven utopia-2 devices using the txaddr[2:0], rxaddr[2:0], and addrsel[2:0] pins. the full thirty-one device space can be accessed by use of an ex- ternal address decoder (connected to one of the txaddr[2:0] and rxaddr[2:0] pins). the maximum bus speed supports the full 50-mhz i/o rate for emerging high-performance sys- tems. utopia address match and selection all actions on a utopia-2 interface are controlled by the ad- dress match and selection states of the interface. these states control the read and write access to the receive and transmit fifos, access to the fifo status flags, and reset of the trans- mit and receive fifos. the CY7C954DX supports the con- cept of an ? address match ? using a three-bit chip address input (addrsel[2:0]) and a pair of data port address vectors (txaddr[2:0] and rxaddr[2:0]). address match and fifo flag access the CY7C954DX makes use of a three-bit address select vector, which is compared to a txaddr and rxaddr input to generate address-match conditions. when these inputs match, as is required to implement an atm address compare on both the txaddr and rxaddr buses. this allows multi- ple CY7C954DX devices to share a common bus, with device output three-state controls being managed by either an address match condition (txaddr[2:0] matches addrsel[2:0]), or by a selection state. the transmit and receive fifo flag output drivers are en- abled in any txclk, or rxclk cycle following txaddr[2:0] matching addrsel[2:0] being sampled true by the rising edge of the respective clock. the txaddr[2:0] and rxaddr[2:0] inputs are sampled separately by the clocks for the transmit and receive interfaces, which allows these clocks to be both asynchronous to each other, and to operate at dif- ferent clock rates. an example of both transmit and receive fifo flag access is shown in figure 6 . when the transmit fifo is enabled by the rising edge of txclk and txaddr[2:0] matches addrsel[2:0], the output drivers for the txclav, txfull* and txempty* fifo flags are enabled. when txaddr[2:0] doesn ? t match addrsel[2:0] at the rising edge of txclk, these same out- put drivers are disabled. device selection the concept of selection is used to control the access to the transmit and receive parallel-data ports of the device. there are five primary types of selection: transmit data selection receive data selection transmit fifo flag selection receive fifo flag selection continuous selection (for either or both transmit and receive interfaces) in addition to these normal selection types, there are two ad- ditional sequences that are used to control the internal trans- mit and receive fifos reset operations: transmit reset sequence receive reset sequence of these selection types, the transmit data selection and trans- mit reset sequence states are mutually exclusive and cannot exist at the same time. the receive data selection and receive rxclk address match rxclav valid figure 6. fifo flag driver enables txclk address match txclav valid transmit port addressing receive port addressing
CY7C954DX preliminary 29 reset sequence states are also mutually exclusive and cannot exist at the same time. either transmit state can exist at the same time as either receive state. all normal forms of selection require that an address match condition must exist (txaddr[2:0] or rxaddr[2:0] matching addrsel[2:0]) either at the same time as the selection con- trol signal being sampled asserted, or one or more clock cy- cles prior to the selection control signal being sampled as- serted. transmit timing and control utopia flag selection when txaddr[2:0] matches addrsel[2:0] and txrst* is sampled high by the rising edge of txclk, a tx_match con- dition is generated. this tx_match condition continues until txaddr[2:0] doesn ? t match addrsel[2:0] or txrst* is sampled low at the rising edge of txclk. when a tx_match (or tx_rstmatch) condition is present, the txclav, txempty*, and txfull* output drivers are enabled. when a tx_match (or tx_rstmatch) condition is not present, these same drivers are disabled (high-z). utopia data selection the selection state of the transmit fifo is entered when a tx_match condition is present, and txen* transitions from high to low. once selected, the transmit fifo remains se- lected until txen* is sampled high by the rising edge of txclk. in the selected state, data present on the txdata inputs is captured and stored in the transmit fifo. this trans- mit interface selection process is shown in figure 7 . receive timing and control utopia flag selection when rxaddr[2:0] matches addrsel[2:0] and rxrst* is sampled high by the rising edge of rxclk input, an rx_match condition is generated. this rx_match condition continues until rxaddr[2:0] doesn ? t match addrsel[2:0] or rxrst* is sampled low at the rising edge of rxclk input. when an rx_match (or rx_rstmatch) condition is present, the rxclav, rxempty* and rxfull* output drivers are en- abled. when an rx_match (or rx_rstmatch) condition is not present, these same drivers are disabled (high-z). the utopia data selection state of the receive fifo is en- tered when an rx_match condition is present, and rxen* transitions from high to low. once selected, the receive fifo remains selected until rxen* is sampled high by the rising edge of rxclk input. the selected state initiates a read cycle from the receive fifo, and enables the receive fifo data onto the rxdata bus. this receive interface selection process is shown in figure 8 . continuous selection continuous selection is a specialized form of selection which does not require sequenced assertion of address match and txen* or rxen* to select the device for data transfers. in this continuous selection mode, the txaddr[2:0] or rxaddr[2:0] matches addrsel[2:0] and associated txen* or rxen* en- figure 7. transmit selection notes: 22. signals labeled in italics are internal to the CY7C954DX. 23. signals shown as dotted lines represent the differences in timing and active state of signals when operated in cascade timin g. [22] [22] not full txrst* address match tx_match txen* tx_selected txdata txclk d1 not full d2 d3 txclav d1 d2 d3 (utopia timing) txdata (cascade timing) note 23 note 23
CY7C954DX preliminary 30 able signal must be deasserted for one clock cycle when the device is powered up. so long as these signals remain assert- ed, the device remains selected and data is accepted and pre- sented on every clock cycle. note: the use of continuous selection makes it impossible to reset the respective internal fifos. fifo reset address match when txaddr[2:0] matches addrsel[2:0] and txrst* are both low, and this condition is sampled by eight consec- utive rising edges of txclk, a tx_rstmatch condition is gen- erated. this tx_rstmatch condition continues until txaddr[2:0] doesn ? t match addrsel[2:0] or txrst* is sampled high by the rising edge of txclk. when a tx_rstmatch (or tx_match) condition is present, the txempty*, and txfull* output drivers are enabled (just as in a normal tx_match condition). when a tx_rstmatch (or tx_match) condition is not present, these same drivers are disabled (high-z). the transmit fifo reset address match is shown in figure 9 . note that although txrst* remains low for more than one clock cycle, the tx_rstmatch does not be- cause the txaddr[2:0] doesn ? t match addrsel[2:0]. when rxaddr[2:0] matches addrsel[2:0] and rxrst* is low, and this condition is sampled by eight consecutive rising edges of rxclk, an rx_rstmatch condition is generated. this rx_rstmatch condition continues until rxaddr[2:0] doesn ? t match addrsel[2:0] or rxrst* is sampled high, at the rising edge of rxclk. when an rx_rstmatch (or rx_match) condition is present, the rxempty* and rxfull* output drivers are enabled. when an rx_rstmatch (or rx_match) condition is not present, these same drivers are disabled (high-z). the receive fifo reset address match is shown in figure 10 . note that while the fifo flags remain asserted for more than one clock cycle, this is due to an rx_match condition, not a continuation of the rx_rstmatch. fifo reset sequence on power-up, the transmitter and receiver fifos may contain random data. the transmitter fifo will empty automatically as the transmitter sends the random data within the first 256 character times after power is applied. the receiver fifo will retain any random data stored in it at power-up, and will accu- mulate all the random data being received from any attached transmitter as it is powered up. most of the incoming random data may be discarded based on the receiver discard policy shown in figure 5 . this random received data can be ? flushed ? by reading it, or the receive fifo can be ? reset ? to remove the unwanted data. the transmit fifo and receive fifo are reset when the tx_rstmatch or rx_rstmatch condition remains present for h1 h2 h3 rxclk address match rx_match rxen rx_selected rxdata rxclav figure 8. receive selection rxrst* not empty not empty [22] [22] note 23 note 23 txclk address match txclav txrst* tx_rstmatch tx_match figure 9. transmit fifo reset address match note: 24. signal names listed in italics are internal signals, shown for reference only. valid [24] [24]
CY7C954DX preliminary 31 eight consecutive clock cycles. any disruption of the reset se- quence prior to reaching the eight cycle count, either by re- moval of the txaddr[2:0] or rxaddr[2:0] matches with addrsel[2:0] or the respective txrst* or rxrst*, or as- sertion of the associated txen* or rxen*, terminates the se- quence and does not reset the fifo. because the txaddr[2:0] or rxaddr[2:0] matching addrsel[2:0] must remain asserted during the reset sequence, the addressed fifo flags remain driven during the entire sequence. the fifo reset sequence will remove any pre-existing ad- dress match condition and txen* or rxen* w ill need to be deasserted for one clock cycle before address match can be re-established. transmit fifo reset sequence the transmit fifo reset sequence is started when txrst* is sampled low and txaddr[2:0] matches addrsel[2:0] on the rising edge of txclk. however, if txen* is asserted, the reset sequence is inhibited until it is removed (txen* is sam- pled high for utopia timing or low for cascade timing). because a tx_rstmatch condition is present, the transmit fifo flags are asserted and can be used to track the status of any transmit fifo reset in progress. once the reset sequence has reached its maximum count, the transmit fifo flags are forced to indicate a full* condition (txclav is deasserted, and txfull* is asserted). this indicates that the transmit fifo reset has been recognized by the transmit control state machine and that a reset has been started. note: the fifo full state forced by the reset operation is dif- ferent from a full state caused by normal fifo data writes. for normal fifo write operations, when full is first asserted, the transmit fifo must still accept up to four additional writes of data. when a full state is asserted due to a transmit fifo reset operation, the fifo will not accept any additional data. the transmit fifo reset does not complete until the external reset condition is removed. this can be removed by deasser- tion of either txrst* or the address match. if the address match is deasserted to remove the reset condition, the trans- mit fifo flag ? s drivers are disabled, and the transmit fifo must be addressed at a later time to validate completion of the transmit fifo reset. if txrst* is deasserted (high) to re- move the reset condition, the tx_rstmatch is changed to a tx_match, and the transmit fifo status flags remain driven. the transmit fifo reset operation is complete when the transmit fifo flags indicate an empty state (txempty* and txclav are asserted and txfull* is deasserted). a valid transmit fifo reset sequence is shown in figure 11 . here the txaddr[2:0] matches addrsel[2:0] and txrst* is asserted (low) at the same time. when these signals are both sampled low by txclk, a tx_rstmatch condition is present. with txen* deasserted (high), the transmit fifo is not selected for data transfers. this tx_rstmatch condition remains for eight txclk cycles to generate the tx_fifo_reset. following this the txfull* fifo status flag is asserted to indicate that the transmit fifo reset sequence has completed and that a transmit fifo reset is in progress. when the txrst* signal is deasserted (high), txaddr[2:0] still matches addrsel[2:0] to allow the fifo status flags to be driven. this allows the completion of the reset operation to be monitored. to allow better multi-tasking on multi-phy im- plementations, it is possible to deassert the address match as soon as the full state is indicated. the fifo reset operation will complete and the empty state (indicating completion of the reset operation) can be detected during a separate polling op- eration. for those links implemented with a single phy, it is possible to hard wire txaddr[2:0] to match addrsel[2:0] and still per- form normal accesses and reset operations. this is shown in figure 12 . in a single-phy implementation with address match always true, a transmit fifo reset can never be initiated with txen* asserted at the same time as txrst*. since the address match is always true, any assertion of txen* caus- es the transmit fifo to be selected, preventing the reset counter from advancing. figure 13 shows a sequence of input signals which will not produce a fifo reset. in this case txen* was asserted to select the a transmit fifo for data transfers. because txen* remains active, the assertion of a txaddr[2:0] matching addrsel[2:0] and txrst* does not initiate a reset opera- tion. this is shown by the txfull* flag remaining high (deasserted) following what would be the normal expiration of the eight-state reset counter. receive fifo reset sequence the receive fifo reset sequence operates (for the most part) the same as the transmit fifo reset sequence. the same requirements exist for the assertion state of rxrst* and se- lection of the interface. a sample receive fifo reset se- quence is shown in figure 14 . upon recognition of a receive fifo reset, the receive fifo flags are forced to indicate an empty state to prohibit additional reads from the fifo. unlike the transmit fifo, where the internal completion of the reset operation is shown by first going full and later going empty when the internal reset is complete, there is no secondary in- dication of the completion of the internal reset of the receive fifo. the receive fifo is usable as soon as new data is placed into it by the receive control state machine. fifo reset and continuous selection when configured for continuous selection (txaddr[2:0] matching addrsel[2:0] asserted with txen* always en- abled, or rxaddr[2:0] matching addrsel[2:0] asserted with rxen* always enabled), it is not possible to reset the transmit and receive fifos. rxclk address match rxempty rxrst* rx_rstmatch valid rx_match figure 10. receive fifo reset address match valid [24] [24]
CY7C954DX preliminary 32 figure 11. transmit fifo reset sequence note: 25. signals shown as dotted lines indicate timing and levels when configured for external fifos (extfifo is high). txclk txrst* tx_rstmatch tx_fifo_reset txclav txen* address match tx_match not full full note 25 [24] [24] [24] note 25 figure 12. transmit fifo reset sequence with constant address match txclk txrst* tx_rstmatch tx_fifo_reset txfull* txen* address match tx_match [24] [24] [24] note 25 not full full note 25
CY7C954DX preliminary 33 figure 13. invalid transmit fifo reset sequence with txen* asserted txclk txrst* tx_rstmatch tx_fifo_reset txfull* txen* address match tx_match [24] [24] note 25 not full note 25 [24] figure 14. receive fifo reset sequence rxclk rxrst* rx_rstmatch rx_fifo_reset rxempty* rxen* address match rx_match [24] [24] [24] note 25 not empty empty note 25
CY7C954DX preliminary 34 x3.230 codes and notation conventions information to be transmitted over a serial link is encoded eight bits at a time into a 10-bit transmission character and then sent serially, bit by bit. information received over a serial link is collected ten bits at a time, and those transmission characters that are used for data (data characters) are decoded into the correct eight-bit codes. the 10-bit transmission code sup- ports all 256 8-bit combinations. some of the remaining trans- mission characters (special characters) are used for func- tions other than data transmission. the primary rationale for use of a transmission code is to improve the transmission characteristics of a serial link. the encoding defined by the transmission code ensures that suf- ficient transitions are present in the serial bit stream to make clock recovery possible at the receiver. such encoding also greatly increases the likelihood of detecting any single or mul- tiple bit errors that may occur during transmission and recep- tion of information. in addition, some special characters of the transmission code selected by fibre channel standard con- sist of a distinct and easily recognizable bit pattern (the special character comma) that assists a receiver in achieving word alignment on the incoming bit stream. notation conventions the documentation for the 8b/10b transmission code uses letter notation for the bits in an 8-bit byte. fibre channel stan- dard notation uses a bit notation of a, b, c, d, e, f, g, h for the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, j for encoded 10-bit data. there is a correspondence between bit a and bit a, b and b, c and c, d and d, e and e, f and f, g and g, and h and h. bits i and j are derived, respec- tively, from (a,b,c,d,e) and (f,g,h). the bit labeled a in the description of the 8b/10b transmission code corresponds to bit 0 in the numbering scheme of the fc- 2 specification, b corresponds to bit 1, as shown below. fc-2 bit designation ? 76543210 hotlink d/q designation ? 76543210 8b/10b bit designation ? hgf edcba to clarify this correspondence, the following example shows the conversion from an fc-2 valid data byte to a transmission character (using 8b/10b transmission code notation) fc-2 45 bits: 7654 3210 0100 0101 converted to 8b/10b notation (note carefully that the order of bits is reversed): data byte name d5.2 bits: abcde fgh 10100 010 translated to a transmission character in the 8b/10b trans- mission code: bits: abcdei fgh j 1010010101 each valid transmission character of the 8b/10b transmis- sion code has been given a name using the following conven- tion: cxx.y, where c is used to show whether the transmission character is a data character (c is set to d, and the sc/d* pin is low) or a special character (c is set to k, and the sc/d* pin is high). when c is set to d, xx is the decimal value of the binary number composed of the bits e, d, c, b, and a in that order, and the y is the decimal value of the binary number composed of the bits h, g, and f in that order. when c is set to k, xx and y are derived by comparing the encoded bit pat- terns of the special character to those patterns derived from encoded valid data bytes and selecting the names of the pat- terns most similar to the encoded bit patterns of the special character. under the above conventions, the transmission character used for the examples above, is referred to by the name d5.2. the special character k29.7 is so named because the first six bits (abcdei) of this character make up a bit pattern similar to that resulting from the encoding of the unencoded 11101 pat- tern (29), and because the second four bits (fghj) make up a bit pattern similar to that resulting from the encoding of the unencoded 111 pattern (7). note: this definition of the 10-bit transmission code is based on (and is in basic agreement with) the following references, which describe the same 10-bit transmission code. a.x. widmer and p.a. franaszek. ? a dc-balanced, parti- tioned-block, 8b/10b transmission code ? ibm journal of re- search and development , 27, no. 5: 440-451 (september, 1983). u.s. patent 4,486,739. peter a. franaszek and albert x. wid- mer. ? byte-oriented dc balanced (0.4) 8b/10b partitioned block transmission code ? (december 4, 1984). fibre channel physical and signaling interface (ans x3.230- 1994 ansi fc-ph standard). ibm enterprise systems architecture/390 escon i/o inter- face (document number sa22-7202). 8b/10b transmission code the following information describes how the tables shall be used for both generating valid transmission characters (en- coding) and checking the validity of received transmission characters (decoding). it also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within the higher-level constructs specified by the standard. transmission order within the definition of the 8b/10b transmission code, the bit positions of the transmission characters are labeled a, b, c, d, e, i, f, g, h, j. bit ? a ? shall be transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. (note that bit i shall be transmitted between bit e and bit f, rather than in alphabetical order.) valid and invalid transmission characters the following tables define the valid data characters and valid special characters (k characters), respectively. the tables are used for both generating valid transmission characters (en- coding) and checking the validity of received transmission characters (decoding). in the tables, each valid-data-byte or special-character-code entry has two columns that represent two (not necessarily different) transmission characters. the two columns correspond to the current value of the running disparity ( ? current rd ?? or ? current rd+ ? ). running disparity is a binary parameter with either the value negative ( ? ) or the value positive (+). after powering on, the transmitter may assume either a posi- tive or negative value for its initial running disparity. upon
CY7C954DX preliminary 35 transmission of any transmission character, the transmitter will select the proper version of the transmission character based on the current running disparity value, and the trans- mitter shall calculate a new value for its running disparity based on the contents of the transmitted character. special character codes c1.7 and c2.7 can be used to force the trans- mission of a specific special character with a specific running disparity as required for some special sequences in x3.230. after powering on, the receiver may assume either a positive or negative value for its initial running disparity. upon reception of any transmission character, the receiver shall decide whether the transmission character is valid or invalid accord- ing to the following rules and tables and shall calculate a new value for its running disparity based on the contents of the received character. the following rules for running disparity shall be used to cal- culate the new running-disparity value for transmission char- acters that have been transmitted (transmitter ? s running dis- parity) and that have been received (receiver ? s running disparity). running disparity for a transmission character shall be calcu- lated from sub-blocks, where the first six bits (abcdei) form one sub-block and the second four bits (fghj) form the other sub- block. running disparity at the beginning of the 6-bit sub-block is the running disparity at the end of the previous transmission character. running disparity at the beginning of the 4-bit sub- block is the running disparity at the end of the 6-bit sub-block. running disparity at the end of the transmission character is the running disparity at the end of the 4-bit sub-block. running disparity for the sub-blocks shall be calculated as fol- lows: 1. running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. it is also pos- itive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. it is also neg- ative at the end of the 6-bit sub-block if the 6-bit sub-block is 111000, and it is negative at the end of the 4-bit sub-block if the 4-bit sub-block is 1100. 3. otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. use of the tables for generating transmission characters the appropriate entry in the table shall be found for the valid data byte or the special character byte for which a transmis- sion character is to be generated (encoded). the current val- ue of the transmitter ? s running disparity shall be used to select the transmission character from its corresponding column. for each transmission character transmitted, a new value of the running disparity shall be calculated. this new value shall be used as the transmitter ? s current running disparity for the next valid data byte or special character byte to be encoded and transmitted. table 6 shows naming notations and examples of valid transmission characters. use of the tables for checking the validity of received transmission characters the column corresponding to the current value of the receiv- er ? s running disparity shall be searched for the received trans- mission character. if the received transmission character is found in the proper column, then the transmission character is valid and the associated data byte or special character code is determined (decoded). if the received transmission character is not found in that column, then the transmission character is invalid. this is called a code violation. indepen- dent of the transmission character ? s validity, the received transmission character shall be used to calculate a new value of running disparity. the new value shall be used as the re- ceiver ? s current running disparity for the next received trans- mission character. detection of a code violation does not necessarily show that the transmission character in which the code violation was detected is in error. code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the transmission char- acter in which the error occurred. ta b l e 7 shows an example of this behavior. table 6. valid transmission characters data byte name d in or q out hex value 765 43210 d0.0 000 00000 00 d1.0 000 00001 01 d2.0 000 00010 02 . . . . . . . . d5.2 010 000101 45 . . . . . . . . d30.7 111 11110 fe d31.7 111 11111 ff table 7. code violations resulting from prior errors rd character rd character rd character rd transmitted data character ? d21.1 ? d10.2 ? d23.5 + transmitted bit stream ? 101010 1001 ? 010101 0101 ? 111010 1010 + bit stream after error ? 101010 1011 + 010101 0101 + 111010 1010 + decoded data character ? d21.0 + d10.2 + code violation +
CY7C954DX preliminary 36 table 8. valid data characters (txsc/d* = low, rxsc/d* = low) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj d0.0 000 00000 100111 0100 011000 1011 d0.1 001 00000 100111 1001 011000 1001 d1.0 000 00001 011101 0100 100010 1011 d1.1 001 00001 011101 1001 100010 1001 d2.0 000 00010 101101 0100 010010 1011 d2.1 001 00010 101101 1001 010010 1001 d3.0 000 00011 110001 1011 110001 0100 d3.1 001 00011 110001 1001 110001 1001 d4.0 000 00100 110101 0100 001010 1011 d4.1 001 00100 110101 1001 001010 1001 d5.0 000 00101 101001 1011 101001 0100 d5.1 001 00101 101001 1001 101001 1001 d6.0 000 00110 011001 1011 011001 0100 d6.1 001 00110 011001 1001 011001 1001 d7.0 000 00111 111000 1011 000111 0100 d7.1 001 00111 111000 1001 000111 1001 d8.0 000 01000 111001 0100 000110 1011 d8.1 001 01000 111001 1001 000110 1001 d9.0 000 01001 100101 1011 100101 0100 d9.1 001 01001 100101 1001 100101 1001 d10.0 000 01010 010101 1011 010101 0100 d10.1 001 01010 010101 1001 010101 1001 d11.0 000 01011 110100 1011 110100 0100 d11.1 001 01011 110100 1001 110100 1001 d12.0 000 01100 001101 1011 001101 0100 d12.1 001 01100 001101 1001 001101 1001 d13.0 000 01101 101100 1011 101100 0100 d13.1 001 01101 101100 1001 101100 1001 d14.0 000 01110 011100 1011 011100 0100 d14.1 001 01110 011100 1001 011100 1001 d15.0 000 01111 010111 0100 101000 1011 d15.1 001 01111 010111 1001 101000 1001 d16.0 000 10000 011011 0100 100100 1011 d16.1 001 10000 011011 1001 100100 1001 d17.0 000 10001 100011 1011 100011 0100 d17.1 001 10001 100011 1001 100011 1001 d18.0 000 10010 010011 1011 010011 0100 d18.1 001 10010 010011 1001 010011 1001 d19.0 000 10011 110010 1011 110010 0100 d19.1 001 10011 110010 1001 110010 1001 d20.0 000 10100 001011 1011 001011 0100 d20.1 001 10100 001011 1001 001011 1001 d21.0 000 10101 101010 1011 101010 0100 d21.1 001 10101 101010 1001 101010 1001 d22.0 000 10110 011010 1011 011010 0100 d22.1 001 10110 011010 1001 011010 1001 d23.0 000 10111 111010 0100 000101 1011 d23.1 001 10111 111010 1001 000101 1001 d24.0 000 11000 110011 0100 001100 1011 d24.1 001 11000 110011 1001 001100 1001 d25.0 000 11001 100110 1011 100110 0100 d25.1 001 11001 100110 1001 100110 1001 d26.0 000 11010 010110 1011 010110 0100 d26.1 001 11010 010110 1001 010110 1001 d27.0 000 11011 110110 0100 001001 1011 d27.1 001 11011 110110 1001 001001 1001 d28.0 000 11100 001110 1011 001110 0100 d28.1 001 11100 001110 1001 001110 1001 d29.0 000 11101 101110 0100 010001 1011 d29.1 001 11101 101110 1001 010001 1001 d30.0 000 11110 011110 0100 100001 1011 d30.1 001 11110 011110 1001 100001 1001 d31.0 000 11111 101011 0100 010100 1011 d31.1 001 11111 101011 1001 010100 1001
CY7C954DX preliminary 37 d0.2 010 00000 100111 0101 011000 0101 d0.3 011 00000 100111 0011 011000 1100 d1.2 010 00001 011101 0101 100010 0101 d1.3 011 00001 011101 0011 100010 1100 d2.2 010 00010 101101 0101 010010 0101 d2.3 011 00010 101101 0011 010010 1100 d3.2 010 00011 110001 0101 110001 0101 d3.3 011 00011 110001 1100 110001 0011 d4.2 010 00100 110101 0101 001010 0101 d4.3 011 00100 110101 0011 001010 1100 d5.2 010 00101 101001 0101 101001 0101 d5.3 011 00101 101001 1100 101001 0011 d6.2 010 00110 011001 0101 011001 0101 d6.3 011 00110 011001 1100 011001 0011 d7.2 010 00111 111000 0101 000111 0101 d7.3 011 00111 111000 1100 000111 0011 d8.2 010 01000 111001 0101 000110 0101 d8.3 011 01000 111001 0011 000110 1100 d9.2 010 01001 100101 0101 100101 0101 d9.3 011 01001 100101 1100 100101 0011 d10.2 010 01010 010101 0101 010101 0101 d10.3 011 01010 010101 1100 010101 0011 d11.2 010 01011 110100 0101 110100 0101 d11.3 011 01011 110100 1100 110100 0011 d12.2 010 01100 001101 0101 001101 0101 d12.3 011 01100 001101 1100 001101 0011 d13.2 010 01101 101100 0101 101100 0101 d13.3 011 01101 101100 1100 101100 0011 d14.2 010 01110 011100 0101 011100 0101 d14.3 011 01110 011100 1100 011100 0011 d15.2 010 01111 010111 0101 101000 0101 d15.3 011 01111 010111 0011 101000 1100 d16.2 010 10000 011011 0101 100100 0101 d16.3 011 10000 011011 0011 100100 1100 d17.2 010 10001 100011 0101 100011 0101 d17.3 011 10001 100011 1100 100011 0011 d18.2 010 10010 010011 0101 010011 0101 d18.3 011 10010 010011 1100 010011 0011 d19.2 010 10011 110010 0101 110010 0101 d19.3 011 10011 110010 1100 110010 0011 d20.2 010 10100 001011 0101 001011 0101 d20.3 011 10100 001011 1100 001011 0011 d21.2 010 10101 101010 0101 101010 0101 d21.3 011 10101 101010 1100 101010 0011 d22.2 010 10110 011010 0101 011010 0101 d22.3 011 10110 011010 1100 011010 0011 d23.2 010 10111 111010 0101 000101 0101 d23.3 011 10111 111010 0011 000101 1100 d24.2 010 11000 110011 0101 001100 0101 d24.3 011 11000 110011 0011 001100 1100 d25.2 010 11001 100110 0101 100110 0101 d25.3 011 11001 100110 1100 100110 0011 d26.2 010 11010 010110 0101 010110 0101 d26.3 011 11010 010110 1100 010110 0011 d27.2 010 11011 110110 0101 001001 0101 d27.3 011 11011 110110 0011 001001 1100 d28.2 010 11100 001110 0101 001110 0101 d28.3 011 11100 001110 1100 001110 0011 d29.2 010 11101 101110 0101 010001 0101 d29.3 011 11101 101110 0011 010001 1100 d30.2 010 11110 011110 0101 100001 0101 d30.3 011 11110 011110 0011 100001 1100 d31.2 010 11111 101011 0101 010100 0101 d31.3 011 11111 101011 0011 010100 1100 table 8. valid data characters (txsc/d* = low, rxsc/d* = low) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
CY7C954DX preliminary 38 d0.4 100 00000 100111 0010 011000 1101 d0.5 101 00000 100111 1010 011000 1010 d1.4 100 00001 011101 0010 100010 1101 d1.5 101 00001 011101 1010 100010 1010 d2.4 100 00010 101101 0010 010010 1101 d2.5 101 00010 101101 1010 010010 1010 d3.4 100 00011 110001 1101 110001 0010 d3.5 101 00011 110001 1010 110001 1010 d4.4 100 00100 110101 0010 001010 1101 d4.5 101 00100 110101 1010 001010 1010 d5.4 100 00101 101001 1101 101001 0010 d5.5 101 00101 101001 1010 101001 1010 d6.4 100 00110 011001 1101 011001 0010 d6.5 101 00110 011001 1010 011001 1010 d7.4 100 00111 111000 1101 000111 0010 d7.5 101 00111 111000 1010 000111 1010 d8.4 100 01000 111001 0010 000110 1101 d8.5 101 01000 111001 1010 000110 1010 d9.4 100 01001 100101 1101 100101 0010 d9.5 101 01001 100101 1010 100101 1010 d10.4 100 01010 010101 1101 010101 0010 d10.5 101 01010 010101 1010 010101 1010 d11.4 100 01011 110100 1101 110100 0010 d11.5 101 01011 110100 1010 110100 1010 d12.4 100 01100 001101 1101 001101 0010 d12.5 101 01100 001101 1010 001101 1010 d13.4 100 01101 101100 1101 101100 0010 d13.5 101 01101 101100 1010 101100 1010 d14.4 100 01110 011100 1101 011100 0010 d14.5 101 01110 011100 1010 011100 1010 d15.4 100 01111 010111 0010 101000 1101 d15.5 101 01111 010111 1010 101000 1010 d16.4 100 10000 011011 0010 100100 1101 d16.5 101 10000 011011 1010 100100 1010 d17.4 100 10001 100011 1101 100011 0010 d17.5 101 10001 100011 1010 100011 1010 d18.4 100 10010 010011 1101 010011 0010 d18.5 101 10010 010011 1010 010011 1010 d19.4 100 10011 110010 1101 110010 0010 d19.5 101 10011 110010 1010 110010 1010 d20.4 100 10100 001011 1101 001011 0010 d20.5 101 10100 001011 1010 001011 1010 d21.4 100 10101 101010 1101 101010 0010 d21.5 101 10101 101010 1010 101010 1010 d22.4 100 10110 011010 1101 011010 0010 d22.5 101 10110 011010 1010 011010 1010 d23.4 100 10111 111010 0010 000101 1101 d23.5 101 10111 111010 1010 000101 1010 d24.4 100 11000 110011 0010 001100 1101 d24.5 101 11000 110011 1010 001100 1010 d25.4 100 11001 100110 1101 100110 0010 d25.5 101 11001 100110 1010 100110 1010 d26.4 100 11010 010110 1101 010110 0010 d26.5 101 11010 010110 1010 010110 1010 d27.4 100 11011 110110 0010 001001 1101 d27.5 101 11011 110110 1010 001001 1010 d28.4 100 11100 001110 1101 001110 0010 d28.5 101 11100 001110 1010 001110 1010 d29.4 100 11101 101110 0010 010001 1101 d29.5 101 11101 101110 1010 010001 1010 d30.4 100 11110 011110 0010 100001 1101 d30.5 101 11110 011110 1010 100001 1010 d31.4 100 11111 101011 0010 010100 1101 d31.5 101 11111 101011 1010 010100 1010 table 8. valid data characters (txsc/d* = low, rxsc/d* = low) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
CY7C954DX preliminary 39 d0.6 110 00000 100111 0110 011000 0110 d0.7 111 00000 100111 0001 011000 1110 d1.6 110 00001 011101 0110 100010 0110 d1.7 111 00001 011101 0001 100010 1110 d2.6 110 00010 101101 0110 010010 0110 d2.7 111 00010 101101 0001 010010 1110 d3.6 110 00011 110001 0110 110001 0110 d3.7 111 00011 110001 1110 110001 0001 d4.6 110 00100 110101 0110 001010 0110 d4.7 111 00100 110101 0001 001010 1110 d5.6 110 00101 101001 0110 101001 0110 d5.7 111 00101 101001 1110 101001 0001 d6.6 110 00110 011001 0110 011001 0110 d6.7 111 00110 011001 1110 011001 0001 d7.6 110 00111 111000 0110 000111 0110 d7.7 111 00111 111000 1110 000111 0001 d8.6 110 01000 111001 0110 000110 0110 d8.7 111 01000 111001 0001 000110 1110 d9.6 110 01001 100101 0110 100101 0110 d9.7 111 01001 100101 1110 100101 0001 d10.6 110 01010 010101 0110 010101 0110 d10.7 111 01010 010101 1110 010101 0001 d11.6 110 01011 110100 0110 110100 0110 d11.7 111 01011 110100 1110 110100 1000 d12.6 110 01100 001101 0110 001101 0110 d12.7 111 01100 001101 1110 001101 0001 d13.6 110 01101 101100 0110 101100 0110 d13.7 111 01101 101100 1110 101100 1000 d14.6 110 01110 011100 0110 011100 0110 d14.7 111 01110 011100 1110 011100 1000 d15.6 110 01111 010111 0110 101000 0110 d15.7 111 01111 010111 0001 101000 1110 d16.6 110 10000 011011 0110 100100 0110 d16.7 111 10000 011011 0001 100100 1110 d17.6 110 10001 100011 0110 100011 0110 d17.7 111 10001 100011 0111 100011 0001 d18.6 110 10010 010011 0110 010011 0110 d18.7 111 10010 010011 0111 010011 0001 d19.6 110 10011 110010 0110 110010 0110 d19.7 111 10011 110010 1110 110010 0001 d20.6 110 10100 001011 0110 001011 0110 d20.7 111 10100 001011 0111 001011 0001 d21.6 110 10101 101010 0110 101010 0110 d21.7 111 10101 101010 1110 101010 0001 d22.6 110 10110 011010 0110 011010 0110 d22.7 111 10110 011010 1110 011010 0001 d23.6 110 10111 111010 0110 000101 0110 d23.7 111 10111 111010 0001 000101 1110 d24.6 110 11000 110011 0110 001100 0110 d24.7 111 11000 110011 0001 001100 1110 d25.6 110 11001 100110 0110 100110 0110 d25.7 111 11001 100110 1110 100110 0001 d26.6 110 11010 010110 0110 010110 0110 d26.7 111 11010 010110 1110 010110 0001 d27.6 110 11011 110110 0110 001001 0110 d27.7 111 11011 110110 0001 001001 1110 d28.6 110 11100 001110 0110 001110 0110 d28.7 111 11100 001110 1110 001110 0001 d29.6 110 11101 101110 0110 010001 0110 d29.7 111 11101 101110 0001 010001 1110 d30.6 110 11110 011110 0110 100001 0110 d30.7 111 11110 011110 0001 100001 1110 d31.6 110 11111 101011 0110 010100 0110 d31.7 111 11111 101011 0001 010100 1110 table 8. valid data characters (txsc/d* = low, rxsc/d* = low) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
CY7C954DX preliminary 40 table 9. valid special character codes and sequences (txsc/d* = high or rxsc/d* = high) [26, 27] s.c. byte name s.c. code name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj k28.0 c0.0 [28] (c00) 000 00000 001111 0100 110000 1011 k28.1 c1.0 [29] (c01) 000 00001 001111 1001 110000 0110 k28.2 c2.0 [29] (c02) 000 00010 001111 0101 110000 1010 k28.3 c3.0 [28] (c03) 000 00011 001111 0011 110000 1100 k28.4 c4.0 [29] (c04) 000 00100 001111 0010 110000 1101 k28.5 c5.0 [29, 30] (c05) 000 00101 001111 1010 110000 0101 k28.6 c6.0 [29] (c06) 000 00110 001111 0110 110000 1001 k28.7 c7.0 [29, 31] (c07) 000 00111 001111 1000 110000 0111 k23.7 c8.0 [28] (c08) 000 01000 111010 1000 000101 0111 k27.7 c9.0 [28] (c09) 000 01001 110110 1000 001001 0111 k29.7 c10.0 [28] (c0a) 000 01010 101110 1000 010001 0111 k30.7 c11.0 (c0b) 000 01011 011110 1000 100001 0111 end of frame sequence eofxx c2.1 (c22) 001 00010 ? k28.5,dn.xxx0 [32] +k28.5,dn.xxx1 [32] code rule violation and svs tx pattern exception c0.7 [31] (ce0) 111 00000 100111 1000 [33] 011000 0111 [33] ? k28.5 c1.7 (ce1) 111 00001 001111 1010 [34] 001111 1010 [34] +k28.5 c2.7 (ce2) 111 00010 110000 0101 [35] 110000 0101 [35] running disparity violation pattern exception c4.7 (ce4) 111 00100 110111 0101 [36] 001000 1010 [36] notes: 26. all codes not shown are reserved. 27. notation for special character code name is consistent with fibre channel and escon naming conventions. special character co de name is intended to describe binary information present on i/o pins. common usage for the name can either be in the form used for describing data p atterns (i.e., c0.0 through c31.7), or in hex notation (i.e., cnn where nn = the specified value between 00h and ffh). 28. when received, these characters are discarded, but cause the rxsoc to be set high, along with various combinations of rxrvs and rxsc/d*. they can be explicitly sent by a transmitter using the txsc/d* and the appropriate data pattern, or by setting txsoc and various combina tions of txsvs and txsc/d*. 29. these characters are used for control of escon interfaces. they can be sent as embedded commands or other markers when not o perating using escon protocols. 30. the k28.5 character is used for framing operations by the receiver. it is also the pad or fill character transmitted to main tain the serial link when no user data is available and is discarded prior to loading into the receive fifo. 31. care must be taken when using this special character code. when a c7.0 is followed by a d11.x or d20.x, or when an svs (c0.7 ) is followed by a d11.x, and alias k28.5 sync character is created. these sequences can cause erroneous framing and should be avoided while rfen is high . 32. c2.1 = transmit either ? k28.5+ or +k28.5 ? as determined by current rd and modify the transmission character that follows, by setting its least significant bit to 1 or 0. if current rd at the start of the following character is plus (+) the lsb is set to 0, and if current rd is minu s ( ? ) the lsb becomes 1. this modification allows construction of special data sequences wherein the second data byte is determined by the current rd. for example, to send a fibre-channel ? eofdt ? the controller could issue the sequence c2.1 ? d21.4 ? d21.4 ? d21.4, and the hotlink transmitter will send either k28.5 ? d21.4 ? d21.4 ? d21.4 or k28.5 ? d21.5 ? d21.4 ? d21.4 based on current rd. likewise to send ? eofdti ? the controller could issue the sequence c2.1 ? d10.4 ? d21.4 ? d21.4, and the hotlink transmitter will send either k28.5 ? d10.4 ? d21.4 ? d21.4 or k28.5 ? d10.5 ? d21.4 ? d21.4 based on current rd. the receiver will never output this special character, since k28.5 is decoded as c5.0 (which is discarded), c1.7, or c2.7 (both of which are accompanied by an rxrvs error indication), and the subsequent bytes are decoded as data. 33. c0.7 = transmit a deliberate code rule violation. the code chosen for this function follows the normal running disparity rul es. transmission of this special character has the same effect as asserting txsvs = high. the receiver will only output this special character if the transmissi on character being decoded is not found in the tables. 34. c1.7 = transmit negative k28.5 ( ? k28.5+) disregarding current rd. the receiver will only output this special character if k28.5 is received with the wrong running disparity. the receiver will output c1.7 if ? k28.5 is received with rd+, otherwise k28.5 is discarded or decoded as c2.7. 35. c2.7 = transmit positive k28.5 (+k28.5 ? ) disregarding current rd. the receiver will only output this special character if k28.5 is received with the wrong running disparity. the receiver will output c2.7 if +k28.5 is received with rd ? , otherwise k28.5 is discarded or decoded as c1.7. 36. c4.7 = transmit a deliberate code rule violation to indicate a running disparity violation. the receiver will only output th is special character if the transmission character being decoded is found in the tables, but running disparity does not match. this might indicate that an error occurre d in a prior byte.
CY7C954DX preliminary 41 printed circuit board layout suggestions this is a typical printed circuit board layout showing example placement of power supply bypass components and other components mounted on the same side as the CY7C954DX. other layouts, including cases with components mounted on the reverse side would work as well. outa+ outb+ inb+ ina+ refclk curseta resistor cursetb resistor rxsc/d reset 0.01 f mlc x7r 1206 chip cap (2 sites) power supply bypass 0.01 f mlc x7r 1206 chip cap (4 sites) power supply bypass 0.01 f mlc x7r power supply bypass 0.01 f mlc x7r power supply bypass 0.01 f mlc x7r power supply bypass via to v dd plane via to v ss plane CY7C954DX-ac
CY7C954DX preliminary ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document #: 38-00812-a ordering information ordering code package name package type operating range CY7C954DX-ac a100 100-lead thin quad flat pack commercial package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b

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