features ? 10-bit resolution adc 2.2 gsps sampling rate seamless ascending compatib ility with atmel ts83102g0b 10-bit 2 gsps adc 500 mvpp full scale analog input range 100 ? differential or 50 ? single-ended analog input and clock input 100 ? differential outputs ecl/lvds output compatibility functions: ? adc gain adjust and sampling delay adjust ? data ready output with asynchronous reset ? out-of-range output bit power consumption: 4.2w power supplies: ? analog: -5v, 5v ? digital: -5v to -2.2v and 1.5v radiation tolerant (to be confirmed) package: cbga152 cavity down hermetic package evaluation board AT84AS008gl-eb companion device: ? dmux 8/10 bit 1:2/1:4 lvds 2.2 gsps at84cs001 performances ? 3.3 ghz full power input bandwidth (-3 db) ? gain flatness: 0.2 db (from dc up to 1.5 ghz) ? low input vswr: 1.2 maxi mum from dc to 2.5 ghz ? single tone performances (- 1dbfs): sfdr = -56 dbc; 8.0 enob; snr = 52 dbc at f s = 1.7 gsps, f in = 850 mhz sfdr = -55 dbc; 7.7 enob; snr = 51 dbc at f s = 2.2 gsps, f in = 1.1 ghz sfdr = -55 dbc, 7.3 enob; snr = 48 dbc at f s = 2.2 gsps, f in = 2 ghz ? dual tone performances (imd3), fs = 1.7 gps, (-7dbfs tone): (fin1= 995 mhz, fin2 = 1005 mhz): imd3 = 60 dbf s (fin1= 1545 mhz, fin2 = 1555 mhz): imd3 = 60 dbf s (fin1= 1945 mhz, fin2 = 1955 mhz): imd3 = 57 dbf s ? low bit error rate (10 -11 ) at 2.2 gsps screening ? temperature range for packaged device: 0c < t c ; t j < 90c (commercial ?c? grade) -20c < t c ; t j < 110c (industrial ?v? grade) applications ? broadband direct rf down conversion ? wide band satellite receivers ? phased array antennas, radars and ecm ? high-speed instrumentation and high speed acquisition systems ? high energy physics ? automatic test equipment adc 10-bit 2.2 gsps AT84AS008 summary 5404as?bdc?05/05 note: this is a summary docu ment. a complete document is not available at this time. for more information, please contact your local atmel sales office.
2 5404as?bdc?05/05 1. description the AT84AS008 10-bit 2.2 gsps adc allows accu rate digitization of high frequency signals thanks to the 3.3 ghz analog input bandwidth. the innovative design of the on-chip track and hold (t/h) and digitizing core lead to unprece- dented dynamic performance at a sampling rate of 2.2 ghz (over the full first nyquist zone). a 7.7 enob is achieved at 2.2 gps in nyquist c onditions using gray encoded digital outputs for optimum snr performance. the AT84AS008 features an enhanced spectral purity and a very low noise floor, independent on frequency and temperature. it is particularly well suited for performance enhancements (i.e., dithering). the AT84AS008 is fully compatible with at mel?s ts83102g0b 10-bit 2 gsps adc, allowing zero-effort system improvement by plug-and-play replacement with the new part. figure 1-1. block diagram 2. functional description the AT84AS008 is a 10-bit 2.2 gsps adc. t he device includes a front-end track and hold stage (t/h), followed by an analog encoding stage (analog quantizer) which outputs analog residues resulting from analog quantization. successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuitry and a resynchronization stage followed by 100 ? differential output buffers. the AT84AS008 works in fully differential mode from the analog inputs up to the digital outputs. a differential data ready output (dr/drb) is available to indicate when the outputs are valid and an asynchronous data ready reset ensures th at the first digitized data corresponds to the first acquisition. for sampling rates exceeding 2 gsps, the gray output encoding is recommended for optimum snr performance. track & hold clock generation logic block analog quantizer vin vinb clk clkb pgeb b/gb drrb or orb d9 d9b d0 d0b ga dr drb 50 50 50 50 sda sda decb/ diode
3 5404as?bdc?05/05 the control pin b/gb (a11 of the cbga package) is provided to select either a binary or gray data output format. the gain control pin ga (r9 of the cbga package) is provided to adjust the adc gain transfer function. a sampling delay adjust function (sda) is provided to fine tune the adc aperture delay, for applications requesting the interleaving of multiple adcs for example. a pattern generator is integrated on-chip for debug or acquisition set-up. this function is enabled through the pgeb pin (a9 of the cbga package). an out-of-range bit (or/orb) indicates when the input overrides 0.5 vpp. a selectable decimation by 32 function is also available for enhanced te stability coverage (a10 of the cbga package) along with a die ju nction temperature monitoring function. the AT84AS008 uses only vertical isolated npn transistors together with oxide isolated polysili- con resistors, which allow enhanced radiation tolerance (over 100krad (si) expected total dose). the AT84AS008 provides full ascending co mpatibility with the ts83102g0b with enhanced performances. 3. package description figure 3-1. hermetic cbga 152 outline dimensions (bottom view) pin a1 index (no ball) 152 x o d = 0.80 +/- 0.10 mm 0.20 t a b (position of column array/ref a and b) 0.15 t (position of balls within array) 1 chamfer 0.4 (x4) metallic cap 9.27 x 9.27 mm 1.27 mm pitch 21.00 mm +/- 0.20 a 21.00 mm +/- 0.20 b a
4 5404as?bdc?05/05 4. ordering information part number package temperature range screening level comments at84xas008gl cbga152 ambient prototype please contact your local atmel sales office AT84AS008cgl cbga152 commercial ?c? grade 0 c < t c , t j < 90 c standard AT84AS008vgl cbga152 industrial ?v? grade -20 c < t c , t j < 110 c standard AT84AS008gl-eb cbga152 ambient prototype evaluation board (delivered with a heat sink)
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