View NCP5331FTR2G_5959487.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2005 march, 2005 ? rev. 12 1 publication order number: ncp5331/d ncp5331 two-phase pwm controller with integrated gate drivers the ncp5331 is a second?generation, two?phase, buck controller that incorporates advanced control functions to power 64?bit amd athlon processors and low voltage, high current power supplies. proprietary multiphase architecture guarantees balanced load?current sharing, reduces output voltage and input current ripple, decreases filter requirements and inductor values, and increases output current slew rate. traditional enhanced v 2 has been combined with an internal pwm ramp and voltage feedback directly from v core to the internal pwm comparator. these features and enhancements deliver the fastest transient response, reduce output voltage jitter, provide greater design flexibility and portability, and minimize overall solution cost. advanced features include adjustable power?good delay, programmable overcurrent shutdown timer, superior overvoltage protection (ovp), and differential remote sensing. an innovative overvoltage protection (ovp) scheme safeguards the cpu during extreme situations including power up with a shorted upper mosfet, shorting of an upper mosfet during normal operation, and loss of the voltage feedback signal, corefb+. features ? reduced smt package size (7 mm 7 mm) ? enhanced v 2 control method ? four on?board gate drivers ? internal pwm ramps ? differential remote voltage sense ? fast feedback pin (v ffb ) ? 5?bit dac with 0.8% system tolerance ? timed hiccup mode current limit ? power good output with programmable delay ? advanced overvoltage protection (ovp) ? adjustable output voltage positioning ? 150 khz to 600 khz operation set by resistor ? alosslesso current sensing through output inductors ? independent current sense amplifiers ? 5.0 v, 2 ma reference output ? pb?free package is available* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com a = assembly location wl = wafer lot yy = year ww = work week x = g or marking diagrams lqfp?32 ft suffix case 873a ncp5331 awlyywwx ordering information ncp5331ftr2 lqfp?32 2000 tape & reel device package shipping 2 32 1 *pb?free indicator, ago or microdot a o, may or may not be present. NCP5331FTR2G lqfp?32 (pb?free) 2000 tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
ncp5331 http://onsemi.com 2 pin connections gl1 gnd1 gh1 cb out v cch gh2 gnd2 gl2 comp i lim 5 v sb pgd c pgd c ovc v ccl v ccl1 r osc ?sen v id0 v id1 v id2 v id3 v id4 v ccl2 v fb v drp lgnd cs1 cs ref cs2 v ffb 5 v ref 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 lqfp?32
ncp5331 http://onsemi.com 3 figure 1. application diagram, 12 v to 1.2 v at 52 a, 200 khz for 64?bit amd athlon processor recommended components: q1, q4: on semiconductor ntd60n03 (60 a, 28 v, 6.1 m ) q5 - q9: on semiconductor ntd80n02 (80 a, 24 v, 5.0 m ) l1, l2: coiltronics ctx22?15274 or t50?8b/90 w/ 6 t of #16 awg bifilar (1 m ) l3: coiltronics ctx15?14771 or t30?26 w/ 3 t of #16 awg c in : 5 rubycon 16mbz1500m10x20 (1500 f, 16 v, 2.55 a rms ) co1: 10 rubycon 16mbz1000m10x16 (1000 f, 16 v, 19 m ) co2: 24 tdk c2012x5r0j106m (10 f, 6.3 v, 0805) co3: 16 tdk c1608x5r1a224kt (0.22 f, 10 v, 0603) co4: 2 sanyo poscap 6tpd330m (330 f, 6.3 v, 10 m , 4.4 a rms ) v fb v drp lgnd cs1 cs ref cs2 v ffb 5 v ref gl1 gnd1 gh1 cb out v cch gh2 gnd2 gl2 r osc ?sen v id0 v id1 v id2 v id3 v id4 v ccl2 comp i lim 5 v sb pgd c pgd c ovc v ccl v ccl1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 ncp5331 r osc 51 k v id0 v id2 v id4 v id1 v id3 cl 1.0 f cs1 0.11 f cs2 0.1 f lgnd ties to pgnd at 1 point c ffb 0.01 f r lim2 910 i lim csa 0.1 f rs 1.87 k r drp 14.7 k rf1 3.6 k cf1 1.0 nf ca1 0.01 f cc2 0.1 f rc1 7.5 k cc1 2.2 nf pgd 5 v sb i lim c ovc 0.22 f c pgd 0.022 f c vcc 1.0 f +12 v r1 15 r2 910 d1 7.5 v, 5% bzx84c7v5lt3 7.0 v d3 d2 c2 0.33 f q7 q8 + c in rs2 10 k rs1 10 k swnode2 swnode1 l1 825 nh l2 825 nh co3 + co1 v core corefb+ v core r3 56 csb 470 pf r lim1 2.37 k c ref 0.1 f corefb# v core r4 56 rcb 6.2 k ccb 1.0 f d4 bat54clt1 12 v 5 v sb co2 + co4 q9 r7 2 c4 4700 pf q4 cp2 1.0 f q5 q6 r6 2 c3 4700 pf q1 cp1 1.0 f l3 300 nh +12 v pwr ch 1.0 f c 5vsb 0.1 f +12 v r5 3 c1 10 f q7 mmbt2132lt3 1.0 m
ncp5331 http://onsemi.com 4 maximum ratings* rating value unit operating junction temperature 150 c lead temperature soldering smd reflow profile (60 seconds maximum) 230 183 c peak c storage temperature range ?65 to 150 c package thermal resistance: junction?to?ambient, r ja 52 c/w esd susceptibility (human body model) 2.0 kv jedec moisture sensitivity tbd ? *the maximum package power dissipation must be observed. maximum ratings pin symbol v max v min i source i sink comp 6.0 v ?0.3 v 1.0 ma 1.0 ma v fb 6.0 v ?0.3 v 1.0 ma 1.0 ma v drp 6.0 v ?0.3 v 1.0 ma 1.0 ma cs1, cs2 6.0 v ?0.3 v 1.0 ma 1.0 ma cs ref 6.0 v ?0.3 v 1.0 ma 1.0 ma r osc 6.0 v ?0.3 v 1.0 ma 1.0 ma pgd 6.0 v ?0.3 v 1.0 ma 8.0 ma vid pins 6.0 v ?0.3 v 1.0 ma 1.0 ma i lim 6.0 v ?0.3 v 1.0 ma 1.0 ma 5 v ref 6.0 v ?0.3 v 1.0 ma 20 ma cb out 13.2 v ?0.3 v 1.0 ma 4.0 ma c pgd 6.0 v ?0.3 v 1.0 ma 1.0 ma c ovc 6.0 v ?0.3 v 1.0 ma 1.0 ma v ccl 16 v ?0.3 v n/a 50 ma v cch 20 v ?0.3 v n/a 1.5 a for 1.0 s, 200 ma dc v cclx 16 v ?0.3 v n/a 1.5 a for 1.0 s, 200 ma dc 5 v sb 6.0 v ?0.3 v n/a 1.0 ma ghx 20 v ?2.0 v for 100 ns, ?0.3 v dc 1.5 a for 1.0 s, 200 ma dc 1.5 a for 1.0 s, 200 ma dc glx 16 v ?2.0 v for 100 ns, ?0.3 v dc 1.5 a for 1.0 s, 200 ma dc 1.5 a for 1.0 s, 200 ma dc gnd1, gnd2 0.3 v ?0.3 v 2.0 a for 1.0 s, 200 ma dc n/a lgnd 0 v 0 v 50 ma n/a ?sen 0.3 v ?0.3 v 1.0 ma 1.0 ma
ncp5331 http://onsemi.com 5 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v ccl < 16 v; 9.0 v < v cch < 20 v; 9.0 v < v ccl1 = v ccl2 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k , c comp = 1.0 nf, c 5v(ref) = 0.1 f, dac code 01110 (1.2 v), c vcc = 1.0 f, 0.25 v i lim 1.0 v; unless otherwise noted) characteristic test conditions min typ max unit voltage identification dac voltage identification (vid) codes measure v = comp sen = lgnd v id4 v id3 v id2 v id1 v id0 measure v fb = comp, ?sen = lgnd 0 0 0 0 0 ? ? 1.550 ? v 0 0 0 0 1 ? ? 1.525 ? v 0 0 0 1 0 ? ? 1.500 ? v 0 0 0 1 1 ? ? 1.475 ? v 0 0 1 0 0 ? ? 1.450 ? v 0 0 1 0 1 ? ? 1.425 ? v 0 0 1 1 0 ? ? 1.400 ? v 0 0 1 1 1 ? ? 1.375 ? v 0 1 0 0 0 ? ? 1.350 ? v 0 1 0 0 1 ? ? 1.325 ? v 0 1 0 1 0 ? ? 1.300 ? v 0 1 0 1 1 ? ? 1.275 ? v 0 1 1 0 0 ? ? 1.250 ? v 0 1 1 0 1 ? ? 1.225 ? v 0 1 1 1 0 ? ? 1.200 ? v 0 1 1 1 1 ? ? 1.175 ? v 1 0 0 0 0 ? ? 1.150 ? v 1 0 0 0 1 ? ? 1.125 ? v 1 0 0 1 0 ? ? 1.100 ? v 1 0 0 1 1 ? ? 1.075 ? v 1 0 1 0 0 ? ? 1.050 ? v 1 0 1 0 1 ? ? 1.025 ? v 1 0 1 1 0 ? ? 1.000 ? v 1 0 1 1 1 ? ? 0.975 ? v 1 1 0 0 0 ? ? 0.950 ? v 1 1 0 0 1 ? ? 0.925 ? v 1 1 0 1 0 ? ? 0.900 ? v 1 1 0 1 1 ? ? 0.875 ? v 1 1 1 0 0 ? ? 0.850 ? v 1 1 1 0 1 ? ? 0.825 ? v 1 1 1 1 0 ? ? 0.800 ? v 1 1 1 1 1 ? shutdown v system accuracy percent deviation from programmed vid codes ?0.8 ? 0.8 % shutdown time delay vid = 1 1111 5.0 10 15 s input threshold v id0 ?v id4 1.00 1.25 1.50 v vid pin bias current v id0 ?v id4 12 25 40 a vid pin clamp voltage ? ? 2.3 2.6 v
ncp5331 http://onsemi.com 6 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v ccl < 16 v; 9.0 v < v cch < 20 v; 9.0 v < v ccl1 = v ccl2 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k , c comp = 1.0 nf, c 5v(ref) = 0.1 f, dac code 01110 (1.2 v), c vcc = 1.0 f, 0.25 v i lim 1.0 v; unless otherwise noted) characteristic test conditions min typ max unit voltage identification dac (continued) ?sen bias current lgnd < 55 mv, all dac codes 40 80 120 a ?sen offset from gnd ? ?150 ? 200 mv power good output internal delay time ? 175 290 425 s pwrgd low output voltage i pgd = 4.0 ma ? 250 400 mv output leakage current v pgd = 5.5 v ? 0.1 2.0 a v core /cs ref comparator threshold voltage tolerance from dac setting ?15% ?12.5% ?10% % c pgd charge current r osc = 32.4 k 14.5 16 17.5 a c pgd comparator threshold voltage ? 2.8 3.0 3.2 v c pgd external delay time c pgd = 0.033 f. note 1. 4.8 6.0 7.8 ms voltage feedback error amplifier v fb bias current 0.7 v < v fb < 1.6 v. note 2. 9.4 10.3 11.1 a comp source current comp = 0.5 v to 2.0 v; v fb = 0.8 v 15 30 60 a comp sink current comp = 0.5 v to 2.0 v; v fb = 1.5 v 15 30 60 a comp discharge threshold voltage ? 0.20 0.33 0.40 v transconductance ?10 a < i comp < +10 a ? 32 ? mmho output impedance ? ? 2.5 ? m open loop dc gain note 1. 60 90 ? db unity gain bandwidth c comp = 0.01 f ? 400 ? khz psrr @ 1.0 khz ? ? 70 ? db comp max voltage v fb = 0.8 v, comp open 4.1 4.4 ? v comp min voltage v fb = 1.5 v, comp open ? 0.1 0.2 v hiccup latch discharge current ? 4.0 7.5 13 a hiccup latch charge/discharge ratio ? ? 4.0 ? ? pwm comparators minimum pulse width cs1 = cs2 = cs ref ? 235 280 ns channel start?up offset cs1 = cs2 = v fb = cs ref = 0 v; measure comp when ghx switch high 0.45 0.60 0.80 v overcurrent shutdown timer overcurrent shutdown voltage threshold ? 2.8 3.0 3.2 v c ovc low output voltage ? ? 250 400 mv c ovc source current ? 3.0 5.0 8.0 a 1. guaranteed by design. not tested in production. 2. the v fb bias current changes with the value of r osc per figure 5.
ncp5331 http://onsemi.com 7 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v ccl < 16 v; 9.0 v < v cch < 20 v; 9.0 v < v ccl1 = v ccl2 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k , c comp = 1.0 nf, c 5v(ref) = 0.1 f, dac code 01110 (1.2 v), c vcc = 1.0 f, 0.25 v i lim 1.0 v; unless otherwise noted) characteristic unit max typ min test conditions overcurrent shutdown timer (continued) overcurrent shutdown time c ovc = 0.22 f. note 3. 65 120 230 ms internal overvoltage protection (ovp) overvoltage threshold lgnd = 0 v, v fb = 0 v, cs ref = 0 v, increase cs ref until gl1 and gl2 switch high. 2.0 2.1 2.2 v external overvoltage protection (cb out ) overvoltage positive threshold 5 v sb = 5.0 v, lgnd = 0 v, cs ref = 0 v, increase cs ref until cb out = high. 2.0 2.1 2.2 v overvoltage negative threshold 5 v sb = 5.0 v, lgnd = 0 v, cs ref = 3.0 v, decrease cs ref until cb out = low. 0.8 0.9 1.0 v cb out maximum allowable sink current ? ? ? 2.0 ma cb out low voltage 6.6 k pull?up to 13.2 v ? ? 0.4 v gate drivers high voltage (ac) measure v cclx ? glx or v cchx ? ghx. note 3. ? 0 1.0 v low voltage (ac) measure glx or ghx. note 3. ? 0 0.5 v rise time ghx 1.0 v < ghx < 8.0 v; v cch = 10 v ? 35 80 ns rise time glx 1.0 v < glx < 8.0 v; v cclx = 10 v ? 35 80 ns fall time ghx 8.0 v > ghx > 1.0 v; v cch = 10 v ? 35 80 ns fall time glx 8.0 v > glx > 1.0 v; v cclx = 10 v ? 35 80 ns ghx to glx delay ghx < 2.0 v, glx > 2.0 v 30 65 110 ns glx to ghx delay glx < 2.0 v, ghx > 2.0 v 30 65 110 ns gate pull?down force 100 a into gate with no power applied to v cch and v cclx = 2.0 v. ? 1.2 1.6 v oscillator switching frequency r osc = 32.4 k 255 300 345 khz switching frequency r osc = 63.4 k; note 3. 110 150 190 khz switching frequency r osc = 16.2 k; note 3. 450 600 750 khz r osc voltage ? ? 1.0 ? v phase delay ? 165 180 195 deg adaptive voltage positioning v drp output voltage to dac out offset cs1 = cs2 = cs ref , v fb = comp, measure v drp ? comp 6 mv maximum v drp voltage 10 mv (cs1 = cs2) ? cs ref 50 mv, v fb = comp, measure v drp ? comp 300 400 500 mv current sense amp to v drp gain 10 mv (cs1 = cs2) ? cs ref 50 mv v fb = comp, measure v drp ? comp 3.9 4.2 4.75 v/v 3. guaranteed by design. not tested in production.
ncp5331 http://onsemi.com 8 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v ccl < 16 v; 9.0 v < v cch < 20 v; 9.0 v < v ccl1 = v ccl2 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k , c comp = 1.0 nf, c 5v(ref) = 0.1 f, dac code 01110 (1.2 v), c vcc = 1.0 f, 0.25 v i lim 1.0 v; unless otherwise noted) characteristic unit max typ min test conditions current sensing cs1?cs2 input bias current csx = cs ref = 0 v ? 0.1 0.5 a cs ref input bias current csx ? cs ref = 50 mv ? 0.35 1.5 a v ffb pull?up resistor ? 80 110 145 k current sense amplifier gain csx ? cs ref = 40 mv 1.85 2.1 2.35 v/v current sense input to i lim gain i lim = 1.00 v 9.5 12 14 v/v current limit filter slew rate ? 4.0 7.0 13 mv/ s i lim operating voltage range note 4. ? ? 3.0 v i lim bias current 0 < i lim < 1.0 v ? 0.1 1.0 a current sense amplifier bandwidth note 4. 1.0 ? ? mhz general electrical specifications v ccl operating current v fb = comp (no switching) ? 22 26 ma v ccl1 or v ccl2 operating current v fb = comp (no switching) ? 5.0 10 ma v cch operating current v fb = comp (no switching) ? 6.4 9.0 ma 5 v sb quiescent current cb out = low ? ? 400 a v ccl start threshold gates switching, comp charging 8.1 8.5 8.9 v v ccl stop threshold gates stop switching, comp discharging 5.75 6.15 6.55 v v ccl hysteresis gates not switching, comp not charging 2.05 2.35 2.65 v v cch start threshold gates switching, comp charging 8.1 8.5 8.9 v v cch stop threshold gates stop switching, comp discharging 6.35 6.75 7.15 v v cch hysteresis gates not switching, comp not charging 1.45 1.75 2.05 v reference output 5 v ref output voltage 0 ma < i(5 v ref ) < 1.0 ma 4.85 5.0 5.15 v internal ramp ramp height @ 50% pwm duty cycle cs1 = cs2 = cs ref ? 125 ? mv 4. guaranteed by design. not tested in production.
ncp5331 http://onsemi.com 9 package pin description pin no. symbol description 1 v fb voltage feedback pin. to use adaptive voltage positioning (avp), set the light load offset voltage by connecting a resistor between v fb and v core . the resistor and the v fb bias current determine the offset. for no adaptive positioning connect v fb directly to v core . 2 v drp current sense output for adaptive voltage positioning (avp). the offset of this pin above the dac voltage is proportional to the output current. connect a resistor from this pin to v fb to set the amount avp or leave this pin open for no avp. this pin's maximum working voltage is 4.1 vdc. 3 lgnd return for the internal control circuits and the ic substrate connection. 4, 6 cs1, cs2 current sense inputs. connect the current sense network for the corresponding phase to each in- put. the input voltages to these pins must be kept within 125 mv of cs ref . 5 cs ref reference for both differential current sense amplifiers. to balance input offset voltages between the inverting and non?inverting inputs of the current sense amplifiers, connect this pin to the output voltage through a resistor equal to one third of the value of the current sense resistors. 7 v ffb fast feedback connection to the pwm comparators and input to the power good comparator. 8 5 v ref reference output. decouple to lgnd with 0.1 f. 9 r osc a resistor from this pin to ground sets the operating frequency and v fb bias current. 10 ?sen ground connection for the dac. provides remote sensing of ground at the load. 11?15 vid pins voltage id dac inputs. these pins are internally pulled up and clamped at 2.3 v if left unconnected. 16 v ccl2 power for gl2. 17 gl2 low side driver #2. 18 gnd2 return for driver #2. 19 gh2 high side driver #2. 20 v cch power for gh1 and gh2. 21 cb out open?collector crowbar output pin. this pin is high impedance when an overvoltage condition is detected at cs ref . connect this pin to the gate of a mosfet or scr to crowbar either v core or v in to gnd. to prevent failure of the crowbar device, this pin should be used in conjunction with logic on the motherboard to disable the atx supply via ps on and/or a relatively fast fuse should be placed upstream to disconnect the input voltage. 22 gh1 high side driver #1. 23 gnd1 return for driver #1. 24 gl1 low side driver #1. 25 v ccl1 power for gl1. 26 v ccl power for the internal control circuits. uvlo sense for logic connects to this pin. 27 c ovc a capacitor from this pin to ground sets the time the controller will be in hiccup mode current limit. this timer is started by the first overcurrent condition (set by the i lim voltage). once timed out, volt- age at the v ccl pin must be cycled to reset this fault. connecting this pin to lgnd 200 mv will disable this function and hiccup mode current limit will operate indefinitely. 28 c pgd a capacitor from this pin to ground sets the programmable time between when v core crosses the pwrgd threshold and when the open?collector pwrgd pin transitions from a logic low to a logic high. the minimum delay is internally set to 200 s. connecting this pin to 5 v ref will disable the programmable timer and the delay will be set to the internal delay. 29 pgd power good output. open collector output that will transition low when cs ref (v core ) is out of regulation. 30 5 v sb input power for the cb out circuitry. to provide maximum overvoltage protection to the cpu, this pin should be connected to 5 v sb from the atx supply (atx, pin 9). if the cb out function is not used, this pin must be connected to the ncp5331 controller's internal voltage reference (5 v ref , pin 8). 31 i lim sets the threshold for current limit. connect to reference through a resistive divider. this pin's maxi- mum working voltage is 3.0 vdc. 32 comp output of the error amplifier and input for the pwm comparators.
ncp5331 http://onsemi.com 10 figure 2. block diagram, control functions + ? v id0 v id1 v id2 v id3 v id4 5?bit dac out 11111 5.0 v ref v ccl 5.0 v ref v fb current gen r osc osc lgnd cs ref ph1 ph2 ? + error amp comp 11111 shutdown v fb_bias ? + cs1 cs2 g csa1 2.0 g csa2 2.0 g vdrp 2.0 su offset 0.6 v + ramp1 + ramp2 v drp delay 10 s ?sen dac out osc ibias + + i total ph1 current ph2 current v ffb 100 k 5.0 v ref ? + ? + + ? pwmc1 s r reset dominant q q d f/f non?overlap gate driver ph1 v cch gh1 v ccl1 gl1 gnd1 s r reset dominant q q d f/f non?overlap gate driver ph2 gh2 v ccl2 gl2 gnd2 pwmc2 fault comp_lo dac out ? + 12.5% of dac + ? cs ref pgd comparator c pgd 7.5 a pgd no delay 1 = on + ? + ? 3.0 v/0.5 v ext delay 5.0 v ref 15 a int. delay 200 s pgd pgd uvlo over over fault 7.5 a 1 = on comp discharge
ncp5331 http://onsemi.com 11 figure 3. block diagram, protection + ? cs ref g ilim 6.0 ? + ? + slew rate limit i lim current limit v ccl fault v ccl + ? start stop 8.50 v 6.15 v ? + v cch fault v cch + ? start stop 8.50 v 6.75 v s r set dominant q q d f/f 5.0 a 2.05 v/0.75 v external crowbar + ? + ? 2.0v internal crowbar overvoltage overcurrent s r reset dominant q q d f/f over uvlo overcurrent and overvoltage latch + ? + ? 3.0v ovc timer 5.0 v ref pgd i total uvlo overcurrent uvlo s r set dominant q q d f/f fault latch fault 11111 shutdown ? + comp reset comp + ? comp_lo 0.27 v comp discharge threshold 5 v sb cb out c ovc
ncp5331 http://onsemi.com 12 + ? 5.0 v 25 a 1.65 v v id0 ?v id4 figure 4. simplified vid pin input circuitry 0.65 v ncp5331 controller hi or lo typical performance characteristics figure 5. oscillator frequency vs. r osc value figure 6. v fb current vs. r osc value 10 v fb bias current, a 0 r osc value, k 5 10 15 20 25 20 30 40 50 60 70 80 10 frequency (khz) 100 r osc (k) 300 350 400 450 500 550 600 20 30 40 50 70 150 200 250 60 maximum frequency (khz) 200 v core (v) 300 350 400 450 500 550 600 250 0.800 0.850 0.900 0.950 1.000 1.050 1.100 1.150 1.200 1.250 1.300 1.350 1.400 1.450 1.500 1.550 v source = 12 v minimum ncp5331 pulse width = 280 ns figure 7. maximum frequency vs. v core 650 v source = 5 v
ncp5331 http://onsemi.com 13 typical performance characteristics temperature ( c) v dp (mv) 10 20 30 40 50 60 70 0 ?5 0 5 10 15 20 25 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 temperature ( c) 5.0 v ref (v) 5.00 5.05 5.10 5.15 4.85 4.90 4.95 010203040506070 9.4 9.6 9.8 10.0 10.2 10.4 10.6 10.8 11.0 figure 8. csa to v drp gain vs. temperature figure 9. 5.0 v ref output voltage vs. temperature figure 10. csa to i lim gain vs. temperature figure 11. v drp output to dac out offset vs. temperature 10 11 12 13 14 15 figure 12. v fb bias current vs. temperature temperature ( c) gain (v/v) 4.2 4.3 4.4 4.5 4.6 4.7 4.8 3.9 4.0 4.1 010203040506070 temperature ( c) gain (v/v) 10 20 30 40 50 60 70 0 i fb ;( a) 10 20 30 40 50 60 70 0 temperature ( c) v core percent of dac (%) 10 20 30 40 50 60 70 0 temperature ( c) figure 13. pgd threshold vs. temperature
ncp5331 http://onsemi.com 14 applications information overview the ncp5331 dc/dc controller utilizes an enhanced v 2 topology to meet requirements of low voltage, high current loads with fast transient requirements. transient response has been improved and voltage jitter virtually eliminated by including an internal pwm ramp, connecting fast?feedback from v core directly to the internal pwm comparator, and precise routing and grounding inside the controller. advanced features such as adjustable power?good delay, programmable overcurrent shutdown time, superior overvoltage protection (ovp), and differential remote voltage sensing make it easy to obtain amd certification. an innovative overvoltage protection (ovp) scheme safeguards the cpu during extreme situations including power up with a shorted upper mosfet, shorting of an upper mosfet during normal operation, and loss of the voltage feedback signal, corefb+. the ncp5331 provides a afully integrated solutiono to simplify design, minimize circuit board area, and reduce overall system cost. two advantages of a multiphase converter over a single?phase converter are current sharing and increased apparent output frequency. current sharing allows the designer to use less inductance in each phase than would be required in a single?phase converter. the smaller inductor produces lar ger ripple currents but the total per phase power dissipation is reduced because the rms current is lower. transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. increased apparent output frequency is desirable because the of f?time and the ripple voltage of the two?phase converter will be less than that of a single?phase converter. fixed frequency multiphase control in a multiphase converter, multiple converters are connected in parallel and are switched on at different times. this reduces output current from the individual converters and increases the apparent ripple frequency. because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. the ncp5331 controller uses a two?phase, fixed frequency, enhanced v 2 architecture to measure and control currents in individual phases. each phase is delayed 180 from the previous phase. normally, ghx (x = 1 or 2) transitions to a high voltage at the beginning of each oscillator cycle. inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the pwm comparator and bring ghx low. once ghx goes low, it will remain low until the beginning of the next oscillator cycle. while ghx is high, the enhanced v 2 loop will respond to line and load variations (i.e. the upper gate on?time will be increased or reduced as required). on the other hand, once ghx is low, the loop can not respond until the beginning of the next pwm cycle. therefore, constant frequency enhanced v 2 will typically respond to disturbances within the off?time of the converter. the enhanced v 2 architecture measures and adjusts the output current in each phase. an additional input, csx (x = 1 or 2), for inductor current information has been added to the v 2 loop for each phase as shown in figure 14. the triangular inductor current is measured differentially across rs, amplified by csa and summed with the channel startup offset, the internal ramp, and the output voltage at the noninverting input of the pwm comparator. the purpose of the internal ramp is to compensate for propagation delays in the ncp5331. this provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation, and pwm duty cycles above 50% without external slope compensation. as the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the pwm comparator rises and terminates the pwm cycle. if the inductor starts a cycle figure 14. enhanced v 2 control employing resistive current sensing and additional internal ramp + ? swnode lx rlx rsx csx csa con cs ref + v out (v core ) afast?feedbacko connection + ? pwm comp to f/f reset channel start?up offset ? + error amp dac out v fb comp internal ramp x = 1 or 2 ? + v ffb
ncp5331 http://onsemi.com 15 figure 15. enhanced v 2 control employing lossless inductive current sensing and internal ramp + ? swnode lx rlx rsx csx csa con cs ref + v out (v core ) afast?feedbacko connection + ? pwm comp to f/f reset channel start?up offset ? + error amp dac out v fb comp internal ramp x = 1 or 2 ? + v ffb csx with higher current, the pwm cycle will terminate earlier providing negative feedback. the ncp5331 provides a csx input for each phase, but the cs ref and comp inputs are common to all phases. current sharing is accomplished by referencing all phases to the same cs ref and comp pins, so that a phase with a larger current signal will turn off earlier than a phase with a smaller current signal. enhanced v 2 responds to disturbances in v core by employing both aslowo and afasto voltage regulation. the internal error amplifier performs the slow regulation. depending on the gain and frequency compensation set by the amplifier's external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in 1?2 pwm cycles. fast voltage feedback is implemented by a direct connection from v core to the noninverting pin of the pwm comparator via the summation with the inductor current, internal ramp, and the startup offset. a rapid increase in load current will produce a negative offset at v core and at the output of the summer. this will cause the pwm duty cycle to increase almost instantly. fast feedback will typically adjust the pwm duty cycle within 1 pwm cycle. as shown in figure 14, an internal ramp (nominally 125 mv at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the pwm comparator. this additional ramp compensates for propagation time delays from the current sense amplifier (csa), the pwm comparator, and the mosfet gate drivers. as a result, the minimum on time of the controller is reduced and lower duty cycles may be achieved at higher frequencies. also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the rsxcsx (x = 1 or 2) time constant (see figure 15) of the feedback components from v core to the csx pin. including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. when the average output current is zero, the comp pin will be v comp v core @0a channel_startup_offset int_ramp g csa ext_ramp 2 int_ramp is the internal ramp value at the corresponding duty cycle, ext_ramp is the peak?to?peak external steady?state ramp at 0 a, g csa is the current sense amplifier gain (nominally 2.0 v/v), and the startup offset is typically 0.60 v. the magnitude of the ext_ramp can be calculated from ext_ramp d (v in v core ) (rsx csx f sw ) for example, if v core at 0 a is set to 1.225 v with avp and the input voltage is 12.0 v, the duty cycle (d) will be 1.225/12.0 or 10.2%. int_ramp will be 125 mv ? 10.2/50 = 25.5 mv. realistic values for rsx, csx and f sw are 5.6 k , 0.1 f, and 200 khz - using these and the previously mentioned formula, ext_ramp will be 9.8 mv. v comp 1.225 v 0.60 v 25.5 mv 2.0 v v 9.8 mv 2 1.855 vdc. if the comp pin is held steady and the inductor current changes, there must also be a change in the output voltage. or, in a closed loop configuration when the output current changes, the comp pin must move to keep the same output voltage. the required change in the output voltage or comp pin depends on the scaling of the current feedback signal and is calculated as v rsx g csa i out . the single?phase power stage output impedance is single stage impedance v out i out r s g csa the multiphase power stage output impedance is the single?phase output impedance divided by the number of phases. the output impedance of the power stage determines how the converter will respond during the first few
ncp5331 http://onsemi.com 16 swnode v fb (v out ) internal ramp csa out w/ exaggerated delays comp?offset csa out + ramp + cs ref t1 t2 figure 16. open loop operation microseconds of a transient before the feedback loop has repositioned the comp pin. the peak output current can be calculated from i out,peak (v comp v core offset) (rsx g csa ) figure 16 shows the step response of the comp pin at a fixed level. before time t1 the converter is in normal steady state operation. the inductor current provides a portion of the pwm ramp through the current sense amplifier. the pwm cycle ends when the sum of the current ramp, the internal ramp voltage and startup offset exceed the voltage level of the comp pin. at t1 the output current increases and the output voltage sags. the next pwm cycle begins and this pwm cycle continues longer than previously. as a result, the current signal increases enough to make up for the lower voltage at the v fb pin and the cycle ends at t2. after t2 the output voltage remains lower than at light load and the average current signal level (csx output) is raised so that the sum of the current and voltage signal is the same as with the original load. in a closed loop system the comp pin would move higher to restore the output voltage to the original level. inductive current sensing for lossless sensing, current can be sensed across the output inductor as shown in figure 15. in the diagram, lx is the output inductance and rlx is the inherent inductor resistance. to compensate the current sense signal, the values of rsx and csx are chosen so that lx/rlx = rsx ? csx. if this criteria is met, the current sense signal will be the same shape as the inductor current and the voltage signal at csx will represent the instantaneous value of inductor current. also, the circuit can be analyzed as if a sense resistor of value rlx was used as a sense resistor (rsx). when choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. copper magnet wire has a temperature coefficient of 0.39% per c. the increase in winding resistance at higher temperatures should be considered when setting the overcurrent (i lim )threshold. if a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in figure 14. current sharing accuracy printed circuit board (pcb) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is connected. for accurate current sharing, the current sense inputs should sense the current at relatively the same point for each phase and the connection to the cs ref pin should be made so that no phase is favored. in some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance. the total current sense resistance used for calculations must include any pcb trace resistance between the csx input and the cs ref input that carries inductor current. current sense amplifier (csa) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. the worst case current sense amplifier input mismatch is 5.0 mv and will typically be within 3.0 mv. the difference in peak currents between phases will be the csa input mismatch divided by the current sense resistance. if all current sense components are of equal resistance a 3.0 mv mismatch with a 2.0 m total sense resistance will produce a 1.5 a difference in current between phases. external ramp size and current sensing the internal ramp allows flexibility of current sense time constant. typically, the current sense rsxcsx time constant should be equal to or slower than the inductor's time constant. if the rc time constant is chosen to be smaller (faster) than l/r l , the ac or transient portion of the current sensing signal will be scaled larger than the dc portion. this will provide a larger steady state ramp, but circuit performance (i.e. transient response) will be affected and must be evaluated carefully. the current signal will overshoot during transients and settle at the rate determined by rsx ? csx. it will eventually settle to the correct dc level, but the error will decay with the time constant of rsx ? csx. if this error is excessive it will effect transient response, adaptive positioning and current limit. during a positive current transient, the comp pin will be required to undershoot in response to the current signal in order to maintain the output voltage. similarly, the v drp signal will overshoot and will produce too much transient droop in the output voltage. also, the hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents.
ncp5331 http://onsemi.com 17 figure 17. inductive sensing waveform during a load step with fast rc time constant (50 s/div) figure 18. hiccup mode operation figure 19. overcurrent timer operation the waveforms in figure 17 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of l = 500 nh, r l = 1.6 m , rsx = 20 k and csx = 0.01 f. for ideal current signal compensation the value of rsx should be 31 k . due to the faster than ideal rc time constant there is an overshoot of 50% and the overshoot decays with a 200 s time constant. with this compensation the i lim pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step. current limit, hiccup mode and overcurrent timer the individual phase currents are summed and low?pass filtered to create an average current signal. the average current is then compared to a user adjustable voltage at the i lim pin. if the i lim voltage is exceeded, the fault latch is set, switching stops, and the comp pin is discharged until it decreases to 0.27 v. at this point, the fault latch is reset, the comp voltage will begin to rise and a new startup cycle begins. during startup, the output voltage and load current will increase until either regulation is achieved or the i lim voltage is again exceeded. the converter will continue to operate in ahiccup modeo until the fault condition is corrected or the overcurrent timer expires. when an overcurrent fault occurs the converter will enter a low duty cycle hiccup mode. during hiccup mode the converter will not switch from the time a fault is detected until the soft start capacitor (c c2 ) has discharged below the comp discharge threshold and then charged back up above the channel start up offset. figure 18 shows the ncp5331 operating in hiccup mode with the converter output shorted to gnd. hiccup mode will continue until the overcurrent timer terminates operation. the overcurrent timer sets a limit to how long the converter will operate in hiccup mode. placing a capacitor from the c ovc pin to gnd sets the length of time ? a larger capacitor sets a longer time. the first hiccup pulse starts the timer by turning on a current source that charges the capacitor at the c ovc pin. if the voltage at the c ovc pin rises to 3 v before the output voltage exceeds the pgd threshold, then the overcurrent latch is set, comp is discharged, and pgd is latched low. once set, the overcurrent latch will hold the converter in this state until the input voltage, either v ccl or v cch , is cycled. conversely, if the timer starts and either the output short circuit is removed or the load is decreased before the overcurrent timer expires, pgd will transition high after its programmed delay time and the timer will be reset. the nominal overcurrent time can be calculated using the following equation. t ovc c ovc (ovc thresh ovc min ) i ovc c ovc (3.0 v 0.25 v) 5.0 a c ovc 5.5 10 5 figure 19 shows the overcurrent timer terminating hiccup mode when c ovc charges up to 3.0 v.
ncp5331 http://onsemi.com 18 figure 20. overvoltage occurs with uvlo enabled note: using the lower mosfets to prevent overvoltage is not adequate if the mosfets are turned off at the uvlo threshold ? v core reaches 4.0 v within 100 s. figure 21. overvoltage occurs with uvlo disabled note: even if the lower mosfets remain on after uvlo, there is not enough gate drive voltage to prevent v core from reaching 4.0 v. overvoltage protection the ncp5331 provides a comprehensive level of overvoltage protection. overvoltage protection (ovp) addresses the following five cases (in decreasing level of difficulty): 1. normal operation, upper mosfet shorts 2. upper mosfet shorted, turn on the atx power 3. normal operation, open the voltage feedback signal 4. normal operation, ground the voltage feedback signal 5. open the voltage feedback signal, apply atx power by far the most difficult overvoltage scenario is when the upper mosfet shorts during normal operation. the energy stored in the output filters of both the atx supply and the dc/dc converter must be dissipated very quickly or an overvoltage condition will occur. when the upper mosfet shorts, v core rises and the error amplifier, due to the closed loop control, will within approximately 400 ns, command the upper mosfets (those that aren't shorted) to turn off and all the lower mosfets to turn on. this will cause two things to occur: v core will stop increasing, and a very high current will be drawn from the atx supply. the current limit in the atx supply should become active and the input voltage to the converter will be removed. now, when the input voltage drops below the ncp5331's uvlo threshold the lower mosfets will be turned off. at this point, a fair amount of the energy in the system will have been dissipated, however, the converter's output voltage will begin to rise again as shown in figure 20. even if the lower mosfets are not turned off at the uvlo threshold, as v in decays, adequate gate drive voltage will not exist to fully enhance the devices and the cpu may be damaged. this case is shown in figure 21. the ncp5331 avoids the problems with uvlo and the gate drive voltage. when v core exceeds 2.05 v, the ncp5331 will activate an external crowbar mosfet via the cb out pin. this additional mosfet will clamp v core and dissipate the remainder of the energy in the system. the cb out circuitry is powered by 5 v sb and is not disabled during uvlo. also, the cb out pin will always have adequate gate drive to enhance the lower mosfet. the ovp circuits in the ncp5331 are not effected when the atx supply current limits and v in is removed. figure 22 and figure 23 document successful operation of the cb out circuitry when an upper mosfet is shorted during normal operation with 0 a and 45 a loading. the second most difficult overvoltage scenario is when an upper mosfet is shorted and the atx power is applied. in this case, v core is equal to v in due to the shorted upper mosfet. when v in reaches the maximum rating for the cpu (2.2 v) adequate gate drive voltage is not available to enhance the lower mosfets or crowbar device enough to protect the cpu. a typical alogic levelo mosfet will conduct only 100?300 a for a gate drive of 2.0?2.5 v (r ds(on) = 6 k to 25 k ). the r ds(on) of the crowbar device must be lower than 15 m during startup to prevent damage to the cpu. the ncp5331 avoids this problem by taking advantage of the 5 v sb voltage from the atx supply. if v in is less than 5 v sb , then 5 v will be used to enhance the crowbar device. most modern mosfets will be less than 10 m for a v gs greater than 4.5 v. figure 24 shows the ncp5331 preventing v core from exceeding 2.0 v with a shorted upper mosfet during startup. if the voltage feedback signal (corefb+) is broken, a high value internal pull?up resistor will cause v ffb (and v fb ) to float higher in voltage. as v ffb (and v fb ) are pulled higher, the error amplifier will athinko v core is too high and command a lower and lower duty cycle until v core is driven to 0 v. w ithout the internal pull?up resistor the error amplifier would command 100% duty cycle and v core would be driven very high, damaging the cpu.
ncp5331 http://onsemi.com 19 figure 22. ncp5331 prevents overvoltage at 0 a note: the ncp5331 maintains v core < 2.2 v when an upper mosfet shorts during no?load operation. figure 23. ncp5331 prevents overvoltage at 45 a note: the ncp5331 maintains v core < 2.2 v when an upper mosfet shorts with 45 a loading. if the voltage feedback signal (corefb+) is accidentally grounded (but v core is not), the error amplifier will respond by increasing the duty cycle. of course, this will cause v core to rise. when v core reaches 2.0 v, the internal crowbar circuit will be activated and the overcurrent/overvoltage latch will be set. this latch will discharge comp, turn off the upper mosfets, and turn on the lower mosfets. the overcurrent/overvoltage latch will hold the controller in this state until the input power is cycled. transient response and adaptive positioning for applications with fast transient currents the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. adaptive voltage positioning can reduce peak?to?peak output voltage deviations during load transients and allow for a smaller output filter. the output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. for low current applications a droop resistor can provide fast accurate adaptive positioning. however, at high currents the loss in a droop resistor becomes excessive. for example; in a 50 a converter a 1 m resistor to provide a 50 mv change in output voltage between no load and full load would dissipate 2.5 w. lossless adaptive positioning is an alternative to using a droop resistor, but must respond to changes in load current. figure 25 shows how adaptive positioning works. the waveform labeled anormalo shows a converter without adaptive positioning. on the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. with fast (ideal) adaptive positioning the peak to peak excursions are cut in half. in the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. figure 24. ncp5331 prevents overvoltage at startup note: the ncp5331 maintains v core < 2.2 v when an upper mosfet is shorted and atx power is applied. adaptive positioning adaptive positioning normal fast slow limits figure 25. adaptive positioning the controller can be configured to adjust the output voltage based on the output current of the converter. (refer to the application schematic in figure 1). to set the no?load positioning, a resistor is placed between the output voltage and v fb pin. the v fb bias current will develop a voltage across the resistor to adjust the no?load output voltage. the v fb bias current is dependent on the value of r osc as shown in the data sheets.
ncp5331 http://onsemi.com 20 during no load conditions the v drp pin is at the same voltage as the v fb pin, so none of the v fb bias current flows through the v drp resistor. when output current increases the v drp pin increases proportionally and the v drp pin current offsets the v fb bias current and causes the output voltage to decrease. the response during the first few microseconds of a load transient are controlled primarily by power stage output impedance and the esr and esl of the output filter. the transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. if the current signal (external ramp) size is too large or the error amp too slow there will be a long transition to the final voltage after a transient. this will be most apparent with lower capacitance output filters. error amp compensation, tuning, and soft start the transconductance error amplifier requires a capacitance (c c1 + c c2 in the applications diagram) between the comp pin and gnd for two reasons. first, this capacitance stabilizes the transconductance error amplifier. values less than a few nf may cause oscillations of the comp voltage and increase the output voltage jitter. second, this capacitance sets the soft start and hiccup mode slopes. the internal error amplifier will source approximately 30 a during soft start and hiccup mode. no switching will occur until the comp voltage exceeds the channel startup offset (nominally 0.6 v). if c c2 is set to 0.1 f the 30 a from the error amplifier will allow the output to ramp up or down at approximately 30 a/0.1 f or 0.3 v/ms or 1.2 v in 4 ms. the comp voltage will ramp up to the following value. v comp v core @0a channel_startup_offset int_ramp g csa ext_ramp 2 the comp pin will disable the converter when pulled below the comp discharge threshold (nominally 0.27 v). the rc network between the comp pin and the soft start capacitor (r c1 , c c1 ) allows the comp voltage to slew quickly during transient loading of the converter. without this network the error amplifier would have to drive the large soft start capacitor (c c2 ) directly, which would drastically limit the slew rate of the comp voltage. the r c1 /c c1 network allows the comp voltage to undergo a step change of approximately r c1 ? i comp . the capacitor (c a1 ) between the comp pin and the error amplifier's inverting input (the v fb pin) and the parallel combination of the resistors r f1 and r drp determine the bandwidth of the error amplifier. the gain of the error amplifier crosses 0 db at a high enough frequency to give a quick transient response, but well below the switching frequency to minimize ripple and noise on the comp pin. a capacitor in parallel with the r f1 resistor (c f1 ) adds a zero to boost phase near the crossover frequency to improve loop stability. figure 26. power good delay operation note: the pgd timer insures that pgd will transition high when v core is in regulation. setting up and tuning the error amplifier is a three step process. first, the no?load and full?load adaptive voltage positioning (a vp) are set using r f1 and r drp , respectively. second, the current sense time constant and error amplifier gain are adjusted with rsx and c a1 while monitoring v core during transient loading. lastly, the peak?to?peak voltage ripple on the comp pin is examined when the converter is fully loaded to insure low output voltage jitter. the exact details of this process are covered in the design procedure section. undervoltage lockout (uvlo) the controller has undervoltage lockout comparators monitoring two pins. one, intended for the logic and low?side drivers, is connected to the v ccl pin with an 8.5 v turn?on and 6.15 v turn?off threshold. a second, for the high side drivers, is connected to the v cch pin with an 8.5 v turn?on and 6.75 v turn?off threshold. a uvlo fault sets the fault latch which forces switching to stop and the upper and lower gate drivers produce a logic low (i.e., all the mosfets are turned off). power good (pgd) is pulled low when uvlo occurs. the overcurrent/overvoltage latch is reset by the uvlo signal. power good (pgd) delay time when v core is less than the power good threshold, 87.5% ? dac, or greater than 2.0 v the open?collector power good pin (pgd) will be pulled low by the ncp5331. when v core is in regulation pgd will become high impedance. an external pull?up resistor is required on pgd. during soft start, when v core reaches the power good threshold, 87.5% ? dac, then the alongero of two timers will dictate when pgd becomes high impedance. one timer is internally set to 200 s and can not be changed. placing a capacitor from the c pgd pin to gnd sets the second programmable timer. when v core crosses the pgd threshold, a current source will charge c pgd starting at
ncp5331 http://onsemi.com 21 0.25 v and atiming outo at 3 v. the current delivered to the c pgd capacitor (i pgd ) is a function of the r osc resistor according to the following equation. i pgd 0.52 v r osc the programmed delay time can be calculated from t pgd c pgd (pgd thresh pgd min ) i pgd c pgd (3.0 v 0.25 v) i pgd the programmable timer may be disabled (set to 0) by connecting the c pgd pin to 5 v ref . this will set the pgd delay time to the internal delay of 200 s. figure 26 demonstrates the use of the programmable pgd timer (set to 6.0 ms) to allow pgd to transition high when v core is safely within the regulation limits for the processor (dac 50 mv). implementing an enable function an enable function may be implemented on the ncp5331 in one of two ways. the first method (method a in figure 27) is to pull low on the ilim pin. this method is the preferred method, as both the ghx and the glx pins will be kept low at turn?off, preventing v core from being pulled below ground. however, if using the atimed hiccup mode current limito feature with method a, the covc pin will time out when the ilim pin is pulled low, and the ncp5331 will not turn back on (after time out) unless the power is recycled. this can be avoided by adding another transistor to the covc pin, thereby keeping it low while the part is disabled. the second method (method b in figure 28) is to pull low on the ncp5331's comp pin. with this method, ghx will be low and glx will be high while the part is disabled. however, under method b, if the part is disabled at turn?on, and if using the atimed hiccup mode current limito feature, the covc pin will again time out and the ncp5331 will not be able to be turned on after the time out has occurred. this too can be avoided by the use of a transistor at the covc pin keeping it low while the part is disabled. if using method b but not with a transistor at the covc pin, a 1.0 k resistor must be added between the drain of the transistor and the comp pin to prevent the current limit from being tripped when the comp pin is quickly pulled low. i lim figure 27. enable method a *needed if using `timed hiccup mode current limit' qi lim bss123 1 2 3 c ovc *qc ovc bss123 2 3 1 hi to disable lo to enable comp figure 28. enable method b qcomp bss123 1 2 3 c ovc **qc ovc bss123 2 3 1 hi to disable lo to enable *r 1.0 k *needed if not using qcovc **allows disabling at turn?on (when using `timed hiccup mode current limit')
ncp5331 http://onsemi.com 22 power dissipation ncp5331 power dissipation may be approximated by the following equation: p loss f sw (v cch q thighfets v cclx q tlowfets ) p quiescent where: p quiescent v ccl i ccl 2v cclx i cclx (v cch v in )i cch f sw is the switching frequency v ccl is 12 v v cclx is the low?side gate drive voltage and may be varied between 5.0 and 12 v v cch is the high?side gate drive voltage and is between 4.5 and 7.0 v v in is the input voltage to the converter and is either 5.0 or 12 v i ccl , i cclx , i cch are typical device quiescent currents and can be found under the general electrical specifications. q thighfets is the sum of the high?side mosfets total gate charge q tlowfets is the sum of the low?side mosfets total gate charge figure 29 shows device temperature rise versus switching frequency at various gate drive voltage combinations using on semiconductor's ntd60n03 (qt = 31nc at 5.0 v) as the high?side mosfet and ntd80n02 (qt = 39nc at 7.0 v) as the low?side mosfet. using other mosfets will of course result in different losses, but the general conclusion will be the same. if trying to drive 2 lower mosfets at frequencies higher than 200 khz, it may be necessary to reduce the low?side gate drive voltage. figure 29. calculated ncp5331 temperature rise (lqfp?32 package) versus frequency at various typical gate drive voltage combinations with typical on semiconductor mosfets. 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 100 150 200 250 300 350 frequency (khz) v cch = 4.5 v; v cclx = 12 v; 1 low?side fets v cch = 4.5 v; v cclx = 12 v; 2 low?side fets v cch = 7.0 v; v cclx = 12 v; 2 low?side fets v cch 4.5 v; v cclx = 12 v; 2 low?side fets v cch = 7.0 v; v cclx = 12 v; 1 low?side fets v cch = 7.0 v; v cclx = 12 v; 2 low?side fets
ncp5331 http://onsemi.com 23 layout guidelines with the fast rise, high output currents of microprocessor applications, parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. typically, a multilayer board with at least one ground plane is recommended. if the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to route the currents away from the controller. the slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. additional power and ground planes or islands can be added as required for a particular layout. gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. gate drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. if required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. the current sense signals are typically tens of millivolts. noise pick?up should be avoided wherever possible. current feedback traces should be routed away from noisy areas such as the switch node and gate drive signals. if the current signals are taken from a location other than directly at the inductor any additional resistance between the pick?off point and the inductor appears as part of the inherent inductor resistances and should be considered in design calculations. the capacitors for the current feedback networks should be placed as close to the current sense pins as practical. after placing the ncp5331 control ic, follow these guidelines to optimize the layout and routing: 1. place the 1 f ceramic power?supply bypass capacitors close to their associated pins: v ccl , v cch , v ccl1 and v ccl2 . 2. place the mosfets to minimize the length of the gate traces. orient the mosfets such that the drain connections are away from the controller and the gate connections are closest to the controller. 3. place the components associated with the internal error amplifier (r f1 , c f1 , c c1 , c c2 , r c1 , c a1 , r drp ) to minimize the trace lengths to the pins v fb , v drp and comp. 4. place the current sense components (r s1 , r s2 , c s1 , c s2 , r s , c sa , c sb ) near the cs1, cs2, and cs ref pins. 5. place the frequency setting resistor (r osc ) close to the r osc pin. the r osc pin is very sensitive to noise. route noisy traces, such as the swnodes and gate traces, away from the r osc pin and resistor. 6. place the mosfets and output inductors to reduce the size of the noisy swnodes. however, there is a trade?off between reducing the size of the swnodes for noise reduction and providing adequate heat?sinking for the synchronous mosfets. 7. place the input inductor and input capacitor(s) near the drain of the control (upper) mosfets. there is a trade?off between reducing the size of this node to save board area and providing adequate heat?sinking for the control (upper) mosfets. 8. place the output capacitors (electrolytic and ceramic) close to the processor socket or output connector. 9. the trace from the swnodes to the current sense components (r s1 , r s2 ) will be very noisy. route this away from more sensitive, low?level traces. the ground layer can be used to help isolate this trace. 10. the gate traces are very noisy. route these away from more sensitive, low?level traces. try to keep each gate signal on one layer and insure that there is an uninterrupted return path directly below the gate trace. the ground layer can be used to help isolate these traces. 11. gate driver returns, gnd1 and gnd2, should not be connected to lgnd, but instead directly to the ground plane. 12. try not to adaisy chaino connections to ground from one via. ideally, each connection to ground will have its own via located as close to the component as possible. 13. use a slot in the ground plane to prevent high currents from flowing beneath the control ic. this slot should form an aislando for signal ground under the control ic. asignal groundo and apower groundo must be separated. examples of signal ground include the capacitors at comp, cs ref , and 5v ref , the resistors at r osc and i lim , and the lgnd pin to the controller. examples of power ground include the capacitors to v cch and v ccl1 and v ccl2 , the source of the synchronous mosfets, and the gnd1 and gnd2 pins of the controller.
ncp5331 http://onsemi.com 24 14. the cs ref sense point should be equidistant between the output inductors to equalize the pcb resistance added to the current sense paths. this will insure acceptable current sharing. also, route the cs ref connection away from noisy traces such as the swnodes and gate traces. if noise from the swnodes or gate signals capacitively couples to the csref trace the external ramps will be very noisy and voltage jitter will result. 15. ideally, the swnodes are exactly the same shape and the current sense points (connections to r s1 and r s2 ) are made at identical locations to equalize the pcb resistance added to the current sense paths. this will help to insure acceptable current sharing. 16. place the 1 f ceramic capacitors, c p1 and c p2 , close to the drains of the mosfets q1 and q2, respectively. 17. if snubbers are used, they must be placed very close to their associated mosfets and swnode. the connections to the snubber components should be as short as possible. design procedure 1. output capacitor selection the output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. typically, microprocessor applications will require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. the bulk capacitors provide ahold upo during transient loading. the low impedance capacitors reduce steady?state ripple and bypass the bulk capacitance when the output current changes very quickly. the microprocessor manufacturers usually specify a minimum number of ceramic capacitors. the designer must determine the number of bulk capacitors. choose the number of bulk output capacitors to meet the peak transient requirements. the following formula can be used to provide a starting point for the minimum number of bulk capacitors (n out,min ). n out,min esr per capacitor i o,max v o,max (1) in reality, both the esr and esl of the bulk capacitors determine the voltage change during a load transient according to v o , max ( i o , max t) esl i o , max esr (2) unfortunately, capacitor manufacturers do not specify the esl of their components and the inductance added by the pcb traces is highly dependent on the layout and routing. therefore, it is necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors. 2. output inductor selection the output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady?state and transient performance of the converter. when selecting an inductor the designer must consider factors such as dc current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size, and cost (usually the primary concern). in general, the output inductance value should be as low and physically small as possible to provide the best transient response and minimum cost. if a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. on the other hand, too low an inductance value will result in very large ripple currents in the power components (mosfets, capacitors, etc) resulting in increased dissipation and lower converter efficiency. also, increased ripple currents will force the designer to use higher rated mosfets, oversize the thermal solution, and use more, higher rated input and output capacitors ? the converter cost will be adversely effected. one method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. lower ripple currents will result in less core and mosfet losses and higher converter efficiency. equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current ( a ) per phase. the inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. conversely, higher inductor values will result in less than the maximum ripple current. lo min (v in v core ) v core ( i o,max v in f sw ) (3) a is the ripple current as a percentage of the maximum output current per phase ( a = 0.15 for 15%, a = 0.25 for 25%, etc). if the minimum inductor value is used, the inductor current will swing a % about its value at the center (half the dc output current for a two?phase converter). therefore, for a two?phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + a ) ? i o,max /2. the maximum inductor value is limited by the transient response of the converter. if the converter is to have a fast transient response then the inductor should be made as small as possible. if the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required, and the converter cost will be increased. for a given inductor value, its interesting to determine the time required to increase or decrease the current.
ncp5331 http://onsemi.com 25 for increasing current t inc lo i o (v in v core ) (3.1) for decreasing current t dec lo i o (v core ) (3.2) for typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. it may be more difficult for the converter to stay within the regulation limits when the load is removed than when it is applied ? excessive overshoot may result. the output voltage ripple can be calculated using the output inductor value derived in this section (lo min ), the number of output capacitors (n out,min ) and the per capacitor esr determined in the previous section. v out,p?p (esr per cap n out,min ) (v in #phases v core ) d (lo min f sw ) (4) this formula assumes steady?state conditions with no more than one phase on at any time. the second term in equation 4 is the total ripple current seen by the output capacitors. the total output ripple current is the atime summationo of the two individual phase currents that are 180 degrees out?of?phase. as the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. therefore, the total output ripple current and voltage are reduced in a multiphase converter. 3. input capacitor selection the choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. the designer must choose capacitors that will support the worst case input voltage with adequate margin. to calculate the number of input capacitors one must first determine the total rms input ripple current. to this end, begin by calculating the average input current to the converter. i in,avg i o,max d (5) where d is the duty cycle of the converter, d = v core /v in , h is the specified minimum efficiency, i o,max is the maximum converter output current. the input capacitors will discharge when the control fet is on and charge when the control fet is off as shown in figure 30. the following equations will determine the maximum and minimum currents delivered by the input capacitors. i c,max i lo,max i in,avg (6) i c,min i lo,min i in,avg (7) i lo,max is the maximum output inductor current. i lo,max i o,max 2 i lo 2 (8) i c,max i c,min 0 a ?i in,avg fet on, caps discharging fet off, caps charging t on t/2 i c,in = i c,max ? i c,min figure 30. input capacitor current for a two?phase converter i lo,min is the minimum output inductor current. i lo,min i o,max 2 i lo 2 (9) i lo is the peak?to?peak ripple current in the output inductor of value l o . i lo (v in v core ) d (lo f sw ) (10) for the two?phase converter, the input capacitor(s) rms current is then i cin,rms [2d (i c,min 2 i c,min i c,in i c,in 2 3) i in,avg 2 (1 2d)] 1 2 (11) select the number of input capacitors (n in ) to provide the rms input current (i cin,rms ) based on the rms ripple current rating per capacitor (i rms,rated ). n in i cin,rms i rms,rated (12) for a two?phase converter with perfect efficiency ( h = 1), the worst case input ripple current will occur when the converter is operating at a 25% duty cycle. at this operating point, the parallel combination of input capacitors must support an rms ripple current equal to 25% of the converter's dc output current. at other duty cycles, the ripple current will be less. for example, at a duty cycle of either 10% or 40%, the two?phase input ripple current will be approximately 20% of the converter's dc output current. in general, capacitor manufacturers require derating to the specified ripple current based on the ambient temperature. more capacitors will be required because of the current derating. the designer should be cognizant of the esr of the input capacitors. the input capacitor power loss can be calculated from p cin i cin,rms 2 esr_per_capacitor n in (13) low esr capacitors are recommended to minimize losses and reduce capacitor heating. the life of an electrolytic capacitor is reduced 50% for every 10 c rise in the capacitor's temperature.
ncp5331 http://onsemi.com 26 + + vi 12 v li tbd ci 5 16mbz1500m10x20 esr ci 13 m/5 = 2.6 m q2 q1 lo 729 nh esr co 19 m/6 = 3.2 m 26 u(t) co 6 16mbz1000m10x16 vi(t = 0) = 12 v swnode vo(t = 0) = 1.225 v v ci i lo v out i li max di/dt occurs in first few pwm cycles. figure 31. calculating the input inductance + ? 4. input inductor selection the use of an inductor between the input capacitors and the power source will accomplish two objectives. first, it will isolate the voltage source and the system from the noise generated in the switching supply. second, it will limit the inrush current into the input capacitors at power up. large inrush currents will reduce the expected life of the input capacitors. the inductor's limiting effect on the input current slew rate becomes increasingly beneficial during load transients. the worst case input current slew rate will occur during the first few pwm cycles immediately after a step?load change is applied as shown in figure 31. when the load is applied, the output voltage is pulled down very quickly. current through the output inductors will not change instantaneously so the initial transient load current must be conducted by the output capacitors. the output voltage will step downward depending on the magnitude of the output current (i o,max ), the per capacitor esr of the output capacitors (esr out ), and the number of the output capacitors (n out ) as shown in figure 31. assuming the load current is shared equally between the two phases, the output voltage at full, transient load will be v core,full?load (14) v core,no?load (i o,max 2) esr out n out when the control mosfet (q1 in figure 31) turns on, the input voltage will be applied to the opposite terminal of the output inductor (the swnode). at that instant, the voltage across the output inductor can be calculated as v lo v in v core,full?load (15) v in v core,no?load (i o,max 2) esr out n out the differential voltage across the output inductor will cause its current to increase linearly with time. the slew rate of this current can be calculated from di lo dt v lo lo (16) current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. the amount of voltage drop across the input capacitors ( v ci ) is determined by the number of input capacitors (n in ), their per capacitor esr (esr in ), and the current in the output inductor according to v ci esr in n in di lo dt t on esr in n in di lo dt d f sw (17) before the load is applied, the voltage across the input inductor (v li ) is very small ? the input capacitors charge to the input voltage, v in . after the load is applied the voltage drop across the input capacitors, v ci , appears across the input inductor as well. knowing this, the minimum value of the input inductor can be calculated from li min v li di in dt max v ci di in dt max (18) where di in /dt max is the maximum allowable input current slew rate. the input inductance value calculated from equation 18 is relatively conservative. it assumes the supply voltage is very astiffo and does not account for any parasitic elements that will limit di/dt such as stray inductance. also, the esr values of the capacitors specified by the manufacturer's data sheets are worst case high limits. in reality input voltage asag,o lower capacitor esrs, and stray inductance will help reduce the slew rate of the input current. as with the output inductor, the input inductor must support the maximum current without saturating the magnetic. also, for an inexpensive iron powder core, such as the ?26 or ?52 from micrometals, the inductance aswingo with dc bias must be taken into account ? inductance will decrease as the dc input current increases. at the maximum input current, the inductance must not decrease below the minimum value or the di/dt will be higher than expected.
ncp5331 http://onsemi.com 27 5. mosfet and heatsink selection power dissipation, package size, and thermal solution drive mosfet selection. to adequately size the heat sink, the design must first predict the mosfet power dissipation. once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the control or upper mosfet will display both switching and conduction losses. the synchronous or lower mosfet will exhibit only conduction losses because it switches into nearly zero voltage. however, the body diode in the synchronous mosfet will suffer diode losses during the nonoverlap time of the gate drivers. for the upper or control mosfet, the power dissipation can be approximated from p d,control (i rms,cntl 2 r ds(on) ) (i lo,max q switch i g v in f sw ) (q oss 2 v in f sw ) (v in q rr f sw ) (19) the first term represents the conduction or ir losses when the mosfet is on, while the second term represents the switching losses. the third term is the losses associated with the control and synchronous mosfet output charge when the control mosfet turns on. the output losses are caused by both the control and synchronous mosfet but are dissipated only in the control fet. the fourth term is the loss due to the reverse recovery time of the body diode in the synchronous mosfet. the first two terms are usually adequate to predict the majority of the losses. i rms,cntl is the rms value of the trapezoidal current in the control mosfet. (20) i rms,cntl [d (i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 i lo,max is the maximum output inductor current. i lo,max i o,max 2 i lo 2 (21) i lo,min is the minimum output inductor current. i lo,min i o,max 2 i lo 2 (22) i o,max is the maximum converter output current. d is the duty cycle of the converter. d v core v in (23) i lo is the peak?to?peak ripple current in the output inductor of value l o . i lo (v in v core ) d (lo f sw ) (24) r ds(on) is the on resistance of the mosfet at the applied gate drive voltage. q switch is the post gate threshold portion of the gate?to?source charge plus the gate?to?drain charge. this may be specified in the data sheet or approximated from the gate?charge curve as shown in the figure 32. i d v gate v drain q gd q gs2 q gs1 v gs_th figure 32. mosfet switching characteristics q switch q gs2 q gd (25) i g is the output current from the gate driver ic. v in is the input voltage to the converter. f sw is the switching frequency of the converter. q rr is the reverse recovery charge of the lower mosfet. q oss is the sum of all the mosfet output charges. for the lower or synchronous mosfet, the power dissipation can be approximated from p d,synch (i rms,synch 2 r ds(on) ) (vf diode i o,max 2 t_nonoverlap f sw ) (26) the first term represents the conduction or ir losses when the mosfet is on, and the second term represents the diode losses that occur during the gate nonoverlap time. all terms were defined in the previous discussion for the control mosfet with the exception of (27) i rms,synch [(1 d) (i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 vf diode is the forward voltage of the mosfet's intrinsic diode at the converter output current. t_nonoverlap is the nonoverlap time between the upper and lower gate drivers to prevent cross conduction. this time is usually specified in the data sheet for the control ic. when the mosfet power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature. t (t j t a ) p d (28) where t is the total thermal impedance ( jc + sa ), jc is the junction?to?case thermal impedance of the mosfet, sa is the sink?to?ambient thermal impedance of the heatsink assuming direct mounting of the mosfet (no thermal apado is used), t j is the specified maximum allowed junction temperature, t a is the worst case ambient operating temperature.
ncp5331 http://onsemi.com 28 for to?220 and to?263 packages, standard fr?4 copper clad circuit boards will have approximate thermal resistances ( sa ) as shown in the following table. pad size (in 2 /mm 2 ) single?sided 1 oz. copper 0.5/323 60?65 c/w 0.75/484 55?60 c/w 1.0/645 50?55 c/w 1.5/968 45?50 c/w 2.0/1290 38?42 c/w 2.5/1612 33?37 c/w as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case mosfet r ds(on) ). also, the inductors and capacitors share the mosfet's heatsinks and will add heat and raise the temperature of the circuit board and mosfet. for any new design, its advisable to have as much heatsink area as possible ? all too often new designs are found to be too hot and require redesign to add heatsinking. 6. adaptive voltage positioning there are two resistors that determine the adaptive voltage positioning, r f1 and r drp . r f1 establishes the no?load ahigho voltage position and r drp determines the full?load adroopo voltage. resistor r f1 is connected between v core and the v fb pin of the controller. at no load, this resistor will conduct the internal bias current of the v fb pin and develop a voltage drop from v core to the v fb pin. because the error amplifier regulates v fb to the dac setting, the output voltage, v core , will be higher by the amount ibias vfb ? r f1 . this condition is shown in figure 33. to calculate r f1 the designer must specify the no?load voltage increase above the vid setting ( v no?load ) and determine the v fb bias current. usually, the no?load voltage increase is specified in the design guide for the processor that is available from the manufacturer. the v fb bias current is determined by the value of the resistor from r osc to ground (see figure tbd for a graph of ibias vfb versus r osc ). the value of r f1 can then be calculated. r f1 v no?load ibias vfb (29) resistor r drp is connected between the v drp and the v fb pins. at no?load, the v drp and the v fb pins will both be at the dac voltage so this resistor will conduct zero current. however, at full?load, the voltage at the v drp pin will increase proportional to the output inductor's current while v fb will still be regulated to the dac voltage. current will be conducted from v drp to v fb by r drp . this current will be large enough to supply the v fb bias current and cause a voltage drop from v fb to v core across r f1 ? the converter's output voltage will be reduced. this condition is shown in figure 34. to determine the value of r drp the designer must specify the full?load voltage reduction from the vid (dac) setting ( v core,full?load ) and predict the voltage increase at the v drp pin at full?load. usually, the full?load voltage reduction is specified in the design guide for the processor that is available from the manufacturer. to predict the voltage increase at the v drp pin at full?load ( v drp ), the designer must consider the output inductor's resistance (r l ), the pcb trace resistance between the current sense points (r pcb ), and the controller ic's gain from the current sense to the v drp pin (g vdrp ). v drp i o,max (r l r pcb ) g vdrp (30) the value of r drp can then be calculated. r drp v drp (ibias vfb v core , full?load r f1 ) (31) v core,full?load is the full?load voltage reduction from the vid (dac) setting. v core,full?load is not the voltage change from the no?load avp setting. ? + + ? s r s1 cs1 c s1 l1 0 a g vdrp + ? r s2 cs2 c s2 l2 0 a g vdrp cs ref comp error amp vid setting ibias vfb r drp r f1 v drp = vid v fb = vid v core i drp = 0 i fbk = ibias vfb v core = vid + ibias vfb r f1 figure 33. avp circuitry at no?load + ?
ncp5331 http://onsemi.com 29 ? + + ? s r s1 cs1 c s1 l1 i max /2 g vdrp + ? r s2 cs2 c s2 l2 i max /2 g vdrp cs ref comp error amp vid setting ibias vfb r drp r f1 v drp = vid + i max ? r l ? g vdrp v fb = vid v core i drp i fbk v core = vid ? (i drp ? ibias vfb ) r f1 figure 34. avp circuitry at full?load i drp = i max ? r l ? g vdrp /r drp i fbk = i drp ? ibias vfb + ? figure 35. v drp tuning, rc time too long note: the rc time constant of the current sense network is too long (slow); v drp and v core respond too slowly. figure 36. v drp tuning, rc time too short note: the rc time constant of the current sense network is too short (fast); v drp and v core both overshoot. 7. current sensing for inductive current sensing, choose the current sense network (rsx, csx) to satisfy rsx csx lo (r l r pcb ) (32) for resistive current sensing, choose the current sense network (rsx, csx) to satisfy rsx csx lo (r sense ) (33) this will provide an adequate starting point for rsx and csx. after the converter is constructed, the value of rsx (and/or lsx) should be fine?tuned in the lab by observing the v drp signal during a step change in load current. tune the rsx ? csx network to provide a asquare?waveo at the v drp output pin with maximum rise time and minimal overshoot as shown in figures 34 ? 36. figure 37. v drp tuning, rc time optimal note: the rc time constant of the current sense network is optimal; v drp and v core respond to the load current quickly without overshooting.
ncp5331 http://onsemi.com 30 note: the value of c a1 is too low and the loop gain/ bandwidth too high. comp moves too quickly, which is evident from the small spike in its voltage when the load is applied or removed. the output voltage transitions more slowly because of the comp spike. figure 38. comp tuning, bandwidth too low figure 39. comp tuning, bandwidth too high note: the value of c a1 is too high and the loop gain/ bandwidth too low. comp slews too slowly which results in overshoot in v core . figure 40. comp tuning, bandwidth optimal note: the value of c a1 is optimal. comp slews quickly without spiking or ringing. v core does not overshoot and monotonically settles to its final value. 8. error amplifier tuning after the steady?state (static) avp has been set and the current sense network has been optimized the error amplifier must be tuned. basically, the gain of the error amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the error amplifier's feedback capacitor (c a1 in the applications diagram). the bandwidth of the control loop will vary directly with the gain of the error amplifier. if c a1 is too large the loop gain/bandwidth will be low, the comp pin will slew too slowly, and the output voltage will overshoot as shown in figure 38. on the other hand, if c a1 is too small the loop gain/bandwidth will be high, the comp pin will slew very quickly and overshoot. integrator awind upo is the cause of the overshoot. in this case the output voltage will transition more slowly because comp spikes upward as shown in figure 39. too much loop gain/bandwidth increase the risk of instability. in general, one should use the lowest loop gain/bandwidth as possible to achieve acceptable transient response ? this will insure good stability. if c a1 is optimal the comp pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in figure 40. after the control loop is tuned to provide an acceptable transient response the steady?state voltage ripple on the comp pin should be examined. when the converter is operating at full, steady?state load, the peak?to?peak voltage ripple on the comp pin should be less than 20 mvpp as shown in figure 41. less than 10 mvpp is ideal. excessive ripple on the comp pin will contribute to output voltage jitter. 9. current limit setting when the output of the current sense amplifier (co1 or co2 in the block diagram) exceeds the voltage on the i lim pin the part will enter hiccup mode. for inductive sensing, the i lim pin voltage should be set based on the inductor's maximum resistance (r lmax ). the design must consider note: at full load the peak?to?peak voltage ripple on the comp pin should be less than 20 mv for a well?tuned/stable controller. higher comp voltage ripple will contribute to output voltage jitter. figure 41. comp ripple for a stable system
ncp5331 http://onsemi.com 31 the inductor's resistance increase due to current heating and ambient temperature rise. also, depending on the current sense points, the circuit board may add additional resistance. in general, the temperature coefficient of copper is +0.393% per c. if using a current sense resistor (r sense ), the i lim pin voltage should be set based on the maximum value of the sense resistor. to set the level of the i lim pin, v ilim (i out,lim i lo 2) r g ilim (34) where i out,lim is the current limit threshold of the converter, i lo /2 is half the inductor ripple current, r is either (r lmax + r pcb ) or r sense , g ilim is the current sense to i lim gain. for the overcurrent protection to work properly, the current sense time constant (rc) should be slightly larger than the rl time constant. if the rc time constant is too fast, during step load changes the sensed current waveform will appear larger than the actual inductor current and will probably trip the current limit at a lower level than expected. 10. overcurrent timer the overcurrent timer sets the time the converter will allow hiccup mode operation. given the capacitance from the c ovc pin to gnd, the nominal overcurrent time (t ovc ) can be calculated from the following equation. t ovc c ovc (ovc thresh ovc min ) i ovc (35) c ovc (3.0 v 0.25 v) 5.0 a c ovc 5.5 10 5 where ovc thresh is the overcurrent timer's shutdown voltage, nominally 3 v, ovc min is the overcurrent timer's starting voltage, nominally 0.25 v, i ovc is the charge current supplied to the capacitor at the c ovc pin, nominally 5 a. 11. soft start time the soft start time (t ss ) can be calculated from t ss (v comp r c1 i comp ) c c2 i comp (36) where v comp v core @0a channel_startup_offset int_ramp g csa ext_ramp 2 ext_ramp d (v in v core ) (r csx c csx f sw ) int_ramp 125 mv d 0.50 i comp is the comp source current from the data sheet, int_ramp is the internal ramp value at the corresponding duty cycle, ext_ramp is the peak?to?peak external steady?state ramp at 0 a, g csa is the current sense amplifier gain (nominally 2.0 v/v), startup offset is typically 0.60v. 12. power good delay time the power good timer sets the delay time between when v core exceeds the c pgd comparator's threshold voltage and when pgd will actually transition high. the pgd delay time can be calculated from t pgd c pgd (pgd thresh pgd min ) i pgd (37) c pgd (3.0 v 0.25v) i pgd where pgd thresh is the pgd comparator's threshold voltage, nominally 3 v, pgd min is the pgd timer's starting voltage, nominally 0.25 v, i pgd is the charge current supplied to the capacitor at the c pgd pin. this current is a function of the r osc resistor according to i pgd = 0.52 v/r osc . design example typical design requirements: v in = 12.0 vdc v core = 1.20 vdc (nominal) v out,ripple < 20 mv pp max vid range: 0.800 vdc ? 1.550 vdc i o,max = 52 a at full?load i out,lim = 72 adc di in /dt = 0.50 a/ s max f sw = 200 khz h = 80% min at full?load t a,max = 55 c t j,max = 120 c t ss = 6.0 ms (soft start time) t ovc = 120 ms (overcurrent time) t pgd = 6.0 ms (pgd delay time) v core at no?load (static) = ?25 mv from vid setting = 1.225 vdc v core at full?load (static) = 37 mv from vid setting = 1.163 vdc v core transient loading from 3.0 a to 25 a = ?50 mv from vid setting = 1.150 vdc 1. output capacitor selection first, choose a low?cost, low?esr output capacitor such as the rubycon 16mbz1000m10x16: 16 v, 1000 f, 2.55 a rms , 19 m , 10 16 mm. calculate the minimum number of output capacitors. n out,min esr per capacitor i o,max v o,max 19 m 22 a (1.225 v 1.150 v) 5.6 or 6 capacitors minimum (6000 f) (1)
ncp5331 http://onsemi.com 32 2. output inductor selection calculate the minimum output inductance at i o,max according to equation 3 with 20% inductor ripple current ( a = 0.15). lo min (v in v out ) v out ( i o,max v in f sw ) (12 v 1.163 v) 1.163 v (0.15 52 a 12 v 200 khz) 673 nh (3) to minimize core losses, we choose the t50 - 8b/90 core from micrometals: 23.0 nh/n 2 , 2.50 cm/turn. according to the micrometals catalog, at 26 a (per phase) the permeability of this core will be approximately 88% of the permeability at 0 a. therefore, at 0 a we must achieve at least 673 nh/0.88 or 765 nh. using 6 turns of #16 awg bifilar (2 m /ft) will produce 828 nh . we will need the nominal and worst case inductor resistances for subsequent calculations. r l 6 turns 2.5 cm turn 0.03218 ft cm 2m ft 0.965 m the inductor resistance will be maximized when the inductor is ahoto due to the load current and the ambient temperature is high. assuming a 50 c temperature rise of the inductor at full?load and a 35 c ambient temperature rise we can calculate r l,max 0.965 m [1 0.39% c (50 c 35 c)] 1.28 m the output inductance at full?load will be reduced due to the saturation characteristic of the core material. lo 52 a 0.88 828 nh 729 nh at full load next, use equation 4 to insure the output voltage ripple will satisfy the design goal with the minimum number of output capacitors and the full load output inductance. (1.163 v 12 v) (729 nh 200 khz)} (4) (19 m 6) {(12 v 2 1.163 v) 20 mv v out,p?p (esr per cap n out,min ) {(v in #phases v core ) d (lo 52 a f sw )} so, the ripple requirement will be satisfied if the minimum number of output capacitors is used. more output capacitors will probably be required to satisfy the transient requirement, which will result in a lower ripple voltage. 3. input capacitor selection use equation 5 to determine the average input current to the converter at full?load. i in,avg i o,max d 52 a (1.163 v 12 v) 0.80 6.30 a (5) next, use equation 6 to equation 10 with the full?load inductance value of 729 nh. i lo (v in v out ) d (lo f sw ) (12 v 1.163 v) (1.163 v 12 v) (729 nh 200 khz) 7.20 app (10) i lo,max i o,max 2 i lo 2 52 a 2 7.20 app 2 29.6 a (8) i lo,min i o,max 2 i lo 2 52 a 2 7.20 app 2 22.4 a (9) i c,max i lo,max i in,avg 29.6 a 0.80 6.30 a 30.7 a (6) i c,min i lo,min i in,avg 22.4 a 0.80 6.30 a 21.7 a (7) for the two?phase converter, the input capacitor(s) rms current at full?load is as follows. (note: d = 1.163 v/12 v = 0.097.) i cin,rms [2d (i c,min 2 i c,min i c,in (11) i c,in 2 3) i in,avg 2 (1 2d)] 1 2 [0.19 (21.7 2 21.7 9.0 9.0 2 3) 6.30 2 (1 0.19)] 1 2 12.9 a rms at this point, the designer must decide between saving board space by using higher?rated/more costly capacitors or saving cost by using more lower?rated/less costly capacitors. to save cost, we choose the mbz series capacitors by rubycon. part number 16mbz1500m10x20: 1500 f, 16 v, 2.55 a rms , 13 m , 10 20 mm. this design will require n in = 12.8 a/2.55 a = 5 capacitors on the input for a cost sensitive design or 6 capacitors for a conservative design. 4. input inductor selection for the claw hammper cpu, the input inductor must limit the input current slew rate to less than 0.5 a/ s during a load transient from 0 to 52 a. a conservative value will be calculated assuming the minimum number of output capacitors (n out = 6), five input capacitors (n in = 5), worst case esr values for both the input and output capacitors, and a maximum duty cycle at the maximum dac setting with 25 mv of no?load avp. d max (1.550 v 25 mv avp ) 10.8 v in 0.146
ncp5331 http://onsemi.com 33 first, use equation 15 to calculate the voltage across the output inductor due to the 52 a load current being shared equally between the two phases. (15) v lo v in v core,no?load (i o,max 2) esr out n out 12 v 1.575 v 52 a 2 19 m 6 10.51 v second, use equation 16 to determine the rate of current increase in the output inductor when the load is applied (i.e., lo has decreased to 88% due to the dc current). di lo dt v lo lo 10.51 v 729 nh 14.4 v s (16) finally, use equation 17 and equation 18 to calculate the minimum input inductance value. v ci esr in n in di lo dt d f sw 13 m 5 14.4 v s 0.146 200 khz 28 mv (17) li min v ci di in dt max 28 mv 0.50 a s 55 nh (18) next, choose the small, cost effective t30?26 core from micrometals (33.5 nh/n 2 ) with #16 awg. the design requires only 1.28 turns to achieve the minimum inductance value. we allow for inductance aswingo at full?load by using three turns. the input inductor's value will be l i 3 2 33.5 nh n 2 301 nh this inductor is available as part number ctx15?14771 from coiltronics. 5. mosfet & heatsink selection for the upper mosfet we choose two (1) ntd60n03 and for the lower mosfets we choose two (2) ntd80n02, both are from on semiconductor. the following parameters are derived from the data sheets. ncp5331 parameter value gate drive current 1.5 a for 1.0 s upper gate voltage 6.5 v lower gate voltage 11.5 v gate nonoverlap time 65 ns parameter ntd60n03 ntd80n02 r ds(on) 8.0 m @ 6.5 v 5.0 m @ 10 v q switch 27 nc 26 nc q rr 43 nc 36 nc q oss 12 nc 12 nc v f,diode 0.75 v @ 2.3 a 0.92 v @ 20 a jc 1.65 c/w 1.65 c/w the rms value of the current in the control mosfet is calculated from equation 20 and the previously derived values for d, i lmax , and i lmin at the converter's maximum output current. 0.097 [(29.6 2 29.6 22.4 22.4 2 ) 3] 1 2 (20) i rms,cntl [d (i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 2.53 a rms equation 19 is used to calculate the power dissipation of the control mosfet but has been modified for one upper and two lower mosfets. p d,control { (i rms,cntl 2 ) r ds(on) } (i lo,max q switch i g v in f sw ) (3 q oss 2 v in f sw ) (v in q rr f sw ) (19) { 2.53 2 a rms 8.0 m } (29.6 a 27 nc 1.5 a 12 v 200 khz) (3 12 nc 2 12 v 200 khz) (12 v 43 nc 200 khz) 0.051 w 1.28 w 0.043 w 0.10 w 1.48 w per fet the rms value of the current in the synchronous mosfet is calculated from equation 27 and the previously derived values for d, i lo,max , and i lo,min at the converter's maximum output current. (27) i rms,synch [(1 d) (i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 (1 0.097) [(29.6 2 29.6 22.4 22.4 2 ) 3] 1 2 23.5 a rm s (shared by two synchronous mosfets) equation 26 is used to calculate the power dissipation of each synchronous mosfet. note: the rms current is shared by the two lower mosfets so the total rms current is divided by two in the following equation. also, during the nonoverlap time, the per?phase current is shared by two body diodes so the full load current is divided between two phases and two forward body diodes per phase. p d,synch (i rms,synch 2 r ds(on) ) (vf diode i o,max 2 t_nonoverlap f sw ) (26) (23.5 2) 2 a rms 5.0 m 0.92 v (52 a 2 2) 65 ns 200 khz 0.69 w 0.16 w 0.85 w per fet
ncp5331 http://onsemi.com 34 equation 28 is used to calculate the heat sink thermal impedances necessary to maintain less than the specified maximum junction temperatures at 55 c ambient. cntrl sa (120 55 c) 1.48 w 1.65 c w 42.3 c w synch sa (120 55 c) 0.85 w 1.65 c w 74.8 c w per mosfet or 37.4 c w per phase for two mosfets phase if board area permits, a cost effective heatsink could be formed by using a to?263 mounting pad of at least 2.0 in 2 (1282 mm 2 ) for the upper and lower mosfets on a single?sided, 1 oz copper pcb. the total required pad area would be slightly less if the area were divided evenly between top and bottom layers with multiple thermal vias joining the two areas. to conserve board space, aavid offers clip?on heatsinks for to?220 thru?hole packages. examples of these heatsinks include #577002 (1 0.75 0.25 , 33 c/w at 2 w) and #591302 (0.75 0.5 0.5 , 29 c/w at 2 w). 6. adaptive voltage positioning first, to achieve the 200 khz switching frequency, use figure 5 to determine that a 51 k resistor is needed for r osc . then, use figure 6 to find the v fb bias current at the corresponding value of r osc . in this example, the 51 k r osc resistor results in a v fb bias current of approximately 7.0 a. knowing the v fb bias current, one can calculate the required values for r f1 and r drp using equation 29 through equation 31. the no?load position is easily set using equation 29. r vfbk v no?load ibias vfb +25 mv 7.0 a 3.6 k (29) for inductive current sensing, the designer must calculate the inductor's resistance (r l ) and approximate any resistance added by the circuit board (r pcb ). we found the inductor's nominal resistance in section 2 (0.965 m ). in this example, we assume 0.2 m for the circuit board resistance (r pcb ). with this information, equation 30 can be used to calculate the increase at the v drp pin at full load. v drp i o,max (r l r pcb ) g vdrp 52 a (0.965 m 0.2 m ) 4.2 v v 0.254 mv (30) r drp can then be calculated from equation 31. r drp v drp (ibias vfb v core,full?load r f1 ) (31) 254 mv (7.0 a 37 mv 3.6 k ) 14.7 k 7. current sensing choose the current sense network (r sx , c sx , x = 1 or 2) to satisfy r sx c sx lo (r l r pcb ) (32) equation 32 will be most accurate for better iron powder core material (such as the ?8 from micrometals). this material is very consistent with dc current and frequency. less expensive core materials (such as the ?52 from micrometals) change their characteristics with dc current, ac flux density, and frequency. this material will yield acceptable converter performance if the current sense time constant is set lower (longer) than anticipated. as a rule of thumb, start with approximately twice the resistance (r sx ) or twice the capacitance (c sx ) when using the less expensive core material. the component values determined thus far are l o = 828 nh, r l = 0.965 m , and r pcb = 0.2 m . we choose a convenient value for c s1 (0.1 f) and solve for r sx . r sn 828 nh (0.965 m 0.2 m ) 0.1 f 7.10 k after the circuit is constructed, the values of r sx and/or c sx should be tuned to provide a asquare?waveo at the v drp pin with minimal overshoot and fast rise time due to a step change in load current as shown in figure 35, figure 36 and figure 37. this testing has shown that for a 3 to 25 a transient, a value of 10.0 k will produce the desired square wave at v drp. 8. error amplifier tuning the error amplifier is tuned by adjusting c a1 to provide an acceptable full?load transient response as shown in figure 38, figure 39 and figure 40. after a value for c a1 is chosen, the peak?to?peak voltage ripple on the comp pin is examined under full?load to insure less than 20 mvpp as shown in figure 41. 9. current limit setting the maximum inductor resistance, the maximum pcb resistance, and the maximum current?sense gain determine the current limit as shown in equation 34. the maximum current, i out,limit , was specified in the design requirements. the maximum inductor resistance occurs at full load and the highest ambient temperature. this value was found in the aoutput inductor sectiono (1.28 m ). this analysis assumes the pcb resistance only increases due to the change in ambient temperature. component heating will also increase the pcb temperature but quantifying this effect is difficult. lab testing should be used to afine tuneo the overcurrent threshold. r pcb,max 0.2 m {1 0.39% c (100 c 25 c)} 0.26 m
ncp5331 http://onsemi.com 35 v ilim (i out,lim i lo 2) (r lmax r pcb,max ) g ilim (72 a 7.20 a 2) (1.28 m 0.26 m ) 12 v v 1.4 vdc set the voltage at the i lim pin using a resistor divider from the 5.0 v reference output as shown in figure 42. if the resistor from i lim to gnd is chosen to be 910 (r lim2 ), then the resistor from i lim to 5.0 v ref can be calculated from r lim1 (v ref v ilim ) (v ilim r lim2 ) (5.0 v 1.4 v) (1.4 v 910 ) 2340 or 2.37 k 10. overcurrent timer to set the overcurrent timer, solve equation 35 for c ovc and substitute t ovc = 120 ms. c ovc t ovc (5.5 10 5 ) (35) 120 ms (5.5 10 5 ) 0.218 for 0.22 f 11. soft start time to set the soft start time, first calculate the external ramp size at a duty?cycle of d = 1.225 v/12 v = 0.102. ext_ramp d (v in v out ) (r sx c sx f sw ) 0.102 (12 v 1.225 v) (10.0 k 0.1 f 200 khz) 5.5 mv r lim2 910 r lim1 5 v ref to i lim pin v lim figure 42. setting the current limit then calculate the steady?state comp voltage. v comp v out @0a channel_startup_offset int_ramp g csa ext_ramp 2 1.225 v 0.60 v 0.102 250 mv 4.0 v v 5.3 mv 2 1.86 v finally, solve equation 35 for the soft?start capacitor, c c2 , and substitute as required. c c2 (t ss i comp ) (v comp r c1 i comp ) (36) (6 ms 30 a) (1.86 v 7.5 k 30 a) 0.11 for 0.1 f 12. power good delay time first, use the previously derived value for r osc to calculate the current that will be supplied to the c pgd capacitor. i pgd 0.52 v r osc 0.52 v 51 k 10.2 a next, solve equation 37 for c pgd and substitute as required. c pgd t pgd i pgd (pgd thresh pgd min ) (37) 6ms 10.2 a (3.0 v 0.25 v) 0.022 f
ncp5331 http://onsemi.com 36 package dimensions lqfp?32 ft suffix case 873a?02 issue b detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ?t? ?z? ?u? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp5331/d v 2 is a trademark of switch power, inc. amd athlon is a trademark of advanced micro devices, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

▲Up To Search▲

Price & Availability of NCP5331FTR2G

	To Download NCP5331FTR2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .