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STV1602A serial interface transmission decoder december 1992 28 29 30 31 32 33 34 35 18 17 16 15 14 13 12 11 10 27 26 25 24 23 22 21 20 19 36 123456789 37 d0 d1 d2 d3 d4 d5 d6 d8 d7 qfs cx gnd mon ads dix diy dpr fv eso sy gnd sx qsw tn1 d9 v ee v ee gnd aix aiy rse evr syn pck gnd v ee esi 1601a-01.eps pin connections pga37 (ceramic package) order code : STV1602A built-in automatic equalizer for up to 30db attenuation at 135mhz (typically 300m of high-grade coaxial cable), pll circuit for reclocking, and serial-par- allel conversion circuit. this serial transmission decoder re- quires only few external components. other related ics include : . stv1601a, a serial transmission en- coder (parallel-to-serial conver- sion) . stv1389aq coaxial cable driver structure . hybrid ic applications serial data transmission decoder . 100 to 270 mb/s applications examples . serial data transmission of digital television signals 525-625 lines . 4:2:2 component 270mb/s (10-bit) . 4*fsc pal composite 177mb/s (10-bit) . 4*fsc ntsc composite 143mb/s (10-bit) functions . cable equalizer (maximum gain : 30db at 135mhz) . pll for serial clock generation . reclocked repeater output (active loop through) . descrambler : modulo-2 multiplication by g(x) = (x 9 + x 4 + 1) (x + 1) . parallel-to-serial conversion . sync monitor output . eye pattern monitoring . input signal detector description the STV1602A is a hybrid ic decoder which con- verts serial data coming from a serial transmission line into parallel data. 1/22
pin description pin n o symbol equivalent circuit description i/o standard min. typ. max. unit 3sy reclocked serial data output in differential mode. sx and sy are disabled when tn1 is set high. in this case, sx is set high and sy is set low h l o -1.6 -2.4 v v 4sx 5 qsw (gnd) to be connected to gnd i 36 fv adjustment of vco free running frequency : v ee level gives the lowest frequency. to adjust it, set tn1 high. i 1 eso output of phase comparator : must be connected to esi with the shortest distance o -3.2 v 1602a-01.tbl gnd ee v v r3 30 w 30 w 2k w 2k w 3 4 145 w 1602a-02.eps gnd ee v 1 2k w 1k w 1k w 2k w 1602a-04.eps gnd ee v 36 5 1k w 10k w 10k w 1602a-03.eps STV1602A 2/22
pin description (continued) pin n o symbol equivalent circuit description i/o standard min. typ. max. unit 9 to 18 d9 to d0 parallel data output h l o -0.8 -1.6 v v 19 pck parallel clock output (rising edge at data center) h l o -0.8 -1.6 v v 21 evr data output reference potential o-1.2 v 26 aix equalizer differential input i -2.0 v 25 aiy 28 nc to be left open i -4.6 v 29 cx equalizer detector output; input signal : absent present o -2.4 -2.0 v v 1602a-02.tbl gnd ee v 21 9 18 600 w 600 w 300 w 210 w 210 w v r3 1602a-05.eps gnd ee v 10k w 10k w 26 300 w 3k w 4k w 4k w 25 1602a-06.eps gnd ee v 29 28 16k w 2k w 2k w 1k w 2k w 1602a-07.eps STV1602A 3/22
pin description (continued) pin n o symbol equivalent circuit description i/o standard min. typ. max. unit 31 mon equalizer monitor output. connect 75 w resistor between mon-gnd. observe using a 50 w input oscilloscope at the 75 w coaxial cable. o 15 mv (pp) 32 ads serial data input selection high : digital input dix/diy low : equalizer input aix/aiy h l i -0.5 -5 v v 33 dix serial data digital differential input i 34 diy selected when ads is high. h l -1.0 -1.6 v v 1602a-03.tbl gnd ee v 31 v r3 500 w 1k w 500 w 500 w 1602a-08.eps gnd ee v v r3 v r2 ? 32 2k w 2k w 2k w 1602a-09.eps ee v v r3 33 34 v r1 gnd 500 w 500 w 500 w 1602a-10.eps STV1602A 4/22
pin description (continued) pin n o symbol equivalent circuit description i/o standard min. typ. max. unit 37 esi pll error signal input : must be connected to eso with the shortest distance i -3.2 v 6tn1 serial data input activation high : input disabled (vco free running condition). low : input enabled. during switch-on phase, by temporarily hold high for quick start-up i -1.0 -4.0 v v 20 syn state changes at each trs sync word 3ffh 000h 000h h l o -1.0 -4.0 v v 1602a-04.tbl ee v gnd 37 2k w 1602a-11.eps ee v gnd 6 4k w 12k w 2k w 20k w 1602a-12.eps v cc gnd 2k w 4k w 2k w ee v 20 1602a-13.eps STV1602A 5/22
pin description (continued) pin n o symbol equivalent circuit description i/o standard min. typ. max. unit 35 dpr serial data detection output. when there is an input signal at the input side selected through ads, this pin goes high. at no signal, it goes low. h l i.e. - present : high - absent : low o -1.0 -4.0 v v 22 rse selects vco frequency range h : high range 140 to 270mhz l : low range 100 to 145mhz h l i -0.4 -4.0 v v 7 23 v ee -5v supply i/o buffer, pll equalizer -5.2 -5.0 -4.8 v 8v ee -5v supply logic part -5.2 -5.0 -4.8 v 2 24 27 30 gnd gnd 1602a-05.tbl ee v gnd 6k w 1k w 1k w 35 1602a-14.eps ee v gnd 22 10k w 2k w 10k w 10k w 1602a-15.eps STV1602A 6/22
18 17 16 15 14 13 12 11 10 9 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 30-bit shift register 10-bit latch timing generator data detector nrzi to nrz edge detector vco phase detector 8 4 3 22 7 23 sync detector 21 20 19 evr syn pck ecl out reference voltage 33 34 37 1 36 35 32 6 automatic cable equalizer 26 25 28 29 31 2 24 27 30 gnd gnd gnd gnd aix aiy qfs cx mon dix diy ads tn1 dpr fv eso esi rse sy sx v ee v ee v ee serial clock parallel clock reclocked serial data x + x + 1 descrambler 94 input select data relay 1602a-16.eps block diagram absolute maximum ratings (t a = 25 o c) symbol parameter value unit v ee supply voltage -6 v v in input voltage v ee to 0 v i out output current -30 ma t oper operating temperature 0 to 65 o c t stg storage temperature -50 to 125 o c p d allowable power dissipation 2.0 w 1602a-06.tbl recommended operating conditions symbol parameter value unit v ee supply voltage -4.8 to -5.2 v t oper operating temperature 0 to 65 o c 1602a-07.tbl STV1602A 7/22
electrical characteristics (v ee = -5v, t a = 25 o c unless otherwise specified) symbol parameter test conditions test circuit min. typ. max. unit dc characteristics i ee supply current v ee = 5v figure 4 185 ma v ih input voltage pin ads -0.4 v v il -1.5 v v ih pin rse figure 10 -0.4 v v il -4.0 v v ih pin dix, diy -1.0 v v il -1.6 v i ih input current pin dix, diy figure 5 5.0 m a i il -1.0 +1.0 m a v ih input voltage pin tn1 figure 9 -1.0 v v il -4.6 v v oh output voltage pin pcx, dn r p = 1k w -0.8 v v ol -1.6 v v m pin evr, r p = 1k w -1.2 v v oh pin dpr, syn i oh = -10 m a, i ol = +10 m a figure 7 -1.0 v v ol figure 8 -4.0 v v oh pin sx, sy r p = 220 w -1.6 v v ol -2.4 v ac characteristics f max1 vco max. oscillation frequency 1 rse = "h" figure 6 30.0 mhz f min1 vco min. oscillation frequency 1 rse = "h" 14.0 mhz f max2 vco max. oscillation frequency 2 rse = "l" 15.0 mhz f min2 vco min. oscillation frequency 2 rse = "l" 10.0 mhz f hp1 pll pull in range f signal = 270mhz rse = "h" figure 3 27.7 mhz f lp1 25.5 mhz f hp2 f signal = 177mhz rse = "h" 18.5 mhz f lp2 16.8 mhz f hp3 f signal = 143mhz rse = "h" 15.0 mhz f lp3 13.3 mhz f op1 pll generator frequency rse = "h" 14.0 27.0 mhz f op2 rse = "l" 10.0 14.5 mhz frequency at 1/10 the value of signal frequency (tested through pin pck) 1602a-08.tbl switching characteristics (v ee = -5v, t a = 25 o c unless otherwise specified) symbol parameter test conditions test circuit min. typ. max. unit t r rise time pins pck, dn r p = 1k w figure 3 0.8 nsec t f fall time 1.4 nsec t r rise time pins sx, sy r p = 220 w 0.7 nsec t f fall time 0.7 nsec t d delay time pins pck, dn -3 +3 nsec 1602a-09.tbl STV1602A 8/22
equalizer (v ee = -5v, t a = 25 o c unless otherwise specified) symbol parameter test conditions test circuit min. typ. max. unit v max equalizer max. input voltage pins aix, aiy figure 3 0.88 vp-p g max equalizer max. gain 30 db c in input capacity pins aix, freq = 100mhz pf r in input resistance pins aix, freq = 100mhz w 1602a-10.tbl 1602a-17.eps / 1602a-18.eps figure 1 : t r , t f , t c , t d definition 80% 20% tt rf 50% t c t d t w c t /2 c t /2 dn pck 21 19 18 9 evr pck d0 d9 1k w 1k w 1k w 1k w v ee STV1602A 0.1 m f 220 w 220 w 220 w 8 v ee (-5v) ecl line drivers or ecl/ttl translators power save sw 1602a-19.eps figure 2 : a suggested parallel clock / data output circuit syn pin guaranteed operation range. sync pin and serial to parallel conversion operate normally within the frequency and ambient tem- perature ranges according to the following consid- erations. reclocked output. STV1602A may be used as a repeater. the re- clocked output, providing characteristics almost identical to the serial output of stv1601a is avail- able from sx (pin 4) and sy (pin 3). when the reclocked output is used, it is recom- mended not to use simultaneously use the parallel outputs (data and clock) in order to avoid poss ible logic errors caused by an excessively high tem- perature which may result from additional power dissipation created by the reclocked output circuit under certain environnmental conditions. if, for the sake of a design convenience, both reclocked and parallel outputs are to be used, the ambient temperature has to be kept as low as possible or, at least, the airflow around STV1602A must be carefully considered. in addition, it is rec- ommended to put 220 w resistors on all parallel outputs including the clock as shown in figure 2. this reduces the magnitude of the spike current resulting from the parallel output circuit inside the chip and helps reduce the probability of logic errors at high temperature. power saving in repeater mode since the parallell output is not always required for a reclocked repeater, the chip has been designed such that the uncessary parallel logic circuit can be disabled by disconnecting pin 8, one of v ee s, from the power supply. with this arrangement the power dissipation is reducible to about 45 percent of that of the fully functional mode. in practice, a test switch should be provided so that some parallel signals may be available during ad- justment procedures as shown in figure 2. STV1602A 9/22
hp8180a signal genera tor 30 31 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 d0y d0x d1y d1x d2y d2x d3y d3x d4y d4x d5y d5x d6y d6x d7y d7x d8y d8x d9y d9x pcx pcy 2 532 29 27 26 gnd v cc v ee 0.1 10/ 16v 37 33 28 n.c. 35 -5v -5v -5v sw1 sw2 a b 10 m f/10v 22k w a b high range low range vco range select on : af frequency adjust 150pf 0.22 m h 34 trp tn1 -5v 36 pck 1k w frequency monitor 1 lst 3 4 220 w 220 w -5v 0.1 220 w sx sy 0.1 vco frequency adjust 10k w v r1 0.1 220 w -5v 220 w 0.1 0.1 0.1 -5v 0.1 0.1 220 w 150 w 150 w 75 w 75 w 1 2 serial out ee v -5v stv1389aq pll lock detector 33 34 dix diy 220 w 0.1 -5v 220 w 220 w 25 26 28 aiy aix qfs 73 w 41pf 41pf mon 31 100 w a b serial in cx 29 ads 32 sw2 -5v 10k w sy sx 4 3 2 gnd v ee 0.1 0.1 10/16v 24 27 30 23 87 -5v a b input select cable input digital input -5v vco frequency adjust 10k w fv 36 v r2 eso esi rse 22 1 37 dpr 35 -5v 0.1 20 syn evr pck d0 d1 21 19 18 17 -5v 0.1 1k w x 4 trs detector signal freqency monitor d2 d3 d4 d5 d6 d7 d8 d9 16 15 14 13 12 11 10 9 1k w x 8 22k w tn1 100k w qsw 6 5 sw3 10 m f -5v 0.1 led 330 w on : af frequency adjust hp8182a signal analyzer fv rse r v - .3v vco range select vco range select 33 34 dix diy 220 w 0.1 -5v 220 w 220 w ads 32 2 gnd v ee 0.1 0.1 10/16v 24 27 30 23 8 7 -5v STV1602A -5v vco frequency adjust 10k w fv 36 v r2 eso esi rse 22 137 dpr 35 -5v 0.1 20 syn pck 19 trs detector signal freqency monitor 22k w tn1 100k w qsw 6 5 sw3 10 m f -5v 0.1 led 330 w on : af frequency adjust 1k w d.u.t. STV1602A stv1601a 10 m f 1602a-20.eps figure 3 : test circuit diagram example STV1602A 10/22
2 a fv rse gnd ee v 10k w -5v -5v sw1 on position 0.1 m f 220 w 1k w 10/16v 0.1 ee i ee v -5v 24 27 30 8 7 23 STV1602A 22 ads 32 36 10 m f sw1 -5v 10k w 5 qsw 37 1 esi eso 1k w 1k w 1k w evr pcx d0 d9 21 19 18 9 tn1 6 0.1 1602a-21.eps figure 4 2 fv rse gnd ee v 10k w -5v 10/16v 0.1 24 27 30 8 7 23 STV1602A 22 ads 32 36 5 qsw 37 1 esi eso tn1 6 0.1 -5v dix diy 33 34 11 12 v 1 v 2 v 1 v 2 a1 a2 -0.8v -1.6v -1.6v -0.8v i il i il i ih i ih 1602a-22.eps figure 5 STV1602A 11/22
2 fv rse gnd ee v 10k w -5v -5v sw1 position 0.1 m f 1k w 10/16v 0.1 24 27 30 8 7 23 STV1602A 22 ads 32 36 10 m f -5v 10k w 5 qsw 37 1 esi eso 1k w 1k w 1k w evr pcx d0 d9 21 19 18 9 tn1 6 0.1 -5v frequency monitor 22k w sw2 a a b sw1 b on on sw2 vco range high low 1602a-23.eps figure 6 2 fv rse gnd ee v 10k w -5v 10/16v 0.1 24 27 30 8 7 23 STV1602A 22 ads 32 36 5 qsw 37 1 esi eso tn1 6 0.1 -5v dix diy 33 34 vi 29 cx 10 m f 41pf 41pf 73 w dpr 35 v i il l v oh v ol serial in input open 270mb/s signal -10 m a 10 m a serial in 1602a-24.eps figure 7 STV1602A 12/22
2 fv gnd ee v 10k w -5v 10/16v 0.1 24 27 30 8 7 23 STV1602A ads 32 36 5 qsw 37 1 esi eso 6 0.1 -5v dix diy 33 34 tn1 -5v 22k w sw3 10 m f/16v 20 syn 22 rse -5v 10k w vi l vi l v oh v ol -10 m a 10 m a one - shot trs generator 1602a-25.eps figure 8 2 fv rse gnd ee v 10k w -5v 10/16v 0.1 24 27 30 8 7 23 STV1602A 22 ads 32 36 5 qsw 37 1 esi eso 0.1 -5v diy 34 v d0 18 dix 33 tn1 6 -5v 10k w v 1 1602a-26.eps figure 9 STV1602A 13/22
2 fv gnd ee v 10k w -5v 10/16v 0.1 24 27 30 8 7 23 STV1602A 22 ads 32 36 5 qsw 37 1 esi eso 6 0.1 -5v dix diy 33 34 tn1 -5v 22k w sw3 10 m f/16v 19 pcx rse -5v v 1 frequency monitor 0.1 1k w -5v 1602a-27.eps figure 10 31 29 30 26 25 75 w 100 w 47pf 10 m f 47pf monitor out serial in mon gnd cx aix aiy STV1602A 1602a-28.eps figure 11 : equalizer capacitor coupling input circuit STV1602A general as shown in the overall block diagram on page 7, STV1602A is composed of the following functions : (1) analog input as a primary input with automatic equalizer to meet the loss characteristics of coaxial cable (2) digital input as a secondary input to receive the encoded signal from short distances within the same printed circuit board or the same equipment (3) phase locked loop (pll) variable oscillator (4) reclocked serial output (5) serial descrambler (6) sync detector (7) deserializer (8) parallel output buffer amplifiers (9) three diagnostic signals : eye monitor, sync monitor and input data presence monitor a brief explanation of each function is given in the following sections. 1. cable equalizer transmission of high speed digital data by means of coaxial cable can greatly attenuate high fre- quency components. according to the cable length, received signals can widely differ from those sent; in such conditions, clock extraction and data iden- tification could be difficult. the cable equalizer overcomes this problem. the ic performs up to 30db (typical) equalization at 135mhz, typically 300m of high-grade coaxial cable. the equalization is automatically performed according to the coaxial cable length. the input signal can be delivered either through a transformer or through a capacitor. when the digital input is selected, the equalizer is disabled. typical characteristics of the equalization are given in figure 31. STV1602A 14/22
26 25 75 w serial in aix aiy STV1602A 1602a-29.eps figure 12 : equalizer transformer input circuit STV1602A mon gnd 35 30 50 w coaxial cable to 50 w input oscilloscope 75 w 1602a-31.eps figure 14 : equalized waveforms monitoring STV1602A 29 cx 10 m f/16v 2.2k w 1602a-32.eps figure 15 : agc time constant coaxial cable 75 47pf 47pf aiy pin 25 aix pin 26 terminator 1mm printed circuit inductance r = 6mm ( through-hole to a ground plane) 1602a-30.eps figure 13 : an example of technique to improve the return-loss figure for the capaci- tor coupling input case in both input circuit configurations, a consideration is required in a practical design to obtain a sufficient return-loss (at least 15db over a frequency range of 5mhz to the bit rate frequency used). to achieve this, it is effective to add a small inductance in series with the 75 w termination resistor. figure 13 shows an implementation example. mon pin (31) equalized signals can be observed at this pin by connecting an oscilloscope input (50 w ). cx pin (29) equalizer agc time constant connect a 10 m f capacitor in serial with 2.2k w resistor between this pin and gnd in order to obtain stable operation at all times. according to input signals, voltage changes from -2v to -2.4v can occur. 2. digital input the serial data input can be used without the equalizer. dix (pin 33) and diy (pin 34) are differential inputs for ecl signals. from these pins, input signals are differentially amplified, therefore with no input signals, the data detection signals could go high and erroneous data would be transferred to the parallel output. to avoid this, a voltage level conforming to ecl specifications must be applied between dix and diy pins. also, while the analog input is in use, digital input must be kept "quiet" in order to avoid possible errors caused by cross-talk. this cross-talk prob- lem naturally gets most severe when the analog input cable length is close to the limit of the trans- mission capability. 3. serial input selection selection of the serial input is performed by ads (pin 32); when high the digital input is enabled; this input can be used for very short transmission lines. when low, the equalizer input is enabled; this input must be used for long transmission lines. 4. pll in order to extract clock signals from the equalized serial data, it is processed to generate edge signals which are sent to the phase comparator. when the pll is locked, the identifier clock (d - flipflop) will be in phase with the incoming clock. the identifier clock rises at the center of the data period for easy identification. the pll detailed block diagram is shown in fig- ure 16. esi is the vco control input (pin 37). normally, the phase comparator output eso (pin 1) is connected to esi. since the vco employed has a very high sensitiv- ity, those two nodes must be connected with a shortest distance and a minimum area of conductor STV1602A 15/22
descrambler nzri to nrz conversion dc sx sy phase comparator vco rse dl dl dix din ads tn1 eso esi fv f a b c d e from equalizer 1602a-33.eps figure 16 : serial data input and pll on the printed circuit board. encircling those two nodes by a ground guarding is an efficient method to prevent errors caused by an "antenna effect". through fv (pin 35) one can adjust the free run- ning frequency; when the fv voltage is equal to v ee , the free running frequency is the lowest; the voltage adjustment can be performed by using a variable resistor connected between fv and vee. rse (pin 22) selects the vco frequency range; high : 140 to 270mhz, low : 100 to 145mhz. when tn1 (pin 6) is set high, input signals are disabled and the vco free runs. the capacitor connected between tn1 and gnd avoids mislock- ing problem when the power supply is switched on. data detection serial data edges are detected and go through low pass filter. the processed signal is available at dpr (pin 35).dpr goes high when an input signal is detected, otherwise it stays low. the driving capability of this pin is weak. it is recommended to load it with a high impedance cmos or equivalent. 5. nrzi to nrz conversion, descrambler serial data delivered by the identifier is available in differential mode, sx (pin 4) and sy (pin 3). at the same time, to recover the or iginal data, nrzi to nrz conversion and descrambling are performed. pll d data (nrzi) clock serial signal data (nrz) 1602a-34.eps figure 17 : nrzi to nrz conversion d1 d2 d3 d4 d5 d6 d7 d8 d9 out in 1602a-35.eps figure 18 : x 9 + x 4 + 1 descrambler d1 d2 d3 d4 d5 d6 d7 d8 d9 out in d10 1602a-36.eps figure 19 : actual x 9 + x 4 + 1 descrambler 6. serial to parallel conversion after descrambling, serial data is s ent to a 30-bit register to detect the sync word (trs). when the sequen ce 111111111 100000000000000000000 is detected, sync word detection signal is output, the counter which divides the clock frequency by 10 is initialized and data is converted to parallel (10-bit word) to be output. STV1602A 16/22
e a v s a v e a v s a v e a v s a v e a v h- blk active video h- blk active video h- blk active video 1 tv line 4:2:2 data stream syn output (case a) syn output (case b) syn output (case c) 1602a-37.eps figure 20 : sync output in 4:2:2 case (not to scale) 1 tv line t r s syn output active video + h- blk t r s t r s active video + h- blk active video + h- blk 4 fsc datastream 1602a-38.eps figure 21 : sync output in 4 fsc case (not to scale) each time the sync word is detected, syn (pin 20) changes state as shown in figure 20. when a receiver using STV1602A is properly im- plemented and adjusted, the health of the imple- mentation can be checked simply by looking at syn (pin 20) output while an encoded signal is present at the input. syn is an output of a flip-flop which toggles at each detection of trs at the sync detector. since the 4:2:2 signal contains two kinds of trss, sav and eav, when the output of syn is observed by an oscilloscope it looks like either case a or case b as shown in figure 20 depending upon the initial condition of the flip-flop. when bit erros are occurring somewhere in the transmission path, syn output is affected and looks like as shown in case c. figure 21 illustrates the case for 4 fsc (d2 ntsc and pal). differing from the 4:2:2 case, syn output has an equal mark and space ratio due to the periodic occurence (once per one tv line) of the trs detection. however, transmission path bit errors will cause the syn output to appear similar to the 4:2:2 case. if syn signal is used other than for monitoring purposes, buffering similar to that of dpr is re- quired due to the high impedance nature of syn output. 7. phase relation s hip between p arallel data and parallel clock parallel data and clock are output so that the rising edge of the parallel clock is located at the center of the parallel data. both par allel data and clock (nearly identical to that of single ecl) have dc levels depending on the temperature. in order to simplify the driving amplifier, a reference level (evr) is available at pin 21. pcx, dn and evr use pull down resistors ( identical values). a peripheral circuit example is shown in figure 23. figure 24 shows a circuit to disable the parallel clock output. STV1602A 17/22
parallel clock parallel data v oh v ol evr output voltage 1601a-39.eps figure 22 : phase relation of parallel clock, data and evr voltage level 21 19 18 9 evr pck d0 d9 1k w 1k w 1k w 1k w v ee STV1602A 0.1 m f 1602a-40.eps figure 23 : parallel clock data output circuit evr pck 1k w 1k w v ee STV1602A 0.1 m f 21 6 35 dpr 0.1 m f cmos inverter 10k w 10k w 1602a-41.eps figure 24 : a circuit example to disable parallel clock v ee 10k w tn1 pcx fv small signal transistor frequency monitor 10 m f 22k w 1k w STV1602A 63619 1602a-42.eps figure 25 : vco temperature compensation and free running frequency ad- justment 8. vco temperature compensation and oscil- lation frequency adjustment. vco oscillation frequency depends on the tem- perature as shown in figures 29 and 30 "repre- sentative characteristics example". within the normal range of operation, frequency increases with temperature. fv pin voltage remains almost constant regardless of temperature. figure 25 shows an example of a temperature compensation circuit using a diode (transistor with c-b diode short-circuited) and a resistor between fv and v ee . pll pull-in range (signal frequency 270, 177 and 143mhz) are given by figures 32, 33 and 34. 9. vco free running frequency adjustment vco free running frequency adjustment is per- formed at room temperature. if tn1 is set high, vco is free running. wait for 5 to 10 minutes after turning power supply on (warm up time). while monitoring pck (pin 19) output, adjust the signal frequency (within 1%) with the variable resistor connected between fv and v ee . STV1602A 18/22
input data : hex, 10-bit (hex, 8-bit) serial output when the worst sequence on dc component is occuring (case a) (case b) 300 (co) 198 (66) 300 (co) 198 (66) 19 bits 1 bit 1 bit 1602a-43.eps figure 26 input data : hex, 10-bit (hex, 8-bit) serial output when the worst sequence on bit slip is occuring 110 (44) 200 (80) 110 (44) 200 (80) 20 bits 20 bits 1602a-44.eps figure 27 : particular data words for checking pll bit slip using particular codes to check overall perform - ance althrough the scrambling method employed effec- tively randomizes the incoming data and puts out a signal with a nearly uniform spectr um, there still exist some combinations of codes that give some- what unfriendly conditions to the transmission path in terms of low frequency component or of a long run without any transitions. as shown in figure 26, it is known that if the code words 300, 198 (hex, 10-bit) are given alternately to the parallel input of the encoder, the largest amount of dc component (nearly one tv line period) can be produced at some place with a certain probability (such a sequence is, however, destroyed when different data is input to the en- coder). even with such signals, error-free reception is pos- sible with the STV1602A if a proper implementation is made (refer to section 12 for a recommended circuit). another particular combination of words, but with a different nature, is 200, 110 (hex, 10-bit) which can generate the sequence which is most vulnerable* to bit slip of nearly one tv line period. figure 27 illustrates such a situation. similar to the previous case, the worst sequence stops upon an arrival of a data other than the alternating 200, 110 at the input of the encoder. * stricly speaking the longest isolated run is 38 clocks for 4:2:2 and 43 clocks for 4 fsc ntsc and pal. however, the above sequence generally shows the most critical situation for the bit slip problem. note : actually there exists a family of such particular code as above described. they will, however, create an identical sequence in the serial domain since the difference amongst the family is merely which bit is regarded as the start bit of a word. STV1602A 19/22
27 75 w 47pf 47pf 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 1234 5 22k w 37 36 35 34 33 32 31 30 29 28 10k w 10k w (decoder module) STV1602A qfs cx gnd mo n ads (input select) dix diy dpr fv esi d8 d7 d6 d5 d4 d3 d2 d1 d0 pck syn evr gnd aiy aix gnd eso gnd sy sx qsw tn1 d9 v ee v ee v ee test jumper 10 m f/16v -5v 0.1 m f (-1.3v) parallel ck parallel data out (ecl) test point -5v (open) 10 m f/16v -5v serial in digital in q1 1k w serial in (from cable) rse (rate select) 100 w vco center freq. adj. high d1, d2 pal low d2 ntsc 10k w ecl pair tx line eye monitoring 2.2k w -5v 1602a-45.eps figure 28 : application circuit example STV1602A 20/22
representative characteristics example 0.80 0.90 1.00 1.10 1.20 1.30 300 260 220 180 140 fv pin voltage (v) vco oscillation frequency (mhz) rse: "h" 85?c 65?c 45?c 25?c 5?c -15?c 1602a-46.eps figure 29 : vco oscillation frequency versus fv pin voltage 0.90 1.00 1.10 1.20 1.30 fv pin voltage (v) vco oscillation frequency (mhz) 100 110 120 130 140 150 85?c 65?c 45?c 25?c 5?c -15?c rse : "l" 85?c 45?c 1602a-47.eps figure 30 : vco oscillation frequency versus fv pin voltage -155 25456585 ambient temperature (?c) 30 29 28 27 26 25 24 23 frequency (mhz) high pull in low pull in free run 1602a-49.eps figure 32 : pull-in range and free run fre- quency (270mb/s) 1602a-48.eps frequency (mhz) gain (db) 5 10 15 20 100 200 0 figure 31 : an example of equalizer charac- teristics using 5c - 2v coaxial cable with respect to the gain for 0.5meter -155 25456585 ambient temperature (?c) 18 17 16 15 14 13 12 11 frequency (mhz) high pull in free run low pull in 1602a-52.eps figure 34 : pull-in range and free run fre- quency (143mb/s) -155 25456585 ambient temperature (?c) 21 20 19 18 17 16 15 14 frequency (mhz) free run high pull in low pull in 1602a-51.eps figure 33 : pull-in range and free run fre- quency (177mb/s) STV1602A 21/22
bottom view 25.4 0.5 0.46 0.05 1.2 0.1 25.4 0.5 3.8 1.15 0.15 4.2 seating plane 0.2 2.54 x 9 = 22.86 0.25 pin 28 pin 19 pin 36 pin 10 pin 1 pin 37 2.54 2.54 2.032 max. 2.54 x 9 = 22.86 0.25 dimensions in mm pm-pga37.eps package mechanical data 37 pins - ceramic pga information furnished is believed to be accurate and rel iable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - it aly - ja pan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV1602A 22/22

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